src/amd/compiler/aco_instruction_selection.cpp

   1 /*
   2  * Copyright © 2018 Valve Corporation
   3  * Copyright © 2018 Google
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <algorithm>
  27 #include <array>
  28 #include <stack>
  29 #include <map>
  30
  31 #include "ac_shader_util.h"
  32 #include "aco_ir.h"
  33 #include "aco_builder.h"
  34 #include "aco_interface.h"
  35 #include "aco_instruction_selection_setup.cpp"
  36 #include "util/fast_idiv_by_const.h"
  37
  38 namespace aco {
  39 namespace {
  40
  41 class loop_info_RAII {
  42    isel_context* ctx;
  43    unsigned header_idx_old;
  44    Block* exit_old;
  45    bool divergent_cont_old;
  46    bool divergent_branch_old;
  47    bool divergent_if_old;
  48
  49 public:
  50    loop_info_RAII(isel_context* ctx, unsigned loop_header_idx, Block* loop_exit)
  51       : ctx(ctx),
  52         header_idx_old(ctx->cf_info.parent_loop.header_idx), exit_old(ctx->cf_info.parent_loop.exit),
  53         divergent_cont_old(ctx->cf_info.parent_loop.has_divergent_continue),
  54         divergent_branch_old(ctx->cf_info.parent_loop.has_divergent_branch),
  55         divergent_if_old(ctx->cf_info.parent_if.is_divergent)
  56    {
  57       ctx->cf_info.parent_loop.header_idx = loop_header_idx;
  58       ctx->cf_info.parent_loop.exit = loop_exit;
  59       ctx->cf_info.parent_loop.has_divergent_continue = false;
  60       ctx->cf_info.parent_loop.has_divergent_branch = false;
  61       ctx->cf_info.parent_if.is_divergent = false;
  62       ctx->cf_info.loop_nest_depth = ctx->cf_info.loop_nest_depth + 1;
  63    }
  64
  65    ~loop_info_RAII()
  66    {
  67       ctx->cf_info.parent_loop.header_idx = header_idx_old;
  68       ctx->cf_info.parent_loop.exit = exit_old;
  69       ctx->cf_info.parent_loop.has_divergent_continue = divergent_cont_old;
  70       ctx->cf_info.parent_loop.has_divergent_branch = divergent_branch_old;
  71       ctx->cf_info.parent_if.is_divergent = divergent_if_old;
  72       ctx->cf_info.loop_nest_depth = ctx->cf_info.loop_nest_depth - 1;
  73       if (!ctx->cf_info.loop_nest_depth && !ctx->cf_info.parent_if.is_divergent)
  74          ctx->cf_info.exec_potentially_empty_discard = false;
  75    }
  76 };
  77
  78 struct if_context {
  79    Temp cond;
  80
  81    bool divergent_old;
  82    bool exec_potentially_empty_discard_old;
  83    bool exec_potentially_empty_break_old;
  84    uint16_t exec_potentially_empty_break_depth_old;
  85
  86    unsigned BB_if_idx;
  87    unsigned invert_idx;
  88    bool then_branch_divergent;
  89    Block BB_invert;
  90    Block BB_endif;
  91 };
  92
  93 static bool visit_cf_list(struct isel_context *ctx,
  94                           struct exec_list *list);
  95
  96 static void add_logical_edge(unsigned pred_idx, Block *succ)
  97 {
  98    succ->logical_preds.emplace_back(pred_idx);
  99 }
 100
 101
 102 static void add_linear_edge(unsigned pred_idx, Block *succ)
 103 {
 104    succ->linear_preds.emplace_back(pred_idx);
 105 }
 106
 107 static void add_edge(unsigned pred_idx, Block *succ)
 108 {
 109    add_logical_edge(pred_idx, succ);
 110    add_linear_edge(pred_idx, succ);
 111 }
 112
 113 static void append_logical_start(Block *b)
 114 {
 115    Builder(NULL, b).pseudo(aco_opcode::p_logical_start);
 116 }
 117
 118 static void append_logical_end(Block *b)
 119 {
 120    Builder(NULL, b).pseudo(aco_opcode::p_logical_end);
 121 }
 122
 123 Temp get_ssa_temp(struct isel_context *ctx, nir_ssa_def *def)
 124 {
 125    assert(ctx->allocated[def->index].id());
 126    return ctx->allocated[def->index];
 127 }
 128
 129 Temp emit_mbcnt(isel_context *ctx, Definition dst,
 130                 Operand mask_lo = Operand((uint32_t) -1), Operand mask_hi = Operand((uint32_t) -1))
 131 {
 132    Builder bld(ctx->program, ctx->block);
 133    Definition lo_def = ctx->program->wave_size == 32 ? dst : bld.def(v1);
 134    Temp thread_id_lo = bld.vop3(aco_opcode::v_mbcnt_lo_u32_b32, lo_def, mask_lo, Operand(0u));
 135
 136    if (ctx->program->wave_size == 32) {
 137       return thread_id_lo;
 138    } else {
 139       Temp thread_id_hi = bld.vop3(aco_opcode::v_mbcnt_hi_u32_b32, dst, mask_hi, thread_id_lo);
 140       return thread_id_hi;
 141    }
 142 }
 143
 144 Temp emit_wqm(isel_context *ctx, Temp src, Temp dst=Temp(0, s1), bool program_needs_wqm = false)
 145 {
 146    Builder bld(ctx->program, ctx->block);
 147
 148    if (!dst.id())
 149       dst = bld.tmp(src.regClass());
 150
 151    assert(src.size() == dst.size());
 152
 153    if (ctx->stage != fragment_fs) {
 154       if (!dst.id())
 155          return src;
 156
 157       bld.copy(Definition(dst), src);
 158       return dst;
 159    }
 160
 161    bld.pseudo(aco_opcode::p_wqm, Definition(dst), src);
 162    ctx->program->needs_wqm |= program_needs_wqm;
 163    return dst;
 164 }
 165
 166 static Temp emit_bpermute(isel_context *ctx, Builder &bld, Temp index, Temp data)
 167 {
 168    if (index.regClass() == s1)
 169       return bld.readlane(bld.def(s1), data, index);
 170
 171    Temp index_x4 = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), index);
 172
 173    /* Currently not implemented on GFX6-7 */
 174    assert(ctx->options->chip_class >= GFX8);
 175
 176    if (ctx->options->chip_class <= GFX9 || ctx->program->wave_size == 32) {
 177       return bld.ds(aco_opcode::ds_bpermute_b32, bld.def(v1), index_x4, data);
 178    }
 179
 180    /* GFX10, wave64 mode:
 181     * The bpermute instruction is limited to half-wave operation, which means that it can't
 182     * properly support subgroup shuffle like older generations (or wave32 mode), so we
 183     * emulate it here.
 184     */
 185    if (!ctx->has_gfx10_wave64_bpermute) {
 186       ctx->has_gfx10_wave64_bpermute = true;
 187       ctx->program->config->num_shared_vgprs = 8; /* Shared VGPRs are allocated in groups of 8 */
 188       ctx->program->vgpr_limit -= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
 189    }
 190
 191    Temp lane_id = emit_mbcnt(ctx, bld.def(v1));
 192    Temp lane_is_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x20u), lane_id);
 193    Temp index_is_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x20u), index);
 194    Temp cmp = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm, vcc), lane_is_hi, index_is_hi);
 195
 196    return bld.reduction(aco_opcode::p_wave64_bpermute, bld.def(v1), bld.def(s2), bld.def(s1, scc),
 197                         bld.vcc(cmp), Operand(v2.as_linear()), index_x4, data, gfx10_wave64_bpermute);
 198 }
 199
 200 Temp as_vgpr(isel_context *ctx, Temp val)
 201 {
 202    if (val.type() == RegType::sgpr) {
 203       Builder bld(ctx->program, ctx->block);
 204       return bld.copy(bld.def(RegType::vgpr, val.size()), val);
 205    }
 206    assert(val.type() == RegType::vgpr);
 207    return val;
 208 }
 209
 210 //assumes a != 0xffffffff
 211 void emit_v_div_u32(isel_context *ctx, Temp dst, Temp a, uint32_t b)
 212 {
 213    assert(b != 0);
 214    Builder bld(ctx->program, ctx->block);
 215
 216    if (util_is_power_of_two_or_zero(b)) {
 217       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(dst), Operand((uint32_t)util_logbase2(b)), a);
 218       return;
 219    }
 220
 221    util_fast_udiv_info info = util_compute_fast_udiv_info(b, 32, 32);
 222
 223    assert(info.multiplier <= 0xffffffff);
 224
 225    bool pre_shift = info.pre_shift != 0;
 226    bool increment = info.increment != 0;
 227    bool multiply = true;
 228    bool post_shift = info.post_shift != 0;
 229
 230    if (!pre_shift && !increment && !multiply && !post_shift) {
 231       bld.vop1(aco_opcode::v_mov_b32, Definition(dst), a);
 232       return;
 233    }
 234
 235    Temp pre_shift_dst = a;
 236    if (pre_shift) {
 237       pre_shift_dst = (increment || multiply || post_shift) ? bld.tmp(v1) : dst;
 238       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(pre_shift_dst), Operand((uint32_t)info.pre_shift), a);
 239    }
 240
 241    Temp increment_dst = pre_shift_dst;
 242    if (increment) {
 243       increment_dst = (post_shift || multiply) ? bld.tmp(v1) : dst;
 244       bld.vadd32(Definition(increment_dst), Operand((uint32_t) info.increment), pre_shift_dst);
 245    }
 246
 247    Temp multiply_dst = increment_dst;
 248    if (multiply) {
 249       multiply_dst = post_shift ? bld.tmp(v1) : dst;
 250       bld.vop3(aco_opcode::v_mul_hi_u32, Definition(multiply_dst), increment_dst,
 251                bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand((uint32_t)info.multiplier)));
 252    }
 253
 254    if (post_shift) {
 255       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(dst), Operand((uint32_t)info.post_shift), multiply_dst);
 256    }
 257 }
 258
 259 void emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, Temp dst)
 260 {
 261    Builder bld(ctx->program, ctx->block);
 262    bld.pseudo(aco_opcode::p_extract_vector, Definition(dst), src, Operand(idx));
 263 }
 264
 265
 266 Temp emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, RegClass dst_rc)
 267 {
 268    /* no need to extract the whole vector */
 269    if (src.regClass() == dst_rc) {
 270       assert(idx == 0);
 271       return src;
 272    }
 273    assert(src.size() > idx);
 274    Builder bld(ctx->program, ctx->block);
 275    auto it = ctx->allocated_vec.find(src.id());
 276    /* the size check needs to be early because elements other than 0 may be garbage */
 277    if (it != ctx->allocated_vec.end() && it->second[0].size() == dst_rc.size()) {
 278       if (it->second[idx].regClass() == dst_rc) {
 279          return it->second[idx];
 280       } else {
 281          assert(dst_rc.size() == it->second[idx].regClass().size());
 282          assert(dst_rc.type() == RegType::vgpr && it->second[idx].type() == RegType::sgpr);
 283          return bld.copy(bld.def(dst_rc), it->second[idx]);
 284       }
 285    }
 286
 287    if (src.size() == dst_rc.size()) {
 288       assert(idx == 0);
 289       return bld.copy(bld.def(dst_rc), src);
 290    } else {
 291       Temp dst = bld.tmp(dst_rc);
 292       emit_extract_vector(ctx, src, idx, dst);
 293       return dst;
 294    }
 295 }
 296
 297 void emit_split_vector(isel_context* ctx, Temp vec_src, unsigned num_components)
 298 {
 299    if (num_components == 1)
 300       return;
 301    if (ctx->allocated_vec.find(vec_src.id()) != ctx->allocated_vec.end())
 302       return;
 303    aco_ptr<Pseudo_instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector, Format::PSEUDO, 1, num_components)};
 304    split->operands[0] = Operand(vec_src);
 305    std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 306    for (unsigned i = 0; i < num_components; i++) {
 307       elems[i] = {ctx->program->allocateId(), RegClass(vec_src.type(), vec_src.size() / num_components)};
 308       split->definitions[i] = Definition(elems[i]);
 309    }
 310    ctx->block->instructions.emplace_back(std::move(split));
 311    ctx->allocated_vec.emplace(vec_src.id(), elems);
 312 }
 313
 314 /* This vector expansion uses a mask to determine which elements in the new vector
 315  * come from the original vector. The other elements are undefined. */
 316 void expand_vector(isel_context* ctx, Temp vec_src, Temp dst, unsigned num_components, unsigned mask)
 317 {
 318    emit_split_vector(ctx, vec_src, util_bitcount(mask));
 319
 320    if (vec_src == dst)
 321       return;
 322
 323    Builder bld(ctx->program, ctx->block);
 324    if (num_components == 1) {
 325       if (dst.type() == RegType::sgpr)
 326          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec_src);
 327       else
 328          bld.copy(Definition(dst), vec_src);
 329       return;
 330    }
 331
 332    unsigned component_size = dst.size() / num_components;
 333    std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 334
 335    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1)};
 336    vec->definitions[0] = Definition(dst);
 337    unsigned k = 0;
 338    for (unsigned i = 0; i < num_components; i++) {
 339       if (mask & (1 << i)) {
 340          Temp src = emit_extract_vector(ctx, vec_src, k++, RegClass(vec_src.type(), component_size));
 341          if (dst.type() == RegType::sgpr)
 342             src = bld.as_uniform(src);
 343          vec->operands[i] = Operand(src);
 344       } else {
 345          vec->operands[i] = Operand(0u);
 346       }
 347       elems[i] = vec->operands[i].getTemp();
 348    }
 349    ctx->block->instructions.emplace_back(std::move(vec));
 350    ctx->allocated_vec.emplace(dst.id(), elems);
 351 }
 352
 353 Temp bool_to_vector_condition(isel_context *ctx, Temp val, Temp dst = Temp(0, s2))
 354 {
 355    Builder bld(ctx->program, ctx->block);
 356    if (!dst.id())
 357       dst = bld.tmp(bld.lm);
 358
 359    assert(val.regClass() == s1);
 360    assert(dst.regClass() == bld.lm);
 361
 362    return bld.sop2(Builder::s_cselect, Definition(dst), Operand((uint32_t) -1), Operand(0u), bld.scc(val));
 363 }
 364
 365 Temp bool_to_scalar_condition(isel_context *ctx, Temp val, Temp dst = Temp(0, s1))
 366 {
 367    Builder bld(ctx->program, ctx->block);
 368    if (!dst.id())
 369       dst = bld.tmp(s1);
 370
 371    assert(val.regClass() == bld.lm);
 372    assert(dst.regClass() == s1);
 373
 374    /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
 375    Temp tmp = bld.tmp(s1);
 376    bld.sop2(Builder::s_and, bld.def(bld.lm), bld.scc(Definition(tmp)), val, Operand(exec, bld.lm));
 377    return emit_wqm(ctx, tmp, dst);
 378 }
 379
 380 Temp get_alu_src(struct isel_context *ctx, nir_alu_src src, unsigned size=1)
 381 {
 382    if (src.src.ssa->num_components == 1 && src.swizzle[0] == 0 && size == 1)
 383       return get_ssa_temp(ctx, src.src.ssa);
 384
 385    if (src.src.ssa->num_components == size) {
 386       bool identity_swizzle = true;
 387       for (unsigned i = 0; identity_swizzle && i < size; i++) {
 388          if (src.swizzle[i] != i)
 389             identity_swizzle = false;
 390       }
 391       if (identity_swizzle)
 392          return get_ssa_temp(ctx, src.src.ssa);
 393    }
 394
 395    Temp vec = get_ssa_temp(ctx, src.src.ssa);
 396    unsigned elem_size = vec.size() / src.src.ssa->num_components;
 397    assert(elem_size > 0); /* TODO: 8 and 16-bit vectors not supported */
 398    assert(vec.size() % elem_size == 0);
 399
 400    RegClass elem_rc = RegClass(vec.type(), elem_size);
 401    if (size == 1) {
 402       return emit_extract_vector(ctx, vec, src.swizzle[0], elem_rc);
 403    } else {
 404       assert(size <= 4);
 405       std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 406       aco_ptr<Pseudo_instruction> vec_instr{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, size, 1)};
 407       for (unsigned i = 0; i < size; ++i) {
 408          elems[i] = emit_extract_vector(ctx, vec, src.swizzle[i], elem_rc);
 409          vec_instr->operands[i] = Operand{elems[i]};
 410       }
 411       Temp dst{ctx->program->allocateId(), RegClass(vec.type(), elem_size * size)};
 412       vec_instr->definitions[0] = Definition(dst);
 413       ctx->block->instructions.emplace_back(std::move(vec_instr));
 414       ctx->allocated_vec.emplace(dst.id(), elems);
 415       return dst;
 416    }
 417 }
 418
 419 Temp convert_pointer_to_64_bit(isel_context *ctx, Temp ptr)
 420 {
 421    if (ptr.size() == 2)
 422       return ptr;
 423    Builder bld(ctx->program, ctx->block);
 424    if (ptr.type() == RegType::vgpr)
 425       ptr = bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), ptr);
 426    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s2),
 427                      ptr, Operand((unsigned)ctx->options->address32_hi));
 428 }
 429
 430 void emit_sop2_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst, bool writes_scc)
 431 {
 432    aco_ptr<SOP2_instruction> sop2{create_instruction<SOP2_instruction>(op, Format::SOP2, 2, writes_scc ? 2 : 1)};
 433    sop2->operands[0] = Operand(get_alu_src(ctx, instr->src[0]));
 434    sop2->operands[1] = Operand(get_alu_src(ctx, instr->src[1]));
 435    sop2->definitions[0] = Definition(dst);
 436    if (writes_scc)
 437       sop2->definitions[1] = Definition(ctx->program->allocateId(), scc, s1);
 438    ctx->block->instructions.emplace_back(std::move(sop2));
 439 }
 440
 441 void emit_vop2_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst,
 442                            bool commutative, bool swap_srcs=false, bool flush_denorms = false)
 443 {
 444    Builder bld(ctx->program, ctx->block);
 445    Temp src0 = get_alu_src(ctx, instr->src[swap_srcs ? 1 : 0]);
 446    Temp src1 = get_alu_src(ctx, instr->src[swap_srcs ? 0 : 1]);
 447    if (src1.type() == RegType::sgpr) {
 448       if (commutative && src0.type() == RegType::vgpr) {
 449          Temp t = src0;
 450          src0 = src1;
 451          src1 = t;
 452       } else if (src0.type() == RegType::vgpr &&
 453                  op != aco_opcode::v_madmk_f32 &&
 454                  op != aco_opcode::v_madak_f32 &&
 455                  op != aco_opcode::v_madmk_f16 &&
 456                  op != aco_opcode::v_madak_f16) {
 457          /* If the instruction is not commutative, we emit a VOP3A instruction */
 458          bld.vop2_e64(op, Definition(dst), src0, src1);
 459          return;
 460       } else {
 461          src1 = bld.copy(bld.def(RegType::vgpr, src1.size()), src1); //TODO: as_vgpr
 462       }
 463    }
 464
 465    if (flush_denorms && ctx->program->chip_class < GFX9) {
 466       assert(dst.size() == 1);
 467       Temp tmp = bld.vop2(op, bld.def(v1), src0, src1);
 468       bld.vop2(aco_opcode::v_mul_f32, Definition(dst), Operand(0x3f800000u), tmp);
 469    } else {
 470       bld.vop2(op, Definition(dst), src0, src1);
 471    }
 472 }
 473
 474 void emit_vop3a_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst,
 475                             bool flush_denorms = false)
 476 {
 477    Temp src0 = get_alu_src(ctx, instr->src[0]);
 478    Temp src1 = get_alu_src(ctx, instr->src[1]);
 479    Temp src2 = get_alu_src(ctx, instr->src[2]);
 480
 481    /* ensure that the instruction has at most 1 sgpr operand
 482     * The optimizer will inline constants for us */
 483    if (src0.type() == RegType::sgpr && src1.type() == RegType::sgpr)
 484       src0 = as_vgpr(ctx, src0);
 485    if (src1.type() == RegType::sgpr && src2.type() == RegType::sgpr)
 486       src1 = as_vgpr(ctx, src1);
 487    if (src2.type() == RegType::sgpr && src0.type() == RegType::sgpr)
 488       src2 = as_vgpr(ctx, src2);
 489
 490    Builder bld(ctx->program, ctx->block);
 491    if (flush_denorms && ctx->program->chip_class < GFX9) {
 492       assert(dst.size() == 1);
 493       Temp tmp = bld.vop3(op, Definition(dst), src0, src1, src2);
 494       bld.vop2(aco_opcode::v_mul_f32, Definition(dst), Operand(0x3f800000u), tmp);
 495    } else {
 496       bld.vop3(op, Definition(dst), src0, src1, src2);
 497    }
 498 }
 499
 500 void emit_vop1_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 501 {
 502    Builder bld(ctx->program, ctx->block);
 503    bld.vop1(op, Definition(dst), get_alu_src(ctx, instr->src[0]));
 504 }
 505
 506 void emit_vopc_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 507 {
 508    Temp src0 = get_alu_src(ctx, instr->src[0]);
 509    Temp src1 = get_alu_src(ctx, instr->src[1]);
 510    assert(src0.size() == src1.size());
 511
 512    aco_ptr<Instruction> vopc;
 513    if (src1.type() == RegType::sgpr) {
 514       if (src0.type() == RegType::vgpr) {
 515          /* to swap the operands, we might also have to change the opcode */
 516          switch (op) {
 517             case aco_opcode::v_cmp_lt_f32:
 518                op = aco_opcode::v_cmp_gt_f32;
 519                break;
 520             case aco_opcode::v_cmp_ge_f32:
 521                op = aco_opcode::v_cmp_le_f32;
 522                break;
 523             case aco_opcode::v_cmp_lt_i32:
 524                op = aco_opcode::v_cmp_gt_i32;
 525                break;
 526             case aco_opcode::v_cmp_ge_i32:
 527                op = aco_opcode::v_cmp_le_i32;
 528                break;
 529             case aco_opcode::v_cmp_lt_u32:
 530                op = aco_opcode::v_cmp_gt_u32;
 531                break;
 532             case aco_opcode::v_cmp_ge_u32:
 533                op = aco_opcode::v_cmp_le_u32;
 534                break;
 535             case aco_opcode::v_cmp_lt_f64:
 536                op = aco_opcode::v_cmp_gt_f64;
 537                break;
 538             case aco_opcode::v_cmp_ge_f64:
 539                op = aco_opcode::v_cmp_le_f64;
 540                break;
 541             case aco_opcode::v_cmp_lt_i64:
 542                op = aco_opcode::v_cmp_gt_i64;
 543                break;
 544             case aco_opcode::v_cmp_ge_i64:
 545                op = aco_opcode::v_cmp_le_i64;
 546                break;
 547             case aco_opcode::v_cmp_lt_u64:
 548                op = aco_opcode::v_cmp_gt_u64;
 549                break;
 550             case aco_opcode::v_cmp_ge_u64:
 551                op = aco_opcode::v_cmp_le_u64;
 552                break;
 553             default: /* eq and ne are commutative */
 554                break;
 555          }
 556          Temp t = src0;
 557          src0 = src1;
 558          src1 = t;
 559       } else {
 560          src1 = as_vgpr(ctx, src1);
 561       }
 562    }
 563
 564    Builder bld(ctx->program, ctx->block);
 565    bld.vopc(op, bld.hint_vcc(Definition(dst)), src0, src1);
 566 }
 567
 568 void emit_sopc_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 569 {
 570    Temp src0 = get_alu_src(ctx, instr->src[0]);
 571    Temp src1 = get_alu_src(ctx, instr->src[1]);
 572    Builder bld(ctx->program, ctx->block);
 573
 574    assert(dst.regClass() == bld.lm);
 575    assert(src0.type() == RegType::sgpr);
 576    assert(src1.type() == RegType::sgpr);
 577    assert(src0.regClass() == src1.regClass());
 578
 579    /* Emit the SALU comparison instruction */
 580    Temp cmp = bld.sopc(op, bld.scc(bld.def(s1)), src0, src1);
 581    /* Turn the result into a per-lane bool */
 582    bool_to_vector_condition(ctx, cmp, dst);
 583 }
 584
 585 void emit_comparison(isel_context *ctx, nir_alu_instr *instr, Temp dst,
 586                      aco_opcode v32_op, aco_opcode v64_op, aco_opcode s32_op = aco_opcode::num_opcodes, aco_opcode s64_op = aco_opcode::num_opcodes)
 587 {
 588    aco_opcode s_op = instr->src[0].src.ssa->bit_size == 64 ? s64_op : s32_op;
 589    aco_opcode v_op = instr->src[0].src.ssa->bit_size == 64 ? v64_op : v32_op;
 590    bool divergent_vals = ctx->divergent_vals[instr->dest.dest.ssa.index];
 591    bool use_valu = s_op == aco_opcode::num_opcodes ||
 592                    divergent_vals ||
 593                    ctx->allocated[instr->src[0].src.ssa->index].type() == RegType::vgpr ||
 594                    ctx->allocated[instr->src[1].src.ssa->index].type() == RegType::vgpr;
 595    aco_opcode op = use_valu ? v_op : s_op;
 596    assert(op != aco_opcode::num_opcodes);
 597    assert(dst.regClass() == ctx->program->lane_mask);
 598
 599    if (use_valu)
 600       emit_vopc_instruction(ctx, instr, op, dst);
 601    else
 602       emit_sopc_instruction(ctx, instr, op, dst);
 603 }
 604
 605 void emit_boolean_logic(isel_context *ctx, nir_alu_instr *instr, Builder::WaveSpecificOpcode op, Temp dst)
 606 {
 607    Builder bld(ctx->program, ctx->block);
 608    Temp src0 = get_alu_src(ctx, instr->src[0]);
 609    Temp src1 = get_alu_src(ctx, instr->src[1]);
 610
 611    assert(dst.regClass() == bld.lm);
 612    assert(src0.regClass() == bld.lm);
 613    assert(src1.regClass() == bld.lm);
 614
 615    bld.sop2(op, Definition(dst), bld.def(s1, scc), src0, src1);
 616 }
 617
 618 void emit_bcsel(isel_context *ctx, nir_alu_instr *instr, Temp dst)
 619 {
 620    Builder bld(ctx->program, ctx->block);
 621    Temp cond = get_alu_src(ctx, instr->src[0]);
 622    Temp then = get_alu_src(ctx, instr->src[1]);
 623    Temp els = get_alu_src(ctx, instr->src[2]);
 624
 625    assert(cond.regClass() == bld.lm);
 626
 627    if (dst.type() == RegType::vgpr) {
 628       aco_ptr<Instruction> bcsel;
 629       if (dst.size() == 1) {
 630          then = as_vgpr(ctx, then);
 631          els = as_vgpr(ctx, els);
 632
 633          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), els, then, cond);
 634       } else if (dst.size() == 2) {
 635          Temp then_lo = bld.tmp(v1), then_hi = bld.tmp(v1);
 636          bld.pseudo(aco_opcode::p_split_vector, Definition(then_lo), Definition(then_hi), then);
 637          Temp else_lo = bld.tmp(v1), else_hi = bld.tmp(v1);
 638          bld.pseudo(aco_opcode::p_split_vector, Definition(else_lo), Definition(else_hi), els);
 639
 640          Temp dst0 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_lo, then_lo, cond);
 641          Temp dst1 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_hi, then_hi, cond);
 642
 643          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
 644       } else {
 645          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 646          nir_print_instr(&instr->instr, stderr);
 647          fprintf(stderr, "\n");
 648       }
 649       return;
 650    }
 651
 652    if (instr->dest.dest.ssa.bit_size == 1) {
 653       assert(dst.regClass() == bld.lm);
 654       assert(then.regClass() == bld.lm);
 655       assert(els.regClass() == bld.lm);
 656    }
 657
 658    if (!ctx->divergent_vals[instr->src[0].src.ssa->index]) { /* uniform condition and values in sgpr */
 659       if (dst.regClass() == s1 || dst.regClass() == s2) {
 660          assert((then.regClass() == s1 || then.regClass() == s2) && els.regClass() == then.regClass());
 661          assert(dst.size() == then.size());
 662          aco_opcode op = dst.regClass() == s1 ? aco_opcode::s_cselect_b32 : aco_opcode::s_cselect_b64;
 663          bld.sop2(op, Definition(dst), then, els, bld.scc(bool_to_scalar_condition(ctx, cond)));
 664       } else {
 665          fprintf(stderr, "Unimplemented uniform bcsel bit size: ");
 666          nir_print_instr(&instr->instr, stderr);
 667          fprintf(stderr, "\n");
 668       }
 669       return;
 670    }
 671
 672    /* divergent boolean bcsel
 673     * this implements bcsel on bools: dst = s0 ? s1 : s2
 674     * are going to be: dst = (s0 & s1) | (~s0 & s2) */
 675    assert(instr->dest.dest.ssa.bit_size == 1);
 676
 677    if (cond.id() != then.id())
 678       then = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), cond, then);
 679
 680    if (cond.id() == els.id())
 681       bld.sop1(Builder::s_mov, Definition(dst), then);
 682    else
 683       bld.sop2(Builder::s_or, Definition(dst), bld.def(s1, scc), then,
 684                bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), els, cond));
 685 }
 686
 687 void emit_scaled_op(isel_context *ctx, Builder& bld, Definition dst, Temp val,
 688                     aco_opcode op, uint32_t undo)
 689 {
 690    /* multiply by 16777216 to handle denormals */
 691    Temp is_denormal = bld.vopc(aco_opcode::v_cmp_class_f32, bld.hint_vcc(bld.def(bld.lm)),
 692                                as_vgpr(ctx, val), bld.copy(bld.def(v1), Operand((1u << 7) | (1u << 4))));
 693    Temp scaled = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x4b800000u), val);
 694    scaled = bld.vop1(op, bld.def(v1), scaled);
 695    scaled = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(undo), scaled);
 696
 697    Temp not_scaled = bld.vop1(op, bld.def(v1), val);
 698
 699    bld.vop2(aco_opcode::v_cndmask_b32, dst, not_scaled, scaled, is_denormal);
 700 }
 701
 702 void emit_rcp(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 703 {
 704    if (ctx->block->fp_mode.denorm32 == 0) {
 705       bld.vop1(aco_opcode::v_rcp_f32, dst, val);
 706       return;
 707    }
 708
 709    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_rcp_f32, 0x4b800000u);
 710 }
 711
 712 void emit_rsq(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 713 {
 714    if (ctx->block->fp_mode.denorm32 == 0) {
 715       bld.vop1(aco_opcode::v_rsq_f32, dst, val);
 716       return;
 717    }
 718
 719    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_rsq_f32, 0x45800000u);
 720 }
 721
 722 void emit_sqrt(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 723 {
 724    if (ctx->block->fp_mode.denorm32 == 0) {
 725       bld.vop1(aco_opcode::v_sqrt_f32, dst, val);
 726       return;
 727    }
 728
 729    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_sqrt_f32, 0x39800000u);
 730 }
 731
 732 void emit_log2(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 733 {
 734    if (ctx->block->fp_mode.denorm32 == 0) {
 735       bld.vop1(aco_opcode::v_log_f32, dst, val);
 736       return;
 737    }
 738
 739    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_log_f32, 0xc1c00000u);
 740 }
 741
 742 Temp emit_trunc_f64(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 743 {
 744    if (ctx->options->chip_class >= GFX7)
 745       return bld.vop1(aco_opcode::v_trunc_f64, Definition(dst), val);
 746
 747    /* GFX6 doesn't support V_TRUNC_F64, lower it. */
 748    /* TODO: create more efficient code! */
 749    if (val.type() == RegType::sgpr)
 750       val = as_vgpr(ctx, val);
 751
 752    /* Split the input value. */
 753    Temp val_lo = bld.tmp(v1), val_hi = bld.tmp(v1);
 754    bld.pseudo(aco_opcode::p_split_vector, Definition(val_lo), Definition(val_hi), val);
 755
 756    /* Extract the exponent and compute the unbiased value. */
 757    Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f64, bld.def(v1), val);
 758
 759    /* Extract the fractional part. */
 760    Temp fract_mask = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(-1u), Operand(0x000fffffu));
 761    fract_mask = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), fract_mask, exponent);
 762
 763    Temp fract_mask_lo = bld.tmp(v1), fract_mask_hi = bld.tmp(v1);
 764    bld.pseudo(aco_opcode::p_split_vector, Definition(fract_mask_lo), Definition(fract_mask_hi), fract_mask);
 765
 766    Temp fract_lo = bld.tmp(v1), fract_hi = bld.tmp(v1);
 767    Temp tmp = bld.vop1(aco_opcode::v_not_b32, bld.def(v1), fract_mask_lo);
 768    fract_lo = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), val_lo, tmp);
 769    tmp = bld.vop1(aco_opcode::v_not_b32, bld.def(v1), fract_mask_hi);
 770    fract_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), val_hi, tmp);
 771
 772    /* Get the sign bit. */
 773    Temp sign = bld.vop2(aco_opcode::v_ashr_i32, bld.def(v1), Operand(31u), val_hi);
 774
 775    /* Decide the operation to apply depending on the unbiased exponent. */
 776    Temp exp_lt0 = bld.vopc_e64(aco_opcode::v_cmp_lt_i32, bld.hint_vcc(bld.def(bld.lm)), exponent, Operand(0u));
 777    Temp dst_lo = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), fract_lo, bld.copy(bld.def(v1), Operand(0u)), exp_lt0);
 778    Temp dst_hi = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), fract_hi, sign, exp_lt0);
 779    Temp exp_gt51 = bld.vopc_e64(aco_opcode::v_cmp_gt_i32, bld.def(s2), exponent, Operand(51u));
 780    dst_lo = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), dst_lo, val_lo, exp_gt51);
 781    dst_hi = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), dst_hi, val_hi, exp_gt51);
 782
 783    return bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst_lo, dst_hi);
 784 }
 785
 786 Temp emit_floor_f64(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 787 {
 788    if (ctx->options->chip_class >= GFX7)
 789       return bld.vop1(aco_opcode::v_floor_f64, Definition(dst), val);
 790
 791    /* GFX6 doesn't support V_FLOOR_F64, lower it. */
 792    Temp src0 = as_vgpr(ctx, val);
 793
 794    Temp mask = bld.copy(bld.def(s1), Operand(3u)); /* isnan */
 795    Temp min_val = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(-1u), Operand(0x3fefffffu));
 796
 797    Temp isnan = bld.vopc_e64(aco_opcode::v_cmp_class_f64, bld.hint_vcc(bld.def(bld.lm)), src0, mask);
 798    Temp fract = bld.vop1(aco_opcode::v_fract_f64, bld.def(v2), src0);
 799    Temp min = bld.vop3(aco_opcode::v_min_f64, bld.def(v2), fract, min_val);
 800
 801    Temp then_lo = bld.tmp(v1), then_hi = bld.tmp(v1);
 802    bld.pseudo(aco_opcode::p_split_vector, Definition(then_lo), Definition(then_hi), src0);
 803    Temp else_lo = bld.tmp(v1), else_hi = bld.tmp(v1);
 804    bld.pseudo(aco_opcode::p_split_vector, Definition(else_lo), Definition(else_hi), min);
 805
 806    Temp dst0 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_lo, then_lo, isnan);
 807    Temp dst1 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_hi, then_hi, isnan);
 808
 809    Temp v = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), dst0, dst1);
 810
 811    Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst), src0, v);
 812    static_cast<VOP3A_instruction*>(add)->neg[1] = true;
 813
 814    return add->definitions[0].getTemp();
 815 }
 816
 817 void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
 818 {
 819    if (!instr->dest.dest.is_ssa) {
 820       fprintf(stderr, "nir alu dst not in ssa: ");
 821       nir_print_instr(&instr->instr, stderr);
 822       fprintf(stderr, "\n");
 823       abort();
 824    }
 825    Builder bld(ctx->program, ctx->block);
 826    Temp dst = get_ssa_temp(ctx, &instr->dest.dest.ssa);
 827    switch(instr->op) {
 828    case nir_op_vec2:
 829    case nir_op_vec3:
 830    case nir_op_vec4: {
 831       std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 832       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.dest.ssa.num_components, 1)};
 833       for (unsigned i = 0; i < instr->dest.dest.ssa.num_components; ++i) {
 834          elems[i] = get_alu_src(ctx, instr->src[i]);
 835          vec->operands[i] = Operand{elems[i]};
 836       }
 837       vec->definitions[0] = Definition(dst);
 838       ctx->block->instructions.emplace_back(std::move(vec));
 839       ctx->allocated_vec.emplace(dst.id(), elems);
 840       break;
 841    }
 842    case nir_op_mov: {
 843       Temp src = get_alu_src(ctx, instr->src[0]);
 844       aco_ptr<Instruction> mov;
 845       if (dst.type() == RegType::sgpr) {
 846          if (src.type() == RegType::vgpr)
 847             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), src);
 848          else if (src.regClass() == s1)
 849             bld.sop1(aco_opcode::s_mov_b32, Definition(dst), src);
 850          else if (src.regClass() == s2)
 851             bld.sop1(aco_opcode::s_mov_b64, Definition(dst), src);
 852          else
 853             unreachable("wrong src register class for nir_op_imov");
 854       } else if (dst.regClass() == v1) {
 855          bld.vop1(aco_opcode::v_mov_b32, Definition(dst), src);
 856       } else if (dst.regClass() == v2) {
 857          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src);
 858       } else {
 859          nir_print_instr(&instr->instr, stderr);
 860          unreachable("Should have been lowered to scalar.");
 861       }
 862       break;
 863    }
 864    case nir_op_inot: {
 865       Temp src = get_alu_src(ctx, instr->src[0]);
 866       if (instr->dest.dest.ssa.bit_size == 1) {
 867          assert(src.regClass() == bld.lm);
 868          assert(dst.regClass() == bld.lm);
 869          /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
 870          Temp tmp = bld.sop1(Builder::s_not, bld.def(bld.lm), bld.def(s1, scc), src);
 871          bld.sop2(Builder::s_and, Definition(dst), bld.def(s1, scc), tmp, Operand(exec, bld.lm));
 872       } else if (dst.regClass() == v1) {
 873          emit_vop1_instruction(ctx, instr, aco_opcode::v_not_b32, dst);
 874       } else if (dst.type() == RegType::sgpr) {
 875          aco_opcode opcode = dst.size() == 1 ? aco_opcode::s_not_b32 : aco_opcode::s_not_b64;
 876          bld.sop1(opcode, Definition(dst), bld.def(s1, scc), src);
 877       } else {
 878          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 879          nir_print_instr(&instr->instr, stderr);
 880          fprintf(stderr, "\n");
 881       }
 882       break;
 883    }
 884    case nir_op_ineg: {
 885       Temp src = get_alu_src(ctx, instr->src[0]);
 886       if (dst.regClass() == v1) {
 887          bld.vsub32(Definition(dst), Operand(0u), Operand(src));
 888       } else if (dst.regClass() == s1) {
 889          bld.sop2(aco_opcode::s_mul_i32, Definition(dst), Operand((uint32_t) -1), src);
 890       } else if (dst.size() == 2) {
 891          Temp src0 = bld.tmp(dst.type(), 1);
 892          Temp src1 = bld.tmp(dst.type(), 1);
 893          bld.pseudo(aco_opcode::p_split_vector, Definition(src0), Definition(src1), src);
 894
 895          if (dst.regClass() == s2) {
 896             Temp carry = bld.tmp(s1);
 897             Temp dst0 = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(carry)), Operand(0u), src0);
 898             Temp dst1 = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), src1, carry);
 899             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
 900          } else {
 901             Temp lower = bld.tmp(v1);
 902             Temp borrow = bld.vsub32(Definition(lower), Operand(0u), src0, true).def(1).getTemp();
 903             Temp upper = bld.vsub32(bld.def(v1), Operand(0u), src1, false, borrow);
 904             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
 905          }
 906       } else {
 907          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 908          nir_print_instr(&instr->instr, stderr);
 909          fprintf(stderr, "\n");
 910       }
 911       break;
 912    }
 913    case nir_op_iabs: {
 914       if (dst.regClass() == s1) {
 915          bld.sop1(aco_opcode::s_abs_i32, Definition(dst), bld.def(s1, scc), get_alu_src(ctx, instr->src[0]));
 916       } else if (dst.regClass() == v1) {
 917          Temp src = get_alu_src(ctx, instr->src[0]);
 918          bld.vop2(aco_opcode::v_max_i32, Definition(dst), src, bld.vsub32(bld.def(v1), Operand(0u), src));
 919       } else {
 920          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 921          nir_print_instr(&instr->instr, stderr);
 922          fprintf(stderr, "\n");
 923       }
 924       break;
 925    }
 926    case nir_op_isign: {
 927       Temp src = get_alu_src(ctx, instr->src[0]);
 928       if (dst.regClass() == s1) {
 929          Temp tmp = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
 930          Temp gtz = bld.sopc(aco_opcode::s_cmp_gt_i32, bld.def(s1, scc), src, Operand(0u));
 931          bld.sop2(aco_opcode::s_add_i32, Definition(dst), bld.def(s1, scc), gtz, tmp);
 932       } else if (dst.regClass() == s2) {
 933          Temp neg = bld.sop2(aco_opcode::s_ashr_i64, bld.def(s2), bld.def(s1, scc), src, Operand(63u));
 934          Temp neqz;
 935          if (ctx->program->chip_class >= GFX8)
 936             neqz = bld.sopc(aco_opcode::s_cmp_lg_u64, bld.def(s1, scc), src, Operand(0u));
 937          else
 938             neqz = bld.sop2(aco_opcode::s_or_b64, bld.def(s2), bld.def(s1, scc), src, Operand(0u)).def(1).getTemp();
 939          /* SCC gets zero-extended to 64 bit */
 940          bld.sop2(aco_opcode::s_or_b64, Definition(dst), bld.def(s1, scc), neg, bld.scc(neqz));
 941       } else if (dst.regClass() == v1) {
 942          Temp tmp = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
 943          Temp gtz = bld.vopc(aco_opcode::v_cmp_ge_i32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
 944          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(1u), tmp, gtz);
 945       } else if (dst.regClass() == v2) {
 946          Temp upper = emit_extract_vector(ctx, src, 1, v1);
 947          Temp neg = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), upper);
 948          Temp gtz = bld.vopc(aco_opcode::v_cmp_ge_i64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
 949          Temp lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(1u), neg, gtz);
 950          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), neg, gtz);
 951          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
 952       } else {
 953          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 954          nir_print_instr(&instr->instr, stderr);
 955          fprintf(stderr, "\n");
 956       }
 957       break;
 958    }
 959    case nir_op_imax: {
 960       if (dst.regClass() == v1) {
 961          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_i32, dst, true);
 962       } else if (dst.regClass() == s1) {
 963          emit_sop2_instruction(ctx, instr, aco_opcode::s_max_i32, dst, true);
 964       } else {
 965          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 966          nir_print_instr(&instr->instr, stderr);
 967          fprintf(stderr, "\n");
 968       }
 969       break;
 970    }
 971    case nir_op_umax: {
 972       if (dst.regClass() == v1) {
 973          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_u32, dst, true);
 974       } else if (dst.regClass() == s1) {
 975          emit_sop2_instruction(ctx, instr, aco_opcode::s_max_u32, dst, true);
 976       } else {
 977          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 978          nir_print_instr(&instr->instr, stderr);
 979          fprintf(stderr, "\n");
 980       }
 981       break;
 982    }
 983    case nir_op_imin: {
 984       if (dst.regClass() == v1) {
 985          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_i32, dst, true);
 986       } else if (dst.regClass() == s1) {
 987          emit_sop2_instruction(ctx, instr, aco_opcode::s_min_i32, dst, true);
 988       } else {
 989          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 990          nir_print_instr(&instr->instr, stderr);
 991          fprintf(stderr, "\n");
 992       }
 993       break;
 994    }
 995    case nir_op_umin: {
 996       if (dst.regClass() == v1) {
 997          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_u32, dst, true);
 998       } else if (dst.regClass() == s1) {
 999          emit_sop2_instruction(ctx, instr, aco_opcode::s_min_u32, dst, true);
1000       } else {
1001          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1002          nir_print_instr(&instr->instr, stderr);
1003          fprintf(stderr, "\n");
1004       }
1005       break;
1006    }
1007    case nir_op_ior: {
1008       if (instr->dest.dest.ssa.bit_size == 1) {
1009          emit_boolean_logic(ctx, instr, Builder::s_or, dst);
1010       } else if (dst.regClass() == v1) {
1011          emit_vop2_instruction(ctx, instr, aco_opcode::v_or_b32, dst, true);
1012       } else if (dst.regClass() == s1) {
1013          emit_sop2_instruction(ctx, instr, aco_opcode::s_or_b32, dst, true);
1014       } else if (dst.regClass() == s2) {
1015          emit_sop2_instruction(ctx, instr, aco_opcode::s_or_b64, dst, true);
1016       } else {
1017          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1018          nir_print_instr(&instr->instr, stderr);
1019          fprintf(stderr, "\n");
1020       }
1021       break;
1022    }
1023    case nir_op_iand: {
1024       if (instr->dest.dest.ssa.bit_size == 1) {
1025          emit_boolean_logic(ctx, instr, Builder::s_and, dst);
1026       } else if (dst.regClass() == v1) {
1027          emit_vop2_instruction(ctx, instr, aco_opcode::v_and_b32, dst, true);
1028       } else if (dst.regClass() == s1) {
1029          emit_sop2_instruction(ctx, instr, aco_opcode::s_and_b32, dst, true);
1030       } else if (dst.regClass() == s2) {
1031          emit_sop2_instruction(ctx, instr, aco_opcode::s_and_b64, dst, true);
1032       } else {
1033          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1034          nir_print_instr(&instr->instr, stderr);
1035          fprintf(stderr, "\n");
1036       }
1037       break;
1038    }
1039    case nir_op_ixor: {
1040       if (instr->dest.dest.ssa.bit_size == 1) {
1041          emit_boolean_logic(ctx, instr, Builder::s_xor, dst);
1042       } else if (dst.regClass() == v1) {
1043          emit_vop2_instruction(ctx, instr, aco_opcode::v_xor_b32, dst, true);
1044       } else if (dst.regClass() == s1) {
1045          emit_sop2_instruction(ctx, instr, aco_opcode::s_xor_b32, dst, true);
1046       } else if (dst.regClass() == s2) {
1047          emit_sop2_instruction(ctx, instr, aco_opcode::s_xor_b64, dst, true);
1048       } else {
1049          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1050          nir_print_instr(&instr->instr, stderr);
1051          fprintf(stderr, "\n");
1052       }
1053       break;
1054    }
1055    case nir_op_ushr: {
1056       if (dst.regClass() == v1) {
1057          emit_vop2_instruction(ctx, instr, aco_opcode::v_lshrrev_b32, dst, false, true);
1058       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
1059          bld.vop3(aco_opcode::v_lshrrev_b64, Definition(dst),
1060                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
1061       } else if (dst.regClass() == v2) {
1062          bld.vop3(aco_opcode::v_lshr_b64, Definition(dst),
1063                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1064       } else if (dst.regClass() == s2) {
1065          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshr_b64, dst, true);
1066       } else if (dst.regClass() == s1) {
1067          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshr_b32, dst, true);
1068       } else {
1069          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1070          nir_print_instr(&instr->instr, stderr);
1071          fprintf(stderr, "\n");
1072       }
1073       break;
1074    }
1075    case nir_op_ishl: {
1076       if (dst.regClass() == v1) {
1077          emit_vop2_instruction(ctx, instr, aco_opcode::v_lshlrev_b32, dst, false, true);
1078       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
1079          bld.vop3(aco_opcode::v_lshlrev_b64, Definition(dst),
1080                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
1081       } else if (dst.regClass() == v2) {
1082          bld.vop3(aco_opcode::v_lshl_b64, Definition(dst),
1083                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1084       } else if (dst.regClass() == s1) {
1085          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshl_b32, dst, true);
1086       } else if (dst.regClass() == s2) {
1087          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshl_b64, dst, true);
1088       } else {
1089          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1090          nir_print_instr(&instr->instr, stderr);
1091          fprintf(stderr, "\n");
1092       }
1093       break;
1094    }
1095    case nir_op_ishr: {
1096       if (dst.regClass() == v1) {
1097          emit_vop2_instruction(ctx, instr, aco_opcode::v_ashrrev_i32, dst, false, true);
1098       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
1099          bld.vop3(aco_opcode::v_ashrrev_i64, Definition(dst),
1100                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
1101       } else if (dst.regClass() == v2) {
1102          bld.vop3(aco_opcode::v_ashr_i64, Definition(dst),
1103                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1104       } else if (dst.regClass() == s1) {
1105          emit_sop2_instruction(ctx, instr, aco_opcode::s_ashr_i32, dst, true);
1106       } else if (dst.regClass() == s2) {
1107          emit_sop2_instruction(ctx, instr, aco_opcode::s_ashr_i64, dst, true);
1108       } else {
1109          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1110          nir_print_instr(&instr->instr, stderr);
1111          fprintf(stderr, "\n");
1112       }
1113       break;
1114    }
1115    case nir_op_find_lsb: {
1116       Temp src = get_alu_src(ctx, instr->src[0]);
1117       if (src.regClass() == s1) {
1118          bld.sop1(aco_opcode::s_ff1_i32_b32, Definition(dst), src);
1119       } else if (src.regClass() == v1) {
1120          emit_vop1_instruction(ctx, instr, aco_opcode::v_ffbl_b32, dst);
1121       } else if (src.regClass() == s2) {
1122          bld.sop1(aco_opcode::s_ff1_i32_b64, Definition(dst), src);
1123       } else {
1124          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1125          nir_print_instr(&instr->instr, stderr);
1126          fprintf(stderr, "\n");
1127       }
1128       break;
1129    }
1130    case nir_op_ufind_msb:
1131    case nir_op_ifind_msb: {
1132       Temp src = get_alu_src(ctx, instr->src[0]);
1133       if (src.regClass() == s1 || src.regClass() == s2) {
1134          aco_opcode op = src.regClass() == s2 ?
1135                          (instr->op == nir_op_ufind_msb ? aco_opcode::s_flbit_i32_b64 : aco_opcode::s_flbit_i32_i64) :
1136                          (instr->op == nir_op_ufind_msb ? aco_opcode::s_flbit_i32_b32 : aco_opcode::s_flbit_i32);
1137          Temp msb_rev = bld.sop1(op, bld.def(s1), src);
1138
1139          Builder::Result sub = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc),
1140                                         Operand(src.size() * 32u - 1u), msb_rev);
1141          Temp msb = sub.def(0).getTemp();
1142          Temp carry = sub.def(1).getTemp();
1143
1144          bld.sop2(aco_opcode::s_cselect_b32, Definition(dst), Operand((uint32_t)-1), msb, bld.scc(carry));
1145       } else if (src.regClass() == v1) {
1146          aco_opcode op = instr->op == nir_op_ufind_msb ? aco_opcode::v_ffbh_u32 : aco_opcode::v_ffbh_i32;
1147          Temp msb_rev = bld.tmp(v1);
1148          emit_vop1_instruction(ctx, instr, op, msb_rev);
1149          Temp msb = bld.tmp(v1);
1150          Temp carry = bld.vsub32(Definition(msb), Operand(31u), Operand(msb_rev), true).def(1).getTemp();
1151          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), msb, Operand((uint32_t)-1), carry);
1152       } else {
1153          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1154          nir_print_instr(&instr->instr, stderr);
1155          fprintf(stderr, "\n");
1156       }
1157       break;
1158    }
1159    case nir_op_bitfield_reverse: {
1160       if (dst.regClass() == s1) {
1161          bld.sop1(aco_opcode::s_brev_b32, Definition(dst), get_alu_src(ctx, instr->src[0]));
1162       } else if (dst.regClass() == v1) {
1163          bld.vop1(aco_opcode::v_bfrev_b32, Definition(dst), get_alu_src(ctx, instr->src[0]));
1164       } else {
1165          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1166          nir_print_instr(&instr->instr, stderr);
1167          fprintf(stderr, "\n");
1168       }
1169       break;
1170    }
1171    case nir_op_iadd: {
1172       if (dst.regClass() == s1) {
1173          emit_sop2_instruction(ctx, instr, aco_opcode::s_add_u32, dst, true);
1174          break;
1175       }
1176
1177       Temp src0 = get_alu_src(ctx, instr->src[0]);
1178       Temp src1 = get_alu_src(ctx, instr->src[1]);
1179       if (dst.regClass() == v1) {
1180          bld.vadd32(Definition(dst), Operand(src0), Operand(src1));
1181          break;
1182       }
1183
1184       assert(src0.size() == 2 && src1.size() == 2);
1185       Temp src00 = bld.tmp(src0.type(), 1);
1186       Temp src01 = bld.tmp(dst.type(), 1);
1187       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1188       Temp src10 = bld.tmp(src1.type(), 1);
1189       Temp src11 = bld.tmp(dst.type(), 1);
1190       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1191
1192       if (dst.regClass() == s2) {
1193          Temp carry = bld.tmp(s1);
1194          Temp dst0 = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1195          Temp dst1 = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), src01, src11, bld.scc(carry));
1196          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1197       } else if (dst.regClass() == v2) {
1198          Temp dst0 = bld.tmp(v1);
1199          Temp carry = bld.vadd32(Definition(dst0), src00, src10, true).def(1).getTemp();
1200          Temp dst1 = bld.vadd32(bld.def(v1), src01, src11, false, carry);
1201          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1202       } else {
1203          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1204          nir_print_instr(&instr->instr, stderr);
1205          fprintf(stderr, "\n");
1206       }
1207       break;
1208    }
1209    case nir_op_uadd_sat: {
1210       Temp src0 = get_alu_src(ctx, instr->src[0]);
1211       Temp src1 = get_alu_src(ctx, instr->src[1]);
1212       if (dst.regClass() == s1) {
1213          Temp tmp = bld.tmp(s1), carry = bld.tmp(s1);
1214          bld.sop2(aco_opcode::s_add_u32, Definition(tmp), bld.scc(Definition(carry)),
1215                   src0, src1);
1216          bld.sop2(aco_opcode::s_cselect_b32, Definition(dst), Operand((uint32_t) -1), tmp, bld.scc(carry));
1217       } else if (dst.regClass() == v1) {
1218          if (ctx->options->chip_class >= GFX9) {
1219             aco_ptr<VOP3A_instruction> add{create_instruction<VOP3A_instruction>(aco_opcode::v_add_u32, asVOP3(Format::VOP2), 2, 1)};
1220             add->operands[0] = Operand(src0);
1221             add->operands[1] = Operand(src1);
1222             add->definitions[0] = Definition(dst);
1223             add->clamp = 1;
1224             ctx->block->instructions.emplace_back(std::move(add));
1225          } else {
1226             if (src1.regClass() != v1)
1227                std::swap(src0, src1);
1228             assert(src1.regClass() == v1);
1229             Temp tmp = bld.tmp(v1);
1230             Temp carry = bld.vadd32(Definition(tmp), src0, src1, true).def(1).getTemp();
1231             bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), tmp, Operand((uint32_t) -1), carry);
1232          }
1233       } else {
1234          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1235          nir_print_instr(&instr->instr, stderr);
1236          fprintf(stderr, "\n");
1237       }
1238       break;
1239    }
1240    case nir_op_uadd_carry: {
1241       Temp src0 = get_alu_src(ctx, instr->src[0]);
1242       Temp src1 = get_alu_src(ctx, instr->src[1]);
1243       if (dst.regClass() == s1) {
1244          bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(dst)), src0, src1);
1245          break;
1246       }
1247       if (dst.regClass() == v1) {
1248          Temp carry = bld.vadd32(bld.def(v1), src0, src1, true).def(1).getTemp();
1249          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), carry);
1250          break;
1251       }
1252
1253       Temp src00 = bld.tmp(src0.type(), 1);
1254       Temp src01 = bld.tmp(dst.type(), 1);
1255       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1256       Temp src10 = bld.tmp(src1.type(), 1);
1257       Temp src11 = bld.tmp(dst.type(), 1);
1258       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1259       if (dst.regClass() == s2) {
1260          Temp carry = bld.tmp(s1);
1261          bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1262          carry = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.scc(bld.def(s1)), src01, src11, bld.scc(carry)).def(1).getTemp();
1263          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), carry, Operand(0u));
1264       } else if (dst.regClass() == v2) {
1265          Temp carry = bld.vadd32(bld.def(v1), src00, src10, true).def(1).getTemp();
1266          carry = bld.vadd32(bld.def(v1), src01, src11, true, carry).def(1).getTemp();
1267          carry = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand(1u), carry);
1268          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), carry, Operand(0u));
1269       } else {
1270          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1271          nir_print_instr(&instr->instr, stderr);
1272          fprintf(stderr, "\n");
1273       }
1274       break;
1275    }
1276    case nir_op_isub: {
1277       if (dst.regClass() == s1) {
1278          emit_sop2_instruction(ctx, instr, aco_opcode::s_sub_i32, dst, true);
1279          break;
1280       }
1281
1282       Temp src0 = get_alu_src(ctx, instr->src[0]);
1283       Temp src1 = get_alu_src(ctx, instr->src[1]);
1284       if (dst.regClass() == v1) {
1285          bld.vsub32(Definition(dst), src0, src1);
1286          break;
1287       }
1288
1289       Temp src00 = bld.tmp(src0.type(), 1);
1290       Temp src01 = bld.tmp(dst.type(), 1);
1291       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1292       Temp src10 = bld.tmp(src1.type(), 1);
1293       Temp src11 = bld.tmp(dst.type(), 1);
1294       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1295       if (dst.regClass() == s2) {
1296          Temp carry = bld.tmp(s1);
1297          Temp dst0 = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1298          Temp dst1 = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), src01, src11, carry);
1299          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1300       } else if (dst.regClass() == v2) {
1301          Temp lower = bld.tmp(v1);
1302          Temp borrow = bld.vsub32(Definition(lower), src00, src10, true).def(1).getTemp();
1303          Temp upper = bld.vsub32(bld.def(v1), src01, src11, false, borrow);
1304          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1305       } else {
1306          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1307          nir_print_instr(&instr->instr, stderr);
1308          fprintf(stderr, "\n");
1309       }
1310       break;
1311    }
1312    case nir_op_usub_borrow: {
1313       Temp src0 = get_alu_src(ctx, instr->src[0]);
1314       Temp src1 = get_alu_src(ctx, instr->src[1]);
1315       if (dst.regClass() == s1) {
1316          bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(dst)), src0, src1);
1317          break;
1318       } else if (dst.regClass() == v1) {
1319          Temp borrow = bld.vsub32(bld.def(v1), src0, src1, true).def(1).getTemp();
1320          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), borrow);
1321          break;
1322       }
1323
1324       Temp src00 = bld.tmp(src0.type(), 1);
1325       Temp src01 = bld.tmp(dst.type(), 1);
1326       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1327       Temp src10 = bld.tmp(src1.type(), 1);
1328       Temp src11 = bld.tmp(dst.type(), 1);
1329       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1330       if (dst.regClass() == s2) {
1331          Temp borrow = bld.tmp(s1);
1332          bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(borrow)), src00, src10);
1333          borrow = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.scc(bld.def(s1)), src01, src11, bld.scc(borrow)).def(1).getTemp();
1334          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), borrow, Operand(0u));
1335       } else if (dst.regClass() == v2) {
1336          Temp borrow = bld.vsub32(bld.def(v1), src00, src10, true).def(1).getTemp();
1337          borrow = bld.vsub32(bld.def(v1), src01, src11, true, Operand(borrow)).def(1).getTemp();
1338          borrow = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand(1u), borrow);
1339          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), borrow, Operand(0u));
1340       } else {
1341          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1342          nir_print_instr(&instr->instr, stderr);
1343          fprintf(stderr, "\n");
1344       }
1345       break;
1346    }
1347    case nir_op_imul: {
1348       if (dst.regClass() == v1) {
1349          bld.vop3(aco_opcode::v_mul_lo_u32, Definition(dst),
1350                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1351       } else if (dst.regClass() == s1) {
1352          emit_sop2_instruction(ctx, instr, aco_opcode::s_mul_i32, dst, false);
1353       } else {
1354          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1355          nir_print_instr(&instr->instr, stderr);
1356          fprintf(stderr, "\n");
1357       }
1358       break;
1359    }
1360    case nir_op_umul_high: {
1361       if (dst.regClass() == v1) {
1362          bld.vop3(aco_opcode::v_mul_hi_u32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1363       } else if (dst.regClass() == s1 && ctx->options->chip_class >= GFX9) {
1364          bld.sop2(aco_opcode::s_mul_hi_u32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1365       } else if (dst.regClass() == s1) {
1366          Temp tmp = bld.vop3(aco_opcode::v_mul_hi_u32, bld.def(v1), get_alu_src(ctx, instr->src[0]),
1367                              as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1368          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), tmp);
1369       } else {
1370          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1371          nir_print_instr(&instr->instr, stderr);
1372          fprintf(stderr, "\n");
1373       }
1374       break;
1375    }
1376    case nir_op_imul_high: {
1377       if (dst.regClass() == v1) {
1378          bld.vop3(aco_opcode::v_mul_hi_i32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1379       } else if (dst.regClass() == s1 && ctx->options->chip_class >= GFX9) {
1380          bld.sop2(aco_opcode::s_mul_hi_i32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1381       } else if (dst.regClass() == s1) {
1382          Temp tmp = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), get_alu_src(ctx, instr->src[0]),
1383                              as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1384          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), tmp);
1385       } else {
1386          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1387          nir_print_instr(&instr->instr, stderr);
1388          fprintf(stderr, "\n");
1389       }
1390       break;
1391    }
1392    case nir_op_fmul: {
1393       if (dst.size() == 1) {
1394          emit_vop2_instruction(ctx, instr, aco_opcode::v_mul_f32, dst, true);
1395       } else if (dst.size() == 2) {
1396          bld.vop3(aco_opcode::v_mul_f64, Definition(dst), get_alu_src(ctx, instr->src[0]),
1397                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1398       } else {
1399          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1400          nir_print_instr(&instr->instr, stderr);
1401          fprintf(stderr, "\n");
1402       }
1403       break;
1404    }
1405    case nir_op_fadd: {
1406       if (dst.size() == 1) {
1407          emit_vop2_instruction(ctx, instr, aco_opcode::v_add_f32, dst, true);
1408       } else if (dst.size() == 2) {
1409          bld.vop3(aco_opcode::v_add_f64, Definition(dst), get_alu_src(ctx, instr->src[0]),
1410                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1411       } else {
1412          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1413          nir_print_instr(&instr->instr, stderr);
1414          fprintf(stderr, "\n");
1415       }
1416       break;
1417    }
1418    case nir_op_fsub: {
1419       Temp src0 = get_alu_src(ctx, instr->src[0]);
1420       Temp src1 = get_alu_src(ctx, instr->src[1]);
1421       if (dst.size() == 1) {
1422          if (src1.type() == RegType::vgpr || src0.type() != RegType::vgpr)
1423             emit_vop2_instruction(ctx, instr, aco_opcode::v_sub_f32, dst, false);
1424          else
1425             emit_vop2_instruction(ctx, instr, aco_opcode::v_subrev_f32, dst, true);
1426       } else if (dst.size() == 2) {
1427          Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst),
1428                                      get_alu_src(ctx, instr->src[0]),
1429                                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1430          VOP3A_instruction* sub = static_cast<VOP3A_instruction*>(add);
1431          sub->neg[1] = true;
1432       } else {
1433          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1434          nir_print_instr(&instr->instr, stderr);
1435          fprintf(stderr, "\n");
1436       }
1437       break;
1438    }
1439    case nir_op_fmax: {
1440       if (dst.size() == 1) {
1441          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_f32, dst, true, false, ctx->block->fp_mode.must_flush_denorms32);
1442       } else if (dst.size() == 2) {
1443          if (ctx->block->fp_mode.must_flush_denorms16_64 && ctx->program->chip_class < GFX9) {
1444             Temp tmp = bld.vop3(aco_opcode::v_max_f64, bld.def(v2),
1445                                 get_alu_src(ctx, instr->src[0]),
1446                                 as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1447             bld.vop3(aco_opcode::v_mul_f64, Definition(dst), Operand(0x3FF0000000000000lu), tmp);
1448          } else {
1449             bld.vop3(aco_opcode::v_max_f64, Definition(dst),
1450                      get_alu_src(ctx, instr->src[0]),
1451                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1452          }
1453       } else {
1454          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1455          nir_print_instr(&instr->instr, stderr);
1456          fprintf(stderr, "\n");
1457       }
1458       break;
1459    }
1460    case nir_op_fmin: {
1461       if (dst.size() == 1) {
1462          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_f32, dst, true, false, ctx->block->fp_mode.must_flush_denorms32);
1463       } else if (dst.size() == 2) {
1464          if (ctx->block->fp_mode.must_flush_denorms16_64 && ctx->program->chip_class < GFX9) {
1465             Temp tmp = bld.vop3(aco_opcode::v_min_f64, bld.def(v2),
1466                                 get_alu_src(ctx, instr->src[0]),
1467                                 as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1468             bld.vop3(aco_opcode::v_mul_f64, Definition(dst), Operand(0x3FF0000000000000lu), tmp);
1469          } else {
1470             bld.vop3(aco_opcode::v_min_f64, Definition(dst),
1471                      get_alu_src(ctx, instr->src[0]),
1472                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1473          }
1474       } else {
1475          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1476          nir_print_instr(&instr->instr, stderr);
1477          fprintf(stderr, "\n");
1478       }
1479       break;
1480    }
1481    case nir_op_fmax3: {
1482       if (dst.size() == 1) {
1483          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_f32, dst, ctx->block->fp_mode.must_flush_denorms32);
1484       } else {
1485          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1486          nir_print_instr(&instr->instr, stderr);
1487          fprintf(stderr, "\n");
1488       }
1489       break;
1490    }
1491    case nir_op_fmin3: {
1492       if (dst.size() == 1) {
1493          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_f32, dst, ctx->block->fp_mode.must_flush_denorms32);
1494       } else {
1495          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1496          nir_print_instr(&instr->instr, stderr);
1497          fprintf(stderr, "\n");
1498       }
1499       break;
1500    }
1501    case nir_op_fmed3: {
1502       if (dst.size() == 1) {
1503          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_f32, dst, ctx->block->fp_mode.must_flush_denorms32);
1504       } else {
1505          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1506          nir_print_instr(&instr->instr, stderr);
1507          fprintf(stderr, "\n");
1508       }
1509       break;
1510    }
1511    case nir_op_umax3: {
1512       if (dst.size() == 1) {
1513          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_u32, dst);
1514       } else {
1515          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1516          nir_print_instr(&instr->instr, stderr);
1517          fprintf(stderr, "\n");
1518       }
1519       break;
1520    }
1521    case nir_op_umin3: {
1522       if (dst.size() == 1) {
1523          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_u32, dst);
1524       } else {
1525          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1526          nir_print_instr(&instr->instr, stderr);
1527          fprintf(stderr, "\n");
1528       }
1529       break;
1530    }
1531    case nir_op_umed3: {
1532       if (dst.size() == 1) {
1533          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_u32, dst);
1534       } else {
1535          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1536          nir_print_instr(&instr->instr, stderr);
1537          fprintf(stderr, "\n");
1538       }
1539       break;
1540    }
1541    case nir_op_imax3: {
1542       if (dst.size() == 1) {
1543          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_i32, dst);
1544       } else {
1545          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1546          nir_print_instr(&instr->instr, stderr);
1547          fprintf(stderr, "\n");
1548       }
1549       break;
1550    }
1551    case nir_op_imin3: {
1552       if (dst.size() == 1) {
1553          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_i32, dst);
1554       } else {
1555          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1556          nir_print_instr(&instr->instr, stderr);
1557          fprintf(stderr, "\n");
1558       }
1559       break;
1560    }
1561    case nir_op_imed3: {
1562       if (dst.size() == 1) {
1563          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_i32, dst);
1564       } else {
1565          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1566          nir_print_instr(&instr->instr, stderr);
1567          fprintf(stderr, "\n");
1568       }
1569       break;
1570    }
1571    case nir_op_cube_face_coord: {
1572       Temp in = get_alu_src(ctx, instr->src[0], 3);
1573       Temp src[3] = { emit_extract_vector(ctx, in, 0, v1),
1574                       emit_extract_vector(ctx, in, 1, v1),
1575                       emit_extract_vector(ctx, in, 2, v1) };
1576       Temp ma = bld.vop3(aco_opcode::v_cubema_f32, bld.def(v1), src[0], src[1], src[2]);
1577       ma = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), ma);
1578       Temp sc = bld.vop3(aco_opcode::v_cubesc_f32, bld.def(v1), src[0], src[1], src[2]);
1579       Temp tc = bld.vop3(aco_opcode::v_cubetc_f32, bld.def(v1), src[0], src[1], src[2]);
1580       sc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), sc, ma, Operand(0x3f000000u/*0.5*/));
1581       tc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), tc, ma, Operand(0x3f000000u/*0.5*/));
1582       bld.pseudo(aco_opcode::p_create_vector, Definition(dst), sc, tc);
1583       break;
1584    }
1585    case nir_op_cube_face_index: {
1586       Temp in = get_alu_src(ctx, instr->src[0], 3);
1587       Temp src[3] = { emit_extract_vector(ctx, in, 0, v1),
1588                       emit_extract_vector(ctx, in, 1, v1),
1589                       emit_extract_vector(ctx, in, 2, v1) };
1590       bld.vop3(aco_opcode::v_cubeid_f32, Definition(dst), src[0], src[1], src[2]);
1591       break;
1592    }
1593    case nir_op_bcsel: {
1594       emit_bcsel(ctx, instr, dst);
1595       break;
1596    }
1597    case nir_op_frsq: {
1598       if (dst.size() == 1) {
1599          emit_rsq(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1600       } else if (dst.size() == 2) {
1601          emit_vop1_instruction(ctx, instr, aco_opcode::v_rsq_f64, dst);
1602       } else {
1603          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1604          nir_print_instr(&instr->instr, stderr);
1605          fprintf(stderr, "\n");
1606       }
1607       break;
1608    }
1609    case nir_op_fneg: {
1610       Temp src = get_alu_src(ctx, instr->src[0]);
1611       if (dst.size() == 1) {
1612          if (ctx->block->fp_mode.must_flush_denorms32)
1613             src = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x3f800000u), as_vgpr(ctx, src));
1614          bld.vop2(aco_opcode::v_xor_b32, Definition(dst), Operand(0x80000000u), as_vgpr(ctx, src));
1615       } else if (dst.size() == 2) {
1616          if (ctx->block->fp_mode.must_flush_denorms16_64)
1617             src = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), Operand(0x3FF0000000000000lu), as_vgpr(ctx, src));
1618          Temp upper = bld.tmp(v1), lower = bld.tmp(v1);
1619          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1620          upper = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), Operand(0x80000000u), upper);
1621          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1622       } else {
1623          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1624          nir_print_instr(&instr->instr, stderr);
1625          fprintf(stderr, "\n");
1626       }
1627       break;
1628    }
1629    case nir_op_fabs: {
1630       Temp src = get_alu_src(ctx, instr->src[0]);
1631       if (dst.size() == 1) {
1632          if (ctx->block->fp_mode.must_flush_denorms32)
1633             src = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x3f800000u), as_vgpr(ctx, src));
1634          bld.vop2(aco_opcode::v_and_b32, Definition(dst), Operand(0x7FFFFFFFu), as_vgpr(ctx, src));
1635       } else if (dst.size() == 2) {
1636          if (ctx->block->fp_mode.must_flush_denorms16_64)
1637             src = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), Operand(0x3FF0000000000000lu), as_vgpr(ctx, src));
1638          Temp upper = bld.tmp(v1), lower = bld.tmp(v1);
1639          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1640          upper = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7FFFFFFFu), upper);
1641          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1642       } else {
1643          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1644          nir_print_instr(&instr->instr, stderr);
1645          fprintf(stderr, "\n");
1646       }
1647       break;
1648    }
1649    case nir_op_fsat: {
1650       Temp src = get_alu_src(ctx, instr->src[0]);
1651       if (dst.size() == 1) {
1652          bld.vop3(aco_opcode::v_med3_f32, Definition(dst), Operand(0u), Operand(0x3f800000u), src);
1653          /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1654          // TODO: confirm that this holds under any circumstances
1655       } else if (dst.size() == 2) {
1656          Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst), src, Operand(0u));
1657          VOP3A_instruction* vop3 = static_cast<VOP3A_instruction*>(add);
1658          vop3->clamp = true;
1659       } else {
1660          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1661          nir_print_instr(&instr->instr, stderr);
1662          fprintf(stderr, "\n");
1663       }
1664       break;
1665    }
1666    case nir_op_flog2: {
1667       if (dst.size() == 1) {
1668          emit_log2(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1669       } else {
1670          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1671          nir_print_instr(&instr->instr, stderr);
1672          fprintf(stderr, "\n");
1673       }
1674       break;
1675    }
1676    case nir_op_frcp: {
1677       if (dst.size() == 1) {
1678          emit_rcp(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1679       } else if (dst.size() == 2) {
1680          emit_vop1_instruction(ctx, instr, aco_opcode::v_rcp_f64, dst);
1681       } else {
1682          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1683          nir_print_instr(&instr->instr, stderr);
1684          fprintf(stderr, "\n");
1685       }
1686       break;
1687    }
1688    case nir_op_fexp2: {
1689       if (dst.size() == 1) {
1690          emit_vop1_instruction(ctx, instr, aco_opcode::v_exp_f32, dst);
1691       } else {
1692          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1693          nir_print_instr(&instr->instr, stderr);
1694          fprintf(stderr, "\n");
1695       }
1696       break;
1697    }
1698    case nir_op_fsqrt: {
1699       if (dst.size() == 1) {
1700          emit_sqrt(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1701       } else if (dst.size() == 2) {
1702          emit_vop1_instruction(ctx, instr, aco_opcode::v_sqrt_f64, dst);
1703       } else {
1704          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1705          nir_print_instr(&instr->instr, stderr);
1706          fprintf(stderr, "\n");
1707       }
1708       break;
1709    }
1710    case nir_op_ffract: {
1711       if (dst.size() == 1) {
1712          emit_vop1_instruction(ctx, instr, aco_opcode::v_fract_f32, dst);
1713       } else if (dst.size() == 2) {
1714          emit_vop1_instruction(ctx, instr, aco_opcode::v_fract_f64, dst);
1715       } else {
1716          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1717          nir_print_instr(&instr->instr, stderr);
1718          fprintf(stderr, "\n");
1719       }
1720       break;
1721    }
1722    case nir_op_ffloor: {
1723       if (dst.size() == 1) {
1724          emit_vop1_instruction(ctx, instr, aco_opcode::v_floor_f32, dst);
1725       } else if (dst.size() == 2) {
1726          emit_floor_f64(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1727       } else {
1728          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1729          nir_print_instr(&instr->instr, stderr);
1730          fprintf(stderr, "\n");
1731       }
1732       break;
1733    }
1734    case nir_op_fceil: {
1735       if (dst.size() == 1) {
1736          emit_vop1_instruction(ctx, instr, aco_opcode::v_ceil_f32, dst);
1737       } else if (dst.size() == 2) {
1738          if (ctx->options->chip_class >= GFX7) {
1739             emit_vop1_instruction(ctx, instr, aco_opcode::v_ceil_f64, dst);
1740          } else {
1741             /* GFX6 doesn't support V_CEIL_F64, lower it. */
1742             Temp src0 = get_alu_src(ctx, instr->src[0]);
1743
1744             /* trunc = trunc(src0)
1745              * if (src0 > 0.0 && src0 != trunc)
1746              *    trunc += 1.0
1747              */
1748             Temp trunc = emit_trunc_f64(ctx, bld, bld.def(v2), src0);
1749             Temp tmp0 = bld.vopc_e64(aco_opcode::v_cmp_gt_f64, bld.def(bld.lm), src0, Operand(0u));
1750             Temp tmp1 = bld.vopc(aco_opcode::v_cmp_lg_f64, bld.hint_vcc(bld.def(bld.lm)), src0, trunc);
1751             Temp cond = bld.sop2(aco_opcode::s_and_b64, bld.hint_vcc(bld.def(s2)), bld.def(s1, scc), tmp0, tmp1);
1752             Temp add = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), bld.copy(bld.def(v1), Operand(0u)), bld.copy(bld.def(v1), Operand(0x3ff00000u)), cond);
1753             add = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), bld.copy(bld.def(v1), Operand(0u)), add);
1754             bld.vop3(aco_opcode::v_add_f64, Definition(dst), trunc, add);
1755          }
1756       } else {
1757          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1758          nir_print_instr(&instr->instr, stderr);
1759          fprintf(stderr, "\n");
1760       }
1761       break;
1762    }
1763    case nir_op_ftrunc: {
1764       if (dst.size() == 1) {
1765          emit_vop1_instruction(ctx, instr, aco_opcode::v_trunc_f32, dst);
1766       } else if (dst.size() == 2) {
1767          emit_trunc_f64(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1768       } else {
1769          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1770          nir_print_instr(&instr->instr, stderr);
1771          fprintf(stderr, "\n");
1772       }
1773       break;
1774    }
1775    case nir_op_fround_even: {
1776       if (dst.size() == 1) {
1777          emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f32, dst);
1778       } else if (dst.size() == 2) {
1779          if (ctx->options->chip_class >= GFX7) {
1780             emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f64, dst);
1781          } else {
1782             /* GFX6 doesn't support V_RNDNE_F64, lower it. */
1783             Temp src0 = get_alu_src(ctx, instr->src[0]);
1784
1785             Temp src0_lo = bld.tmp(v1), src0_hi = bld.tmp(v1);
1786             bld.pseudo(aco_opcode::p_split_vector, Definition(src0_lo), Definition(src0_hi), src0);
1787
1788             Temp bitmask = bld.sop1(aco_opcode::s_brev_b32, bld.def(s1), bld.copy(bld.def(s1), Operand(-2u)));
1789             Temp bfi = bld.vop3(aco_opcode::v_bfi_b32, bld.def(v1), bitmask, bld.copy(bld.def(v1), Operand(0x43300000u)), as_vgpr(ctx, src0_hi));
1790             Temp tmp = bld.vop3(aco_opcode::v_add_f64, bld.def(v2), src0, bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), bfi));
1791             Instruction *sub = bld.vop3(aco_opcode::v_add_f64, bld.def(v2), tmp, bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), bfi));
1792             static_cast<VOP3A_instruction*>(sub)->neg[1] = true;
1793             tmp = sub->definitions[0].getTemp();
1794
1795             Temp v = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(-1u), Operand(0x432fffffu));
1796             Instruction* vop3 = bld.vopc_e64(aco_opcode::v_cmp_gt_f64, bld.hint_vcc(bld.def(bld.lm)), src0, v);
1797             static_cast<VOP3A_instruction*>(vop3)->abs[0] = true;
1798             Temp cond = vop3->definitions[0].getTemp();
1799
1800             Temp tmp_lo = bld.tmp(v1), tmp_hi = bld.tmp(v1);
1801             bld.pseudo(aco_opcode::p_split_vector, Definition(tmp_lo), Definition(tmp_hi), tmp);
1802             Temp dst0 = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), tmp_lo, as_vgpr(ctx, src0_lo), cond);
1803             Temp dst1 = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), tmp_hi, as_vgpr(ctx, src0_hi), cond);
1804
1805             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1806          }
1807       } else {
1808          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1809          nir_print_instr(&instr->instr, stderr);
1810          fprintf(stderr, "\n");
1811       }
1812       break;
1813    }
1814    case nir_op_fsin:
1815    case nir_op_fcos: {
1816       Temp src = get_alu_src(ctx, instr->src[0]);
1817       aco_ptr<Instruction> norm;
1818       if (dst.size() == 1) {
1819          Temp half_pi = bld.copy(bld.def(s1), Operand(0x3e22f983u));
1820          Temp tmp = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), half_pi, as_vgpr(ctx, src));
1821
1822          /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
1823          if (ctx->options->chip_class < GFX9)
1824             tmp = bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), tmp);
1825
1826          aco_opcode opcode = instr->op == nir_op_fsin ? aco_opcode::v_sin_f32 : aco_opcode::v_cos_f32;
1827          bld.vop1(opcode, Definition(dst), tmp);
1828       } else {
1829          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1830          nir_print_instr(&instr->instr, stderr);
1831          fprintf(stderr, "\n");
1832       }
1833       break;
1834    }
1835    case nir_op_ldexp: {
1836       if (dst.size() == 1) {
1837          bld.vop3(aco_opcode::v_ldexp_f32, Definition(dst),
1838                   as_vgpr(ctx, get_alu_src(ctx, instr->src[0])),
1839                   get_alu_src(ctx, instr->src[1]));
1840       } else if (dst.size() == 2) {
1841          bld.vop3(aco_opcode::v_ldexp_f64, Definition(dst),
1842                   as_vgpr(ctx, get_alu_src(ctx, instr->src[0])),
1843                   get_alu_src(ctx, instr->src[1]));
1844       } else {
1845          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1846          nir_print_instr(&instr->instr, stderr);
1847          fprintf(stderr, "\n");
1848       }
1849       break;
1850    }
1851    case nir_op_frexp_sig: {
1852       if (dst.size() == 1) {
1853          bld.vop1(aco_opcode::v_frexp_mant_f32, Definition(dst),
1854                   get_alu_src(ctx, instr->src[0]));
1855       } else if (dst.size() == 2) {
1856          bld.vop1(aco_opcode::v_frexp_mant_f64, Definition(dst),
1857                   get_alu_src(ctx, instr->src[0]));
1858       } else {
1859          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1860          nir_print_instr(&instr->instr, stderr);
1861          fprintf(stderr, "\n");
1862       }
1863       break;
1864    }
1865    case nir_op_frexp_exp: {
1866       if (instr->src[0].src.ssa->bit_size == 32) {
1867          bld.vop1(aco_opcode::v_frexp_exp_i32_f32, Definition(dst),
1868                   get_alu_src(ctx, instr->src[0]));
1869       } else if (instr->src[0].src.ssa->bit_size == 64) {
1870          bld.vop1(aco_opcode::v_frexp_exp_i32_f64, Definition(dst),
1871                   get_alu_src(ctx, instr->src[0]));
1872       } else {
1873          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1874          nir_print_instr(&instr->instr, stderr);
1875          fprintf(stderr, "\n");
1876       }
1877       break;
1878    }
1879    case nir_op_fsign: {
1880       Temp src = as_vgpr(ctx, get_alu_src(ctx, instr->src[0]));
1881       if (dst.size() == 1) {
1882          Temp cond = bld.vopc(aco_opcode::v_cmp_nlt_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1883          src = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0x3f800000u), src, cond);
1884          cond = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1885          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0xbf800000u), src, cond);
1886       } else if (dst.size() == 2) {
1887          Temp cond = bld.vopc(aco_opcode::v_cmp_nlt_f64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1888          Temp tmp = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0x3FF00000u));
1889          Temp upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), tmp, emit_extract_vector(ctx, src, 1, v1), cond);
1890
1891          cond = bld.vopc(aco_opcode::v_cmp_le_f64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1892          tmp = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0xBFF00000u));
1893          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), tmp, upper, cond);
1894
1895          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), Operand(0u), upper);
1896       } else {
1897          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1898          nir_print_instr(&instr->instr, stderr);
1899          fprintf(stderr, "\n");
1900       }
1901       break;
1902    }
1903    case nir_op_f2f32: {
1904       if (instr->src[0].src.ssa->bit_size == 64) {
1905          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_f64, dst);
1906       } else {
1907          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1908          nir_print_instr(&instr->instr, stderr);
1909          fprintf(stderr, "\n");
1910       }
1911       break;
1912    }
1913    case nir_op_f2f64: {
1914       if (instr->src[0].src.ssa->bit_size == 32) {
1915          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_f32, dst);
1916       } else {
1917          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1918          nir_print_instr(&instr->instr, stderr);
1919          fprintf(stderr, "\n");
1920       }
1921       break;
1922    }
1923    case nir_op_i2f32: {
1924       assert(dst.size() == 1);
1925       emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_i32, dst);
1926       break;
1927    }
1928    case nir_op_i2f64: {
1929       if (instr->src[0].src.ssa->bit_size == 32) {
1930          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_i32, dst);
1931       } else if (instr->src[0].src.ssa->bit_size == 64) {
1932          Temp src = get_alu_src(ctx, instr->src[0]);
1933          RegClass rc = RegClass(src.type(), 1);
1934          Temp lower = bld.tmp(rc), upper = bld.tmp(rc);
1935          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1936          lower = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), lower);
1937          upper = bld.vop1(aco_opcode::v_cvt_f64_i32, bld.def(v2), upper);
1938          upper = bld.vop3(aco_opcode::v_ldexp_f64, bld.def(v2), upper, Operand(32u));
1939          bld.vop3(aco_opcode::v_add_f64, Definition(dst), lower, upper);
1940
1941       } else {
1942          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1943          nir_print_instr(&instr->instr, stderr);
1944          fprintf(stderr, "\n");
1945       }
1946       break;
1947    }
1948    case nir_op_u2f32: {
1949       assert(dst.size() == 1);
1950       emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_u32, dst);
1951       break;
1952    }
1953    case nir_op_u2f64: {
1954       if (instr->src[0].src.ssa->bit_size == 32) {
1955          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_u32, dst);
1956       } else if (instr->src[0].src.ssa->bit_size == 64) {
1957          Temp src = get_alu_src(ctx, instr->src[0]);
1958          RegClass rc = RegClass(src.type(), 1);
1959          Temp lower = bld.tmp(rc), upper = bld.tmp(rc);
1960          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1961          lower = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), lower);
1962          upper = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), upper);
1963          upper = bld.vop3(aco_opcode::v_ldexp_f64, bld.def(v2), upper, Operand(32u));
1964          bld.vop3(aco_opcode::v_add_f64, Definition(dst), lower, upper);
1965       } else {
1966          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1967          nir_print_instr(&instr->instr, stderr);
1968          fprintf(stderr, "\n");
1969       }
1970       break;
1971    }
1972    case nir_op_f2i32: {
1973       Temp src = get_alu_src(ctx, instr->src[0]);
1974       if (instr->src[0].src.ssa->bit_size == 32) {
1975          if (dst.type() == RegType::vgpr)
1976             bld.vop1(aco_opcode::v_cvt_i32_f32, Definition(dst), src);
1977          else
1978             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1979                        bld.vop1(aco_opcode::v_cvt_i32_f32, bld.def(v1), src));
1980
1981       } else if (instr->src[0].src.ssa->bit_size == 64) {
1982          if (dst.type() == RegType::vgpr)
1983             bld.vop1(aco_opcode::v_cvt_i32_f64, Definition(dst), src);
1984          else
1985             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1986                        bld.vop1(aco_opcode::v_cvt_i32_f64, bld.def(v1), src));
1987
1988       } else {
1989          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1990          nir_print_instr(&instr->instr, stderr);
1991          fprintf(stderr, "\n");
1992       }
1993       break;
1994    }
1995    case nir_op_f2u32: {
1996       Temp src = get_alu_src(ctx, instr->src[0]);
1997       if (instr->src[0].src.ssa->bit_size == 32) {
1998          if (dst.type() == RegType::vgpr)
1999             bld.vop1(aco_opcode::v_cvt_u32_f32, Definition(dst), src);
2000          else
2001             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
2002                        bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), src));
2003
2004       } else if (instr->src[0].src.ssa->bit_size == 64) {
2005          if (dst.type() == RegType::vgpr)
2006             bld.vop1(aco_opcode::v_cvt_u32_f64, Definition(dst), src);
2007          else
2008             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
2009                        bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), src));
2010
2011       } else {
2012          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2013          nir_print_instr(&instr->instr, stderr);
2014          fprintf(stderr, "\n");
2015       }
2016       break;
2017    }
2018    case nir_op_f2i64: {
2019       Temp src = get_alu_src(ctx, instr->src[0]);
2020       if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::vgpr) {
2021          Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f32, bld.def(v1), src);
2022          exponent = bld.vop3(aco_opcode::v_med3_i32, bld.def(v1), Operand(0x0u), exponent, Operand(64u));
2023          Temp mantissa = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffu), src);
2024          Temp sign = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
2025          mantissa = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(0x800000u), mantissa);
2026          mantissa = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(7u), mantissa);
2027          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), mantissa);
2028          Temp new_exponent = bld.tmp(v1);
2029          Temp borrow = bld.vsub32(Definition(new_exponent), Operand(63u), exponent, true).def(1).getTemp();
2030          if (ctx->program->chip_class >= GFX8)
2031             mantissa = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), new_exponent, mantissa);
2032          else
2033             mantissa = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), mantissa, new_exponent);
2034          Temp saturate = bld.vop1(aco_opcode::v_bfrev_b32, bld.def(v1), Operand(0xfffffffeu));
2035          Temp lower = bld.tmp(v1), upper = bld.tmp(v1);
2036          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2037          lower = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), lower, Operand(0xffffffffu), borrow);
2038          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), upper, saturate, borrow);
2039          lower = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), sign, lower);
2040          upper = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), sign, upper);
2041          Temp new_lower = bld.tmp(v1);
2042          borrow = bld.vsub32(Definition(new_lower), lower, sign, true).def(1).getTemp();
2043          Temp new_upper = bld.vsub32(bld.def(v1), upper, sign, false, borrow);
2044          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), new_lower, new_upper);
2045
2046       } else if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::sgpr) {
2047          if (src.type() == RegType::vgpr)
2048             src = bld.as_uniform(src);
2049          Temp exponent = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), src, Operand(0x80017u));
2050          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(126u));
2051          exponent = bld.sop2(aco_opcode::s_max_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), exponent);
2052          exponent = bld.sop2(aco_opcode::s_min_u32, bld.def(s1), bld.def(s1, scc), Operand(64u), exponent);
2053          Temp mantissa = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0x7fffffu), src);
2054          Temp sign = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
2055          mantissa = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(0x800000u), mantissa);
2056          mantissa = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), mantissa, Operand(7u));
2057          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), mantissa);
2058          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), Operand(63u), exponent);
2059          mantissa = bld.sop2(aco_opcode::s_lshr_b64, bld.def(s2), bld.def(s1, scc), mantissa, exponent);
2060          Temp cond = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), exponent, Operand(0xffffffffu)); // exp >= 64
2061          Temp saturate = bld.sop1(aco_opcode::s_brev_b64, bld.def(s2), Operand(0xfffffffeu));
2062          mantissa = bld.sop2(aco_opcode::s_cselect_b64, bld.def(s2), saturate, mantissa, cond);
2063          Temp lower = bld.tmp(s1), upper = bld.tmp(s1);
2064          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2065          lower = bld.sop2(aco_opcode::s_xor_b32, bld.def(s1), bld.def(s1, scc), sign, lower);
2066          upper = bld.sop2(aco_opcode::s_xor_b32, bld.def(s1), bld.def(s1, scc), sign, upper);
2067          Temp borrow = bld.tmp(s1);
2068          lower = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(borrow)), lower, sign);
2069          upper = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), upper, sign, borrow);
2070          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2071
2072       } else if (instr->src[0].src.ssa->bit_size == 64) {
2073          Temp vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0x3df00000u));
2074          Temp trunc = emit_trunc_f64(ctx, bld, bld.def(v2), src);
2075          Temp mul = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), trunc, vec);
2076          vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0xc1f00000u));
2077          Temp floor = emit_floor_f64(ctx, bld, bld.def(v2), mul);
2078          Temp fma = bld.vop3(aco_opcode::v_fma_f64, bld.def(v2), floor, vec, trunc);
2079          Temp lower = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), fma);
2080          Temp upper = bld.vop1(aco_opcode::v_cvt_i32_f64, bld.def(v1), floor);
2081          if (dst.type() == RegType::sgpr) {
2082             lower = bld.as_uniform(lower);
2083             upper = bld.as_uniform(upper);
2084          }
2085          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2086
2087       } else {
2088          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2089          nir_print_instr(&instr->instr, stderr);
2090          fprintf(stderr, "\n");
2091       }
2092       break;
2093    }
2094    case nir_op_f2u64: {
2095       Temp src = get_alu_src(ctx, instr->src[0]);
2096       if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::vgpr) {
2097          Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f32, bld.def(v1), src);
2098          Temp exponent_in_range = bld.vopc(aco_opcode::v_cmp_ge_i32, bld.hint_vcc(bld.def(bld.lm)), Operand(64u), exponent);
2099          exponent = bld.vop2(aco_opcode::v_max_i32, bld.def(v1), Operand(0x0u), exponent);
2100          Temp mantissa = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffu), src);
2101          mantissa = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(0x800000u), mantissa);
2102          Temp exponent_small = bld.vsub32(bld.def(v1), Operand(24u), exponent);
2103          Temp small = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), exponent_small, mantissa);
2104          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), mantissa);
2105          Temp new_exponent = bld.tmp(v1);
2106          Temp cond_small = bld.vsub32(Definition(new_exponent), exponent, Operand(24u), true).def(1).getTemp();
2107          if (ctx->program->chip_class >= GFX8)
2108             mantissa = bld.vop3(aco_opcode::v_lshlrev_b64, bld.def(v2), new_exponent, mantissa);
2109          else
2110             mantissa = bld.vop3(aco_opcode::v_lshl_b64, bld.def(v2), mantissa, new_exponent);
2111          Temp lower = bld.tmp(v1), upper = bld.tmp(v1);
2112          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2113          lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), lower, small, cond_small);
2114          upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), upper, Operand(0u), cond_small);
2115          lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xffffffffu), lower, exponent_in_range);
2116          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xffffffffu), upper, exponent_in_range);
2117          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2118
2119       } else if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::sgpr) {
2120          if (src.type() == RegType::vgpr)
2121             src = bld.as_uniform(src);
2122          Temp exponent = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), src, Operand(0x80017u));
2123          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(126u));
2124          exponent = bld.sop2(aco_opcode::s_max_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), exponent);
2125          Temp mantissa = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0x7fffffu), src);
2126          mantissa = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(0x800000u), mantissa);
2127          Temp exponent_small = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), Operand(24u), exponent);
2128          Temp small = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), mantissa, exponent_small);
2129          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), mantissa);
2130          Temp exponent_large = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(24u));
2131          mantissa = bld.sop2(aco_opcode::s_lshl_b64, bld.def(s2), bld.def(s1, scc), mantissa, exponent_large);
2132          Temp cond = bld.sopc(aco_opcode::s_cmp_ge_i32, bld.def(s1, scc), Operand(64u), exponent);
2133          mantissa = bld.sop2(aco_opcode::s_cselect_b64, bld.def(s2), mantissa, Operand(0xffffffffu), cond);
2134          Temp lower = bld.tmp(s1), upper = bld.tmp(s1);
2135          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2136          Temp cond_small = bld.sopc(aco_opcode::s_cmp_le_i32, bld.def(s1, scc), exponent, Operand(24u));
2137          lower = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), small, lower, cond_small);
2138          upper = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), Operand(0u), upper, cond_small);
2139          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2140
2141       } else if (instr->src[0].src.ssa->bit_size == 64) {
2142          Temp vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0x3df00000u));
2143          Temp trunc = emit_trunc_f64(ctx, bld, bld.def(v2), src);
2144          Temp mul = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), trunc, vec);
2145          vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0xc1f00000u));
2146          Temp floor = emit_floor_f64(ctx, bld, bld.def(v2), mul);
2147          Temp fma = bld.vop3(aco_opcode::v_fma_f64, bld.def(v2), floor, vec, trunc);
2148          Temp lower = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), fma);
2149          Temp upper = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), floor);
2150          if (dst.type() == RegType::sgpr) {
2151             lower = bld.as_uniform(lower);
2152             upper = bld.as_uniform(upper);
2153          }
2154          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2155
2156       } else {
2157          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2158          nir_print_instr(&instr->instr, stderr);
2159          fprintf(stderr, "\n");
2160       }
2161       break;
2162    }
2163    case nir_op_b2f32: {
2164       Temp src = get_alu_src(ctx, instr->src[0]);
2165       assert(src.regClass() == bld.lm);
2166
2167       if (dst.regClass() == s1) {
2168          src = bool_to_scalar_condition(ctx, src);
2169          bld.sop2(aco_opcode::s_mul_i32, Definition(dst), Operand(0x3f800000u), src);
2170       } else if (dst.regClass() == v1) {
2171          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(0x3f800000u), src);
2172       } else {
2173          unreachable("Wrong destination register class for nir_op_b2f32.");
2174       }
2175       break;
2176    }
2177    case nir_op_b2f64: {
2178       Temp src = get_alu_src(ctx, instr->src[0]);
2179       assert(src.regClass() == bld.lm);
2180
2181       if (dst.regClass() == s2) {
2182          src = bool_to_scalar_condition(ctx, src);
2183          bld.sop2(aco_opcode::s_cselect_b64, Definition(dst), Operand(0x3f800000u), Operand(0u), bld.scc(src));
2184       } else if (dst.regClass() == v2) {
2185          Temp one = bld.vop1(aco_opcode::v_mov_b32, bld.def(v2), Operand(0x3FF00000u));
2186          Temp upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), one, src);
2187          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), Operand(0u), upper);
2188       } else {
2189          unreachable("Wrong destination register class for nir_op_b2f64.");
2190       }
2191       break;
2192    }
2193    case nir_op_i2i32: {
2194       Temp src = get_alu_src(ctx, instr->src[0]);
2195       if (instr->src[0].src.ssa->bit_size == 64) {
2196          /* we can actually just say dst = src, as it would map the lower register */
2197          emit_extract_vector(ctx, src, 0, dst);
2198       } else {
2199          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2200          nir_print_instr(&instr->instr, stderr);
2201          fprintf(stderr, "\n");
2202       }
2203       break;
2204    }
2205    case nir_op_u2u32: {
2206       Temp src = get_alu_src(ctx, instr->src[0]);
2207       if (instr->src[0].src.ssa->bit_size == 16) {
2208          if (dst.regClass() == s1) {
2209             bld.sop2(aco_opcode::s_and_b32, Definition(dst), bld.def(s1, scc), Operand(0xFFFFu), src);
2210          } else {
2211             // TODO: do better with SDWA
2212             bld.vop2(aco_opcode::v_and_b32, Definition(dst), Operand(0xFFFFu), src);
2213          }
2214       } else if (instr->src[0].src.ssa->bit_size == 64) {
2215          /* we can actually just say dst = src, as it would map the lower register */
2216          emit_extract_vector(ctx, src, 0, dst);
2217       } else {
2218          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2219          nir_print_instr(&instr->instr, stderr);
2220          fprintf(stderr, "\n");
2221       }
2222       break;
2223    }
2224    case nir_op_i2i64: {
2225       Temp src = get_alu_src(ctx, instr->src[0]);
2226       if (src.regClass() == s1) {
2227          Temp high = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
2228          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, high);
2229       } else if (src.regClass() == v1) {
2230          Temp high = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
2231          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, high);
2232       } else {
2233          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2234          nir_print_instr(&instr->instr, stderr);
2235          fprintf(stderr, "\n");
2236       }
2237       break;
2238    }
2239    case nir_op_u2u64: {
2240       Temp src = get_alu_src(ctx, instr->src[0]);
2241       if (instr->src[0].src.ssa->bit_size == 32) {
2242          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, Operand(0u));
2243       } else {
2244          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2245          nir_print_instr(&instr->instr, stderr);
2246          fprintf(stderr, "\n");
2247       }
2248       break;
2249    }
2250    case nir_op_b2i32: {
2251       Temp src = get_alu_src(ctx, instr->src[0]);
2252       assert(src.regClass() == bld.lm);
2253
2254       if (dst.regClass() == s1) {
2255          // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2256          bool_to_scalar_condition(ctx, src, dst);
2257       } else if (dst.regClass() == v1) {
2258          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), src);
2259       } else {
2260          unreachable("Invalid register class for b2i32");
2261       }
2262       break;
2263    }
2264    case nir_op_i2b1: {
2265       Temp src = get_alu_src(ctx, instr->src[0]);
2266       assert(dst.regClass() == bld.lm);
2267
2268       if (src.type() == RegType::vgpr) {
2269          assert(src.regClass() == v1 || src.regClass() == v2);
2270          assert(dst.regClass() == bld.lm);
2271          bld.vopc(src.size() == 2 ? aco_opcode::v_cmp_lg_u64 : aco_opcode::v_cmp_lg_u32,
2272                   Definition(dst), Operand(0u), src).def(0).setHint(vcc);
2273       } else {
2274          assert(src.regClass() == s1 || src.regClass() == s2);
2275          Temp tmp;
2276          if (src.regClass() == s2 && ctx->program->chip_class <= GFX7) {
2277             tmp = bld.sop2(aco_opcode::s_or_b64, bld.def(s2), bld.def(s1, scc), Operand(0u), src).def(1).getTemp();
2278          } else {
2279             tmp = bld.sopc(src.size() == 2 ? aco_opcode::s_cmp_lg_u64 : aco_opcode::s_cmp_lg_u32,
2280                            bld.scc(bld.def(s1)), Operand(0u), src);
2281          }
2282          bool_to_vector_condition(ctx, tmp, dst);
2283       }
2284       break;
2285    }
2286    case nir_op_pack_64_2x32_split: {
2287       Temp src0 = get_alu_src(ctx, instr->src[0]);
2288       Temp src1 = get_alu_src(ctx, instr->src[1]);
2289
2290       bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src0, src1);
2291       break;
2292    }
2293    case nir_op_unpack_64_2x32_split_x:
2294       bld.pseudo(aco_opcode::p_split_vector, Definition(dst), bld.def(dst.regClass()), get_alu_src(ctx, instr->src[0]));
2295       break;
2296    case nir_op_unpack_64_2x32_split_y:
2297       bld.pseudo(aco_opcode::p_split_vector, bld.def(dst.regClass()), Definition(dst), get_alu_src(ctx, instr->src[0]));
2298       break;
2299    case nir_op_pack_half_2x16: {
2300       Temp src = get_alu_src(ctx, instr->src[0], 2);
2301
2302       if (dst.regClass() == v1) {
2303          Temp src0 = bld.tmp(v1);
2304          Temp src1 = bld.tmp(v1);
2305          bld.pseudo(aco_opcode::p_split_vector, Definition(src0), Definition(src1), src);
2306          if (!ctx->block->fp_mode.care_about_round32 || ctx->block->fp_mode.round32 == fp_round_tz)
2307             bld.vop3(aco_opcode::v_cvt_pkrtz_f16_f32, Definition(dst), src0, src1);
2308          else
2309             bld.vop3(aco_opcode::v_cvt_pk_u16_u32, Definition(dst),
2310                      bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src0),
2311                      bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src1));
2312       } else {
2313          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2314          nir_print_instr(&instr->instr, stderr);
2315          fprintf(stderr, "\n");
2316       }
2317       break;
2318    }
2319    case nir_op_unpack_half_2x16_split_x: {
2320       if (dst.regClass() == v1) {
2321          Builder bld(ctx->program, ctx->block);
2322          bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst), get_alu_src(ctx, instr->src[0]));
2323       } else {
2324          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2325          nir_print_instr(&instr->instr, stderr);
2326          fprintf(stderr, "\n");
2327       }
2328       break;
2329    }
2330    case nir_op_unpack_half_2x16_split_y: {
2331       if (dst.regClass() == v1) {
2332          Builder bld(ctx->program, ctx->block);
2333          /* TODO: use SDWA here */
2334          bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst),
2335                   bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(16u), as_vgpr(ctx, get_alu_src(ctx, instr->src[0]))));
2336       } else {
2337          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2338          nir_print_instr(&instr->instr, stderr);
2339          fprintf(stderr, "\n");
2340       }
2341       break;
2342    }
2343    case nir_op_fquantize2f16: {
2344       Temp src = get_alu_src(ctx, instr->src[0]);
2345       Temp f16 = bld.vop1(aco_opcode::v_cvt_f16_f32, bld.def(v1), src);
2346       Temp f32, cmp_res;
2347
2348       if (ctx->program->chip_class >= GFX8) {
2349          Temp mask = bld.copy(bld.def(s1), Operand(0x36Fu)); /* value is NOT negative/positive denormal value */
2350          cmp_res = bld.vopc_e64(aco_opcode::v_cmp_class_f16, bld.hint_vcc(bld.def(bld.lm)), f16, mask);
2351          f32 = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), f16);
2352       } else {
2353          /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2354           * so compare the result and flush to 0 if it's smaller.
2355           */
2356          f32 = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), f16);
2357          Temp smallest = bld.copy(bld.def(s1), Operand(0x38800000u));
2358          Instruction* vop3 = bld.vopc_e64(aco_opcode::v_cmp_nlt_f32, bld.hint_vcc(bld.def(bld.lm)), f32, smallest);
2359          static_cast<VOP3A_instruction*>(vop3)->abs[0] = true;
2360          cmp_res = vop3->definitions[0].getTemp();
2361       }
2362
2363       if (ctx->block->fp_mode.preserve_signed_zero_inf_nan32 || ctx->program->chip_class < GFX8) {
2364          Temp copysign_0 = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0u), as_vgpr(ctx, src));
2365          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), copysign_0, f32, cmp_res);
2366       } else {
2367          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), f32, cmp_res);
2368       }
2369       break;
2370    }
2371    case nir_op_bfm: {
2372       Temp bits = get_alu_src(ctx, instr->src[0]);
2373       Temp offset = get_alu_src(ctx, instr->src[1]);
2374
2375       if (dst.regClass() == s1) {
2376          bld.sop2(aco_opcode::s_bfm_b32, Definition(dst), bits, offset);
2377       } else if (dst.regClass() == v1) {
2378          bld.vop3(aco_opcode::v_bfm_b32, Definition(dst), bits, offset);
2379       } else {
2380          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2381          nir_print_instr(&instr->instr, stderr);
2382          fprintf(stderr, "\n");
2383       }
2384       break;
2385    }
2386    case nir_op_bitfield_select: {
2387       /* (mask & insert) | (~mask & base) */
2388       Temp bitmask = get_alu_src(ctx, instr->src[0]);
2389       Temp insert = get_alu_src(ctx, instr->src[1]);
2390       Temp base = get_alu_src(ctx, instr->src[2]);
2391
2392       /* dst = (insert & bitmask) | (base & ~bitmask) */
2393       if (dst.regClass() == s1) {
2394          aco_ptr<Instruction> sop2;
2395          nir_const_value* const_bitmask = nir_src_as_const_value(instr->src[0].src);
2396          nir_const_value* const_insert = nir_src_as_const_value(instr->src[1].src);
2397          Operand lhs;
2398          if (const_insert && const_bitmask) {
2399             lhs = Operand(const_insert->u32 & const_bitmask->u32);
2400          } else {
2401             insert = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), insert, bitmask);
2402             lhs = Operand(insert);
2403          }
2404
2405          Operand rhs;
2406          nir_const_value* const_base = nir_src_as_const_value(instr->src[2].src);
2407          if (const_base && const_bitmask) {
2408             rhs = Operand(const_base->u32 & ~const_bitmask->u32);
2409          } else {
2410             base = bld.sop2(aco_opcode::s_andn2_b32, bld.def(s1), bld.def(s1, scc), base, bitmask);
2411             rhs = Operand(base);
2412          }
2413
2414          bld.sop2(aco_opcode::s_or_b32, Definition(dst), bld.def(s1, scc), rhs, lhs);
2415
2416       } else if (dst.regClass() == v1) {
2417          if (base.type() == RegType::sgpr && (bitmask.type() == RegType::sgpr || (insert.type() == RegType::sgpr)))
2418             base = as_vgpr(ctx, base);
2419          if (insert.type() == RegType::sgpr && bitmask.type() == RegType::sgpr)
2420             insert = as_vgpr(ctx, insert);
2421
2422          bld.vop3(aco_opcode::v_bfi_b32, Definition(dst), bitmask, insert, base);
2423
2424       } else {
2425          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2426          nir_print_instr(&instr->instr, stderr);
2427          fprintf(stderr, "\n");
2428       }
2429       break;
2430    }
2431    case nir_op_ubfe:
2432    case nir_op_ibfe: {
2433       Temp base = get_alu_src(ctx, instr->src[0]);
2434       Temp offset = get_alu_src(ctx, instr->src[1]);
2435       Temp bits = get_alu_src(ctx, instr->src[2]);
2436
2437       if (dst.type() == RegType::sgpr) {
2438          Operand extract;
2439          nir_const_value* const_offset = nir_src_as_const_value(instr->src[1].src);
2440          nir_const_value* const_bits = nir_src_as_const_value(instr->src[2].src);
2441          if (const_offset && const_bits) {
2442             uint32_t const_extract = (const_bits->u32 << 16) | const_offset->u32;
2443             extract = Operand(const_extract);
2444          } else {
2445             Operand width;
2446             if (const_bits) {
2447                width = Operand(const_bits->u32 << 16);
2448             } else {
2449                width = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), bits, Operand(16u));
2450             }
2451             extract = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), offset, width);
2452          }
2453
2454          aco_opcode opcode;
2455          if (dst.regClass() == s1) {
2456             if (instr->op == nir_op_ubfe)
2457                opcode = aco_opcode::s_bfe_u32;
2458             else
2459                opcode = aco_opcode::s_bfe_i32;
2460          } else if (dst.regClass() == s2) {
2461             if (instr->op == nir_op_ubfe)
2462                opcode = aco_opcode::s_bfe_u64;
2463             else
2464                opcode = aco_opcode::s_bfe_i64;
2465          } else {
2466             unreachable("Unsupported BFE bit size");
2467          }
2468
2469          bld.sop2(opcode, Definition(dst), bld.def(s1, scc), base, extract);
2470
2471       } else {
2472          aco_opcode opcode;
2473          if (dst.regClass() == v1) {
2474             if (instr->op == nir_op_ubfe)
2475                opcode = aco_opcode::v_bfe_u32;
2476             else
2477                opcode = aco_opcode::v_bfe_i32;
2478          } else {
2479             unreachable("Unsupported BFE bit size");
2480          }
2481
2482          emit_vop3a_instruction(ctx, instr, opcode, dst);
2483       }
2484       break;
2485    }
2486    case nir_op_bit_count: {
2487       Temp src = get_alu_src(ctx, instr->src[0]);
2488       if (src.regClass() == s1) {
2489          bld.sop1(aco_opcode::s_bcnt1_i32_b32, Definition(dst), bld.def(s1, scc), src);
2490       } else if (src.regClass() == v1) {
2491          bld.vop3(aco_opcode::v_bcnt_u32_b32, Definition(dst), src, Operand(0u));
2492       } else if (src.regClass() == v2) {
2493          bld.vop3(aco_opcode::v_bcnt_u32_b32, Definition(dst),
2494                   emit_extract_vector(ctx, src, 1, v1),
2495                   bld.vop3(aco_opcode::v_bcnt_u32_b32, bld.def(v1),
2496                            emit_extract_vector(ctx, src, 0, v1), Operand(0u)));
2497       } else if (src.regClass() == s2) {
2498          bld.sop1(aco_opcode::s_bcnt1_i32_b64, Definition(dst), bld.def(s1, scc), src);
2499       } else {
2500          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2501          nir_print_instr(&instr->instr, stderr);
2502          fprintf(stderr, "\n");
2503       }
2504       break;
2505    }
2506    case nir_op_flt: {
2507       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_f32, aco_opcode::v_cmp_lt_f64);
2508       break;
2509    }
2510    case nir_op_fge: {
2511       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_f32, aco_opcode::v_cmp_ge_f64);
2512       break;
2513    }
2514    case nir_op_feq: {
2515       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_eq_f32, aco_opcode::v_cmp_eq_f64);
2516       break;
2517    }
2518    case nir_op_fne: {
2519       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_neq_f32, aco_opcode::v_cmp_neq_f64);
2520       break;
2521    }
2522    case nir_op_ilt: {
2523       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_i32, aco_opcode::v_cmp_lt_i64, aco_opcode::s_cmp_lt_i32);
2524       break;
2525    }
2526    case nir_op_ige: {
2527       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_i32, aco_opcode::v_cmp_ge_i64, aco_opcode::s_cmp_ge_i32);
2528       break;
2529    }
2530    case nir_op_ieq: {
2531       if (instr->src[0].src.ssa->bit_size == 1)
2532          emit_boolean_logic(ctx, instr, Builder::s_xnor, dst);
2533       else
2534          emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_eq_i32, aco_opcode::v_cmp_eq_i64, aco_opcode::s_cmp_eq_i32,
2535                          ctx->program->chip_class >= GFX8 ? aco_opcode::s_cmp_eq_u64 : aco_opcode::num_opcodes);
2536       break;
2537    }
2538    case nir_op_ine: {
2539       if (instr->src[0].src.ssa->bit_size == 1)
2540          emit_boolean_logic(ctx, instr, Builder::s_xor, dst);
2541       else
2542          emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lg_i32, aco_opcode::v_cmp_lg_i64, aco_opcode::s_cmp_lg_i32,
2543                          ctx->program->chip_class >= GFX8 ? aco_opcode::s_cmp_lg_u64 : aco_opcode::num_opcodes);
2544       break;
2545    }
2546    case nir_op_ult: {
2547       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_u32, aco_opcode::v_cmp_lt_u64, aco_opcode::s_cmp_lt_u32);
2548       break;
2549    }
2550    case nir_op_uge: {
2551       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_u32, aco_opcode::v_cmp_ge_u64, aco_opcode::s_cmp_ge_u32);
2552       break;
2553    }
2554    case nir_op_fddx:
2555    case nir_op_fddy:
2556    case nir_op_fddx_fine:
2557    case nir_op_fddy_fine:
2558    case nir_op_fddx_coarse:
2559    case nir_op_fddy_coarse: {
2560       Temp src = get_alu_src(ctx, instr->src[0]);
2561       uint16_t dpp_ctrl1, dpp_ctrl2;
2562       if (instr->op == nir_op_fddx_fine) {
2563          dpp_ctrl1 = dpp_quad_perm(0, 0, 2, 2);
2564          dpp_ctrl2 = dpp_quad_perm(1, 1, 3, 3);
2565       } else if (instr->op == nir_op_fddy_fine) {
2566          dpp_ctrl1 = dpp_quad_perm(0, 1, 0, 1);
2567          dpp_ctrl2 = dpp_quad_perm(2, 3, 2, 3);
2568       } else {
2569          dpp_ctrl1 = dpp_quad_perm(0, 0, 0, 0);
2570          if (instr->op == nir_op_fddx || instr->op == nir_op_fddx_coarse)
2571             dpp_ctrl2 = dpp_quad_perm(1, 1, 1, 1);
2572          else
2573             dpp_ctrl2 = dpp_quad_perm(2, 2, 2, 2);
2574       }
2575
2576       Temp tmp;
2577       if (ctx->program->chip_class >= GFX8) {
2578          Temp tl = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl1);
2579          tmp = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), src, tl, dpp_ctrl2);
2580       } else {
2581          Temp tl = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl1);
2582          Temp tr = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl2);
2583          tmp = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), tr, tl);
2584       }
2585       emit_wqm(ctx, tmp, dst, true);
2586       break;
2587    }
2588    default:
2589       fprintf(stderr, "Unknown NIR ALU instr: ");
2590       nir_print_instr(&instr->instr, stderr);
2591       fprintf(stderr, "\n");
2592    }
2593 }
2594
2595 void visit_load_const(isel_context *ctx, nir_load_const_instr *instr)
2596 {
2597    Temp dst = get_ssa_temp(ctx, &instr->def);
2598
2599    // TODO: we really want to have the resulting type as this would allow for 64bit literals
2600    // which get truncated the lsb if double and msb if int
2601    // for now, we only use s_mov_b64 with 64bit inline constants
2602    assert(instr->def.num_components == 1 && "Vector load_const should be lowered to scalar.");
2603    assert(dst.type() == RegType::sgpr);
2604
2605    Builder bld(ctx->program, ctx->block);
2606
2607    if (instr->def.bit_size == 1) {
2608       assert(dst.regClass() == bld.lm);
2609       int val = instr->value[0].b ? -1 : 0;
2610       Operand op = bld.lm.size() == 1 ? Operand((uint32_t) val) : Operand((uint64_t) val);
2611       bld.sop1(Builder::s_mov, Definition(dst), op);
2612    } else if (dst.size() == 1) {
2613       bld.copy(Definition(dst), Operand(instr->value[0].u32));
2614    } else {
2615       assert(dst.size() != 1);
2616       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
2617       if (instr->def.bit_size == 64)
2618          for (unsigned i = 0; i < dst.size(); i++)
2619             vec->operands[i] = Operand{(uint32_t)(instr->value[0].u64 >> i * 32)};
2620       else {
2621          for (unsigned i = 0; i < dst.size(); i++)
2622             vec->operands[i] = Operand{instr->value[i].u32};
2623       }
2624       vec->definitions[0] = Definition(dst);
2625       ctx->block->instructions.emplace_back(std::move(vec));
2626    }
2627 }
2628
2629 uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2630 {
2631    uint32_t new_mask = 0;
2632    for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2633       if (mask & (1u << i))
2634          new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2635    return new_mask;
2636 }
2637
2638 Operand load_lds_size_m0(isel_context *ctx)
2639 {
2640    /* TODO: m0 does not need to be initialized on GFX9+ */
2641    Builder bld(ctx->program, ctx->block);
2642    return bld.m0((Temp)bld.sopk(aco_opcode::s_movk_i32, bld.def(s1, m0), 0xffff));
2643 }
2644
2645 Temp load_lds(isel_context *ctx, unsigned elem_size_bytes, Temp dst,
2646               Temp address, unsigned base_offset, unsigned align)
2647 {
2648    assert(util_is_power_of_two_nonzero(align) && align >= 4);
2649
2650    Builder bld(ctx->program, ctx->block);
2651
2652    Operand m = load_lds_size_m0(ctx);
2653
2654    unsigned num_components = dst.size() * 4u / elem_size_bytes;
2655    unsigned bytes_read = 0;
2656    unsigned result_size = 0;
2657    unsigned total_bytes = num_components * elem_size_bytes;
2658    std::array<Temp, NIR_MAX_VEC_COMPONENTS> result;
2659    bool large_ds_read = ctx->options->chip_class >= GFX7;
2660    bool usable_read2 = ctx->options->chip_class >= GFX7;
2661
2662    while (bytes_read < total_bytes) {
2663       unsigned todo = total_bytes - bytes_read;
2664       bool aligned8 = bytes_read % 8 == 0 && align % 8 == 0;
2665       bool aligned16 = bytes_read % 16 == 0 && align % 16 == 0;
2666
2667       aco_opcode op = aco_opcode::last_opcode;
2668       bool read2 = false;
2669       if (todo >= 16 && aligned16 && large_ds_read) {
2670          op = aco_opcode::ds_read_b128;
2671          todo = 16;
2672       } else if (todo >= 16 && aligned8 && usable_read2) {
2673          op = aco_opcode::ds_read2_b64;
2674          read2 = true;
2675          todo = 16;
2676       } else if (todo >= 12 && aligned16 && large_ds_read) {
2677          op = aco_opcode::ds_read_b96;
2678          todo = 12;
2679       } else if (todo >= 8 && aligned8) {
2680          op = aco_opcode::ds_read_b64;
2681          todo = 8;
2682       } else if (todo >= 8 && usable_read2) {
2683          op = aco_opcode::ds_read2_b32;
2684          read2 = true;
2685          todo = 8;
2686       } else if (todo >= 4) {
2687          op = aco_opcode::ds_read_b32;
2688          todo = 4;
2689       } else {
2690          assert(false);
2691       }
2692       assert(todo % elem_size_bytes == 0);
2693       unsigned num_elements = todo / elem_size_bytes;
2694       unsigned offset = base_offset + bytes_read;
2695       unsigned max_offset = read2 ? 1019 : 65535;
2696
2697       Temp address_offset = address;
2698       if (offset > max_offset) {
2699          address_offset = bld.vadd32(bld.def(v1), Operand(base_offset), address_offset);
2700          offset = bytes_read;
2701       }
2702       assert(offset <= max_offset); /* bytes_read shouldn't be large enough for this to happen */
2703
2704       Temp res;
2705       if (num_components == 1 && dst.type() == RegType::vgpr)
2706          res = dst;
2707       else
2708          res = bld.tmp(RegClass(RegType::vgpr, todo / 4));
2709
2710       if (read2)
2711          res = bld.ds(op, Definition(res), address_offset, m, offset / (todo / 2), (offset / (todo / 2)) + 1);
2712       else
2713          res = bld.ds(op, Definition(res), address_offset, m, offset);
2714
2715       if (num_components == 1) {
2716          assert(todo == total_bytes);
2717          if (dst.type() == RegType::sgpr)
2718             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), res);
2719          return dst;
2720       }
2721
2722       if (dst.type() == RegType::sgpr) {
2723          Temp new_res = bld.tmp(RegType::sgpr, res.size());
2724          expand_vector(ctx, res, new_res, res.size(), (1 << res.size()) - 1);
2725          res = new_res;
2726       }
2727
2728       if (num_elements == 1) {
2729          result[result_size++] = res;
2730       } else {
2731          assert(res != dst && res.size() % num_elements == 0);
2732          aco_ptr<Pseudo_instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector, Format::PSEUDO, 1, num_elements)};
2733          split->operands[0] = Operand(res);
2734          for (unsigned i = 0; i < num_elements; i++)
2735             split->definitions[i] = Definition(result[result_size++] = bld.tmp(res.type(), elem_size_bytes / 4));
2736          ctx->block->instructions.emplace_back(std::move(split));
2737       }
2738
2739       bytes_read += todo;
2740    }
2741
2742    assert(result_size == num_components && result_size > 1);
2743    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, result_size, 1)};
2744    for (unsigned i = 0; i < result_size; i++)
2745       vec->operands[i] = Operand(result[i]);
2746    vec->definitions[0] = Definition(dst);
2747    ctx->block->instructions.emplace_back(std::move(vec));
2748    ctx->allocated_vec.emplace(dst.id(), result);
2749
2750    return dst;
2751 }
2752
2753 Temp extract_subvector(isel_context *ctx, Temp data, unsigned start, unsigned size, RegType type)
2754 {
2755    if (start == 0 && size == data.size())
2756       return type == RegType::vgpr ? as_vgpr(ctx, data) : data;
2757
2758    unsigned size_hint = 1;
2759    auto it = ctx->allocated_vec.find(data.id());
2760    if (it != ctx->allocated_vec.end())
2761       size_hint = it->second[0].size();
2762    if (size % size_hint || start % size_hint)
2763       size_hint = 1;
2764
2765    start /= size_hint;
2766    size /= size_hint;
2767
2768    Temp elems[size];
2769    for (unsigned i = 0; i < size; i++)
2770       elems[i] = emit_extract_vector(ctx, data, start + i, RegClass(type, size_hint));
2771
2772    if (size == 1)
2773       return type == RegType::vgpr ? as_vgpr(ctx, elems[0]) : elems[0];
2774
2775    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, size, 1)};
2776    for (unsigned i = 0; i < size; i++)
2777       vec->operands[i] = Operand(elems[i]);
2778    Temp res = {ctx->program->allocateId(), RegClass(type, size * size_hint)};
2779    vec->definitions[0] = Definition(res);
2780    ctx->block->instructions.emplace_back(std::move(vec));
2781    return res;
2782 }
2783
2784 void ds_write_helper(isel_context *ctx, Operand m, Temp address, Temp data, unsigned data_start, unsigned total_size, unsigned offset0, unsigned offset1, unsigned align)
2785 {
2786    Builder bld(ctx->program, ctx->block);
2787    unsigned bytes_written = 0;
2788    bool large_ds_write = ctx->options->chip_class >= GFX7;
2789    bool usable_write2 = ctx->options->chip_class >= GFX7;
2790
2791    while (bytes_written < total_size * 4) {
2792       unsigned todo = total_size * 4 - bytes_written;
2793       bool aligned8 = bytes_written % 8 == 0 && align % 8 == 0;
2794       bool aligned16 = bytes_written % 16 == 0 && align % 16 == 0;
2795
2796       aco_opcode op = aco_opcode::last_opcode;
2797       bool write2 = false;
2798       unsigned size = 0;
2799       if (todo >= 16 && aligned16 && large_ds_write) {
2800          op = aco_opcode::ds_write_b128;
2801          size = 4;
2802       } else if (todo >= 16 && aligned8 && usable_write2) {
2803          op = aco_opcode::ds_write2_b64;
2804          write2 = true;
2805          size = 4;
2806       } else if (todo >= 12 && aligned16 && large_ds_write) {
2807          op = aco_opcode::ds_write_b96;
2808          size = 3;
2809       } else if (todo >= 8 && aligned8) {
2810          op = aco_opcode::ds_write_b64;
2811          size = 2;
2812       } else if (todo >= 8 && usable_write2) {
2813          op = aco_opcode::ds_write2_b32;
2814          write2 = true;
2815          size = 2;
2816       } else if (todo >= 4) {
2817          op = aco_opcode::ds_write_b32;
2818          size = 1;
2819       } else {
2820          assert(false);
2821       }
2822
2823       unsigned offset = offset0 + offset1 + bytes_written;
2824       unsigned max_offset = write2 ? 1020 : 65535;
2825       Temp address_offset = address;
2826       if (offset > max_offset) {
2827          address_offset = bld.vadd32(bld.def(v1), Operand(offset0), address_offset);
2828          offset = offset1 + bytes_written;
2829       }
2830       assert(offset <= max_offset); /* offset1 shouldn't be large enough for this to happen */
2831
2832       if (write2) {
2833          Temp val0 = extract_subvector(ctx, data, data_start + (bytes_written >> 2), size / 2, RegType::vgpr);
2834          Temp val1 = extract_subvector(ctx, data, data_start + (bytes_written >> 2) + 1, size / 2, RegType::vgpr);
2835          bld.ds(op, address_offset, val0, val1, m, offset / size / 2, (offset / size / 2) + 1);
2836       } else {
2837          Temp val = extract_subvector(ctx, data, data_start + (bytes_written >> 2), size, RegType::vgpr);
2838          bld.ds(op, address_offset, val, m, offset);
2839       }
2840
2841       bytes_written += size * 4;
2842    }
2843 }
2844
2845 void store_lds(isel_context *ctx, unsigned elem_size_bytes, Temp data, uint32_t wrmask,
2846                Temp address, unsigned base_offset, unsigned align)
2847 {
2848    assert(util_is_power_of_two_nonzero(align) && align >= 4);
2849    assert(elem_size_bytes == 4 || elem_size_bytes == 8);
2850
2851    Operand m = load_lds_size_m0(ctx);
2852
2853    /* we need at most two stores, assuming that the writemask is at most 4 bits wide */
2854    assert(wrmask <= 0x0f);
2855    int start[2], count[2];
2856    u_bit_scan_consecutive_range(&wrmask, &start[0], &count[0]);
2857    u_bit_scan_consecutive_range(&wrmask, &start[1], &count[1]);
2858    assert(wrmask == 0);
2859
2860    /* one combined store is sufficient */
2861    if (count[0] == count[1] && (align % elem_size_bytes) == 0 && (base_offset % elem_size_bytes) == 0) {
2862       Builder bld(ctx->program, ctx->block);
2863
2864       Temp address_offset = address;
2865       if ((base_offset / elem_size_bytes) + start[1] > 255) {
2866          address_offset = bld.vadd32(bld.def(v1), Operand(base_offset), address_offset);
2867          base_offset = 0;
2868       }
2869
2870       assert(count[0] == 1);
2871       RegClass xtract_rc(RegType::vgpr, elem_size_bytes / 4);
2872
2873       Temp val0 = emit_extract_vector(ctx, data, start[0], xtract_rc);
2874       Temp val1 = emit_extract_vector(ctx, data, start[1], xtract_rc);
2875       aco_opcode op = elem_size_bytes == 4 ? aco_opcode::ds_write2_b32 : aco_opcode::ds_write2_b64;
2876       base_offset = base_offset / elem_size_bytes;
2877       bld.ds(op, address_offset, val0, val1, m,
2878              base_offset + start[0], base_offset + start[1]);
2879       return;
2880    }
2881
2882    for (unsigned i = 0; i < 2; i++) {
2883       if (count[i] == 0)
2884          continue;
2885
2886       unsigned elem_size_words = elem_size_bytes / 4;
2887       ds_write_helper(ctx, m, address, data, start[i] * elem_size_words, count[i] * elem_size_words,
2888                       base_offset, start[i] * elem_size_bytes, align);
2889    }
2890    return;
2891 }
2892
2893 unsigned calculate_lds_alignment(isel_context *ctx, unsigned const_offset)
2894 {
2895    unsigned align = 16;
2896    if (const_offset)
2897       align = std::min(align, 1u << (ffs(const_offset) - 1));
2898
2899    return align;
2900 }
2901
2902
2903 Temp create_vec_from_array(isel_context *ctx, Temp arr[], unsigned cnt, RegType reg_type, unsigned elem_size_bytes,
2904                            unsigned split_cnt = 0u, Temp dst = Temp())
2905 {
2906    Builder bld(ctx->program, ctx->block);
2907    unsigned dword_size = elem_size_bytes / 4;
2908
2909    if (!dst.id())
2910       dst = bld.tmp(RegClass(reg_type, cnt * dword_size));
2911
2912    std::array<Temp, NIR_MAX_VEC_COMPONENTS> allocated_vec;
2913    aco_ptr<Pseudo_instruction> instr {create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, cnt, 1)};
2914    instr->definitions[0] = Definition(dst);
2915
2916    for (unsigned i = 0; i < cnt; ++i) {
2917       if (arr[i].id()) {
2918          assert(arr[i].size() == dword_size);
2919          allocated_vec[i] = arr[i];
2920          instr->operands[i] = Operand(arr[i]);
2921       } else {
2922          Temp zero = bld.copy(bld.def(RegClass(reg_type, dword_size)), Operand(0u, dword_size == 2));
2923          allocated_vec[i] = zero;
2924          instr->operands[i] = Operand(zero);
2925       }
2926    }
2927
2928    bld.insert(std::move(instr));
2929
2930    if (split_cnt)
2931       emit_split_vector(ctx, dst, split_cnt);
2932    else
2933       ctx->allocated_vec.emplace(dst.id(), allocated_vec); /* emit_split_vector already does this */
2934
2935    return dst;
2936 }
2937
2938 inline unsigned resolve_excess_vmem_const_offset(Builder &bld, Temp &voffset, unsigned const_offset)
2939 {
2940    if (const_offset >= 4096) {
2941       unsigned excess_const_offset = const_offset / 4096u * 4096u;
2942       const_offset %= 4096u;
2943
2944       if (!voffset.id())
2945          voffset = bld.copy(bld.def(v1), Operand(excess_const_offset));
2946       else if (unlikely(voffset.regClass() == s1))
2947          voffset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), Operand(excess_const_offset), Operand(voffset));
2948       else if (likely(voffset.regClass() == v1))
2949          voffset = bld.vadd32(bld.def(v1), Operand(voffset), Operand(excess_const_offset));
2950       else
2951          unreachable("Unsupported register class of voffset");
2952    }
2953
2954    return const_offset;
2955 }
2956
2957 void emit_single_mubuf_store(isel_context *ctx, Temp descriptor, Temp voffset, Temp soffset, Temp vdata,
2958                              unsigned const_offset = 0u, bool allow_reorder = true, bool slc = false)
2959 {
2960    assert(vdata.id());
2961    assert(vdata.size() != 3 || ctx->program->chip_class != GFX6);
2962    assert(vdata.size() >= 1 && vdata.size() <= 4);
2963
2964    Builder bld(ctx->program, ctx->block);
2965    aco_opcode op = (aco_opcode) ((unsigned) aco_opcode::buffer_store_dword + vdata.size() - 1);
2966    const_offset = resolve_excess_vmem_const_offset(bld, voffset, const_offset);
2967
2968    Operand voffset_op = voffset.id() ? Operand(as_vgpr(ctx, voffset)) : Operand(v1);
2969    Operand soffset_op = soffset.id() ? Operand(soffset) : Operand(0u);
2970    Builder::Result r = bld.mubuf(op, Operand(descriptor), voffset_op, soffset_op, Operand(vdata), const_offset,
2971                                  /* offen */ !voffset_op.isUndefined(), /* idxen*/ false, /* addr64 */ false,
2972                                  /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc);
2973
2974    static_cast<MUBUF_instruction *>(r.instr)->can_reorder = allow_reorder;
2975 }
2976
2977 void store_vmem_mubuf(isel_context *ctx, Temp src, Temp descriptor, Temp voffset, Temp soffset,
2978                                    unsigned base_const_offset, unsigned elem_size_bytes, unsigned write_mask,
2979                                    bool allow_combining = true, bool reorder = true, bool slc = false)
2980 {
2981    Builder bld(ctx->program, ctx->block);
2982    assert(elem_size_bytes == 4 || elem_size_bytes == 8);
2983    assert(write_mask);
2984
2985    if (elem_size_bytes == 8) {
2986       elem_size_bytes = 4;
2987       write_mask = widen_mask(write_mask, 2);
2988    }
2989
2990    while (write_mask) {
2991       int start = 0;
2992       int count = 0;
2993       u_bit_scan_consecutive_range(&write_mask, &start, &count);
2994       assert(count > 0);
2995       assert(start >= 0);
2996
2997       while (count > 0) {
2998          unsigned sub_count = allow_combining ? MIN2(count, 4) : 1;
2999          unsigned const_offset = (unsigned) start * elem_size_bytes + base_const_offset;
3000
3001          /* GFX6 doesn't have buffer_store_dwordx3, so make sure not to emit that here either. */
3002          if (unlikely(ctx->program->chip_class == GFX6 && sub_count == 3))
3003             sub_count = 2;
3004
3005          Temp elem = extract_subvector(ctx, src, start, sub_count, RegType::vgpr);
3006          emit_single_mubuf_store(ctx, descriptor, voffset, soffset, elem, const_offset, reorder, slc);
3007
3008          count -= sub_count;
3009          start += sub_count;
3010       }
3011
3012       assert(count == 0);
3013    }
3014 }
3015
3016 Temp emit_single_mubuf_load(isel_context *ctx, Temp descriptor, Temp voffset, Temp soffset,
3017                             unsigned const_offset, unsigned size_dwords, bool allow_reorder = true)
3018 {
3019    assert(size_dwords != 3 || ctx->program->chip_class != GFX6);
3020    assert(size_dwords >= 1 && size_dwords <= 4);
3021
3022    Builder bld(ctx->program, ctx->block);
3023    Temp vdata = bld.tmp(RegClass(RegType::vgpr, size_dwords));
3024    aco_opcode op = (aco_opcode) ((unsigned) aco_opcode::buffer_load_dword + size_dwords - 1);
3025    const_offset = resolve_excess_vmem_const_offset(bld, voffset, const_offset);
3026
3027    Operand voffset_op = voffset.id() ? Operand(as_vgpr(ctx, voffset)) : Operand(v1);
3028    Operand soffset_op = soffset.id() ? Operand(soffset) : Operand(0u);
3029    Builder::Result r = bld.mubuf(op, Definition(vdata), Operand(descriptor), voffset_op, soffset_op, const_offset,
3030                                  /* offen */ !voffset_op.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3031                                  /* disable_wqm */ false, /* glc */ true,
3032                                  /* dlc*/ ctx->program->chip_class >= GFX10, /* slc */ false);
3033
3034    static_cast<MUBUF_instruction *>(r.instr)->can_reorder = allow_reorder;
3035
3036    return vdata;
3037 }
3038
3039 void load_vmem_mubuf(isel_context *ctx, Temp dst, Temp descriptor, Temp voffset, Temp soffset,
3040                      unsigned base_const_offset, unsigned elem_size_bytes, unsigned num_components,
3041                      unsigned stride = 0u, bool allow_combining = true, bool allow_reorder = true)
3042 {
3043    assert(elem_size_bytes == 4 || elem_size_bytes == 8);
3044    assert((num_components * elem_size_bytes / 4) == dst.size());
3045    assert(!!stride != allow_combining);
3046
3047    Builder bld(ctx->program, ctx->block);
3048    unsigned split_cnt = num_components;
3049
3050    if (elem_size_bytes == 8) {
3051       elem_size_bytes = 4;
3052       num_components *= 2;
3053    }
3054
3055    if (!stride)
3056       stride = elem_size_bytes;
3057
3058    unsigned load_size = 1;
3059    if (allow_combining) {
3060       if ((num_components % 4) == 0)
3061          load_size = 4;
3062       else if ((num_components % 3) == 0 && ctx->program->chip_class != GFX6)
3063          load_size = 3;
3064       else if ((num_components % 2) == 0)
3065          load_size = 2;
3066    }
3067
3068    unsigned num_loads = num_components / load_size;
3069    std::array<Temp, NIR_MAX_VEC_COMPONENTS> elems;
3070
3071    for (unsigned i = 0; i < num_loads; ++i) {
3072       unsigned const_offset = i * stride * load_size + base_const_offset;
3073       elems[i] = emit_single_mubuf_load(ctx, descriptor, voffset, soffset, const_offset, load_size, allow_reorder);
3074    }
3075
3076    create_vec_from_array(ctx, elems.data(), num_loads, RegType::vgpr, load_size * 4u, split_cnt, dst);
3077 }
3078
3079 std::pair<Temp, unsigned> offset_add_from_nir(isel_context *ctx, const std::pair<Temp, unsigned> &base_offset, nir_src *off_src, unsigned stride = 1u)
3080 {
3081    Builder bld(ctx->program, ctx->block);
3082    Temp offset = base_offset.first;
3083    unsigned const_offset = base_offset.second;
3084
3085    if (!nir_src_is_const(*off_src)) {
3086       Temp indirect_offset_arg = get_ssa_temp(ctx, off_src->ssa);
3087       Temp with_stride;
3088
3089       /* Calculate indirect offset with stride */
3090       if (likely(indirect_offset_arg.regClass() == v1))
3091          with_stride = bld.v_mul_imm(bld.def(v1), indirect_offset_arg, stride);
3092       else if (indirect_offset_arg.regClass() == s1)
3093          with_stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), indirect_offset_arg);
3094       else
3095          unreachable("Unsupported register class of indirect offset");
3096
3097       /* Add to the supplied base offset */
3098       if (offset.id() == 0)
3099          offset = with_stride;
3100       else if (unlikely(offset.regClass() == s1 && with_stride.regClass() == s1))
3101          offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), with_stride, offset);
3102       else if (offset.size() == 1 && with_stride.size() == 1)
3103          offset = bld.vadd32(bld.def(v1), with_stride, offset);
3104       else
3105          unreachable("Unsupported register class of indirect offset");
3106    } else {
3107       unsigned const_offset_arg = nir_src_as_uint(*off_src);
3108       const_offset += const_offset_arg * stride;
3109    }
3110
3111    return std::make_pair(offset, const_offset);
3112 }
3113
3114 std::pair<Temp, unsigned> offset_add(isel_context *ctx, const std::pair<Temp, unsigned> &off1, const std::pair<Temp, unsigned> &off2)
3115 {
3116    Builder bld(ctx->program, ctx->block);
3117    Temp offset;
3118
3119    if (off1.first.id() && off2.first.id()) {
3120       if (unlikely(off1.first.regClass() == s1 && off2.first.regClass() == s1))
3121          offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), off1.first, off2.first);
3122       else if (off1.first.size() == 1 && off2.first.size() == 1)
3123          offset = bld.vadd32(bld.def(v1), off1.first, off2.first);
3124       else
3125          unreachable("Unsupported register class of indirect offset");
3126    } else {
3127       offset = off1.first.id() ? off1.first : off2.first;
3128    }
3129
3130    return std::make_pair(offset, off1.second + off2.second);
3131 }
3132
3133 std::pair<Temp, unsigned> offset_mul(isel_context *ctx, const std::pair<Temp, unsigned> &offs, unsigned multiplier)
3134 {
3135    Builder bld(ctx->program, ctx->block);
3136    unsigned const_offset = offs.second * multiplier;
3137
3138    if (!offs.first.id())
3139       return std::make_pair(offs.first, const_offset);
3140
3141    Temp offset = unlikely(offs.first.regClass() == s1)
3142                  ? bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(multiplier), offs.first)
3143                  : bld.v_mul_imm(bld.def(v1), offs.first, multiplier);
3144
3145    return std::make_pair(offset, const_offset);
3146 }
3147
3148 std::pair<Temp, unsigned> get_intrinsic_io_basic_offset(isel_context *ctx, nir_intrinsic_instr *instr, unsigned base_stride, unsigned component_stride)
3149 {
3150    Builder bld(ctx->program, ctx->block);
3151
3152    /* base is the driver_location, which is already multiplied by 4, so is in dwords */
3153    unsigned const_offset = nir_intrinsic_base(instr) * base_stride;
3154    /* component is in bytes */
3155    const_offset += nir_intrinsic_component(instr) * component_stride;
3156
3157    /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
3158    nir_src *off_src = nir_get_io_offset_src(instr);
3159    return offset_add_from_nir(ctx, std::make_pair(Temp(), const_offset), off_src, 4u * base_stride);
3160 }
3161
3162 std::pair<Temp, unsigned> get_intrinsic_io_basic_offset(isel_context *ctx, nir_intrinsic_instr *instr, unsigned stride = 1u)
3163 {
3164    return get_intrinsic_io_basic_offset(ctx, instr, stride, stride);
3165 }
3166
3167 Temp get_tess_rel_patch_id(isel_context *ctx)
3168 {
3169    Builder bld(ctx->program, ctx->block);
3170
3171    switch (ctx->shader->info.stage) {
3172    case MESA_SHADER_TESS_CTRL:
3173       return bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0xffu),
3174                       get_arg(ctx, ctx->args->ac.tcs_rel_ids));
3175    case MESA_SHADER_TESS_EVAL:
3176       return get_arg(ctx, ctx->args->tes_rel_patch_id);
3177    default:
3178       unreachable("Unsupported stage in get_tess_rel_patch_id");
3179    }
3180 }
3181
3182 std::pair<Temp, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context *ctx, nir_intrinsic_instr *instr)
3183 {
3184    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
3185    Builder bld(ctx->program, ctx->block);
3186
3187    uint32_t tcs_in_patch_stride = ctx->args->options->key.tcs.input_vertices * ctx->tcs_num_inputs * 4;
3188    uint32_t tcs_in_vertex_stride = ctx->tcs_num_inputs * 4;
3189
3190    std::pair<Temp, unsigned> offs = get_intrinsic_io_basic_offset(ctx, instr);
3191
3192    nir_src *vertex_index_src = nir_get_io_vertex_index_src(instr);
3193    offs = offset_add_from_nir(ctx, offs, vertex_index_src, tcs_in_vertex_stride);
3194
3195    Temp rel_patch_id = get_tess_rel_patch_id(ctx);
3196    Temp tcs_in_current_patch_offset = bld.v_mul24_imm(bld.def(v1), rel_patch_id, tcs_in_patch_stride);
3197    offs = offset_add(ctx, offs, std::make_pair(tcs_in_current_patch_offset, 0));
3198
3199    return offset_mul(ctx, offs, 4u);
3200 }
3201
3202 std::pair<Temp, unsigned> get_tcs_output_lds_offset(isel_context *ctx, nir_intrinsic_instr *instr = nullptr, bool per_vertex = false)
3203 {
3204    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
3205    Builder bld(ctx->program, ctx->block);
3206
3207    uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * ctx->tcs_num_inputs * 16;
3208    uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
3209    uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->args->shader_info->tcs.patch_outputs_written);
3210    uint32_t output_vertex_size = num_tcs_outputs * 16;
3211    uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
3212    uint32_t output_patch_stride = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
3213
3214    std::pair<Temp, unsigned> offs = instr
3215                                     ? get_intrinsic_io_basic_offset(ctx, instr, 4u)
3216                                     : std::make_pair(Temp(), 0u);
3217
3218    Temp rel_patch_id = get_tess_rel_patch_id(ctx);
3219    Temp patch_off = bld.v_mul24_imm(bld.def(v1), rel_patch_id, output_patch_stride);
3220
3221    if (per_vertex) {
3222       assert(instr);
3223
3224       nir_src *vertex_index_src = nir_get_io_vertex_index_src(instr);
3225       offs = offset_add_from_nir(ctx, offs, vertex_index_src, output_vertex_size);
3226
3227       uint32_t output_patch0_offset = (input_patch_size * ctx->tcs_num_patches);
3228       offs = offset_add(ctx, offs, std::make_pair(patch_off, output_patch0_offset));
3229    } else {
3230       uint32_t output_patch0_patch_data_offset = (input_patch_size * ctx->tcs_num_patches + pervertex_output_patch_size);
3231       offs = offset_add(ctx, offs, std::make_pair(patch_off, output_patch0_patch_data_offset));
3232    }
3233
3234    return offs;
3235 }
3236
3237 std::pair<Temp, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context *ctx, nir_intrinsic_instr *instr)
3238 {
3239    Builder bld(ctx->program, ctx->block);
3240
3241    unsigned vertices_per_patch = ctx->shader->info.tess.tcs_vertices_out;
3242    unsigned attr_stride = vertices_per_patch * ctx->tcs_num_patches;
3243
3244    std::pair<Temp, unsigned> offs = get_intrinsic_io_basic_offset(ctx, instr, attr_stride * 4u, 4u);
3245
3246    Temp rel_patch_id = get_tess_rel_patch_id(ctx);
3247    Temp patch_off = bld.v_mul24_imm(bld.def(v1), rel_patch_id, vertices_per_patch * 16u);
3248    offs = offset_add(ctx, offs, std::make_pair(patch_off, 0u));
3249
3250    nir_src *vertex_index_src = nir_get_io_vertex_index_src(instr);
3251    offs = offset_add_from_nir(ctx, offs, vertex_index_src, 16u);
3252
3253    return offs;
3254 }
3255
3256 std::pair<Temp, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context *ctx, nir_intrinsic_instr *instr = nullptr, unsigned const_base_offset = 0u)
3257 {
3258    Builder bld(ctx->program, ctx->block);
3259
3260    unsigned num_tcs_outputs = ctx->shader->info.stage == MESA_SHADER_TESS_CTRL
3261                               ? util_last_bit64(ctx->args->shader_info->tcs.outputs_written)
3262                               : ctx->args->options->key.tes.tcs_num_outputs;
3263
3264    unsigned output_vertex_size = num_tcs_outputs * 16;
3265    unsigned per_vertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
3266    unsigned per_patch_data_offset = per_vertex_output_patch_size * ctx->tcs_num_patches;
3267    unsigned attr_stride = ctx->tcs_num_patches;
3268
3269    std::pair<Temp, unsigned> offs = instr
3270                                     ? get_intrinsic_io_basic_offset(ctx, instr, attr_stride * 4u, 4u)
3271                                     : std::make_pair(Temp(), 0u);
3272
3273    if (const_base_offset)
3274       offs.second += const_base_offset * attr_stride;
3275
3276    Temp rel_patch_id = get_tess_rel_patch_id(ctx);
3277    Temp patch_off = bld.v_mul_imm(bld.def(v1), rel_patch_id, 16u);
3278    offs = offset_add(ctx, offs, std::make_pair(patch_off, per_patch_data_offset));
3279
3280    return offs;
3281 }
3282
3283 bool tcs_driver_location_matches_api_mask(isel_context *ctx, nir_intrinsic_instr *instr, bool per_vertex, uint64_t mask, bool *indirect)
3284 {
3285    unsigned off = nir_intrinsic_base(instr) * 4u;
3286    nir_src *off_src = nir_get_io_offset_src(instr);
3287
3288    if (!nir_src_is_const(*off_src)) {
3289       *indirect = true;
3290       return false;
3291    }
3292
3293    *indirect = false;
3294    off += nir_src_as_uint(*off_src) * 16u;
3295
3296    while (mask) {
3297       unsigned slot = u_bit_scan64(&mask) + (per_vertex ? 0 : VARYING_SLOT_PATCH0);
3298       if (off == shader_io_get_unique_index((gl_varying_slot) slot) * 16u)
3299          return true;
3300    }
3301
3302    return false;
3303 }
3304
3305 bool store_output_to_temps(isel_context *ctx, nir_intrinsic_instr *instr)
3306 {
3307    unsigned write_mask = nir_intrinsic_write_mask(instr);
3308    unsigned component = nir_intrinsic_component(instr);
3309    unsigned idx = nir_intrinsic_base(instr) + component;
3310
3311    nir_instr *off_instr = instr->src[1].ssa->parent_instr;
3312    if (off_instr->type != nir_instr_type_load_const)
3313       return false;
3314
3315    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
3316    idx += nir_src_as_uint(instr->src[1]) * 4u;
3317
3318    if (instr->src[0].ssa->bit_size == 64)
3319       write_mask = widen_mask(write_mask, 2);
3320
3321    for (unsigned i = 0; i < 8; ++i) {
3322       if (write_mask & (1 << i)) {
3323          ctx->outputs.mask[idx / 4u] |= 1 << (idx % 4u);
3324          ctx->outputs.temps[idx] = emit_extract_vector(ctx, src, i, v1);
3325       }
3326       idx++;
3327    }
3328
3329    return true;
3330 }
3331
3332 void visit_store_ls_or_es_output(isel_context *ctx, nir_intrinsic_instr *instr)
3333 {
3334    Builder bld(ctx->program, ctx->block);
3335
3336    std::pair<Temp, unsigned> offs = get_intrinsic_io_basic_offset(ctx, instr, 4u);
3337    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
3338    unsigned write_mask = nir_intrinsic_write_mask(instr);
3339    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8u;
3340
3341    if (ctx->stage == vertex_es || ctx->stage == tess_eval_es) {
3342       /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
3343       Temp esgs_ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_ESGS_VS * 16u));
3344       Temp es2gs_offset = get_arg(ctx, ctx->args->es2gs_offset);
3345       store_vmem_mubuf(ctx, src, esgs_ring, offs.first, es2gs_offset, offs.second, elem_size_bytes, write_mask, false, true, true);
3346    } else {
3347       Temp lds_base;
3348
3349       if (ctx->stage == vertex_geometry_gs || ctx->stage == tess_eval_geometry_gs) {
3350          /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
3351          unsigned itemsize = ctx->stage == vertex_geometry_gs
3352                              ? ctx->program->info->vs.es_info.esgs_itemsize
3353                              : ctx->program->info->tes.es_info.esgs_itemsize;
3354          Temp thread_id = emit_mbcnt(ctx, bld.def(v1));
3355          Temp wave_idx = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), get_arg(ctx, ctx->args->merged_wave_info), Operand(4u << 16 | 24));
3356          Temp vertex_idx = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), thread_id,
3357                                bld.v_mul24_imm(bld.def(v1), as_vgpr(ctx, wave_idx), ctx->program->wave_size));
3358          lds_base = bld.v_mul24_imm(bld.def(v1), vertex_idx, itemsize);
3359       } else if (ctx->stage == vertex_ls || ctx->stage == vertex_tess_control_hs) {
3360          /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
3361           * GFX9+: LS is merged into HS, but still uses the same LDS layout.
3362           */
3363          unsigned num_tcs_inputs = util_last_bit64(ctx->args->shader_info->vs.ls_outputs_written);
3364          Temp vertex_idx = get_arg(ctx, ctx->args->rel_auto_id);
3365          lds_base = bld.v_mul_imm(bld.def(v1), vertex_idx, num_tcs_inputs * 16u);
3366       } else {
3367          unreachable("Invalid LS or ES stage");
3368       }
3369
3370       offs = offset_add(ctx, offs, std::make_pair(lds_base, 0u));
3371       unsigned lds_align = calculate_lds_alignment(ctx, offs.second);
3372       store_lds(ctx, elem_size_bytes, src, write_mask, offs.first, offs.second, lds_align);
3373    }
3374 }
3375
3376 bool should_write_tcs_patch_output_to_vmem(isel_context *ctx, nir_intrinsic_instr *instr)
3377 {
3378    unsigned off = nir_intrinsic_base(instr) * 4u;
3379    return off != ctx->tcs_tess_lvl_out_loc &&
3380           off != ctx->tcs_tess_lvl_in_loc;
3381 }
3382
3383 bool should_write_tcs_output_to_lds(isel_context *ctx, nir_intrinsic_instr *instr, bool per_vertex)
3384 {
3385    /* When none of the appropriate outputs are read, we are OK to never write to LDS */
3386    if (per_vertex ? ctx->shader->info.outputs_read == 0U : ctx->shader->info.patch_outputs_read == 0u)
3387       return false;
3388
3389    uint64_t mask = per_vertex
3390                    ? ctx->shader->info.outputs_read
3391                    : ctx->shader->info.patch_outputs_read;
3392    bool indirect_write;
3393    bool output_read = tcs_driver_location_matches_api_mask(ctx, instr, per_vertex, mask, &indirect_write);
3394    return indirect_write || output_read;
3395 }
3396
3397 void visit_store_tcs_output(isel_context *ctx, nir_intrinsic_instr *instr, bool per_vertex)
3398 {
3399    assert(ctx->stage == tess_control_hs || ctx->stage == vertex_tess_control_hs);
3400    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
3401
3402    Builder bld(ctx->program, ctx->block);
3403
3404    Temp store_val = get_ssa_temp(ctx, instr->src[0].ssa);
3405    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
3406    unsigned write_mask = nir_intrinsic_write_mask(instr);
3407
3408    /* Only write to VMEM if the output is per-vertex or it's per-patch non tess factor */
3409    bool write_to_vmem = per_vertex || should_write_tcs_patch_output_to_vmem(ctx, instr);
3410    /* Only write to LDS if the output is read by the shader, or it's per-patch tess factor */
3411    bool write_to_lds = !write_to_vmem || should_write_tcs_output_to_lds(ctx, instr, per_vertex);
3412
3413    if (write_to_vmem) {
3414       std::pair<Temp, unsigned> vmem_offs = per_vertex
3415                                             ? get_tcs_per_vertex_output_vmem_offset(ctx, instr)
3416                                             : get_tcs_per_patch_output_vmem_offset(ctx, instr);
3417
3418       Temp hs_ring_tess_offchip = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_HS_TESS_OFFCHIP * 16u));
3419       Temp oc_lds = get_arg(ctx, ctx->args->oc_lds);
3420       store_vmem_mubuf(ctx, store_val, hs_ring_tess_offchip, vmem_offs.first, oc_lds, vmem_offs.second, elem_size_bytes, write_mask, true, false);
3421    }
3422
3423    if (write_to_lds) {
3424       std::pair<Temp, unsigned> lds_offs = get_tcs_output_lds_offset(ctx, instr, per_vertex);
3425       unsigned lds_align = calculate_lds_alignment(ctx, lds_offs.second);
3426       store_lds(ctx, elem_size_bytes, store_val, write_mask, lds_offs.first, lds_offs.second, lds_align);
3427    }
3428 }
3429
3430 void visit_load_tcs_output(isel_context *ctx, nir_intrinsic_instr *instr, bool per_vertex)
3431 {
3432    assert(ctx->stage == tess_control_hs || ctx->stage == vertex_tess_control_hs);
3433    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
3434
3435    Builder bld(ctx->program, ctx->block);
3436
3437    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3438    std::pair<Temp, unsigned> lds_offs = get_tcs_output_lds_offset(ctx, instr, per_vertex);
3439    unsigned lds_align = calculate_lds_alignment(ctx, lds_offs.second);
3440    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
3441
3442    load_lds(ctx, elem_size_bytes, dst, lds_offs.first, lds_offs.second, lds_align);
3443 }
3444
3445 void visit_store_output(isel_context *ctx, nir_intrinsic_instr *instr)
3446 {
3447    if (ctx->stage == vertex_vs ||
3448        ctx->stage == tess_eval_vs ||
3449        ctx->stage == fragment_fs ||
3450        ctx->shader->info.stage == MESA_SHADER_GEOMETRY) {
3451       bool stored_to_temps = store_output_to_temps(ctx, instr);
3452       if (!stored_to_temps) {
3453          fprintf(stderr, "Unimplemented output offset instruction:\n");
3454          nir_print_instr(instr->src[1].ssa->parent_instr, stderr);
3455          fprintf(stderr, "\n");
3456          abort();
3457       }
3458    } else if (ctx->stage == vertex_es ||
3459               ctx->stage == vertex_ls ||
3460               ctx->stage == tess_eval_es ||
3461               (ctx->stage == vertex_tess_control_hs && ctx->shader->info.stage == MESA_SHADER_VERTEX) ||
3462               (ctx->stage == vertex_geometry_gs && ctx->shader->info.stage == MESA_SHADER_VERTEX) ||
3463               (ctx->stage == tess_eval_geometry_gs && ctx->shader->info.stage == MESA_SHADER_TESS_EVAL)) {
3464       visit_store_ls_or_es_output(ctx, instr);
3465    } else if (ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) {
3466       visit_store_tcs_output(ctx, instr, false);
3467    } else {
3468       unreachable("Shader stage not implemented");
3469    }
3470 }
3471
3472 void visit_load_output(isel_context *ctx, nir_intrinsic_instr *instr)
3473 {
3474    visit_load_tcs_output(ctx, instr, false);
3475 }
3476
3477 void emit_interp_instr(isel_context *ctx, unsigned idx, unsigned component, Temp src, Temp dst, Temp prim_mask)
3478 {
3479    Temp coord1 = emit_extract_vector(ctx, src, 0, v1);
3480    Temp coord2 = emit_extract_vector(ctx, src, 1, v1);
3481
3482    Builder bld(ctx->program, ctx->block);
3483    Builder::Result interp_p1 = bld.vintrp(aco_opcode::v_interp_p1_f32, bld.def(v1), coord1, bld.m0(prim_mask), idx, component);
3484    if (ctx->program->has_16bank_lds)
3485       interp_p1.instr->operands[0].setLateKill(true);
3486    bld.vintrp(aco_opcode::v_interp_p2_f32, Definition(dst), coord2, bld.m0(prim_mask), interp_p1, idx, component);
3487 }
3488
3489 void emit_load_frag_coord(isel_context *ctx, Temp dst, unsigned num_components)
3490 {
3491    aco_ptr<Pseudo_instruction> vec(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1));
3492    for (unsigned i = 0; i < num_components; i++)
3493       vec->operands[i] = Operand(get_arg(ctx, ctx->args->ac.frag_pos[i]));
3494    if (G_0286CC_POS_W_FLOAT_ENA(ctx->program->config->spi_ps_input_ena)) {
3495       assert(num_components == 4);
3496       Builder bld(ctx->program, ctx->block);
3497       vec->operands[3] = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), get_arg(ctx, ctx->args->ac.frag_pos[3]));
3498    }
3499
3500    for (Operand& op : vec->operands)
3501       op = op.isUndefined() ? Operand(0u) : op;
3502
3503    vec->definitions[0] = Definition(dst);
3504    ctx->block->instructions.emplace_back(std::move(vec));
3505    emit_split_vector(ctx, dst, num_components);
3506    return;
3507 }
3508
3509 void visit_load_interpolated_input(isel_context *ctx, nir_intrinsic_instr *instr)
3510 {
3511    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3512    Temp coords = get_ssa_temp(ctx, instr->src[0].ssa);
3513    unsigned idx = nir_intrinsic_base(instr);
3514    unsigned component = nir_intrinsic_component(instr);
3515    Temp prim_mask = get_arg(ctx, ctx->args->ac.prim_mask);
3516
3517    nir_const_value* offset = nir_src_as_const_value(instr->src[1]);
3518    if (offset) {
3519       assert(offset->u32 == 0);
3520    } else {
3521       /* the lower 15bit of the prim_mask contain the offset into LDS
3522        * while the upper bits contain the number of prims */
3523       Temp offset_src = get_ssa_temp(ctx, instr->src[1].ssa);
3524       assert(offset_src.regClass() == s1 && "TODO: divergent offsets...");
3525       Builder bld(ctx->program, ctx->block);
3526       Temp stride = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), prim_mask, Operand(16u));
3527       stride = bld.sop1(aco_opcode::s_bcnt1_i32_b32, bld.def(s1), bld.def(s1, scc), stride);
3528       stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, Operand(48u));
3529       offset_src = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, offset_src);
3530       prim_mask = bld.sop2(aco_opcode::s_add_i32, bld.def(s1, m0), bld.def(s1, scc), offset_src, prim_mask);
3531    }
3532
3533    if (instr->dest.ssa.num_components == 1) {
3534       emit_interp_instr(ctx, idx, component, coords, dst, prim_mask);
3535    } else {
3536       aco_ptr<Pseudo_instruction> vec(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.ssa.num_components, 1));
3537       for (unsigned i = 0; i < instr->dest.ssa.num_components; i++)
3538       {
3539          Temp tmp = {ctx->program->allocateId(), v1};
3540          emit_interp_instr(ctx, idx, component+i, coords, tmp, prim_mask);
3541          vec->operands[i] = Operand(tmp);
3542       }
3543       vec->definitions[0] = Definition(dst);
3544       ctx->block->instructions.emplace_back(std::move(vec));
3545    }
3546 }
3547
3548 bool check_vertex_fetch_size(isel_context *ctx, const ac_data_format_info *vtx_info,
3549                              unsigned offset, unsigned stride, unsigned channels)
3550 {
3551    unsigned vertex_byte_size = vtx_info->chan_byte_size * channels;
3552    if (vtx_info->chan_byte_size != 4 && channels == 3)
3553       return false;
3554    return (ctx->options->chip_class != GFX6 && ctx->options->chip_class != GFX10) ||
3555           (offset % vertex_byte_size == 0 && stride % vertex_byte_size == 0);
3556 }
3557
3558 uint8_t get_fetch_data_format(isel_context *ctx, const ac_data_format_info *vtx_info,
3559                               unsigned offset, unsigned stride, unsigned *channels)
3560 {
3561    if (!vtx_info->chan_byte_size) {
3562       *channels = vtx_info->num_channels;
3563       return vtx_info->chan_format;
3564    }
3565
3566    unsigned num_channels = *channels;
3567    if (!check_vertex_fetch_size(ctx, vtx_info, offset, stride, *channels)) {
3568       unsigned new_channels = num_channels + 1;
3569       /* first, assume more loads is worse and try using a larger data format */
3570       while (new_channels <= 4 && !check_vertex_fetch_size(ctx, vtx_info, offset, stride, new_channels)) {
3571          new_channels++;
3572          /* don't make the attribute potentially out-of-bounds */
3573          if (offset + new_channels * vtx_info->chan_byte_size > stride)
3574             new_channels = 5;
3575       }
3576
3577       if (new_channels == 5) {
3578          /* then try decreasing load size (at the cost of more loads) */
3579          new_channels = *channels;
3580          while (new_channels > 1 && !check_vertex_fetch_size(ctx, vtx_info, offset, stride, new_channels))
3581             new_channels--;
3582       }
3583
3584       if (new_channels < *channels)
3585          *channels = new_channels;
3586       num_channels = new_channels;
3587    }
3588
3589    switch (vtx_info->chan_format) {
3590    case V_008F0C_BUF_DATA_FORMAT_8:
3591       return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8, V_008F0C_BUF_DATA_FORMAT_8_8,
3592                          V_008F0C_BUF_DATA_FORMAT_INVALID, V_008F0C_BUF_DATA_FORMAT_8_8_8_8}[num_channels - 1];
3593    case V_008F0C_BUF_DATA_FORMAT_16:
3594       return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16, V_008F0C_BUF_DATA_FORMAT_16_16,
3595                          V_008F0C_BUF_DATA_FORMAT_INVALID, V_008F0C_BUF_DATA_FORMAT_16_16_16_16}[num_channels - 1];
3596    case V_008F0C_BUF_DATA_FORMAT_32:
3597       return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32, V_008F0C_BUF_DATA_FORMAT_32_32,
3598                          V_008F0C_BUF_DATA_FORMAT_32_32_32, V_008F0C_BUF_DATA_FORMAT_32_32_32_32}[num_channels - 1];
3599    }
3600    unreachable("shouldn't reach here");
3601    return V_008F0C_BUF_DATA_FORMAT_INVALID;
3602 }
3603
3604 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
3605  * so we may need to fix it up. */
3606 Temp adjust_vertex_fetch_alpha(isel_context *ctx, unsigned adjustment, Temp alpha)
3607 {
3608    Builder bld(ctx->program, ctx->block);
3609
3610    if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
3611       alpha = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), alpha);
3612
3613    /* For the integer-like cases, do a natural sign extension.
3614     *
3615     * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
3616     * and happen to contain 0, 1, 2, 3 as the two LSBs of the
3617     * exponent.
3618     */
3619    alpha = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(adjustment == RADV_ALPHA_ADJUST_SNORM ? 7u : 30u), alpha);
3620    alpha = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(30u), alpha);
3621
3622    /* Convert back to the right type. */
3623    if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
3624       alpha = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), alpha);
3625       Temp clamp = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0xbf800000u), alpha);
3626       alpha = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xbf800000u), alpha, clamp);
3627    } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
3628       alpha = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), alpha);
3629    }
3630
3631    return alpha;
3632 }
3633
3634 void visit_load_input(isel_context *ctx, nir_intrinsic_instr *instr)
3635 {
3636    Builder bld(ctx->program, ctx->block);
3637    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3638    if (ctx->shader->info.stage == MESA_SHADER_VERTEX) {
3639
3640       nir_instr *off_instr = instr->src[0].ssa->parent_instr;
3641       if (off_instr->type != nir_instr_type_load_const) {
3642          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
3643          nir_print_instr(off_instr, stderr);
3644          fprintf(stderr, "\n");
3645       }
3646       uint32_t offset = nir_instr_as_load_const(off_instr)->value[0].u32;
3647
3648       Temp vertex_buffers = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->vertex_buffers));
3649
3650       unsigned location = nir_intrinsic_base(instr) / 4 - VERT_ATTRIB_GENERIC0 + offset;
3651       unsigned component = nir_intrinsic_component(instr);
3652       unsigned attrib_binding = ctx->options->key.vs.vertex_attribute_bindings[location];
3653       uint32_t attrib_offset = ctx->options->key.vs.vertex_attribute_offsets[location];
3654       uint32_t attrib_stride = ctx->options->key.vs.vertex_attribute_strides[location];
3655       unsigned attrib_format = ctx->options->key.vs.vertex_attribute_formats[location];
3656
3657       unsigned dfmt = attrib_format & 0xf;
3658       unsigned nfmt = (attrib_format >> 4) & 0x7;
3659       const struct ac_data_format_info *vtx_info = ac_get_data_format_info(dfmt);
3660
3661       unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa) << component;
3662       unsigned num_channels = MIN2(util_last_bit(mask), vtx_info->num_channels);
3663       unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> (location * 2)) & 3;
3664       bool post_shuffle = ctx->options->key.vs.post_shuffle & (1 << location);
3665       if (post_shuffle)
3666          num_channels = MAX2(num_channels, 3);
3667
3668       Operand off = bld.copy(bld.def(s1), Operand(attrib_binding * 16u));
3669       Temp list = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), vertex_buffers, off);
3670
3671       Temp index;
3672       if (ctx->options->key.vs.instance_rate_inputs & (1u << location)) {
3673          uint32_t divisor = ctx->options->key.vs.instance_rate_divisors[location];
3674          Temp start_instance = get_arg(ctx, ctx->args->ac.start_instance);
3675          if (divisor) {
3676             Temp instance_id = get_arg(ctx, ctx->args->ac.instance_id);
3677             if (divisor != 1) {
3678                Temp divided = bld.tmp(v1);
3679                emit_v_div_u32(ctx, divided, as_vgpr(ctx, instance_id), divisor);
3680                index = bld.vadd32(bld.def(v1), start_instance, divided);
3681             } else {
3682                index = bld.vadd32(bld.def(v1), start_instance, instance_id);
3683             }
3684          } else {
3685             index = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), start_instance);
3686          }
3687       } else {
3688          index = bld.vadd32(bld.def(v1),
3689                             get_arg(ctx, ctx->args->ac.base_vertex),
3690                             get_arg(ctx, ctx->args->ac.vertex_id));
3691       }
3692
3693       Temp channels[num_channels];
3694       unsigned channel_start = 0;
3695       bool direct_fetch = false;
3696
3697       /* skip unused channels at the start */
3698       if (vtx_info->chan_byte_size && !post_shuffle) {
3699          channel_start = ffs(mask) - 1;
3700          for (unsigned i = 0; i < channel_start; i++)
3701             channels[i] = Temp(0, s1);
3702       } else if (vtx_info->chan_byte_size && post_shuffle && !(mask & 0x8)) {
3703          num_channels = 3 - (ffs(mask) - 1);
3704       }
3705
3706       /* load channels */
3707       while (channel_start < num_channels) {
3708          unsigned fetch_size = num_channels - channel_start;
3709          unsigned fetch_offset = attrib_offset + channel_start * vtx_info->chan_byte_size;
3710          bool expanded = false;
3711
3712          /* use MUBUF when possible to avoid possible alignment issues */
3713          /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
3714          bool use_mubuf = (nfmt == V_008F0C_BUF_NUM_FORMAT_FLOAT ||
3715                            nfmt == V_008F0C_BUF_NUM_FORMAT_UINT ||
3716                            nfmt == V_008F0C_BUF_NUM_FORMAT_SINT) &&
3717                           vtx_info->chan_byte_size == 4;
3718          unsigned fetch_dfmt = V_008F0C_BUF_DATA_FORMAT_INVALID;
3719          if (!use_mubuf) {
3720             fetch_dfmt = get_fetch_data_format(ctx, vtx_info, fetch_offset, attrib_stride, &fetch_size);
3721          } else {
3722             if (fetch_size == 3 && ctx->options->chip_class == GFX6) {
3723                /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
3724                fetch_size = 4;
3725                expanded = true;
3726             }
3727          }
3728
3729          Temp fetch_index = index;
3730          if (attrib_stride != 0 && fetch_offset > attrib_stride) {
3731             fetch_index = bld.vadd32(bld.def(v1), Operand(fetch_offset / attrib_stride), fetch_index);
3732             fetch_offset = fetch_offset % attrib_stride;
3733          }
3734
3735          Operand soffset(0u);
3736          if (fetch_offset >= 4096) {
3737             soffset = bld.copy(bld.def(s1), Operand(fetch_offset / 4096 * 4096));
3738             fetch_offset %= 4096;
3739          }
3740
3741          aco_opcode opcode;
3742          switch (fetch_size) {
3743          case 1:
3744             opcode = use_mubuf ? aco_opcode::buffer_load_dword : aco_opcode::tbuffer_load_format_x;
3745             break;
3746          case 2:
3747             opcode = use_mubuf ? aco_opcode::buffer_load_dwordx2 : aco_opcode::tbuffer_load_format_xy;
3748             break;
3749          case 3:
3750             assert(ctx->options->chip_class >= GFX7 ||
3751                    (!use_mubuf && ctx->options->chip_class == GFX6));
3752             opcode = use_mubuf ? aco_opcode::buffer_load_dwordx3 : aco_opcode::tbuffer_load_format_xyz;
3753             break;
3754          case 4:
3755             opcode = use_mubuf ? aco_opcode::buffer_load_dwordx4 : aco_opcode::tbuffer_load_format_xyzw;
3756             break;
3757          default:
3758             unreachable("Unimplemented load_input vector size");
3759          }
3760
3761          Temp fetch_dst;
3762          if (channel_start == 0 && fetch_size == dst.size() && !post_shuffle &&
3763              !expanded && (alpha_adjust == RADV_ALPHA_ADJUST_NONE ||
3764                            num_channels <= 3)) {
3765             direct_fetch = true;
3766             fetch_dst = dst;
3767          } else {
3768             fetch_dst = bld.tmp(RegType::vgpr, fetch_size);
3769          }
3770
3771          if (use_mubuf) {
3772             Instruction *mubuf = bld.mubuf(opcode,
3773                                            Definition(fetch_dst), list, fetch_index, soffset,
3774                                            fetch_offset, false, true).instr;
3775             static_cast<MUBUF_instruction*>(mubuf)->can_reorder = true;
3776          } else {
3777             Instruction *mtbuf = bld.mtbuf(opcode,
3778                                            Definition(fetch_dst), list, fetch_index, soffset,
3779                                            fetch_dfmt, nfmt, fetch_offset, false, true).instr;
3780             static_cast<MTBUF_instruction*>(mtbuf)->can_reorder = true;
3781          }
3782
3783          emit_split_vector(ctx, fetch_dst, fetch_dst.size());
3784
3785          if (fetch_size == 1) {
3786             channels[channel_start] = fetch_dst;
3787          } else {
3788             for (unsigned i = 0; i < MIN2(fetch_size, num_channels - channel_start); i++)
3789                channels[channel_start + i] = emit_extract_vector(ctx, fetch_dst, i, v1);
3790          }
3791
3792          channel_start += fetch_size;
3793       }
3794
3795       if (!direct_fetch) {
3796          bool is_float = nfmt != V_008F0C_BUF_NUM_FORMAT_UINT &&
3797                          nfmt != V_008F0C_BUF_NUM_FORMAT_SINT;
3798
3799          static const unsigned swizzle_normal[4] = {0, 1, 2, 3};
3800          static const unsigned swizzle_post_shuffle[4] = {2, 1, 0, 3};
3801          const unsigned *swizzle = post_shuffle ? swizzle_post_shuffle : swizzle_normal;
3802
3803          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
3804          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
3805          unsigned num_temp = 0;
3806          for (unsigned i = 0; i < dst.size(); i++) {
3807             unsigned idx = i + component;
3808             if (swizzle[idx] < num_channels && channels[swizzle[idx]].id()) {
3809                Temp channel = channels[swizzle[idx]];
3810                if (idx == 3 && alpha_adjust != RADV_ALPHA_ADJUST_NONE)
3811                   channel = adjust_vertex_fetch_alpha(ctx, alpha_adjust, channel);
3812                vec->operands[i] = Operand(channel);
3813
3814                num_temp++;
3815                elems[i] = channel;
3816             } else if (is_float && idx == 3) {
3817                vec->operands[i] = Operand(0x3f800000u);
3818             } else if (!is_float && idx == 3) {
3819                vec->operands[i] = Operand(1u);
3820             } else {
3821                vec->operands[i] = Operand(0u);
3822             }
3823          }
3824          vec->definitions[0] = Definition(dst);
3825          ctx->block->instructions.emplace_back(std::move(vec));
3826          emit_split_vector(ctx, dst, dst.size());
3827
3828          if (num_temp == dst.size())
3829             ctx->allocated_vec.emplace(dst.id(), elems);
3830       }
3831    } else if (ctx->shader->info.stage == MESA_SHADER_FRAGMENT) {
3832       unsigned offset_idx = instr->intrinsic == nir_intrinsic_load_input ? 0 : 1;
3833       nir_instr *off_instr = instr->src[offset_idx].ssa->parent_instr;
3834       if (off_instr->type != nir_instr_type_load_const ||
3835           nir_instr_as_load_const(off_instr)->value[0].u32 != 0) {
3836          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
3837          nir_print_instr(off_instr, stderr);
3838          fprintf(stderr, "\n");
3839       }
3840
3841       Temp prim_mask = get_arg(ctx, ctx->args->ac.prim_mask);
3842       nir_const_value* offset = nir_src_as_const_value(instr->src[offset_idx]);
3843       if (offset) {
3844          assert(offset->u32 == 0);
3845       } else {
3846          /* the lower 15bit of the prim_mask contain the offset into LDS
3847           * while the upper bits contain the number of prims */
3848          Temp offset_src = get_ssa_temp(ctx, instr->src[offset_idx].ssa);
3849          assert(offset_src.regClass() == s1 && "TODO: divergent offsets...");
3850          Builder bld(ctx->program, ctx->block);
3851          Temp stride = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), prim_mask, Operand(16u));
3852          stride = bld.sop1(aco_opcode::s_bcnt1_i32_b32, bld.def(s1), bld.def(s1, scc), stride);
3853          stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, Operand(48u));
3854          offset_src = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, offset_src);
3855          prim_mask = bld.sop2(aco_opcode::s_add_i32, bld.def(s1, m0), bld.def(s1, scc), offset_src, prim_mask);
3856       }
3857
3858       unsigned idx = nir_intrinsic_base(instr);
3859       unsigned component = nir_intrinsic_component(instr);
3860       unsigned vertex_id = 2; /* P0 */
3861
3862       if (instr->intrinsic == nir_intrinsic_load_input_vertex) {
3863          nir_const_value* src0 = nir_src_as_const_value(instr->src[0]);
3864          switch (src0->u32) {
3865          case 0:
3866             vertex_id = 2; /* P0 */
3867             break;
3868          case 1:
3869             vertex_id = 0; /* P10 */
3870             break;
3871          case 2:
3872             vertex_id = 1; /* P20 */
3873             break;
3874          default:
3875             unreachable("invalid vertex index");
3876          }
3877       }
3878
3879       if (dst.size() == 1) {
3880          bld.vintrp(aco_opcode::v_interp_mov_f32, Definition(dst), Operand(vertex_id), bld.m0(prim_mask), idx, component);
3881       } else {
3882          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
3883          for (unsigned i = 0; i < dst.size(); i++)
3884             vec->operands[i] = bld.vintrp(aco_opcode::v_interp_mov_f32, bld.def(v1), Operand(vertex_id), bld.m0(prim_mask), idx, component + i);
3885          vec->definitions[0] = Definition(dst);
3886          bld.insert(std::move(vec));
3887       }
3888
3889    } else if (ctx->shader->info.stage == MESA_SHADER_TESS_EVAL) {
3890       Temp ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_HS_TESS_OFFCHIP * 16u));
3891       Temp soffset = get_arg(ctx, ctx->args->oc_lds);
3892       std::pair<Temp, unsigned> offs = get_tcs_per_patch_output_vmem_offset(ctx, instr);
3893       unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8u;
3894
3895       load_vmem_mubuf(ctx, dst, ring, offs.first, soffset, offs.second, elem_size_bytes, instr->dest.ssa.num_components);
3896    } else {
3897       unreachable("Shader stage not implemented");
3898    }
3899 }
3900
3901 std::pair<Temp, unsigned> get_gs_per_vertex_input_offset(isel_context *ctx, nir_intrinsic_instr *instr, unsigned base_stride = 1u)
3902 {
3903    assert(ctx->shader->info.stage == MESA_SHADER_GEOMETRY);
3904
3905    Builder bld(ctx->program, ctx->block);
3906    nir_src *vertex_src = nir_get_io_vertex_index_src(instr);
3907    Temp vertex_offset;
3908
3909    if (!nir_src_is_const(*vertex_src)) {
3910       /* better code could be created, but this case probably doesn't happen
3911        * much in practice */
3912       Temp indirect_vertex = as_vgpr(ctx, get_ssa_temp(ctx, vertex_src->ssa));
3913       for (unsigned i = 0; i < ctx->shader->info.gs.vertices_in; i++) {
3914          Temp elem;
3915
3916          if (ctx->stage == vertex_geometry_gs || ctx->stage == tess_eval_geometry_gs) {
3917             elem = get_arg(ctx, ctx->args->gs_vtx_offset[i / 2u * 2u]);
3918             if (i % 2u)
3919                elem = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(16u), elem);
3920          } else {
3921             elem = get_arg(ctx, ctx->args->gs_vtx_offset[i]);
3922          }
3923
3924          if (vertex_offset.id()) {
3925             Temp cond = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.hint_vcc(bld.def(bld.lm)),
3926                                  Operand(i), indirect_vertex);
3927             vertex_offset = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), vertex_offset, elem, cond);
3928          } else {
3929             vertex_offset = elem;
3930          }
3931       }
3932
3933       if (ctx->stage == vertex_geometry_gs || ctx->stage == tess_eval_geometry_gs)
3934          vertex_offset = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0xffffu), vertex_offset);
3935    } else {
3936       unsigned vertex = nir_src_as_uint(*vertex_src);
3937       if (ctx->stage == vertex_geometry_gs || ctx->stage == tess_eval_geometry_gs)
3938          vertex_offset = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1),
3939                                   get_arg(ctx, ctx->args->gs_vtx_offset[vertex / 2u * 2u]),
3940                                   Operand((vertex % 2u) * 16u), Operand(16u));
3941       else
3942          vertex_offset = get_arg(ctx, ctx->args->gs_vtx_offset[vertex]);
3943    }
3944
3945    std::pair<Temp, unsigned> offs = get_intrinsic_io_basic_offset(ctx, instr, base_stride);
3946    offs = offset_add(ctx, offs, std::make_pair(vertex_offset, 0u));
3947    return offset_mul(ctx, offs, 4u);
3948 }
3949
3950 void visit_load_gs_per_vertex_input(isel_context *ctx, nir_intrinsic_instr *instr)
3951 {
3952    assert(ctx->shader->info.stage == MESA_SHADER_GEOMETRY);
3953
3954    Builder bld(ctx->program, ctx->block);
3955    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3956    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
3957
3958    if (ctx->stage == geometry_gs) {
3959       std::pair<Temp, unsigned> offs = get_gs_per_vertex_input_offset(ctx, instr, ctx->program->wave_size);
3960       Temp ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_ESGS_GS * 16u));
3961       load_vmem_mubuf(ctx, dst, ring, offs.first, Temp(), offs.second, elem_size_bytes, instr->dest.ssa.num_components, 4u * ctx->program->wave_size, false, true);
3962    } else if (ctx->stage == vertex_geometry_gs || ctx->stage == tess_eval_geometry_gs) {
3963       std::pair<Temp, unsigned> offs = get_gs_per_vertex_input_offset(ctx, instr);
3964       unsigned lds_align = calculate_lds_alignment(ctx, offs.second);
3965       load_lds(ctx, elem_size_bytes, dst, offs.first, offs.second, lds_align);
3966    } else {
3967       unreachable("Unsupported GS stage.");
3968    }
3969 }
3970
3971 void visit_load_tcs_per_vertex_input(isel_context *ctx, nir_intrinsic_instr *instr)
3972 {
3973    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
3974
3975    Builder bld(ctx->program, ctx->block);
3976    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3977    std::pair<Temp, unsigned> offs = get_tcs_per_vertex_input_lds_offset(ctx, instr);
3978    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
3979    unsigned lds_align = calculate_lds_alignment(ctx, offs.second);
3980
3981    load_lds(ctx, elem_size_bytes, dst, offs.first, offs.second, lds_align);
3982 }
3983
3984 void visit_load_tes_per_vertex_input(isel_context *ctx, nir_intrinsic_instr *instr)
3985 {
3986    assert(ctx->shader->info.stage == MESA_SHADER_TESS_EVAL);
3987
3988    Builder bld(ctx->program, ctx->block);
3989
3990    Temp ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_HS_TESS_OFFCHIP * 16u));
3991    Temp oc_lds = get_arg(ctx, ctx->args->oc_lds);
3992    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3993
3994    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
3995    std::pair<Temp, unsigned> offs = get_tcs_per_vertex_output_vmem_offset(ctx, instr);
3996
3997    load_vmem_mubuf(ctx, dst, ring, offs.first, oc_lds, offs.second, elem_size_bytes, instr->dest.ssa.num_components, 0u, true, true);
3998 }
3999
4000 void visit_load_per_vertex_input(isel_context *ctx, nir_intrinsic_instr *instr)
4001 {
4002    switch (ctx->shader->info.stage) {
4003    case MESA_SHADER_GEOMETRY:
4004       visit_load_gs_per_vertex_input(ctx, instr);
4005       break;
4006    case MESA_SHADER_TESS_CTRL:
4007       visit_load_tcs_per_vertex_input(ctx, instr);
4008       break;
4009    case MESA_SHADER_TESS_EVAL:
4010       visit_load_tes_per_vertex_input(ctx, instr);
4011       break;
4012    default:
4013       unreachable("Unimplemented shader stage");
4014    }
4015 }
4016
4017 void visit_load_per_vertex_output(isel_context *ctx, nir_intrinsic_instr *instr)
4018 {
4019    visit_load_tcs_output(ctx, instr, true);
4020 }
4021
4022 void visit_store_per_vertex_output(isel_context *ctx, nir_intrinsic_instr *instr)
4023 {
4024    assert(ctx->stage == tess_control_hs || ctx->stage == vertex_tess_control_hs);
4025    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
4026
4027    visit_store_tcs_output(ctx, instr, true);
4028 }
4029
4030 void visit_load_tess_coord(isel_context *ctx, nir_intrinsic_instr *instr)
4031 {
4032    assert(ctx->shader->info.stage == MESA_SHADER_TESS_EVAL);
4033
4034    Builder bld(ctx->program, ctx->block);
4035    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4036
4037    Operand tes_u(get_arg(ctx, ctx->args->tes_u));
4038    Operand tes_v(get_arg(ctx, ctx->args->tes_v));
4039    Operand tes_w(0u);
4040
4041    if (ctx->shader->info.tess.primitive_mode == GL_TRIANGLES) {
4042       Temp tmp = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), tes_u, tes_v);
4043       tmp = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), Operand(0x3f800000u /* 1.0f */), tmp);
4044       tes_w = Operand(tmp);
4045    }
4046
4047    Temp tess_coord = bld.pseudo(aco_opcode::p_create_vector, Definition(dst), tes_u, tes_v, tes_w);
4048    emit_split_vector(ctx, tess_coord, 3);
4049 }
4050
4051 Temp load_desc_ptr(isel_context *ctx, unsigned desc_set)
4052 {
4053    if (ctx->program->info->need_indirect_descriptor_sets) {
4054       Builder bld(ctx->program, ctx->block);
4055       Temp ptr64 = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->descriptor_sets[0]));
4056       Operand off = bld.copy(bld.def(s1), Operand(desc_set << 2));
4057       return bld.smem(aco_opcode::s_load_dword, bld.def(s1), ptr64, off);//, false, false, false);
4058    }
4059
4060    return get_arg(ctx, ctx->args->descriptor_sets[desc_set]);
4061 }
4062
4063
4064 void visit_load_resource(isel_context *ctx, nir_intrinsic_instr *instr)
4065 {
4066    Builder bld(ctx->program, ctx->block);
4067    Temp index = get_ssa_temp(ctx, instr->src[0].ssa);
4068    if (!ctx->divergent_vals[instr->dest.ssa.index])
4069       index = bld.as_uniform(index);
4070    unsigned desc_set = nir_intrinsic_desc_set(instr);
4071    unsigned binding = nir_intrinsic_binding(instr);
4072
4073    Temp desc_ptr;
4074    radv_pipeline_layout *pipeline_layout = ctx->options->layout;
4075    radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
4076    unsigned offset = layout->binding[binding].offset;
4077    unsigned stride;
4078    if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
4079        layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
4080       unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start + layout->binding[binding].dynamic_offset_offset;
4081       desc_ptr = get_arg(ctx, ctx->args->ac.push_constants);
4082       offset = pipeline_layout->push_constant_size + 16 * idx;
4083       stride = 16;
4084    } else {
4085       desc_ptr = load_desc_ptr(ctx, desc_set);
4086       stride = layout->binding[binding].size;
4087    }
4088
4089    nir_const_value* nir_const_index = nir_src_as_const_value(instr->src[0]);
4090    unsigned const_index = nir_const_index ? nir_const_index->u32 : 0;
4091    if (stride != 1) {
4092       if (nir_const_index) {
4093          const_index = const_index * stride;
4094       } else if (index.type() == RegType::vgpr) {
4095          bool index24bit = layout->binding[binding].array_size <= 0x1000000;
4096          index = bld.v_mul_imm(bld.def(v1), index, stride, index24bit);
4097       } else {
4098          index = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), Operand(index));
4099       }
4100    }
4101    if (offset) {
4102       if (nir_const_index) {
4103          const_index = const_index + offset;
4104       } else if (index.type() == RegType::vgpr) {
4105          index = bld.vadd32(bld.def(v1), Operand(offset), index);
4106       } else {
4107          index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset), Operand(index));
4108       }
4109    }
4110
4111    if (nir_const_index && const_index == 0) {
4112       index = desc_ptr;
4113    } else if (index.type() == RegType::vgpr) {
4114       index = bld.vadd32(bld.def(v1),
4115                          nir_const_index ? Operand(const_index) : Operand(index),
4116                          Operand(desc_ptr));
4117    } else {
4118       index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
4119                        nir_const_index ? Operand(const_index) : Operand(index),
4120                        Operand(desc_ptr));
4121    }
4122
4123    bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), index);
4124 }
4125
4126 void load_buffer(isel_context *ctx, unsigned num_components, Temp dst,
4127                  Temp rsrc, Temp offset, bool glc=false, bool readonly=true)
4128 {
4129    Builder bld(ctx->program, ctx->block);
4130
4131    unsigned num_bytes = dst.size() * 4;
4132    bool dlc = glc && ctx->options->chip_class >= GFX10;
4133
4134    aco_opcode op;
4135    if (dst.type() == RegType::vgpr || (ctx->options->chip_class < GFX8 && !readonly)) {
4136       Operand vaddr = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
4137       Operand soffset = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
4138       unsigned const_offset = 0;
4139
4140       Temp lower = Temp();
4141       if (num_bytes > 16) {
4142          assert(num_components == 3 || num_components == 4);
4143          op = aco_opcode::buffer_load_dwordx4;
4144          lower = bld.tmp(v4);
4145          aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
4146          mubuf->definitions[0] = Definition(lower);
4147          mubuf->operands[0] = Operand(rsrc);
4148          mubuf->operands[1] = vaddr;
4149          mubuf->operands[2] = soffset;
4150          mubuf->offen = (offset.type() == RegType::vgpr);
4151          mubuf->glc = glc;
4152          mubuf->dlc = dlc;
4153          mubuf->barrier = readonly ? barrier_none : barrier_buffer;
4154          mubuf->can_reorder = readonly;
4155          bld.insert(std::move(mubuf));
4156          emit_split_vector(ctx, lower, 2);
4157          num_bytes -= 16;
4158          const_offset = 16;
4159       } else if (num_bytes == 12 && ctx->options->chip_class == GFX6) {
4160          /* GFX6 doesn't support loading vec3, expand to vec4. */
4161          num_bytes = 16;
4162       }
4163
4164       switch (num_bytes) {
4165          case 4:
4166             op = aco_opcode::buffer_load_dword;
4167             break;
4168          case 8:
4169             op = aco_opcode::buffer_load_dwordx2;
4170             break;
4171          case 12:
4172             assert(ctx->options->chip_class > GFX6);
4173             op = aco_opcode::buffer_load_dwordx3;
4174             break;
4175          case 16:
4176             op = aco_opcode::buffer_load_dwordx4;
4177             break;
4178          default:
4179             unreachable("Load SSBO not implemented for this size.");
4180       }
4181       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
4182       mubuf->operands[0] = Operand(rsrc);
4183       mubuf->operands[1] = vaddr;
4184       mubuf->operands[2] = soffset;
4185       mubuf->offen = (offset.type() == RegType::vgpr);
4186       mubuf->glc = glc;
4187       mubuf->dlc = dlc;
4188       mubuf->barrier = readonly ? barrier_none : barrier_buffer;
4189       mubuf->can_reorder = readonly;
4190       mubuf->offset = const_offset;
4191       aco_ptr<Instruction> instr = std::move(mubuf);
4192
4193       if (dst.size() > 4) {
4194          assert(lower != Temp());
4195          Temp upper = bld.tmp(RegType::vgpr, dst.size() - lower.size());
4196          instr->definitions[0] = Definition(upper);
4197          bld.insert(std::move(instr));
4198          if (dst.size() == 8)
4199             emit_split_vector(ctx, upper, 2);
4200          instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size() / 2, 1));
4201          instr->operands[0] = Operand(emit_extract_vector(ctx, lower, 0, v2));
4202          instr->operands[1] = Operand(emit_extract_vector(ctx, lower, 1, v2));
4203          instr->operands[2] = Operand(emit_extract_vector(ctx, upper, 0, v2));
4204          if (dst.size() == 8)
4205             instr->operands[3] = Operand(emit_extract_vector(ctx, upper, 1, v2));
4206       } else if (dst.size() == 3 && ctx->options->chip_class == GFX6) {
4207          Temp vec = bld.tmp(v4);
4208          instr->definitions[0] = Definition(vec);
4209          bld.insert(std::move(instr));
4210          emit_split_vector(ctx, vec, 4);
4211
4212          instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, 3, 1));
4213          instr->operands[0] = Operand(emit_extract_vector(ctx, vec, 0, v1));
4214          instr->operands[1] = Operand(emit_extract_vector(ctx, vec, 1, v1));
4215          instr->operands[2] = Operand(emit_extract_vector(ctx, vec, 2, v1));
4216       }
4217
4218       if (dst.type() == RegType::sgpr) {
4219          Temp vec = bld.tmp(RegType::vgpr, dst.size());
4220          instr->definitions[0] = Definition(vec);
4221          bld.insert(std::move(instr));
4222          expand_vector(ctx, vec, dst, num_components, (1 << num_components) - 1);
4223       } else {
4224          instr->definitions[0] = Definition(dst);
4225          bld.insert(std::move(instr));
4226          emit_split_vector(ctx, dst, num_components);
4227       }
4228    } else {
4229       switch (num_bytes) {
4230          case 4:
4231             op = aco_opcode::s_buffer_load_dword;
4232             break;
4233          case 8:
4234             op = aco_opcode::s_buffer_load_dwordx2;
4235             break;
4236          case 12:
4237          case 16:
4238             op = aco_opcode::s_buffer_load_dwordx4;
4239             break;
4240          case 24:
4241          case 32:
4242             op = aco_opcode::s_buffer_load_dwordx8;
4243             break;
4244          default:
4245             unreachable("Load SSBO not implemented for this size.");
4246       }
4247       aco_ptr<SMEM_instruction> load{create_instruction<SMEM_instruction>(op, Format::SMEM, 2, 1)};
4248       load->operands[0] = Operand(rsrc);
4249       load->operands[1] = Operand(bld.as_uniform(offset));
4250       assert(load->operands[1].getTemp().type() == RegType::sgpr);
4251       load->definitions[0] = Definition(dst);
4252       load->glc = glc;
4253       load->dlc = dlc;
4254       load->barrier = readonly ? barrier_none : barrier_buffer;
4255       load->can_reorder = false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
4256       assert(ctx->options->chip_class >= GFX8 || !glc);
4257
4258       /* trim vector */
4259       if (dst.size() == 3) {
4260          Temp vec = bld.tmp(s4);
4261          load->definitions[0] = Definition(vec);
4262          bld.insert(std::move(load));
4263          emit_split_vector(ctx, vec, 4);
4264
4265          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4266                     emit_extract_vector(ctx, vec, 0, s1),
4267                     emit_extract_vector(ctx, vec, 1, s1),
4268                     emit_extract_vector(ctx, vec, 2, s1));
4269       } else if (dst.size() == 6) {
4270          Temp vec = bld.tmp(s8);
4271          load->definitions[0] = Definition(vec);
4272          bld.insert(std::move(load));
4273          emit_split_vector(ctx, vec, 4);
4274
4275          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4276                     emit_extract_vector(ctx, vec, 0, s2),
4277                     emit_extract_vector(ctx, vec, 1, s2),
4278                     emit_extract_vector(ctx, vec, 2, s2));
4279       } else {
4280          bld.insert(std::move(load));
4281       }
4282       emit_split_vector(ctx, dst, num_components);
4283    }
4284 }
4285
4286 void visit_load_ubo(isel_context *ctx, nir_intrinsic_instr *instr)
4287 {
4288    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4289    Temp rsrc = get_ssa_temp(ctx, instr->src[0].ssa);
4290
4291    Builder bld(ctx->program, ctx->block);
4292
4293    nir_intrinsic_instr* idx_instr = nir_instr_as_intrinsic(instr->src[0].ssa->parent_instr);
4294    unsigned desc_set = nir_intrinsic_desc_set(idx_instr);
4295    unsigned binding = nir_intrinsic_binding(idx_instr);
4296    radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
4297
4298    if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
4299       uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
4300                            S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
4301                            S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
4302                            S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
4303       if (ctx->options->chip_class >= GFX10) {
4304          desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
4305                       S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
4306                       S_008F0C_RESOURCE_LEVEL(1);
4307       } else {
4308          desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
4309                       S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
4310       }
4311       Temp upper_dwords = bld.pseudo(aco_opcode::p_create_vector, bld.def(s3),
4312                                      Operand(S_008F04_BASE_ADDRESS_HI(ctx->options->address32_hi)),
4313                                      Operand(0xFFFFFFFFu),
4314                                      Operand(desc_type));
4315       rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
4316                         rsrc, upper_dwords);
4317    } else {
4318       rsrc = convert_pointer_to_64_bit(ctx, rsrc);
4319       rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
4320    }
4321
4322    load_buffer(ctx, instr->num_components, dst, rsrc, get_ssa_temp(ctx, instr->src[1].ssa));
4323 }
4324
4325 void visit_load_push_constant(isel_context *ctx, nir_intrinsic_instr *instr)
4326 {
4327    Builder bld(ctx->program, ctx->block);
4328    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4329
4330    unsigned offset = nir_intrinsic_base(instr);
4331    nir_const_value *index_cv = nir_src_as_const_value(instr->src[0]);
4332    if (index_cv && instr->dest.ssa.bit_size == 32) {
4333
4334       unsigned count = instr->dest.ssa.num_components;
4335       unsigned start = (offset + index_cv->u32) / 4u;
4336       start -= ctx->args->ac.base_inline_push_consts;
4337       if (start + count <= ctx->args->ac.num_inline_push_consts) {
4338          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
4339          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
4340          for (unsigned i = 0; i < count; ++i) {
4341             elems[i] = get_arg(ctx, ctx->args->ac.inline_push_consts[start + i]);
4342             vec->operands[i] = Operand{elems[i]};
4343          }
4344          vec->definitions[0] = Definition(dst);
4345          ctx->block->instructions.emplace_back(std::move(vec));
4346          ctx->allocated_vec.emplace(dst.id(), elems);
4347          return;
4348       }
4349    }
4350
4351    Temp index = bld.as_uniform(get_ssa_temp(ctx, instr->src[0].ssa));
4352    if (offset != 0) // TODO check if index != 0 as well
4353       index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset), index);
4354    Temp ptr = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->ac.push_constants));
4355    Temp vec = dst;
4356    bool trim = false;
4357    aco_opcode op;
4358
4359    switch (dst.size()) {
4360    case 1:
4361       op = aco_opcode::s_load_dword;
4362       break;
4363    case 2:
4364       op = aco_opcode::s_load_dwordx2;
4365       break;
4366    case 3:
4367       vec = bld.tmp(s4);
4368       trim = true;
4369    case 4:
4370       op = aco_opcode::s_load_dwordx4;
4371       break;
4372    case 6:
4373       vec = bld.tmp(s8);
4374       trim = true;
4375    case 8:
4376       op = aco_opcode::s_load_dwordx8;
4377       break;
4378    default:
4379       unreachable("unimplemented or forbidden load_push_constant.");
4380    }
4381
4382    bld.smem(op, Definition(vec), ptr, index);
4383
4384    if (trim) {
4385       emit_split_vector(ctx, vec, 4);
4386       RegClass rc = dst.size() == 3 ? s1 : s2;
4387       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4388                  emit_extract_vector(ctx, vec, 0, rc),
4389                  emit_extract_vector(ctx, vec, 1, rc),
4390                  emit_extract_vector(ctx, vec, 2, rc));
4391
4392    }
4393    emit_split_vector(ctx, dst, instr->dest.ssa.num_components);
4394 }
4395
4396 void visit_load_constant(isel_context *ctx, nir_intrinsic_instr *instr)
4397 {
4398    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4399
4400    Builder bld(ctx->program, ctx->block);
4401
4402    uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
4403                         S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
4404                         S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
4405                         S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
4406    if (ctx->options->chip_class >= GFX10) {
4407       desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
4408                    S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
4409                    S_008F0C_RESOURCE_LEVEL(1);
4410    } else {
4411       desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
4412                    S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
4413    }
4414
4415    unsigned base = nir_intrinsic_base(instr);
4416    unsigned range = nir_intrinsic_range(instr);
4417
4418    Temp offset = get_ssa_temp(ctx, instr->src[0].ssa);
4419    if (base && offset.type() == RegType::sgpr)
4420       offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), offset, Operand(base));
4421    else if (base && offset.type() == RegType::vgpr)
4422       offset = bld.vadd32(bld.def(v1), Operand(base), offset);
4423
4424    Temp rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
4425                           bld.sop1(aco_opcode::p_constaddr, bld.def(s2), bld.def(s1, scc), Operand(ctx->constant_data_offset)),
4426                           Operand(MIN2(base + range, ctx->shader->constant_data_size)),
4427                           Operand(desc_type));
4428
4429    load_buffer(ctx, instr->num_components, dst, rsrc, offset);
4430 }
4431
4432 void visit_discard_if(isel_context *ctx, nir_intrinsic_instr *instr)
4433 {
4434    if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
4435       ctx->cf_info.exec_potentially_empty_discard = true;
4436
4437    ctx->program->needs_exact = true;
4438
4439    // TODO: optimize uniform conditions
4440    Builder bld(ctx->program, ctx->block);
4441    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
4442    assert(src.regClass() == bld.lm);
4443    src = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
4444    bld.pseudo(aco_opcode::p_discard_if, src);
4445    ctx->block->kind |= block_kind_uses_discard_if;
4446    return;
4447 }
4448
4449 void visit_discard(isel_context* ctx, nir_intrinsic_instr *instr)
4450 {
4451    Builder bld(ctx->program, ctx->block);
4452
4453    if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
4454       ctx->cf_info.exec_potentially_empty_discard = true;
4455
4456    bool divergent = ctx->cf_info.parent_if.is_divergent ||
4457                     ctx->cf_info.parent_loop.has_divergent_continue;
4458
4459    if (ctx->block->loop_nest_depth &&
4460        ((nir_instr_is_last(&instr->instr) && !divergent) || divergent)) {
4461       /* we handle discards the same way as jump instructions */
4462       append_logical_end(ctx->block);
4463
4464       /* in loops, discard behaves like break */
4465       Block *linear_target = ctx->cf_info.parent_loop.exit;
4466       ctx->block->kind |= block_kind_discard;
4467
4468       if (!divergent) {
4469          /* uniform discard - loop ends here */
4470          assert(nir_instr_is_last(&instr->instr));
4471          ctx->block->kind |= block_kind_uniform;
4472          ctx->cf_info.has_branch = true;
4473          bld.branch(aco_opcode::p_branch);
4474          add_linear_edge(ctx->block->index, linear_target);
4475          return;
4476       }
4477
4478       /* we add a break right behind the discard() instructions */
4479       ctx->block->kind |= block_kind_break;
4480       unsigned idx = ctx->block->index;
4481
4482       ctx->cf_info.parent_loop.has_divergent_branch = true;
4483       ctx->cf_info.nir_to_aco[instr->instr.block->index] = idx;
4484
4485       /* remove critical edges from linear CFG */
4486       bld.branch(aco_opcode::p_branch);
4487       Block* break_block = ctx->program->create_and_insert_block();
4488       break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
4489       break_block->kind |= block_kind_uniform;
4490       add_linear_edge(idx, break_block);
4491       add_linear_edge(break_block->index, linear_target);
4492       bld.reset(break_block);
4493       bld.branch(aco_opcode::p_branch);
4494
4495       Block* continue_block = ctx->program->create_and_insert_block();
4496       continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
4497       add_linear_edge(idx, continue_block);
4498       append_logical_start(continue_block);
4499       ctx->block = continue_block;
4500
4501       return;
4502    }
4503
4504    /* it can currently happen that NIR doesn't remove the unreachable code */
4505    if (!nir_instr_is_last(&instr->instr)) {
4506       ctx->program->needs_exact = true;
4507       /* save exec somewhere temporarily so that it doesn't get
4508        * overwritten before the discard from outer exec masks */
4509       Temp cond = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), Operand(0xFFFFFFFF), Operand(exec, bld.lm));
4510       bld.pseudo(aco_opcode::p_discard_if, cond);
4511       ctx->block->kind |= block_kind_uses_discard_if;
4512       return;
4513    }
4514
4515    /* This condition is incorrect for uniformly branched discards in a loop
4516     * predicated by a divergent condition, but the above code catches that case
4517     * and the discard would end up turning into a discard_if.
4518     * For example:
4519     * if (divergent) {
4520     *    while (...) {
4521     *       if (uniform) {
4522     *          discard;
4523     *       }
4524     *    }
4525     * }
4526     */
4527    if (!ctx->cf_info.parent_if.is_divergent) {
4528       /* program just ends here */
4529       ctx->block->kind |= block_kind_uniform;
4530       bld.exp(aco_opcode::exp, Operand(v1), Operand(v1), Operand(v1), Operand(v1),
4531               0 /* enabled mask */, 9 /* dest */,
4532               false /* compressed */, true/* done */, true /* valid mask */);
4533       bld.sopp(aco_opcode::s_endpgm);
4534       // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
4535    } else {
4536       ctx->block->kind |= block_kind_discard;
4537       /* branch and linear edge is added by visit_if() */
4538    }
4539 }
4540
4541 enum aco_descriptor_type {
4542    ACO_DESC_IMAGE,
4543    ACO_DESC_FMASK,
4544    ACO_DESC_SAMPLER,
4545    ACO_DESC_BUFFER,
4546    ACO_DESC_PLANE_0,
4547    ACO_DESC_PLANE_1,
4548    ACO_DESC_PLANE_2,
4549 };
4550
4551 static bool
4552 should_declare_array(isel_context *ctx, enum glsl_sampler_dim sampler_dim, bool is_array) {
4553    if (sampler_dim == GLSL_SAMPLER_DIM_BUF)
4554       return false;
4555    ac_image_dim dim = ac_get_sampler_dim(ctx->options->chip_class, sampler_dim, is_array);
4556    return dim == ac_image_cube ||
4557           dim == ac_image_1darray ||
4558           dim == ac_image_2darray ||
4559           dim == ac_image_2darraymsaa;
4560 }
4561
4562 Temp get_sampler_desc(isel_context *ctx, nir_deref_instr *deref_instr,
4563                       enum aco_descriptor_type desc_type,
4564                       const nir_tex_instr *tex_instr, bool image, bool write)
4565 {
4566 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
4567    std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
4568    if (it != ctx->tex_desc.end())
4569       return it->second;
4570 */
4571    Temp index = Temp();
4572    bool index_set = false;
4573    unsigned constant_index = 0;
4574    unsigned descriptor_set;
4575    unsigned base_index;
4576    Builder bld(ctx->program, ctx->block);
4577
4578    if (!deref_instr) {
4579       assert(tex_instr && !image);
4580       descriptor_set = 0;
4581       base_index = tex_instr->sampler_index;
4582    } else {
4583       while(deref_instr->deref_type != nir_deref_type_var) {
4584          unsigned array_size = glsl_get_aoa_size(deref_instr->type);
4585          if (!array_size)
4586             array_size = 1;
4587
4588          assert(deref_instr->deref_type == nir_deref_type_array);
4589          nir_const_value *const_value = nir_src_as_const_value(deref_instr->arr.index);
4590          if (const_value) {
4591             constant_index += array_size * const_value->u32;
4592          } else {
4593             Temp indirect = get_ssa_temp(ctx, deref_instr->arr.index.ssa);
4594             if (indirect.type() == RegType::vgpr)
4595                indirect = bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), indirect);
4596
4597             if (array_size != 1)
4598                indirect = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(array_size), indirect);
4599
4600             if (!index_set) {
4601                index = indirect;
4602                index_set = true;
4603             } else {
4604                index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), index, indirect);
4605             }
4606          }
4607
4608          deref_instr = nir_src_as_deref(deref_instr->parent);
4609       }
4610       descriptor_set = deref_instr->var->data.descriptor_set;
4611       base_index = deref_instr->var->data.binding;
4612    }
4613
4614    Temp list = load_desc_ptr(ctx, descriptor_set);
4615    list = convert_pointer_to_64_bit(ctx, list);
4616
4617    struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4618    struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4619    unsigned offset = binding->offset;
4620    unsigned stride = binding->size;
4621    aco_opcode opcode;
4622    RegClass type;
4623
4624    assert(base_index < layout->binding_count);
4625
4626    switch (desc_type) {
4627    case ACO_DESC_IMAGE:
4628       type = s8;
4629       opcode = aco_opcode::s_load_dwordx8;
4630       break;
4631    case ACO_DESC_FMASK:
4632       type = s8;
4633       opcode = aco_opcode::s_load_dwordx8;
4634       offset += 32;
4635       break;
4636    case ACO_DESC_SAMPLER:
4637       type = s4;
4638       opcode = aco_opcode::s_load_dwordx4;
4639       if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4640          offset += radv_combined_image_descriptor_sampler_offset(binding);
4641       break;
4642    case ACO_DESC_BUFFER:
4643       type = s4;
4644       opcode = aco_opcode::s_load_dwordx4;
4645       break;
4646    case ACO_DESC_PLANE_0:
4647    case ACO_DESC_PLANE_1:
4648       type = s8;
4649       opcode = aco_opcode::s_load_dwordx8;
4650       offset += 32 * (desc_type - ACO_DESC_PLANE_0);
4651       break;
4652    case ACO_DESC_PLANE_2:
4653       type = s4;
4654       opcode = aco_opcode::s_load_dwordx4;
4655       offset += 64;
4656       break;
4657    default:
4658       unreachable("invalid desc_type\n");
4659    }
4660
4661    offset += constant_index * stride;
4662
4663    if (desc_type == ACO_DESC_SAMPLER && binding->immutable_samplers_offset &&
4664       (!index_set || binding->immutable_samplers_equal)) {
4665       if (binding->immutable_samplers_equal)
4666          constant_index = 0;
4667
4668       const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4669       return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
4670                         Operand(samplers[constant_index * 4 + 0]),
4671                         Operand(samplers[constant_index * 4 + 1]),
4672                         Operand(samplers[constant_index * 4 + 2]),
4673                         Operand(samplers[constant_index * 4 + 3]));
4674    }
4675
4676    Operand off;
4677    if (!index_set) {
4678       off = bld.copy(bld.def(s1), Operand(offset));
4679    } else {
4680       off = Operand((Temp)bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset),
4681                                    bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), index)));
4682    }
4683
4684    Temp res = bld.smem(opcode, bld.def(type), list, off);
4685
4686    if (desc_type == ACO_DESC_PLANE_2) {
4687       Temp components[8];
4688       for (unsigned i = 0; i < 8; i++)
4689          components[i] = bld.tmp(s1);
4690       bld.pseudo(aco_opcode::p_split_vector,
4691                  Definition(components[0]),
4692                  Definition(components[1]),
4693                  Definition(components[2]),
4694                  Definition(components[3]),
4695                  res);
4696
4697       Temp desc2 = get_sampler_desc(ctx, deref_instr, ACO_DESC_PLANE_1, tex_instr, image, write);
4698       bld.pseudo(aco_opcode::p_split_vector,
4699                  bld.def(s1), bld.def(s1), bld.def(s1), bld.def(s1),
4700                  Definition(components[4]),
4701                  Definition(components[5]),
4702                  Definition(components[6]),
4703                  Definition(components[7]),
4704                  desc2);
4705
4706       res = bld.pseudo(aco_opcode::p_create_vector, bld.def(s8),
4707                        components[0], components[1], components[2], components[3],
4708                        components[4], components[5], components[6], components[7]);
4709    }
4710
4711    return res;
4712 }
4713
4714 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
4715 {
4716    switch (dim) {
4717    case GLSL_SAMPLER_DIM_BUF:
4718       return 1;
4719    case GLSL_SAMPLER_DIM_1D:
4720       return array ? 2 : 1;
4721    case GLSL_SAMPLER_DIM_2D:
4722       return array ? 3 : 2;
4723    case GLSL_SAMPLER_DIM_MS:
4724       return array ? 4 : 3;
4725    case GLSL_SAMPLER_DIM_3D:
4726    case GLSL_SAMPLER_DIM_CUBE:
4727       return 3;
4728    case GLSL_SAMPLER_DIM_RECT:
4729    case GLSL_SAMPLER_DIM_SUBPASS:
4730       return 2;
4731    case GLSL_SAMPLER_DIM_SUBPASS_MS:
4732       return 3;
4733    default:
4734       break;
4735    }
4736    return 0;
4737 }
4738
4739
4740 /* Adjust the sample index according to FMASK.
4741  *
4742  * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4743  * which is the identity mapping. Each nibble says which physical sample
4744  * should be fetched to get that sample.
4745  *
4746  * For example, 0x11111100 means there are only 2 samples stored and
4747  * the second sample covers 3/4 of the pixel. When reading samples 0
4748  * and 1, return physical sample 0 (determined by the first two 0s
4749  * in FMASK), otherwise return physical sample 1.
4750  *
4751  * The sample index should be adjusted as follows:
4752  *   sample_index = (fmask >> (sample_index * 4)) & 0xF;
4753  */
4754 static Temp adjust_sample_index_using_fmask(isel_context *ctx, bool da, std::vector<Temp>& coords, Operand sample_index, Temp fmask_desc_ptr)
4755 {
4756    Builder bld(ctx->program, ctx->block);
4757    Temp fmask = bld.tmp(v1);
4758    unsigned dim = ctx->options->chip_class >= GFX10
4759                   ? ac_get_sampler_dim(ctx->options->chip_class, GLSL_SAMPLER_DIM_2D, da)
4760                   : 0;
4761
4762    Temp coord = da ? bld.pseudo(aco_opcode::p_create_vector, bld.def(v3), coords[0], coords[1], coords[2]) :
4763                      bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), coords[0], coords[1]);
4764    aco_ptr<MIMG_instruction> load{create_instruction<MIMG_instruction>(aco_opcode::image_load, Format::MIMG, 3, 1)};
4765    load->operands[0] = Operand(fmask_desc_ptr);
4766    load->operands[1] = Operand(s4); /* no sampler */
4767    load->operands[2] = Operand(coord);
4768    load->definitions[0] = Definition(fmask);
4769    load->glc = false;
4770    load->dlc = false;
4771    load->dmask = 0x1;
4772    load->unrm = true;
4773    load->da = da;
4774    load->dim = dim;
4775    load->can_reorder = true; /* fmask images shouldn't be modified */
4776    ctx->block->instructions.emplace_back(std::move(load));
4777
4778    Operand sample_index4;
4779    if (sample_index.isConstant() && sample_index.constantValue() < 16) {
4780       sample_index4 = Operand(sample_index.constantValue() << 2);
4781    } else if (sample_index.regClass() == s1) {
4782       sample_index4 = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), sample_index, Operand(2u));
4783    } else {
4784       assert(sample_index.regClass() == v1);
4785       sample_index4 = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), sample_index);
4786    }
4787
4788    Temp final_sample;
4789    if (sample_index4.isConstant() && sample_index4.constantValue() == 0)
4790       final_sample = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(15u), fmask);
4791    else if (sample_index4.isConstant() && sample_index4.constantValue() == 28)
4792       final_sample = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(28u), fmask);
4793    else
4794       final_sample = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1), fmask, sample_index4, Operand(4u));
4795
4796    /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4797     * resource descriptor is 0 (invalid),
4798     */
4799    Temp compare = bld.tmp(bld.lm);
4800    bld.vopc_e64(aco_opcode::v_cmp_lg_u32, Definition(compare),
4801                 Operand(0u), emit_extract_vector(ctx, fmask_desc_ptr, 1, s1)).def(0).setHint(vcc);
4802
4803    Temp sample_index_v = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), sample_index);
4804
4805    /* Replace the MSAA sample index. */
4806    return bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), sample_index_v, final_sample, compare);
4807 }
4808
4809 static Temp get_image_coords(isel_context *ctx, const nir_intrinsic_instr *instr, const struct glsl_type *type)
4810 {
4811
4812    Temp src0 = get_ssa_temp(ctx, instr->src[1].ssa);
4813    enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4814    bool is_array = glsl_sampler_type_is_array(type);
4815    ASSERTED bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS || dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
4816    assert(!add_frag_pos && "Input attachments should be lowered.");
4817    bool is_ms = (dim == GLSL_SAMPLER_DIM_MS || dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
4818    bool gfx9_1d = ctx->options->chip_class == GFX9 && dim == GLSL_SAMPLER_DIM_1D;
4819    int count = image_type_to_components_count(dim, is_array);
4820    std::vector<Temp> coords(count);
4821    Builder bld(ctx->program, ctx->block);
4822
4823    if (is_ms) {
4824       count--;
4825       Temp src2 = get_ssa_temp(ctx, instr->src[2].ssa);
4826       /* get sample index */
4827       if (instr->intrinsic == nir_intrinsic_image_deref_load) {
4828          nir_const_value *sample_cv = nir_src_as_const_value(instr->src[2]);
4829          Operand sample_index = sample_cv ? Operand(sample_cv->u32) : Operand(emit_extract_vector(ctx, src2, 0, v1));
4830          std::vector<Temp> fmask_load_address;
4831          for (unsigned i = 0; i < (is_array ? 3 : 2); i++)
4832             fmask_load_address.emplace_back(emit_extract_vector(ctx, src0, i, v1));
4833
4834          Temp fmask_desc_ptr = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_FMASK, nullptr, false, false);
4835          coords[count] = adjust_sample_index_using_fmask(ctx, is_array, fmask_load_address, sample_index, fmask_desc_ptr);
4836       } else {
4837          coords[count] = emit_extract_vector(ctx, src2, 0, v1);
4838       }
4839    }
4840
4841    if (gfx9_1d) {
4842       coords[0] = emit_extract_vector(ctx, src0, 0, v1);
4843       coords.resize(coords.size() + 1);
4844       coords[1] = bld.copy(bld.def(v1), Operand(0u));
4845       if (is_array)
4846          coords[2] = emit_extract_vector(ctx, src0, 1, v1);
4847    } else {
4848       for (int i = 0; i < count; i++)
4849          coords[i] = emit_extract_vector(ctx, src0, i, v1);
4850    }
4851
4852    if (instr->intrinsic == nir_intrinsic_image_deref_load ||
4853        instr->intrinsic == nir_intrinsic_image_deref_store) {
4854       int lod_index = instr->intrinsic == nir_intrinsic_image_deref_load ? 3 : 4;
4855       bool level_zero = nir_src_is_const(instr->src[lod_index]) && nir_src_as_uint(instr->src[lod_index]) == 0;
4856
4857       if (!level_zero)
4858          coords.emplace_back(get_ssa_temp(ctx, instr->src[lod_index].ssa));
4859    }
4860
4861    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, coords.size(), 1)};
4862    for (unsigned i = 0; i < coords.size(); i++)
4863       vec->operands[i] = Operand(coords[i]);
4864    Temp res = {ctx->program->allocateId(), RegClass(RegType::vgpr, coords.size())};
4865    vec->definitions[0] = Definition(res);
4866    ctx->block->instructions.emplace_back(std::move(vec));
4867    return res;
4868 }
4869
4870
4871 void visit_image_load(isel_context *ctx, nir_intrinsic_instr *instr)
4872 {
4873    Builder bld(ctx->program, ctx->block);
4874    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4875    const struct glsl_type *type = glsl_without_array(var->type);
4876    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4877    bool is_array = glsl_sampler_type_is_array(type);
4878    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4879
4880    if (dim == GLSL_SAMPLER_DIM_BUF) {
4881       unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
4882       unsigned num_channels = util_last_bit(mask);
4883       Temp rsrc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4884       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4885
4886       aco_opcode opcode;
4887       switch (num_channels) {
4888       case 1:
4889          opcode = aco_opcode::buffer_load_format_x;
4890          break;
4891       case 2:
4892          opcode = aco_opcode::buffer_load_format_xy;
4893          break;
4894       case 3:
4895          opcode = aco_opcode::buffer_load_format_xyz;
4896          break;
4897       case 4:
4898          opcode = aco_opcode::buffer_load_format_xyzw;
4899          break;
4900       default:
4901          unreachable(">4 channel buffer image load");
4902       }
4903       aco_ptr<MUBUF_instruction> load{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 3, 1)};
4904       load->operands[0] = Operand(rsrc);
4905       load->operands[1] = Operand(vindex);
4906       load->operands[2] = Operand((uint32_t) 0);
4907       Temp tmp;
4908       if (num_channels == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
4909          tmp = dst;
4910       else
4911          tmp = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_channels)};
4912       load->definitions[0] = Definition(tmp);
4913       load->idxen = true;
4914       load->glc = var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT);
4915       load->dlc = load->glc && ctx->options->chip_class >= GFX10;
4916       load->barrier = barrier_image;
4917       ctx->block->instructions.emplace_back(std::move(load));
4918
4919       expand_vector(ctx, tmp, dst, instr->dest.ssa.num_components, (1 << num_channels) - 1);
4920       return;
4921    }
4922
4923    Temp coords = get_image_coords(ctx, instr, type);
4924    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
4925
4926    unsigned dmask = nir_ssa_def_components_read(&instr->dest.ssa);
4927    unsigned num_components = util_bitcount(dmask);
4928    Temp tmp;
4929    if (num_components == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
4930       tmp = dst;
4931    else
4932       tmp = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_components)};
4933
4934    bool level_zero = nir_src_is_const(instr->src[3]) && nir_src_as_uint(instr->src[3]) == 0;
4935    aco_opcode opcode = level_zero ? aco_opcode::image_load : aco_opcode::image_load_mip;
4936
4937    aco_ptr<MIMG_instruction> load{create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 1)};
4938    load->operands[0] = Operand(resource);
4939    load->operands[1] = Operand(s4); /* no sampler */
4940    load->operands[2] = Operand(coords);
4941    load->definitions[0] = Definition(tmp);
4942    load->glc = var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT) ? 1 : 0;
4943    load->dlc = load->glc && ctx->options->chip_class >= GFX10;
4944    load->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4945    load->dmask = dmask;
4946    load->unrm = true;
4947    load->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
4948    load->barrier = barrier_image;
4949    ctx->block->instructions.emplace_back(std::move(load));
4950
4951    expand_vector(ctx, tmp, dst, instr->dest.ssa.num_components, dmask);
4952    return;
4953 }
4954
4955 void visit_image_store(isel_context *ctx, nir_intrinsic_instr *instr)
4956 {
4957    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4958    const struct glsl_type *type = glsl_without_array(var->type);
4959    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4960    bool is_array = glsl_sampler_type_is_array(type);
4961    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[3].ssa));
4962
4963    bool glc = ctx->options->chip_class == GFX6 || var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE) ? 1 : 0;
4964
4965    if (dim == GLSL_SAMPLER_DIM_BUF) {
4966       Temp rsrc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4967       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4968       aco_opcode opcode;
4969       switch (data.size()) {
4970       case 1:
4971          opcode = aco_opcode::buffer_store_format_x;
4972          break;
4973       case 2:
4974          opcode = aco_opcode::buffer_store_format_xy;
4975          break;
4976       case 3:
4977          opcode = aco_opcode::buffer_store_format_xyz;
4978          break;
4979       case 4:
4980          opcode = aco_opcode::buffer_store_format_xyzw;
4981          break;
4982       default:
4983          unreachable(">4 channel buffer image store");
4984       }
4985       aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 4, 0)};
4986       store->operands[0] = Operand(rsrc);
4987       store->operands[1] = Operand(vindex);
4988       store->operands[2] = Operand((uint32_t) 0);
4989       store->operands[3] = Operand(data);
4990       store->idxen = true;
4991       store->glc = glc;
4992       store->dlc = false;
4993       store->disable_wqm = true;
4994       store->barrier = barrier_image;
4995       ctx->program->needs_exact = true;
4996       ctx->block->instructions.emplace_back(std::move(store));
4997       return;
4998    }
4999
5000    assert(data.type() == RegType::vgpr);
5001    Temp coords = get_image_coords(ctx, instr, type);
5002    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
5003
5004    bool level_zero = nir_src_is_const(instr->src[4]) && nir_src_as_uint(instr->src[4]) == 0;
5005    aco_opcode opcode = level_zero ? aco_opcode::image_store : aco_opcode::image_store_mip;
5006
5007    aco_ptr<MIMG_instruction> store{create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 0)};
5008    store->operands[0] = Operand(resource);
5009    store->operands[1] = Operand(data);
5010    store->operands[2] = Operand(coords);
5011    store->glc = glc;
5012    store->dlc = false;
5013    store->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
5014    store->dmask = (1 << data.size()) - 1;
5015    store->unrm = true;
5016    store->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
5017    store->disable_wqm = true;
5018    store->barrier = barrier_image;
5019    ctx->program->needs_exact = true;
5020    ctx->block->instructions.emplace_back(std::move(store));
5021    return;
5022 }
5023
5024 void visit_image_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
5025 {
5026    /* return the previous value if dest is ever used */
5027    bool return_previous = false;
5028    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
5029       return_previous = true;
5030       break;
5031    }
5032    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
5033       return_previous = true;
5034       break;
5035    }
5036
5037    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
5038    const struct glsl_type *type = glsl_without_array(var->type);
5039    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
5040    bool is_array = glsl_sampler_type_is_array(type);
5041    Builder bld(ctx->program, ctx->block);
5042
5043    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[3].ssa));
5044    assert(data.size() == 1 && "64bit ssbo atomics not yet implemented.");
5045
5046    if (instr->intrinsic == nir_intrinsic_image_deref_atomic_comp_swap)
5047       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), get_ssa_temp(ctx, instr->src[4].ssa), data);
5048
5049    aco_opcode buf_op, image_op;
5050    switch (instr->intrinsic) {
5051       case nir_intrinsic_image_deref_atomic_add:
5052          buf_op = aco_opcode::buffer_atomic_add;
5053          image_op = aco_opcode::image_atomic_add;
5054          break;
5055       case nir_intrinsic_image_deref_atomic_umin:
5056          buf_op = aco_opcode::buffer_atomic_umin;
5057          image_op = aco_opcode::image_atomic_umin;
5058          break;
5059       case nir_intrinsic_image_deref_atomic_imin:
5060          buf_op = aco_opcode::buffer_atomic_smin;
5061          image_op = aco_opcode::image_atomic_smin;
5062          break;
5063       case nir_intrinsic_image_deref_atomic_umax:
5064          buf_op = aco_opcode::buffer_atomic_umax;
5065          image_op = aco_opcode::image_atomic_umax;
5066          break;
5067       case nir_intrinsic_image_deref_atomic_imax:
5068          buf_op = aco_opcode::buffer_atomic_smax;
5069          image_op = aco_opcode::image_atomic_smax;
5070          break;
5071       case nir_intrinsic_image_deref_atomic_and:
5072          buf_op = aco_opcode::buffer_atomic_and;
5073          image_op = aco_opcode::image_atomic_and;
5074          break;
5075       case nir_intrinsic_image_deref_atomic_or:
5076          buf_op = aco_opcode::buffer_atomic_or;
5077          image_op = aco_opcode::image_atomic_or;
5078          break;
5079       case nir_intrinsic_image_deref_atomic_xor:
5080          buf_op = aco_opcode::buffer_atomic_xor;
5081          image_op = aco_opcode::image_atomic_xor;
5082          break;
5083       case nir_intrinsic_image_deref_atomic_exchange:
5084          buf_op = aco_opcode::buffer_atomic_swap;
5085          image_op = aco_opcode::image_atomic_swap;
5086          break;
5087       case nir_intrinsic_image_deref_atomic_comp_swap:
5088          buf_op = aco_opcode::buffer_atomic_cmpswap;
5089          image_op = aco_opcode::image_atomic_cmpswap;
5090          break;
5091       default:
5092          unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5093    }
5094
5095    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5096
5097    if (dim == GLSL_SAMPLER_DIM_BUF) {
5098       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
5099       Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
5100       //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5101       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(buf_op, Format::MUBUF, 4, return_previous ? 1 : 0)};
5102       mubuf->operands[0] = Operand(resource);
5103       mubuf->operands[1] = Operand(vindex);
5104       mubuf->operands[2] = Operand((uint32_t)0);
5105       mubuf->operands[3] = Operand(data);
5106       if (return_previous)
5107          mubuf->definitions[0] = Definition(dst);
5108       mubuf->offset = 0;
5109       mubuf->idxen = true;
5110       mubuf->glc = return_previous;
5111       mubuf->dlc = false; /* Not needed for atomics */
5112       mubuf->disable_wqm = true;
5113       mubuf->barrier = barrier_image;
5114       ctx->program->needs_exact = true;
5115       ctx->block->instructions.emplace_back(std::move(mubuf));
5116       return;
5117    }
5118
5119    Temp coords = get_image_coords(ctx, instr, type);
5120    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
5121    aco_ptr<MIMG_instruction> mimg{create_instruction<MIMG_instruction>(image_op, Format::MIMG, 3, return_previous ? 1 : 0)};
5122    mimg->operands[0] = Operand(resource);
5123    mimg->operands[1] = Operand(data);
5124    mimg->operands[2] = Operand(coords);
5125    if (return_previous)
5126       mimg->definitions[0] = Definition(dst);
5127    mimg->glc = return_previous;
5128    mimg->dlc = false; /* Not needed for atomics */
5129    mimg->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
5130    mimg->dmask = (1 << data.size()) - 1;
5131    mimg->unrm = true;
5132    mimg->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
5133    mimg->disable_wqm = true;
5134    mimg->barrier = barrier_image;
5135    ctx->program->needs_exact = true;
5136    ctx->block->instructions.emplace_back(std::move(mimg));
5137    return;
5138 }
5139
5140 void get_buffer_size(isel_context *ctx, Temp desc, Temp dst, bool in_elements)
5141 {
5142    if (in_elements && ctx->options->chip_class == GFX8) {
5143       /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
5144       Builder bld(ctx->program, ctx->block);
5145
5146       Temp size = emit_extract_vector(ctx, desc, 2, s1);
5147
5148       Temp size_div3 = bld.vop3(aco_opcode::v_mul_hi_u32, bld.def(v1), bld.copy(bld.def(v1), Operand(0xaaaaaaabu)), size);
5149       size_div3 = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.as_uniform(size_div3), Operand(1u));
5150
5151       Temp stride = emit_extract_vector(ctx, desc, 1, s1);
5152       stride = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), stride, Operand((5u << 16) | 16u));
5153
5154       Temp is12 = bld.sopc(aco_opcode::s_cmp_eq_i32, bld.def(s1, scc), stride, Operand(12u));
5155       size = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), size_div3, size, bld.scc(is12));
5156
5157       Temp shr_dst = dst.type() == RegType::vgpr ? bld.tmp(s1) : dst;
5158       bld.sop2(aco_opcode::s_lshr_b32, Definition(shr_dst), bld.def(s1, scc),
5159                size, bld.sop1(aco_opcode::s_ff1_i32_b32, bld.def(s1), stride));
5160       if (dst.type() == RegType::vgpr)
5161          bld.copy(Definition(dst), shr_dst);
5162
5163       /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
5164    } else {
5165       emit_extract_vector(ctx, desc, 2, dst);
5166    }
5167 }
5168
5169 void visit_image_size(isel_context *ctx, nir_intrinsic_instr *instr)
5170 {
5171    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
5172    const struct glsl_type *type = glsl_without_array(var->type);
5173    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
5174    bool is_array = glsl_sampler_type_is_array(type);
5175    Builder bld(ctx->program, ctx->block);
5176
5177    if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
5178       Temp desc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, NULL, true, false);
5179       return get_buffer_size(ctx, desc, get_ssa_temp(ctx, &instr->dest.ssa), true);
5180    }
5181
5182    /* LOD */
5183    Temp lod = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
5184
5185    /* Resource */
5186    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, NULL, true, false);
5187
5188    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5189
5190    aco_ptr<MIMG_instruction> mimg{create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 3, 1)};
5191    mimg->operands[0] = Operand(resource);
5192    mimg->operands[1] = Operand(s4); /* no sampler */
5193    mimg->operands[2] = Operand(lod);
5194    uint8_t& dmask = mimg->dmask;
5195    mimg->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
5196    mimg->dmask = (1 << instr->dest.ssa.num_components) - 1;
5197    mimg->da = glsl_sampler_type_is_array(type);
5198    mimg->can_reorder = true;
5199    Definition& def = mimg->definitions[0];
5200    ctx->block->instructions.emplace_back(std::move(mimg));
5201
5202    if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
5203        glsl_sampler_type_is_array(type)) {
5204
5205       assert(instr->dest.ssa.num_components == 3);
5206       Temp tmp = {ctx->program->allocateId(), v3};
5207       def = Definition(tmp);
5208       emit_split_vector(ctx, tmp, 3);
5209
5210       /* divide 3rd value by 6 by multiplying with magic number */
5211       Temp c = bld.copy(bld.def(s1), Operand((uint32_t) 0x2AAAAAAB));
5212       Temp by_6 = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), emit_extract_vector(ctx, tmp, 2, v1), c);
5213
5214       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
5215                  emit_extract_vector(ctx, tmp, 0, v1),
5216                  emit_extract_vector(ctx, tmp, 1, v1),
5217                  by_6);
5218
5219    } else if (ctx->options->chip_class == GFX9 &&
5220               glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
5221               glsl_sampler_type_is_array(type)) {
5222       assert(instr->dest.ssa.num_components == 2);
5223       def = Definition(dst);
5224       dmask = 0x5;
5225    } else {
5226       def = Definition(dst);
5227    }
5228
5229    emit_split_vector(ctx, dst, instr->dest.ssa.num_components);
5230 }
5231
5232 void visit_load_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
5233 {
5234    Builder bld(ctx->program, ctx->block);
5235    unsigned num_components = instr->num_components;
5236
5237    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5238    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5239    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
5240
5241    bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT);
5242    load_buffer(ctx, num_components, dst, rsrc, get_ssa_temp(ctx, instr->src[1].ssa), glc, false);
5243 }
5244
5245 void visit_store_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
5246 {
5247    Builder bld(ctx->program, ctx->block);
5248    Temp data = get_ssa_temp(ctx, instr->src[0].ssa);
5249    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
5250    unsigned writemask = nir_intrinsic_write_mask(instr);
5251    Temp offset = get_ssa_temp(ctx, instr->src[2].ssa);
5252
5253    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5254    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
5255
5256    bool smem = !ctx->divergent_vals[instr->src[2].ssa->index] &&
5257                ctx->options->chip_class >= GFX8;
5258    if (smem)
5259       offset = bld.as_uniform(offset);
5260    bool smem_nonfs = smem && ctx->stage != fragment_fs;
5261
5262    while (writemask) {
5263       int start, count;
5264       u_bit_scan_consecutive_range(&writemask, &start, &count);
5265       if (count == 3 && (smem || ctx->options->chip_class == GFX6)) {
5266          /* GFX6 doesn't support storing vec3, split it. */
5267          writemask |= 1u << (start + 2);
5268          count = 2;
5269       }
5270       int num_bytes = count * elem_size_bytes;
5271
5272       if (num_bytes > 16) {
5273          assert(elem_size_bytes == 8);
5274          writemask |= (((count - 2) << 1) - 1) << (start + 2);
5275          count = 2;
5276          num_bytes = 16;
5277       }
5278
5279       // TODO: check alignment of sub-dword stores
5280       // TODO: split 3 bytes. there is no store instruction for that
5281
5282       Temp write_data;
5283       if (count != instr->num_components) {
5284          emit_split_vector(ctx, data, instr->num_components);
5285          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
5286          for (int i = 0; i < count; i++) {
5287             Temp elem = emit_extract_vector(ctx, data, start + i, RegClass(data.type(), elem_size_bytes / 4));
5288             vec->operands[i] = Operand(smem_nonfs ? bld.as_uniform(elem) : elem);
5289          }
5290          write_data = bld.tmp(!smem ? RegType::vgpr : smem_nonfs ? RegType::sgpr : data.type(), count * elem_size_bytes / 4);
5291          vec->definitions[0] = Definition(write_data);
5292          ctx->block->instructions.emplace_back(std::move(vec));
5293       } else if (!smem && data.type() != RegType::vgpr) {
5294          assert(num_bytes % 4 == 0);
5295          write_data = bld.copy(bld.def(RegType::vgpr, num_bytes / 4), data);
5296       } else if (smem_nonfs && data.type() == RegType::vgpr) {
5297          assert(num_bytes % 4 == 0);
5298          write_data = bld.as_uniform(data);
5299       } else {
5300          write_data = data;
5301       }
5302
5303       aco_opcode vmem_op, smem_op;
5304       switch (num_bytes) {
5305          case 4:
5306             vmem_op = aco_opcode::buffer_store_dword;
5307             smem_op = aco_opcode::s_buffer_store_dword;
5308             break;
5309          case 8:
5310             vmem_op = aco_opcode::buffer_store_dwordx2;
5311             smem_op = aco_opcode::s_buffer_store_dwordx2;
5312             break;
5313          case 12:
5314             vmem_op = aco_opcode::buffer_store_dwordx3;
5315             smem_op = aco_opcode::last_opcode;
5316             assert(!smem && ctx->options->chip_class > GFX6);
5317             break;
5318          case 16:
5319             vmem_op = aco_opcode::buffer_store_dwordx4;
5320             smem_op = aco_opcode::s_buffer_store_dwordx4;
5321             break;
5322          default:
5323             unreachable("Store SSBO not implemented for this size.");
5324       }
5325       if (ctx->stage == fragment_fs)
5326          smem_op = aco_opcode::p_fs_buffer_store_smem;
5327
5328       if (smem) {
5329          aco_ptr<SMEM_instruction> store{create_instruction<SMEM_instruction>(smem_op, Format::SMEM, 3, 0)};
5330          store->operands[0] = Operand(rsrc);
5331          if (start) {
5332             Temp off = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
5333                                 offset, Operand(start * elem_size_bytes));
5334             store->operands[1] = Operand(off);
5335          } else {
5336             store->operands[1] = Operand(offset);
5337          }
5338          if (smem_op != aco_opcode::p_fs_buffer_store_smem)
5339             store->operands[1].setFixed(m0);
5340          store->operands[2] = Operand(write_data);
5341          store->glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
5342          store->dlc = false;
5343          store->disable_wqm = true;
5344          store->barrier = barrier_buffer;
5345          ctx->block->instructions.emplace_back(std::move(store));
5346          ctx->program->wb_smem_l1_on_end = true;
5347          if (smem_op == aco_opcode::p_fs_buffer_store_smem) {
5348             ctx->block->kind |= block_kind_needs_lowering;
5349             ctx->program->needs_exact = true;
5350          }
5351       } else {
5352          aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(vmem_op, Format::MUBUF, 4, 0)};
5353          store->operands[0] = Operand(rsrc);
5354          store->operands[1] = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
5355          store->operands[2] = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
5356          store->operands[3] = Operand(write_data);
5357          store->offset = start * elem_size_bytes;
5358          store->offen = (offset.type() == RegType::vgpr);
5359          store->glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
5360          store->dlc = false;
5361          store->disable_wqm = true;
5362          store->barrier = barrier_buffer;
5363          ctx->program->needs_exact = true;
5364          ctx->block->instructions.emplace_back(std::move(store));
5365       }
5366    }
5367 }
5368
5369 void visit_atomic_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
5370 {
5371    /* return the previous value if dest is ever used */
5372    bool return_previous = false;
5373    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
5374       return_previous = true;
5375       break;
5376    }
5377    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
5378       return_previous = true;
5379       break;
5380    }
5381
5382    Builder bld(ctx->program, ctx->block);
5383    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[2].ssa));
5384
5385    if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap)
5386       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(RegType::vgpr, data.size() * 2),
5387                         get_ssa_temp(ctx, instr->src[3].ssa), data);
5388
5389    Temp offset = get_ssa_temp(ctx, instr->src[1].ssa);
5390    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5391    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
5392
5393    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5394
5395    aco_opcode op32, op64;
5396    switch (instr->intrinsic) {
5397       case nir_intrinsic_ssbo_atomic_add:
5398          op32 = aco_opcode::buffer_atomic_add;
5399          op64 = aco_opcode::buffer_atomic_add_x2;
5400          break;
5401       case nir_intrinsic_ssbo_atomic_imin:
5402          op32 = aco_opcode::buffer_atomic_smin;
5403          op64 = aco_opcode::buffer_atomic_smin_x2;
5404          break;
5405       case nir_intrinsic_ssbo_atomic_umin:
5406          op32 = aco_opcode::buffer_atomic_umin;
5407          op64 = aco_opcode::buffer_atomic_umin_x2;
5408          break;
5409       case nir_intrinsic_ssbo_atomic_imax:
5410          op32 = aco_opcode::buffer_atomic_smax;
5411          op64 = aco_opcode::buffer_atomic_smax_x2;
5412          break;
5413       case nir_intrinsic_ssbo_atomic_umax:
5414          op32 = aco_opcode::buffer_atomic_umax;
5415          op64 = aco_opcode::buffer_atomic_umax_x2;
5416          break;
5417       case nir_intrinsic_ssbo_atomic_and:
5418          op32 = aco_opcode::buffer_atomic_and;
5419          op64 = aco_opcode::buffer_atomic_and_x2;
5420          break;
5421       case nir_intrinsic_ssbo_atomic_or:
5422          op32 = aco_opcode::buffer_atomic_or;
5423          op64 = aco_opcode::buffer_atomic_or_x2;
5424          break;
5425       case nir_intrinsic_ssbo_atomic_xor:
5426          op32 = aco_opcode::buffer_atomic_xor;
5427          op64 = aco_opcode::buffer_atomic_xor_x2;
5428          break;
5429       case nir_intrinsic_ssbo_atomic_exchange:
5430          op32 = aco_opcode::buffer_atomic_swap;
5431          op64 = aco_opcode::buffer_atomic_swap_x2;
5432          break;
5433       case nir_intrinsic_ssbo_atomic_comp_swap:
5434          op32 = aco_opcode::buffer_atomic_cmpswap;
5435          op64 = aco_opcode::buffer_atomic_cmpswap_x2;
5436          break;
5437       default:
5438          unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
5439    }
5440    aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
5441    aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, return_previous ? 1 : 0)};
5442    mubuf->operands[0] = Operand(rsrc);
5443    mubuf->operands[1] = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
5444    mubuf->operands[2] = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
5445    mubuf->operands[3] = Operand(data);
5446    if (return_previous)
5447       mubuf->definitions[0] = Definition(dst);
5448    mubuf->offset = 0;
5449    mubuf->offen = (offset.type() == RegType::vgpr);
5450    mubuf->glc = return_previous;
5451    mubuf->dlc = false; /* Not needed for atomics */
5452    mubuf->disable_wqm = true;
5453    mubuf->barrier = barrier_buffer;
5454    ctx->program->needs_exact = true;
5455    ctx->block->instructions.emplace_back(std::move(mubuf));
5456 }
5457
5458 void visit_get_buffer_size(isel_context *ctx, nir_intrinsic_instr *instr) {
5459
5460    Temp index = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5461    Builder bld(ctx->program, ctx->block);
5462    Temp desc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), index, Operand(0u));
5463    get_buffer_size(ctx, desc, get_ssa_temp(ctx, &instr->dest.ssa), false);
5464 }
5465
5466 Temp get_gfx6_global_rsrc(Builder& bld, Temp addr)
5467 {
5468    uint32_t rsrc_conf = S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5469                         S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
5470
5471    if (addr.type() == RegType::vgpr)
5472       return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf));
5473    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), addr, Operand(-1u), Operand(rsrc_conf));
5474 }
5475
5476 void visit_load_global(isel_context *ctx, nir_intrinsic_instr *instr)
5477 {
5478    Builder bld(ctx->program, ctx->block);
5479    unsigned num_components = instr->num_components;
5480    unsigned num_bytes = num_components * instr->dest.ssa.bit_size / 8;
5481
5482    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5483    Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
5484
5485    bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT);
5486    bool dlc = glc && ctx->options->chip_class >= GFX10;
5487    aco_opcode op;
5488    if (dst.type() == RegType::vgpr || (glc && ctx->options->chip_class < GFX8)) {
5489       bool global = ctx->options->chip_class >= GFX9;
5490
5491       if (ctx->options->chip_class >= GFX7) {
5492          aco_opcode op;
5493          switch (num_bytes) {
5494          case 4:
5495             op = global ? aco_opcode::global_load_dword : aco_opcode::flat_load_dword;
5496             break;
5497          case 8:
5498             op = global ? aco_opcode::global_load_dwordx2 : aco_opcode::flat_load_dwordx2;
5499             break;
5500          case 12:
5501             op = global ? aco_opcode::global_load_dwordx3 : aco_opcode::flat_load_dwordx3;
5502             break;
5503          case 16:
5504             op = global ? aco_opcode::global_load_dwordx4 : aco_opcode::flat_load_dwordx4;
5505             break;
5506          default:
5507             unreachable("load_global not implemented for this size.");
5508          }
5509
5510          aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 2, 1)};
5511          flat->operands[0] = Operand(addr);
5512          flat->operands[1] = Operand(s1);
5513          flat->glc = glc;
5514          flat->dlc = dlc;
5515          flat->barrier = barrier_buffer;
5516
5517          if (dst.type() == RegType::sgpr) {
5518             Temp vec = bld.tmp(RegType::vgpr, dst.size());
5519             flat->definitions[0] = Definition(vec);
5520             ctx->block->instructions.emplace_back(std::move(flat));
5521             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec);
5522          } else {
5523             flat->definitions[0] = Definition(dst);
5524             ctx->block->instructions.emplace_back(std::move(flat));
5525          }
5526          emit_split_vector(ctx, dst, num_components);
5527       } else {
5528          assert(ctx->options->chip_class == GFX6);
5529
5530          /* GFX6 doesn't support loading vec3, expand to vec4. */
5531          num_bytes = num_bytes == 12 ? 16 : num_bytes;
5532
5533          aco_opcode op;
5534          switch (num_bytes) {
5535          case 4:
5536             op = aco_opcode::buffer_load_dword;
5537             break;
5538          case 8:
5539             op = aco_opcode::buffer_load_dwordx2;
5540             break;
5541          case 16:
5542             op = aco_opcode::buffer_load_dwordx4;
5543             break;
5544          default:
5545             unreachable("load_global not implemented for this size.");
5546          }
5547
5548          Temp rsrc = get_gfx6_global_rsrc(bld, addr);
5549
5550          aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
5551          mubuf->operands[0] = Operand(rsrc);
5552          mubuf->operands[1] = addr.type() == RegType::vgpr ? Operand(addr) : Operand(v1);
5553          mubuf->operands[2] = Operand(0u);
5554          mubuf->glc = glc;
5555          mubuf->dlc = false;
5556          mubuf->offset = 0;
5557          mubuf->addr64 = addr.type() == RegType::vgpr;
5558          mubuf->disable_wqm = false;
5559          mubuf->barrier = barrier_buffer;
5560          aco_ptr<Instruction> instr = std::move(mubuf);
5561
5562          /* expand vector */
5563          if (dst.size() == 3) {
5564             Temp vec = bld.tmp(v4);
5565             instr->definitions[0] = Definition(vec);
5566             bld.insert(std::move(instr));
5567             emit_split_vector(ctx, vec, 4);
5568
5569             instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, 3, 1));
5570             instr->operands[0] = Operand(emit_extract_vector(ctx, vec, 0, v1));
5571             instr->operands[1] = Operand(emit_extract_vector(ctx, vec, 1, v1));
5572             instr->operands[2] = Operand(emit_extract_vector(ctx, vec, 2, v1));
5573          }
5574
5575          if (dst.type() == RegType::sgpr) {
5576             Temp vec = bld.tmp(RegType::vgpr, dst.size());
5577             instr->definitions[0] = Definition(vec);
5578             bld.insert(std::move(instr));
5579             expand_vector(ctx, vec, dst, num_components, (1 << num_components) - 1);
5580             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec);
5581          } else {
5582             instr->definitions[0] = Definition(dst);
5583             bld.insert(std::move(instr));
5584             emit_split_vector(ctx, dst, num_components);
5585          }
5586       }
5587    } else {
5588       switch (num_bytes) {
5589          case 4:
5590             op = aco_opcode::s_load_dword;
5591             break;
5592          case 8:
5593             op = aco_opcode::s_load_dwordx2;
5594             break;
5595          case 12:
5596          case 16:
5597             op = aco_opcode::s_load_dwordx4;
5598             break;
5599          default:
5600             unreachable("load_global not implemented for this size.");
5601       }
5602       aco_ptr<SMEM_instruction> load{create_instruction<SMEM_instruction>(op, Format::SMEM, 2, 1)};
5603       load->operands[0] = Operand(addr);
5604       load->operands[1] = Operand(0u);
5605       load->definitions[0] = Definition(dst);
5606       load->glc = glc;
5607       load->dlc = dlc;
5608       load->barrier = barrier_buffer;
5609       assert(ctx->options->chip_class >= GFX8 || !glc);
5610
5611       if (dst.size() == 3) {
5612          /* trim vector */
5613          Temp vec = bld.tmp(s4);
5614          load->definitions[0] = Definition(vec);
5615          ctx->block->instructions.emplace_back(std::move(load));
5616          emit_split_vector(ctx, vec, 4);
5617
5618          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
5619                     emit_extract_vector(ctx, vec, 0, s1),
5620                     emit_extract_vector(ctx, vec, 1, s1),
5621                     emit_extract_vector(ctx, vec, 2, s1));
5622       } else {
5623          ctx->block->instructions.emplace_back(std::move(load));
5624       }
5625    }
5626 }
5627
5628 void visit_store_global(isel_context *ctx, nir_intrinsic_instr *instr)
5629 {
5630    Builder bld(ctx->program, ctx->block);
5631    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
5632
5633    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5634    Temp addr = get_ssa_temp(ctx, instr->src[1].ssa);
5635
5636    if (ctx->options->chip_class >= GFX7)
5637       addr = as_vgpr(ctx, addr);
5638
5639    unsigned writemask = nir_intrinsic_write_mask(instr);
5640    while (writemask) {
5641       int start, count;
5642       u_bit_scan_consecutive_range(&writemask, &start, &count);
5643       if (count == 3 && ctx->options->chip_class == GFX6) {
5644          /* GFX6 doesn't support storing vec3, split it. */
5645          writemask |= 1u << (start + 2);
5646          count = 2;
5647       }
5648       unsigned num_bytes = count * elem_size_bytes;
5649
5650       Temp write_data = data;
5651       if (count != instr->num_components) {
5652          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
5653          for (int i = 0; i < count; i++)
5654             vec->operands[i] = Operand(emit_extract_vector(ctx, data, start + i, v1));
5655          write_data = bld.tmp(RegType::vgpr, count);
5656          vec->definitions[0] = Definition(write_data);
5657          ctx->block->instructions.emplace_back(std::move(vec));
5658       }
5659
5660       bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
5661       unsigned offset = start * elem_size_bytes;
5662
5663       if (ctx->options->chip_class >= GFX7) {
5664          if (offset > 0 && ctx->options->chip_class < GFX9) {
5665             Temp addr0 = bld.tmp(v1), addr1 = bld.tmp(v1);
5666             Temp new_addr0 = bld.tmp(v1), new_addr1 = bld.tmp(v1);
5667             Temp carry = bld.tmp(bld.lm);
5668             bld.pseudo(aco_opcode::p_split_vector, Definition(addr0), Definition(addr1), addr);
5669
5670             bld.vop2(aco_opcode::v_add_co_u32, Definition(new_addr0), bld.hint_vcc(Definition(carry)),
5671                      Operand(offset), addr0);
5672             bld.vop2(aco_opcode::v_addc_co_u32, Definition(new_addr1), bld.def(bld.lm),
5673                      Operand(0u), addr1,
5674                      carry).def(1).setHint(vcc);
5675
5676             addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), new_addr0, new_addr1);
5677
5678             offset = 0;
5679          }
5680
5681          bool global = ctx->options->chip_class >= GFX9;
5682          aco_opcode op;
5683          switch (num_bytes) {
5684          case 4:
5685             op = global ? aco_opcode::global_store_dword : aco_opcode::flat_store_dword;
5686             break;
5687          case 8:
5688             op = global ? aco_opcode::global_store_dwordx2 : aco_opcode::flat_store_dwordx2;
5689             break;
5690          case 12:
5691             op = global ? aco_opcode::global_store_dwordx3 : aco_opcode::flat_store_dwordx3;
5692             break;
5693          case 16:
5694             op = global ? aco_opcode::global_store_dwordx4 : aco_opcode::flat_store_dwordx4;
5695             break;
5696          default:
5697             unreachable("store_global not implemented for this size.");
5698          }
5699
5700          aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 3, 0)};
5701          flat->operands[0] = Operand(addr);
5702          flat->operands[1] = Operand(s1);
5703          flat->operands[2] = Operand(data);
5704          flat->glc = glc;
5705          flat->dlc = false;
5706          flat->offset = offset;
5707          flat->disable_wqm = true;
5708          flat->barrier = barrier_buffer;
5709          ctx->program->needs_exact = true;
5710          ctx->block->instructions.emplace_back(std::move(flat));
5711       } else {
5712          assert(ctx->options->chip_class == GFX6);
5713
5714          aco_opcode op;
5715          switch (num_bytes) {
5716          case 4:
5717             op = aco_opcode::buffer_store_dword;
5718             break;
5719          case 8:
5720             op = aco_opcode::buffer_store_dwordx2;
5721             break;
5722          case 16:
5723             op = aco_opcode::buffer_store_dwordx4;
5724             break;
5725          default:
5726             unreachable("store_global not implemented for this size.");
5727          }
5728
5729          Temp rsrc = get_gfx6_global_rsrc(bld, addr);
5730
5731          aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, 0)};
5732          mubuf->operands[0] = Operand(rsrc);
5733          mubuf->operands[1] = addr.type() == RegType::vgpr ? Operand(addr) : Operand(v1);
5734          mubuf->operands[2] = Operand(0u);
5735          mubuf->operands[3] = Operand(write_data);
5736          mubuf->glc = glc;
5737          mubuf->dlc = false;
5738          mubuf->offset = offset;
5739          mubuf->addr64 = addr.type() == RegType::vgpr;
5740          mubuf->disable_wqm = true;
5741          mubuf->barrier = barrier_buffer;
5742          ctx->program->needs_exact = true;
5743          ctx->block->instructions.emplace_back(std::move(mubuf));
5744       }
5745    }
5746 }
5747
5748 void visit_global_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
5749 {
5750    /* return the previous value if dest is ever used */
5751    bool return_previous = false;
5752    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
5753       return_previous = true;
5754       break;
5755    }
5756    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
5757       return_previous = true;
5758       break;
5759    }
5760
5761    Builder bld(ctx->program, ctx->block);
5762    Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
5763    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5764
5765    if (ctx->options->chip_class >= GFX7)
5766       addr = as_vgpr(ctx, addr);
5767
5768    if (instr->intrinsic == nir_intrinsic_global_atomic_comp_swap)
5769       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(RegType::vgpr, data.size() * 2),
5770                         get_ssa_temp(ctx, instr->src[2].ssa), data);
5771
5772    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5773
5774    aco_opcode op32, op64;
5775
5776    if (ctx->options->chip_class >= GFX7) {
5777       bool global = ctx->options->chip_class >= GFX9;
5778       switch (instr->intrinsic) {
5779          case nir_intrinsic_global_atomic_add:
5780             op32 = global ? aco_opcode::global_atomic_add : aco_opcode::flat_atomic_add;
5781             op64 = global ? aco_opcode::global_atomic_add_x2 : aco_opcode::flat_atomic_add_x2;
5782             break;
5783          case nir_intrinsic_global_atomic_imin:
5784             op32 = global ? aco_opcode::global_atomic_smin : aco_opcode::flat_atomic_smin;
5785             op64 = global ? aco_opcode::global_atomic_smin_x2 : aco_opcode::flat_atomic_smin_x2;
5786             break;
5787          case nir_intrinsic_global_atomic_umin:
5788             op32 = global ? aco_opcode::global_atomic_umin : aco_opcode::flat_atomic_umin;
5789             op64 = global ? aco_opcode::global_atomic_umin_x2 : aco_opcode::flat_atomic_umin_x2;
5790             break;
5791          case nir_intrinsic_global_atomic_imax:
5792             op32 = global ? aco_opcode::global_atomic_smax : aco_opcode::flat_atomic_smax;
5793             op64 = global ? aco_opcode::global_atomic_smax_x2 : aco_opcode::flat_atomic_smax_x2;
5794             break;
5795          case nir_intrinsic_global_atomic_umax:
5796             op32 = global ? aco_opcode::global_atomic_umax : aco_opcode::flat_atomic_umax;
5797             op64 = global ? aco_opcode::global_atomic_umax_x2 : aco_opcode::flat_atomic_umax_x2;
5798             break;
5799          case nir_intrinsic_global_atomic_and:
5800             op32 = global ? aco_opcode::global_atomic_and : aco_opcode::flat_atomic_and;
5801             op64 = global ? aco_opcode::global_atomic_and_x2 : aco_opcode::flat_atomic_and_x2;
5802             break;
5803          case nir_intrinsic_global_atomic_or:
5804             op32 = global ? aco_opcode::global_atomic_or : aco_opcode::flat_atomic_or;
5805             op64 = global ? aco_opcode::global_atomic_or_x2 : aco_opcode::flat_atomic_or_x2;
5806             break;
5807          case nir_intrinsic_global_atomic_xor:
5808             op32 = global ? aco_opcode::global_atomic_xor : aco_opcode::flat_atomic_xor;
5809             op64 = global ? aco_opcode::global_atomic_xor_x2 : aco_opcode::flat_atomic_xor_x2;
5810             break;
5811          case nir_intrinsic_global_atomic_exchange:
5812             op32 = global ? aco_opcode::global_atomic_swap : aco_opcode::flat_atomic_swap;
5813             op64 = global ? aco_opcode::global_atomic_swap_x2 : aco_opcode::flat_atomic_swap_x2;
5814             break;
5815          case nir_intrinsic_global_atomic_comp_swap:
5816             op32 = global ? aco_opcode::global_atomic_cmpswap : aco_opcode::flat_atomic_cmpswap;
5817             op64 = global ? aco_opcode::global_atomic_cmpswap_x2 : aco_opcode::flat_atomic_cmpswap_x2;
5818             break;
5819          default:
5820             unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
5821       }
5822
5823       aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
5824       aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 3, return_previous ? 1 : 0)};
5825       flat->operands[0] = Operand(addr);
5826       flat->operands[1] = Operand(s1);
5827       flat->operands[2] = Operand(data);
5828       if (return_previous)
5829          flat->definitions[0] = Definition(dst);
5830       flat->glc = return_previous;
5831       flat->dlc = false; /* Not needed for atomics */
5832       flat->offset = 0;
5833       flat->disable_wqm = true;
5834       flat->barrier = barrier_buffer;
5835       ctx->program->needs_exact = true;
5836       ctx->block->instructions.emplace_back(std::move(flat));
5837    } else {
5838       assert(ctx->options->chip_class == GFX6);
5839
5840       switch (instr->intrinsic) {
5841          case nir_intrinsic_global_atomic_add:
5842             op32 = aco_opcode::buffer_atomic_add;
5843             op64 = aco_opcode::buffer_atomic_add_x2;
5844             break;
5845          case nir_intrinsic_global_atomic_imin:
5846             op32 = aco_opcode::buffer_atomic_smin;
5847             op64 = aco_opcode::buffer_atomic_smin_x2;
5848             break;
5849          case nir_intrinsic_global_atomic_umin:
5850             op32 = aco_opcode::buffer_atomic_umin;
5851             op64 = aco_opcode::buffer_atomic_umin_x2;
5852             break;
5853          case nir_intrinsic_global_atomic_imax:
5854             op32 = aco_opcode::buffer_atomic_smax;
5855             op64 = aco_opcode::buffer_atomic_smax_x2;
5856             break;
5857          case nir_intrinsic_global_atomic_umax:
5858             op32 = aco_opcode::buffer_atomic_umax;
5859             op64 = aco_opcode::buffer_atomic_umax_x2;
5860             break;
5861          case nir_intrinsic_global_atomic_and:
5862             op32 = aco_opcode::buffer_atomic_and;
5863             op64 = aco_opcode::buffer_atomic_and_x2;
5864             break;
5865          case nir_intrinsic_global_atomic_or:
5866             op32 = aco_opcode::buffer_atomic_or;
5867             op64 = aco_opcode::buffer_atomic_or_x2;
5868             break;
5869          case nir_intrinsic_global_atomic_xor:
5870             op32 = aco_opcode::buffer_atomic_xor;
5871             op64 = aco_opcode::buffer_atomic_xor_x2;
5872             break;
5873          case nir_intrinsic_global_atomic_exchange:
5874             op32 = aco_opcode::buffer_atomic_swap;
5875             op64 = aco_opcode::buffer_atomic_swap_x2;
5876             break;
5877          case nir_intrinsic_global_atomic_comp_swap:
5878             op32 = aco_opcode::buffer_atomic_cmpswap;
5879             op64 = aco_opcode::buffer_atomic_cmpswap_x2;
5880             break;
5881          default:
5882             unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
5883       }
5884
5885       Temp rsrc = get_gfx6_global_rsrc(bld, addr);
5886
5887       aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
5888
5889       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, return_previous ? 1 : 0)};
5890       mubuf->operands[0] = Operand(rsrc);
5891       mubuf->operands[1] = addr.type() == RegType::vgpr ? Operand(addr) : Operand(v1);
5892       mubuf->operands[2] = Operand(0u);
5893       mubuf->operands[3] = Operand(data);
5894       if (return_previous)
5895          mubuf->definitions[0] = Definition(dst);
5896       mubuf->glc = return_previous;
5897       mubuf->dlc = false;
5898       mubuf->offset = 0;
5899       mubuf->addr64 = addr.type() == RegType::vgpr;
5900       mubuf->disable_wqm = true;
5901       mubuf->barrier = barrier_buffer;
5902       ctx->program->needs_exact = true;
5903       ctx->block->instructions.emplace_back(std::move(mubuf));
5904    }
5905 }
5906
5907 void emit_memory_barrier(isel_context *ctx, nir_intrinsic_instr *instr) {
5908    Builder bld(ctx->program, ctx->block);
5909    switch(instr->intrinsic) {
5910       case nir_intrinsic_group_memory_barrier:
5911       case nir_intrinsic_memory_barrier:
5912          bld.barrier(aco_opcode::p_memory_barrier_common);
5913          break;
5914       case nir_intrinsic_memory_barrier_buffer:
5915          bld.barrier(aco_opcode::p_memory_barrier_buffer);
5916          break;
5917       case nir_intrinsic_memory_barrier_image:
5918          bld.barrier(aco_opcode::p_memory_barrier_image);
5919          break;
5920       case nir_intrinsic_memory_barrier_tcs_patch:
5921       case nir_intrinsic_memory_barrier_shared:
5922          bld.barrier(aco_opcode::p_memory_barrier_shared);
5923          break;
5924       default:
5925          unreachable("Unimplemented memory barrier intrinsic");
5926          break;
5927    }
5928 }
5929
5930 void visit_load_shared(isel_context *ctx, nir_intrinsic_instr *instr)
5931 {
5932    // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
5933    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5934    assert(instr->dest.ssa.bit_size >= 32 && "Bitsize not supported in load_shared.");
5935    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5936    Builder bld(ctx->program, ctx->block);
5937
5938    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
5939    unsigned align = nir_intrinsic_align_mul(instr) ? nir_intrinsic_align(instr) : elem_size_bytes;
5940    load_lds(ctx, elem_size_bytes, dst, address, nir_intrinsic_base(instr), align);
5941 }
5942
5943 void visit_store_shared(isel_context *ctx, nir_intrinsic_instr *instr)
5944 {
5945    unsigned writemask = nir_intrinsic_write_mask(instr);
5946    Temp data = get_ssa_temp(ctx, instr->src[0].ssa);
5947    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5948    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
5949    assert(elem_size_bytes >= 4 && "Only 32bit & 64bit store_shared currently supported.");
5950
5951    unsigned align = nir_intrinsic_align_mul(instr) ? nir_intrinsic_align(instr) : elem_size_bytes;
5952    store_lds(ctx, elem_size_bytes, data, writemask, address, nir_intrinsic_base(instr), align);
5953 }
5954
5955 void visit_shared_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
5956 {
5957    unsigned offset = nir_intrinsic_base(instr);
5958    Operand m = load_lds_size_m0(ctx);
5959    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5960    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5961
5962    unsigned num_operands = 3;
5963    aco_opcode op32, op64, op32_rtn, op64_rtn;
5964    switch(instr->intrinsic) {
5965       case nir_intrinsic_shared_atomic_add:
5966          op32 = aco_opcode::ds_add_u32;
5967          op64 = aco_opcode::ds_add_u64;
5968          op32_rtn = aco_opcode::ds_add_rtn_u32;
5969          op64_rtn = aco_opcode::ds_add_rtn_u64;
5970          break;
5971       case nir_intrinsic_shared_atomic_imin:
5972          op32 = aco_opcode::ds_min_i32;
5973          op64 = aco_opcode::ds_min_i64;
5974          op32_rtn = aco_opcode::ds_min_rtn_i32;
5975          op64_rtn = aco_opcode::ds_min_rtn_i64;
5976          break;
5977       case nir_intrinsic_shared_atomic_umin:
5978          op32 = aco_opcode::ds_min_u32;
5979          op64 = aco_opcode::ds_min_u64;
5980          op32_rtn = aco_opcode::ds_min_rtn_u32;
5981          op64_rtn = aco_opcode::ds_min_rtn_u64;
5982          break;
5983       case nir_intrinsic_shared_atomic_imax:
5984          op32 = aco_opcode::ds_max_i32;
5985          op64 = aco_opcode::ds_max_i64;
5986          op32_rtn = aco_opcode::ds_max_rtn_i32;
5987          op64_rtn = aco_opcode::ds_max_rtn_i64;
5988          break;
5989       case nir_intrinsic_shared_atomic_umax:
5990          op32 = aco_opcode::ds_max_u32;
5991          op64 = aco_opcode::ds_max_u64;
5992          op32_rtn = aco_opcode::ds_max_rtn_u32;
5993          op64_rtn = aco_opcode::ds_max_rtn_u64;
5994          break;
5995       case nir_intrinsic_shared_atomic_and:
5996          op32 = aco_opcode::ds_and_b32;
5997          op64 = aco_opcode::ds_and_b64;
5998          op32_rtn = aco_opcode::ds_and_rtn_b32;
5999          op64_rtn = aco_opcode::ds_and_rtn_b64;
6000          break;
6001       case nir_intrinsic_shared_atomic_or:
6002          op32 = aco_opcode::ds_or_b32;
6003          op64 = aco_opcode::ds_or_b64;
6004          op32_rtn = aco_opcode::ds_or_rtn_b32;
6005          op64_rtn = aco_opcode::ds_or_rtn_b64;
6006          break;
6007       case nir_intrinsic_shared_atomic_xor:
6008          op32 = aco_opcode::ds_xor_b32;
6009          op64 = aco_opcode::ds_xor_b64;
6010          op32_rtn = aco_opcode::ds_xor_rtn_b32;
6011          op64_rtn = aco_opcode::ds_xor_rtn_b64;
6012          break;
6013       case nir_intrinsic_shared_atomic_exchange:
6014          op32 = aco_opcode::ds_write_b32;
6015          op64 = aco_opcode::ds_write_b64;
6016          op32_rtn = aco_opcode::ds_wrxchg_rtn_b32;
6017          op64_rtn = aco_opcode::ds_wrxchg2_rtn_b64;
6018          break;
6019       case nir_intrinsic_shared_atomic_comp_swap:
6020          op32 = aco_opcode::ds_cmpst_b32;
6021          op64 = aco_opcode::ds_cmpst_b64;
6022          op32_rtn = aco_opcode::ds_cmpst_rtn_b32;
6023          op64_rtn = aco_opcode::ds_cmpst_rtn_b64;
6024          num_operands = 4;
6025          break;
6026       default:
6027          unreachable("Unhandled shared atomic intrinsic");
6028    }
6029
6030    /* return the previous value if dest is ever used */
6031    bool return_previous = false;
6032    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
6033       return_previous = true;
6034       break;
6035    }
6036    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
6037       return_previous = true;
6038       break;
6039    }
6040
6041    aco_opcode op;
6042    if (data.size() == 1) {
6043       assert(instr->dest.ssa.bit_size == 32);
6044       op = return_previous ? op32_rtn : op32;
6045    } else {
6046       assert(instr->dest.ssa.bit_size == 64);
6047       op = return_previous ? op64_rtn : op64;
6048    }
6049
6050    if (offset > 65535) {
6051       Builder bld(ctx->program, ctx->block);
6052       address = bld.vadd32(bld.def(v1), Operand(offset), address);
6053       offset = 0;
6054    }
6055
6056    aco_ptr<DS_instruction> ds;
6057    ds.reset(create_instruction<DS_instruction>(op, Format::DS, num_operands, return_previous ? 1 : 0));
6058    ds->operands[0] = Operand(address);
6059    ds->operands[1] = Operand(data);
6060    if (num_operands == 4)
6061       ds->operands[2] = Operand(get_ssa_temp(ctx, instr->src[2].ssa));
6062    ds->operands[num_operands - 1] = m;
6063    ds->offset0 = offset;
6064    if (return_previous)
6065       ds->definitions[0] = Definition(get_ssa_temp(ctx, &instr->dest.ssa));
6066    ctx->block->instructions.emplace_back(std::move(ds));
6067 }
6068
6069 Temp get_scratch_resource(isel_context *ctx)
6070 {
6071    Builder bld(ctx->program, ctx->block);
6072    Temp scratch_addr = ctx->program->private_segment_buffer;
6073    if (ctx->stage != compute_cs)
6074       scratch_addr = bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), scratch_addr, Operand(0u));
6075
6076    uint32_t rsrc_conf = S_008F0C_ADD_TID_ENABLE(1) |
6077                         S_008F0C_INDEX_STRIDE(ctx->program->wave_size == 64 ? 3 : 2);;
6078
6079    if (ctx->program->chip_class >= GFX10) {
6080       rsrc_conf |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
6081                    S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
6082                    S_008F0C_RESOURCE_LEVEL(1);
6083    } else if (ctx->program->chip_class <= GFX7) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6084       rsrc_conf |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
6085                    S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
6086    }
6087
6088    /* older generations need element size = 16 bytes. element size removed in GFX9 */
6089    if (ctx->program->chip_class <= GFX8)
6090       rsrc_conf |= S_008F0C_ELEMENT_SIZE(3);
6091
6092    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), scratch_addr, Operand(-1u), Operand(rsrc_conf));
6093 }
6094
6095 void visit_load_scratch(isel_context *ctx, nir_intrinsic_instr *instr) {
6096    assert(instr->dest.ssa.bit_size == 32 || instr->dest.ssa.bit_size == 64);
6097    Builder bld(ctx->program, ctx->block);
6098    Temp rsrc = get_scratch_resource(ctx);
6099    Temp offset = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
6100    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6101
6102    aco_opcode op;
6103    switch (dst.size()) {
6104       case 1:
6105          op = aco_opcode::buffer_load_dword;
6106          break;
6107       case 2:
6108          op = aco_opcode::buffer_load_dwordx2;
6109          break;
6110       case 3:
6111          op = aco_opcode::buffer_load_dwordx3;
6112          break;
6113       case 4:
6114          op = aco_opcode::buffer_load_dwordx4;
6115          break;
6116       case 6:
6117       case 8: {
6118          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
6119          Temp lower = bld.mubuf(aco_opcode::buffer_load_dwordx4,
6120                                 bld.def(v4), rsrc, offset,
6121                                 ctx->program->scratch_offset, 0, true);
6122          Temp upper = bld.mubuf(dst.size() == 6 ? aco_opcode::buffer_load_dwordx2 :
6123                                                   aco_opcode::buffer_load_dwordx4,
6124                                 dst.size() == 6 ? bld.def(v2) : bld.def(v4),
6125                                 rsrc, offset, ctx->program->scratch_offset, 16, true);
6126          emit_split_vector(ctx, lower, 2);
6127          elems[0] = emit_extract_vector(ctx, lower, 0, v2);
6128          elems[1] = emit_extract_vector(ctx, lower, 1, v2);
6129          if (dst.size() == 8) {
6130             emit_split_vector(ctx, upper, 2);
6131             elems[2] = emit_extract_vector(ctx, upper, 0, v2);
6132             elems[3] = emit_extract_vector(ctx, upper, 1, v2);
6133          } else {
6134             elems[2] = upper;
6135          }
6136
6137          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector,
6138                                                                          Format::PSEUDO, dst.size() / 2, 1)};
6139          for (unsigned i = 0; i < dst.size() / 2; i++)
6140             vec->operands[i] = Operand(elems[i]);
6141          vec->definitions[0] = Definition(dst);
6142          bld.insert(std::move(vec));
6143          ctx->allocated_vec.emplace(dst.id(), elems);
6144          return;
6145       }
6146       default:
6147          unreachable("Wrong dst size for nir_intrinsic_load_scratch");
6148    }
6149
6150    bld.mubuf(op, Definition(dst), rsrc, offset, ctx->program->scratch_offset, 0, true);
6151    emit_split_vector(ctx, dst, instr->num_components);
6152 }
6153
6154 void visit_store_scratch(isel_context *ctx, nir_intrinsic_instr *instr) {
6155    assert(instr->src[0].ssa->bit_size == 32 || instr->src[0].ssa->bit_size == 64);
6156    Builder bld(ctx->program, ctx->block);
6157    Temp rsrc = get_scratch_resource(ctx);
6158    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
6159    Temp offset = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
6160
6161    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
6162    unsigned writemask = nir_intrinsic_write_mask(instr);
6163
6164    while (writemask) {
6165       int start, count;
6166       u_bit_scan_consecutive_range(&writemask, &start, &count);
6167       int num_bytes = count * elem_size_bytes;
6168
6169       if (num_bytes > 16) {
6170          assert(elem_size_bytes == 8);
6171          writemask |= (((count - 2) << 1) - 1) << (start + 2);
6172          count = 2;
6173          num_bytes = 16;
6174       }
6175
6176       // TODO: check alignment of sub-dword stores
6177       // TODO: split 3 bytes. there is no store instruction for that
6178
6179       Temp write_data;
6180       if (count != instr->num_components) {
6181          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
6182          for (int i = 0; i < count; i++) {
6183             Temp elem = emit_extract_vector(ctx, data, start + i, RegClass(RegType::vgpr, elem_size_bytes / 4));
6184             vec->operands[i] = Operand(elem);
6185          }
6186          write_data = bld.tmp(RegClass(RegType::vgpr, count * elem_size_bytes / 4));
6187          vec->definitions[0] = Definition(write_data);
6188          ctx->block->instructions.emplace_back(std::move(vec));
6189       } else {
6190          write_data = data;
6191       }
6192
6193       aco_opcode op;
6194       switch (num_bytes) {
6195          case 4:
6196             op = aco_opcode::buffer_store_dword;
6197             break;
6198          case 8:
6199             op = aco_opcode::buffer_store_dwordx2;
6200             break;
6201          case 12:
6202             op = aco_opcode::buffer_store_dwordx3;
6203             break;
6204          case 16:
6205             op = aco_opcode::buffer_store_dwordx4;
6206             break;
6207          default:
6208             unreachable("Invalid data size for nir_intrinsic_store_scratch.");
6209       }
6210
6211       bld.mubuf(op, rsrc, offset, ctx->program->scratch_offset, write_data, start * elem_size_bytes, true);
6212    }
6213 }
6214
6215 void visit_load_sample_mask_in(isel_context *ctx, nir_intrinsic_instr *instr) {
6216    uint8_t log2_ps_iter_samples;
6217    if (ctx->program->info->ps.force_persample) {
6218       log2_ps_iter_samples =
6219          util_logbase2(ctx->options->key.fs.num_samples);
6220    } else {
6221       log2_ps_iter_samples = ctx->options->key.fs.log2_ps_iter_samples;
6222    }
6223
6224    /* The bit pattern matches that used by fixed function fragment
6225     * processing. */
6226    static const unsigned ps_iter_masks[] = {
6227       0xffff, /* not used */
6228       0x5555,
6229       0x1111,
6230       0x0101,
6231       0x0001,
6232    };
6233    assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
6234
6235    Builder bld(ctx->program, ctx->block);
6236
6237    Temp sample_id = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1),
6238                              get_arg(ctx, ctx->args->ac.ancillary), Operand(8u), Operand(4u));
6239    Temp ps_iter_mask = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(ps_iter_masks[log2_ps_iter_samples]));
6240    Temp mask = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), sample_id, ps_iter_mask);
6241    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6242    bld.vop2(aco_opcode::v_and_b32, Definition(dst), mask, get_arg(ctx, ctx->args->ac.sample_coverage));
6243 }
6244
6245 void visit_emit_vertex_with_counter(isel_context *ctx, nir_intrinsic_instr *instr) {
6246    Builder bld(ctx->program, ctx->block);
6247
6248    unsigned stream = nir_intrinsic_stream_id(instr);
6249    Temp next_vertex = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
6250    next_vertex = bld.v_mul_imm(bld.def(v1), next_vertex, 4u);
6251    nir_const_value *next_vertex_cv = nir_src_as_const_value(instr->src[0]);
6252
6253    /* get GSVS ring */
6254    Temp gsvs_ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_GSVS_GS * 16u));
6255
6256    unsigned num_components =
6257       ctx->program->info->gs.num_stream_output_components[stream];
6258    assert(num_components);
6259
6260    unsigned stride = 4u * num_components * ctx->shader->info.gs.vertices_out;
6261    unsigned stream_offset = 0;
6262    for (unsigned i = 0; i < stream; i++) {
6263       unsigned prev_stride = 4u * ctx->program->info->gs.num_stream_output_components[i] * ctx->shader->info.gs.vertices_out;
6264       stream_offset += prev_stride * ctx->program->wave_size;
6265    }
6266
6267    /* Limit on the stride field for <= GFX7. */
6268    assert(stride < (1 << 14));
6269
6270    Temp gsvs_dwords[4];
6271    for (unsigned i = 0; i < 4; i++)
6272       gsvs_dwords[i] = bld.tmp(s1);
6273    bld.pseudo(aco_opcode::p_split_vector,
6274               Definition(gsvs_dwords[0]),
6275               Definition(gsvs_dwords[1]),
6276               Definition(gsvs_dwords[2]),
6277               Definition(gsvs_dwords[3]),
6278               gsvs_ring);
6279
6280    if (stream_offset) {
6281       Temp stream_offset_tmp = bld.copy(bld.def(s1), Operand(stream_offset));
6282
6283       Temp carry = bld.tmp(s1);
6284       gsvs_dwords[0] = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), gsvs_dwords[0], stream_offset_tmp);
6285       gsvs_dwords[1] = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), gsvs_dwords[1], Operand(0u), bld.scc(carry));
6286    }
6287
6288    gsvs_dwords[1] = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), gsvs_dwords[1], Operand(S_008F04_STRIDE(stride)));
6289    gsvs_dwords[2] = bld.copy(bld.def(s1), Operand((uint32_t)ctx->program->wave_size));
6290
6291    gsvs_ring = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
6292                           gsvs_dwords[0], gsvs_dwords[1], gsvs_dwords[2], gsvs_dwords[3]);
6293
6294    unsigned offset = 0;
6295    for (unsigned i = 0; i <= VARYING_SLOT_VAR31; i++) {
6296       if (ctx->program->info->gs.output_streams[i] != stream)
6297          continue;
6298
6299       for (unsigned j = 0; j < 4; j++) {
6300          if (!(ctx->program->info->gs.output_usage_mask[i] & (1 << j)))
6301             continue;
6302
6303          if (ctx->outputs.mask[i] & (1 << j)) {
6304             Operand vaddr_offset = next_vertex_cv ? Operand(v1) : Operand(next_vertex);
6305             unsigned const_offset = (offset + (next_vertex_cv ? next_vertex_cv->u32 : 0u)) * 4u;
6306             if (const_offset >= 4096u) {
6307                if (vaddr_offset.isUndefined())
6308                   vaddr_offset = bld.copy(bld.def(v1), Operand(const_offset / 4096u * 4096u));
6309                else
6310                   vaddr_offset = bld.vadd32(bld.def(v1), Operand(const_offset / 4096u * 4096u), vaddr_offset);
6311                const_offset %= 4096u;
6312             }
6313
6314             aco_ptr<MTBUF_instruction> mtbuf{create_instruction<MTBUF_instruction>(aco_opcode::tbuffer_store_format_x, Format::MTBUF, 4, 0)};
6315             mtbuf->operands[0] = Operand(gsvs_ring);
6316             mtbuf->operands[1] = vaddr_offset;
6317             mtbuf->operands[2] = Operand(get_arg(ctx, ctx->args->gs2vs_offset));
6318             mtbuf->operands[3] = Operand(ctx->outputs.temps[i * 4u + j]);
6319             mtbuf->offen = !vaddr_offset.isUndefined();
6320             mtbuf->dfmt = V_008F0C_BUF_DATA_FORMAT_32;
6321             mtbuf->nfmt = V_008F0C_BUF_NUM_FORMAT_UINT;
6322             mtbuf->offset = const_offset;
6323             mtbuf->glc = true;
6324             mtbuf->slc = true;
6325             mtbuf->barrier = barrier_gs_data;
6326             mtbuf->can_reorder = true;
6327             bld.insert(std::move(mtbuf));
6328          }
6329
6330          offset += ctx->shader->info.gs.vertices_out;
6331       }
6332
6333       /* outputs for the next vertex are undefined and keeping them around can
6334        * create invalid IR with control flow */
6335       ctx->outputs.mask[i] = 0;
6336    }
6337
6338    bld.sopp(aco_opcode::s_sendmsg, bld.m0(ctx->gs_wave_id), -1, sendmsg_gs(false, true, stream));
6339 }
6340
6341 Temp emit_boolean_reduce(isel_context *ctx, nir_op op, unsigned cluster_size, Temp src)
6342 {
6343    Builder bld(ctx->program, ctx->block);
6344
6345    if (cluster_size == 1) {
6346       return src;
6347    } if (op == nir_op_iand && cluster_size == 4) {
6348       //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6349       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src);
6350       return bld.sop1(Builder::s_not, bld.def(bld.lm), bld.def(s1, scc),
6351                       bld.sop1(Builder::s_wqm, bld.def(bld.lm), bld.def(s1, scc), tmp));
6352    } else if (op == nir_op_ior && cluster_size == 4) {
6353       //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6354       return bld.sop1(Builder::s_wqm, bld.def(bld.lm), bld.def(s1, scc),
6355                       bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm)));
6356    } else if (op == nir_op_iand && cluster_size == ctx->program->wave_size) {
6357       //subgroupAnd(val) -> (exec & ~val) == 0
6358       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src).def(1).getTemp();
6359       Temp cond = bool_to_vector_condition(ctx, emit_wqm(ctx, tmp));
6360       return bld.sop1(Builder::s_not, bld.def(bld.lm), bld.def(s1, scc), cond);
6361    } else if (op == nir_op_ior && cluster_size == ctx->program->wave_size) {
6362       //subgroupOr(val) -> (val & exec) != 0
6363       Temp tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm)).def(1).getTemp();
6364       return bool_to_vector_condition(ctx, tmp);
6365    } else if (op == nir_op_ixor && cluster_size == ctx->program->wave_size) {
6366       //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6367       Temp tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
6368       tmp = bld.sop1(Builder::s_bcnt1_i32, bld.def(s1), bld.def(s1, scc), tmp);
6369       tmp = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), tmp, Operand(1u)).def(1).getTemp();
6370       return bool_to_vector_condition(ctx, tmp);
6371    } else {
6372       //subgroupClustered{And,Or,Xor}(val, n) ->
6373       //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ;  just v_mbcnt_lo_u32_b32 on wave32
6374       //cluster_offset = ~(n - 1) & lane_id
6375       //cluster_mask = ((1 << n) - 1)
6376       //subgroupClusteredAnd():
6377       //   return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6378       //subgroupClusteredOr():
6379       //   return ((val & exec) >> cluster_offset) & cluster_mask != 0
6380       //subgroupClusteredXor():
6381       //   return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6382       Temp lane_id = emit_mbcnt(ctx, bld.def(v1));
6383       Temp cluster_offset = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(~uint32_t(cluster_size - 1)), lane_id);
6384
6385       Temp tmp;
6386       if (op == nir_op_iand)
6387          tmp = bld.sop2(Builder::s_orn2, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
6388       else
6389          tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
6390
6391       uint32_t cluster_mask = cluster_size == 32 ? -1 : (1u << cluster_size) - 1u;
6392
6393       if (ctx->program->chip_class <= GFX7)
6394          tmp = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), tmp, cluster_offset);
6395       else if (ctx->program->wave_size == 64)
6396          tmp = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), cluster_offset, tmp);
6397       else
6398          tmp = bld.vop2_e64(aco_opcode::v_lshrrev_b32, bld.def(v1), cluster_offset, tmp);
6399       tmp = emit_extract_vector(ctx, tmp, 0, v1);
6400       if (cluster_mask != 0xffffffff)
6401          tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(cluster_mask), tmp);
6402
6403       Definition cmp_def = Definition();
6404       if (op == nir_op_iand) {
6405          cmp_def = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm), Operand(cluster_mask), tmp).def(0);
6406       } else if (op == nir_op_ior) {
6407          cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp).def(0);
6408       } else if (op == nir_op_ixor) {
6409          tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u),
6410                         bld.vop3(aco_opcode::v_bcnt_u32_b32, bld.def(v1), tmp, Operand(0u)));
6411          cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp).def(0);
6412       }
6413       cmp_def.setHint(vcc);
6414       return cmp_def.getTemp();
6415    }
6416 }
6417
6418 Temp emit_boolean_exclusive_scan(isel_context *ctx, nir_op op, Temp src)
6419 {
6420    Builder bld(ctx->program, ctx->block);
6421
6422    //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
6423    //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
6424    //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
6425    Temp tmp;
6426    if (op == nir_op_iand)
6427       tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src);
6428    else
6429       tmp = bld.sop2(Builder::s_and, bld.def(s2), bld.def(s1, scc), src, Operand(exec, bld.lm));
6430
6431    Builder::Result lohi = bld.pseudo(aco_opcode::p_split_vector, bld.def(s1), bld.def(s1), tmp);
6432    Temp lo = lohi.def(0).getTemp();
6433    Temp hi = lohi.def(1).getTemp();
6434    Temp mbcnt = emit_mbcnt(ctx, bld.def(v1), Operand(lo), Operand(hi));
6435
6436    Definition cmp_def = Definition();
6437    if (op == nir_op_iand)
6438       cmp_def = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm), Operand(0u), mbcnt).def(0);
6439    else if (op == nir_op_ior)
6440       cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), mbcnt).def(0);
6441    else if (op == nir_op_ixor)
6442       cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u),
6443                          bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u), mbcnt)).def(0);
6444    cmp_def.setHint(vcc);
6445    return cmp_def.getTemp();
6446 }
6447
6448 Temp emit_boolean_inclusive_scan(isel_context *ctx, nir_op op, Temp src)
6449 {
6450    Builder bld(ctx->program, ctx->block);
6451
6452    //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
6453    //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
6454    //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
6455    Temp tmp = emit_boolean_exclusive_scan(ctx, op, src);
6456    if (op == nir_op_iand)
6457       return bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
6458    else if (op == nir_op_ior)
6459       return bld.sop2(Builder::s_or, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
6460    else if (op == nir_op_ixor)
6461       return bld.sop2(Builder::s_xor, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
6462
6463    assert(false);
6464    return Temp();
6465 }
6466
6467 void emit_uniform_subgroup(isel_context *ctx, nir_intrinsic_instr *instr, Temp src)
6468 {
6469    Builder bld(ctx->program, ctx->block);
6470    Definition dst(get_ssa_temp(ctx, &instr->dest.ssa));
6471    if (src.regClass().type() == RegType::vgpr) {
6472       bld.pseudo(aco_opcode::p_as_uniform, dst, src);
6473    } else if (src.regClass() == s1) {
6474       bld.sop1(aco_opcode::s_mov_b32, dst, src);
6475    } else if (src.regClass() == s2) {
6476       bld.sop1(aco_opcode::s_mov_b64, dst, src);
6477    } else {
6478       fprintf(stderr, "Unimplemented NIR instr bit size: ");
6479       nir_print_instr(&instr->instr, stderr);
6480       fprintf(stderr, "\n");
6481    }
6482 }
6483
6484 void emit_interp_center(isel_context *ctx, Temp dst, Temp pos1, Temp pos2)
6485 {
6486    Builder bld(ctx->program, ctx->block);
6487    Temp persp_center = get_arg(ctx, ctx->args->ac.persp_center);
6488    Temp p1 = emit_extract_vector(ctx, persp_center, 0, v1);
6489    Temp p2 = emit_extract_vector(ctx, persp_center, 1, v1);
6490
6491    Temp ddx_1, ddx_2, ddy_1, ddy_2;
6492    uint32_t dpp_ctrl0 = dpp_quad_perm(0, 0, 0, 0);
6493    uint32_t dpp_ctrl1 = dpp_quad_perm(1, 1, 1, 1);
6494    uint32_t dpp_ctrl2 = dpp_quad_perm(2, 2, 2, 2);
6495
6496    /* Build DD X/Y */
6497    if (ctx->program->chip_class >= GFX8) {
6498       Temp tl_1 = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), p1, dpp_ctrl0);
6499       ddx_1 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p1, tl_1, dpp_ctrl1);
6500       ddy_1 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p1, tl_1, dpp_ctrl2);
6501       Temp tl_2 = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), p2, dpp_ctrl0);
6502       ddx_2 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p2, tl_2, dpp_ctrl1);
6503       ddy_2 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p2, tl_2, dpp_ctrl2);
6504    } else {
6505       Temp tl_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl0);
6506       ddx_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl1);
6507       ddx_1 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddx_1, tl_1);
6508       ddx_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl2);
6509       ddx_2 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddx_2, tl_1);
6510       Temp tl_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl0);
6511       ddy_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl1);
6512       ddy_1 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddy_1, tl_2);
6513       ddy_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl2);
6514       ddy_2 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddy_2, tl_2);
6515    }
6516
6517    /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
6518    Temp tmp1 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddx_1, pos1, p1);
6519    Temp tmp2 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddx_2, pos1, p2);
6520    tmp1 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddy_1, pos2, tmp1);
6521    tmp2 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddy_2, pos2, tmp2);
6522    Temp wqm1 = bld.tmp(v1);
6523    emit_wqm(ctx, tmp1, wqm1, true);
6524    Temp wqm2 = bld.tmp(v1);
6525    emit_wqm(ctx, tmp2, wqm2, true);
6526    bld.pseudo(aco_opcode::p_create_vector, Definition(dst), wqm1, wqm2);
6527    return;
6528 }
6529
6530 void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr)
6531 {
6532    Builder bld(ctx->program, ctx->block);
6533    switch(instr->intrinsic) {
6534    case nir_intrinsic_load_barycentric_sample:
6535    case nir_intrinsic_load_barycentric_pixel:
6536    case nir_intrinsic_load_barycentric_centroid: {
6537       glsl_interp_mode mode = (glsl_interp_mode)nir_intrinsic_interp_mode(instr);
6538       Temp bary = Temp(0, s2);
6539       switch (mode) {
6540       case INTERP_MODE_SMOOTH:
6541       case INTERP_MODE_NONE:
6542          if (instr->intrinsic == nir_intrinsic_load_barycentric_pixel)
6543             bary = get_arg(ctx, ctx->args->ac.persp_center);
6544          else if (instr->intrinsic == nir_intrinsic_load_barycentric_centroid)
6545             bary = ctx->persp_centroid;
6546          else if (instr->intrinsic == nir_intrinsic_load_barycentric_sample)
6547             bary = get_arg(ctx, ctx->args->ac.persp_sample);
6548          break;
6549       case INTERP_MODE_NOPERSPECTIVE:
6550          if (instr->intrinsic == nir_intrinsic_load_barycentric_pixel)
6551             bary = get_arg(ctx, ctx->args->ac.linear_center);
6552          else if (instr->intrinsic == nir_intrinsic_load_barycentric_centroid)
6553             bary = ctx->linear_centroid;
6554          else if (instr->intrinsic == nir_intrinsic_load_barycentric_sample)
6555             bary = get_arg(ctx, ctx->args->ac.linear_sample);
6556          break;
6557       default:
6558          break;
6559       }
6560       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6561       Temp p1 = emit_extract_vector(ctx, bary, 0, v1);
6562       Temp p2 = emit_extract_vector(ctx, bary, 1, v1);
6563       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
6564                  Operand(p1), Operand(p2));
6565       emit_split_vector(ctx, dst, 2);
6566       break;
6567    }
6568    case nir_intrinsic_load_barycentric_model: {
6569       Temp model = get_arg(ctx, ctx->args->ac.pull_model);
6570
6571       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6572       Temp p1 = emit_extract_vector(ctx, model, 0, v1);
6573       Temp p2 = emit_extract_vector(ctx, model, 1, v1);
6574       Temp p3 = emit_extract_vector(ctx, model, 2, v1);
6575       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
6576                  Operand(p1), Operand(p2), Operand(p3));
6577       emit_split_vector(ctx, dst, 3);
6578       break;
6579    }
6580    case nir_intrinsic_load_barycentric_at_sample: {
6581       uint32_t sample_pos_offset = RING_PS_SAMPLE_POSITIONS * 16;
6582       switch (ctx->options->key.fs.num_samples) {
6583          case 2: sample_pos_offset += 1 << 3; break;
6584          case 4: sample_pos_offset += 3 << 3; break;
6585          case 8: sample_pos_offset += 7 << 3; break;
6586          default: break;
6587       }
6588       Temp sample_pos;
6589       Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
6590       nir_const_value* const_addr = nir_src_as_const_value(instr->src[0]);
6591       Temp private_segment_buffer = ctx->program->private_segment_buffer;
6592       if (addr.type() == RegType::sgpr) {
6593          Operand offset;
6594          if (const_addr) {
6595             sample_pos_offset += const_addr->u32 << 3;
6596             offset = Operand(sample_pos_offset);
6597          } else if (ctx->options->chip_class >= GFX9) {
6598             offset = bld.sop2(aco_opcode::s_lshl3_add_u32, bld.def(s1), bld.def(s1, scc), addr, Operand(sample_pos_offset));
6599          } else {
6600             offset = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), addr, Operand(3u));
6601             offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), addr, Operand(sample_pos_offset));
6602          }
6603
6604          Operand off = bld.copy(bld.def(s1), Operand(offset));
6605          sample_pos = bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), private_segment_buffer, off);
6606
6607       } else if (ctx->options->chip_class >= GFX9) {
6608          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
6609          sample_pos = bld.global(aco_opcode::global_load_dwordx2, bld.def(v2), addr, private_segment_buffer, sample_pos_offset);
6610       } else if (ctx->options->chip_class >= GFX7) {
6611          /* addr += private_segment_buffer + sample_pos_offset */
6612          Temp tmp0 = bld.tmp(s1);
6613          Temp tmp1 = bld.tmp(s1);
6614          bld.pseudo(aco_opcode::p_split_vector, Definition(tmp0), Definition(tmp1), private_segment_buffer);
6615          Definition scc_tmp = bld.def(s1, scc);
6616          tmp0 = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), scc_tmp, tmp0, Operand(sample_pos_offset));
6617          tmp1 = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), tmp1, Operand(0u), bld.scc(scc_tmp.getTemp()));
6618          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
6619          Temp pck0 = bld.tmp(v1);
6620          Temp carry = bld.vadd32(Definition(pck0), tmp0, addr, true).def(1).getTemp();
6621          tmp1 = as_vgpr(ctx, tmp1);
6622          Temp pck1 = bld.vop2_e64(aco_opcode::v_addc_co_u32, bld.def(v1), bld.hint_vcc(bld.def(bld.lm)), tmp1, Operand(0u), carry);
6623          addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), pck0, pck1);
6624
6625          /* sample_pos = flat_load_dwordx2 addr */
6626          sample_pos = bld.flat(aco_opcode::flat_load_dwordx2, bld.def(v2), addr, Operand(s1));
6627       } else {
6628          assert(ctx->options->chip_class == GFX6);
6629
6630          uint32_t rsrc_conf = S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
6631                               S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
6632          Temp rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), private_segment_buffer, Operand(0u), Operand(rsrc_conf));
6633
6634          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
6635          addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), addr, Operand(0u));
6636
6637          sample_pos = bld.tmp(v2);
6638
6639          aco_ptr<MUBUF_instruction> load{create_instruction<MUBUF_instruction>(aco_opcode::buffer_load_dwordx2, Format::MUBUF, 3, 1)};
6640          load->definitions[0] = Definition(sample_pos);
6641          load->operands[0] = Operand(rsrc);
6642          load->operands[1] = Operand(addr);
6643          load->operands[2] = Operand(0u);
6644          load->offset = sample_pos_offset;
6645          load->offen = 0;
6646          load->addr64 = true;
6647          load->glc = false;
6648          load->dlc = false;
6649          load->disable_wqm = false;
6650          load->barrier = barrier_none;
6651          load->can_reorder = true;
6652          ctx->block->instructions.emplace_back(std::move(load));
6653       }
6654
6655       /* sample_pos -= 0.5 */
6656       Temp pos1 = bld.tmp(RegClass(sample_pos.type(), 1));
6657       Temp pos2 = bld.tmp(RegClass(sample_pos.type(), 1));
6658       bld.pseudo(aco_opcode::p_split_vector, Definition(pos1), Definition(pos2), sample_pos);
6659       pos1 = bld.vop2_e64(aco_opcode::v_sub_f32, bld.def(v1), pos1, Operand(0x3f000000u));
6660       pos2 = bld.vop2_e64(aco_opcode::v_sub_f32, bld.def(v1), pos2, Operand(0x3f000000u));
6661
6662       emit_interp_center(ctx, get_ssa_temp(ctx, &instr->dest.ssa), pos1, pos2);
6663       break;
6664    }
6665    case nir_intrinsic_load_barycentric_at_offset: {
6666       Temp offset = get_ssa_temp(ctx, instr->src[0].ssa);
6667       RegClass rc = RegClass(offset.type(), 1);
6668       Temp pos1 = bld.tmp(rc), pos2 = bld.tmp(rc);
6669       bld.pseudo(aco_opcode::p_split_vector, Definition(pos1), Definition(pos2), offset);
6670       emit_interp_center(ctx, get_ssa_temp(ctx, &instr->dest.ssa), pos1, pos2);
6671       break;
6672    }
6673    case nir_intrinsic_load_front_face: {
6674       bld.vopc(aco_opcode::v_cmp_lg_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6675                Operand(0u), get_arg(ctx, ctx->args->ac.front_face)).def(0).setHint(vcc);
6676       break;
6677    }
6678    case nir_intrinsic_load_view_index: {
6679       if (ctx->stage & (sw_vs | sw_gs | sw_tcs | sw_tes)) {
6680          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6681          bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.view_index)));
6682          break;
6683       }
6684
6685       /* fallthrough */
6686    }
6687    case nir_intrinsic_load_layer_id: {
6688       unsigned idx = nir_intrinsic_base(instr);
6689       bld.vintrp(aco_opcode::v_interp_mov_f32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6690                  Operand(2u), bld.m0(get_arg(ctx, ctx->args->ac.prim_mask)), idx, 0);
6691       break;
6692    }
6693    case nir_intrinsic_load_frag_coord: {
6694       emit_load_frag_coord(ctx, get_ssa_temp(ctx, &instr->dest.ssa), 4);
6695       break;
6696    }
6697    case nir_intrinsic_load_sample_pos: {
6698       Temp posx = get_arg(ctx, ctx->args->ac.frag_pos[0]);
6699       Temp posy = get_arg(ctx, ctx->args->ac.frag_pos[1]);
6700       bld.pseudo(aco_opcode::p_create_vector, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6701                  posx.id() ? bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), posx) : Operand(0u),
6702                  posy.id() ? bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), posy) : Operand(0u));
6703       break;
6704    }
6705    case nir_intrinsic_load_tess_coord:
6706       visit_load_tess_coord(ctx, instr);
6707       break;
6708    case nir_intrinsic_load_interpolated_input:
6709       visit_load_interpolated_input(ctx, instr);
6710       break;
6711    case nir_intrinsic_store_output:
6712       visit_store_output(ctx, instr);
6713       break;
6714    case nir_intrinsic_load_input:
6715    case nir_intrinsic_load_input_vertex:
6716       visit_load_input(ctx, instr);
6717       break;
6718    case nir_intrinsic_load_output:
6719       visit_load_output(ctx, instr);
6720       break;
6721    case nir_intrinsic_load_per_vertex_input:
6722       visit_load_per_vertex_input(ctx, instr);
6723       break;
6724    case nir_intrinsic_load_per_vertex_output:
6725       visit_load_per_vertex_output(ctx, instr);
6726       break;
6727    case nir_intrinsic_store_per_vertex_output:
6728       visit_store_per_vertex_output(ctx, instr);
6729       break;
6730    case nir_intrinsic_load_ubo:
6731       visit_load_ubo(ctx, instr);
6732       break;
6733    case nir_intrinsic_load_push_constant:
6734       visit_load_push_constant(ctx, instr);
6735       break;
6736    case nir_intrinsic_load_constant:
6737       visit_load_constant(ctx, instr);
6738       break;
6739    case nir_intrinsic_vulkan_resource_index:
6740       visit_load_resource(ctx, instr);
6741       break;
6742    case nir_intrinsic_discard:
6743       visit_discard(ctx, instr);
6744       break;
6745    case nir_intrinsic_discard_if:
6746       visit_discard_if(ctx, instr);
6747       break;
6748    case nir_intrinsic_load_shared:
6749       visit_load_shared(ctx, instr);
6750       break;
6751    case nir_intrinsic_store_shared:
6752       visit_store_shared(ctx, instr);
6753       break;
6754    case nir_intrinsic_shared_atomic_add:
6755    case nir_intrinsic_shared_atomic_imin:
6756    case nir_intrinsic_shared_atomic_umin:
6757    case nir_intrinsic_shared_atomic_imax:
6758    case nir_intrinsic_shared_atomic_umax:
6759    case nir_intrinsic_shared_atomic_and:
6760    case nir_intrinsic_shared_atomic_or:
6761    case nir_intrinsic_shared_atomic_xor:
6762    case nir_intrinsic_shared_atomic_exchange:
6763    case nir_intrinsic_shared_atomic_comp_swap:
6764       visit_shared_atomic(ctx, instr);
6765       break;
6766    case nir_intrinsic_image_deref_load:
6767       visit_image_load(ctx, instr);
6768       break;
6769    case nir_intrinsic_image_deref_store:
6770       visit_image_store(ctx, instr);
6771       break;
6772    case nir_intrinsic_image_deref_atomic_add:
6773    case nir_intrinsic_image_deref_atomic_umin:
6774    case nir_intrinsic_image_deref_atomic_imin:
6775    case nir_intrinsic_image_deref_atomic_umax:
6776    case nir_intrinsic_image_deref_atomic_imax:
6777    case nir_intrinsic_image_deref_atomic_and:
6778    case nir_intrinsic_image_deref_atomic_or:
6779    case nir_intrinsic_image_deref_atomic_xor:
6780    case nir_intrinsic_image_deref_atomic_exchange:
6781    case nir_intrinsic_image_deref_atomic_comp_swap:
6782       visit_image_atomic(ctx, instr);
6783       break;
6784    case nir_intrinsic_image_deref_size:
6785       visit_image_size(ctx, instr);
6786       break;
6787    case nir_intrinsic_load_ssbo:
6788       visit_load_ssbo(ctx, instr);
6789       break;
6790    case nir_intrinsic_store_ssbo:
6791       visit_store_ssbo(ctx, instr);
6792       break;
6793    case nir_intrinsic_load_global:
6794       visit_load_global(ctx, instr);
6795       break;
6796    case nir_intrinsic_store_global:
6797       visit_store_global(ctx, instr);
6798       break;
6799    case nir_intrinsic_global_atomic_add:
6800    case nir_intrinsic_global_atomic_imin:
6801    case nir_intrinsic_global_atomic_umin:
6802    case nir_intrinsic_global_atomic_imax:
6803    case nir_intrinsic_global_atomic_umax:
6804    case nir_intrinsic_global_atomic_and:
6805    case nir_intrinsic_global_atomic_or:
6806    case nir_intrinsic_global_atomic_xor:
6807    case nir_intrinsic_global_atomic_exchange:
6808    case nir_intrinsic_global_atomic_comp_swap:
6809       visit_global_atomic(ctx, instr);
6810       break;
6811    case nir_intrinsic_ssbo_atomic_add:
6812    case nir_intrinsic_ssbo_atomic_imin:
6813    case nir_intrinsic_ssbo_atomic_umin:
6814    case nir_intrinsic_ssbo_atomic_imax:
6815    case nir_intrinsic_ssbo_atomic_umax:
6816    case nir_intrinsic_ssbo_atomic_and:
6817    case nir_intrinsic_ssbo_atomic_or:
6818    case nir_intrinsic_ssbo_atomic_xor:
6819    case nir_intrinsic_ssbo_atomic_exchange:
6820    case nir_intrinsic_ssbo_atomic_comp_swap:
6821       visit_atomic_ssbo(ctx, instr);
6822       break;
6823    case nir_intrinsic_load_scratch:
6824       visit_load_scratch(ctx, instr);
6825       break;
6826    case nir_intrinsic_store_scratch:
6827       visit_store_scratch(ctx, instr);
6828       break;
6829    case nir_intrinsic_get_buffer_size:
6830       visit_get_buffer_size(ctx, instr);
6831       break;
6832    case nir_intrinsic_control_barrier: {
6833       if (ctx->program->chip_class == GFX6 && ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) {
6834          /* GFX6 only (thanks to a hw bug workaround):
6835           * The real barrier instruction isn’t needed, because an entire patch
6836           * always fits into a single wave.
6837           */
6838          break;
6839       }
6840
6841       if (ctx->program->workgroup_size > ctx->program->wave_size)
6842          bld.sopp(aco_opcode::s_barrier);
6843
6844       break;
6845    }
6846    case nir_intrinsic_memory_barrier_tcs_patch:
6847    case nir_intrinsic_group_memory_barrier:
6848    case nir_intrinsic_memory_barrier:
6849    case nir_intrinsic_memory_barrier_buffer:
6850    case nir_intrinsic_memory_barrier_image:
6851    case nir_intrinsic_memory_barrier_shared:
6852       emit_memory_barrier(ctx, instr);
6853       break;
6854    case nir_intrinsic_load_num_work_groups: {
6855       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6856       bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.num_work_groups)));
6857       emit_split_vector(ctx, dst, 3);
6858       break;
6859    }
6860    case nir_intrinsic_load_local_invocation_id: {
6861       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6862       bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.local_invocation_ids)));
6863       emit_split_vector(ctx, dst, 3);
6864       break;
6865    }
6866    case nir_intrinsic_load_work_group_id: {
6867       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6868       struct ac_arg *args = ctx->args->ac.workgroup_ids;
6869       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
6870                  args[0].used ? Operand(get_arg(ctx, args[0])) : Operand(0u),
6871                  args[1].used ? Operand(get_arg(ctx, args[1])) : Operand(0u),
6872                  args[2].used ? Operand(get_arg(ctx, args[2])) : Operand(0u));
6873       emit_split_vector(ctx, dst, 3);
6874       break;
6875    }
6876    case nir_intrinsic_load_local_invocation_index: {
6877       Temp id = emit_mbcnt(ctx, bld.def(v1));
6878
6879       /* The tg_size bits [6:11] contain the subgroup id,
6880        * we need this multiplied by the wave size, and then OR the thread id to it.
6881        */
6882       if (ctx->program->wave_size == 64) {
6883          /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
6884          Temp tg_num = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0xfc0u),
6885                                 get_arg(ctx, ctx->args->ac.tg_size));
6886          bld.vop2(aco_opcode::v_or_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), tg_num, id);
6887       } else {
6888          /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR  */
6889          Temp tg_num = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
6890                                 get_arg(ctx, ctx->args->ac.tg_size), Operand(0x6u | (0x6u << 16)));
6891          bld.vop3(aco_opcode::v_lshl_or_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), tg_num, Operand(0x5u), id);
6892       }
6893       break;
6894    }
6895    case nir_intrinsic_load_subgroup_id: {
6896       if (ctx->stage == compute_cs) {
6897          bld.sop2(aco_opcode::s_bfe_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), bld.def(s1, scc),
6898                   get_arg(ctx, ctx->args->ac.tg_size), Operand(0x6u | (0x6u << 16)));
6899       } else {
6900          bld.sop1(aco_opcode::s_mov_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand(0x0u));
6901       }
6902       break;
6903    }
6904    case nir_intrinsic_load_subgroup_invocation: {
6905       emit_mbcnt(ctx, Definition(get_ssa_temp(ctx, &instr->dest.ssa)));
6906       break;
6907    }
6908    case nir_intrinsic_load_num_subgroups: {
6909       if (ctx->stage == compute_cs)
6910          bld.sop2(aco_opcode::s_and_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), bld.def(s1, scc), Operand(0x3fu),
6911                   get_arg(ctx, ctx->args->ac.tg_size));
6912       else
6913          bld.sop1(aco_opcode::s_mov_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand(0x1u));
6914       break;
6915    }
6916    case nir_intrinsic_ballot: {
6917       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6918       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6919       Definition tmp = bld.def(dst.regClass());
6920       Definition lanemask_tmp = dst.size() == bld.lm.size() ? tmp : bld.def(src.regClass());
6921       if (instr->src[0].ssa->bit_size == 1) {
6922          assert(src.regClass() == bld.lm);
6923          bld.sop2(Builder::s_and, lanemask_tmp, bld.def(s1, scc), Operand(exec, bld.lm), src);
6924       } else if (instr->src[0].ssa->bit_size == 32 && src.regClass() == v1) {
6925          bld.vopc(aco_opcode::v_cmp_lg_u32, lanemask_tmp, Operand(0u), src);
6926       } else if (instr->src[0].ssa->bit_size == 64 && src.regClass() == v2) {
6927          bld.vopc(aco_opcode::v_cmp_lg_u64, lanemask_tmp, Operand(0u), src);
6928       } else {
6929          fprintf(stderr, "Unimplemented NIR instr bit size: ");
6930          nir_print_instr(&instr->instr, stderr);
6931          fprintf(stderr, "\n");
6932       }
6933       if (dst.size() != bld.lm.size()) {
6934          /* Wave32 with ballot size set to 64 */
6935          bld.pseudo(aco_opcode::p_create_vector, Definition(tmp), lanemask_tmp.getTemp(), Operand(0u));
6936       }
6937       emit_wqm(ctx, tmp.getTemp(), dst);
6938       break;
6939    }
6940    case nir_intrinsic_shuffle:
6941    case nir_intrinsic_read_invocation: {
6942       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6943       if (!ctx->divergent_vals[instr->src[0].ssa->index]) {
6944          emit_uniform_subgroup(ctx, instr, src);
6945       } else {
6946          Temp tid = get_ssa_temp(ctx, instr->src[1].ssa);
6947          if (instr->intrinsic == nir_intrinsic_read_invocation || !ctx->divergent_vals[instr->src[1].ssa->index])
6948             tid = bld.as_uniform(tid);
6949          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6950          if (src.regClass() == v1) {
6951             emit_wqm(ctx, emit_bpermute(ctx, bld, tid, src), dst);
6952          } else if (src.regClass() == v2) {
6953             Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6954             bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6955             lo = emit_wqm(ctx, emit_bpermute(ctx, bld, tid, lo));
6956             hi = emit_wqm(ctx, emit_bpermute(ctx, bld, tid, hi));
6957             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6958             emit_split_vector(ctx, dst, 2);
6959          } else if (instr->dest.ssa.bit_size == 1 && tid.regClass() == s1) {
6960             assert(src.regClass() == bld.lm);
6961             Temp tmp = bld.sopc(Builder::s_bitcmp1, bld.def(s1, scc), src, tid);
6962             bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
6963          } else if (instr->dest.ssa.bit_size == 1 && tid.regClass() == v1) {
6964             assert(src.regClass() == bld.lm);
6965             Temp tmp;
6966             if (ctx->program->chip_class <= GFX7)
6967                tmp = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), src, tid);
6968             else if (ctx->program->wave_size == 64)
6969                tmp = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), tid, src);
6970             else
6971                tmp = bld.vop2_e64(aco_opcode::v_lshrrev_b32, bld.def(v1), tid, src);
6972             tmp = emit_extract_vector(ctx, tmp, 0, v1);
6973             tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u), tmp);
6974             emit_wqm(ctx, bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp), dst);
6975          } else {
6976             fprintf(stderr, "Unimplemented NIR instr bit size: ");
6977             nir_print_instr(&instr->instr, stderr);
6978             fprintf(stderr, "\n");
6979          }
6980       }
6981       break;
6982    }
6983    case nir_intrinsic_load_sample_id: {
6984       bld.vop3(aco_opcode::v_bfe_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6985                get_arg(ctx, ctx->args->ac.ancillary), Operand(8u), Operand(4u));
6986       break;
6987    }
6988    case nir_intrinsic_load_sample_mask_in: {
6989       visit_load_sample_mask_in(ctx, instr);
6990       break;
6991    }
6992    case nir_intrinsic_read_first_invocation: {
6993       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6994       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6995       if (src.regClass() == v1) {
6996          emit_wqm(ctx,
6997                   bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), src),
6998                   dst);
6999       } else if (src.regClass() == v2) {
7000          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
7001          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
7002          lo = emit_wqm(ctx, bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), lo));
7003          hi = emit_wqm(ctx, bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), hi));
7004          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
7005          emit_split_vector(ctx, dst, 2);
7006       } else if (instr->dest.ssa.bit_size == 1) {
7007          assert(src.regClass() == bld.lm);
7008          Temp tmp = bld.sopc(Builder::s_bitcmp1, bld.def(s1, scc), src,
7009                              bld.sop1(Builder::s_ff1_i32, bld.def(s1), Operand(exec, bld.lm)));
7010          bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
7011       } else if (src.regClass() == s1) {
7012          bld.sop1(aco_opcode::s_mov_b32, Definition(dst), src);
7013       } else if (src.regClass() == s2) {
7014          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src);
7015       } else {
7016          fprintf(stderr, "Unimplemented NIR instr bit size: ");
7017          nir_print_instr(&instr->instr, stderr);
7018          fprintf(stderr, "\n");
7019       }
7020       break;
7021    }
7022    case nir_intrinsic_vote_all: {
7023       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7024       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7025       assert(src.regClass() == bld.lm);
7026       assert(dst.regClass() == bld.lm);
7027
7028       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src).def(1).getTemp();
7029       Temp cond = bool_to_vector_condition(ctx, emit_wqm(ctx, tmp));
7030       bld.sop1(Builder::s_not, Definition(dst), bld.def(s1, scc), cond);
7031       break;
7032    }
7033    case nir_intrinsic_vote_any: {
7034       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7035       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7036       assert(src.regClass() == bld.lm);
7037       assert(dst.regClass() == bld.lm);
7038
7039       Temp tmp = bool_to_scalar_condition(ctx, src);
7040       bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
7041       break;
7042    }
7043    case nir_intrinsic_reduce:
7044    case nir_intrinsic_inclusive_scan:
7045    case nir_intrinsic_exclusive_scan: {
7046       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7047       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7048       nir_op op = (nir_op) nir_intrinsic_reduction_op(instr);
7049       unsigned cluster_size = instr->intrinsic == nir_intrinsic_reduce ?
7050          nir_intrinsic_cluster_size(instr) : 0;
7051       cluster_size = util_next_power_of_two(MIN2(cluster_size ? cluster_size : ctx->program->wave_size, ctx->program->wave_size));
7052
7053       if (!ctx->divergent_vals[instr->src[0].ssa->index] && (op == nir_op_ior || op == nir_op_iand)) {
7054          emit_uniform_subgroup(ctx, instr, src);
7055       } else if (instr->dest.ssa.bit_size == 1) {
7056          if (op == nir_op_imul || op == nir_op_umin || op == nir_op_imin)
7057             op = nir_op_iand;
7058          else if (op == nir_op_iadd)
7059             op = nir_op_ixor;
7060          else if (op == nir_op_umax || op == nir_op_imax)
7061             op = nir_op_ior;
7062          assert(op == nir_op_iand || op == nir_op_ior || op == nir_op_ixor);
7063
7064          switch (instr->intrinsic) {
7065          case nir_intrinsic_reduce:
7066             emit_wqm(ctx, emit_boolean_reduce(ctx, op, cluster_size, src), dst);
7067             break;
7068          case nir_intrinsic_exclusive_scan:
7069             emit_wqm(ctx, emit_boolean_exclusive_scan(ctx, op, src), dst);
7070             break;
7071          case nir_intrinsic_inclusive_scan:
7072             emit_wqm(ctx, emit_boolean_inclusive_scan(ctx, op, src), dst);
7073             break;
7074          default:
7075             assert(false);
7076          }
7077       } else if (cluster_size == 1) {
7078          bld.copy(Definition(dst), src);
7079       } else {
7080          src = as_vgpr(ctx, src);
7081
7082          ReduceOp reduce_op;
7083          switch (op) {
7084          #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
7085             CASE(iadd)
7086             CASE(imul)
7087             CASE(fadd)
7088             CASE(fmul)
7089             CASE(imin)
7090             CASE(umin)
7091             CASE(fmin)
7092             CASE(imax)
7093             CASE(umax)
7094             CASE(fmax)
7095             CASE(iand)
7096             CASE(ior)
7097             CASE(ixor)
7098             default:
7099                unreachable("unknown reduction op");
7100          #undef CASE
7101          }
7102
7103          aco_opcode aco_op;
7104          switch (instr->intrinsic) {
7105             case nir_intrinsic_reduce: aco_op = aco_opcode::p_reduce; break;
7106             case nir_intrinsic_inclusive_scan: aco_op = aco_opcode::p_inclusive_scan; break;
7107             case nir_intrinsic_exclusive_scan: aco_op = aco_opcode::p_exclusive_scan; break;
7108             default:
7109                unreachable("unknown reduce intrinsic");
7110          }
7111
7112          aco_ptr<Pseudo_reduction_instruction> reduce{create_instruction<Pseudo_reduction_instruction>(aco_op, Format::PSEUDO_REDUCTION, 3, 5)};
7113          reduce->operands[0] = Operand(src);
7114          // filled in by aco_reduce_assign.cpp, used internally as part of the
7115          // reduce sequence
7116          assert(dst.size() == 1 || dst.size() == 2);
7117          reduce->operands[1] = Operand(RegClass(RegType::vgpr, dst.size()).as_linear());
7118          reduce->operands[2] = Operand(v1.as_linear());
7119
7120          Temp tmp_dst = bld.tmp(dst.regClass());
7121          reduce->definitions[0] = Definition(tmp_dst);
7122          reduce->definitions[1] = bld.def(ctx->program->lane_mask); // used internally
7123          reduce->definitions[2] = Definition();
7124          reduce->definitions[3] = Definition(scc, s1);
7125          reduce->definitions[4] = Definition();
7126          reduce->reduce_op = reduce_op;
7127          reduce->cluster_size = cluster_size;
7128          ctx->block->instructions.emplace_back(std::move(reduce));
7129
7130          emit_wqm(ctx, tmp_dst, dst);
7131       }
7132       break;
7133    }
7134    case nir_intrinsic_quad_broadcast: {
7135       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7136       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
7137          emit_uniform_subgroup(ctx, instr, src);
7138       } else {
7139          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7140          unsigned lane = nir_src_as_const_value(instr->src[1])->u32;
7141          uint32_t dpp_ctrl = dpp_quad_perm(lane, lane, lane, lane);
7142
7143          if (instr->dest.ssa.bit_size == 1) {
7144             assert(src.regClass() == bld.lm);
7145             assert(dst.regClass() == bld.lm);
7146             uint32_t half_mask = 0x11111111u << lane;
7147             Temp mask_tmp = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(half_mask), Operand(half_mask));
7148             Temp tmp = bld.tmp(bld.lm);
7149             bld.sop1(Builder::s_wqm, Definition(tmp),
7150                      bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), mask_tmp,
7151                               bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm))));
7152             emit_wqm(ctx, tmp, dst);
7153          } else if (instr->dest.ssa.bit_size == 32) {
7154             if (ctx->program->chip_class >= GFX8)
7155                emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl), dst);
7156             else
7157                emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl), dst);
7158          } else if (instr->dest.ssa.bit_size == 64) {
7159             Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
7160             bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
7161             if (ctx->program->chip_class >= GFX8) {
7162                lo = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), lo, dpp_ctrl));
7163                hi = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), hi, dpp_ctrl));
7164             } else {
7165                lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, (1 << 15) | dpp_ctrl));
7166                hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, (1 << 15) | dpp_ctrl));
7167             }
7168             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
7169             emit_split_vector(ctx, dst, 2);
7170          } else {
7171             fprintf(stderr, "Unimplemented NIR instr bit size: ");
7172             nir_print_instr(&instr->instr, stderr);
7173             fprintf(stderr, "\n");
7174          }
7175       }
7176       break;
7177    }
7178    case nir_intrinsic_quad_swap_horizontal:
7179    case nir_intrinsic_quad_swap_vertical:
7180    case nir_intrinsic_quad_swap_diagonal:
7181    case nir_intrinsic_quad_swizzle_amd: {
7182       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7183       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
7184          emit_uniform_subgroup(ctx, instr, src);
7185          break;
7186       }
7187       uint16_t dpp_ctrl = 0;
7188       switch (instr->intrinsic) {
7189       case nir_intrinsic_quad_swap_horizontal:
7190          dpp_ctrl = dpp_quad_perm(1, 0, 3, 2);
7191          break;
7192       case nir_intrinsic_quad_swap_vertical:
7193          dpp_ctrl = dpp_quad_perm(2, 3, 0, 1);
7194          break;
7195       case nir_intrinsic_quad_swap_diagonal:
7196          dpp_ctrl = dpp_quad_perm(3, 2, 1, 0);
7197          break;
7198       case nir_intrinsic_quad_swizzle_amd:
7199          dpp_ctrl = nir_intrinsic_swizzle_mask(instr);
7200          break;
7201       default:
7202          break;
7203       }
7204       if (ctx->program->chip_class < GFX8)
7205          dpp_ctrl |= (1 << 15);
7206
7207       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7208       if (instr->dest.ssa.bit_size == 1) {
7209          assert(src.regClass() == bld.lm);
7210          src = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand((uint32_t)-1), src);
7211          if (ctx->program->chip_class >= GFX8)
7212             src = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl);
7213          else
7214             src = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, dpp_ctrl);
7215          Temp tmp = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), src);
7216          emit_wqm(ctx, tmp, dst);
7217       } else if (instr->dest.ssa.bit_size == 32) {
7218          Temp tmp;
7219          if (ctx->program->chip_class >= GFX8)
7220             tmp = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl);
7221          else
7222             tmp = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, dpp_ctrl);
7223          emit_wqm(ctx, tmp, dst);
7224       } else if (instr->dest.ssa.bit_size == 64) {
7225          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
7226          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
7227          if (ctx->program->chip_class >= GFX8) {
7228             lo = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), lo, dpp_ctrl));
7229             hi = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), hi, dpp_ctrl));
7230          } else {
7231             lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, dpp_ctrl));
7232             hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, dpp_ctrl));
7233          }
7234          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
7235          emit_split_vector(ctx, dst, 2);
7236       } else {
7237          fprintf(stderr, "Unimplemented NIR instr bit size: ");
7238          nir_print_instr(&instr->instr, stderr);
7239          fprintf(stderr, "\n");
7240       }
7241       break;
7242    }
7243    case nir_intrinsic_masked_swizzle_amd: {
7244       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7245       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
7246          emit_uniform_subgroup(ctx, instr, src);
7247          break;
7248       }
7249       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7250       uint32_t mask = nir_intrinsic_swizzle_mask(instr);
7251       if (dst.regClass() == v1) {
7252          emit_wqm(ctx,
7253                   bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, mask, 0, false),
7254                   dst);
7255       } else if (dst.regClass() == v2) {
7256          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
7257          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
7258          lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, mask, 0, false));
7259          hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, mask, 0, false));
7260          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
7261          emit_split_vector(ctx, dst, 2);
7262       } else {
7263          fprintf(stderr, "Unimplemented NIR instr bit size: ");
7264          nir_print_instr(&instr->instr, stderr);
7265          fprintf(stderr, "\n");
7266       }
7267       break;
7268    }
7269    case nir_intrinsic_write_invocation_amd: {
7270       Temp src = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
7271       Temp val = bld.as_uniform(get_ssa_temp(ctx, instr->src[1].ssa));
7272       Temp lane = bld.as_uniform(get_ssa_temp(ctx, instr->src[2].ssa));
7273       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7274       if (dst.regClass() == v1) {
7275          /* src2 is ignored for writelane. RA assigns the same reg for dst */
7276          emit_wqm(ctx, bld.writelane(bld.def(v1), val, lane, src), dst);
7277       } else if (dst.regClass() == v2) {
7278          Temp src_lo = bld.tmp(v1), src_hi = bld.tmp(v1);
7279          Temp val_lo = bld.tmp(s1), val_hi = bld.tmp(s1);
7280          bld.pseudo(aco_opcode::p_split_vector, Definition(src_lo), Definition(src_hi), src);
7281          bld.pseudo(aco_opcode::p_split_vector, Definition(val_lo), Definition(val_hi), val);
7282          Temp lo = emit_wqm(ctx, bld.writelane(bld.def(v1), val_lo, lane, src_hi));
7283          Temp hi = emit_wqm(ctx, bld.writelane(bld.def(v1), val_hi, lane, src_hi));
7284          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
7285          emit_split_vector(ctx, dst, 2);
7286       } else {
7287          fprintf(stderr, "Unimplemented NIR instr bit size: ");
7288          nir_print_instr(&instr->instr, stderr);
7289          fprintf(stderr, "\n");
7290       }
7291       break;
7292    }
7293    case nir_intrinsic_mbcnt_amd: {
7294       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7295       RegClass rc = RegClass(src.type(), 1);
7296       Temp mask_lo = bld.tmp(rc), mask_hi = bld.tmp(rc);
7297       bld.pseudo(aco_opcode::p_split_vector, Definition(mask_lo), Definition(mask_hi), src);
7298       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7299       Temp wqm_tmp = emit_mbcnt(ctx, bld.def(v1), Operand(mask_lo), Operand(mask_hi));
7300       emit_wqm(ctx, wqm_tmp, dst);
7301       break;
7302    }
7303    case nir_intrinsic_load_helper_invocation: {
7304       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7305       bld.pseudo(aco_opcode::p_load_helper, Definition(dst));
7306       ctx->block->kind |= block_kind_needs_lowering;
7307       ctx->program->needs_exact = true;
7308       break;
7309    }
7310    case nir_intrinsic_is_helper_invocation: {
7311       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7312       bld.pseudo(aco_opcode::p_is_helper, Definition(dst));
7313       ctx->block->kind |= block_kind_needs_lowering;
7314       ctx->program->needs_exact = true;
7315       break;
7316    }
7317    case nir_intrinsic_demote:
7318       bld.pseudo(aco_opcode::p_demote_to_helper, Operand(-1u));
7319
7320       if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
7321          ctx->cf_info.exec_potentially_empty_discard = true;
7322       ctx->block->kind |= block_kind_uses_demote;
7323       ctx->program->needs_exact = true;
7324       break;
7325    case nir_intrinsic_demote_if: {
7326       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7327       assert(src.regClass() == bld.lm);
7328       Temp cond = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
7329       bld.pseudo(aco_opcode::p_demote_to_helper, cond);
7330
7331       if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
7332          ctx->cf_info.exec_potentially_empty_discard = true;
7333       ctx->block->kind |= block_kind_uses_demote;
7334       ctx->program->needs_exact = true;
7335       break;
7336    }
7337    case nir_intrinsic_first_invocation: {
7338       emit_wqm(ctx, bld.sop1(Builder::s_ff1_i32, bld.def(s1), Operand(exec, bld.lm)),
7339                get_ssa_temp(ctx, &instr->dest.ssa));
7340       break;
7341    }
7342    case nir_intrinsic_shader_clock:
7343       bld.smem(aco_opcode::s_memtime, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), false);
7344       emit_split_vector(ctx, get_ssa_temp(ctx, &instr->dest.ssa), 2);
7345       break;
7346    case nir_intrinsic_load_vertex_id_zero_base: {
7347       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7348       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.vertex_id));
7349       break;
7350    }
7351    case nir_intrinsic_load_first_vertex: {
7352       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7353       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.base_vertex));
7354       break;
7355    }
7356    case nir_intrinsic_load_base_instance: {
7357       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7358       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.start_instance));
7359       break;
7360    }
7361    case nir_intrinsic_load_instance_id: {
7362       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7363       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.instance_id));
7364       break;
7365    }
7366    case nir_intrinsic_load_draw_id: {
7367       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7368       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.draw_id));
7369       break;
7370    }
7371    case nir_intrinsic_load_invocation_id: {
7372       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7373
7374       if (ctx->shader->info.stage == MESA_SHADER_GEOMETRY) {
7375          if (ctx->options->chip_class >= GFX10)
7376             bld.vop2_e64(aco_opcode::v_and_b32, Definition(dst), Operand(127u), get_arg(ctx, ctx->args->ac.gs_invocation_id));
7377          else
7378             bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.gs_invocation_id));
7379       } else if (ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) {
7380          bld.vop3(aco_opcode::v_bfe_u32, Definition(dst),
7381                   get_arg(ctx, ctx->args->ac.tcs_rel_ids), Operand(8u), Operand(5u));
7382       } else {
7383          unreachable("Unsupported stage for load_invocation_id");
7384       }
7385
7386       break;
7387    }
7388    case nir_intrinsic_load_primitive_id: {
7389       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7390
7391       switch (ctx->shader->info.stage) {
7392       case MESA_SHADER_GEOMETRY:
7393          bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.gs_prim_id));
7394          break;
7395       case MESA_SHADER_TESS_CTRL:
7396          bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.tcs_patch_id));
7397          break;
7398       case MESA_SHADER_TESS_EVAL:
7399          bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.tes_patch_id));
7400          break;
7401       default:
7402          unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
7403       }
7404
7405       break;
7406    }
7407    case nir_intrinsic_load_patch_vertices_in: {
7408       assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL ||
7409              ctx->shader->info.stage == MESA_SHADER_TESS_EVAL);
7410
7411       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7412       bld.copy(Definition(dst), Operand(ctx->args->options->key.tcs.input_vertices));
7413       break;
7414    }
7415    case nir_intrinsic_emit_vertex_with_counter: {
7416       visit_emit_vertex_with_counter(ctx, instr);
7417       break;
7418    }
7419    case nir_intrinsic_end_primitive_with_counter: {
7420       unsigned stream = nir_intrinsic_stream_id(instr);
7421       bld.sopp(aco_opcode::s_sendmsg, bld.m0(ctx->gs_wave_id), -1, sendmsg_gs(true, false, stream));
7422       break;
7423    }
7424    case nir_intrinsic_set_vertex_count: {
7425       /* unused, the HW keeps track of this for us */
7426       break;
7427    }
7428    default:
7429       fprintf(stderr, "Unimplemented intrinsic instr: ");
7430       nir_print_instr(&instr->instr, stderr);
7431       fprintf(stderr, "\n");
7432       abort();
7433
7434       break;
7435    }
7436 }
7437
7438
7439 void tex_fetch_ptrs(isel_context *ctx, nir_tex_instr *instr,
7440                     Temp *res_ptr, Temp *samp_ptr, Temp *fmask_ptr,
7441                     enum glsl_base_type *stype)
7442 {
7443    nir_deref_instr *texture_deref_instr = NULL;
7444    nir_deref_instr *sampler_deref_instr = NULL;
7445    int plane = -1;
7446
7447    for (unsigned i = 0; i < instr->num_srcs; i++) {
7448       switch (instr->src[i].src_type) {
7449       case nir_tex_src_texture_deref:
7450          texture_deref_instr = nir_src_as_deref(instr->src[i].src);
7451          break;
7452       case nir_tex_src_sampler_deref:
7453          sampler_deref_instr = nir_src_as_deref(instr->src[i].src);
7454          break;
7455       case nir_tex_src_plane:
7456          plane = nir_src_as_int(instr->src[i].src);
7457          break;
7458       default:
7459          break;
7460       }
7461    }
7462
7463    *stype = glsl_get_sampler_result_type(texture_deref_instr->type);
7464
7465    if (!sampler_deref_instr)
7466       sampler_deref_instr = texture_deref_instr;
7467
7468    if (plane >= 0) {
7469       assert(instr->op != nir_texop_txf_ms &&
7470              instr->op != nir_texop_samples_identical);
7471       assert(instr->sampler_dim  != GLSL_SAMPLER_DIM_BUF);
7472       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, (aco_descriptor_type)(ACO_DESC_PLANE_0 + plane), instr, false, false);
7473    } else if (instr->sampler_dim  == GLSL_SAMPLER_DIM_BUF) {
7474       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_BUFFER, instr, false, false);
7475    } else if (instr->op == nir_texop_fragment_mask_fetch) {
7476       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_FMASK, instr, false, false);
7477    } else {
7478       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_IMAGE, instr, false, false);
7479    }
7480    if (samp_ptr) {
7481       *samp_ptr = get_sampler_desc(ctx, sampler_deref_instr, ACO_DESC_SAMPLER, instr, false, false);
7482
7483       if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT && ctx->options->chip_class < GFX8) {
7484          /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
7485          Builder bld(ctx->program, ctx->block);
7486
7487          /* to avoid unnecessary moves, we split and recombine sampler and image */
7488          Temp img[8] = {bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1),
7489                         bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1)};
7490          Temp samp[4] = {bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1)};
7491          bld.pseudo(aco_opcode::p_split_vector, Definition(img[0]), Definition(img[1]),
7492                     Definition(img[2]), Definition(img[3]), Definition(img[4]),
7493                     Definition(img[5]), Definition(img[6]), Definition(img[7]), *res_ptr);
7494          bld.pseudo(aco_opcode::p_split_vector, Definition(samp[0]), Definition(samp[1]),
7495                     Definition(samp[2]), Definition(samp[3]), *samp_ptr);
7496
7497          samp[0] = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), samp[0], img[7]);
7498          *res_ptr = bld.pseudo(aco_opcode::p_create_vector, bld.def(s8),
7499                                img[0], img[1], img[2], img[3],
7500                                img[4], img[5], img[6], img[7]);
7501          *samp_ptr = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
7502                                 samp[0], samp[1], samp[2], samp[3]);
7503       }
7504    }
7505    if (fmask_ptr && (instr->op == nir_texop_txf_ms ||
7506                      instr->op == nir_texop_samples_identical))
7507       *fmask_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_FMASK, instr, false, false);
7508 }
7509
7510 void build_cube_select(isel_context *ctx, Temp ma, Temp id, Temp deriv,
7511                        Temp *out_ma, Temp *out_sc, Temp *out_tc)
7512 {
7513    Builder bld(ctx->program, ctx->block);
7514
7515    Temp deriv_x = emit_extract_vector(ctx, deriv, 0, v1);
7516    Temp deriv_y = emit_extract_vector(ctx, deriv, 1, v1);
7517    Temp deriv_z = emit_extract_vector(ctx, deriv, 2, v1);
7518
7519    Operand neg_one(0xbf800000u);
7520    Operand one(0x3f800000u);
7521    Operand two(0x40000000u);
7522    Operand four(0x40800000u);
7523
7524    Temp is_ma_positive = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), ma);
7525    Temp sgn_ma = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), neg_one, one, is_ma_positive);
7526    Temp neg_sgn_ma = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), Operand(0u), sgn_ma);
7527
7528    Temp is_ma_z = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), four, id);
7529    Temp is_ma_y = bld.vopc(aco_opcode::v_cmp_le_f32, bld.def(bld.lm), two, id);
7530    is_ma_y = bld.sop2(Builder::s_andn2, bld.hint_vcc(bld.def(bld.lm)), is_ma_y, is_ma_z);
7531    Temp is_not_ma_x = bld.sop2(aco_opcode::s_or_b64, bld.hint_vcc(bld.def(bld.lm)), bld.def(s1, scc), is_ma_z, is_ma_y);
7532
7533    // select sc
7534    Temp tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_z, deriv_x, is_not_ma_x);
7535    Temp sgn = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1),
7536                        bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), neg_sgn_ma, sgn_ma, is_ma_z),
7537                        one, is_ma_y);
7538    *out_sc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tmp, sgn);
7539
7540    // select tc
7541    tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_y, deriv_z, is_ma_y);
7542    sgn = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), neg_one, sgn_ma, is_ma_y);
7543    *out_tc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tmp, sgn);
7544
7545    // select ma
7546    tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
7547                   bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_x, deriv_y, is_ma_y),
7548                   deriv_z, is_ma_z);
7549    tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffffu), tmp);
7550    *out_ma = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), two, tmp);
7551 }
7552
7553 void prepare_cube_coords(isel_context *ctx, std::vector<Temp>& coords, Temp* ddx, Temp* ddy, bool is_deriv, bool is_array)
7554 {
7555    Builder bld(ctx->program, ctx->block);
7556    Temp ma, tc, sc, id;
7557
7558    if (is_array) {
7559       coords[3] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coords[3]);
7560
7561       // see comment in ac_prepare_cube_coords()
7562       if (ctx->options->chip_class <= GFX8)
7563          coords[3] = bld.vop2(aco_opcode::v_max_f32, bld.def(v1), Operand(0u), coords[3]);
7564    }
7565
7566    ma = bld.vop3(aco_opcode::v_cubema_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7567
7568    aco_ptr<VOP3A_instruction> vop3a{create_instruction<VOP3A_instruction>(aco_opcode::v_rcp_f32, asVOP3(Format::VOP1), 1, 1)};
7569    vop3a->operands[0] = Operand(ma);
7570    vop3a->abs[0] = true;
7571    Temp invma = bld.tmp(v1);
7572    vop3a->definitions[0] = Definition(invma);
7573    ctx->block->instructions.emplace_back(std::move(vop3a));
7574
7575    sc = bld.vop3(aco_opcode::v_cubesc_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7576    if (!is_deriv)
7577       sc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), sc, invma, Operand(0x3fc00000u/*1.5*/));
7578
7579    tc = bld.vop3(aco_opcode::v_cubetc_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7580    if (!is_deriv)
7581       tc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), tc, invma, Operand(0x3fc00000u/*1.5*/));
7582
7583    id = bld.vop3(aco_opcode::v_cubeid_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7584
7585    if (is_deriv) {
7586       sc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), sc, invma);
7587       tc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tc, invma);
7588
7589       for (unsigned i = 0; i < 2; i++) {
7590          // see comment in ac_prepare_cube_coords()
7591          Temp deriv_ma;
7592          Temp deriv_sc, deriv_tc;
7593          build_cube_select(ctx, ma, id, i ? *ddy : *ddx,
7594                            &deriv_ma, &deriv_sc, &deriv_tc);
7595
7596          deriv_ma = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, invma);
7597
7598          Temp x = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1),
7599                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_sc, invma),
7600                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, sc));
7601          Temp y = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1),
7602                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_tc, invma),
7603                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, tc));
7604          *(i ? ddy : ddx) = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), x, y);
7605       }
7606
7607       sc = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), Operand(0x3fc00000u/*1.5*/), sc);
7608       tc = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), Operand(0x3fc00000u/*1.5*/), tc);
7609    }
7610
7611    if (is_array)
7612       id = bld.vop2(aco_opcode::v_madmk_f32, bld.def(v1), coords[3], id, Operand(0x41000000u/*8.0*/));
7613    coords.resize(3);
7614    coords[0] = sc;
7615    coords[1] = tc;
7616    coords[2] = id;
7617 }
7618
7619 void get_const_vec(nir_ssa_def *vec, nir_const_value *cv[4])
7620 {
7621    if (vec->parent_instr->type != nir_instr_type_alu)
7622       return;
7623    nir_alu_instr *vec_instr = nir_instr_as_alu(vec->parent_instr);
7624    if (vec_instr->op != nir_op_vec(vec->num_components))
7625       return;
7626
7627    for (unsigned i = 0; i < vec->num_components; i++) {
7628       cv[i] = vec_instr->src[i].swizzle[0] == 0 ?
7629               nir_src_as_const_value(vec_instr->src[i].src) : NULL;
7630    }
7631 }
7632
7633 void visit_tex(isel_context *ctx, nir_tex_instr *instr)
7634 {
7635    Builder bld(ctx->program, ctx->block);
7636    bool has_bias = false, has_lod = false, level_zero = false, has_compare = false,
7637         has_offset = false, has_ddx = false, has_ddy = false, has_derivs = false, has_sample_index = false;
7638    Temp resource, sampler, fmask_ptr, bias = Temp(), compare = Temp(), sample_index = Temp(),
7639         lod = Temp(), offset = Temp(), ddx = Temp(), ddy = Temp();
7640    std::vector<Temp> coords;
7641    std::vector<Temp> derivs;
7642    nir_const_value *sample_index_cv = NULL;
7643    nir_const_value *const_offset[4] = {NULL, NULL, NULL, NULL};
7644    enum glsl_base_type stype;
7645    tex_fetch_ptrs(ctx, instr, &resource, &sampler, &fmask_ptr, &stype);
7646
7647    bool tg4_integer_workarounds = ctx->options->chip_class <= GFX8 && instr->op == nir_texop_tg4 &&
7648                                   (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT);
7649    bool tg4_integer_cube_workaround = tg4_integer_workarounds &&
7650                                       instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
7651
7652    for (unsigned i = 0; i < instr->num_srcs; i++) {
7653       switch (instr->src[i].src_type) {
7654       case nir_tex_src_coord: {
7655          Temp coord = get_ssa_temp(ctx, instr->src[i].src.ssa);
7656          for (unsigned i = 0; i < coord.size(); i++)
7657             coords.emplace_back(emit_extract_vector(ctx, coord, i, v1));
7658          break;
7659       }
7660       case nir_tex_src_bias:
7661          if (instr->op == nir_texop_txb) {
7662             bias = get_ssa_temp(ctx, instr->src[i].src.ssa);
7663             has_bias = true;
7664          }
7665          break;
7666       case nir_tex_src_lod: {
7667          nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
7668
7669          if (val && val->f32 <= 0.0) {
7670             level_zero = true;
7671          } else {
7672             lod = get_ssa_temp(ctx, instr->src[i].src.ssa);
7673             has_lod = true;
7674          }
7675          break;
7676       }
7677       case nir_tex_src_comparator:
7678          if (instr->is_shadow) {
7679             compare = get_ssa_temp(ctx, instr->src[i].src.ssa);
7680             has_compare = true;
7681          }
7682          break;
7683       case nir_tex_src_offset:
7684          offset = get_ssa_temp(ctx, instr->src[i].src.ssa);
7685          get_const_vec(instr->src[i].src.ssa, const_offset);
7686          has_offset = true;
7687          break;
7688       case nir_tex_src_ddx:
7689          ddx = get_ssa_temp(ctx, instr->src[i].src.ssa);
7690          has_ddx = true;
7691          break;
7692       case nir_tex_src_ddy:
7693          ddy = get_ssa_temp(ctx, instr->src[i].src.ssa);
7694          has_ddy = true;
7695          break;
7696       case nir_tex_src_ms_index:
7697          sample_index = get_ssa_temp(ctx, instr->src[i].src.ssa);
7698          sample_index_cv = nir_src_as_const_value(instr->src[i].src);
7699          has_sample_index = true;
7700          break;
7701       case nir_tex_src_texture_offset:
7702       case nir_tex_src_sampler_offset:
7703       default:
7704          break;
7705       }
7706    }
7707
7708    if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
7709       return get_buffer_size(ctx, resource, get_ssa_temp(ctx, &instr->dest.ssa), true);
7710
7711    if (instr->op == nir_texop_texture_samples) {
7712       Temp dword3 = emit_extract_vector(ctx, resource, 3, s1);
7713
7714       Temp samples_log2 = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), dword3, Operand(16u | 4u<<16));
7715       Temp samples = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), Operand(1u), samples_log2);
7716       Temp type = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), dword3, Operand(28u | 4u<<16 /* offset=28, width=4 */));
7717       Temp is_msaa = bld.sopc(aco_opcode::s_cmp_ge_u32, bld.def(s1, scc), type, Operand(14u));
7718
7719       bld.sop2(aco_opcode::s_cselect_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
7720                samples, Operand(1u), bld.scc(is_msaa));
7721       return;
7722    }
7723
7724    if (has_offset && instr->op != nir_texop_txf && instr->op != nir_texop_txf_ms) {
7725       aco_ptr<Instruction> tmp_instr;
7726       Temp acc, pack = Temp();
7727
7728       uint32_t pack_const = 0;
7729       for (unsigned i = 0; i < offset.size(); i++) {
7730          if (!const_offset[i])
7731             continue;
7732          pack_const |= (const_offset[i]->u32 & 0x3Fu) << (8u * i);
7733       }
7734
7735       if (offset.type() == RegType::sgpr) {
7736          for (unsigned i = 0; i < offset.size(); i++) {
7737             if (const_offset[i])
7738                continue;
7739
7740             acc = emit_extract_vector(ctx, offset, i, s1);
7741             acc = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), acc, Operand(0x3Fu));
7742
7743             if (i) {
7744                acc = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), acc, Operand(8u * i));
7745             }
7746
7747             if (pack == Temp()) {
7748                pack = acc;
7749             } else {
7750                pack = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), pack, acc);
7751             }
7752          }
7753
7754          if (pack_const && pack != Temp())
7755             pack = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(pack_const), pack);
7756       } else {
7757          for (unsigned i = 0; i < offset.size(); i++) {
7758             if (const_offset[i])
7759                continue;
7760
7761             acc = emit_extract_vector(ctx, offset, i, v1);
7762             acc = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x3Fu), acc);
7763
7764             if (i) {
7765                acc = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(8u * i), acc);
7766             }
7767
7768             if (pack == Temp()) {
7769                pack = acc;
7770             } else {
7771                pack = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), pack, acc);
7772             }
7773          }
7774
7775          if (pack_const && pack != Temp())
7776             pack = bld.sop2(aco_opcode::v_or_b32, bld.def(v1), Operand(pack_const), pack);
7777       }
7778       if (pack_const && pack == Temp())
7779          offset = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(pack_const));
7780       else if (pack == Temp())
7781          has_offset = false;
7782       else
7783          offset = pack;
7784    }
7785
7786    if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && instr->coord_components)
7787       prepare_cube_coords(ctx, coords, &ddx, &ddy, instr->op == nir_texop_txd, instr->is_array && instr->op != nir_texop_lod);
7788
7789    /* pack derivatives */
7790    if (has_ddx || has_ddy) {
7791       if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && ctx->options->chip_class == GFX9) {
7792          assert(has_ddx && has_ddy && ddx.size() == 1 && ddy.size() == 1);
7793          Temp zero = bld.copy(bld.def(v1), Operand(0u));
7794          derivs = {ddy, zero, ddy, zero};
7795       } else {
7796          for (unsigned i = 0; has_ddx && i < ddx.size(); i++)
7797             derivs.emplace_back(emit_extract_vector(ctx, ddx, i, v1));
7798          for (unsigned i = 0; has_ddy && i < ddy.size(); i++)
7799             derivs.emplace_back(emit_extract_vector(ctx, ddy, i, v1));
7800       }
7801       has_derivs = true;
7802    }
7803
7804    if (instr->coord_components > 1 &&
7805        instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
7806        instr->is_array &&
7807        instr->op != nir_texop_txf)
7808       coords[1] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coords[1]);
7809
7810    if (instr->coord_components > 2 &&
7811       (instr->sampler_dim == GLSL_SAMPLER_DIM_2D ||
7812        instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
7813        instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS ||
7814        instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
7815        instr->is_array &&
7816        instr->op != nir_texop_txf &&
7817        instr->op != nir_texop_txf_ms &&
7818        instr->op != nir_texop_fragment_fetch &&
7819        instr->op != nir_texop_fragment_mask_fetch)
7820       coords[2] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coords[2]);
7821
7822    if (ctx->options->chip_class == GFX9 &&
7823        instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
7824        instr->op != nir_texop_lod && instr->coord_components) {
7825       assert(coords.size() > 0 && coords.size() < 3);
7826
7827       coords.insert(std::next(coords.begin()), bld.copy(bld.def(v1), instr->op == nir_texop_txf ?
7828                                                                      Operand((uint32_t) 0) :
7829                                                                      Operand((uint32_t) 0x3f000000)));
7830    }
7831
7832    bool da = should_declare_array(ctx, instr->sampler_dim, instr->is_array);
7833
7834    if (instr->op == nir_texop_samples_identical)
7835       resource = fmask_ptr;
7836
7837    else if ((instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
7838              instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
7839             instr->op != nir_texop_txs &&
7840             instr->op != nir_texop_fragment_fetch &&
7841             instr->op != nir_texop_fragment_mask_fetch) {
7842       assert(has_sample_index);
7843       Operand op(sample_index);
7844       if (sample_index_cv)
7845          op = Operand(sample_index_cv->u32);
7846       sample_index = adjust_sample_index_using_fmask(ctx, da, coords, op, fmask_ptr);
7847    }
7848
7849    if (has_offset && (instr->op == nir_texop_txf || instr->op == nir_texop_txf_ms)) {
7850       for (unsigned i = 0; i < std::min(offset.size(), instr->coord_components); i++) {
7851          Temp off = emit_extract_vector(ctx, offset, i, v1);
7852          coords[i] = bld.vadd32(bld.def(v1), coords[i], off);
7853       }
7854       has_offset = false;
7855    }
7856
7857    /* Build tex instruction */
7858    unsigned dmask = nir_ssa_def_components_read(&instr->dest.ssa);
7859    unsigned dim = ctx->options->chip_class >= GFX10 && instr->sampler_dim != GLSL_SAMPLER_DIM_BUF
7860                   ? ac_get_sampler_dim(ctx->options->chip_class, instr->sampler_dim, instr->is_array)
7861                   : 0;
7862    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7863    Temp tmp_dst = dst;
7864
7865    /* gather4 selects the component by dmask and always returns vec4 */
7866    if (instr->op == nir_texop_tg4) {
7867       assert(instr->dest.ssa.num_components == 4);
7868       if (instr->is_shadow)
7869          dmask = 1;
7870       else
7871          dmask = 1 << instr->component;
7872       if (tg4_integer_cube_workaround || dst.type() == RegType::sgpr)
7873          tmp_dst = bld.tmp(v4);
7874    } else if (instr->op == nir_texop_samples_identical) {
7875       tmp_dst = bld.tmp(v1);
7876    } else if (util_bitcount(dmask) != instr->dest.ssa.num_components || dst.type() == RegType::sgpr) {
7877       tmp_dst = bld.tmp(RegClass(RegType::vgpr, util_bitcount(dmask)));
7878    }
7879
7880    aco_ptr<MIMG_instruction> tex;
7881    if (instr->op == nir_texop_txs || instr->op == nir_texop_query_levels) {
7882       if (!has_lod)
7883          lod = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
7884
7885       bool div_by_6 = instr->op == nir_texop_txs &&
7886                       instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
7887                       instr->is_array &&
7888                       (dmask & (1 << 2));
7889       if (tmp_dst.id() == dst.id() && div_by_6)
7890          tmp_dst = bld.tmp(tmp_dst.regClass());
7891
7892       tex.reset(create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 3, 1));
7893       tex->operands[0] = Operand(resource);
7894       tex->operands[1] = Operand(s4); /* no sampler */
7895       tex->operands[2] = Operand(as_vgpr(ctx,lod));
7896       if (ctx->options->chip_class == GFX9 &&
7897           instr->op == nir_texop_txs &&
7898           instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
7899           instr->is_array) {
7900          tex->dmask = (dmask & 0x1) | ((dmask & 0x2) << 1);
7901       } else if (instr->op == nir_texop_query_levels) {
7902          tex->dmask = 1 << 3;
7903       } else {
7904          tex->dmask = dmask;
7905       }
7906       tex->da = da;
7907       tex->definitions[0] = Definition(tmp_dst);
7908       tex->dim = dim;
7909       tex->can_reorder = true;
7910       ctx->block->instructions.emplace_back(std::move(tex));
7911
7912       if (div_by_6) {
7913          /* divide 3rd value by 6 by multiplying with magic number */
7914          emit_split_vector(ctx, tmp_dst, tmp_dst.size());
7915          Temp c = bld.copy(bld.def(s1), Operand((uint32_t) 0x2AAAAAAB));
7916          Temp by_6 = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), emit_extract_vector(ctx, tmp_dst, 2, v1), c);
7917          assert(instr->dest.ssa.num_components == 3);
7918          Temp tmp = dst.type() == RegType::vgpr ? dst : bld.tmp(v3);
7919          tmp_dst = bld.pseudo(aco_opcode::p_create_vector, Definition(tmp),
7920                               emit_extract_vector(ctx, tmp_dst, 0, v1),
7921                               emit_extract_vector(ctx, tmp_dst, 1, v1),
7922                               by_6);
7923
7924       }
7925
7926       expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, dmask);
7927       return;
7928    }
7929
7930    Temp tg4_compare_cube_wa64 = Temp();
7931
7932    if (tg4_integer_workarounds) {
7933       tex.reset(create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 3, 1));
7934       tex->operands[0] = Operand(resource);
7935       tex->operands[1] = Operand(s4); /* no sampler */
7936       tex->operands[2] = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
7937       tex->dim = dim;
7938       tex->dmask = 0x3;
7939       tex->da = da;
7940       Temp size = bld.tmp(v2);
7941       tex->definitions[0] = Definition(size);
7942       tex->can_reorder = true;
7943       ctx->block->instructions.emplace_back(std::move(tex));
7944       emit_split_vector(ctx, size, size.size());
7945
7946       Temp half_texel[2];
7947       for (unsigned i = 0; i < 2; i++) {
7948          half_texel[i] = emit_extract_vector(ctx, size, i, v1);
7949          half_texel[i] = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), half_texel[i]);
7950          half_texel[i] = bld.vop1(aco_opcode::v_rcp_iflag_f32, bld.def(v1), half_texel[i]);
7951          half_texel[i] = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0xbf000000/*-0.5*/), half_texel[i]);
7952       }
7953
7954       Temp new_coords[2] = {
7955          bld.vop2(aco_opcode::v_add_f32, bld.def(v1), coords[0], half_texel[0]),
7956          bld.vop2(aco_opcode::v_add_f32, bld.def(v1), coords[1], half_texel[1])
7957       };
7958
7959       if (tg4_integer_cube_workaround) {
7960          // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
7961          Temp desc[resource.size()];
7962          aco_ptr<Instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector,
7963                                                                            Format::PSEUDO, 1, resource.size())};
7964          split->operands[0] = Operand(resource);
7965          for (unsigned i = 0; i < resource.size(); i++) {
7966             desc[i] = bld.tmp(s1);
7967             split->definitions[i] = Definition(desc[i]);
7968          }
7969          ctx->block->instructions.emplace_back(std::move(split));
7970
7971          Temp dfmt = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), desc[1], Operand(20u | (6u << 16)));
7972          Temp compare_cube_wa = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), dfmt,
7973                                          Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8));
7974
7975          Temp nfmt;
7976          if (stype == GLSL_TYPE_UINT) {
7977             nfmt = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1),
7978                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED),
7979                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT),
7980                             bld.scc(compare_cube_wa));
7981          } else {
7982             nfmt = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1),
7983                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED),
7984                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT),
7985                             bld.scc(compare_cube_wa));
7986          }
7987          tg4_compare_cube_wa64 = bld.tmp(bld.lm);
7988          bool_to_vector_condition(ctx, compare_cube_wa, tg4_compare_cube_wa64);
7989
7990          nfmt = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), nfmt, Operand(26u));
7991
7992          desc[1] = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), desc[1],
7993                             Operand((uint32_t)C_008F14_NUM_FORMAT));
7994          desc[1] = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), desc[1], nfmt);
7995
7996          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector,
7997                                                                          Format::PSEUDO, resource.size(), 1)};
7998          for (unsigned i = 0; i < resource.size(); i++)
7999             vec->operands[i] = Operand(desc[i]);
8000          resource = bld.tmp(resource.regClass());
8001          vec->definitions[0] = Definition(resource);
8002          ctx->block->instructions.emplace_back(std::move(vec));
8003
8004          new_coords[0] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
8005                                   new_coords[0], coords[0], tg4_compare_cube_wa64);
8006          new_coords[1] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
8007                                   new_coords[1], coords[1], tg4_compare_cube_wa64);
8008       }
8009       coords[0] = new_coords[0];
8010       coords[1] = new_coords[1];
8011    }
8012
8013    if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
8014       //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8015
8016       assert(coords.size() == 1);
8017       unsigned last_bit = util_last_bit(nir_ssa_def_components_read(&instr->dest.ssa));
8018       aco_opcode op;
8019       switch (last_bit) {
8020       case 1:
8021          op = aco_opcode::buffer_load_format_x; break;
8022       case 2:
8023          op = aco_opcode::buffer_load_format_xy; break;
8024       case 3:
8025          op = aco_opcode::buffer_load_format_xyz; break;
8026       case 4:
8027          op = aco_opcode::buffer_load_format_xyzw; break;
8028       default:
8029          unreachable("Tex instruction loads more than 4 components.");
8030       }
8031
8032       /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8033       if (last_bit == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
8034          tmp_dst = dst;
8035       else
8036          tmp_dst = bld.tmp(RegType::vgpr, last_bit);
8037
8038       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
8039       mubuf->operands[0] = Operand(resource);
8040       mubuf->operands[1] = Operand(coords[0]);
8041       mubuf->operands[2] = Operand((uint32_t) 0);
8042       mubuf->definitions[0] = Definition(tmp_dst);
8043       mubuf->idxen = true;
8044       mubuf->can_reorder = true;
8045       ctx->block->instructions.emplace_back(std::move(mubuf));
8046
8047       expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, (1 << last_bit) - 1);
8048       return;
8049    }
8050
8051    /* gather MIMG address components */
8052    std::vector<Temp> args;
8053    if (has_offset)
8054       args.emplace_back(offset);
8055    if (has_bias)
8056       args.emplace_back(bias);
8057    if (has_compare)
8058       args.emplace_back(compare);
8059    if (has_derivs)
8060       args.insert(args.end(), derivs.begin(), derivs.end());
8061
8062    args.insert(args.end(), coords.begin(), coords.end());
8063    if (has_sample_index)
8064       args.emplace_back(sample_index);
8065    if (has_lod)
8066       args.emplace_back(lod);
8067
8068    Temp arg = bld.tmp(RegClass(RegType::vgpr, args.size()));
8069    aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, args.size(), 1)};
8070    vec->definitions[0] = Definition(arg);
8071    for (unsigned i = 0; i < args.size(); i++)
8072       vec->operands[i] = Operand(args[i]);
8073    ctx->block->instructions.emplace_back(std::move(vec));
8074
8075
8076    if (instr->op == nir_texop_txf ||
8077        instr->op == nir_texop_txf_ms ||
8078        instr->op == nir_texop_samples_identical ||
8079        instr->op == nir_texop_fragment_fetch ||
8080        instr->op == nir_texop_fragment_mask_fetch) {
8081       aco_opcode op = level_zero || instr->sampler_dim == GLSL_SAMPLER_DIM_MS || instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS ? aco_opcode::image_load : aco_opcode::image_load_mip;
8082       tex.reset(create_instruction<MIMG_instruction>(op, Format::MIMG, 3, 1));
8083       tex->operands[0] = Operand(resource);
8084       tex->operands[1] = Operand(s4); /* no sampler */
8085       tex->operands[2] = Operand(arg);
8086       tex->dim = dim;
8087       tex->dmask = dmask;
8088       tex->unrm = true;
8089       tex->da = da;
8090       tex->definitions[0] = Definition(tmp_dst);
8091       tex->can_reorder = true;
8092       ctx->block->instructions.emplace_back(std::move(tex));
8093
8094       if (instr->op == nir_texop_samples_identical) {
8095          assert(dmask == 1 && dst.regClass() == v1);
8096          assert(dst.id() != tmp_dst.id());
8097
8098          Temp tmp = bld.tmp(bld.lm);
8099          bld.vopc(aco_opcode::v_cmp_eq_u32, Definition(tmp), Operand(0u), tmp_dst).def(0).setHint(vcc);
8100          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand((uint32_t)-1), tmp);
8101
8102       } else {
8103          expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, dmask);
8104       }
8105       return;
8106    }
8107
8108    // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8109    aco_opcode opcode = aco_opcode::image_sample;
8110    if (has_offset) { /* image_sample_*_o */
8111       if (has_compare) {
8112          opcode = aco_opcode::image_sample_c_o;
8113          if (has_derivs)
8114             opcode = aco_opcode::image_sample_c_d_o;
8115          if (has_bias)
8116             opcode = aco_opcode::image_sample_c_b_o;
8117          if (level_zero)
8118             opcode = aco_opcode::image_sample_c_lz_o;
8119          if (has_lod)
8120             opcode = aco_opcode::image_sample_c_l_o;
8121       } else {
8122          opcode = aco_opcode::image_sample_o;
8123          if (has_derivs)
8124             opcode = aco_opcode::image_sample_d_o;
8125          if (has_bias)
8126             opcode = aco_opcode::image_sample_b_o;
8127          if (level_zero)
8128             opcode = aco_opcode::image_sample_lz_o;
8129          if (has_lod)
8130             opcode = aco_opcode::image_sample_l_o;
8131       }
8132    } else { /* no offset */
8133       if (has_compare) {
8134          opcode = aco_opcode::image_sample_c;
8135          if (has_derivs)
8136             opcode = aco_opcode::image_sample_c_d;
8137          if (has_bias)
8138             opcode = aco_opcode::image_sample_c_b;
8139          if (level_zero)
8140             opcode = aco_opcode::image_sample_c_lz;
8141          if (has_lod)
8142             opcode = aco_opcode::image_sample_c_l;
8143       } else {
8144          opcode = aco_opcode::image_sample;
8145          if (has_derivs)
8146             opcode = aco_opcode::image_sample_d;
8147          if (has_bias)
8148             opcode = aco_opcode::image_sample_b;
8149          if (level_zero)
8150             opcode = aco_opcode::image_sample_lz;
8151          if (has_lod)
8152             opcode = aco_opcode::image_sample_l;
8153       }
8154    }
8155
8156    if (instr->op == nir_texop_tg4) {
8157       if (has_offset) {
8158          opcode = aco_opcode::image_gather4_lz_o;
8159          if (has_compare)
8160             opcode = aco_opcode::image_gather4_c_lz_o;
8161       } else {
8162          opcode = aco_opcode::image_gather4_lz;
8163          if (has_compare)
8164             opcode = aco_opcode::image_gather4_c_lz;
8165       }
8166    } else if (instr->op == nir_texop_lod) {
8167       opcode = aco_opcode::image_get_lod;
8168    }
8169
8170    /* we don't need the bias, sample index, compare value or offset to be
8171     * computed in WQM but if the p_create_vector copies the coordinates, then it
8172     * needs to be in WQM */
8173    if (ctx->stage == fragment_fs &&
8174        !has_derivs && !has_lod && !level_zero &&
8175        instr->sampler_dim != GLSL_SAMPLER_DIM_MS &&
8176        instr->sampler_dim != GLSL_SAMPLER_DIM_SUBPASS_MS)
8177       arg = emit_wqm(ctx, arg, bld.tmp(arg.regClass()), true);
8178
8179    tex.reset(create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 1));
8180    tex->operands[0] = Operand(resource);
8181    tex->operands[1] = Operand(sampler);
8182    tex->operands[2] = Operand(arg);
8183    tex->dim = dim;
8184    tex->dmask = dmask;
8185    tex->da = da;
8186    tex->definitions[0] = Definition(tmp_dst);
8187    tex->can_reorder = true;
8188    ctx->block->instructions.emplace_back(std::move(tex));
8189
8190    if (tg4_integer_cube_workaround) {
8191       assert(tmp_dst.id() != dst.id());
8192       assert(tmp_dst.size() == dst.size() && dst.size() == 4);
8193
8194       emit_split_vector(ctx, tmp_dst, tmp_dst.size());
8195       Temp val[4];
8196       for (unsigned i = 0; i < dst.size(); i++) {
8197          val[i] = emit_extract_vector(ctx, tmp_dst, i, v1);
8198          Temp cvt_val;
8199          if (stype == GLSL_TYPE_UINT)
8200             cvt_val = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), val[i]);
8201          else
8202             cvt_val = bld.vop1(aco_opcode::v_cvt_i32_f32, bld.def(v1), val[i]);
8203          val[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), val[i], cvt_val, tg4_compare_cube_wa64);
8204       }
8205       Temp tmp = dst.regClass() == v4 ? dst : bld.tmp(v4);
8206       tmp_dst = bld.pseudo(aco_opcode::p_create_vector, Definition(tmp),
8207                            val[0], val[1], val[2], val[3]);
8208    }
8209    unsigned mask = instr->op == nir_texop_tg4 ? 0xF : dmask;
8210    expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, mask);
8211
8212 }
8213
8214
8215 Operand get_phi_operand(isel_context *ctx, nir_ssa_def *ssa)
8216 {
8217    Temp tmp = get_ssa_temp(ctx, ssa);
8218    if (ssa->parent_instr->type == nir_instr_type_ssa_undef)
8219       return Operand(tmp.regClass());
8220    else
8221       return Operand(tmp);
8222 }
8223
8224 void visit_phi(isel_context *ctx, nir_phi_instr *instr)
8225 {
8226    aco_ptr<Pseudo_instruction> phi;
8227    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
8228    assert(instr->dest.ssa.bit_size != 1 || dst.regClass() == ctx->program->lane_mask);
8229
8230    bool logical = !dst.is_linear() || ctx->divergent_vals[instr->dest.ssa.index];
8231    logical |= ctx->block->kind & block_kind_merge;
8232    aco_opcode opcode = logical ? aco_opcode::p_phi : aco_opcode::p_linear_phi;
8233
8234    /* we want a sorted list of sources, since the predecessor list is also sorted */
8235    std::map<unsigned, nir_ssa_def*> phi_src;
8236    nir_foreach_phi_src(src, instr)
8237       phi_src[src->pred->index] = src->src.ssa;
8238
8239    std::vector<unsigned>& preds = logical ? ctx->block->logical_preds : ctx->block->linear_preds;
8240    unsigned num_operands = 0;
8241    Operand operands[std::max(exec_list_length(&instr->srcs), (unsigned)preds.size()) + 1];
8242    unsigned num_defined = 0;
8243    unsigned cur_pred_idx = 0;
8244    for (std::pair<unsigned, nir_ssa_def *> src : phi_src) {
8245       if (cur_pred_idx < preds.size()) {
8246          /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8247          unsigned block = ctx->cf_info.nir_to_aco[src.first];
8248          unsigned skipped = 0;
8249          while (cur_pred_idx + skipped < preds.size() && preds[cur_pred_idx + skipped] != block)
8250             skipped++;
8251          if (cur_pred_idx + skipped < preds.size()) {
8252             for (unsigned i = 0; i < skipped; i++)
8253                operands[num_operands++] = Operand(dst.regClass());
8254             cur_pred_idx += skipped;
8255          } else {
8256             continue;
8257          }
8258       }
8259       /* Handle missing predecessors at the end. This shouldn't happen with loop
8260        * headers and we can't ignore these sources for loop header phis. */
8261       if (!(ctx->block->kind & block_kind_loop_header) && cur_pred_idx >= preds.size())
8262          continue;
8263       cur_pred_idx++;
8264       Operand op = get_phi_operand(ctx, src.second);
8265       operands[num_operands++] = op;
8266       num_defined += !op.isUndefined();
8267    }
8268    /* handle block_kind_continue_or_break at loop exit blocks */
8269    while (cur_pred_idx++ < preds.size())
8270       operands[num_operands++] = Operand(dst.regClass());
8271
8272    /* If the loop ends with a break, still add a linear continue edge in case
8273     * that break is divergent or continue_or_break is used. We'll either remove
8274     * this operand later in visit_loop() if it's not necessary or replace the
8275     * undef with something correct. */
8276    if (!logical && ctx->block->kind & block_kind_loop_header) {
8277       nir_loop *loop = nir_cf_node_as_loop(instr->instr.block->cf_node.parent);
8278       nir_block *last = nir_loop_last_block(loop);
8279       if (last->successors[0] != instr->instr.block)
8280          operands[num_operands++] = Operand(RegClass());
8281    }
8282
8283    if (num_defined == 0) {
8284       Builder bld(ctx->program, ctx->block);
8285       if (dst.regClass() == s1) {
8286          bld.sop1(aco_opcode::s_mov_b32, Definition(dst), Operand(0u));
8287       } else if (dst.regClass() == v1) {
8288          bld.vop1(aco_opcode::v_mov_b32, Definition(dst), Operand(0u));
8289       } else {
8290          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
8291          for (unsigned i = 0; i < dst.size(); i++)
8292             vec->operands[i] = Operand(0u);
8293          vec->definitions[0] = Definition(dst);
8294          ctx->block->instructions.emplace_back(std::move(vec));
8295       }
8296       return;
8297    }
8298
8299    /* we can use a linear phi in some cases if one src is undef */
8300    if (dst.is_linear() && ctx->block->kind & block_kind_merge && num_defined == 1) {
8301       phi.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_linear_phi, Format::PSEUDO, num_operands, 1));
8302
8303       Block *linear_else = &ctx->program->blocks[ctx->block->linear_preds[1]];
8304       Block *invert = &ctx->program->blocks[linear_else->linear_preds[0]];
8305       assert(invert->kind & block_kind_invert);
8306
8307       unsigned then_block = invert->linear_preds[0];
8308
8309       Block* insert_block = NULL;
8310       for (unsigned i = 0; i < num_operands; i++) {
8311          Operand op = operands[i];
8312          if (op.isUndefined())
8313             continue;
8314          insert_block = ctx->block->logical_preds[i] == then_block ? invert : ctx->block;
8315          phi->operands[0] = op;
8316          break;
8317       }
8318       assert(insert_block); /* should be handled by the "num_defined == 0" case above */
8319       phi->operands[1] = Operand(dst.regClass());
8320       phi->definitions[0] = Definition(dst);
8321       insert_block->instructions.emplace(insert_block->instructions.begin(), std::move(phi));
8322       return;
8323    }
8324
8325    /* try to scalarize vector phis */
8326    if (instr->dest.ssa.bit_size != 1 && dst.size() > 1) {
8327       // TODO: scalarize linear phis on divergent ifs
8328       bool can_scalarize = (opcode == aco_opcode::p_phi || !(ctx->block->kind & block_kind_merge));
8329       std::array<Temp, NIR_MAX_VEC_COMPONENTS> new_vec;
8330       for (unsigned i = 0; can_scalarize && (i < num_operands); i++) {
8331          Operand src = operands[i];
8332          if (src.isTemp() && ctx->allocated_vec.find(src.tempId()) == ctx->allocated_vec.end())
8333             can_scalarize = false;
8334       }
8335       if (can_scalarize) {
8336          unsigned num_components = instr->dest.ssa.num_components;
8337          assert(dst.size() % num_components == 0);
8338          RegClass rc = RegClass(dst.type(), dst.size() / num_components);
8339
8340          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1)};
8341          for (unsigned k = 0; k < num_components; k++) {
8342             phi.reset(create_instruction<Pseudo_instruction>(opcode, Format::PSEUDO, num_operands, 1));
8343             for (unsigned i = 0; i < num_operands; i++) {
8344                Operand src = operands[i];
8345                phi->operands[i] = src.isTemp() ? Operand(ctx->allocated_vec[src.tempId()][k]) : Operand(rc);
8346             }
8347             Temp phi_dst = {ctx->program->allocateId(), rc};
8348             phi->definitions[0] = Definition(phi_dst);
8349             ctx->block->instructions.emplace(ctx->block->instructions.begin(), std::move(phi));
8350             new_vec[k] = phi_dst;
8351             vec->operands[k] = Operand(phi_dst);
8352          }
8353          vec->definitions[0] = Definition(dst);
8354          ctx->block->instructions.emplace_back(std::move(vec));
8355          ctx->allocated_vec.emplace(dst.id(), new_vec);
8356          return;
8357       }
8358    }
8359
8360    phi.reset(create_instruction<Pseudo_instruction>(opcode, Format::PSEUDO, num_operands, 1));
8361    for (unsigned i = 0; i < num_operands; i++)
8362       phi->operands[i] = operands[i];
8363    phi->definitions[0] = Definition(dst);
8364    ctx->block->instructions.emplace(ctx->block->instructions.begin(), std::move(phi));
8365 }
8366
8367
8368 void visit_undef(isel_context *ctx, nir_ssa_undef_instr *instr)
8369 {
8370    Temp dst = get_ssa_temp(ctx, &instr->def);
8371
8372    assert(dst.type() == RegType::sgpr);
8373
8374    if (dst.size() == 1) {
8375       Builder(ctx->program, ctx->block).copy(Definition(dst), Operand(0u));
8376    } else {
8377       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
8378       for (unsigned i = 0; i < dst.size(); i++)
8379          vec->operands[i] = Operand(0u);
8380       vec->definitions[0] = Definition(dst);
8381       ctx->block->instructions.emplace_back(std::move(vec));
8382    }
8383 }
8384
8385 void visit_jump(isel_context *ctx, nir_jump_instr *instr)
8386 {
8387    Builder bld(ctx->program, ctx->block);
8388    Block *logical_target;
8389    append_logical_end(ctx->block);
8390    unsigned idx = ctx->block->index;
8391
8392    switch (instr->type) {
8393    case nir_jump_break:
8394       logical_target = ctx->cf_info.parent_loop.exit;
8395       add_logical_edge(idx, logical_target);
8396       ctx->block->kind |= block_kind_break;
8397
8398       if (!ctx->cf_info.parent_if.is_divergent &&
8399           !ctx->cf_info.parent_loop.has_divergent_continue) {
8400          /* uniform break - directly jump out of the loop */
8401          ctx->block->kind |= block_kind_uniform;
8402          ctx->cf_info.has_branch = true;
8403          bld.branch(aco_opcode::p_branch);
8404          add_linear_edge(idx, logical_target);
8405          return;
8406       }
8407       ctx->cf_info.parent_loop.has_divergent_branch = true;
8408       ctx->cf_info.nir_to_aco[instr->instr.block->index] = ctx->block->index;
8409       break;
8410    case nir_jump_continue:
8411       logical_target = &ctx->program->blocks[ctx->cf_info.parent_loop.header_idx];
8412       add_logical_edge(idx, logical_target);
8413       ctx->block->kind |= block_kind_continue;
8414
8415       if (ctx->cf_info.parent_if.is_divergent) {
8416          /* for potential uniform breaks after this continue,
8417             we must ensure that they are handled correctly */
8418          ctx->cf_info.parent_loop.has_divergent_continue = true;
8419          ctx->cf_info.parent_loop.has_divergent_branch = true;
8420          ctx->cf_info.nir_to_aco[instr->instr.block->index] = ctx->block->index;
8421       } else {
8422          /* uniform continue - directly jump to the loop header */
8423          ctx->block->kind |= block_kind_uniform;
8424          ctx->cf_info.has_branch = true;
8425          bld.branch(aco_opcode::p_branch);
8426          add_linear_edge(idx, logical_target);
8427          return;
8428       }
8429       break;
8430    default:
8431       fprintf(stderr, "Unknown NIR jump instr: ");
8432       nir_print_instr(&instr->instr, stderr);
8433       fprintf(stderr, "\n");
8434       abort();
8435    }
8436
8437    if (ctx->cf_info.parent_if.is_divergent && !ctx->cf_info.exec_potentially_empty_break) {
8438       ctx->cf_info.exec_potentially_empty_break = true;
8439       ctx->cf_info.exec_potentially_empty_break_depth = ctx->cf_info.loop_nest_depth;
8440    }
8441
8442    /* remove critical edges from linear CFG */
8443    bld.branch(aco_opcode::p_branch);
8444    Block* break_block = ctx->program->create_and_insert_block();
8445    break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8446    break_block->kind |= block_kind_uniform;
8447    add_linear_edge(idx, break_block);
8448    /* the loop_header pointer might be invalidated by this point */
8449    if (instr->type == nir_jump_continue)
8450       logical_target = &ctx->program->blocks[ctx->cf_info.parent_loop.header_idx];
8451    add_linear_edge(break_block->index, logical_target);
8452    bld.reset(break_block);
8453    bld.branch(aco_opcode::p_branch);
8454
8455    Block* continue_block = ctx->program->create_and_insert_block();
8456    continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8457    add_linear_edge(idx, continue_block);
8458    append_logical_start(continue_block);
8459    ctx->block = continue_block;
8460    return;
8461 }
8462
8463 void visit_block(isel_context *ctx, nir_block *block)
8464 {
8465    nir_foreach_instr(instr, block) {
8466       switch (instr->type) {
8467       case nir_instr_type_alu:
8468          visit_alu_instr(ctx, nir_instr_as_alu(instr));
8469          break;
8470       case nir_instr_type_load_const:
8471          visit_load_const(ctx, nir_instr_as_load_const(instr));
8472          break;
8473       case nir_instr_type_intrinsic:
8474          visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
8475          break;
8476       case nir_instr_type_tex:
8477          visit_tex(ctx, nir_instr_as_tex(instr));
8478          break;
8479       case nir_instr_type_phi:
8480          visit_phi(ctx, nir_instr_as_phi(instr));
8481          break;
8482       case nir_instr_type_ssa_undef:
8483          visit_undef(ctx, nir_instr_as_ssa_undef(instr));
8484          break;
8485       case nir_instr_type_deref:
8486          break;
8487       case nir_instr_type_jump:
8488          visit_jump(ctx, nir_instr_as_jump(instr));
8489          break;
8490       default:
8491          fprintf(stderr, "Unknown NIR instr type: ");
8492          nir_print_instr(instr, stderr);
8493          fprintf(stderr, "\n");
8494          //abort();
8495       }
8496    }
8497
8498    if (!ctx->cf_info.parent_loop.has_divergent_branch)
8499       ctx->cf_info.nir_to_aco[block->index] = ctx->block->index;
8500 }
8501
8502
8503
8504 static Operand create_continue_phis(isel_context *ctx, unsigned first, unsigned last,
8505                                     aco_ptr<Instruction>& header_phi, Operand *vals)
8506 {
8507    vals[0] = Operand(header_phi->definitions[0].getTemp());
8508    RegClass rc = vals[0].regClass();
8509
8510    unsigned loop_nest_depth = ctx->program->blocks[first].loop_nest_depth;
8511
8512    unsigned next_pred = 1;
8513
8514    for (unsigned idx = first + 1; idx <= last; idx++) {
8515       Block& block = ctx->program->blocks[idx];
8516       if (block.loop_nest_depth != loop_nest_depth) {
8517          vals[idx - first] = vals[idx - 1 - first];
8518          continue;
8519       }
8520
8521       if (block.kind & block_kind_continue) {
8522          vals[idx - first] = header_phi->operands[next_pred];
8523          next_pred++;
8524          continue;
8525       }
8526
8527       bool all_same = true;
8528       for (unsigned i = 1; all_same && (i < block.linear_preds.size()); i++)
8529          all_same = vals[block.linear_preds[i] - first] == vals[block.linear_preds[0] - first];
8530
8531       Operand val;
8532       if (all_same) {
8533          val = vals[block.linear_preds[0] - first];
8534       } else {
8535          aco_ptr<Instruction> phi(create_instruction<Pseudo_instruction>(
8536             aco_opcode::p_linear_phi, Format::PSEUDO, block.linear_preds.size(), 1));
8537          for (unsigned i = 0; i < block.linear_preds.size(); i++)
8538             phi->operands[i] = vals[block.linear_preds[i] - first];
8539          val = Operand(Temp(ctx->program->allocateId(), rc));
8540          phi->definitions[0] = Definition(val.getTemp());
8541          block.instructions.emplace(block.instructions.begin(), std::move(phi));
8542       }
8543       vals[idx - first] = val;
8544    }
8545
8546    return vals[last - first];
8547 }
8548
8549 static void visit_loop(isel_context *ctx, nir_loop *loop)
8550 {
8551    //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
8552    append_logical_end(ctx->block);
8553    ctx->block->kind |= block_kind_loop_preheader | block_kind_uniform;
8554    Builder bld(ctx->program, ctx->block);
8555    bld.branch(aco_opcode::p_branch);
8556    unsigned loop_preheader_idx = ctx->block->index;
8557
8558    Block loop_exit = Block();
8559    loop_exit.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8560    loop_exit.kind |= (block_kind_loop_exit | (ctx->block->kind & block_kind_top_level));
8561
8562    Block* loop_header = ctx->program->create_and_insert_block();
8563    loop_header->loop_nest_depth = ctx->cf_info.loop_nest_depth + 1;
8564    loop_header->kind |= block_kind_loop_header;
8565    add_edge(loop_preheader_idx, loop_header);
8566    ctx->block = loop_header;
8567
8568    /* emit loop body */
8569    unsigned loop_header_idx = loop_header->index;
8570    loop_info_RAII loop_raii(ctx, loop_header_idx, &loop_exit);
8571    append_logical_start(ctx->block);
8572    bool unreachable = visit_cf_list(ctx, &loop->body);
8573
8574    //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
8575    if (!ctx->cf_info.has_branch) {
8576       append_logical_end(ctx->block);
8577       if (ctx->cf_info.exec_potentially_empty_discard || ctx->cf_info.exec_potentially_empty_break) {
8578          /* Discards can result in code running with an empty exec mask.
8579           * This would result in divergent breaks not ever being taken. As a
8580           * workaround, break the loop when the loop mask is empty instead of
8581           * always continuing. */
8582          ctx->block->kind |= (block_kind_continue_or_break | block_kind_uniform);
8583          unsigned block_idx = ctx->block->index;
8584
8585          /* create helper blocks to avoid critical edges */
8586          Block *break_block = ctx->program->create_and_insert_block();
8587          break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8588          break_block->kind = block_kind_uniform;
8589          bld.reset(break_block);
8590          bld.branch(aco_opcode::p_branch);
8591          add_linear_edge(block_idx, break_block);
8592          add_linear_edge(break_block->index, &loop_exit);
8593
8594          Block *continue_block = ctx->program->create_and_insert_block();
8595          continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8596          continue_block->kind = block_kind_uniform;
8597          bld.reset(continue_block);
8598          bld.branch(aco_opcode::p_branch);
8599          add_linear_edge(block_idx, continue_block);
8600          add_linear_edge(continue_block->index, &ctx->program->blocks[loop_header_idx]);
8601
8602          if (!ctx->cf_info.parent_loop.has_divergent_branch)
8603             add_logical_edge(block_idx, &ctx->program->blocks[loop_header_idx]);
8604          ctx->block = &ctx->program->blocks[block_idx];
8605       } else {
8606          ctx->block->kind |= (block_kind_continue | block_kind_uniform);
8607          if (!ctx->cf_info.parent_loop.has_divergent_branch)
8608             add_edge(ctx->block->index, &ctx->program->blocks[loop_header_idx]);
8609          else
8610             add_linear_edge(ctx->block->index, &ctx->program->blocks[loop_header_idx]);
8611       }
8612
8613       bld.reset(ctx->block);
8614       bld.branch(aco_opcode::p_branch);
8615    }
8616
8617    /* Fixup phis in loop header from unreachable blocks.
8618     * has_branch/has_divergent_branch also indicates if the loop ends with a
8619     * break/continue instruction, but we don't emit those if unreachable=true */
8620    if (unreachable) {
8621       assert(ctx->cf_info.has_branch || ctx->cf_info.parent_loop.has_divergent_branch);
8622       bool linear = ctx->cf_info.has_branch;
8623       bool logical = ctx->cf_info.has_branch || ctx->cf_info.parent_loop.has_divergent_branch;
8624       for (aco_ptr<Instruction>& instr : ctx->program->blocks[loop_header_idx].instructions) {
8625          if ((logical && instr->opcode == aco_opcode::p_phi) ||
8626              (linear && instr->opcode == aco_opcode::p_linear_phi)) {
8627             /* the last operand should be the one that needs to be removed */
8628             instr->operands.pop_back();
8629          } else if (!is_phi(instr)) {
8630             break;
8631          }
8632       }
8633    }
8634
8635    /* Fixup linear phis in loop header from expecting a continue. Both this fixup
8636     * and the previous one shouldn't both happen at once because a break in the
8637     * merge block would get CSE'd */
8638    if (nir_loop_last_block(loop)->successors[0] != nir_loop_first_block(loop)) {
8639       unsigned num_vals = ctx->cf_info.has_branch ? 1 : (ctx->block->index - loop_header_idx + 1);
8640       Operand vals[num_vals];
8641       for (aco_ptr<Instruction>& instr : ctx->program->blocks[loop_header_idx].instructions) {
8642          if (instr->opcode == aco_opcode::p_linear_phi) {
8643             if (ctx->cf_info.has_branch)
8644                instr->operands.pop_back();
8645             else
8646                instr->operands.back() = create_continue_phis(ctx, loop_header_idx, ctx->block->index, instr, vals);
8647          } else if (!is_phi(instr)) {
8648             break;
8649          }
8650       }
8651    }
8652
8653    ctx->cf_info.has_branch = false;
8654
8655    // TODO: if the loop has not a single exit, we must add one °°
8656    /* emit loop successor block */
8657    ctx->block = ctx->program->insert_block(std::move(loop_exit));
8658    append_logical_start(ctx->block);
8659
8660    #if 0
8661    // TODO: check if it is beneficial to not branch on continues
8662    /* trim linear phis in loop header */
8663    for (auto&& instr : loop_entry->instructions) {
8664       if (instr->opcode == aco_opcode::p_linear_phi) {
8665          aco_ptr<Pseudo_instruction> new_phi{create_instruction<Pseudo_instruction>(aco_opcode::p_linear_phi, Format::PSEUDO, loop_entry->linear_predecessors.size(), 1)};
8666          new_phi->definitions[0] = instr->definitions[0];
8667          for (unsigned i = 0; i < new_phi->operands.size(); i++)
8668             new_phi->operands[i] = instr->operands[i];
8669          /* check that the remaining operands are all the same */
8670          for (unsigned i = new_phi->operands.size(); i < instr->operands.size(); i++)
8671             assert(instr->operands[i].tempId() == instr->operands.back().tempId());
8672          instr.swap(new_phi);
8673       } else if (instr->opcode == aco_opcode::p_phi) {
8674          continue;
8675       } else {
8676          break;
8677       }
8678    }
8679    #endif
8680 }
8681
8682 static void begin_divergent_if_then(isel_context *ctx, if_context *ic, Temp cond)
8683 {
8684    ic->cond = cond;
8685
8686    append_logical_end(ctx->block);
8687    ctx->block->kind |= block_kind_branch;
8688
8689    /* branch to linear then block */
8690    assert(cond.regClass() == ctx->program->lane_mask);
8691    aco_ptr<Pseudo_branch_instruction> branch;
8692    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_z, Format::PSEUDO_BRANCH, 1, 0));
8693    branch->operands[0] = Operand(cond);
8694    ctx->block->instructions.push_back(std::move(branch));
8695
8696    ic->BB_if_idx = ctx->block->index;
8697    ic->BB_invert = Block();
8698    ic->BB_invert.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8699    /* Invert blocks are intentionally not marked as top level because they
8700     * are not part of the logical cfg. */
8701    ic->BB_invert.kind |= block_kind_invert;
8702    ic->BB_endif = Block();
8703    ic->BB_endif.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8704    ic->BB_endif.kind |= (block_kind_merge | (ctx->block->kind & block_kind_top_level));
8705
8706    ic->exec_potentially_empty_discard_old = ctx->cf_info.exec_potentially_empty_discard;
8707    ic->exec_potentially_empty_break_old = ctx->cf_info.exec_potentially_empty_break;
8708    ic->exec_potentially_empty_break_depth_old = ctx->cf_info.exec_potentially_empty_break_depth;
8709    ic->divergent_old = ctx->cf_info.parent_if.is_divergent;
8710    ctx->cf_info.parent_if.is_divergent = true;
8711
8712    /* divergent branches use cbranch_execz */
8713    ctx->cf_info.exec_potentially_empty_discard = false;
8714    ctx->cf_info.exec_potentially_empty_break = false;
8715    ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8716
8717    /** emit logical then block */
8718    Block* BB_then_logical = ctx->program->create_and_insert_block();
8719    BB_then_logical->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8720    add_edge(ic->BB_if_idx, BB_then_logical);
8721    ctx->block = BB_then_logical;
8722    append_logical_start(BB_then_logical);
8723 }
8724
8725 static void begin_divergent_if_else(isel_context *ctx, if_context *ic)
8726 {
8727    Block *BB_then_logical = ctx->block;
8728    append_logical_end(BB_then_logical);
8729     /* branch from logical then block to invert block */
8730    aco_ptr<Pseudo_branch_instruction> branch;
8731    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8732    BB_then_logical->instructions.emplace_back(std::move(branch));
8733    add_linear_edge(BB_then_logical->index, &ic->BB_invert);
8734    if (!ctx->cf_info.parent_loop.has_divergent_branch)
8735       add_logical_edge(BB_then_logical->index, &ic->BB_endif);
8736    BB_then_logical->kind |= block_kind_uniform;
8737    assert(!ctx->cf_info.has_branch);
8738    ic->then_branch_divergent = ctx->cf_info.parent_loop.has_divergent_branch;
8739    ctx->cf_info.parent_loop.has_divergent_branch = false;
8740
8741    /** emit linear then block */
8742    Block* BB_then_linear = ctx->program->create_and_insert_block();
8743    BB_then_linear->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8744    BB_then_linear->kind |= block_kind_uniform;
8745    add_linear_edge(ic->BB_if_idx, BB_then_linear);
8746    /* branch from linear then block to invert block */
8747    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8748    BB_then_linear->instructions.emplace_back(std::move(branch));
8749    add_linear_edge(BB_then_linear->index, &ic->BB_invert);
8750
8751    /** emit invert merge block */
8752    ctx->block = ctx->program->insert_block(std::move(ic->BB_invert));
8753    ic->invert_idx = ctx->block->index;
8754
8755    /* branch to linear else block (skip else) */
8756    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_nz, Format::PSEUDO_BRANCH, 1, 0));
8757    branch->operands[0] = Operand(ic->cond);
8758    ctx->block->instructions.push_back(std::move(branch));
8759
8760    ic->exec_potentially_empty_discard_old |= ctx->cf_info.exec_potentially_empty_discard;
8761    ic->exec_potentially_empty_break_old |= ctx->cf_info.exec_potentially_empty_break;
8762    ic->exec_potentially_empty_break_depth_old =
8763       std::min(ic->exec_potentially_empty_break_depth_old, ctx->cf_info.exec_potentially_empty_break_depth);
8764    /* divergent branches use cbranch_execz */
8765    ctx->cf_info.exec_potentially_empty_discard = false;
8766    ctx->cf_info.exec_potentially_empty_break = false;
8767    ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8768
8769    /** emit logical else block */
8770    Block* BB_else_logical = ctx->program->create_and_insert_block();
8771    BB_else_logical->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8772    add_logical_edge(ic->BB_if_idx, BB_else_logical);
8773    add_linear_edge(ic->invert_idx, BB_else_logical);
8774    ctx->block = BB_else_logical;
8775    append_logical_start(BB_else_logical);
8776 }
8777
8778 static void end_divergent_if(isel_context *ctx, if_context *ic)
8779 {
8780    Block *BB_else_logical = ctx->block;
8781    append_logical_end(BB_else_logical);
8782
8783    /* branch from logical else block to endif block */
8784    aco_ptr<Pseudo_branch_instruction> branch;
8785    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8786    BB_else_logical->instructions.emplace_back(std::move(branch));
8787    add_linear_edge(BB_else_logical->index, &ic->BB_endif);
8788    if (!ctx->cf_info.parent_loop.has_divergent_branch)
8789       add_logical_edge(BB_else_logical->index, &ic->BB_endif);
8790    BB_else_logical->kind |= block_kind_uniform;
8791
8792    assert(!ctx->cf_info.has_branch);
8793    ctx->cf_info.parent_loop.has_divergent_branch &= ic->then_branch_divergent;
8794
8795
8796    /** emit linear else block */
8797    Block* BB_else_linear = ctx->program->create_and_insert_block();
8798    BB_else_linear->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8799    BB_else_linear->kind |= block_kind_uniform;
8800    add_linear_edge(ic->invert_idx, BB_else_linear);
8801
8802    /* branch from linear else block to endif block */
8803    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8804    BB_else_linear->instructions.emplace_back(std::move(branch));
8805    add_linear_edge(BB_else_linear->index, &ic->BB_endif);
8806
8807
8808    /** emit endif merge block */
8809    ctx->block = ctx->program->insert_block(std::move(ic->BB_endif));
8810    append_logical_start(ctx->block);
8811
8812
8813    ctx->cf_info.parent_if.is_divergent = ic->divergent_old;
8814    ctx->cf_info.exec_potentially_empty_discard |= ic->exec_potentially_empty_discard_old;
8815    ctx->cf_info.exec_potentially_empty_break |= ic->exec_potentially_empty_break_old;
8816    ctx->cf_info.exec_potentially_empty_break_depth =
8817       std::min(ic->exec_potentially_empty_break_depth_old, ctx->cf_info.exec_potentially_empty_break_depth);
8818    if (ctx->cf_info.loop_nest_depth == ctx->cf_info.exec_potentially_empty_break_depth &&
8819        !ctx->cf_info.parent_if.is_divergent) {
8820       ctx->cf_info.exec_potentially_empty_break = false;
8821       ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8822    }
8823    /* uniform control flow never has an empty exec-mask */
8824    if (!ctx->cf_info.loop_nest_depth && !ctx->cf_info.parent_if.is_divergent) {
8825       ctx->cf_info.exec_potentially_empty_discard = false;
8826       ctx->cf_info.exec_potentially_empty_break = false;
8827       ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8828    }
8829 }
8830
8831 static bool visit_if(isel_context *ctx, nir_if *if_stmt)
8832 {
8833    Temp cond = get_ssa_temp(ctx, if_stmt->condition.ssa);
8834    Builder bld(ctx->program, ctx->block);
8835    aco_ptr<Pseudo_branch_instruction> branch;
8836
8837    if (!ctx->divergent_vals[if_stmt->condition.ssa->index]) { /* uniform condition */
8838       /**
8839        * Uniform conditionals are represented in the following way*) :
8840        *
8841        * The linear and logical CFG:
8842        *                        BB_IF
8843        *                        /    \
8844        *       BB_THEN (logical)      BB_ELSE (logical)
8845        *                        \    /
8846        *                        BB_ENDIF
8847        *
8848        * *) Exceptions may be due to break and continue statements within loops
8849        *    If a break/continue happens within uniform control flow, it branches
8850        *    to the loop exit/entry block. Otherwise, it branches to the next
8851        *    merge block.
8852        **/
8853       append_logical_end(ctx->block);
8854       ctx->block->kind |= block_kind_uniform;
8855
8856       /* emit branch */
8857       assert(cond.regClass() == bld.lm);
8858       // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
8859       cond = bool_to_scalar_condition(ctx, cond);
8860
8861       branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_z, Format::PSEUDO_BRANCH, 1, 0));
8862       branch->operands[0] = Operand(cond);
8863       branch->operands[0].setFixed(scc);
8864       ctx->block->instructions.emplace_back(std::move(branch));
8865
8866       unsigned BB_if_idx = ctx->block->index;
8867       Block BB_endif = Block();
8868       BB_endif.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8869       BB_endif.kind |= ctx->block->kind & block_kind_top_level;
8870
8871       /** emit then block */
8872       Block* BB_then = ctx->program->create_and_insert_block();
8873       BB_then->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8874       add_edge(BB_if_idx, BB_then);
8875       append_logical_start(BB_then);
8876       ctx->block = BB_then;
8877       visit_cf_list(ctx, &if_stmt->then_list);
8878       BB_then = ctx->block;
8879       bool then_branch = ctx->cf_info.has_branch;
8880       bool then_branch_divergent = ctx->cf_info.parent_loop.has_divergent_branch;
8881
8882       if (!then_branch) {
8883          append_logical_end(BB_then);
8884          /* branch from then block to endif block */
8885          branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8886          BB_then->instructions.emplace_back(std::move(branch));
8887          add_linear_edge(BB_then->index, &BB_endif);
8888          if (!then_branch_divergent)
8889             add_logical_edge(BB_then->index, &BB_endif);
8890          BB_then->kind |= block_kind_uniform;
8891       }
8892
8893       ctx->cf_info.has_branch = false;
8894       ctx->cf_info.parent_loop.has_divergent_branch = false;
8895
8896       /** emit else block */
8897       Block* BB_else = ctx->program->create_and_insert_block();
8898       BB_else->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8899       add_edge(BB_if_idx, BB_else);
8900       append_logical_start(BB_else);
8901       ctx->block = BB_else;
8902       visit_cf_list(ctx, &if_stmt->else_list);
8903       BB_else = ctx->block;
8904
8905       if (!ctx->cf_info.has_branch) {
8906          append_logical_end(BB_else);
8907          /* branch from then block to endif block */
8908          branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8909          BB_else->instructions.emplace_back(std::move(branch));
8910          add_linear_edge(BB_else->index, &BB_endif);
8911          if (!ctx->cf_info.parent_loop.has_divergent_branch)
8912             add_logical_edge(BB_else->index, &BB_endif);
8913          BB_else->kind |= block_kind_uniform;
8914       }
8915
8916       ctx->cf_info.has_branch &= then_branch;
8917       ctx->cf_info.parent_loop.has_divergent_branch &= then_branch_divergent;
8918
8919       /** emit endif merge block */
8920       if (!ctx->cf_info.has_branch) {
8921          ctx->block = ctx->program->insert_block(std::move(BB_endif));
8922          append_logical_start(ctx->block);
8923       }
8924       return !ctx->cf_info.has_branch;
8925    } else { /* non-uniform condition */
8926       /**
8927        * To maintain a logical and linear CFG without critical edges,
8928        * non-uniform conditionals are represented in the following way*) :
8929        *
8930        * The linear CFG:
8931        *                        BB_IF
8932        *                        /    \
8933        *       BB_THEN (logical)      BB_THEN (linear)
8934        *                        \    /
8935        *                        BB_INVERT (linear)
8936        *                        /    \
8937        *       BB_ELSE (logical)      BB_ELSE (linear)
8938        *                        \    /
8939        *                        BB_ENDIF
8940        *
8941        * The logical CFG:
8942        *                        BB_IF
8943        *                        /    \
8944        *       BB_THEN (logical)      BB_ELSE (logical)
8945        *                        \    /
8946        *                        BB_ENDIF
8947        *
8948        * *) Exceptions may be due to break and continue statements within loops
8949        **/
8950
8951       if_context ic;
8952
8953       begin_divergent_if_then(ctx, &ic, cond);
8954       visit_cf_list(ctx, &if_stmt->then_list);
8955
8956       begin_divergent_if_else(ctx, &ic);
8957       visit_cf_list(ctx, &if_stmt->else_list);
8958
8959       end_divergent_if(ctx, &ic);
8960
8961       return true;
8962    }
8963 }
8964
8965 static bool visit_cf_list(isel_context *ctx,
8966                           struct exec_list *list)
8967 {
8968    foreach_list_typed(nir_cf_node, node, node, list) {
8969       switch (node->type) {
8970       case nir_cf_node_block:
8971          visit_block(ctx, nir_cf_node_as_block(node));
8972          break;
8973       case nir_cf_node_if:
8974          if (!visit_if(ctx, nir_cf_node_as_if(node)))
8975             return true;
8976          break;
8977       case nir_cf_node_loop:
8978          visit_loop(ctx, nir_cf_node_as_loop(node));
8979          break;
8980       default:
8981          unreachable("unimplemented cf list type");
8982       }
8983    }
8984    return false;
8985 }
8986
8987 static void create_null_export(isel_context *ctx)
8988 {
8989    /* Some shader stages always need to have exports.
8990     * So when there is none, we need to add a null export.
8991     */
8992
8993    unsigned dest = (ctx->program->stage & hw_fs) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS;
8994    bool vm = (ctx->program->stage & hw_fs) || ctx->program->chip_class >= GFX10;
8995    Builder bld(ctx->program, ctx->block);
8996    bld.exp(aco_opcode::exp, Operand(v1), Operand(v1), Operand(v1), Operand(v1),
8997            /* enabled_mask */ 0, dest, /* compr */ false, /* done */ true, vm);
8998 }
8999
9000 static bool export_vs_varying(isel_context *ctx, int slot, bool is_pos, int *next_pos)
9001 {
9002    assert(ctx->stage == vertex_vs ||
9003           ctx->stage == tess_eval_vs ||
9004           ctx->stage == gs_copy_vs);
9005
9006    int offset = ctx->stage == tess_eval_vs
9007                 ? ctx->program->info->tes.outinfo.vs_output_param_offset[slot]
9008                 : ctx->program->info->vs.outinfo.vs_output_param_offset[slot];
9009    uint64_t mask = ctx->outputs.mask[slot];
9010    if (!is_pos && !mask)
9011       return false;
9012    if (!is_pos && offset == AC_EXP_PARAM_UNDEFINED)
9013       return false;
9014    aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
9015    exp->enabled_mask = mask;
9016    for (unsigned i = 0; i < 4; ++i) {
9017       if (mask & (1 << i))
9018          exp->operands[i] = Operand(ctx->outputs.temps[slot * 4u + i]);
9019       else
9020          exp->operands[i] = Operand(v1);
9021    }
9022    /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9023     * Setting valid_mask=1 prevents it and has no other effect.
9024     */
9025    exp->valid_mask = ctx->options->chip_class >= GFX10 && is_pos && *next_pos == 0;
9026    exp->done = false;
9027    exp->compressed = false;
9028    if (is_pos)
9029       exp->dest = V_008DFC_SQ_EXP_POS + (*next_pos)++;
9030    else
9031       exp->dest = V_008DFC_SQ_EXP_PARAM + offset;
9032    ctx->block->instructions.emplace_back(std::move(exp));
9033
9034    return true;
9035 }
9036
9037 static void export_vs_psiz_layer_viewport(isel_context *ctx, int *next_pos)
9038 {
9039    aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
9040    exp->enabled_mask = 0;
9041    for (unsigned i = 0; i < 4; ++i)
9042       exp->operands[i] = Operand(v1);
9043    if (ctx->outputs.mask[VARYING_SLOT_PSIZ]) {
9044       exp->operands[0] = Operand(ctx->outputs.temps[VARYING_SLOT_PSIZ * 4u]);
9045       exp->enabled_mask |= 0x1;
9046    }
9047    if (ctx->outputs.mask[VARYING_SLOT_LAYER]) {
9048       exp->operands[2] = Operand(ctx->outputs.temps[VARYING_SLOT_LAYER * 4u]);
9049       exp->enabled_mask |= 0x4;
9050    }
9051    if (ctx->outputs.mask[VARYING_SLOT_VIEWPORT]) {
9052       if (ctx->options->chip_class < GFX9) {
9053          exp->operands[3] = Operand(ctx->outputs.temps[VARYING_SLOT_VIEWPORT * 4u]);
9054          exp->enabled_mask |= 0x8;
9055       } else {
9056          Builder bld(ctx->program, ctx->block);
9057
9058          Temp out = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(16u),
9059                              Operand(ctx->outputs.temps[VARYING_SLOT_VIEWPORT * 4u]));
9060          if (exp->operands[2].isTemp())
9061             out = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(out), exp->operands[2]);
9062
9063          exp->operands[2] = Operand(out);
9064          exp->enabled_mask |= 0x4;
9065       }
9066    }
9067    exp->valid_mask = ctx->options->chip_class >= GFX10 && *next_pos == 0;
9068    exp->done = false;
9069    exp->compressed = false;
9070    exp->dest = V_008DFC_SQ_EXP_POS + (*next_pos)++;
9071    ctx->block->instructions.emplace_back(std::move(exp));
9072 }
9073
9074 static void create_vs_exports(isel_context *ctx)
9075 {
9076    assert(ctx->stage == vertex_vs ||
9077           ctx->stage == tess_eval_vs ||
9078           ctx->stage == gs_copy_vs);
9079
9080    radv_vs_output_info *outinfo = ctx->stage == tess_eval_vs
9081                                   ? &ctx->program->info->tes.outinfo
9082                                   : &ctx->program->info->vs.outinfo;
9083
9084    if (outinfo->export_prim_id) {
9085       ctx->outputs.mask[VARYING_SLOT_PRIMITIVE_ID] |= 0x1;
9086       ctx->outputs.temps[VARYING_SLOT_PRIMITIVE_ID * 4u] = get_arg(ctx, ctx->args->vs_prim_id);
9087    }
9088
9089    if (ctx->options->key.has_multiview_view_index) {
9090       ctx->outputs.mask[VARYING_SLOT_LAYER] |= 0x1;
9091       ctx->outputs.temps[VARYING_SLOT_LAYER * 4u] = as_vgpr(ctx, get_arg(ctx, ctx->args->ac.view_index));
9092    }
9093
9094    /* the order these position exports are created is important */
9095    int next_pos = 0;
9096    bool exported_pos = export_vs_varying(ctx, VARYING_SLOT_POS, true, &next_pos);
9097    if (outinfo->writes_pointsize || outinfo->writes_layer || outinfo->writes_viewport_index) {
9098       export_vs_psiz_layer_viewport(ctx, &next_pos);
9099       exported_pos = true;
9100    }
9101    if (ctx->num_clip_distances + ctx->num_cull_distances > 0)
9102       exported_pos |= export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST0, true, &next_pos);
9103    if (ctx->num_clip_distances + ctx->num_cull_distances > 4)
9104       exported_pos |= export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST1, true, &next_pos);
9105
9106    if (ctx->export_clip_dists) {
9107       if (ctx->num_clip_distances + ctx->num_cull_distances > 0)
9108          export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST0, false, &next_pos);
9109       if (ctx->num_clip_distances + ctx->num_cull_distances > 4)
9110          export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST1, false, &next_pos);
9111    }
9112
9113    for (unsigned i = 0; i <= VARYING_SLOT_VAR31; ++i) {
9114       if (i < VARYING_SLOT_VAR0 && i != VARYING_SLOT_LAYER &&
9115           i != VARYING_SLOT_PRIMITIVE_ID)
9116          continue;
9117
9118       export_vs_varying(ctx, i, false, NULL);
9119    }
9120
9121    if (!exported_pos)
9122       create_null_export(ctx);
9123 }
9124
9125 static bool export_fs_mrt_z(isel_context *ctx)
9126 {
9127    Builder bld(ctx->program, ctx->block);
9128    unsigned enabled_channels = 0;
9129    bool compr = false;
9130    Operand values[4];
9131
9132    for (unsigned i = 0; i < 4; ++i) {
9133       values[i] = Operand(v1);
9134    }
9135
9136    /* Both stencil and sample mask only need 16-bits. */
9137    if (!ctx->program->info->ps.writes_z &&
9138        (ctx->program->info->ps.writes_stencil ||
9139         ctx->program->info->ps.writes_sample_mask)) {
9140       compr = true; /* COMPR flag */
9141
9142       if (ctx->program->info->ps.writes_stencil) {
9143          /* Stencil should be in X[23:16]. */
9144          values[0] = Operand(ctx->outputs.temps[FRAG_RESULT_STENCIL * 4u]);
9145          values[0] = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(16u), values[0]);
9146          enabled_channels |= 0x3;
9147       }
9148
9149       if (ctx->program->info->ps.writes_sample_mask) {
9150          /* SampleMask should be in Y[15:0]. */
9151          values[1] = Operand(ctx->outputs.temps[FRAG_RESULT_SAMPLE_MASK * 4u]);
9152          enabled_channels |= 0xc;
9153      }
9154    } else {
9155       if (ctx->program->info->ps.writes_z) {
9156          values[0] = Operand(ctx->outputs.temps[FRAG_RESULT_DEPTH * 4u]);
9157          enabled_channels |= 0x1;
9158       }
9159
9160       if (ctx->program->info->ps.writes_stencil) {
9161          values[1] = Operand(ctx->outputs.temps[FRAG_RESULT_STENCIL * 4u]);
9162          enabled_channels |= 0x2;
9163       }
9164
9165       if (ctx->program->info->ps.writes_sample_mask) {
9166          values[2] = Operand(ctx->outputs.temps[FRAG_RESULT_SAMPLE_MASK * 4u]);
9167          enabled_channels |= 0x4;
9168       }
9169    }
9170
9171    /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9172     * writemask component.
9173     */
9174    if (ctx->options->chip_class == GFX6 &&
9175        ctx->options->family != CHIP_OLAND &&
9176        ctx->options->family != CHIP_HAINAN) {
9177             enabled_channels |= 0x1;
9178    }
9179
9180    bld.exp(aco_opcode::exp, values[0], values[1], values[2], values[3],
9181            enabled_channels, V_008DFC_SQ_EXP_MRTZ, compr);
9182
9183    return true;
9184 }
9185
9186 static bool export_fs_mrt_color(isel_context *ctx, int slot)
9187 {
9188    Builder bld(ctx->program, ctx->block);
9189    unsigned write_mask = ctx->outputs.mask[slot];
9190    Operand values[4];
9191
9192    for (unsigned i = 0; i < 4; ++i) {
9193       if (write_mask & (1 << i)) {
9194          values[i] = Operand(ctx->outputs.temps[slot * 4u + i]);
9195       } else {
9196          values[i] = Operand(v1);
9197       }
9198    }
9199
9200    unsigned target, col_format;
9201    unsigned enabled_channels = 0;
9202    aco_opcode compr_op = (aco_opcode)0;
9203
9204    slot -= FRAG_RESULT_DATA0;
9205    target = V_008DFC_SQ_EXP_MRT + slot;
9206    col_format = (ctx->options->key.fs.col_format >> (4 * slot)) & 0xf;
9207
9208    bool is_int8 = (ctx->options->key.fs.is_int8 >> slot) & 1;
9209    bool is_int10 = (ctx->options->key.fs.is_int10 >> slot) & 1;
9210
9211    switch (col_format)
9212    {
9213    case V_028714_SPI_SHADER_ZERO:
9214       enabled_channels = 0; /* writemask */
9215       target = V_008DFC_SQ_EXP_NULL;
9216       break;
9217
9218    case V_028714_SPI_SHADER_32_R:
9219       enabled_channels = 1;
9220       break;
9221
9222    case V_028714_SPI_SHADER_32_GR:
9223       enabled_channels = 0x3;
9224       break;
9225
9226    case V_028714_SPI_SHADER_32_AR:
9227       if (ctx->options->chip_class >= GFX10) {
9228          /* Special case: on GFX10, the outputs are different for 32_AR */
9229          enabled_channels = 0x3;
9230          values[1] = values[3];
9231          values[3] = Operand(v1);
9232       } else {
9233          enabled_channels = 0x9;
9234       }
9235       break;
9236
9237    case V_028714_SPI_SHADER_FP16_ABGR:
9238       enabled_channels = 0x5;
9239       compr_op = aco_opcode::v_cvt_pkrtz_f16_f32;
9240       break;
9241
9242    case V_028714_SPI_SHADER_UNORM16_ABGR:
9243       enabled_channels = 0x5;
9244       compr_op = aco_opcode::v_cvt_pknorm_u16_f32;
9245       break;
9246
9247    case V_028714_SPI_SHADER_SNORM16_ABGR:
9248       enabled_channels = 0x5;
9249       compr_op = aco_opcode::v_cvt_pknorm_i16_f32;
9250       break;
9251
9252    case V_028714_SPI_SHADER_UINT16_ABGR: {
9253       enabled_channels = 0x5;
9254       compr_op = aco_opcode::v_cvt_pk_u16_u32;
9255       if (is_int8 || is_int10) {
9256          /* clamp */
9257          uint32_t max_rgb = is_int8 ? 255 : is_int10 ? 1023 : 0;
9258          Temp max_rgb_val = bld.copy(bld.def(s1), Operand(max_rgb));
9259
9260          for (unsigned i = 0; i < 4; i++) {
9261             if ((write_mask >> i) & 1) {
9262                values[i] = bld.vop2(aco_opcode::v_min_u32, bld.def(v1),
9263                                     i == 3 && is_int10 ? Operand(3u) : Operand(max_rgb_val),
9264                                     values[i]);
9265             }
9266          }
9267       }
9268       break;
9269    }
9270
9271    case V_028714_SPI_SHADER_SINT16_ABGR:
9272       enabled_channels = 0x5;
9273       compr_op = aco_opcode::v_cvt_pk_i16_i32;
9274       if (is_int8 || is_int10) {
9275          /* clamp */
9276          uint32_t max_rgb = is_int8 ? 127 : is_int10 ? 511 : 0;
9277          uint32_t min_rgb = is_int8 ? -128 :is_int10 ? -512 : 0;
9278          Temp max_rgb_val = bld.copy(bld.def(s1), Operand(max_rgb));
9279          Temp min_rgb_val = bld.copy(bld.def(s1), Operand(min_rgb));
9280
9281          for (unsigned i = 0; i < 4; i++) {
9282             if ((write_mask >> i) & 1) {
9283                values[i] = bld.vop2(aco_opcode::v_min_i32, bld.def(v1),
9284                                     i == 3 && is_int10 ? Operand(1u) : Operand(max_rgb_val),
9285                                     values[i]);
9286                values[i] = bld.vop2(aco_opcode::v_max_i32, bld.def(v1),
9287                                     i == 3 && is_int10 ? Operand(-2u) : Operand(min_rgb_val),
9288                                     values[i]);
9289             }
9290          }
9291       }
9292       break;
9293
9294    case V_028714_SPI_SHADER_32_ABGR:
9295       enabled_channels = 0xF;
9296       break;
9297
9298    default:
9299       break;
9300    }
9301
9302    if (target == V_008DFC_SQ_EXP_NULL)
9303       return false;
9304
9305    if ((bool) compr_op) {
9306       for (int i = 0; i < 2; i++) {
9307          /* check if at least one of the values to be compressed is enabled */
9308          unsigned enabled = (write_mask >> (i*2) | write_mask >> (i*2+1)) & 0x1;
9309          if (enabled) {
9310             enabled_channels |= enabled << (i*2);
9311             values[i] = bld.vop3(compr_op, bld.def(v1),
9312                                  values[i*2].isUndefined() ? Operand(0u) : values[i*2],
9313                                  values[i*2+1].isUndefined() ? Operand(0u): values[i*2+1]);
9314          } else {
9315             values[i] = Operand(v1);
9316          }
9317       }
9318       values[2] = Operand(v1);
9319       values[3] = Operand(v1);
9320    } else {
9321       for (int i = 0; i < 4; i++)
9322          values[i] = enabled_channels & (1 << i) ? values[i] : Operand(v1);
9323    }
9324
9325    bld.exp(aco_opcode::exp, values[0], values[1], values[2], values[3],
9326            enabled_channels, target, (bool) compr_op);
9327    return true;
9328 }
9329
9330 static void create_fs_exports(isel_context *ctx)
9331 {
9332    bool exported = false;
9333
9334    /* Export depth, stencil and sample mask. */
9335    if (ctx->outputs.mask[FRAG_RESULT_DEPTH] ||
9336        ctx->outputs.mask[FRAG_RESULT_STENCIL] ||
9337        ctx->outputs.mask[FRAG_RESULT_SAMPLE_MASK])
9338       exported |= export_fs_mrt_z(ctx);
9339
9340    /* Export all color render targets. */
9341    for (unsigned i = FRAG_RESULT_DATA0; i < FRAG_RESULT_DATA7 + 1; ++i)
9342       if (ctx->outputs.mask[i])
9343          exported |= export_fs_mrt_color(ctx, i);
9344
9345    if (!exported)
9346       create_null_export(ctx);
9347 }
9348
9349 static void write_tcs_tess_factors(isel_context *ctx)
9350 {
9351    unsigned outer_comps;
9352    unsigned inner_comps;
9353
9354    switch (ctx->args->options->key.tcs.primitive_mode) {
9355    case GL_ISOLINES:
9356       outer_comps = 2;
9357       inner_comps = 0;
9358       break;
9359    case GL_TRIANGLES:
9360       outer_comps = 3;
9361       inner_comps = 1;
9362       break;
9363    case GL_QUADS:
9364       outer_comps = 4;
9365       inner_comps = 2;
9366       break;
9367    default:
9368       return;
9369    }
9370
9371    Builder bld(ctx->program, ctx->block);
9372
9373    bld.barrier(aco_opcode::p_memory_barrier_shared);
9374    if (unlikely(ctx->program->chip_class != GFX6 && ctx->program->workgroup_size > ctx->program->wave_size))
9375       bld.sopp(aco_opcode::s_barrier);
9376
9377    Temp tcs_rel_ids = get_arg(ctx, ctx->args->ac.tcs_rel_ids);
9378    Temp invocation_id = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1), tcs_rel_ids, Operand(8u), Operand(5u));
9379
9380    Temp invocation_id_is_zero = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), invocation_id);
9381    if_context ic_invocation_id_is_zero;
9382    begin_divergent_if_then(ctx, &ic_invocation_id_is_zero, invocation_id_is_zero);
9383    bld.reset(ctx->block);
9384
9385    Temp hs_ring_tess_factor = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_HS_TESS_FACTOR * 16u));
9386
9387    std::pair<Temp, unsigned> lds_base = get_tcs_output_lds_offset(ctx);
9388    unsigned stride = inner_comps + outer_comps;
9389    unsigned lds_align = calculate_lds_alignment(ctx, lds_base.second);
9390    Temp tf_inner_vec;
9391    Temp tf_outer_vec;
9392    Temp out[6];
9393    assert(stride <= (sizeof(out) / sizeof(Temp)));
9394
9395    if (ctx->args->options->key.tcs.primitive_mode == GL_ISOLINES) {
9396       // LINES reversal
9397       tf_outer_vec = load_lds(ctx, 4, bld.tmp(v2), lds_base.first, lds_base.second + ctx->tcs_tess_lvl_out_loc, lds_align);
9398       out[1] = emit_extract_vector(ctx, tf_outer_vec, 0, v1);
9399       out[0] = emit_extract_vector(ctx, tf_outer_vec, 1, v1);
9400    } else {
9401       tf_outer_vec = load_lds(ctx, 4, bld.tmp(RegClass(RegType::vgpr, outer_comps)), lds_base.first, lds_base.second + ctx->tcs_tess_lvl_out_loc, lds_align);
9402       tf_inner_vec = load_lds(ctx, 4, bld.tmp(RegClass(RegType::vgpr, inner_comps)), lds_base.first, lds_base.second + ctx->tcs_tess_lvl_in_loc, lds_align);
9403
9404       for (unsigned i = 0; i < outer_comps; ++i)
9405          out[i] = emit_extract_vector(ctx, tf_outer_vec, i, v1);
9406       for (unsigned i = 0; i < inner_comps; ++i)
9407          out[outer_comps + i] = emit_extract_vector(ctx, tf_inner_vec, i, v1);
9408    }
9409
9410    Temp rel_patch_id = get_tess_rel_patch_id(ctx);
9411    Temp tf_base = get_arg(ctx, ctx->args->tess_factor_offset);
9412    Temp byte_offset = bld.v_mul_imm(bld.def(v1), rel_patch_id, stride * 4u);
9413    unsigned tf_const_offset = 0;
9414
9415    if (ctx->program->chip_class <= GFX8) {
9416       Temp rel_patch_id_is_zero = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), rel_patch_id);
9417       if_context ic_rel_patch_id_is_zero;
9418       begin_divergent_if_then(ctx, &ic_rel_patch_id_is_zero, rel_patch_id_is_zero);
9419       bld.reset(ctx->block);
9420
9421       /* Store the dynamic HS control word. */
9422       Temp control_word = bld.copy(bld.def(v1), Operand(0x80000000u));
9423       bld.mubuf(aco_opcode::buffer_store_dword,
9424                 /* SRSRC */ hs_ring_tess_factor, /* VADDR */ Operand(v1), /* SOFFSET */ tf_base, /* VDATA */ control_word,
9425                 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
9426                 /* disable_wqm */ false, /* glc */ true);
9427       tf_const_offset += 4;
9428
9429       begin_divergent_if_else(ctx, &ic_rel_patch_id_is_zero);
9430       end_divergent_if(ctx, &ic_rel_patch_id_is_zero);
9431       bld.reset(ctx->block);
9432    }
9433
9434    assert(stride == 2 || stride == 4 || stride == 6);
9435    Temp tf_vec = create_vec_from_array(ctx, out, stride, RegType::vgpr, 4u);
9436    store_vmem_mubuf(ctx, tf_vec, hs_ring_tess_factor, byte_offset, tf_base, tf_const_offset, 4, (1 << stride) - 1, true, false);
9437
9438    /* Store to offchip for TES to read - only if TES reads them */
9439    if (ctx->args->options->key.tcs.tes_reads_tess_factors) {
9440       Temp hs_ring_tess_offchip = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_HS_TESS_OFFCHIP * 16u));
9441       Temp oc_lds = get_arg(ctx, ctx->args->oc_lds);
9442
9443       std::pair<Temp, unsigned> vmem_offs_outer = get_tcs_per_patch_output_vmem_offset(ctx, nullptr, ctx->tcs_tess_lvl_out_loc);
9444       store_vmem_mubuf(ctx, tf_outer_vec, hs_ring_tess_offchip, vmem_offs_outer.first, oc_lds, vmem_offs_outer.second, 4, (1 << outer_comps) - 1, true, false);
9445
9446       if (likely(inner_comps)) {
9447          std::pair<Temp, unsigned> vmem_offs_inner = get_tcs_per_patch_output_vmem_offset(ctx, nullptr, ctx->tcs_tess_lvl_in_loc);
9448          store_vmem_mubuf(ctx, tf_inner_vec, hs_ring_tess_offchip, vmem_offs_inner.first, oc_lds, vmem_offs_inner.second, 4, (1 << inner_comps) - 1, true, false);
9449       }
9450    }
9451
9452    begin_divergent_if_else(ctx, &ic_invocation_id_is_zero);
9453    end_divergent_if(ctx, &ic_invocation_id_is_zero);
9454 }
9455
9456 static void emit_stream_output(isel_context *ctx,
9457                                Temp const *so_buffers,
9458                                Temp const *so_write_offset,
9459                                const struct radv_stream_output *output)
9460 {
9461    unsigned num_comps = util_bitcount(output->component_mask);
9462    unsigned writemask = (1 << num_comps) - 1;
9463    unsigned loc = output->location;
9464    unsigned buf = output->buffer;
9465
9466    assert(num_comps && num_comps <= 4);
9467    if (!num_comps || num_comps > 4)
9468       return;
9469
9470    unsigned start = ffs(output->component_mask) - 1;
9471
9472    Temp out[4];
9473    bool all_undef = true;
9474    assert(ctx->stage == vertex_vs || ctx->stage == gs_copy_vs);
9475    for (unsigned i = 0; i < num_comps; i++) {
9476       out[i] = ctx->outputs.temps[loc * 4 + start + i];
9477       all_undef = all_undef && !out[i].id();
9478    }
9479    if (all_undef)
9480       return;
9481
9482    while (writemask) {
9483       int start, count;
9484       u_bit_scan_consecutive_range(&writemask, &start, &count);
9485       if (count == 3 && ctx->options->chip_class == GFX6) {
9486          /* GFX6 doesn't support storing vec3, split it. */
9487          writemask |= 1u << (start + 2);
9488          count = 2;
9489       }
9490
9491       unsigned offset = output->offset + start * 4;
9492
9493       Temp write_data = {ctx->program->allocateId(), RegClass(RegType::vgpr, count)};
9494       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
9495       for (int i = 0; i < count; ++i)
9496          vec->operands[i] = (ctx->outputs.mask[loc] & 1 << (start + i)) ? Operand(out[start + i]) : Operand(0u);
9497       vec->definitions[0] = Definition(write_data);
9498       ctx->block->instructions.emplace_back(std::move(vec));
9499
9500       aco_opcode opcode;
9501       switch (count) {
9502       case 1:
9503          opcode = aco_opcode::buffer_store_dword;
9504          break;
9505       case 2:
9506          opcode = aco_opcode::buffer_store_dwordx2;
9507          break;
9508       case 3:
9509          opcode = aco_opcode::buffer_store_dwordx3;
9510          break;
9511       case 4:
9512          opcode = aco_opcode::buffer_store_dwordx4;
9513          break;
9514       default:
9515          unreachable("Unsupported dword count.");
9516       }
9517
9518       aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 4, 0)};
9519       store->operands[0] = Operand(so_buffers[buf]);
9520       store->operands[1] = Operand(so_write_offset[buf]);
9521       store->operands[2] = Operand((uint32_t) 0);
9522       store->operands[3] = Operand(write_data);
9523       if (offset > 4095) {
9524          /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
9525          Builder bld(ctx->program, ctx->block);
9526          store->operands[0] = bld.vadd32(bld.def(v1), Operand(offset), Operand(so_write_offset[buf]));
9527       } else {
9528          store->offset = offset;
9529       }
9530       store->offen = true;
9531       store->glc = true;
9532       store->dlc = false;
9533       store->slc = true;
9534       store->can_reorder = true;
9535       ctx->block->instructions.emplace_back(std::move(store));
9536    }
9537 }
9538
9539 static void emit_streamout(isel_context *ctx, unsigned stream)
9540 {
9541    Builder bld(ctx->program, ctx->block);
9542
9543    Temp so_buffers[4];
9544    Temp buf_ptr = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->streamout_buffers));
9545    for (unsigned i = 0; i < 4; i++) {
9546       unsigned stride = ctx->program->info->so.strides[i];
9547       if (!stride)
9548          continue;
9549
9550       Operand off = bld.copy(bld.def(s1), Operand(i * 16u));
9551       so_buffers[i] = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), buf_ptr, off);
9552    }
9553
9554    Temp so_vtx_count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
9555                                 get_arg(ctx, ctx->args->streamout_config), Operand(0x70010u));
9556
9557    Temp tid = emit_mbcnt(ctx, bld.def(v1));
9558
9559    Temp can_emit = bld.vopc(aco_opcode::v_cmp_gt_i32, bld.def(bld.lm), so_vtx_count, tid);
9560
9561    if_context ic;
9562    begin_divergent_if_then(ctx, &ic, can_emit);
9563
9564    bld.reset(ctx->block);
9565
9566    Temp so_write_index = bld.vadd32(bld.def(v1), get_arg(ctx, ctx->args->streamout_write_idx), tid);
9567
9568    Temp so_write_offset[4];
9569
9570    for (unsigned i = 0; i < 4; i++) {
9571       unsigned stride = ctx->program->info->so.strides[i];
9572       if (!stride)
9573          continue;
9574
9575       if (stride == 1) {
9576          Temp offset = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
9577                                 get_arg(ctx, ctx->args->streamout_write_idx),
9578                                 get_arg(ctx, ctx->args->streamout_offset[i]));
9579          Temp new_offset = bld.vadd32(bld.def(v1), offset, tid);
9580
9581          so_write_offset[i] = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), new_offset);
9582       } else {
9583          Temp offset = bld.v_mul_imm(bld.def(v1), so_write_index, stride * 4u);
9584          Temp offset2 = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(4u),
9585                                  get_arg(ctx, ctx->args->streamout_offset[i]));
9586          so_write_offset[i] = bld.vadd32(bld.def(v1), offset, offset2);
9587       }
9588    }
9589
9590    for (unsigned i = 0; i < ctx->program->info->so.num_outputs; i++) {
9591       struct radv_stream_output *output =
9592          &ctx->program->info->so.outputs[i];
9593       if (stream != output->stream)
9594          continue;
9595
9596       emit_stream_output(ctx, so_buffers, so_write_offset, output);
9597    }
9598
9599    begin_divergent_if_else(ctx, &ic);
9600    end_divergent_if(ctx, &ic);
9601 }
9602
9603 } /* end namespace */
9604
9605 void fix_ls_vgpr_init_bug(isel_context *ctx, Pseudo_instruction *startpgm)
9606 {
9607    assert(ctx->shader->info.stage == MESA_SHADER_VERTEX);
9608    Builder bld(ctx->program, ctx->block);
9609    constexpr unsigned hs_idx = 1u;
9610    Builder::Result hs_thread_count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
9611                                               get_arg(ctx, ctx->args->merged_wave_info),
9612                                               Operand((8u << 16) | (hs_idx * 8u)));
9613    Temp ls_has_nonzero_hs_threads = bool_to_vector_condition(ctx, hs_thread_count.def(1).getTemp());
9614
9615    /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
9616
9617    Temp instance_id = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
9618                                get_arg(ctx, ctx->args->rel_auto_id),
9619                                get_arg(ctx, ctx->args->ac.instance_id),
9620                                ls_has_nonzero_hs_threads);
9621    Temp rel_auto_id = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
9622                                get_arg(ctx, ctx->args->ac.tcs_rel_ids),
9623                                get_arg(ctx, ctx->args->rel_auto_id),
9624                                ls_has_nonzero_hs_threads);
9625    Temp vertex_id = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
9626                              get_arg(ctx, ctx->args->ac.tcs_patch_id),
9627                              get_arg(ctx, ctx->args->ac.vertex_id),
9628                              ls_has_nonzero_hs_threads);
9629
9630    ctx->arg_temps[ctx->args->ac.instance_id.arg_index] = instance_id;
9631    ctx->arg_temps[ctx->args->rel_auto_id.arg_index] = rel_auto_id;
9632    ctx->arg_temps[ctx->args->ac.vertex_id.arg_index] = vertex_id;
9633 }
9634
9635 void split_arguments(isel_context *ctx, Pseudo_instruction *startpgm)
9636 {
9637    /* Split all arguments except for the first (ring_offsets) and the last
9638     * (exec) so that the dead channels don't stay live throughout the program.
9639     */
9640    for (int i = 1; i < startpgm->definitions.size() - 1; i++) {
9641       if (startpgm->definitions[i].regClass().size() > 1) {
9642          emit_split_vector(ctx, startpgm->definitions[i].getTemp(),
9643                            startpgm->definitions[i].regClass().size());
9644       }
9645    }
9646 }
9647
9648 void handle_bc_optimize(isel_context *ctx)
9649 {
9650    /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
9651    Builder bld(ctx->program, ctx->block);
9652    uint32_t spi_ps_input_ena = ctx->program->config->spi_ps_input_ena;
9653    bool uses_center = G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena);
9654    bool uses_centroid = G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena);
9655    ctx->persp_centroid = get_arg(ctx, ctx->args->ac.persp_centroid);
9656    ctx->linear_centroid = get_arg(ctx, ctx->args->ac.linear_centroid);
9657    if (uses_center && uses_centroid) {
9658       Temp sel = bld.vopc_e64(aco_opcode::v_cmp_lt_i32, bld.hint_vcc(bld.def(bld.lm)),
9659                               get_arg(ctx, ctx->args->ac.prim_mask), Operand(0u));
9660
9661       if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena)) {
9662          Temp new_coord[2];
9663          for (unsigned i = 0; i < 2; i++) {
9664             Temp persp_centroid = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.persp_centroid), i, v1);
9665             Temp persp_center = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.persp_center), i, v1);
9666             new_coord[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
9667                                     persp_centroid, persp_center, sel);
9668          }
9669          ctx->persp_centroid = bld.tmp(v2);
9670          bld.pseudo(aco_opcode::p_create_vector, Definition(ctx->persp_centroid),
9671                     Operand(new_coord[0]), Operand(new_coord[1]));
9672          emit_split_vector(ctx, ctx->persp_centroid, 2);
9673       }
9674
9675       if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena)) {
9676          Temp new_coord[2];
9677          for (unsigned i = 0; i < 2; i++) {
9678             Temp linear_centroid = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.linear_centroid), i, v1);
9679             Temp linear_center = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.linear_center), i, v1);
9680             new_coord[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
9681                                     linear_centroid, linear_center, sel);
9682          }
9683          ctx->linear_centroid = bld.tmp(v2);
9684          bld.pseudo(aco_opcode::p_create_vector, Definition(ctx->linear_centroid),
9685                     Operand(new_coord[0]), Operand(new_coord[1]));
9686          emit_split_vector(ctx, ctx->linear_centroid, 2);
9687       }
9688    }
9689 }
9690
9691 void setup_fp_mode(isel_context *ctx, nir_shader *shader)
9692 {
9693    Program *program = ctx->program;
9694
9695    unsigned float_controls = shader->info.float_controls_execution_mode;
9696
9697    program->next_fp_mode.preserve_signed_zero_inf_nan32 =
9698       float_controls & FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32;
9699    program->next_fp_mode.preserve_signed_zero_inf_nan16_64 =
9700       float_controls & (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16 |
9701                         FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64);
9702
9703    program->next_fp_mode.must_flush_denorms32 =
9704       float_controls & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32;
9705    program->next_fp_mode.must_flush_denorms16_64 =
9706       float_controls & (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16 |
9707                         FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64);
9708
9709    program->next_fp_mode.care_about_round32 =
9710       float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32 | FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32);
9711
9712    program->next_fp_mode.care_about_round16_64 =
9713       float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64 |
9714                         FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64);
9715
9716    /* default to preserving fp16 and fp64 denorms, since it's free */
9717    if (program->next_fp_mode.must_flush_denorms16_64)
9718       program->next_fp_mode.denorm16_64 = 0;
9719    else
9720       program->next_fp_mode.denorm16_64 = fp_denorm_keep;
9721
9722    /* preserving fp32 denorms is expensive, so only do it if asked */
9723    if (float_controls & FLOAT_CONTROLS_DENORM_PRESERVE_FP32)
9724       program->next_fp_mode.denorm32 = fp_denorm_keep;
9725    else
9726       program->next_fp_mode.denorm32 = 0;
9727
9728    if (float_controls & FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32)
9729       program->next_fp_mode.round32 = fp_round_tz;
9730    else
9731       program->next_fp_mode.round32 = fp_round_ne;
9732
9733    if (float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64))
9734       program->next_fp_mode.round16_64 = fp_round_tz;
9735    else
9736       program->next_fp_mode.round16_64 = fp_round_ne;
9737
9738    ctx->block->fp_mode = program->next_fp_mode;
9739 }
9740
9741 void cleanup_cfg(Program *program)
9742 {
9743    /* create linear_succs/logical_succs */
9744    for (Block& BB : program->blocks) {
9745       for (unsigned idx : BB.linear_preds)
9746          program->blocks[idx].linear_succs.emplace_back(BB.index);
9747       for (unsigned idx : BB.logical_preds)
9748          program->blocks[idx].logical_succs.emplace_back(BB.index);
9749    }
9750 }
9751
9752 void select_program(Program *program,
9753                     unsigned shader_count,
9754                     struct nir_shader *const *shaders,
9755                     ac_shader_config* config,
9756                     struct radv_shader_args *args)
9757 {
9758    isel_context ctx = setup_isel_context(program, shader_count, shaders, config, args, false);
9759    if_context ic_merged_wave_info;
9760
9761    for (unsigned i = 0; i < shader_count; i++) {
9762       nir_shader *nir = shaders[i];
9763       init_context(&ctx, nir);
9764
9765       setup_fp_mode(&ctx, nir);
9766
9767       if (!i) {
9768          /* needs to be after init_context() for FS */
9769          Pseudo_instruction *startpgm = add_startpgm(&ctx);
9770          append_logical_start(ctx.block);
9771
9772          if (unlikely(args->options->has_ls_vgpr_init_bug && ctx.stage == vertex_tess_control_hs))
9773             fix_ls_vgpr_init_bug(&ctx, startpgm);
9774
9775          split_arguments(&ctx, startpgm);
9776       }
9777
9778       /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
9779       nir_function_impl *func = nir_shader_get_entrypoint(nir);
9780       bool empty_shader = nir_cf_list_is_empty_block(&func->body) &&
9781                           ((nir->info.stage == MESA_SHADER_VERTEX &&
9782                             (ctx.stage == vertex_tess_control_hs || ctx.stage == vertex_geometry_gs)) ||
9783                            (nir->info.stage == MESA_SHADER_TESS_EVAL &&
9784                             ctx.stage == tess_eval_geometry_gs));
9785
9786       bool check_merged_wave_info = ctx.tcs_in_out_eq ? i == 0 : (shader_count >= 2 && !empty_shader);
9787       bool endif_merged_wave_info = ctx.tcs_in_out_eq ? i == 1 : check_merged_wave_info;
9788       if (check_merged_wave_info) {
9789          Builder bld(ctx.program, ctx.block);
9790
9791          /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
9792          Temp count = i == 0 ? get_arg(&ctx, args->merged_wave_info)
9793                              : bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc),
9794                                         get_arg(&ctx, args->merged_wave_info), Operand(i * 8u));
9795
9796          Temp mask = bld.sop2(aco_opcode::s_bfm_b64, bld.def(s2), count, Operand(0u));
9797          Temp cond;
9798
9799          if (ctx.program->wave_size == 64) {
9800             /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
9801             Temp active_64 = bld.sopc(aco_opcode::s_bitcmp1_b32, bld.def(s1, scc), count, Operand(6u /* log2(64) */));
9802             cond = bld.sop2(Builder::s_cselect, bld.def(bld.lm), Operand(-1u), mask, bld.scc(active_64));
9803          } else {
9804             /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
9805             cond = emit_extract_vector(&ctx, mask, 0, bld.lm);
9806          }
9807
9808          begin_divergent_if_then(&ctx, &ic_merged_wave_info, cond);
9809       }
9810
9811       if (i) {
9812          Builder bld(ctx.program, ctx.block);
9813
9814          bld.barrier(aco_opcode::p_memory_barrier_shared);
9815          bld.sopp(aco_opcode::s_barrier);
9816
9817          if (ctx.stage == vertex_geometry_gs || ctx.stage == tess_eval_geometry_gs) {
9818             ctx.gs_wave_id = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1, m0), bld.def(s1, scc), get_arg(&ctx, args->merged_wave_info), Operand((8u << 16) | 16u));
9819          }
9820       } else if (ctx.stage == geometry_gs)
9821          ctx.gs_wave_id = get_arg(&ctx, args->gs_wave_id);
9822
9823       if (ctx.stage == fragment_fs)
9824          handle_bc_optimize(&ctx);
9825
9826       visit_cf_list(&ctx, &func->body);
9827
9828       if (ctx.program->info->so.num_outputs && (ctx.stage == vertex_vs || ctx.stage == tess_eval_vs))
9829          emit_streamout(&ctx, 0);
9830
9831       if (ctx.stage == vertex_vs || ctx.stage == tess_eval_vs) {
9832          create_vs_exports(&ctx);
9833       } else if (nir->info.stage == MESA_SHADER_GEOMETRY) {
9834          Builder bld(ctx.program, ctx.block);
9835          bld.barrier(aco_opcode::p_memory_barrier_gs_data);
9836          bld.sopp(aco_opcode::s_sendmsg, bld.m0(ctx.gs_wave_id), -1, sendmsg_gs_done(false, false, 0));
9837       } else if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
9838          write_tcs_tess_factors(&ctx);
9839       }
9840
9841       if (ctx.stage == fragment_fs)
9842          create_fs_exports(&ctx);
9843
9844       if (endif_merged_wave_info) {
9845          begin_divergent_if_else(&ctx, &ic_merged_wave_info);
9846          end_divergent_if(&ctx, &ic_merged_wave_info);
9847       }
9848
9849       ralloc_free(ctx.divergent_vals);
9850
9851       if (i == 0 && ctx.stage == vertex_tess_control_hs && ctx.tcs_in_out_eq) {
9852          /* Outputs of the previous stage are inputs to the next stage */
9853          ctx.inputs = ctx.outputs;
9854          ctx.outputs = shader_io_state();
9855       }
9856    }
9857
9858    program->config->float_mode = program->blocks[0].fp_mode.val;
9859
9860    append_logical_end(ctx.block);
9861    ctx.block->kind |= block_kind_uniform | block_kind_export_end;
9862    Builder bld(ctx.program, ctx.block);
9863    if (ctx.program->wb_smem_l1_on_end)
9864       bld.smem(aco_opcode::s_dcache_wb, false);
9865    bld.sopp(aco_opcode::s_endpgm);
9866
9867    cleanup_cfg(program);
9868 }
9869
9870 void select_gs_copy_shader(Program *program, struct nir_shader *gs_shader,
9871                            ac_shader_config* config,
9872                            struct radv_shader_args *args)
9873 {
9874    isel_context ctx = setup_isel_context(program, 1, &gs_shader, config, args, true);
9875
9876    program->next_fp_mode.preserve_signed_zero_inf_nan32 = false;
9877    program->next_fp_mode.preserve_signed_zero_inf_nan16_64 = false;
9878    program->next_fp_mode.must_flush_denorms32 = false;
9879    program->next_fp_mode.must_flush_denorms16_64 = false;
9880    program->next_fp_mode.care_about_round32 = false;
9881    program->next_fp_mode.care_about_round16_64 = false;
9882    program->next_fp_mode.denorm16_64 = fp_denorm_keep;
9883    program->next_fp_mode.denorm32 = 0;
9884    program->next_fp_mode.round32 = fp_round_ne;
9885    program->next_fp_mode.round16_64 = fp_round_ne;
9886    ctx.block->fp_mode = program->next_fp_mode;
9887
9888    add_startpgm(&ctx);
9889    append_logical_start(ctx.block);
9890
9891    Builder bld(ctx.program, ctx.block);
9892
9893    Temp gsvs_ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), program->private_segment_buffer, Operand(RING_GSVS_VS * 16u));
9894
9895    Operand stream_id(0u);
9896    if (args->shader_info->so.num_outputs)
9897       stream_id = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
9898                            get_arg(&ctx, ctx.args->streamout_config), Operand(0x20018u));
9899
9900    Temp vtx_offset = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), get_arg(&ctx, ctx.args->ac.vertex_id));
9901
9902    std::stack<Block> endif_blocks;
9903
9904    for (unsigned stream = 0; stream < 4; stream++) {
9905       if (stream_id.isConstant() && stream != stream_id.constantValue())
9906          continue;
9907
9908       unsigned num_components = args->shader_info->gs.num_stream_output_components[stream];
9909       if (stream > 0 && (!num_components || !args->shader_info->so.num_outputs))
9910          continue;
9911
9912       memset(ctx.outputs.mask, 0, sizeof(ctx.outputs.mask));
9913
9914       unsigned BB_if_idx = ctx.block->index;
9915       Block BB_endif = Block();
9916       if (!stream_id.isConstant()) {
9917          /* begin IF */
9918          Temp cond = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), stream_id, Operand(stream));
9919          append_logical_end(ctx.block);
9920          ctx.block->kind |= block_kind_uniform;
9921          bld.branch(aco_opcode::p_cbranch_z, cond);
9922
9923          BB_endif.kind |= ctx.block->kind & block_kind_top_level;
9924
9925          ctx.block = ctx.program->create_and_insert_block();
9926          add_edge(BB_if_idx, ctx.block);
9927          bld.reset(ctx.block);
9928          append_logical_start(ctx.block);
9929       }
9930
9931       unsigned offset = 0;
9932       for (unsigned i = 0; i <= VARYING_SLOT_VAR31; ++i) {
9933          if (args->shader_info->gs.output_streams[i] != stream)
9934             continue;
9935
9936          unsigned output_usage_mask = args->shader_info->gs.output_usage_mask[i];
9937          unsigned length = util_last_bit(output_usage_mask);
9938          for (unsigned j = 0; j < length; ++j) {
9939             if (!(output_usage_mask & (1 << j)))
9940                continue;
9941
9942             unsigned const_offset = offset * args->shader_info->gs.vertices_out * 16 * 4;
9943             Temp voffset = vtx_offset;
9944             if (const_offset >= 4096u) {
9945                voffset = bld.vadd32(bld.def(v1), Operand(const_offset / 4096u * 4096u), voffset);
9946                const_offset %= 4096u;
9947             }
9948
9949             aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(aco_opcode::buffer_load_dword, Format::MUBUF, 3, 1)};
9950             mubuf->definitions[0] = bld.def(v1);
9951             mubuf->operands[0] = Operand(gsvs_ring);
9952             mubuf->operands[1] = Operand(voffset);
9953             mubuf->operands[2] = Operand(0u);
9954             mubuf->offen = true;
9955             mubuf->offset = const_offset;
9956             mubuf->glc = true;
9957             mubuf->slc = true;
9958             mubuf->dlc = args->options->chip_class >= GFX10;
9959             mubuf->barrier = barrier_none;
9960             mubuf->can_reorder = true;
9961
9962             ctx.outputs.mask[i] |= 1 << j;
9963             ctx.outputs.temps[i * 4u + j] = mubuf->definitions[0].getTemp();
9964
9965             bld.insert(std::move(mubuf));
9966
9967             offset++;
9968          }
9969       }
9970
9971       if (args->shader_info->so.num_outputs) {
9972          emit_streamout(&ctx, stream);
9973          bld.reset(ctx.block);
9974       }
9975
9976       if (stream == 0) {
9977          create_vs_exports(&ctx);
9978          ctx.block->kind |= block_kind_export_end;
9979       }
9980
9981       if (!stream_id.isConstant()) {
9982          append_logical_end(ctx.block);
9983
9984          /* branch from then block to endif block */
9985          bld.branch(aco_opcode::p_branch);
9986          add_edge(ctx.block->index, &BB_endif);
9987          ctx.block->kind |= block_kind_uniform;
9988
9989          /* emit else block */
9990          ctx.block = ctx.program->create_and_insert_block();
9991          add_edge(BB_if_idx, ctx.block);
9992          bld.reset(ctx.block);
9993          append_logical_start(ctx.block);
9994
9995          endif_blocks.push(std::move(BB_endif));
9996       }
9997    }
9998
9999    while (!endif_blocks.empty()) {
10000       Block BB_endif = std::move(endif_blocks.top());
10001       endif_blocks.pop();
10002
10003       Block *BB_else = ctx.block;
10004
10005       append_logical_end(BB_else);
10006       /* branch from else block to endif block */
10007       bld.branch(aco_opcode::p_branch);
10008       add_edge(BB_else->index, &BB_endif);
10009       BB_else->kind |= block_kind_uniform;
10010
10011       /** emit endif merge block */
10012       ctx.block = program->insert_block(std::move(BB_endif));
10013       bld.reset(ctx.block);
10014       append_logical_start(ctx.block);
10015    }
10016
10017    program->config->float_mode = program->blocks[0].fp_mode.val;
10018
10019    append_logical_end(ctx.block);
10020    ctx.block->kind |= block_kind_uniform;
10021    bld.sopp(aco_opcode::s_endpgm);
10022
10023    cleanup_cfg(program);
10024 }
10025 }