src/amd/compiler/aco_instruction_selection.cpp

   1 /*
   2  * Copyright © 2018 Valve Corporation
   3  * Copyright © 2018 Google
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <algorithm>
  27 #include <array>
  28 #include <stack>
  29 #include <map>
  30
  31 #include "ac_shader_util.h"
  32 #include "aco_ir.h"
  33 #include "aco_builder.h"
  34 #include "aco_interface.h"
  35 #include "aco_instruction_selection_setup.cpp"
  36 #include "util/fast_idiv_by_const.h"
  37
  38 namespace aco {
  39 namespace {
  40
  41 class loop_info_RAII {
  42    isel_context* ctx;
  43    unsigned header_idx_old;
  44    Block* exit_old;
  45    bool divergent_cont_old;
  46    bool divergent_branch_old;
  47    bool divergent_if_old;
  48
  49 public:
  50    loop_info_RAII(isel_context* ctx, unsigned loop_header_idx, Block* loop_exit)
  51       : ctx(ctx),
  52         header_idx_old(ctx->cf_info.parent_loop.header_idx), exit_old(ctx->cf_info.parent_loop.exit),
  53         divergent_cont_old(ctx->cf_info.parent_loop.has_divergent_continue),
  54         divergent_branch_old(ctx->cf_info.parent_loop.has_divergent_branch),
  55         divergent_if_old(ctx->cf_info.parent_if.is_divergent)
  56    {
  57       ctx->cf_info.parent_loop.header_idx = loop_header_idx;
  58       ctx->cf_info.parent_loop.exit = loop_exit;
  59       ctx->cf_info.parent_loop.has_divergent_continue = false;
  60       ctx->cf_info.parent_loop.has_divergent_branch = false;
  61       ctx->cf_info.parent_if.is_divergent = false;
  62       ctx->cf_info.loop_nest_depth = ctx->cf_info.loop_nest_depth + 1;
  63    }
  64
  65    ~loop_info_RAII()
  66    {
  67       ctx->cf_info.parent_loop.header_idx = header_idx_old;
  68       ctx->cf_info.parent_loop.exit = exit_old;
  69       ctx->cf_info.parent_loop.has_divergent_continue = divergent_cont_old;
  70       ctx->cf_info.parent_loop.has_divergent_branch = divergent_branch_old;
  71       ctx->cf_info.parent_if.is_divergent = divergent_if_old;
  72       ctx->cf_info.loop_nest_depth = ctx->cf_info.loop_nest_depth - 1;
  73       if (!ctx->cf_info.loop_nest_depth && !ctx->cf_info.parent_if.is_divergent)
  74          ctx->cf_info.exec_potentially_empty_discard = false;
  75    }
  76 };
  77
  78 struct if_context {
  79    Temp cond;
  80
  81    bool divergent_old;
  82    bool exec_potentially_empty_discard_old;
  83    bool exec_potentially_empty_break_old;
  84    uint16_t exec_potentially_empty_break_depth_old;
  85
  86    unsigned BB_if_idx;
  87    unsigned invert_idx;
  88    bool then_branch_divergent;
  89    Block BB_invert;
  90    Block BB_endif;
  91 };
  92
  93 static void visit_cf_list(struct isel_context *ctx,
  94                           struct exec_list *list);
  95
  96 static void add_logical_edge(unsigned pred_idx, Block *succ)
  97 {
  98    succ->logical_preds.emplace_back(pred_idx);
  99 }
 100
 101
 102 static void add_linear_edge(unsigned pred_idx, Block *succ)
 103 {
 104    succ->linear_preds.emplace_back(pred_idx);
 105 }
 106
 107 static void add_edge(unsigned pred_idx, Block *succ)
 108 {
 109    add_logical_edge(pred_idx, succ);
 110    add_linear_edge(pred_idx, succ);
 111 }
 112
 113 static void append_logical_start(Block *b)
 114 {
 115    Builder(NULL, b).pseudo(aco_opcode::p_logical_start);
 116 }
 117
 118 static void append_logical_end(Block *b)
 119 {
 120    Builder(NULL, b).pseudo(aco_opcode::p_logical_end);
 121 }
 122
 123 Temp get_ssa_temp(struct isel_context *ctx, nir_ssa_def *def)
 124 {
 125    assert(ctx->allocated[def->index].id());
 126    return ctx->allocated[def->index];
 127 }
 128
 129 Temp emit_mbcnt(isel_context *ctx, Definition dst,
 130                 Operand mask_lo = Operand((uint32_t) -1), Operand mask_hi = Operand((uint32_t) -1))
 131 {
 132    Builder bld(ctx->program, ctx->block);
 133    Definition lo_def = ctx->program->wave_size == 32 ? dst : bld.def(v1);
 134    Temp thread_id_lo = bld.vop3(aco_opcode::v_mbcnt_lo_u32_b32, lo_def, mask_lo, Operand(0u));
 135
 136    if (ctx->program->wave_size == 32) {
 137       return thread_id_lo;
 138    } else {
 139       Temp thread_id_hi = bld.vop3(aco_opcode::v_mbcnt_hi_u32_b32, dst, mask_hi, thread_id_lo);
 140       return thread_id_hi;
 141    }
 142 }
 143
 144 Temp emit_wqm(isel_context *ctx, Temp src, Temp dst=Temp(0, s1), bool program_needs_wqm = false)
 145 {
 146    Builder bld(ctx->program, ctx->block);
 147
 148    if (!dst.id())
 149       dst = bld.tmp(src.regClass());
 150
 151    assert(src.size() == dst.size());
 152
 153    if (ctx->stage != fragment_fs) {
 154       if (!dst.id())
 155          return src;
 156
 157       bld.copy(Definition(dst), src);
 158       return dst;
 159    }
 160
 161    bld.pseudo(aco_opcode::p_wqm, Definition(dst), src);
 162    ctx->program->needs_wqm |= program_needs_wqm;
 163    return dst;
 164 }
 165
 166 static Temp emit_bpermute(isel_context *ctx, Builder &bld, Temp index, Temp data)
 167 {
 168    if (index.regClass() == s1)
 169       return bld.readlane(bld.def(s1), data, index);
 170
 171    Temp index_x4 = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), index);
 172
 173    /* Currently not implemented on GFX6-7 */
 174    assert(ctx->options->chip_class >= GFX8);
 175
 176    if (ctx->options->chip_class <= GFX9 || ctx->program->wave_size == 32) {
 177       return bld.ds(aco_opcode::ds_bpermute_b32, bld.def(v1), index_x4, data);
 178    }
 179
 180    /* GFX10, wave64 mode:
 181     * The bpermute instruction is limited to half-wave operation, which means that it can't
 182     * properly support subgroup shuffle like older generations (or wave32 mode), so we
 183     * emulate it here.
 184     */
 185    if (!ctx->has_gfx10_wave64_bpermute) {
 186       ctx->has_gfx10_wave64_bpermute = true;
 187       ctx->program->config->num_shared_vgprs = 8; /* Shared VGPRs are allocated in groups of 8 */
 188       ctx->program->vgpr_limit -= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
 189    }
 190
 191    Temp lane_id = emit_mbcnt(ctx, bld.def(v1));
 192    Temp lane_is_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x20u), lane_id);
 193    Temp index_is_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x20u), index);
 194    Temp cmp = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm, vcc), lane_is_hi, index_is_hi);
 195
 196    return bld.reduction(aco_opcode::p_wave64_bpermute, bld.def(v1), bld.def(s2), bld.def(s1, scc),
 197                         bld.vcc(cmp), Operand(v2.as_linear()), index_x4, data, gfx10_wave64_bpermute);
 198 }
 199
 200 Temp as_vgpr(isel_context *ctx, Temp val)
 201 {
 202    if (val.type() == RegType::sgpr) {
 203       Builder bld(ctx->program, ctx->block);
 204       return bld.copy(bld.def(RegType::vgpr, val.size()), val);
 205    }
 206    assert(val.type() == RegType::vgpr);
 207    return val;
 208 }
 209
 210 //assumes a != 0xffffffff
 211 void emit_v_div_u32(isel_context *ctx, Temp dst, Temp a, uint32_t b)
 212 {
 213    assert(b != 0);
 214    Builder bld(ctx->program, ctx->block);
 215
 216    if (util_is_power_of_two_or_zero(b)) {
 217       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(dst), Operand((uint32_t)util_logbase2(b)), a);
 218       return;
 219    }
 220
 221    util_fast_udiv_info info = util_compute_fast_udiv_info(b, 32, 32);
 222
 223    assert(info.multiplier <= 0xffffffff);
 224
 225    bool pre_shift = info.pre_shift != 0;
 226    bool increment = info.increment != 0;
 227    bool multiply = true;
 228    bool post_shift = info.post_shift != 0;
 229
 230    if (!pre_shift && !increment && !multiply && !post_shift) {
 231       bld.vop1(aco_opcode::v_mov_b32, Definition(dst), a);
 232       return;
 233    }
 234
 235    Temp pre_shift_dst = a;
 236    if (pre_shift) {
 237       pre_shift_dst = (increment || multiply || post_shift) ? bld.tmp(v1) : dst;
 238       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(pre_shift_dst), Operand((uint32_t)info.pre_shift), a);
 239    }
 240
 241    Temp increment_dst = pre_shift_dst;
 242    if (increment) {
 243       increment_dst = (post_shift || multiply) ? bld.tmp(v1) : dst;
 244       bld.vadd32(Definition(increment_dst), Operand((uint32_t) info.increment), pre_shift_dst);
 245    }
 246
 247    Temp multiply_dst = increment_dst;
 248    if (multiply) {
 249       multiply_dst = post_shift ? bld.tmp(v1) : dst;
 250       bld.vop3(aco_opcode::v_mul_hi_u32, Definition(multiply_dst), increment_dst,
 251                bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand((uint32_t)info.multiplier)));
 252    }
 253
 254    if (post_shift) {
 255       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(dst), Operand((uint32_t)info.post_shift), multiply_dst);
 256    }
 257 }
 258
 259 void emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, Temp dst)
 260 {
 261    Builder bld(ctx->program, ctx->block);
 262    bld.pseudo(aco_opcode::p_extract_vector, Definition(dst), src, Operand(idx));
 263 }
 264
 265
 266 Temp emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, RegClass dst_rc)
 267 {
 268    /* no need to extract the whole vector */
 269    if (src.regClass() == dst_rc) {
 270       assert(idx == 0);
 271       return src;
 272    }
 273    assert(src.size() > idx);
 274    Builder bld(ctx->program, ctx->block);
 275    auto it = ctx->allocated_vec.find(src.id());
 276    /* the size check needs to be early because elements other than 0 may be garbage */
 277    if (it != ctx->allocated_vec.end() && it->second[0].size() == dst_rc.size()) {
 278       if (it->second[idx].regClass() == dst_rc) {
 279          return it->second[idx];
 280       } else {
 281          assert(dst_rc.size() == it->second[idx].regClass().size());
 282          assert(dst_rc.type() == RegType::vgpr && it->second[idx].type() == RegType::sgpr);
 283          return bld.copy(bld.def(dst_rc), it->second[idx]);
 284       }
 285    }
 286
 287    if (src.size() == dst_rc.size()) {
 288       assert(idx == 0);
 289       return bld.copy(bld.def(dst_rc), src);
 290    } else {
 291       Temp dst = bld.tmp(dst_rc);
 292       emit_extract_vector(ctx, src, idx, dst);
 293       return dst;
 294    }
 295 }
 296
 297 void emit_split_vector(isel_context* ctx, Temp vec_src, unsigned num_components)
 298 {
 299    if (num_components == 1)
 300       return;
 301    if (ctx->allocated_vec.find(vec_src.id()) != ctx->allocated_vec.end())
 302       return;
 303    aco_ptr<Pseudo_instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector, Format::PSEUDO, 1, num_components)};
 304    split->operands[0] = Operand(vec_src);
 305    std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 306    for (unsigned i = 0; i < num_components; i++) {
 307       elems[i] = {ctx->program->allocateId(), RegClass(vec_src.type(), vec_src.size() / num_components)};
 308       split->definitions[i] = Definition(elems[i]);
 309    }
 310    ctx->block->instructions.emplace_back(std::move(split));
 311    ctx->allocated_vec.emplace(vec_src.id(), elems);
 312 }
 313
 314 /* This vector expansion uses a mask to determine which elements in the new vector
 315  * come from the original vector. The other elements are undefined. */
 316 void expand_vector(isel_context* ctx, Temp vec_src, Temp dst, unsigned num_components, unsigned mask)
 317 {
 318    emit_split_vector(ctx, vec_src, util_bitcount(mask));
 319
 320    if (vec_src == dst)
 321       return;
 322
 323    Builder bld(ctx->program, ctx->block);
 324    if (num_components == 1) {
 325       if (dst.type() == RegType::sgpr)
 326          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec_src);
 327       else
 328          bld.copy(Definition(dst), vec_src);
 329       return;
 330    }
 331
 332    unsigned component_size = dst.size() / num_components;
 333    std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 334
 335    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1)};
 336    vec->definitions[0] = Definition(dst);
 337    unsigned k = 0;
 338    for (unsigned i = 0; i < num_components; i++) {
 339       if (mask & (1 << i)) {
 340          Temp src = emit_extract_vector(ctx, vec_src, k++, RegClass(vec_src.type(), component_size));
 341          if (dst.type() == RegType::sgpr)
 342             src = bld.as_uniform(src);
 343          vec->operands[i] = Operand(src);
 344       } else {
 345          vec->operands[i] = Operand(0u);
 346       }
 347       elems[i] = vec->operands[i].getTemp();
 348    }
 349    ctx->block->instructions.emplace_back(std::move(vec));
 350    ctx->allocated_vec.emplace(dst.id(), elems);
 351 }
 352
 353 Temp bool_to_vector_condition(isel_context *ctx, Temp val, Temp dst = Temp(0, s2))
 354 {
 355    Builder bld(ctx->program, ctx->block);
 356    if (!dst.id())
 357       dst = bld.tmp(bld.lm);
 358
 359    assert(val.regClass() == s1);
 360    assert(dst.regClass() == bld.lm);
 361
 362    return bld.sop2(Builder::s_cselect, Definition(dst), Operand((uint32_t) -1), Operand(0u), bld.scc(val));
 363 }
 364
 365 Temp bool_to_scalar_condition(isel_context *ctx, Temp val, Temp dst = Temp(0, s1))
 366 {
 367    Builder bld(ctx->program, ctx->block);
 368    if (!dst.id())
 369       dst = bld.tmp(s1);
 370
 371    assert(val.regClass() == bld.lm);
 372    assert(dst.regClass() == s1);
 373
 374    /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
 375    Temp tmp = bld.tmp(s1);
 376    bld.sop2(Builder::s_and, bld.def(bld.lm), bld.scc(Definition(tmp)), val, Operand(exec, bld.lm));
 377    return emit_wqm(ctx, tmp, dst);
 378 }
 379
 380 Temp get_alu_src(struct isel_context *ctx, nir_alu_src src, unsigned size=1)
 381 {
 382    if (src.src.ssa->num_components == 1 && src.swizzle[0] == 0 && size == 1)
 383       return get_ssa_temp(ctx, src.src.ssa);
 384
 385    if (src.src.ssa->num_components == size) {
 386       bool identity_swizzle = true;
 387       for (unsigned i = 0; identity_swizzle && i < size; i++) {
 388          if (src.swizzle[i] != i)
 389             identity_swizzle = false;
 390       }
 391       if (identity_swizzle)
 392          return get_ssa_temp(ctx, src.src.ssa);
 393    }
 394
 395    Temp vec = get_ssa_temp(ctx, src.src.ssa);
 396    unsigned elem_size = vec.size() / src.src.ssa->num_components;
 397    assert(elem_size > 0); /* TODO: 8 and 16-bit vectors not supported */
 398    assert(vec.size() % elem_size == 0);
 399
 400    RegClass elem_rc = RegClass(vec.type(), elem_size);
 401    if (size == 1) {
 402       return emit_extract_vector(ctx, vec, src.swizzle[0], elem_rc);
 403    } else {
 404       assert(size <= 4);
 405       std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 406       aco_ptr<Pseudo_instruction> vec_instr{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, size, 1)};
 407       for (unsigned i = 0; i < size; ++i) {
 408          elems[i] = emit_extract_vector(ctx, vec, src.swizzle[i], elem_rc);
 409          vec_instr->operands[i] = Operand{elems[i]};
 410       }
 411       Temp dst{ctx->program->allocateId(), RegClass(vec.type(), elem_size * size)};
 412       vec_instr->definitions[0] = Definition(dst);
 413       ctx->block->instructions.emplace_back(std::move(vec_instr));
 414       ctx->allocated_vec.emplace(dst.id(), elems);
 415       return dst;
 416    }
 417 }
 418
 419 Temp convert_pointer_to_64_bit(isel_context *ctx, Temp ptr)
 420 {
 421    if (ptr.size() == 2)
 422       return ptr;
 423    Builder bld(ctx->program, ctx->block);
 424    if (ptr.type() == RegType::vgpr)
 425       ptr = bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), ptr);
 426    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s2),
 427                      ptr, Operand((unsigned)ctx->options->address32_hi));
 428 }
 429
 430 void emit_sop2_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst, bool writes_scc)
 431 {
 432    aco_ptr<SOP2_instruction> sop2{create_instruction<SOP2_instruction>(op, Format::SOP2, 2, writes_scc ? 2 : 1)};
 433    sop2->operands[0] = Operand(get_alu_src(ctx, instr->src[0]));
 434    sop2->operands[1] = Operand(get_alu_src(ctx, instr->src[1]));
 435    sop2->definitions[0] = Definition(dst);
 436    if (writes_scc)
 437       sop2->definitions[1] = Definition(ctx->program->allocateId(), scc, s1);
 438    ctx->block->instructions.emplace_back(std::move(sop2));
 439 }
 440
 441 void emit_vop2_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst,
 442                            bool commutative, bool swap_srcs=false, bool flush_denorms = false)
 443 {
 444    Builder bld(ctx->program, ctx->block);
 445    Temp src0 = get_alu_src(ctx, instr->src[swap_srcs ? 1 : 0]);
 446    Temp src1 = get_alu_src(ctx, instr->src[swap_srcs ? 0 : 1]);
 447    if (src1.type() == RegType::sgpr) {
 448       if (commutative && src0.type() == RegType::vgpr) {
 449          Temp t = src0;
 450          src0 = src1;
 451          src1 = t;
 452       } else if (src0.type() == RegType::vgpr &&
 453                  op != aco_opcode::v_madmk_f32 &&
 454                  op != aco_opcode::v_madak_f32 &&
 455                  op != aco_opcode::v_madmk_f16 &&
 456                  op != aco_opcode::v_madak_f16) {
 457          /* If the instruction is not commutative, we emit a VOP3A instruction */
 458          bld.vop2_e64(op, Definition(dst), src0, src1);
 459          return;
 460       } else {
 461          src1 = bld.copy(bld.def(RegType::vgpr, src1.size()), src1); //TODO: as_vgpr
 462       }
 463    }
 464
 465    if (flush_denorms && ctx->program->chip_class < GFX9) {
 466       assert(dst.size() == 1);
 467       Temp tmp = bld.vop2(op, bld.def(v1), src0, src1);
 468       bld.vop2(aco_opcode::v_mul_f32, Definition(dst), Operand(0x3f800000u), tmp);
 469    } else {
 470       bld.vop2(op, Definition(dst), src0, src1);
 471    }
 472 }
 473
 474 void emit_vop3a_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst,
 475                             bool flush_denorms = false)
 476 {
 477    Temp src0 = get_alu_src(ctx, instr->src[0]);
 478    Temp src1 = get_alu_src(ctx, instr->src[1]);
 479    Temp src2 = get_alu_src(ctx, instr->src[2]);
 480
 481    /* ensure that the instruction has at most 1 sgpr operand
 482     * The optimizer will inline constants for us */
 483    if (src0.type() == RegType::sgpr && src1.type() == RegType::sgpr)
 484       src0 = as_vgpr(ctx, src0);
 485    if (src1.type() == RegType::sgpr && src2.type() == RegType::sgpr)
 486       src1 = as_vgpr(ctx, src1);
 487    if (src2.type() == RegType::sgpr && src0.type() == RegType::sgpr)
 488       src2 = as_vgpr(ctx, src2);
 489
 490    Builder bld(ctx->program, ctx->block);
 491    if (flush_denorms && ctx->program->chip_class < GFX9) {
 492       assert(dst.size() == 1);
 493       Temp tmp = bld.vop3(op, Definition(dst), src0, src1, src2);
 494       bld.vop2(aco_opcode::v_mul_f32, Definition(dst), Operand(0x3f800000u), tmp);
 495    } else {
 496       bld.vop3(op, Definition(dst), src0, src1, src2);
 497    }
 498 }
 499
 500 void emit_vop1_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 501 {
 502    Builder bld(ctx->program, ctx->block);
 503    bld.vop1(op, Definition(dst), get_alu_src(ctx, instr->src[0]));
 504 }
 505
 506 void emit_vopc_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 507 {
 508    Temp src0 = get_alu_src(ctx, instr->src[0]);
 509    Temp src1 = get_alu_src(ctx, instr->src[1]);
 510    assert(src0.size() == src1.size());
 511
 512    aco_ptr<Instruction> vopc;
 513    if (src1.type() == RegType::sgpr) {
 514       if (src0.type() == RegType::vgpr) {
 515          /* to swap the operands, we might also have to change the opcode */
 516          switch (op) {
 517             case aco_opcode::v_cmp_lt_f32:
 518                op = aco_opcode::v_cmp_gt_f32;
 519                break;
 520             case aco_opcode::v_cmp_ge_f32:
 521                op = aco_opcode::v_cmp_le_f32;
 522                break;
 523             case aco_opcode::v_cmp_lt_i32:
 524                op = aco_opcode::v_cmp_gt_i32;
 525                break;
 526             case aco_opcode::v_cmp_ge_i32:
 527                op = aco_opcode::v_cmp_le_i32;
 528                break;
 529             case aco_opcode::v_cmp_lt_u32:
 530                op = aco_opcode::v_cmp_gt_u32;
 531                break;
 532             case aco_opcode::v_cmp_ge_u32:
 533                op = aco_opcode::v_cmp_le_u32;
 534                break;
 535             case aco_opcode::v_cmp_lt_f64:
 536                op = aco_opcode::v_cmp_gt_f64;
 537                break;
 538             case aco_opcode::v_cmp_ge_f64:
 539                op = aco_opcode::v_cmp_le_f64;
 540                break;
 541             case aco_opcode::v_cmp_lt_i64:
 542                op = aco_opcode::v_cmp_gt_i64;
 543                break;
 544             case aco_opcode::v_cmp_ge_i64:
 545                op = aco_opcode::v_cmp_le_i64;
 546                break;
 547             case aco_opcode::v_cmp_lt_u64:
 548                op = aco_opcode::v_cmp_gt_u64;
 549                break;
 550             case aco_opcode::v_cmp_ge_u64:
 551                op = aco_opcode::v_cmp_le_u64;
 552                break;
 553             default: /* eq and ne are commutative */
 554                break;
 555          }
 556          Temp t = src0;
 557          src0 = src1;
 558          src1 = t;
 559       } else {
 560          src1 = as_vgpr(ctx, src1);
 561       }
 562    }
 563
 564    Builder bld(ctx->program, ctx->block);
 565    bld.vopc(op, bld.hint_vcc(Definition(dst)), src0, src1);
 566 }
 567
 568 void emit_sopc_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 569 {
 570    Temp src0 = get_alu_src(ctx, instr->src[0]);
 571    Temp src1 = get_alu_src(ctx, instr->src[1]);
 572    Builder bld(ctx->program, ctx->block);
 573
 574    assert(dst.regClass() == bld.lm);
 575    assert(src0.type() == RegType::sgpr);
 576    assert(src1.type() == RegType::sgpr);
 577    assert(src0.regClass() == src1.regClass());
 578
 579    /* Emit the SALU comparison instruction */
 580    Temp cmp = bld.sopc(op, bld.scc(bld.def(s1)), src0, src1);
 581    /* Turn the result into a per-lane bool */
 582    bool_to_vector_condition(ctx, cmp, dst);
 583 }
 584
 585 void emit_comparison(isel_context *ctx, nir_alu_instr *instr, Temp dst,
 586                      aco_opcode v32_op, aco_opcode v64_op, aco_opcode s32_op = aco_opcode::num_opcodes, aco_opcode s64_op = aco_opcode::num_opcodes)
 587 {
 588    aco_opcode s_op = instr->src[0].src.ssa->bit_size == 64 ? s64_op : s32_op;
 589    aco_opcode v_op = instr->src[0].src.ssa->bit_size == 64 ? v64_op : v32_op;
 590    bool divergent_vals = ctx->divergent_vals[instr->dest.dest.ssa.index];
 591    bool use_valu = s_op == aco_opcode::num_opcodes ||
 592                    divergent_vals ||
 593                    ctx->allocated[instr->src[0].src.ssa->index].type() == RegType::vgpr ||
 594                    ctx->allocated[instr->src[1].src.ssa->index].type() == RegType::vgpr;
 595    aco_opcode op = use_valu ? v_op : s_op;
 596    assert(op != aco_opcode::num_opcodes);
 597    assert(dst.regClass() == ctx->program->lane_mask);
 598
 599    if (use_valu)
 600       emit_vopc_instruction(ctx, instr, op, dst);
 601    else
 602       emit_sopc_instruction(ctx, instr, op, dst);
 603 }
 604
 605 void emit_boolean_logic(isel_context *ctx, nir_alu_instr *instr, Builder::WaveSpecificOpcode op, Temp dst)
 606 {
 607    Builder bld(ctx->program, ctx->block);
 608    Temp src0 = get_alu_src(ctx, instr->src[0]);
 609    Temp src1 = get_alu_src(ctx, instr->src[1]);
 610
 611    assert(dst.regClass() == bld.lm);
 612    assert(src0.regClass() == bld.lm);
 613    assert(src1.regClass() == bld.lm);
 614
 615    bld.sop2(op, Definition(dst), bld.def(s1, scc), src0, src1);
 616 }
 617
 618 void emit_bcsel(isel_context *ctx, nir_alu_instr *instr, Temp dst)
 619 {
 620    Builder bld(ctx->program, ctx->block);
 621    Temp cond = get_alu_src(ctx, instr->src[0]);
 622    Temp then = get_alu_src(ctx, instr->src[1]);
 623    Temp els = get_alu_src(ctx, instr->src[2]);
 624
 625    assert(cond.regClass() == bld.lm);
 626
 627    if (dst.type() == RegType::vgpr) {
 628       aco_ptr<Instruction> bcsel;
 629       if (dst.size() == 1) {
 630          then = as_vgpr(ctx, then);
 631          els = as_vgpr(ctx, els);
 632
 633          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), els, then, cond);
 634       } else if (dst.size() == 2) {
 635          Temp then_lo = bld.tmp(v1), then_hi = bld.tmp(v1);
 636          bld.pseudo(aco_opcode::p_split_vector, Definition(then_lo), Definition(then_hi), then);
 637          Temp else_lo = bld.tmp(v1), else_hi = bld.tmp(v1);
 638          bld.pseudo(aco_opcode::p_split_vector, Definition(else_lo), Definition(else_hi), els);
 639
 640          Temp dst0 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_lo, then_lo, cond);
 641          Temp dst1 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_hi, then_hi, cond);
 642
 643          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
 644       } else {
 645          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 646          nir_print_instr(&instr->instr, stderr);
 647          fprintf(stderr, "\n");
 648       }
 649       return;
 650    }
 651
 652    if (instr->dest.dest.ssa.bit_size == 1) {
 653       assert(dst.regClass() == bld.lm);
 654       assert(then.regClass() == bld.lm);
 655       assert(els.regClass() == bld.lm);
 656    }
 657
 658    if (!ctx->divergent_vals[instr->src[0].src.ssa->index]) { /* uniform condition and values in sgpr */
 659       if (dst.regClass() == s1 || dst.regClass() == s2) {
 660          assert((then.regClass() == s1 || then.regClass() == s2) && els.regClass() == then.regClass());
 661          assert(dst.size() == then.size());
 662          aco_opcode op = dst.regClass() == s1 ? aco_opcode::s_cselect_b32 : aco_opcode::s_cselect_b64;
 663          bld.sop2(op, Definition(dst), then, els, bld.scc(bool_to_scalar_condition(ctx, cond)));
 664       } else {
 665          fprintf(stderr, "Unimplemented uniform bcsel bit size: ");
 666          nir_print_instr(&instr->instr, stderr);
 667          fprintf(stderr, "\n");
 668       }
 669       return;
 670    }
 671
 672    /* divergent boolean bcsel
 673     * this implements bcsel on bools: dst = s0 ? s1 : s2
 674     * are going to be: dst = (s0 & s1) | (~s0 & s2) */
 675    assert(instr->dest.dest.ssa.bit_size == 1);
 676
 677    if (cond.id() != then.id())
 678       then = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), cond, then);
 679
 680    if (cond.id() == els.id())
 681       bld.sop1(Builder::s_mov, Definition(dst), then);
 682    else
 683       bld.sop2(Builder::s_or, Definition(dst), bld.def(s1, scc), then,
 684                bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), els, cond));
 685 }
 686
 687 void emit_scaled_op(isel_context *ctx, Builder& bld, Definition dst, Temp val,
 688                     aco_opcode op, uint32_t undo)
 689 {
 690    /* multiply by 16777216 to handle denormals */
 691    Temp is_denormal = bld.vopc(aco_opcode::v_cmp_class_f32, bld.hint_vcc(bld.def(bld.lm)),
 692                                as_vgpr(ctx, val), bld.copy(bld.def(v1), Operand((1u << 7) | (1u << 4))));
 693    Temp scaled = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x4b800000u), val);
 694    scaled = bld.vop1(op, bld.def(v1), scaled);
 695    scaled = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(undo), scaled);
 696
 697    Temp not_scaled = bld.vop1(op, bld.def(v1), val);
 698
 699    bld.vop2(aco_opcode::v_cndmask_b32, dst, not_scaled, scaled, is_denormal);
 700 }
 701
 702 void emit_rcp(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 703 {
 704    if (ctx->block->fp_mode.denorm32 == 0) {
 705       bld.vop1(aco_opcode::v_rcp_f32, dst, val);
 706       return;
 707    }
 708
 709    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_rcp_f32, 0x4b800000u);
 710 }
 711
 712 void emit_rsq(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 713 {
 714    if (ctx->block->fp_mode.denorm32 == 0) {
 715       bld.vop1(aco_opcode::v_rsq_f32, dst, val);
 716       return;
 717    }
 718
 719    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_rsq_f32, 0x45800000u);
 720 }
 721
 722 void emit_sqrt(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 723 {
 724    if (ctx->block->fp_mode.denorm32 == 0) {
 725       bld.vop1(aco_opcode::v_sqrt_f32, dst, val);
 726       return;
 727    }
 728
 729    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_sqrt_f32, 0x39800000u);
 730 }
 731
 732 void emit_log2(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 733 {
 734    if (ctx->block->fp_mode.denorm32 == 0) {
 735       bld.vop1(aco_opcode::v_log_f32, dst, val);
 736       return;
 737    }
 738
 739    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_log_f32, 0xc1c00000u);
 740 }
 741
 742 Temp emit_trunc_f64(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 743 {
 744    if (ctx->options->chip_class >= GFX7)
 745       return bld.vop1(aco_opcode::v_trunc_f64, Definition(dst), val);
 746
 747    /* GFX6 doesn't support V_TRUNC_F64, lower it. */
 748    /* TODO: create more efficient code! */
 749    if (val.type() == RegType::sgpr)
 750       val = as_vgpr(ctx, val);
 751
 752    /* Split the input value. */
 753    Temp val_lo = bld.tmp(v1), val_hi = bld.tmp(v1);
 754    bld.pseudo(aco_opcode::p_split_vector, Definition(val_lo), Definition(val_hi), val);
 755
 756    /* Extract the exponent and compute the unbiased value. */
 757    Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f64, bld.def(v1), val);
 758
 759    /* Extract the fractional part. */
 760    Temp fract_mask = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(-1u), Operand(0x000fffffu));
 761    fract_mask = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), fract_mask, exponent);
 762
 763    Temp fract_mask_lo = bld.tmp(v1), fract_mask_hi = bld.tmp(v1);
 764    bld.pseudo(aco_opcode::p_split_vector, Definition(fract_mask_lo), Definition(fract_mask_hi), fract_mask);
 765
 766    Temp fract_lo = bld.tmp(v1), fract_hi = bld.tmp(v1);
 767    Temp tmp = bld.vop1(aco_opcode::v_not_b32, bld.def(v1), fract_mask_lo);
 768    fract_lo = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), val_lo, tmp);
 769    tmp = bld.vop1(aco_opcode::v_not_b32, bld.def(v1), fract_mask_hi);
 770    fract_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), val_hi, tmp);
 771
 772    /* Get the sign bit. */
 773    Temp sign = bld.vop2(aco_opcode::v_ashr_i32, bld.def(v1), Operand(31u), val_hi);
 774
 775    /* Decide the operation to apply depending on the unbiased exponent. */
 776    Temp exp_lt0 = bld.vopc_e64(aco_opcode::v_cmp_lt_i32, bld.hint_vcc(bld.def(bld.lm)), exponent, Operand(0u));
 777    Temp dst_lo = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), fract_lo, bld.copy(bld.def(v1), Operand(0u)), exp_lt0);
 778    Temp dst_hi = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), fract_hi, sign, exp_lt0);
 779    Temp exp_gt51 = bld.vopc_e64(aco_opcode::v_cmp_gt_i32, bld.def(s2), exponent, Operand(51u));
 780    dst_lo = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), dst_lo, val_lo, exp_gt51);
 781    dst_hi = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), dst_hi, val_hi, exp_gt51);
 782
 783    return bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst_lo, dst_hi);
 784 }
 785
 786 Temp emit_floor_f64(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 787 {
 788    if (ctx->options->chip_class >= GFX7)
 789       return bld.vop1(aco_opcode::v_floor_f64, Definition(dst), val);
 790
 791    /* GFX6 doesn't support V_FLOOR_F64, lower it. */
 792    Temp src0 = as_vgpr(ctx, val);
 793
 794    Temp mask = bld.copy(bld.def(s1), Operand(3u)); /* isnan */
 795    Temp min_val = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(-1u), Operand(0x3fefffffu));
 796
 797    Temp isnan = bld.vopc_e64(aco_opcode::v_cmp_class_f64, bld.hint_vcc(bld.def(bld.lm)), src0, mask);
 798    Temp fract = bld.vop1(aco_opcode::v_fract_f64, bld.def(v2), src0);
 799    Temp min = bld.vop3(aco_opcode::v_min_f64, bld.def(v2), fract, min_val);
 800
 801    Temp then_lo = bld.tmp(v1), then_hi = bld.tmp(v1);
 802    bld.pseudo(aco_opcode::p_split_vector, Definition(then_lo), Definition(then_hi), src0);
 803    Temp else_lo = bld.tmp(v1), else_hi = bld.tmp(v1);
 804    bld.pseudo(aco_opcode::p_split_vector, Definition(else_lo), Definition(else_hi), min);
 805
 806    Temp dst0 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_lo, then_lo, isnan);
 807    Temp dst1 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_hi, then_hi, isnan);
 808
 809    Temp v = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), dst0, dst1);
 810
 811    Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst), src0, v);
 812    static_cast<VOP3A_instruction*>(add)->neg[1] = true;
 813
 814    return add->definitions[0].getTemp();
 815 }
 816
 817 void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
 818 {
 819    if (!instr->dest.dest.is_ssa) {
 820       fprintf(stderr, "nir alu dst not in ssa: ");
 821       nir_print_instr(&instr->instr, stderr);
 822       fprintf(stderr, "\n");
 823       abort();
 824    }
 825    Builder bld(ctx->program, ctx->block);
 826    Temp dst = get_ssa_temp(ctx, &instr->dest.dest.ssa);
 827    switch(instr->op) {
 828    case nir_op_vec2:
 829    case nir_op_vec3:
 830    case nir_op_vec4: {
 831       std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 832       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.dest.ssa.num_components, 1)};
 833       for (unsigned i = 0; i < instr->dest.dest.ssa.num_components; ++i) {
 834          elems[i] = get_alu_src(ctx, instr->src[i]);
 835          vec->operands[i] = Operand{elems[i]};
 836       }
 837       vec->definitions[0] = Definition(dst);
 838       ctx->block->instructions.emplace_back(std::move(vec));
 839       ctx->allocated_vec.emplace(dst.id(), elems);
 840       break;
 841    }
 842    case nir_op_mov: {
 843       Temp src = get_alu_src(ctx, instr->src[0]);
 844       aco_ptr<Instruction> mov;
 845       if (dst.type() == RegType::sgpr) {
 846          if (src.type() == RegType::vgpr)
 847             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), src);
 848          else if (src.regClass() == s1)
 849             bld.sop1(aco_opcode::s_mov_b32, Definition(dst), src);
 850          else if (src.regClass() == s2)
 851             bld.sop1(aco_opcode::s_mov_b64, Definition(dst), src);
 852          else
 853             unreachable("wrong src register class for nir_op_imov");
 854       } else if (dst.regClass() == v1) {
 855          bld.vop1(aco_opcode::v_mov_b32, Definition(dst), src);
 856       } else if (dst.regClass() == v2) {
 857          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src);
 858       } else {
 859          nir_print_instr(&instr->instr, stderr);
 860          unreachable("Should have been lowered to scalar.");
 861       }
 862       break;
 863    }
 864    case nir_op_inot: {
 865       Temp src = get_alu_src(ctx, instr->src[0]);
 866       if (instr->dest.dest.ssa.bit_size == 1) {
 867          assert(src.regClass() == bld.lm);
 868          assert(dst.regClass() == bld.lm);
 869          /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
 870          Temp tmp = bld.sop1(Builder::s_not, bld.def(bld.lm), bld.def(s1, scc), src);
 871          bld.sop2(Builder::s_and, Definition(dst), bld.def(s1, scc), tmp, Operand(exec, bld.lm));
 872       } else if (dst.regClass() == v1) {
 873          emit_vop1_instruction(ctx, instr, aco_opcode::v_not_b32, dst);
 874       } else if (dst.type() == RegType::sgpr) {
 875          aco_opcode opcode = dst.size() == 1 ? aco_opcode::s_not_b32 : aco_opcode::s_not_b64;
 876          bld.sop1(opcode, Definition(dst), bld.def(s1, scc), src);
 877       } else {
 878          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 879          nir_print_instr(&instr->instr, stderr);
 880          fprintf(stderr, "\n");
 881       }
 882       break;
 883    }
 884    case nir_op_ineg: {
 885       Temp src = get_alu_src(ctx, instr->src[0]);
 886       if (dst.regClass() == v1) {
 887          bld.vsub32(Definition(dst), Operand(0u), Operand(src));
 888       } else if (dst.regClass() == s1) {
 889          bld.sop2(aco_opcode::s_mul_i32, Definition(dst), Operand((uint32_t) -1), src);
 890       } else if (dst.size() == 2) {
 891          Temp src0 = bld.tmp(dst.type(), 1);
 892          Temp src1 = bld.tmp(dst.type(), 1);
 893          bld.pseudo(aco_opcode::p_split_vector, Definition(src0), Definition(src1), src);
 894
 895          if (dst.regClass() == s2) {
 896             Temp carry = bld.tmp(s1);
 897             Temp dst0 = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(carry)), Operand(0u), src0);
 898             Temp dst1 = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), src1, carry);
 899             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
 900          } else {
 901             Temp lower = bld.tmp(v1);
 902             Temp borrow = bld.vsub32(Definition(lower), Operand(0u), src0, true).def(1).getTemp();
 903             Temp upper = bld.vsub32(bld.def(v1), Operand(0u), src1, false, borrow);
 904             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
 905          }
 906       } else {
 907          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 908          nir_print_instr(&instr->instr, stderr);
 909          fprintf(stderr, "\n");
 910       }
 911       break;
 912    }
 913    case nir_op_iabs: {
 914       if (dst.regClass() == s1) {
 915          bld.sop1(aco_opcode::s_abs_i32, Definition(dst), bld.def(s1, scc), get_alu_src(ctx, instr->src[0]));
 916       } else if (dst.regClass() == v1) {
 917          Temp src = get_alu_src(ctx, instr->src[0]);
 918          bld.vop2(aco_opcode::v_max_i32, Definition(dst), src, bld.vsub32(bld.def(v1), Operand(0u), src));
 919       } else {
 920          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 921          nir_print_instr(&instr->instr, stderr);
 922          fprintf(stderr, "\n");
 923       }
 924       break;
 925    }
 926    case nir_op_isign: {
 927       Temp src = get_alu_src(ctx, instr->src[0]);
 928       if (dst.regClass() == s1) {
 929          Temp tmp = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
 930          Temp gtz = bld.sopc(aco_opcode::s_cmp_gt_i32, bld.def(s1, scc), src, Operand(0u));
 931          bld.sop2(aco_opcode::s_add_i32, Definition(dst), bld.def(s1, scc), gtz, tmp);
 932       } else if (dst.regClass() == s2) {
 933          Temp neg = bld.sop2(aco_opcode::s_ashr_i64, bld.def(s2), bld.def(s1, scc), src, Operand(63u));
 934          Temp neqz;
 935          if (ctx->program->chip_class >= GFX8)
 936             neqz = bld.sopc(aco_opcode::s_cmp_lg_u64, bld.def(s1, scc), src, Operand(0u));
 937          else
 938             neqz = bld.sop2(aco_opcode::s_or_b64, bld.def(s2), bld.def(s1, scc), src, Operand(0u)).def(1).getTemp();
 939          /* SCC gets zero-extended to 64 bit */
 940          bld.sop2(aco_opcode::s_or_b64, Definition(dst), bld.def(s1, scc), neg, bld.scc(neqz));
 941       } else if (dst.regClass() == v1) {
 942          Temp tmp = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
 943          Temp gtz = bld.vopc(aco_opcode::v_cmp_ge_i32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
 944          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(1u), tmp, gtz);
 945       } else if (dst.regClass() == v2) {
 946          Temp upper = emit_extract_vector(ctx, src, 1, v1);
 947          Temp neg = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), upper);
 948          Temp gtz = bld.vopc(aco_opcode::v_cmp_ge_i64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
 949          Temp lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(1u), neg, gtz);
 950          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), neg, gtz);
 951          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
 952       } else {
 953          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 954          nir_print_instr(&instr->instr, stderr);
 955          fprintf(stderr, "\n");
 956       }
 957       break;
 958    }
 959    case nir_op_imax: {
 960       if (dst.regClass() == v1) {
 961          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_i32, dst, true);
 962       } else if (dst.regClass() == s1) {
 963          emit_sop2_instruction(ctx, instr, aco_opcode::s_max_i32, dst, true);
 964       } else {
 965          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 966          nir_print_instr(&instr->instr, stderr);
 967          fprintf(stderr, "\n");
 968       }
 969       break;
 970    }
 971    case nir_op_umax: {
 972       if (dst.regClass() == v1) {
 973          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_u32, dst, true);
 974       } else if (dst.regClass() == s1) {
 975          emit_sop2_instruction(ctx, instr, aco_opcode::s_max_u32, dst, true);
 976       } else {
 977          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 978          nir_print_instr(&instr->instr, stderr);
 979          fprintf(stderr, "\n");
 980       }
 981       break;
 982    }
 983    case nir_op_imin: {
 984       if (dst.regClass() == v1) {
 985          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_i32, dst, true);
 986       } else if (dst.regClass() == s1) {
 987          emit_sop2_instruction(ctx, instr, aco_opcode::s_min_i32, dst, true);
 988       } else {
 989          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 990          nir_print_instr(&instr->instr, stderr);
 991          fprintf(stderr, "\n");
 992       }
 993       break;
 994    }
 995    case nir_op_umin: {
 996       if (dst.regClass() == v1) {
 997          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_u32, dst, true);
 998       } else if (dst.regClass() == s1) {
 999          emit_sop2_instruction(ctx, instr, aco_opcode::s_min_u32, dst, true);
1000       } else {
1001          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1002          nir_print_instr(&instr->instr, stderr);
1003          fprintf(stderr, "\n");
1004       }
1005       break;
1006    }
1007    case nir_op_ior: {
1008       if (instr->dest.dest.ssa.bit_size == 1) {
1009          emit_boolean_logic(ctx, instr, Builder::s_or, dst);
1010       } else if (dst.regClass() == v1) {
1011          emit_vop2_instruction(ctx, instr, aco_opcode::v_or_b32, dst, true);
1012       } else if (dst.regClass() == s1) {
1013          emit_sop2_instruction(ctx, instr, aco_opcode::s_or_b32, dst, true);
1014       } else if (dst.regClass() == s2) {
1015          emit_sop2_instruction(ctx, instr, aco_opcode::s_or_b64, dst, true);
1016       } else {
1017          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1018          nir_print_instr(&instr->instr, stderr);
1019          fprintf(stderr, "\n");
1020       }
1021       break;
1022    }
1023    case nir_op_iand: {
1024       if (instr->dest.dest.ssa.bit_size == 1) {
1025          emit_boolean_logic(ctx, instr, Builder::s_and, dst);
1026       } else if (dst.regClass() == v1) {
1027          emit_vop2_instruction(ctx, instr, aco_opcode::v_and_b32, dst, true);
1028       } else if (dst.regClass() == s1) {
1029          emit_sop2_instruction(ctx, instr, aco_opcode::s_and_b32, dst, true);
1030       } else if (dst.regClass() == s2) {
1031          emit_sop2_instruction(ctx, instr, aco_opcode::s_and_b64, dst, true);
1032       } else {
1033          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1034          nir_print_instr(&instr->instr, stderr);
1035          fprintf(stderr, "\n");
1036       }
1037       break;
1038    }
1039    case nir_op_ixor: {
1040       if (instr->dest.dest.ssa.bit_size == 1) {
1041          emit_boolean_logic(ctx, instr, Builder::s_xor, dst);
1042       } else if (dst.regClass() == v1) {
1043          emit_vop2_instruction(ctx, instr, aco_opcode::v_xor_b32, dst, true);
1044       } else if (dst.regClass() == s1) {
1045          emit_sop2_instruction(ctx, instr, aco_opcode::s_xor_b32, dst, true);
1046       } else if (dst.regClass() == s2) {
1047          emit_sop2_instruction(ctx, instr, aco_opcode::s_xor_b64, dst, true);
1048       } else {
1049          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1050          nir_print_instr(&instr->instr, stderr);
1051          fprintf(stderr, "\n");
1052       }
1053       break;
1054    }
1055    case nir_op_ushr: {
1056       if (dst.regClass() == v1) {
1057          emit_vop2_instruction(ctx, instr, aco_opcode::v_lshrrev_b32, dst, false, true);
1058       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
1059          bld.vop3(aco_opcode::v_lshrrev_b64, Definition(dst),
1060                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
1061       } else if (dst.regClass() == v2) {
1062          bld.vop3(aco_opcode::v_lshr_b64, Definition(dst),
1063                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1064       } else if (dst.regClass() == s2) {
1065          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshr_b64, dst, true);
1066       } else if (dst.regClass() == s1) {
1067          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshr_b32, dst, true);
1068       } else {
1069          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1070          nir_print_instr(&instr->instr, stderr);
1071          fprintf(stderr, "\n");
1072       }
1073       break;
1074    }
1075    case nir_op_ishl: {
1076       if (dst.regClass() == v1) {
1077          emit_vop2_instruction(ctx, instr, aco_opcode::v_lshlrev_b32, dst, false, true);
1078       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
1079          bld.vop3(aco_opcode::v_lshlrev_b64, Definition(dst),
1080                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
1081       } else if (dst.regClass() == v2) {
1082          bld.vop3(aco_opcode::v_lshl_b64, Definition(dst),
1083                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1084       } else if (dst.regClass() == s1) {
1085          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshl_b32, dst, true);
1086       } else if (dst.regClass() == s2) {
1087          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshl_b64, dst, true);
1088       } else {
1089          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1090          nir_print_instr(&instr->instr, stderr);
1091          fprintf(stderr, "\n");
1092       }
1093       break;
1094    }
1095    case nir_op_ishr: {
1096       if (dst.regClass() == v1) {
1097          emit_vop2_instruction(ctx, instr, aco_opcode::v_ashrrev_i32, dst, false, true);
1098       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
1099          bld.vop3(aco_opcode::v_ashrrev_i64, Definition(dst),
1100                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
1101       } else if (dst.regClass() == v2) {
1102          bld.vop3(aco_opcode::v_ashr_i64, Definition(dst),
1103                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1104       } else if (dst.regClass() == s1) {
1105          emit_sop2_instruction(ctx, instr, aco_opcode::s_ashr_i32, dst, true);
1106       } else if (dst.regClass() == s2) {
1107          emit_sop2_instruction(ctx, instr, aco_opcode::s_ashr_i64, dst, true);
1108       } else {
1109          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1110          nir_print_instr(&instr->instr, stderr);
1111          fprintf(stderr, "\n");
1112       }
1113       break;
1114    }
1115    case nir_op_find_lsb: {
1116       Temp src = get_alu_src(ctx, instr->src[0]);
1117       if (src.regClass() == s1) {
1118          bld.sop1(aco_opcode::s_ff1_i32_b32, Definition(dst), src);
1119       } else if (src.regClass() == v1) {
1120          emit_vop1_instruction(ctx, instr, aco_opcode::v_ffbl_b32, dst);
1121       } else if (src.regClass() == s2) {
1122          bld.sop1(aco_opcode::s_ff1_i32_b64, Definition(dst), src);
1123       } else {
1124          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1125          nir_print_instr(&instr->instr, stderr);
1126          fprintf(stderr, "\n");
1127       }
1128       break;
1129    }
1130    case nir_op_ufind_msb:
1131    case nir_op_ifind_msb: {
1132       Temp src = get_alu_src(ctx, instr->src[0]);
1133       if (src.regClass() == s1 || src.regClass() == s2) {
1134          aco_opcode op = src.regClass() == s2 ?
1135                          (instr->op == nir_op_ufind_msb ? aco_opcode::s_flbit_i32_b64 : aco_opcode::s_flbit_i32_i64) :
1136                          (instr->op == nir_op_ufind_msb ? aco_opcode::s_flbit_i32_b32 : aco_opcode::s_flbit_i32);
1137          Temp msb_rev = bld.sop1(op, bld.def(s1), src);
1138
1139          Builder::Result sub = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc),
1140                                         Operand(src.size() * 32u - 1u), msb_rev);
1141          Temp msb = sub.def(0).getTemp();
1142          Temp carry = sub.def(1).getTemp();
1143
1144          bld.sop2(aco_opcode::s_cselect_b32, Definition(dst), Operand((uint32_t)-1), msb, bld.scc(carry));
1145       } else if (src.regClass() == v1) {
1146          aco_opcode op = instr->op == nir_op_ufind_msb ? aco_opcode::v_ffbh_u32 : aco_opcode::v_ffbh_i32;
1147          Temp msb_rev = bld.tmp(v1);
1148          emit_vop1_instruction(ctx, instr, op, msb_rev);
1149          Temp msb = bld.tmp(v1);
1150          Temp carry = bld.vsub32(Definition(msb), Operand(31u), Operand(msb_rev), true).def(1).getTemp();
1151          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), msb, Operand((uint32_t)-1), carry);
1152       } else {
1153          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1154          nir_print_instr(&instr->instr, stderr);
1155          fprintf(stderr, "\n");
1156       }
1157       break;
1158    }
1159    case nir_op_bitfield_reverse: {
1160       if (dst.regClass() == s1) {
1161          bld.sop1(aco_opcode::s_brev_b32, Definition(dst), get_alu_src(ctx, instr->src[0]));
1162       } else if (dst.regClass() == v1) {
1163          bld.vop1(aco_opcode::v_bfrev_b32, Definition(dst), get_alu_src(ctx, instr->src[0]));
1164       } else {
1165          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1166          nir_print_instr(&instr->instr, stderr);
1167          fprintf(stderr, "\n");
1168       }
1169       break;
1170    }
1171    case nir_op_iadd: {
1172       if (dst.regClass() == s1) {
1173          emit_sop2_instruction(ctx, instr, aco_opcode::s_add_u32, dst, true);
1174          break;
1175       }
1176
1177       Temp src0 = get_alu_src(ctx, instr->src[0]);
1178       Temp src1 = get_alu_src(ctx, instr->src[1]);
1179       if (dst.regClass() == v1) {
1180          bld.vadd32(Definition(dst), Operand(src0), Operand(src1));
1181          break;
1182       }
1183
1184       assert(src0.size() == 2 && src1.size() == 2);
1185       Temp src00 = bld.tmp(src0.type(), 1);
1186       Temp src01 = bld.tmp(dst.type(), 1);
1187       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1188       Temp src10 = bld.tmp(src1.type(), 1);
1189       Temp src11 = bld.tmp(dst.type(), 1);
1190       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1191
1192       if (dst.regClass() == s2) {
1193          Temp carry = bld.tmp(s1);
1194          Temp dst0 = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1195          Temp dst1 = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), src01, src11, bld.scc(carry));
1196          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1197       } else if (dst.regClass() == v2) {
1198          Temp dst0 = bld.tmp(v1);
1199          Temp carry = bld.vadd32(Definition(dst0), src00, src10, true).def(1).getTemp();
1200          Temp dst1 = bld.vadd32(bld.def(v1), src01, src11, false, carry);
1201          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1202       } else {
1203          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1204          nir_print_instr(&instr->instr, stderr);
1205          fprintf(stderr, "\n");
1206       }
1207       break;
1208    }
1209    case nir_op_uadd_sat: {
1210       Temp src0 = get_alu_src(ctx, instr->src[0]);
1211       Temp src1 = get_alu_src(ctx, instr->src[1]);
1212       if (dst.regClass() == s1) {
1213          Temp tmp = bld.tmp(s1), carry = bld.tmp(s1);
1214          bld.sop2(aco_opcode::s_add_u32, Definition(tmp), bld.scc(Definition(carry)),
1215                   src0, src1);
1216          bld.sop2(aco_opcode::s_cselect_b32, Definition(dst), Operand((uint32_t) -1), tmp, bld.scc(carry));
1217       } else if (dst.regClass() == v1) {
1218          if (ctx->options->chip_class >= GFX9) {
1219             aco_ptr<VOP3A_instruction> add{create_instruction<VOP3A_instruction>(aco_opcode::v_add_u32, asVOP3(Format::VOP2), 2, 1)};
1220             add->operands[0] = Operand(src0);
1221             add->operands[1] = Operand(src1);
1222             add->definitions[0] = Definition(dst);
1223             add->clamp = 1;
1224             ctx->block->instructions.emplace_back(std::move(add));
1225          } else {
1226             if (src1.regClass() != v1)
1227                std::swap(src0, src1);
1228             assert(src1.regClass() == v1);
1229             Temp tmp = bld.tmp(v1);
1230             Temp carry = bld.vadd32(Definition(tmp), src0, src1, true).def(1).getTemp();
1231             bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), tmp, Operand((uint32_t) -1), carry);
1232          }
1233       } else {
1234          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1235          nir_print_instr(&instr->instr, stderr);
1236          fprintf(stderr, "\n");
1237       }
1238       break;
1239    }
1240    case nir_op_uadd_carry: {
1241       Temp src0 = get_alu_src(ctx, instr->src[0]);
1242       Temp src1 = get_alu_src(ctx, instr->src[1]);
1243       if (dst.regClass() == s1) {
1244          bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(dst)), src0, src1);
1245          break;
1246       }
1247       if (dst.regClass() == v1) {
1248          Temp carry = bld.vadd32(bld.def(v1), src0, src1, true).def(1).getTemp();
1249          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), carry);
1250          break;
1251       }
1252
1253       Temp src00 = bld.tmp(src0.type(), 1);
1254       Temp src01 = bld.tmp(dst.type(), 1);
1255       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1256       Temp src10 = bld.tmp(src1.type(), 1);
1257       Temp src11 = bld.tmp(dst.type(), 1);
1258       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1259       if (dst.regClass() == s2) {
1260          Temp carry = bld.tmp(s1);
1261          bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1262          carry = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.scc(bld.def(s1)), src01, src11, bld.scc(carry)).def(1).getTemp();
1263          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), carry, Operand(0u));
1264       } else if (dst.regClass() == v2) {
1265          Temp carry = bld.vadd32(bld.def(v1), src00, src10, true).def(1).getTemp();
1266          carry = bld.vadd32(bld.def(v1), src01, src11, true, carry).def(1).getTemp();
1267          carry = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand(1u), carry);
1268          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), carry, Operand(0u));
1269       } else {
1270          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1271          nir_print_instr(&instr->instr, stderr);
1272          fprintf(stderr, "\n");
1273       }
1274       break;
1275    }
1276    case nir_op_isub: {
1277       if (dst.regClass() == s1) {
1278          emit_sop2_instruction(ctx, instr, aco_opcode::s_sub_i32, dst, true);
1279          break;
1280       }
1281
1282       Temp src0 = get_alu_src(ctx, instr->src[0]);
1283       Temp src1 = get_alu_src(ctx, instr->src[1]);
1284       if (dst.regClass() == v1) {
1285          bld.vsub32(Definition(dst), src0, src1);
1286          break;
1287       }
1288
1289       Temp src00 = bld.tmp(src0.type(), 1);
1290       Temp src01 = bld.tmp(dst.type(), 1);
1291       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1292       Temp src10 = bld.tmp(src1.type(), 1);
1293       Temp src11 = bld.tmp(dst.type(), 1);
1294       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1295       if (dst.regClass() == s2) {
1296          Temp carry = bld.tmp(s1);
1297          Temp dst0 = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1298          Temp dst1 = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), src01, src11, carry);
1299          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1300       } else if (dst.regClass() == v2) {
1301          Temp lower = bld.tmp(v1);
1302          Temp borrow = bld.vsub32(Definition(lower), src00, src10, true).def(1).getTemp();
1303          Temp upper = bld.vsub32(bld.def(v1), src01, src11, false, borrow);
1304          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1305       } else {
1306          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1307          nir_print_instr(&instr->instr, stderr);
1308          fprintf(stderr, "\n");
1309       }
1310       break;
1311    }
1312    case nir_op_usub_borrow: {
1313       Temp src0 = get_alu_src(ctx, instr->src[0]);
1314       Temp src1 = get_alu_src(ctx, instr->src[1]);
1315       if (dst.regClass() == s1) {
1316          bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(dst)), src0, src1);
1317          break;
1318       } else if (dst.regClass() == v1) {
1319          Temp borrow = bld.vsub32(bld.def(v1), src0, src1, true).def(1).getTemp();
1320          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), borrow);
1321          break;
1322       }
1323
1324       Temp src00 = bld.tmp(src0.type(), 1);
1325       Temp src01 = bld.tmp(dst.type(), 1);
1326       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1327       Temp src10 = bld.tmp(src1.type(), 1);
1328       Temp src11 = bld.tmp(dst.type(), 1);
1329       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1330       if (dst.regClass() == s2) {
1331          Temp borrow = bld.tmp(s1);
1332          bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(borrow)), src00, src10);
1333          borrow = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.scc(bld.def(s1)), src01, src11, bld.scc(borrow)).def(1).getTemp();
1334          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), borrow, Operand(0u));
1335       } else if (dst.regClass() == v2) {
1336          Temp borrow = bld.vsub32(bld.def(v1), src00, src10, true).def(1).getTemp();
1337          borrow = bld.vsub32(bld.def(v1), src01, src11, true, Operand(borrow)).def(1).getTemp();
1338          borrow = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand(1u), borrow);
1339          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), borrow, Operand(0u));
1340       } else {
1341          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1342          nir_print_instr(&instr->instr, stderr);
1343          fprintf(stderr, "\n");
1344       }
1345       break;
1346    }
1347    case nir_op_imul: {
1348       if (dst.regClass() == v1) {
1349          bld.vop3(aco_opcode::v_mul_lo_u32, Definition(dst),
1350                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1351       } else if (dst.regClass() == s1) {
1352          emit_sop2_instruction(ctx, instr, aco_opcode::s_mul_i32, dst, false);
1353       } else {
1354          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1355          nir_print_instr(&instr->instr, stderr);
1356          fprintf(stderr, "\n");
1357       }
1358       break;
1359    }
1360    case nir_op_umul_high: {
1361       if (dst.regClass() == v1) {
1362          bld.vop3(aco_opcode::v_mul_hi_u32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1363       } else if (dst.regClass() == s1 && ctx->options->chip_class >= GFX9) {
1364          bld.sop2(aco_opcode::s_mul_hi_u32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1365       } else if (dst.regClass() == s1) {
1366          Temp tmp = bld.vop3(aco_opcode::v_mul_hi_u32, bld.def(v1), get_alu_src(ctx, instr->src[0]),
1367                              as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1368          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), tmp);
1369       } else {
1370          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1371          nir_print_instr(&instr->instr, stderr);
1372          fprintf(stderr, "\n");
1373       }
1374       break;
1375    }
1376    case nir_op_imul_high: {
1377       if (dst.regClass() == v1) {
1378          bld.vop3(aco_opcode::v_mul_hi_i32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1379       } else if (dst.regClass() == s1 && ctx->options->chip_class >= GFX9) {
1380          bld.sop2(aco_opcode::s_mul_hi_i32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1381       } else if (dst.regClass() == s1) {
1382          Temp tmp = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), get_alu_src(ctx, instr->src[0]),
1383                              as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1384          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), tmp);
1385       } else {
1386          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1387          nir_print_instr(&instr->instr, stderr);
1388          fprintf(stderr, "\n");
1389       }
1390       break;
1391    }
1392    case nir_op_fmul: {
1393       if (dst.size() == 1) {
1394          emit_vop2_instruction(ctx, instr, aco_opcode::v_mul_f32, dst, true);
1395       } else if (dst.size() == 2) {
1396          bld.vop3(aco_opcode::v_mul_f64, Definition(dst), get_alu_src(ctx, instr->src[0]),
1397                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1398       } else {
1399          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1400          nir_print_instr(&instr->instr, stderr);
1401          fprintf(stderr, "\n");
1402       }
1403       break;
1404    }
1405    case nir_op_fadd: {
1406       if (dst.size() == 1) {
1407          emit_vop2_instruction(ctx, instr, aco_opcode::v_add_f32, dst, true);
1408       } else if (dst.size() == 2) {
1409          bld.vop3(aco_opcode::v_add_f64, Definition(dst), get_alu_src(ctx, instr->src[0]),
1410                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1411       } else {
1412          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1413          nir_print_instr(&instr->instr, stderr);
1414          fprintf(stderr, "\n");
1415       }
1416       break;
1417    }
1418    case nir_op_fsub: {
1419       Temp src0 = get_alu_src(ctx, instr->src[0]);
1420       Temp src1 = get_alu_src(ctx, instr->src[1]);
1421       if (dst.size() == 1) {
1422          if (src1.type() == RegType::vgpr || src0.type() != RegType::vgpr)
1423             emit_vop2_instruction(ctx, instr, aco_opcode::v_sub_f32, dst, false);
1424          else
1425             emit_vop2_instruction(ctx, instr, aco_opcode::v_subrev_f32, dst, true);
1426       } else if (dst.size() == 2) {
1427          Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst),
1428                                      get_alu_src(ctx, instr->src[0]),
1429                                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1430          VOP3A_instruction* sub = static_cast<VOP3A_instruction*>(add);
1431          sub->neg[1] = true;
1432       } else {
1433          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1434          nir_print_instr(&instr->instr, stderr);
1435          fprintf(stderr, "\n");
1436       }
1437       break;
1438    }
1439    case nir_op_fmax: {
1440       if (dst.size() == 1) {
1441          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_f32, dst, true, false, ctx->block->fp_mode.must_flush_denorms32);
1442       } else if (dst.size() == 2) {
1443          if (ctx->block->fp_mode.must_flush_denorms16_64 && ctx->program->chip_class < GFX9) {
1444             Temp tmp = bld.vop3(aco_opcode::v_max_f64, bld.def(v2),
1445                                 get_alu_src(ctx, instr->src[0]),
1446                                 as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1447             bld.vop3(aco_opcode::v_mul_f64, Definition(dst), Operand(0x3FF0000000000000lu), tmp);
1448          } else {
1449             bld.vop3(aco_opcode::v_max_f64, Definition(dst),
1450                      get_alu_src(ctx, instr->src[0]),
1451                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1452          }
1453       } else {
1454          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1455          nir_print_instr(&instr->instr, stderr);
1456          fprintf(stderr, "\n");
1457       }
1458       break;
1459    }
1460    case nir_op_fmin: {
1461       if (dst.size() == 1) {
1462          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_f32, dst, true, false, ctx->block->fp_mode.must_flush_denorms32);
1463       } else if (dst.size() == 2) {
1464          if (ctx->block->fp_mode.must_flush_denorms16_64 && ctx->program->chip_class < GFX9) {
1465             Temp tmp = bld.vop3(aco_opcode::v_min_f64, bld.def(v2),
1466                                 get_alu_src(ctx, instr->src[0]),
1467                                 as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1468             bld.vop3(aco_opcode::v_mul_f64, Definition(dst), Operand(0x3FF0000000000000lu), tmp);
1469          } else {
1470             bld.vop3(aco_opcode::v_min_f64, Definition(dst),
1471                      get_alu_src(ctx, instr->src[0]),
1472                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1473          }
1474       } else {
1475          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1476          nir_print_instr(&instr->instr, stderr);
1477          fprintf(stderr, "\n");
1478       }
1479       break;
1480    }
1481    case nir_op_fmax3: {
1482       if (dst.size() == 1) {
1483          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_f32, dst, ctx->block->fp_mode.must_flush_denorms32);
1484       } else {
1485          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1486          nir_print_instr(&instr->instr, stderr);
1487          fprintf(stderr, "\n");
1488       }
1489       break;
1490    }
1491    case nir_op_fmin3: {
1492       if (dst.size() == 1) {
1493          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_f32, dst, ctx->block->fp_mode.must_flush_denorms32);
1494       } else {
1495          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1496          nir_print_instr(&instr->instr, stderr);
1497          fprintf(stderr, "\n");
1498       }
1499       break;
1500    }
1501    case nir_op_fmed3: {
1502       if (dst.size() == 1) {
1503          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_f32, dst, ctx->block->fp_mode.must_flush_denorms32);
1504       } else {
1505          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1506          nir_print_instr(&instr->instr, stderr);
1507          fprintf(stderr, "\n");
1508       }
1509       break;
1510    }
1511    case nir_op_umax3: {
1512       if (dst.size() == 1) {
1513          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_u32, dst);
1514       } else {
1515          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1516          nir_print_instr(&instr->instr, stderr);
1517          fprintf(stderr, "\n");
1518       }
1519       break;
1520    }
1521    case nir_op_umin3: {
1522       if (dst.size() == 1) {
1523          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_u32, dst);
1524       } else {
1525          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1526          nir_print_instr(&instr->instr, stderr);
1527          fprintf(stderr, "\n");
1528       }
1529       break;
1530    }
1531    case nir_op_umed3: {
1532       if (dst.size() == 1) {
1533          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_u32, dst);
1534       } else {
1535          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1536          nir_print_instr(&instr->instr, stderr);
1537          fprintf(stderr, "\n");
1538       }
1539       break;
1540    }
1541    case nir_op_imax3: {
1542       if (dst.size() == 1) {
1543          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_i32, dst);
1544       } else {
1545          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1546          nir_print_instr(&instr->instr, stderr);
1547          fprintf(stderr, "\n");
1548       }
1549       break;
1550    }
1551    case nir_op_imin3: {
1552       if (dst.size() == 1) {
1553          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_i32, dst);
1554       } else {
1555          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1556          nir_print_instr(&instr->instr, stderr);
1557          fprintf(stderr, "\n");
1558       }
1559       break;
1560    }
1561    case nir_op_imed3: {
1562       if (dst.size() == 1) {
1563          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_i32, dst);
1564       } else {
1565          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1566          nir_print_instr(&instr->instr, stderr);
1567          fprintf(stderr, "\n");
1568       }
1569       break;
1570    }
1571    case nir_op_cube_face_coord: {
1572       Temp in = get_alu_src(ctx, instr->src[0], 3);
1573       Temp src[3] = { emit_extract_vector(ctx, in, 0, v1),
1574                       emit_extract_vector(ctx, in, 1, v1),
1575                       emit_extract_vector(ctx, in, 2, v1) };
1576       Temp ma = bld.vop3(aco_opcode::v_cubema_f32, bld.def(v1), src[0], src[1], src[2]);
1577       ma = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), ma);
1578       Temp sc = bld.vop3(aco_opcode::v_cubesc_f32, bld.def(v1), src[0], src[1], src[2]);
1579       Temp tc = bld.vop3(aco_opcode::v_cubetc_f32, bld.def(v1), src[0], src[1], src[2]);
1580       sc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), sc, ma, Operand(0x3f000000u/*0.5*/));
1581       tc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), tc, ma, Operand(0x3f000000u/*0.5*/));
1582       bld.pseudo(aco_opcode::p_create_vector, Definition(dst), sc, tc);
1583       break;
1584    }
1585    case nir_op_cube_face_index: {
1586       Temp in = get_alu_src(ctx, instr->src[0], 3);
1587       Temp src[3] = { emit_extract_vector(ctx, in, 0, v1),
1588                       emit_extract_vector(ctx, in, 1, v1),
1589                       emit_extract_vector(ctx, in, 2, v1) };
1590       bld.vop3(aco_opcode::v_cubeid_f32, Definition(dst), src[0], src[1], src[2]);
1591       break;
1592    }
1593    case nir_op_bcsel: {
1594       emit_bcsel(ctx, instr, dst);
1595       break;
1596    }
1597    case nir_op_frsq: {
1598       if (dst.size() == 1) {
1599          emit_rsq(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1600       } else if (dst.size() == 2) {
1601          emit_vop1_instruction(ctx, instr, aco_opcode::v_rsq_f64, dst);
1602       } else {
1603          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1604          nir_print_instr(&instr->instr, stderr);
1605          fprintf(stderr, "\n");
1606       }
1607       break;
1608    }
1609    case nir_op_fneg: {
1610       Temp src = get_alu_src(ctx, instr->src[0]);
1611       if (dst.size() == 1) {
1612          if (ctx->block->fp_mode.must_flush_denorms32)
1613             src = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x3f800000u), as_vgpr(ctx, src));
1614          bld.vop2(aco_opcode::v_xor_b32, Definition(dst), Operand(0x80000000u), as_vgpr(ctx, src));
1615       } else if (dst.size() == 2) {
1616          if (ctx->block->fp_mode.must_flush_denorms16_64)
1617             src = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), Operand(0x3FF0000000000000lu), as_vgpr(ctx, src));
1618          Temp upper = bld.tmp(v1), lower = bld.tmp(v1);
1619          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1620          upper = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), Operand(0x80000000u), upper);
1621          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1622       } else {
1623          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1624          nir_print_instr(&instr->instr, stderr);
1625          fprintf(stderr, "\n");
1626       }
1627       break;
1628    }
1629    case nir_op_fabs: {
1630       Temp src = get_alu_src(ctx, instr->src[0]);
1631       if (dst.size() == 1) {
1632          if (ctx->block->fp_mode.must_flush_denorms32)
1633             src = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x3f800000u), as_vgpr(ctx, src));
1634          bld.vop2(aco_opcode::v_and_b32, Definition(dst), Operand(0x7FFFFFFFu), as_vgpr(ctx, src));
1635       } else if (dst.size() == 2) {
1636          if (ctx->block->fp_mode.must_flush_denorms16_64)
1637             src = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), Operand(0x3FF0000000000000lu), as_vgpr(ctx, src));
1638          Temp upper = bld.tmp(v1), lower = bld.tmp(v1);
1639          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1640          upper = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7FFFFFFFu), upper);
1641          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1642       } else {
1643          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1644          nir_print_instr(&instr->instr, stderr);
1645          fprintf(stderr, "\n");
1646       }
1647       break;
1648    }
1649    case nir_op_fsat: {
1650       Temp src = get_alu_src(ctx, instr->src[0]);
1651       if (dst.size() == 1) {
1652          bld.vop3(aco_opcode::v_med3_f32, Definition(dst), Operand(0u), Operand(0x3f800000u), src);
1653          /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1654          // TODO: confirm that this holds under any circumstances
1655       } else if (dst.size() == 2) {
1656          Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst), src, Operand(0u));
1657          VOP3A_instruction* vop3 = static_cast<VOP3A_instruction*>(add);
1658          vop3->clamp = true;
1659       } else {
1660          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1661          nir_print_instr(&instr->instr, stderr);
1662          fprintf(stderr, "\n");
1663       }
1664       break;
1665    }
1666    case nir_op_flog2: {
1667       if (dst.size() == 1) {
1668          emit_log2(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1669       } else {
1670          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1671          nir_print_instr(&instr->instr, stderr);
1672          fprintf(stderr, "\n");
1673       }
1674       break;
1675    }
1676    case nir_op_frcp: {
1677       if (dst.size() == 1) {
1678          emit_rcp(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1679       } else if (dst.size() == 2) {
1680          emit_vop1_instruction(ctx, instr, aco_opcode::v_rcp_f64, dst);
1681       } else {
1682          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1683          nir_print_instr(&instr->instr, stderr);
1684          fprintf(stderr, "\n");
1685       }
1686       break;
1687    }
1688    case nir_op_fexp2: {
1689       if (dst.size() == 1) {
1690          emit_vop1_instruction(ctx, instr, aco_opcode::v_exp_f32, dst);
1691       } else {
1692          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1693          nir_print_instr(&instr->instr, stderr);
1694          fprintf(stderr, "\n");
1695       }
1696       break;
1697    }
1698    case nir_op_fsqrt: {
1699       if (dst.size() == 1) {
1700          emit_sqrt(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1701       } else if (dst.size() == 2) {
1702          emit_vop1_instruction(ctx, instr, aco_opcode::v_sqrt_f64, dst);
1703       } else {
1704          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1705          nir_print_instr(&instr->instr, stderr);
1706          fprintf(stderr, "\n");
1707       }
1708       break;
1709    }
1710    case nir_op_ffract: {
1711       if (dst.size() == 1) {
1712          emit_vop1_instruction(ctx, instr, aco_opcode::v_fract_f32, dst);
1713       } else if (dst.size() == 2) {
1714          emit_vop1_instruction(ctx, instr, aco_opcode::v_fract_f64, dst);
1715       } else {
1716          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1717          nir_print_instr(&instr->instr, stderr);
1718          fprintf(stderr, "\n");
1719       }
1720       break;
1721    }
1722    case nir_op_ffloor: {
1723       if (dst.size() == 1) {
1724          emit_vop1_instruction(ctx, instr, aco_opcode::v_floor_f32, dst);
1725       } else if (dst.size() == 2) {
1726          emit_floor_f64(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1727       } else {
1728          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1729          nir_print_instr(&instr->instr, stderr);
1730          fprintf(stderr, "\n");
1731       }
1732       break;
1733    }
1734    case nir_op_fceil: {
1735       if (dst.size() == 1) {
1736          emit_vop1_instruction(ctx, instr, aco_opcode::v_ceil_f32, dst);
1737       } else if (dst.size() == 2) {
1738          if (ctx->options->chip_class >= GFX7) {
1739             emit_vop1_instruction(ctx, instr, aco_opcode::v_ceil_f64, dst);
1740          } else {
1741             /* GFX6 doesn't support V_CEIL_F64, lower it. */
1742             Temp src0 = get_alu_src(ctx, instr->src[0]);
1743
1744             /* trunc = trunc(src0)
1745              * if (src0 > 0.0 && src0 != trunc)
1746              *    trunc += 1.0
1747              */
1748             Temp trunc = emit_trunc_f64(ctx, bld, bld.def(v2), src0);
1749             Temp tmp0 = bld.vopc_e64(aco_opcode::v_cmp_gt_f64, bld.def(bld.lm), src0, Operand(0u));
1750             Temp tmp1 = bld.vopc(aco_opcode::v_cmp_lg_f64, bld.hint_vcc(bld.def(bld.lm)), src0, trunc);
1751             Temp cond = bld.sop2(aco_opcode::s_and_b64, bld.hint_vcc(bld.def(s2)), bld.def(s1, scc), tmp0, tmp1);
1752             Temp add = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), bld.copy(bld.def(v1), Operand(0u)), bld.copy(bld.def(v1), Operand(0x3ff00000u)), cond);
1753             add = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), bld.copy(bld.def(v1), Operand(0u)), add);
1754             bld.vop3(aco_opcode::v_add_f64, Definition(dst), trunc, add);
1755          }
1756       } else {
1757          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1758          nir_print_instr(&instr->instr, stderr);
1759          fprintf(stderr, "\n");
1760       }
1761       break;
1762    }
1763    case nir_op_ftrunc: {
1764       if (dst.size() == 1) {
1765          emit_vop1_instruction(ctx, instr, aco_opcode::v_trunc_f32, dst);
1766       } else if (dst.size() == 2) {
1767          emit_trunc_f64(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1768       } else {
1769          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1770          nir_print_instr(&instr->instr, stderr);
1771          fprintf(stderr, "\n");
1772       }
1773       break;
1774    }
1775    case nir_op_fround_even: {
1776       if (dst.size() == 1) {
1777          emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f32, dst);
1778       } else if (dst.size() == 2) {
1779          if (ctx->options->chip_class >= GFX7) {
1780             emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f64, dst);
1781          } else {
1782             /* GFX6 doesn't support V_RNDNE_F64, lower it. */
1783             Temp src0 = get_alu_src(ctx, instr->src[0]);
1784
1785             Temp src0_lo = bld.tmp(v1), src0_hi = bld.tmp(v1);
1786             bld.pseudo(aco_opcode::p_split_vector, Definition(src0_lo), Definition(src0_hi), src0);
1787
1788             Temp bitmask = bld.sop1(aco_opcode::s_brev_b32, bld.def(s1), bld.copy(bld.def(s1), Operand(-2u)));
1789             Temp bfi = bld.vop3(aco_opcode::v_bfi_b32, bld.def(v1), bitmask, bld.copy(bld.def(v1), Operand(0x43300000u)), as_vgpr(ctx, src0_hi));
1790             Temp tmp = bld.vop3(aco_opcode::v_add_f64, bld.def(v2), src0, bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), bfi));
1791             Instruction *sub = bld.vop3(aco_opcode::v_add_f64, bld.def(v2), tmp, bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), bfi));
1792             static_cast<VOP3A_instruction*>(sub)->neg[1] = true;
1793             tmp = sub->definitions[0].getTemp();
1794
1795             Temp v = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(-1u), Operand(0x432fffffu));
1796             Instruction* vop3 = bld.vopc_e64(aco_opcode::v_cmp_gt_f64, bld.hint_vcc(bld.def(bld.lm)), src0, v);
1797             static_cast<VOP3A_instruction*>(vop3)->abs[0] = true;
1798             Temp cond = vop3->definitions[0].getTemp();
1799
1800             Temp tmp_lo = bld.tmp(v1), tmp_hi = bld.tmp(v1);
1801             bld.pseudo(aco_opcode::p_split_vector, Definition(tmp_lo), Definition(tmp_hi), tmp);
1802             Temp dst0 = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), tmp_lo, as_vgpr(ctx, src0_lo), cond);
1803             Temp dst1 = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), tmp_hi, as_vgpr(ctx, src0_hi), cond);
1804
1805             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1806          }
1807       } else {
1808          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1809          nir_print_instr(&instr->instr, stderr);
1810          fprintf(stderr, "\n");
1811       }
1812       break;
1813    }
1814    case nir_op_fsin:
1815    case nir_op_fcos: {
1816       Temp src = get_alu_src(ctx, instr->src[0]);
1817       aco_ptr<Instruction> norm;
1818       if (dst.size() == 1) {
1819          Temp half_pi = bld.copy(bld.def(s1), Operand(0x3e22f983u));
1820          Temp tmp = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), half_pi, as_vgpr(ctx, src));
1821
1822          /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
1823          if (ctx->options->chip_class < GFX9)
1824             tmp = bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), tmp);
1825
1826          aco_opcode opcode = instr->op == nir_op_fsin ? aco_opcode::v_sin_f32 : aco_opcode::v_cos_f32;
1827          bld.vop1(opcode, Definition(dst), tmp);
1828       } else {
1829          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1830          nir_print_instr(&instr->instr, stderr);
1831          fprintf(stderr, "\n");
1832       }
1833       break;
1834    }
1835    case nir_op_ldexp: {
1836       if (dst.size() == 1) {
1837          bld.vop3(aco_opcode::v_ldexp_f32, Definition(dst),
1838                   as_vgpr(ctx, get_alu_src(ctx, instr->src[0])),
1839                   get_alu_src(ctx, instr->src[1]));
1840       } else if (dst.size() == 2) {
1841          bld.vop3(aco_opcode::v_ldexp_f64, Definition(dst),
1842                   as_vgpr(ctx, get_alu_src(ctx, instr->src[0])),
1843                   get_alu_src(ctx, instr->src[1]));
1844       } else {
1845          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1846          nir_print_instr(&instr->instr, stderr);
1847          fprintf(stderr, "\n");
1848       }
1849       break;
1850    }
1851    case nir_op_frexp_sig: {
1852       if (dst.size() == 1) {
1853          bld.vop1(aco_opcode::v_frexp_mant_f32, Definition(dst),
1854                   get_alu_src(ctx, instr->src[0]));
1855       } else if (dst.size() == 2) {
1856          bld.vop1(aco_opcode::v_frexp_mant_f64, Definition(dst),
1857                   get_alu_src(ctx, instr->src[0]));
1858       } else {
1859          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1860          nir_print_instr(&instr->instr, stderr);
1861          fprintf(stderr, "\n");
1862       }
1863       break;
1864    }
1865    case nir_op_frexp_exp: {
1866       if (instr->src[0].src.ssa->bit_size == 32) {
1867          bld.vop1(aco_opcode::v_frexp_exp_i32_f32, Definition(dst),
1868                   get_alu_src(ctx, instr->src[0]));
1869       } else if (instr->src[0].src.ssa->bit_size == 64) {
1870          bld.vop1(aco_opcode::v_frexp_exp_i32_f64, Definition(dst),
1871                   get_alu_src(ctx, instr->src[0]));
1872       } else {
1873          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1874          nir_print_instr(&instr->instr, stderr);
1875          fprintf(stderr, "\n");
1876       }
1877       break;
1878    }
1879    case nir_op_fsign: {
1880       Temp src = as_vgpr(ctx, get_alu_src(ctx, instr->src[0]));
1881       if (dst.size() == 1) {
1882          Temp cond = bld.vopc(aco_opcode::v_cmp_nlt_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1883          src = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0x3f800000u), src, cond);
1884          cond = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1885          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0xbf800000u), src, cond);
1886       } else if (dst.size() == 2) {
1887          Temp cond = bld.vopc(aco_opcode::v_cmp_nlt_f64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1888          Temp tmp = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0x3FF00000u));
1889          Temp upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), tmp, emit_extract_vector(ctx, src, 1, v1), cond);
1890
1891          cond = bld.vopc(aco_opcode::v_cmp_le_f64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1892          tmp = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0xBFF00000u));
1893          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), tmp, upper, cond);
1894
1895          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), Operand(0u), upper);
1896       } else {
1897          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1898          nir_print_instr(&instr->instr, stderr);
1899          fprintf(stderr, "\n");
1900       }
1901       break;
1902    }
1903    case nir_op_f2f32: {
1904       if (instr->src[0].src.ssa->bit_size == 64) {
1905          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_f64, dst);
1906       } else {
1907          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1908          nir_print_instr(&instr->instr, stderr);
1909          fprintf(stderr, "\n");
1910       }
1911       break;
1912    }
1913    case nir_op_f2f64: {
1914       if (instr->src[0].src.ssa->bit_size == 32) {
1915          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_f32, dst);
1916       } else {
1917          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1918          nir_print_instr(&instr->instr, stderr);
1919          fprintf(stderr, "\n");
1920       }
1921       break;
1922    }
1923    case nir_op_i2f32: {
1924       assert(dst.size() == 1);
1925       emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_i32, dst);
1926       break;
1927    }
1928    case nir_op_i2f64: {
1929       if (instr->src[0].src.ssa->bit_size == 32) {
1930          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_i32, dst);
1931       } else if (instr->src[0].src.ssa->bit_size == 64) {
1932          Temp src = get_alu_src(ctx, instr->src[0]);
1933          RegClass rc = RegClass(src.type(), 1);
1934          Temp lower = bld.tmp(rc), upper = bld.tmp(rc);
1935          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1936          lower = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), lower);
1937          upper = bld.vop1(aco_opcode::v_cvt_f64_i32, bld.def(v2), upper);
1938          upper = bld.vop3(aco_opcode::v_ldexp_f64, bld.def(v2), upper, Operand(32u));
1939          bld.vop3(aco_opcode::v_add_f64, Definition(dst), lower, upper);
1940
1941       } else {
1942          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1943          nir_print_instr(&instr->instr, stderr);
1944          fprintf(stderr, "\n");
1945       }
1946       break;
1947    }
1948    case nir_op_u2f32: {
1949       assert(dst.size() == 1);
1950       emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_u32, dst);
1951       break;
1952    }
1953    case nir_op_u2f64: {
1954       if (instr->src[0].src.ssa->bit_size == 32) {
1955          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_u32, dst);
1956       } else if (instr->src[0].src.ssa->bit_size == 64) {
1957          Temp src = get_alu_src(ctx, instr->src[0]);
1958          RegClass rc = RegClass(src.type(), 1);
1959          Temp lower = bld.tmp(rc), upper = bld.tmp(rc);
1960          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1961          lower = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), lower);
1962          upper = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), upper);
1963          upper = bld.vop3(aco_opcode::v_ldexp_f64, bld.def(v2), upper, Operand(32u));
1964          bld.vop3(aco_opcode::v_add_f64, Definition(dst), lower, upper);
1965       } else {
1966          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1967          nir_print_instr(&instr->instr, stderr);
1968          fprintf(stderr, "\n");
1969       }
1970       break;
1971    }
1972    case nir_op_f2i32: {
1973       Temp src = get_alu_src(ctx, instr->src[0]);
1974       if (instr->src[0].src.ssa->bit_size == 32) {
1975          if (dst.type() == RegType::vgpr)
1976             bld.vop1(aco_opcode::v_cvt_i32_f32, Definition(dst), src);
1977          else
1978             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1979                        bld.vop1(aco_opcode::v_cvt_i32_f32, bld.def(v1), src));
1980
1981       } else if (instr->src[0].src.ssa->bit_size == 64) {
1982          if (dst.type() == RegType::vgpr)
1983             bld.vop1(aco_opcode::v_cvt_i32_f64, Definition(dst), src);
1984          else
1985             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1986                        bld.vop1(aco_opcode::v_cvt_i32_f64, bld.def(v1), src));
1987
1988       } else {
1989          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1990          nir_print_instr(&instr->instr, stderr);
1991          fprintf(stderr, "\n");
1992       }
1993       break;
1994    }
1995    case nir_op_f2u32: {
1996       Temp src = get_alu_src(ctx, instr->src[0]);
1997       if (instr->src[0].src.ssa->bit_size == 32) {
1998          if (dst.type() == RegType::vgpr)
1999             bld.vop1(aco_opcode::v_cvt_u32_f32, Definition(dst), src);
2000          else
2001             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
2002                        bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), src));
2003
2004       } else if (instr->src[0].src.ssa->bit_size == 64) {
2005          if (dst.type() == RegType::vgpr)
2006             bld.vop1(aco_opcode::v_cvt_u32_f64, Definition(dst), src);
2007          else
2008             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
2009                        bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), src));
2010
2011       } else {
2012          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2013          nir_print_instr(&instr->instr, stderr);
2014          fprintf(stderr, "\n");
2015       }
2016       break;
2017    }
2018    case nir_op_f2i64: {
2019       Temp src = get_alu_src(ctx, instr->src[0]);
2020       if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::vgpr) {
2021          Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f32, bld.def(v1), src);
2022          exponent = bld.vop3(aco_opcode::v_med3_i32, bld.def(v1), Operand(0x0u), exponent, Operand(64u));
2023          Temp mantissa = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffu), src);
2024          Temp sign = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
2025          mantissa = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(0x800000u), mantissa);
2026          mantissa = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(7u), mantissa);
2027          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), mantissa);
2028          Temp new_exponent = bld.tmp(v1);
2029          Temp borrow = bld.vsub32(Definition(new_exponent), Operand(63u), exponent, true).def(1).getTemp();
2030          if (ctx->program->chip_class >= GFX8)
2031             mantissa = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), new_exponent, mantissa);
2032          else
2033             mantissa = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), mantissa, new_exponent);
2034          Temp saturate = bld.vop1(aco_opcode::v_bfrev_b32, bld.def(v1), Operand(0xfffffffeu));
2035          Temp lower = bld.tmp(v1), upper = bld.tmp(v1);
2036          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2037          lower = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), lower, Operand(0xffffffffu), borrow);
2038          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), upper, saturate, borrow);
2039          lower = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), sign, lower);
2040          upper = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), sign, upper);
2041          Temp new_lower = bld.tmp(v1);
2042          borrow = bld.vsub32(Definition(new_lower), lower, sign, true).def(1).getTemp();
2043          Temp new_upper = bld.vsub32(bld.def(v1), upper, sign, false, borrow);
2044          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), new_lower, new_upper);
2045
2046       } else if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::sgpr) {
2047          if (src.type() == RegType::vgpr)
2048             src = bld.as_uniform(src);
2049          Temp exponent = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), src, Operand(0x80017u));
2050          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(126u));
2051          exponent = bld.sop2(aco_opcode::s_max_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), exponent);
2052          exponent = bld.sop2(aco_opcode::s_min_u32, bld.def(s1), bld.def(s1, scc), Operand(64u), exponent);
2053          Temp mantissa = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0x7fffffu), src);
2054          Temp sign = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
2055          mantissa = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(0x800000u), mantissa);
2056          mantissa = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), mantissa, Operand(7u));
2057          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), mantissa);
2058          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), Operand(63u), exponent);
2059          mantissa = bld.sop2(aco_opcode::s_lshr_b64, bld.def(s2), bld.def(s1, scc), mantissa, exponent);
2060          Temp cond = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), exponent, Operand(0xffffffffu)); // exp >= 64
2061          Temp saturate = bld.sop1(aco_opcode::s_brev_b64, bld.def(s2), Operand(0xfffffffeu));
2062          mantissa = bld.sop2(aco_opcode::s_cselect_b64, bld.def(s2), saturate, mantissa, cond);
2063          Temp lower = bld.tmp(s1), upper = bld.tmp(s1);
2064          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2065          lower = bld.sop2(aco_opcode::s_xor_b32, bld.def(s1), bld.def(s1, scc), sign, lower);
2066          upper = bld.sop2(aco_opcode::s_xor_b32, bld.def(s1), bld.def(s1, scc), sign, upper);
2067          Temp borrow = bld.tmp(s1);
2068          lower = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(borrow)), lower, sign);
2069          upper = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), upper, sign, borrow);
2070          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2071
2072       } else if (instr->src[0].src.ssa->bit_size == 64) {
2073          Temp vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0x3df00000u));
2074          Temp trunc = emit_trunc_f64(ctx, bld, bld.def(v2), src);
2075          Temp mul = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), trunc, vec);
2076          vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0xc1f00000u));
2077          Temp floor = emit_floor_f64(ctx, bld, bld.def(v2), mul);
2078          Temp fma = bld.vop3(aco_opcode::v_fma_f64, bld.def(v2), floor, vec, trunc);
2079          Temp lower = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), fma);
2080          Temp upper = bld.vop1(aco_opcode::v_cvt_i32_f64, bld.def(v1), floor);
2081          if (dst.type() == RegType::sgpr) {
2082             lower = bld.as_uniform(lower);
2083             upper = bld.as_uniform(upper);
2084          }
2085          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2086
2087       } else {
2088          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2089          nir_print_instr(&instr->instr, stderr);
2090          fprintf(stderr, "\n");
2091       }
2092       break;
2093    }
2094    case nir_op_f2u64: {
2095       Temp src = get_alu_src(ctx, instr->src[0]);
2096       if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::vgpr) {
2097          Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f32, bld.def(v1), src);
2098          Temp exponent_in_range = bld.vopc(aco_opcode::v_cmp_ge_i32, bld.hint_vcc(bld.def(bld.lm)), Operand(64u), exponent);
2099          exponent = bld.vop2(aco_opcode::v_max_i32, bld.def(v1), Operand(0x0u), exponent);
2100          Temp mantissa = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffu), src);
2101          mantissa = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(0x800000u), mantissa);
2102          Temp exponent_small = bld.vsub32(bld.def(v1), Operand(24u), exponent);
2103          Temp small = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), exponent_small, mantissa);
2104          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), mantissa);
2105          Temp new_exponent = bld.tmp(v1);
2106          Temp cond_small = bld.vsub32(Definition(new_exponent), exponent, Operand(24u), true).def(1).getTemp();
2107          if (ctx->program->chip_class >= GFX8)
2108             mantissa = bld.vop3(aco_opcode::v_lshlrev_b64, bld.def(v2), new_exponent, mantissa);
2109          else
2110             mantissa = bld.vop3(aco_opcode::v_lshl_b64, bld.def(v2), mantissa, new_exponent);
2111          Temp lower = bld.tmp(v1), upper = bld.tmp(v1);
2112          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2113          lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), lower, small, cond_small);
2114          upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), upper, Operand(0u), cond_small);
2115          lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xffffffffu), lower, exponent_in_range);
2116          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xffffffffu), upper, exponent_in_range);
2117          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2118
2119       } else if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::sgpr) {
2120          if (src.type() == RegType::vgpr)
2121             src = bld.as_uniform(src);
2122          Temp exponent = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), src, Operand(0x80017u));
2123          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(126u));
2124          exponent = bld.sop2(aco_opcode::s_max_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), exponent);
2125          Temp mantissa = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0x7fffffu), src);
2126          mantissa = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(0x800000u), mantissa);
2127          Temp exponent_small = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), Operand(24u), exponent);
2128          Temp small = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), mantissa, exponent_small);
2129          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), mantissa);
2130          Temp exponent_large = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(24u));
2131          mantissa = bld.sop2(aco_opcode::s_lshl_b64, bld.def(s2), bld.def(s1, scc), mantissa, exponent_large);
2132          Temp cond = bld.sopc(aco_opcode::s_cmp_ge_i32, bld.def(s1, scc), Operand(64u), exponent);
2133          mantissa = bld.sop2(aco_opcode::s_cselect_b64, bld.def(s2), mantissa, Operand(0xffffffffu), cond);
2134          Temp lower = bld.tmp(s1), upper = bld.tmp(s1);
2135          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2136          Temp cond_small = bld.sopc(aco_opcode::s_cmp_le_i32, bld.def(s1, scc), exponent, Operand(24u));
2137          lower = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), small, lower, cond_small);
2138          upper = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), Operand(0u), upper, cond_small);
2139          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2140
2141       } else if (instr->src[0].src.ssa->bit_size == 64) {
2142          Temp vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0x3df00000u));
2143          Temp trunc = emit_trunc_f64(ctx, bld, bld.def(v2), src);
2144          Temp mul = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), trunc, vec);
2145          vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0xc1f00000u));
2146          Temp floor = emit_floor_f64(ctx, bld, bld.def(v2), mul);
2147          Temp fma = bld.vop3(aco_opcode::v_fma_f64, bld.def(v2), floor, vec, trunc);
2148          Temp lower = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), fma);
2149          Temp upper = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), floor);
2150          if (dst.type() == RegType::sgpr) {
2151             lower = bld.as_uniform(lower);
2152             upper = bld.as_uniform(upper);
2153          }
2154          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2155
2156       } else {
2157          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2158          nir_print_instr(&instr->instr, stderr);
2159          fprintf(stderr, "\n");
2160       }
2161       break;
2162    }
2163    case nir_op_b2f32: {
2164       Temp src = get_alu_src(ctx, instr->src[0]);
2165       assert(src.regClass() == bld.lm);
2166
2167       if (dst.regClass() == s1) {
2168          src = bool_to_scalar_condition(ctx, src);
2169          bld.sop2(aco_opcode::s_mul_i32, Definition(dst), Operand(0x3f800000u), src);
2170       } else if (dst.regClass() == v1) {
2171          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(0x3f800000u), src);
2172       } else {
2173          unreachable("Wrong destination register class for nir_op_b2f32.");
2174       }
2175       break;
2176    }
2177    case nir_op_b2f64: {
2178       Temp src = get_alu_src(ctx, instr->src[0]);
2179       assert(src.regClass() == bld.lm);
2180
2181       if (dst.regClass() == s2) {
2182          src = bool_to_scalar_condition(ctx, src);
2183          bld.sop2(aco_opcode::s_cselect_b64, Definition(dst), Operand(0x3f800000u), Operand(0u), bld.scc(src));
2184       } else if (dst.regClass() == v2) {
2185          Temp one = bld.vop1(aco_opcode::v_mov_b32, bld.def(v2), Operand(0x3FF00000u));
2186          Temp upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), one, src);
2187          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), Operand(0u), upper);
2188       } else {
2189          unreachable("Wrong destination register class for nir_op_b2f64.");
2190       }
2191       break;
2192    }
2193    case nir_op_i2i32: {
2194       Temp src = get_alu_src(ctx, instr->src[0]);
2195       if (instr->src[0].src.ssa->bit_size == 64) {
2196          /* we can actually just say dst = src, as it would map the lower register */
2197          emit_extract_vector(ctx, src, 0, dst);
2198       } else {
2199          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2200          nir_print_instr(&instr->instr, stderr);
2201          fprintf(stderr, "\n");
2202       }
2203       break;
2204    }
2205    case nir_op_u2u32: {
2206       Temp src = get_alu_src(ctx, instr->src[0]);
2207       if (instr->src[0].src.ssa->bit_size == 16) {
2208          if (dst.regClass() == s1) {
2209             bld.sop2(aco_opcode::s_and_b32, Definition(dst), bld.def(s1, scc), Operand(0xFFFFu), src);
2210          } else {
2211             // TODO: do better with SDWA
2212             bld.vop2(aco_opcode::v_and_b32, Definition(dst), Operand(0xFFFFu), src);
2213          }
2214       } else if (instr->src[0].src.ssa->bit_size == 64) {
2215          /* we can actually just say dst = src, as it would map the lower register */
2216          emit_extract_vector(ctx, src, 0, dst);
2217       } else {
2218          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2219          nir_print_instr(&instr->instr, stderr);
2220          fprintf(stderr, "\n");
2221       }
2222       break;
2223    }
2224    case nir_op_i2i64: {
2225       Temp src = get_alu_src(ctx, instr->src[0]);
2226       if (src.regClass() == s1) {
2227          Temp high = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
2228          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, high);
2229       } else if (src.regClass() == v1) {
2230          Temp high = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
2231          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, high);
2232       } else {
2233          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2234          nir_print_instr(&instr->instr, stderr);
2235          fprintf(stderr, "\n");
2236       }
2237       break;
2238    }
2239    case nir_op_u2u64: {
2240       Temp src = get_alu_src(ctx, instr->src[0]);
2241       if (instr->src[0].src.ssa->bit_size == 32) {
2242          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, Operand(0u));
2243       } else {
2244          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2245          nir_print_instr(&instr->instr, stderr);
2246          fprintf(stderr, "\n");
2247       }
2248       break;
2249    }
2250    case nir_op_b2i32: {
2251       Temp src = get_alu_src(ctx, instr->src[0]);
2252       assert(src.regClass() == bld.lm);
2253
2254       if (dst.regClass() == s1) {
2255          // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2256          bool_to_scalar_condition(ctx, src, dst);
2257       } else if (dst.regClass() == v1) {
2258          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), src);
2259       } else {
2260          unreachable("Invalid register class for b2i32");
2261       }
2262       break;
2263    }
2264    case nir_op_i2b1: {
2265       Temp src = get_alu_src(ctx, instr->src[0]);
2266       assert(dst.regClass() == bld.lm);
2267
2268       if (src.type() == RegType::vgpr) {
2269          assert(src.regClass() == v1 || src.regClass() == v2);
2270          assert(dst.regClass() == bld.lm);
2271          bld.vopc(src.size() == 2 ? aco_opcode::v_cmp_lg_u64 : aco_opcode::v_cmp_lg_u32,
2272                   Definition(dst), Operand(0u), src).def(0).setHint(vcc);
2273       } else {
2274          assert(src.regClass() == s1 || src.regClass() == s2);
2275          Temp tmp;
2276          if (src.regClass() == s2 && ctx->program->chip_class <= GFX7) {
2277             tmp = bld.sop2(aco_opcode::s_or_b64, bld.def(s2), bld.def(s1, scc), Operand(0u), src).def(1).getTemp();
2278          } else {
2279             tmp = bld.sopc(src.size() == 2 ? aco_opcode::s_cmp_lg_u64 : aco_opcode::s_cmp_lg_u32,
2280                            bld.scc(bld.def(s1)), Operand(0u), src);
2281          }
2282          bool_to_vector_condition(ctx, tmp, dst);
2283       }
2284       break;
2285    }
2286    case nir_op_pack_64_2x32_split: {
2287       Temp src0 = get_alu_src(ctx, instr->src[0]);
2288       Temp src1 = get_alu_src(ctx, instr->src[1]);
2289
2290       bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src0, src1);
2291       break;
2292    }
2293    case nir_op_unpack_64_2x32_split_x:
2294       bld.pseudo(aco_opcode::p_split_vector, Definition(dst), bld.def(dst.regClass()), get_alu_src(ctx, instr->src[0]));
2295       break;
2296    case nir_op_unpack_64_2x32_split_y:
2297       bld.pseudo(aco_opcode::p_split_vector, bld.def(dst.regClass()), Definition(dst), get_alu_src(ctx, instr->src[0]));
2298       break;
2299    case nir_op_pack_half_2x16: {
2300       Temp src = get_alu_src(ctx, instr->src[0], 2);
2301
2302       if (dst.regClass() == v1) {
2303          Temp src0 = bld.tmp(v1);
2304          Temp src1 = bld.tmp(v1);
2305          bld.pseudo(aco_opcode::p_split_vector, Definition(src0), Definition(src1), src);
2306          if (!ctx->block->fp_mode.care_about_round32 || ctx->block->fp_mode.round32 == fp_round_tz)
2307             bld.vop3(aco_opcode::v_cvt_pkrtz_f16_f32, Definition(dst), src0, src1);
2308          else
2309             bld.vop3(aco_opcode::v_cvt_pk_u16_u32, Definition(dst),
2310                      bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src0),
2311                      bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src1));
2312       } else {
2313          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2314          nir_print_instr(&instr->instr, stderr);
2315          fprintf(stderr, "\n");
2316       }
2317       break;
2318    }
2319    case nir_op_unpack_half_2x16_split_x: {
2320       if (dst.regClass() == v1) {
2321          Builder bld(ctx->program, ctx->block);
2322          bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst), get_alu_src(ctx, instr->src[0]));
2323       } else {
2324          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2325          nir_print_instr(&instr->instr, stderr);
2326          fprintf(stderr, "\n");
2327       }
2328       break;
2329    }
2330    case nir_op_unpack_half_2x16_split_y: {
2331       if (dst.regClass() == v1) {
2332          Builder bld(ctx->program, ctx->block);
2333          /* TODO: use SDWA here */
2334          bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst),
2335                   bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(16u), as_vgpr(ctx, get_alu_src(ctx, instr->src[0]))));
2336       } else {
2337          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2338          nir_print_instr(&instr->instr, stderr);
2339          fprintf(stderr, "\n");
2340       }
2341       break;
2342    }
2343    case nir_op_fquantize2f16: {
2344       Temp src = get_alu_src(ctx, instr->src[0]);
2345       Temp f16 = bld.vop1(aco_opcode::v_cvt_f16_f32, bld.def(v1), src);
2346       Temp f32, cmp_res;
2347
2348       if (ctx->program->chip_class >= GFX8) {
2349          Temp mask = bld.copy(bld.def(s1), Operand(0x36Fu)); /* value is NOT negative/positive denormal value */
2350          cmp_res = bld.vopc_e64(aco_opcode::v_cmp_class_f16, bld.hint_vcc(bld.def(bld.lm)), f16, mask);
2351          f32 = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), f16);
2352       } else {
2353          /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2354           * so compare the result and flush to 0 if it's smaller.
2355           */
2356          f32 = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), f16);
2357          Temp smallest = bld.copy(bld.def(s1), Operand(0x38800000u));
2358          Instruction* vop3 = bld.vopc_e64(aco_opcode::v_cmp_nlt_f32, bld.hint_vcc(bld.def(bld.lm)), f32, smallest);
2359          static_cast<VOP3A_instruction*>(vop3)->abs[0] = true;
2360          cmp_res = vop3->definitions[0].getTemp();
2361       }
2362
2363       if (ctx->block->fp_mode.preserve_signed_zero_inf_nan32 || ctx->program->chip_class < GFX8) {
2364          Temp copysign_0 = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0u), as_vgpr(ctx, src));
2365          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), copysign_0, f32, cmp_res);
2366       } else {
2367          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), f32, cmp_res);
2368       }
2369       break;
2370    }
2371    case nir_op_bfm: {
2372       Temp bits = get_alu_src(ctx, instr->src[0]);
2373       Temp offset = get_alu_src(ctx, instr->src[1]);
2374
2375       if (dst.regClass() == s1) {
2376          bld.sop2(aco_opcode::s_bfm_b32, Definition(dst), bits, offset);
2377       } else if (dst.regClass() == v1) {
2378          bld.vop3(aco_opcode::v_bfm_b32, Definition(dst), bits, offset);
2379       } else {
2380          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2381          nir_print_instr(&instr->instr, stderr);
2382          fprintf(stderr, "\n");
2383       }
2384       break;
2385    }
2386    case nir_op_bitfield_select: {
2387       /* (mask & insert) | (~mask & base) */
2388       Temp bitmask = get_alu_src(ctx, instr->src[0]);
2389       Temp insert = get_alu_src(ctx, instr->src[1]);
2390       Temp base = get_alu_src(ctx, instr->src[2]);
2391
2392       /* dst = (insert & bitmask) | (base & ~bitmask) */
2393       if (dst.regClass() == s1) {
2394          aco_ptr<Instruction> sop2;
2395          nir_const_value* const_bitmask = nir_src_as_const_value(instr->src[0].src);
2396          nir_const_value* const_insert = nir_src_as_const_value(instr->src[1].src);
2397          Operand lhs;
2398          if (const_insert && const_bitmask) {
2399             lhs = Operand(const_insert->u32 & const_bitmask->u32);
2400          } else {
2401             insert = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), insert, bitmask);
2402             lhs = Operand(insert);
2403          }
2404
2405          Operand rhs;
2406          nir_const_value* const_base = nir_src_as_const_value(instr->src[2].src);
2407          if (const_base && const_bitmask) {
2408             rhs = Operand(const_base->u32 & ~const_bitmask->u32);
2409          } else {
2410             base = bld.sop2(aco_opcode::s_andn2_b32, bld.def(s1), bld.def(s1, scc), base, bitmask);
2411             rhs = Operand(base);
2412          }
2413
2414          bld.sop2(aco_opcode::s_or_b32, Definition(dst), bld.def(s1, scc), rhs, lhs);
2415
2416       } else if (dst.regClass() == v1) {
2417          if (base.type() == RegType::sgpr && (bitmask.type() == RegType::sgpr || (insert.type() == RegType::sgpr)))
2418             base = as_vgpr(ctx, base);
2419          if (insert.type() == RegType::sgpr && bitmask.type() == RegType::sgpr)
2420             insert = as_vgpr(ctx, insert);
2421
2422          bld.vop3(aco_opcode::v_bfi_b32, Definition(dst), bitmask, insert, base);
2423
2424       } else {
2425          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2426          nir_print_instr(&instr->instr, stderr);
2427          fprintf(stderr, "\n");
2428       }
2429       break;
2430    }
2431    case nir_op_ubfe:
2432    case nir_op_ibfe: {
2433       Temp base = get_alu_src(ctx, instr->src[0]);
2434       Temp offset = get_alu_src(ctx, instr->src[1]);
2435       Temp bits = get_alu_src(ctx, instr->src[2]);
2436
2437       if (dst.type() == RegType::sgpr) {
2438          Operand extract;
2439          nir_const_value* const_offset = nir_src_as_const_value(instr->src[1].src);
2440          nir_const_value* const_bits = nir_src_as_const_value(instr->src[2].src);
2441          if (const_offset && const_bits) {
2442             uint32_t const_extract = (const_bits->u32 << 16) | const_offset->u32;
2443             extract = Operand(const_extract);
2444          } else {
2445             Operand width;
2446             if (const_bits) {
2447                width = Operand(const_bits->u32 << 16);
2448             } else {
2449                width = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), bits, Operand(16u));
2450             }
2451             extract = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), offset, width);
2452          }
2453
2454          aco_opcode opcode;
2455          if (dst.regClass() == s1) {
2456             if (instr->op == nir_op_ubfe)
2457                opcode = aco_opcode::s_bfe_u32;
2458             else
2459                opcode = aco_opcode::s_bfe_i32;
2460          } else if (dst.regClass() == s2) {
2461             if (instr->op == nir_op_ubfe)
2462                opcode = aco_opcode::s_bfe_u64;
2463             else
2464                opcode = aco_opcode::s_bfe_i64;
2465          } else {
2466             unreachable("Unsupported BFE bit size");
2467          }
2468
2469          bld.sop2(opcode, Definition(dst), bld.def(s1, scc), base, extract);
2470
2471       } else {
2472          aco_opcode opcode;
2473          if (dst.regClass() == v1) {
2474             if (instr->op == nir_op_ubfe)
2475                opcode = aco_opcode::v_bfe_u32;
2476             else
2477                opcode = aco_opcode::v_bfe_i32;
2478          } else {
2479             unreachable("Unsupported BFE bit size");
2480          }
2481
2482          emit_vop3a_instruction(ctx, instr, opcode, dst);
2483       }
2484       break;
2485    }
2486    case nir_op_bit_count: {
2487       Temp src = get_alu_src(ctx, instr->src[0]);
2488       if (src.regClass() == s1) {
2489          bld.sop1(aco_opcode::s_bcnt1_i32_b32, Definition(dst), bld.def(s1, scc), src);
2490       } else if (src.regClass() == v1) {
2491          bld.vop3(aco_opcode::v_bcnt_u32_b32, Definition(dst), src, Operand(0u));
2492       } else if (src.regClass() == v2) {
2493          bld.vop3(aco_opcode::v_bcnt_u32_b32, Definition(dst),
2494                   emit_extract_vector(ctx, src, 1, v1),
2495                   bld.vop3(aco_opcode::v_bcnt_u32_b32, bld.def(v1),
2496                            emit_extract_vector(ctx, src, 0, v1), Operand(0u)));
2497       } else if (src.regClass() == s2) {
2498          bld.sop1(aco_opcode::s_bcnt1_i32_b64, Definition(dst), bld.def(s1, scc), src);
2499       } else {
2500          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2501          nir_print_instr(&instr->instr, stderr);
2502          fprintf(stderr, "\n");
2503       }
2504       break;
2505    }
2506    case nir_op_flt: {
2507       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_f32, aco_opcode::v_cmp_lt_f64);
2508       break;
2509    }
2510    case nir_op_fge: {
2511       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_f32, aco_opcode::v_cmp_ge_f64);
2512       break;
2513    }
2514    case nir_op_feq: {
2515       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_eq_f32, aco_opcode::v_cmp_eq_f64);
2516       break;
2517    }
2518    case nir_op_fne: {
2519       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_neq_f32, aco_opcode::v_cmp_neq_f64);
2520       break;
2521    }
2522    case nir_op_ilt: {
2523       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_i32, aco_opcode::v_cmp_lt_i64, aco_opcode::s_cmp_lt_i32);
2524       break;
2525    }
2526    case nir_op_ige: {
2527       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_i32, aco_opcode::v_cmp_ge_i64, aco_opcode::s_cmp_ge_i32);
2528       break;
2529    }
2530    case nir_op_ieq: {
2531       if (instr->src[0].src.ssa->bit_size == 1)
2532          emit_boolean_logic(ctx, instr, Builder::s_xnor, dst);
2533       else
2534          emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_eq_i32, aco_opcode::v_cmp_eq_i64, aco_opcode::s_cmp_eq_i32,
2535                          ctx->program->chip_class >= GFX8 ? aco_opcode::s_cmp_eq_u64 : aco_opcode::num_opcodes);
2536       break;
2537    }
2538    case nir_op_ine: {
2539       if (instr->src[0].src.ssa->bit_size == 1)
2540          emit_boolean_logic(ctx, instr, Builder::s_xor, dst);
2541       else
2542          emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lg_i32, aco_opcode::v_cmp_lg_i64, aco_opcode::s_cmp_lg_i32,
2543                          ctx->program->chip_class >= GFX8 ? aco_opcode::s_cmp_lg_u64 : aco_opcode::num_opcodes);
2544       break;
2545    }
2546    case nir_op_ult: {
2547       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_u32, aco_opcode::v_cmp_lt_u64, aco_opcode::s_cmp_lt_u32);
2548       break;
2549    }
2550    case nir_op_uge: {
2551       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_u32, aco_opcode::v_cmp_ge_u64, aco_opcode::s_cmp_ge_u32);
2552       break;
2553    }
2554    case nir_op_fddx:
2555    case nir_op_fddy:
2556    case nir_op_fddx_fine:
2557    case nir_op_fddy_fine:
2558    case nir_op_fddx_coarse:
2559    case nir_op_fddy_coarse: {
2560       Temp src = get_alu_src(ctx, instr->src[0]);
2561       uint16_t dpp_ctrl1, dpp_ctrl2;
2562       if (instr->op == nir_op_fddx_fine) {
2563          dpp_ctrl1 = dpp_quad_perm(0, 0, 2, 2);
2564          dpp_ctrl2 = dpp_quad_perm(1, 1, 3, 3);
2565       } else if (instr->op == nir_op_fddy_fine) {
2566          dpp_ctrl1 = dpp_quad_perm(0, 1, 0, 1);
2567          dpp_ctrl2 = dpp_quad_perm(2, 3, 2, 3);
2568       } else {
2569          dpp_ctrl1 = dpp_quad_perm(0, 0, 0, 0);
2570          if (instr->op == nir_op_fddx || instr->op == nir_op_fddx_coarse)
2571             dpp_ctrl2 = dpp_quad_perm(1, 1, 1, 1);
2572          else
2573             dpp_ctrl2 = dpp_quad_perm(2, 2, 2, 2);
2574       }
2575
2576       Temp tmp;
2577       if (ctx->program->chip_class >= GFX8) {
2578          Temp tl = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl1);
2579          tmp = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), src, tl, dpp_ctrl2);
2580       } else {
2581          Temp tl = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl1);
2582          Temp tr = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl2);
2583          tmp = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), tr, tl);
2584       }
2585       emit_wqm(ctx, tmp, dst, true);
2586       break;
2587    }
2588    default:
2589       fprintf(stderr, "Unknown NIR ALU instr: ");
2590       nir_print_instr(&instr->instr, stderr);
2591       fprintf(stderr, "\n");
2592    }
2593 }
2594
2595 void visit_load_const(isel_context *ctx, nir_load_const_instr *instr)
2596 {
2597    Temp dst = get_ssa_temp(ctx, &instr->def);
2598
2599    // TODO: we really want to have the resulting type as this would allow for 64bit literals
2600    // which get truncated the lsb if double and msb if int
2601    // for now, we only use s_mov_b64 with 64bit inline constants
2602    assert(instr->def.num_components == 1 && "Vector load_const should be lowered to scalar.");
2603    assert(dst.type() == RegType::sgpr);
2604
2605    Builder bld(ctx->program, ctx->block);
2606
2607    if (instr->def.bit_size == 1) {
2608       assert(dst.regClass() == bld.lm);
2609       int val = instr->value[0].b ? -1 : 0;
2610       Operand op = bld.lm.size() == 1 ? Operand((uint32_t) val) : Operand((uint64_t) val);
2611       bld.sop1(Builder::s_mov, Definition(dst), op);
2612    } else if (dst.size() == 1) {
2613       bld.copy(Definition(dst), Operand(instr->value[0].u32));
2614    } else {
2615       assert(dst.size() != 1);
2616       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
2617       if (instr->def.bit_size == 64)
2618          for (unsigned i = 0; i < dst.size(); i++)
2619             vec->operands[i] = Operand{(uint32_t)(instr->value[0].u64 >> i * 32)};
2620       else {
2621          for (unsigned i = 0; i < dst.size(); i++)
2622             vec->operands[i] = Operand{instr->value[i].u32};
2623       }
2624       vec->definitions[0] = Definition(dst);
2625       ctx->block->instructions.emplace_back(std::move(vec));
2626    }
2627 }
2628
2629 uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2630 {
2631    uint32_t new_mask = 0;
2632    for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2633       if (mask & (1u << i))
2634          new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2635    return new_mask;
2636 }
2637
2638 Operand load_lds_size_m0(isel_context *ctx)
2639 {
2640    /* TODO: m0 does not need to be initialized on GFX9+ */
2641    Builder bld(ctx->program, ctx->block);
2642    return bld.m0((Temp)bld.sopk(aco_opcode::s_movk_i32, bld.def(s1, m0), 0xffff));
2643 }
2644
2645 void load_lds(isel_context *ctx, unsigned elem_size_bytes, Temp dst,
2646               Temp address, unsigned base_offset, unsigned align)
2647 {
2648    assert(util_is_power_of_two_nonzero(align) && align >= 4);
2649
2650    Builder bld(ctx->program, ctx->block);
2651
2652    Operand m = load_lds_size_m0(ctx);
2653
2654    unsigned num_components = dst.size() * 4u / elem_size_bytes;
2655    unsigned bytes_read = 0;
2656    unsigned result_size = 0;
2657    unsigned total_bytes = num_components * elem_size_bytes;
2658    std::array<Temp, NIR_MAX_VEC_COMPONENTS> result;
2659    bool large_ds_read = ctx->options->chip_class >= GFX7;
2660    bool usable_read2 = ctx->options->chip_class >= GFX7;
2661
2662    while (bytes_read < total_bytes) {
2663       unsigned todo = total_bytes - bytes_read;
2664       bool aligned8 = bytes_read % 8 == 0 && align % 8 == 0;
2665       bool aligned16 = bytes_read % 16 == 0 && align % 16 == 0;
2666
2667       aco_opcode op = aco_opcode::last_opcode;
2668       bool read2 = false;
2669       if (todo >= 16 && aligned16 && large_ds_read) {
2670          op = aco_opcode::ds_read_b128;
2671          todo = 16;
2672       } else if (todo >= 16 && aligned8 && usable_read2) {
2673          op = aco_opcode::ds_read2_b64;
2674          read2 = true;
2675          todo = 16;
2676       } else if (todo >= 12 && aligned16 && large_ds_read) {
2677          op = aco_opcode::ds_read_b96;
2678          todo = 12;
2679       } else if (todo >= 8 && aligned8) {
2680          op = aco_opcode::ds_read_b64;
2681          todo = 8;
2682       } else if (todo >= 8 && usable_read2) {
2683          op = aco_opcode::ds_read2_b32;
2684          read2 = true;
2685          todo = 8;
2686       } else if (todo >= 4) {
2687          op = aco_opcode::ds_read_b32;
2688          todo = 4;
2689       } else {
2690          assert(false);
2691       }
2692       assert(todo % elem_size_bytes == 0);
2693       unsigned num_elements = todo / elem_size_bytes;
2694       unsigned offset = base_offset + bytes_read;
2695       unsigned max_offset = read2 ? 1019 : 65535;
2696
2697       Temp address_offset = address;
2698       if (offset > max_offset) {
2699          address_offset = bld.vadd32(bld.def(v1), Operand(base_offset), address_offset);
2700          offset = bytes_read;
2701       }
2702       assert(offset <= max_offset); /* bytes_read shouldn't be large enough for this to happen */
2703
2704       Temp res;
2705       if (num_components == 1 && dst.type() == RegType::vgpr)
2706          res = dst;
2707       else
2708          res = bld.tmp(RegClass(RegType::vgpr, todo / 4));
2709
2710       if (read2)
2711          res = bld.ds(op, Definition(res), address_offset, m, offset >> 2, (offset >> 2) + 1);
2712       else
2713          res = bld.ds(op, Definition(res), address_offset, m, offset);
2714
2715       if (num_components == 1) {
2716          assert(todo == total_bytes);
2717          if (dst.type() == RegType::sgpr)
2718             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), res);
2719          return;
2720       }
2721
2722       if (dst.type() == RegType::sgpr) {
2723          Temp new_res = bld.tmp(RegType::sgpr, res.size());
2724          expand_vector(ctx, res, new_res, res.size(), (1 << res.size()) - 1);
2725          res = new_res;
2726       }
2727
2728       if (num_elements == 1) {
2729          result[result_size++] = res;
2730       } else {
2731          assert(res != dst && res.size() % num_elements == 0);
2732          aco_ptr<Pseudo_instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector, Format::PSEUDO, 1, num_elements)};
2733          split->operands[0] = Operand(res);
2734          for (unsigned i = 0; i < num_elements; i++)
2735             split->definitions[i] = Definition(result[result_size++] = bld.tmp(res.type(), elem_size_bytes / 4));
2736          ctx->block->instructions.emplace_back(std::move(split));
2737       }
2738
2739       bytes_read += todo;
2740    }
2741
2742    assert(result_size == num_components && result_size > 1);
2743    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, result_size, 1)};
2744    for (unsigned i = 0; i < result_size; i++)
2745       vec->operands[i] = Operand(result[i]);
2746    vec->definitions[0] = Definition(dst);
2747    ctx->block->instructions.emplace_back(std::move(vec));
2748    ctx->allocated_vec.emplace(dst.id(), result);
2749 }
2750
2751 Temp extract_subvector(isel_context *ctx, Temp data, unsigned start, unsigned size, RegType type)
2752 {
2753    if (start == 0 && size == data.size())
2754       return type == RegType::vgpr ? as_vgpr(ctx, data) : data;
2755
2756    unsigned size_hint = 1;
2757    auto it = ctx->allocated_vec.find(data.id());
2758    if (it != ctx->allocated_vec.end())
2759       size_hint = it->second[0].size();
2760    if (size % size_hint || start % size_hint)
2761       size_hint = 1;
2762
2763    start /= size_hint;
2764    size /= size_hint;
2765
2766    Temp elems[size];
2767    for (unsigned i = 0; i < size; i++)
2768       elems[i] = emit_extract_vector(ctx, data, start + i, RegClass(type, size_hint));
2769
2770    if (size == 1)
2771       return type == RegType::vgpr ? as_vgpr(ctx, elems[0]) : elems[0];
2772
2773    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, size, 1)};
2774    for (unsigned i = 0; i < size; i++)
2775       vec->operands[i] = Operand(elems[i]);
2776    Temp res = {ctx->program->allocateId(), RegClass(type, size * size_hint)};
2777    vec->definitions[0] = Definition(res);
2778    ctx->block->instructions.emplace_back(std::move(vec));
2779    return res;
2780 }
2781
2782 void ds_write_helper(isel_context *ctx, Operand m, Temp address, Temp data, unsigned data_start, unsigned total_size, unsigned offset0, unsigned offset1, unsigned align)
2783 {
2784    Builder bld(ctx->program, ctx->block);
2785    unsigned bytes_written = 0;
2786    bool large_ds_write = ctx->options->chip_class >= GFX7;
2787    bool usable_write2 = ctx->options->chip_class >= GFX7;
2788
2789    while (bytes_written < total_size * 4) {
2790       unsigned todo = total_size * 4 - bytes_written;
2791       bool aligned8 = bytes_written % 8 == 0 && align % 8 == 0;
2792       bool aligned16 = bytes_written % 16 == 0 && align % 16 == 0;
2793
2794       aco_opcode op = aco_opcode::last_opcode;
2795       bool write2 = false;
2796       unsigned size = 0;
2797       if (todo >= 16 && aligned16 && large_ds_write) {
2798          op = aco_opcode::ds_write_b128;
2799          size = 4;
2800       } else if (todo >= 16 && aligned8 && usable_write2) {
2801          op = aco_opcode::ds_write2_b64;
2802          write2 = true;
2803          size = 4;
2804       } else if (todo >= 12 && aligned16 && large_ds_write) {
2805          op = aco_opcode::ds_write_b96;
2806          size = 3;
2807       } else if (todo >= 8 && aligned8) {
2808          op = aco_opcode::ds_write_b64;
2809          size = 2;
2810       } else if (todo >= 8 && usable_write2) {
2811          op = aco_opcode::ds_write2_b32;
2812          write2 = true;
2813          size = 2;
2814       } else if (todo >= 4) {
2815          op = aco_opcode::ds_write_b32;
2816          size = 1;
2817       } else {
2818          assert(false);
2819       }
2820
2821       unsigned offset = offset0 + offset1 + bytes_written;
2822       unsigned max_offset = write2 ? 1020 : 65535;
2823       Temp address_offset = address;
2824       if (offset > max_offset) {
2825          address_offset = bld.vadd32(bld.def(v1), Operand(offset0), address_offset);
2826          offset = offset1 + bytes_written;
2827       }
2828       assert(offset <= max_offset); /* offset1 shouldn't be large enough for this to happen */
2829
2830       if (write2) {
2831          Temp val0 = extract_subvector(ctx, data, data_start + (bytes_written >> 2), size / 2, RegType::vgpr);
2832          Temp val1 = extract_subvector(ctx, data, data_start + (bytes_written >> 2) + 1, size / 2, RegType::vgpr);
2833          bld.ds(op, address_offset, val0, val1, m, offset >> 2, (offset >> 2) + 1);
2834       } else {
2835          Temp val = extract_subvector(ctx, data, data_start + (bytes_written >> 2), size, RegType::vgpr);
2836          bld.ds(op, address_offset, val, m, offset);
2837       }
2838
2839       bytes_written += size * 4;
2840    }
2841 }
2842
2843 void store_lds(isel_context *ctx, unsigned elem_size_bytes, Temp data, uint32_t wrmask,
2844                Temp address, unsigned base_offset, unsigned align)
2845 {
2846    assert(util_is_power_of_two_nonzero(align) && align >= 4);
2847
2848    Operand m = load_lds_size_m0(ctx);
2849
2850    /* we need at most two stores for 32bit variables */
2851    int start[2], count[2];
2852    u_bit_scan_consecutive_range(&wrmask, &start[0], &count[0]);
2853    u_bit_scan_consecutive_range(&wrmask, &start[1], &count[1]);
2854    assert(wrmask == 0);
2855
2856    /* one combined store is sufficient */
2857    if (count[0] == count[1]) {
2858       Builder bld(ctx->program, ctx->block);
2859
2860       Temp address_offset = address;
2861       if ((base_offset >> 2) + start[1] > 255) {
2862          address_offset = bld.vadd32(bld.def(v1), Operand(base_offset), address_offset);
2863          base_offset = 0;
2864       }
2865
2866       assert(count[0] == 1);
2867       Temp val0 = emit_extract_vector(ctx, data, start[0], v1);
2868       Temp val1 = emit_extract_vector(ctx, data, start[1], v1);
2869       aco_opcode op = elem_size_bytes == 4 ? aco_opcode::ds_write2_b32 : aco_opcode::ds_write2_b64;
2870       base_offset = base_offset / elem_size_bytes;
2871       bld.ds(op, address_offset, val0, val1, m,
2872              base_offset + start[0], base_offset + start[1]);
2873       return;
2874    }
2875
2876    for (unsigned i = 0; i < 2; i++) {
2877       if (count[i] == 0)
2878          continue;
2879
2880       unsigned elem_size_words = elem_size_bytes / 4;
2881       ds_write_helper(ctx, m, address, data, start[i] * elem_size_words, count[i] * elem_size_words,
2882                       base_offset, start[i] * elem_size_bytes, align);
2883    }
2884    return;
2885 }
2886
2887 unsigned calculate_lds_alignment(isel_context *ctx, unsigned const_offset)
2888 {
2889    unsigned align = 16;
2890    if (const_offset)
2891       align = std::min(align, 1u << (ffs(const_offset) - 1));
2892
2893    return align;
2894 }
2895
2896
2897 Temp create_vec_from_array(isel_context *ctx, Temp arr[], unsigned cnt, RegType reg_type, unsigned split_cnt = 0u, Temp dst = Temp())
2898 {
2899    Builder bld(ctx->program, ctx->block);
2900
2901    if (!dst.id())
2902       dst = bld.tmp(RegClass(reg_type, cnt * arr[0].size()));
2903
2904    std::array<Temp, NIR_MAX_VEC_COMPONENTS> allocated_vec;
2905    aco_ptr<Pseudo_instruction> instr {create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, cnt, 1)};
2906    instr->definitions[0] = Definition(dst);
2907
2908    for (unsigned i = 0; i < cnt; ++i) {
2909       assert(arr[i].size() == arr[0].size());
2910       allocated_vec[i] = arr[i];
2911       instr->operands[i] = Operand(arr[i]);
2912    }
2913
2914    bld.insert(std::move(instr));
2915
2916    if (split_cnt)
2917       emit_split_vector(ctx, dst, split_cnt);
2918    else
2919       ctx->allocated_vec.emplace(dst.id(), allocated_vec); /* emit_split_vector already does this */
2920
2921    return dst;
2922 }
2923
2924 inline unsigned resolve_excess_vmem_const_offset(Builder &bld, Temp &voffset, unsigned const_offset)
2925 {
2926    if (const_offset >= 4096) {
2927       unsigned excess_const_offset = const_offset / 4096u * 4096u;
2928       const_offset %= 4096u;
2929
2930       if (!voffset.id())
2931          voffset = bld.copy(bld.def(v1), Operand(excess_const_offset));
2932       else if (unlikely(voffset.regClass() == s1))
2933          voffset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), Operand(excess_const_offset), Operand(voffset));
2934       else if (likely(voffset.regClass() == v1))
2935          voffset = bld.vadd32(bld.def(v1), Operand(voffset), Operand(excess_const_offset));
2936       else
2937          unreachable("Unsupported register class of voffset");
2938    }
2939
2940    return const_offset;
2941 }
2942
2943 void emit_single_mubuf_store(isel_context *ctx, Temp descriptor, Temp voffset, Temp soffset, Temp vdata,
2944                              unsigned const_offset = 0u, bool allow_reorder = true, bool slc = false)
2945 {
2946    assert(vdata.id());
2947    assert(vdata.size() != 3 || ctx->program->chip_class != GFX6);
2948    assert(vdata.size() >= 1 && vdata.size() <= 4);
2949
2950    Builder bld(ctx->program, ctx->block);
2951    aco_opcode op = (aco_opcode) ((unsigned) aco_opcode::buffer_store_dword + vdata.size() - 1);
2952    const_offset = resolve_excess_vmem_const_offset(bld, voffset, const_offset);
2953
2954    Operand voffset_op = voffset.id() ? Operand(as_vgpr(ctx, voffset)) : Operand(v1);
2955    Operand soffset_op = soffset.id() ? Operand(soffset) : Operand(0u);
2956    Builder::Result r = bld.mubuf(op, Operand(descriptor), voffset_op, soffset_op, Operand(vdata), const_offset,
2957                                  /* offen */ !voffset_op.isUndefined(), /* idxen*/ false, /* addr64 */ false,
2958                                  /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc);
2959
2960    static_cast<MUBUF_instruction *>(r.instr)->can_reorder = allow_reorder;
2961 }
2962
2963 void store_vmem_mubuf(isel_context *ctx, Temp src, Temp descriptor, Temp voffset, Temp soffset,
2964                                    unsigned base_const_offset, unsigned elem_size_bytes, unsigned write_mask,
2965                                    bool allow_combining = true, bool reorder = true, bool slc = false)
2966 {
2967    Builder bld(ctx->program, ctx->block);
2968    assert(elem_size_bytes == 4 || elem_size_bytes == 8);
2969    assert(write_mask);
2970
2971    if (elem_size_bytes == 8) {
2972       elem_size_bytes = 4;
2973       write_mask = widen_mask(write_mask, 2);
2974    }
2975
2976    while (write_mask) {
2977       int start = 0;
2978       int count = 0;
2979       u_bit_scan_consecutive_range(&write_mask, &start, &count);
2980       assert(count > 0);
2981       assert(start >= 0);
2982
2983       while (count > 0) {
2984          unsigned sub_count = allow_combining ? MIN2(count, 4) : 1;
2985          unsigned const_offset = (unsigned) start * elem_size_bytes + base_const_offset;
2986
2987          /* GFX6 doesn't have buffer_store_dwordx3, so make sure not to emit that here either. */
2988          if (unlikely(ctx->program->chip_class == GFX6 && sub_count == 3))
2989             sub_count = 2;
2990
2991          Temp elem = extract_subvector(ctx, src, start, sub_count, RegType::vgpr);
2992          emit_single_mubuf_store(ctx, descriptor, voffset, soffset, elem, const_offset, reorder, slc);
2993
2994          count -= sub_count;
2995          start += sub_count;
2996       }
2997
2998       assert(count == 0);
2999    }
3000 }
3001
3002 Temp emit_single_mubuf_load(isel_context *ctx, Temp descriptor, Temp voffset, Temp soffset,
3003                             unsigned const_offset, unsigned size_dwords, bool allow_reorder = true)
3004 {
3005    assert(size_dwords != 3 || ctx->program->chip_class != GFX6);
3006    assert(size_dwords >= 1 && size_dwords <= 4);
3007
3008    Builder bld(ctx->program, ctx->block);
3009    Temp vdata = bld.tmp(RegClass(RegType::vgpr, size_dwords));
3010    aco_opcode op = (aco_opcode) ((unsigned) aco_opcode::buffer_load_dword + size_dwords - 1);
3011    const_offset = resolve_excess_vmem_const_offset(bld, voffset, const_offset);
3012
3013    Operand voffset_op = voffset.id() ? Operand(as_vgpr(ctx, voffset)) : Operand(v1);
3014    Operand soffset_op = soffset.id() ? Operand(soffset) : Operand(0u);
3015    Builder::Result r = bld.mubuf(op, Definition(vdata), Operand(descriptor), voffset_op, soffset_op, const_offset,
3016                                  /* offen */ !voffset_op.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3017                                  /* disable_wqm */ false, /* glc */ true,
3018                                  /* dlc*/ ctx->program->chip_class >= GFX10, /* slc */ false);
3019
3020    static_cast<MUBUF_instruction *>(r.instr)->can_reorder = allow_reorder;
3021
3022    return vdata;
3023 }
3024
3025 void load_vmem_mubuf(isel_context *ctx, Temp dst, Temp descriptor, Temp voffset, Temp soffset,
3026                      unsigned base_const_offset, unsigned elem_size_bytes, unsigned num_components,
3027                      unsigned stride = 0u, bool allow_combining = true, bool allow_reorder = true)
3028 {
3029    assert(elem_size_bytes == 4 || elem_size_bytes == 8);
3030    assert((num_components * elem_size_bytes / 4) == dst.size());
3031    assert(!!stride != allow_combining);
3032
3033    Builder bld(ctx->program, ctx->block);
3034    unsigned split_cnt = num_components;
3035
3036    if (elem_size_bytes == 8) {
3037       elem_size_bytes = 4;
3038       num_components *= 2;
3039    }
3040
3041    if (!stride)
3042       stride = elem_size_bytes;
3043
3044    unsigned load_size = 1;
3045    if (allow_combining) {
3046       if ((num_components % 4) == 0)
3047          load_size = 4;
3048       else if ((num_components % 3) == 0 && ctx->program->chip_class != GFX6)
3049          load_size = 3;
3050       else if ((num_components % 2) == 0)
3051          load_size = 2;
3052    }
3053
3054    unsigned num_loads = num_components / load_size;
3055    std::array<Temp, NIR_MAX_VEC_COMPONENTS> elems;
3056
3057    for (unsigned i = 0; i < num_loads; ++i) {
3058       unsigned const_offset = i * stride * load_size + base_const_offset;
3059       elems[i] = emit_single_mubuf_load(ctx, descriptor, voffset, soffset, const_offset, load_size, allow_reorder);
3060    }
3061
3062    create_vec_from_array(ctx, elems.data(), num_loads, RegType::vgpr, split_cnt, dst);
3063 }
3064
3065 std::pair<Temp, unsigned> offset_add_from_nir(isel_context *ctx, const std::pair<Temp, unsigned> &base_offset, nir_src *off_src, unsigned stride = 1u)
3066 {
3067    Builder bld(ctx->program, ctx->block);
3068    Temp offset = base_offset.first;
3069    unsigned const_offset = base_offset.second;
3070
3071    if (!nir_src_is_const(*off_src)) {
3072       Temp indirect_offset_arg = get_ssa_temp(ctx, off_src->ssa);
3073       Temp with_stride;
3074
3075       /* Calculate indirect offset with stride */
3076       if (likely(indirect_offset_arg.regClass() == v1))
3077          with_stride = bld.v_mul_imm(bld.def(v1), indirect_offset_arg, stride);
3078       else if (indirect_offset_arg.regClass() == s1)
3079          with_stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), indirect_offset_arg);
3080       else
3081          unreachable("Unsupported register class of indirect offset");
3082
3083       /* Add to the supplied base offset */
3084       if (offset.id() == 0)
3085          offset = with_stride;
3086       else if (unlikely(offset.regClass() == s1 && with_stride.regClass() == s1))
3087          offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), with_stride, offset);
3088       else if (offset.size() == 1 && with_stride.size() == 1)
3089          offset = bld.vadd32(bld.def(v1), with_stride, offset);
3090       else
3091          unreachable("Unsupported register class of indirect offset");
3092    } else {
3093       unsigned const_offset_arg = nir_src_as_uint(*off_src);
3094       const_offset += const_offset_arg * stride;
3095    }
3096
3097    return std::make_pair(offset, const_offset);
3098 }
3099
3100 std::pair<Temp, unsigned> offset_add(isel_context *ctx, const std::pair<Temp, unsigned> &off1, const std::pair<Temp, unsigned> &off2)
3101 {
3102    Builder bld(ctx->program, ctx->block);
3103    Temp offset;
3104
3105    if (off1.first.id() && off2.first.id()) {
3106       if (unlikely(off1.first.regClass() == s1 && off2.first.regClass() == s1))
3107          offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), off1.first, off2.first);
3108       else if (off1.first.size() == 1 && off2.first.size() == 1)
3109          offset = bld.vadd32(bld.def(v1), off1.first, off2.first);
3110       else
3111          unreachable("Unsupported register class of indirect offset");
3112    } else {
3113       offset = off1.first.id() ? off1.first : off2.first;
3114    }
3115
3116    return std::make_pair(offset, off1.second + off2.second);
3117 }
3118
3119 std::pair<Temp, unsigned> offset_mul(isel_context *ctx, const std::pair<Temp, unsigned> &offs, unsigned multiplier)
3120 {
3121    Builder bld(ctx->program, ctx->block);
3122    unsigned const_offset = offs.second * multiplier;
3123
3124    if (!offs.first.id())
3125       return std::make_pair(offs.first, const_offset);
3126
3127    Temp offset = unlikely(offs.first.regClass() == s1)
3128                  ? bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(multiplier), offs.first)
3129                  : bld.v_mul_imm(bld.def(v1), offs.first, multiplier);
3130
3131    return std::make_pair(offset, const_offset);
3132 }
3133
3134 std::pair<Temp, unsigned> get_intrinsic_io_basic_offset(isel_context *ctx, nir_intrinsic_instr *instr, unsigned base_stride, unsigned component_stride)
3135 {
3136    Builder bld(ctx->program, ctx->block);
3137
3138    /* base is the driver_location, which is already multiplied by 4, so is in dwords */
3139    unsigned const_offset = nir_intrinsic_base(instr) * base_stride;
3140    /* component is in bytes */
3141    const_offset += nir_intrinsic_component(instr) * component_stride;
3142
3143    /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
3144    nir_src *off_src = nir_get_io_offset_src(instr);
3145    return offset_add_from_nir(ctx, std::make_pair(Temp(), const_offset), off_src, 4u * base_stride);
3146 }
3147
3148 std::pair<Temp, unsigned> get_intrinsic_io_basic_offset(isel_context *ctx, nir_intrinsic_instr *instr, unsigned stride = 1u)
3149 {
3150    return get_intrinsic_io_basic_offset(ctx, instr, stride, stride);
3151 }
3152
3153 void visit_store_vsgs_output(isel_context *ctx, nir_intrinsic_instr *instr)
3154 {
3155    unsigned write_mask = nir_intrinsic_write_mask(instr);
3156    unsigned component = nir_intrinsic_component(instr);
3157    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
3158    unsigned idx = (nir_intrinsic_base(instr) + component) * 4u;
3159    Operand offset(s1);
3160    Builder bld(ctx->program, ctx->block);
3161
3162    nir_instr *off_instr = instr->src[1].ssa->parent_instr;
3163    if (off_instr->type != nir_instr_type_load_const)
3164       offset = bld.v_mul24_imm(bld.def(v1), get_ssa_temp(ctx, instr->src[1].ssa), 16u);
3165    else
3166       idx += nir_instr_as_load_const(off_instr)->value[0].u32 * 16u;
3167
3168    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8u;
3169    if (ctx->stage == vertex_es) {
3170       Temp esgs_ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_ESGS_VS * 16u));
3171
3172       Temp elems[NIR_MAX_VEC_COMPONENTS * 2];
3173       if (elem_size_bytes == 8) {
3174          for (unsigned i = 0; i < src.size() / 2; i++) {
3175             Temp elem = emit_extract_vector(ctx, src, i, v2);
3176             elems[i*2] = bld.tmp(v1);
3177             elems[i*2+1] = bld.tmp(v1);
3178             bld.pseudo(aco_opcode::p_split_vector, Definition(elems[i*2]), Definition(elems[i*2+1]), elem);
3179          }
3180          write_mask = widen_mask(write_mask, 2);
3181          elem_size_bytes /= 2u;
3182       } else {
3183          for (unsigned i = 0; i < src.size(); i++)
3184             elems[i] = emit_extract_vector(ctx, src, i, v1);
3185       }
3186
3187       while (write_mask) {
3188          unsigned index = u_bit_scan(&write_mask);
3189          unsigned offset = index * elem_size_bytes;
3190          Temp elem = emit_extract_vector(ctx, src, index, RegClass(RegType::vgpr, elem_size_bytes / 4));
3191
3192          Operand vaddr_offset(v1);
3193          unsigned const_offset = idx + offset;
3194          if (const_offset >= 4096u) {
3195             vaddr_offset = bld.copy(bld.def(v1), Operand(const_offset / 4096u * 4096u));
3196             const_offset %= 4096u;
3197          }
3198
3199          aco_ptr<MTBUF_instruction> mtbuf{create_instruction<MTBUF_instruction>(aco_opcode::tbuffer_store_format_x, Format::MTBUF, 4, 0)};
3200          mtbuf->operands[0] = Operand(esgs_ring);
3201          mtbuf->operands[1] = vaddr_offset;
3202          mtbuf->operands[2] = Operand(get_arg(ctx, ctx->args->es2gs_offset));
3203          mtbuf->operands[3] = Operand(elem);
3204          mtbuf->offen = !vaddr_offset.isUndefined();
3205          mtbuf->dfmt = V_008F0C_BUF_DATA_FORMAT_32;
3206          mtbuf->nfmt = V_008F0C_BUF_NUM_FORMAT_UINT;
3207          mtbuf->offset = const_offset;
3208          mtbuf->glc = true;
3209          mtbuf->slc = true;
3210          mtbuf->barrier = barrier_none;
3211          mtbuf->can_reorder = true;
3212          bld.insert(std::move(mtbuf));
3213       }
3214    } else {
3215       unsigned itemsize = ctx->program->info->vs.es_info.esgs_itemsize;
3216
3217       Temp vertex_idx = emit_mbcnt(ctx, bld.def(v1));
3218       Temp wave_idx = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), get_arg(ctx, ctx->args->merged_wave_info), Operand(4u << 16 | 24));
3219       vertex_idx = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), vertex_idx,
3220                             bld.v_mul24_imm(bld.def(v1), as_vgpr(ctx, wave_idx), ctx->program->wave_size));
3221
3222       Temp lds_base = bld.v_mul24_imm(bld.def(v1), vertex_idx, itemsize);
3223       if (!offset.isUndefined())
3224          lds_base = bld.vadd32(bld.def(v1), offset, lds_base);
3225
3226       unsigned align = calculate_lds_alignment(ctx, idx);
3227       store_lds(ctx, elem_size_bytes, src, write_mask, lds_base, idx, align);
3228    }
3229 }
3230
3231 void visit_store_output(isel_context *ctx, nir_intrinsic_instr *instr)
3232 {
3233    if (ctx->stage == vertex_vs ||
3234        ctx->stage == fragment_fs ||
3235        ctx->shader->info.stage == MESA_SHADER_GEOMETRY) {
3236       unsigned write_mask = nir_intrinsic_write_mask(instr);
3237       unsigned component = nir_intrinsic_component(instr);
3238       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
3239       unsigned idx = nir_intrinsic_base(instr) + component;
3240
3241       nir_instr *off_instr = instr->src[1].ssa->parent_instr;
3242       if (off_instr->type != nir_instr_type_load_const) {
3243          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
3244          nir_print_instr(off_instr, stderr);
3245          fprintf(stderr, "\n");
3246       }
3247       idx += nir_instr_as_load_const(off_instr)->value[0].u32 * 4u;
3248
3249       if (instr->src[0].ssa->bit_size == 64)
3250          write_mask = widen_mask(write_mask, 2);
3251
3252       for (unsigned i = 0; i < 8; ++i) {
3253          if (write_mask & (1 << i)) {
3254             ctx->outputs.mask[idx / 4u] |= 1 << (idx % 4u);
3255             ctx->outputs.outputs[idx / 4u][idx % 4u] = emit_extract_vector(ctx, src, i, v1);
3256          }
3257          idx++;
3258       }
3259    } else if (ctx->stage == vertex_es ||
3260               (ctx->stage == vertex_geometry_gs && ctx->shader->info.stage == MESA_SHADER_VERTEX)) {
3261       visit_store_vsgs_output(ctx, instr);
3262    } else {
3263       unreachable("Shader stage not implemented");
3264    }
3265 }
3266
3267 void emit_interp_instr(isel_context *ctx, unsigned idx, unsigned component, Temp src, Temp dst, Temp prim_mask)
3268 {
3269    Temp coord1 = emit_extract_vector(ctx, src, 0, v1);
3270    Temp coord2 = emit_extract_vector(ctx, src, 1, v1);
3271
3272    Builder bld(ctx->program, ctx->block);
3273    Temp tmp = bld.vintrp(aco_opcode::v_interp_p1_f32, bld.def(v1), coord1, bld.m0(prim_mask), idx, component);
3274    bld.vintrp(aco_opcode::v_interp_p2_f32, Definition(dst), coord2, bld.m0(prim_mask), tmp, idx, component);
3275 }
3276
3277 void emit_load_frag_coord(isel_context *ctx, Temp dst, unsigned num_components)
3278 {
3279    aco_ptr<Pseudo_instruction> vec(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1));
3280    for (unsigned i = 0; i < num_components; i++)
3281       vec->operands[i] = Operand(get_arg(ctx, ctx->args->ac.frag_pos[i]));
3282    if (G_0286CC_POS_W_FLOAT_ENA(ctx->program->config->spi_ps_input_ena)) {
3283       assert(num_components == 4);
3284       Builder bld(ctx->program, ctx->block);
3285       vec->operands[3] = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), get_arg(ctx, ctx->args->ac.frag_pos[3]));
3286    }
3287
3288    for (Operand& op : vec->operands)
3289       op = op.isUndefined() ? Operand(0u) : op;
3290
3291    vec->definitions[0] = Definition(dst);
3292    ctx->block->instructions.emplace_back(std::move(vec));
3293    emit_split_vector(ctx, dst, num_components);
3294    return;
3295 }
3296
3297 void visit_load_interpolated_input(isel_context *ctx, nir_intrinsic_instr *instr)
3298 {
3299    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3300    Temp coords = get_ssa_temp(ctx, instr->src[0].ssa);
3301    unsigned idx = nir_intrinsic_base(instr);
3302    unsigned component = nir_intrinsic_component(instr);
3303    Temp prim_mask = get_arg(ctx, ctx->args->ac.prim_mask);
3304
3305    nir_const_value* offset = nir_src_as_const_value(instr->src[1]);
3306    if (offset) {
3307       assert(offset->u32 == 0);
3308    } else {
3309       /* the lower 15bit of the prim_mask contain the offset into LDS
3310        * while the upper bits contain the number of prims */
3311       Temp offset_src = get_ssa_temp(ctx, instr->src[1].ssa);
3312       assert(offset_src.regClass() == s1 && "TODO: divergent offsets...");
3313       Builder bld(ctx->program, ctx->block);
3314       Temp stride = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), prim_mask, Operand(16u));
3315       stride = bld.sop1(aco_opcode::s_bcnt1_i32_b32, bld.def(s1), bld.def(s1, scc), stride);
3316       stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, Operand(48u));
3317       offset_src = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, offset_src);
3318       prim_mask = bld.sop2(aco_opcode::s_add_i32, bld.def(s1, m0), bld.def(s1, scc), offset_src, prim_mask);
3319    }
3320
3321    if (instr->dest.ssa.num_components == 1) {
3322       emit_interp_instr(ctx, idx, component, coords, dst, prim_mask);
3323    } else {
3324       aco_ptr<Pseudo_instruction> vec(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.ssa.num_components, 1));
3325       for (unsigned i = 0; i < instr->dest.ssa.num_components; i++)
3326       {
3327          Temp tmp = {ctx->program->allocateId(), v1};
3328          emit_interp_instr(ctx, idx, component+i, coords, tmp, prim_mask);
3329          vec->operands[i] = Operand(tmp);
3330       }
3331       vec->definitions[0] = Definition(dst);
3332       ctx->block->instructions.emplace_back(std::move(vec));
3333    }
3334 }
3335
3336 bool check_vertex_fetch_size(isel_context *ctx, const ac_data_format_info *vtx_info,
3337                              unsigned offset, unsigned stride, unsigned channels)
3338 {
3339    unsigned vertex_byte_size = vtx_info->chan_byte_size * channels;
3340    if (vtx_info->chan_byte_size != 4 && channels == 3)
3341       return false;
3342    return (ctx->options->chip_class != GFX6 && ctx->options->chip_class != GFX10) ||
3343           (offset % vertex_byte_size == 0 && stride % vertex_byte_size == 0);
3344 }
3345
3346 uint8_t get_fetch_data_format(isel_context *ctx, const ac_data_format_info *vtx_info,
3347                               unsigned offset, unsigned stride, unsigned *channels)
3348 {
3349    if (!vtx_info->chan_byte_size) {
3350       *channels = vtx_info->num_channels;
3351       return vtx_info->chan_format;
3352    }
3353
3354    unsigned num_channels = *channels;
3355    if (!check_vertex_fetch_size(ctx, vtx_info, offset, stride, *channels)) {
3356       unsigned new_channels = num_channels + 1;
3357       /* first, assume more loads is worse and try using a larger data format */
3358       while (new_channels <= 4 && !check_vertex_fetch_size(ctx, vtx_info, offset, stride, new_channels)) {
3359          new_channels++;
3360          /* don't make the attribute potentially out-of-bounds */
3361          if (offset + new_channels * vtx_info->chan_byte_size > stride)
3362             new_channels = 5;
3363       }
3364
3365       if (new_channels == 5) {
3366          /* then try decreasing load size (at the cost of more loads) */
3367          new_channels = *channels;
3368          while (new_channels > 1 && !check_vertex_fetch_size(ctx, vtx_info, offset, stride, new_channels))
3369             new_channels--;
3370       }
3371
3372       if (new_channels < *channels)
3373          *channels = new_channels;
3374       num_channels = new_channels;
3375    }
3376
3377    switch (vtx_info->chan_format) {
3378    case V_008F0C_BUF_DATA_FORMAT_8:
3379       return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8, V_008F0C_BUF_DATA_FORMAT_8_8,
3380                          V_008F0C_BUF_DATA_FORMAT_INVALID, V_008F0C_BUF_DATA_FORMAT_8_8_8_8}[num_channels - 1];
3381    case V_008F0C_BUF_DATA_FORMAT_16:
3382       return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16, V_008F0C_BUF_DATA_FORMAT_16_16,
3383                          V_008F0C_BUF_DATA_FORMAT_INVALID, V_008F0C_BUF_DATA_FORMAT_16_16_16_16}[num_channels - 1];
3384    case V_008F0C_BUF_DATA_FORMAT_32:
3385       return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32, V_008F0C_BUF_DATA_FORMAT_32_32,
3386                          V_008F0C_BUF_DATA_FORMAT_32_32_32, V_008F0C_BUF_DATA_FORMAT_32_32_32_32}[num_channels - 1];
3387    }
3388    unreachable("shouldn't reach here");
3389    return V_008F0C_BUF_DATA_FORMAT_INVALID;
3390 }
3391
3392 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
3393  * so we may need to fix it up. */
3394 Temp adjust_vertex_fetch_alpha(isel_context *ctx, unsigned adjustment, Temp alpha)
3395 {
3396    Builder bld(ctx->program, ctx->block);
3397
3398    if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
3399       alpha = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), alpha);
3400
3401    /* For the integer-like cases, do a natural sign extension.
3402     *
3403     * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
3404     * and happen to contain 0, 1, 2, 3 as the two LSBs of the
3405     * exponent.
3406     */
3407    alpha = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(adjustment == RADV_ALPHA_ADJUST_SNORM ? 7u : 30u), alpha);
3408    alpha = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(30u), alpha);
3409
3410    /* Convert back to the right type. */
3411    if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
3412       alpha = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), alpha);
3413       Temp clamp = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0xbf800000u), alpha);
3414       alpha = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xbf800000u), alpha, clamp);
3415    } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
3416       alpha = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), alpha);
3417    }
3418
3419    return alpha;
3420 }
3421
3422 void visit_load_input(isel_context *ctx, nir_intrinsic_instr *instr)
3423 {
3424    Builder bld(ctx->program, ctx->block);
3425    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3426    if (ctx->shader->info.stage == MESA_SHADER_VERTEX) {
3427
3428       nir_instr *off_instr = instr->src[0].ssa->parent_instr;
3429       if (off_instr->type != nir_instr_type_load_const) {
3430          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
3431          nir_print_instr(off_instr, stderr);
3432          fprintf(stderr, "\n");
3433       }
3434       uint32_t offset = nir_instr_as_load_const(off_instr)->value[0].u32;
3435
3436       Temp vertex_buffers = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->vertex_buffers));
3437
3438       unsigned location = nir_intrinsic_base(instr) / 4 - VERT_ATTRIB_GENERIC0 + offset;
3439       unsigned component = nir_intrinsic_component(instr);
3440       unsigned attrib_binding = ctx->options->key.vs.vertex_attribute_bindings[location];
3441       uint32_t attrib_offset = ctx->options->key.vs.vertex_attribute_offsets[location];
3442       uint32_t attrib_stride = ctx->options->key.vs.vertex_attribute_strides[location];
3443       unsigned attrib_format = ctx->options->key.vs.vertex_attribute_formats[location];
3444
3445       unsigned dfmt = attrib_format & 0xf;
3446       unsigned nfmt = (attrib_format >> 4) & 0x7;
3447       const struct ac_data_format_info *vtx_info = ac_get_data_format_info(dfmt);
3448
3449       unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa) << component;
3450       unsigned num_channels = MIN2(util_last_bit(mask), vtx_info->num_channels);
3451       unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> (location * 2)) & 3;
3452       bool post_shuffle = ctx->options->key.vs.post_shuffle & (1 << location);
3453       if (post_shuffle)
3454          num_channels = MAX2(num_channels, 3);
3455
3456       Operand off = bld.copy(bld.def(s1), Operand(attrib_binding * 16u));
3457       Temp list = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), vertex_buffers, off);
3458
3459       Temp index;
3460       if (ctx->options->key.vs.instance_rate_inputs & (1u << location)) {
3461          uint32_t divisor = ctx->options->key.vs.instance_rate_divisors[location];
3462          Temp start_instance = get_arg(ctx, ctx->args->ac.start_instance);
3463          if (divisor) {
3464             Temp instance_id = get_arg(ctx, ctx->args->ac.instance_id);
3465             if (divisor != 1) {
3466                Temp divided = bld.tmp(v1);
3467                emit_v_div_u32(ctx, divided, as_vgpr(ctx, instance_id), divisor);
3468                index = bld.vadd32(bld.def(v1), start_instance, divided);
3469             } else {
3470                index = bld.vadd32(bld.def(v1), start_instance, instance_id);
3471             }
3472          } else {
3473             index = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), start_instance);
3474          }
3475       } else {
3476          index = bld.vadd32(bld.def(v1),
3477                             get_arg(ctx, ctx->args->ac.base_vertex),
3478                             get_arg(ctx, ctx->args->ac.vertex_id));
3479       }
3480
3481       Temp channels[num_channels];
3482       unsigned channel_start = 0;
3483       bool direct_fetch = false;
3484
3485       /* skip unused channels at the start */
3486       if (vtx_info->chan_byte_size && !post_shuffle) {
3487          channel_start = ffs(mask) - 1;
3488          for (unsigned i = 0; i < channel_start; i++)
3489             channels[i] = Temp(0, s1);
3490       } else if (vtx_info->chan_byte_size && post_shuffle && !(mask & 0x8)) {
3491          num_channels = 3 - (ffs(mask) - 1);
3492       }
3493
3494       /* load channels */
3495       while (channel_start < num_channels) {
3496          unsigned fetch_size = num_channels - channel_start;
3497          unsigned fetch_offset = attrib_offset + channel_start * vtx_info->chan_byte_size;
3498          bool expanded = false;
3499
3500          /* use MUBUF when possible to avoid possible alignment issues */
3501          /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
3502          bool use_mubuf = (nfmt == V_008F0C_BUF_NUM_FORMAT_FLOAT ||
3503                            nfmt == V_008F0C_BUF_NUM_FORMAT_UINT ||
3504                            nfmt == V_008F0C_BUF_NUM_FORMAT_SINT) &&
3505                           vtx_info->chan_byte_size == 4;
3506          unsigned fetch_dfmt = V_008F0C_BUF_DATA_FORMAT_INVALID;
3507          if (!use_mubuf) {
3508             fetch_dfmt = get_fetch_data_format(ctx, vtx_info, fetch_offset, attrib_stride, &fetch_size);
3509          } else {
3510             if (fetch_size == 3 && ctx->options->chip_class == GFX6) {
3511                /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
3512                fetch_size = 4;
3513                expanded = true;
3514             }
3515          }
3516
3517          Temp fetch_index = index;
3518          if (attrib_stride != 0 && fetch_offset > attrib_stride) {
3519             fetch_index = bld.vadd32(bld.def(v1), Operand(fetch_offset / attrib_stride), fetch_index);
3520             fetch_offset = fetch_offset % attrib_stride;
3521          }
3522
3523          Operand soffset(0u);
3524          if (fetch_offset >= 4096) {
3525             soffset = bld.copy(bld.def(s1), Operand(fetch_offset / 4096 * 4096));
3526             fetch_offset %= 4096;
3527          }
3528
3529          aco_opcode opcode;
3530          switch (fetch_size) {
3531          case 1:
3532             opcode = use_mubuf ? aco_opcode::buffer_load_dword : aco_opcode::tbuffer_load_format_x;
3533             break;
3534          case 2:
3535             opcode = use_mubuf ? aco_opcode::buffer_load_dwordx2 : aco_opcode::tbuffer_load_format_xy;
3536             break;
3537          case 3:
3538             assert(ctx->options->chip_class >= GFX7 ||
3539                    (!use_mubuf && ctx->options->chip_class == GFX6));
3540             opcode = use_mubuf ? aco_opcode::buffer_load_dwordx3 : aco_opcode::tbuffer_load_format_xyz;
3541             break;
3542          case 4:
3543             opcode = use_mubuf ? aco_opcode::buffer_load_dwordx4 : aco_opcode::tbuffer_load_format_xyzw;
3544             break;
3545          default:
3546             unreachable("Unimplemented load_input vector size");
3547          }
3548
3549          Temp fetch_dst;
3550          if (channel_start == 0 && fetch_size == dst.size() && !post_shuffle &&
3551              !expanded && (alpha_adjust == RADV_ALPHA_ADJUST_NONE ||
3552                            num_channels <= 3)) {
3553             direct_fetch = true;
3554             fetch_dst = dst;
3555          } else {
3556             fetch_dst = bld.tmp(RegType::vgpr, fetch_size);
3557          }
3558
3559          if (use_mubuf) {
3560             Instruction *mubuf = bld.mubuf(opcode,
3561                                            Definition(fetch_dst), list, fetch_index, soffset,
3562                                            fetch_offset, false, true).instr;
3563             static_cast<MUBUF_instruction*>(mubuf)->can_reorder = true;
3564          } else {
3565             Instruction *mtbuf = bld.mtbuf(opcode,
3566                                            Definition(fetch_dst), list, fetch_index, soffset,
3567                                            fetch_dfmt, nfmt, fetch_offset, false, true).instr;
3568             static_cast<MTBUF_instruction*>(mtbuf)->can_reorder = true;
3569          }
3570
3571          emit_split_vector(ctx, fetch_dst, fetch_dst.size());
3572
3573          if (fetch_size == 1) {
3574             channels[channel_start] = fetch_dst;
3575          } else {
3576             for (unsigned i = 0; i < MIN2(fetch_size, num_channels - channel_start); i++)
3577                channels[channel_start + i] = emit_extract_vector(ctx, fetch_dst, i, v1);
3578          }
3579
3580          channel_start += fetch_size;
3581       }
3582
3583       if (!direct_fetch) {
3584          bool is_float = nfmt != V_008F0C_BUF_NUM_FORMAT_UINT &&
3585                          nfmt != V_008F0C_BUF_NUM_FORMAT_SINT;
3586
3587          static const unsigned swizzle_normal[4] = {0, 1, 2, 3};
3588          static const unsigned swizzle_post_shuffle[4] = {2, 1, 0, 3};
3589          const unsigned *swizzle = post_shuffle ? swizzle_post_shuffle : swizzle_normal;
3590
3591          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
3592          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
3593          unsigned num_temp = 0;
3594          for (unsigned i = 0; i < dst.size(); i++) {
3595             unsigned idx = i + component;
3596             if (swizzle[idx] < num_channels && channels[swizzle[idx]].id()) {
3597                Temp channel = channels[swizzle[idx]];
3598                if (idx == 3 && alpha_adjust != RADV_ALPHA_ADJUST_NONE)
3599                   channel = adjust_vertex_fetch_alpha(ctx, alpha_adjust, channel);
3600                vec->operands[i] = Operand(channel);
3601
3602                num_temp++;
3603                elems[i] = channel;
3604             } else if (is_float && idx == 3) {
3605                vec->operands[i] = Operand(0x3f800000u);
3606             } else if (!is_float && idx == 3) {
3607                vec->operands[i] = Operand(1u);
3608             } else {
3609                vec->operands[i] = Operand(0u);
3610             }
3611          }
3612          vec->definitions[0] = Definition(dst);
3613          ctx->block->instructions.emplace_back(std::move(vec));
3614          emit_split_vector(ctx, dst, dst.size());
3615
3616          if (num_temp == dst.size())
3617             ctx->allocated_vec.emplace(dst.id(), elems);
3618       }
3619    } else if (ctx->shader->info.stage == MESA_SHADER_FRAGMENT) {
3620       unsigned offset_idx = instr->intrinsic == nir_intrinsic_load_input ? 0 : 1;
3621       nir_instr *off_instr = instr->src[offset_idx].ssa->parent_instr;
3622       if (off_instr->type != nir_instr_type_load_const ||
3623           nir_instr_as_load_const(off_instr)->value[0].u32 != 0) {
3624          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
3625          nir_print_instr(off_instr, stderr);
3626          fprintf(stderr, "\n");
3627       }
3628
3629       Temp prim_mask = get_arg(ctx, ctx->args->ac.prim_mask);
3630       nir_const_value* offset = nir_src_as_const_value(instr->src[offset_idx]);
3631       if (offset) {
3632          assert(offset->u32 == 0);
3633       } else {
3634          /* the lower 15bit of the prim_mask contain the offset into LDS
3635           * while the upper bits contain the number of prims */
3636          Temp offset_src = get_ssa_temp(ctx, instr->src[offset_idx].ssa);
3637          assert(offset_src.regClass() == s1 && "TODO: divergent offsets...");
3638          Builder bld(ctx->program, ctx->block);
3639          Temp stride = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), prim_mask, Operand(16u));
3640          stride = bld.sop1(aco_opcode::s_bcnt1_i32_b32, bld.def(s1), bld.def(s1, scc), stride);
3641          stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, Operand(48u));
3642          offset_src = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, offset_src);
3643          prim_mask = bld.sop2(aco_opcode::s_add_i32, bld.def(s1, m0), bld.def(s1, scc), offset_src, prim_mask);
3644       }
3645
3646       unsigned idx = nir_intrinsic_base(instr);
3647       unsigned component = nir_intrinsic_component(instr);
3648       unsigned vertex_id = 2; /* P0 */
3649
3650       if (instr->intrinsic == nir_intrinsic_load_input_vertex) {
3651          nir_const_value* src0 = nir_src_as_const_value(instr->src[0]);
3652          switch (src0->u32) {
3653          case 0:
3654             vertex_id = 2; /* P0 */
3655             break;
3656          case 1:
3657             vertex_id = 0; /* P10 */
3658             break;
3659          case 2:
3660             vertex_id = 1; /* P20 */
3661             break;
3662          default:
3663             unreachable("invalid vertex index");
3664          }
3665       }
3666
3667       if (dst.size() == 1) {
3668          bld.vintrp(aco_opcode::v_interp_mov_f32, Definition(dst), Operand(vertex_id), bld.m0(prim_mask), idx, component);
3669       } else {
3670          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
3671          for (unsigned i = 0; i < dst.size(); i++)
3672             vec->operands[i] = bld.vintrp(aco_opcode::v_interp_mov_f32, bld.def(v1), Operand(vertex_id), bld.m0(prim_mask), idx, component + i);
3673          vec->definitions[0] = Definition(dst);
3674          bld.insert(std::move(vec));
3675       }
3676
3677    } else {
3678       unreachable("Shader stage not implemented");
3679    }
3680 }
3681
3682 void visit_load_per_vertex_input(isel_context *ctx, nir_intrinsic_instr *instr)
3683 {
3684    assert(ctx->stage == vertex_geometry_gs || ctx->stage == geometry_gs);
3685    assert(ctx->shader->info.stage == MESA_SHADER_GEOMETRY);
3686
3687    Builder bld(ctx->program, ctx->block);
3688    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3689
3690    Temp offset = Temp();
3691    if (instr->src[0].ssa->parent_instr->type != nir_instr_type_load_const) {
3692       /* better code could be created, but this case probably doesn't happen
3693        * much in practice */
3694       Temp indirect_vertex = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
3695       for (unsigned i = 0; i < ctx->shader->info.gs.vertices_in; i++) {
3696          Temp elem;
3697          if (ctx->stage == vertex_geometry_gs) {
3698             elem = get_arg(ctx, ctx->args->gs_vtx_offset[i / 2u * 2u]);
3699             if (i % 2u)
3700                elem = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(16u), elem);
3701          } else {
3702             elem = get_arg(ctx, ctx->args->gs_vtx_offset[i]);
3703          }
3704          if (offset.id()) {
3705             Temp cond = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.hint_vcc(bld.def(s2)),
3706                                  Operand(i), indirect_vertex);
3707             offset = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), offset, elem, cond);
3708          } else {
3709             offset = elem;
3710          }
3711       }
3712       if (ctx->stage == vertex_geometry_gs)
3713          offset = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0xffffu), offset);
3714    } else {
3715       unsigned vertex = nir_src_as_uint(instr->src[0]);
3716       if (ctx->stage == vertex_geometry_gs)
3717          offset = bld.vop3(
3718          aco_opcode::v_bfe_u32, bld.def(v1), get_arg(ctx, ctx->args->gs_vtx_offset[vertex / 2u * 2u]),
3719             Operand((vertex % 2u) * 16u), Operand(16u));
3720       else
3721          offset = get_arg(ctx, ctx->args->gs_vtx_offset[vertex]);
3722    }
3723
3724    unsigned const_offset = nir_intrinsic_base(instr);
3725    const_offset += nir_intrinsic_component(instr);
3726
3727    nir_instr *off_instr = instr->src[1].ssa->parent_instr;
3728    if (off_instr->type != nir_instr_type_load_const) {
3729       Temp indirect_offset = get_ssa_temp(ctx, instr->src[1].ssa);
3730       offset = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u),
3731                         bld.vadd32(bld.def(v1), indirect_offset, offset));
3732    } else {
3733       const_offset += nir_instr_as_load_const(off_instr)->value[0].u32 * 4u;
3734    }
3735    const_offset *= 4u;
3736
3737    offset = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), offset);
3738
3739    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
3740    if (ctx->stage == geometry_gs) {
3741       Temp esgs_ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_ESGS_GS * 16u));
3742
3743       const_offset *= ctx->program->wave_size;
3744
3745       std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
3746       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(
3747          aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.ssa.num_components, 1)};
3748       for (unsigned i = 0; i < instr->dest.ssa.num_components; i++) {
3749          Temp subelems[2];
3750          for (unsigned j = 0; j < elem_size_bytes / 4; j++) {
3751             Operand soffset(0u);
3752             if (const_offset >= 4096u)
3753                soffset = bld.copy(bld.def(s1), Operand(const_offset / 4096u * 4096u));
3754
3755             aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(aco_opcode::buffer_load_dword, Format::MUBUF, 3, 1)};
3756             mubuf->definitions[0] = bld.def(v1);
3757             subelems[j] = mubuf->definitions[0].getTemp();
3758             mubuf->operands[0] = Operand(esgs_ring);
3759             mubuf->operands[1] = Operand(offset);
3760             mubuf->operands[2] = Operand(soffset);
3761             mubuf->offen = true;
3762             mubuf->offset = const_offset % 4096u;
3763             mubuf->glc = true;
3764             mubuf->dlc = ctx->options->chip_class >= GFX10;
3765             mubuf->barrier = barrier_none;
3766             mubuf->can_reorder = true;
3767             bld.insert(std::move(mubuf));
3768
3769             const_offset += ctx->program->wave_size * 4u;
3770          }
3771
3772          if (elem_size_bytes == 4)
3773             elems[i] = subelems[0];
3774          else
3775             elems[i] = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), subelems[0], subelems[1]);
3776          vec->operands[i] = Operand(elems[i]);
3777       }
3778       vec->definitions[0] = Definition(dst);
3779       ctx->block->instructions.emplace_back(std::move(vec));
3780       ctx->allocated_vec.emplace(dst.id(), elems);
3781    } else {
3782       unsigned align = calculate_lds_alignment(ctx, const_offset);
3783       load_lds(ctx, elem_size_bytes, dst, offset, const_offset, align);
3784    }
3785 }
3786
3787 void visit_load_tess_coord(isel_context *ctx, nir_intrinsic_instr *instr)
3788 {
3789    assert(ctx->shader->info.stage == MESA_SHADER_TESS_EVAL);
3790
3791    Builder bld(ctx->program, ctx->block);
3792    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3793
3794    Operand tes_u(get_arg(ctx, ctx->args->tes_u));
3795    Operand tes_v(get_arg(ctx, ctx->args->tes_v));
3796    Operand tes_w(0u);
3797
3798    if (ctx->shader->info.tess.primitive_mode == GL_TRIANGLES) {
3799       Temp tmp = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), tes_u, tes_v);
3800       tmp = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), Operand(0x3f800000u /* 1.0f */), tmp);
3801       tes_w = Operand(tmp);
3802    }
3803
3804    Temp tess_coord = bld.pseudo(aco_opcode::p_create_vector, Definition(dst), tes_u, tes_v, tes_w);
3805    emit_split_vector(ctx, tess_coord, 3);
3806 }
3807
3808 Temp load_desc_ptr(isel_context *ctx, unsigned desc_set)
3809 {
3810    if (ctx->program->info->need_indirect_descriptor_sets) {
3811       Builder bld(ctx->program, ctx->block);
3812       Temp ptr64 = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->descriptor_sets[0]));
3813       Operand off = bld.copy(bld.def(s1), Operand(desc_set << 2));
3814       return bld.smem(aco_opcode::s_load_dword, bld.def(s1), ptr64, off);//, false, false, false);
3815    }
3816
3817    return get_arg(ctx, ctx->args->descriptor_sets[desc_set]);
3818 }
3819
3820
3821 void visit_load_resource(isel_context *ctx, nir_intrinsic_instr *instr)
3822 {
3823    Builder bld(ctx->program, ctx->block);
3824    Temp index = get_ssa_temp(ctx, instr->src[0].ssa);
3825    if (!ctx->divergent_vals[instr->dest.ssa.index])
3826       index = bld.as_uniform(index);
3827    unsigned desc_set = nir_intrinsic_desc_set(instr);
3828    unsigned binding = nir_intrinsic_binding(instr);
3829
3830    Temp desc_ptr;
3831    radv_pipeline_layout *pipeline_layout = ctx->options->layout;
3832    radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
3833    unsigned offset = layout->binding[binding].offset;
3834    unsigned stride;
3835    if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
3836        layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
3837       unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start + layout->binding[binding].dynamic_offset_offset;
3838       desc_ptr = get_arg(ctx, ctx->args->ac.push_constants);
3839       offset = pipeline_layout->push_constant_size + 16 * idx;
3840       stride = 16;
3841    } else {
3842       desc_ptr = load_desc_ptr(ctx, desc_set);
3843       stride = layout->binding[binding].size;
3844    }
3845
3846    nir_const_value* nir_const_index = nir_src_as_const_value(instr->src[0]);
3847    unsigned const_index = nir_const_index ? nir_const_index->u32 : 0;
3848    if (stride != 1) {
3849       if (nir_const_index) {
3850          const_index = const_index * stride;
3851       } else if (index.type() == RegType::vgpr) {
3852          bool index24bit = layout->binding[binding].array_size <= 0x1000000;
3853          index = bld.v_mul_imm(bld.def(v1), index, stride, index24bit);
3854       } else {
3855          index = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), Operand(index));
3856       }
3857    }
3858    if (offset) {
3859       if (nir_const_index) {
3860          const_index = const_index + offset;
3861       } else if (index.type() == RegType::vgpr) {
3862          index = bld.vadd32(bld.def(v1), Operand(offset), index);
3863       } else {
3864          index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset), Operand(index));
3865       }
3866    }
3867
3868    if (nir_const_index && const_index == 0) {
3869       index = desc_ptr;
3870    } else if (index.type() == RegType::vgpr) {
3871       index = bld.vadd32(bld.def(v1),
3872                          nir_const_index ? Operand(const_index) : Operand(index),
3873                          Operand(desc_ptr));
3874    } else {
3875       index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
3876                        nir_const_index ? Operand(const_index) : Operand(index),
3877                        Operand(desc_ptr));
3878    }
3879
3880    bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), index);
3881 }
3882
3883 void load_buffer(isel_context *ctx, unsigned num_components, Temp dst,
3884                  Temp rsrc, Temp offset, bool glc=false, bool readonly=true)
3885 {
3886    Builder bld(ctx->program, ctx->block);
3887
3888    unsigned num_bytes = dst.size() * 4;
3889    bool dlc = glc && ctx->options->chip_class >= GFX10;
3890
3891    aco_opcode op;
3892    if (dst.type() == RegType::vgpr || (ctx->options->chip_class < GFX8 && !readonly)) {
3893       Operand vaddr = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
3894       Operand soffset = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
3895       unsigned const_offset = 0;
3896
3897       Temp lower = Temp();
3898       if (num_bytes > 16) {
3899          assert(num_components == 3 || num_components == 4);
3900          op = aco_opcode::buffer_load_dwordx4;
3901          lower = bld.tmp(v4);
3902          aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
3903          mubuf->definitions[0] = Definition(lower);
3904          mubuf->operands[0] = Operand(rsrc);
3905          mubuf->operands[1] = vaddr;
3906          mubuf->operands[2] = soffset;
3907          mubuf->offen = (offset.type() == RegType::vgpr);
3908          mubuf->glc = glc;
3909          mubuf->dlc = dlc;
3910          mubuf->barrier = readonly ? barrier_none : barrier_buffer;
3911          mubuf->can_reorder = readonly;
3912          bld.insert(std::move(mubuf));
3913          emit_split_vector(ctx, lower, 2);
3914          num_bytes -= 16;
3915          const_offset = 16;
3916       } else if (num_bytes == 12 && ctx->options->chip_class == GFX6) {
3917          /* GFX6 doesn't support loading vec3, expand to vec4. */
3918          num_bytes = 16;
3919       }
3920
3921       switch (num_bytes) {
3922          case 4:
3923             op = aco_opcode::buffer_load_dword;
3924             break;
3925          case 8:
3926             op = aco_opcode::buffer_load_dwordx2;
3927             break;
3928          case 12:
3929             assert(ctx->options->chip_class > GFX6);
3930             op = aco_opcode::buffer_load_dwordx3;
3931             break;
3932          case 16:
3933             op = aco_opcode::buffer_load_dwordx4;
3934             break;
3935          default:
3936             unreachable("Load SSBO not implemented for this size.");
3937       }
3938       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
3939       mubuf->operands[0] = Operand(rsrc);
3940       mubuf->operands[1] = vaddr;
3941       mubuf->operands[2] = soffset;
3942       mubuf->offen = (offset.type() == RegType::vgpr);
3943       mubuf->glc = glc;
3944       mubuf->dlc = dlc;
3945       mubuf->barrier = readonly ? barrier_none : barrier_buffer;
3946       mubuf->can_reorder = readonly;
3947       mubuf->offset = const_offset;
3948       aco_ptr<Instruction> instr = std::move(mubuf);
3949
3950       if (dst.size() > 4) {
3951          assert(lower != Temp());
3952          Temp upper = bld.tmp(RegType::vgpr, dst.size() - lower.size());
3953          instr->definitions[0] = Definition(upper);
3954          bld.insert(std::move(instr));
3955          if (dst.size() == 8)
3956             emit_split_vector(ctx, upper, 2);
3957          instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size() / 2, 1));
3958          instr->operands[0] = Operand(emit_extract_vector(ctx, lower, 0, v2));
3959          instr->operands[1] = Operand(emit_extract_vector(ctx, lower, 1, v2));
3960          instr->operands[2] = Operand(emit_extract_vector(ctx, upper, 0, v2));
3961          if (dst.size() == 8)
3962             instr->operands[3] = Operand(emit_extract_vector(ctx, upper, 1, v2));
3963       } else if (dst.size() == 3 && ctx->options->chip_class == GFX6) {
3964          Temp vec = bld.tmp(v4);
3965          instr->definitions[0] = Definition(vec);
3966          bld.insert(std::move(instr));
3967          emit_split_vector(ctx, vec, 4);
3968
3969          instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, 3, 1));
3970          instr->operands[0] = Operand(emit_extract_vector(ctx, vec, 0, v1));
3971          instr->operands[1] = Operand(emit_extract_vector(ctx, vec, 1, v1));
3972          instr->operands[2] = Operand(emit_extract_vector(ctx, vec, 2, v1));
3973       }
3974
3975       if (dst.type() == RegType::sgpr) {
3976          Temp vec = bld.tmp(RegType::vgpr, dst.size());
3977          instr->definitions[0] = Definition(vec);
3978          bld.insert(std::move(instr));
3979          expand_vector(ctx, vec, dst, num_components, (1 << num_components) - 1);
3980       } else {
3981          instr->definitions[0] = Definition(dst);
3982          bld.insert(std::move(instr));
3983          emit_split_vector(ctx, dst, num_components);
3984       }
3985    } else {
3986       switch (num_bytes) {
3987          case 4:
3988             op = aco_opcode::s_buffer_load_dword;
3989             break;
3990          case 8:
3991             op = aco_opcode::s_buffer_load_dwordx2;
3992             break;
3993          case 12:
3994          case 16:
3995             op = aco_opcode::s_buffer_load_dwordx4;
3996             break;
3997          case 24:
3998          case 32:
3999             op = aco_opcode::s_buffer_load_dwordx8;
4000             break;
4001          default:
4002             unreachable("Load SSBO not implemented for this size.");
4003       }
4004       aco_ptr<SMEM_instruction> load{create_instruction<SMEM_instruction>(op, Format::SMEM, 2, 1)};
4005       load->operands[0] = Operand(rsrc);
4006       load->operands[1] = Operand(bld.as_uniform(offset));
4007       assert(load->operands[1].getTemp().type() == RegType::sgpr);
4008       load->definitions[0] = Definition(dst);
4009       load->glc = glc;
4010       load->dlc = dlc;
4011       load->barrier = readonly ? barrier_none : barrier_buffer;
4012       load->can_reorder = false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
4013       assert(ctx->options->chip_class >= GFX8 || !glc);
4014
4015       /* trim vector */
4016       if (dst.size() == 3) {
4017          Temp vec = bld.tmp(s4);
4018          load->definitions[0] = Definition(vec);
4019          bld.insert(std::move(load));
4020          emit_split_vector(ctx, vec, 4);
4021
4022          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4023                     emit_extract_vector(ctx, vec, 0, s1),
4024                     emit_extract_vector(ctx, vec, 1, s1),
4025                     emit_extract_vector(ctx, vec, 2, s1));
4026       } else if (dst.size() == 6) {
4027          Temp vec = bld.tmp(s8);
4028          load->definitions[0] = Definition(vec);
4029          bld.insert(std::move(load));
4030          emit_split_vector(ctx, vec, 4);
4031
4032          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4033                     emit_extract_vector(ctx, vec, 0, s2),
4034                     emit_extract_vector(ctx, vec, 1, s2),
4035                     emit_extract_vector(ctx, vec, 2, s2));
4036       } else {
4037          bld.insert(std::move(load));
4038       }
4039       emit_split_vector(ctx, dst, num_components);
4040    }
4041 }
4042
4043 void visit_load_ubo(isel_context *ctx, nir_intrinsic_instr *instr)
4044 {
4045    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4046    Temp rsrc = get_ssa_temp(ctx, instr->src[0].ssa);
4047
4048    Builder bld(ctx->program, ctx->block);
4049
4050    nir_intrinsic_instr* idx_instr = nir_instr_as_intrinsic(instr->src[0].ssa->parent_instr);
4051    unsigned desc_set = nir_intrinsic_desc_set(idx_instr);
4052    unsigned binding = nir_intrinsic_binding(idx_instr);
4053    radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
4054
4055    if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
4056       uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
4057                            S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
4058                            S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
4059                            S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
4060       if (ctx->options->chip_class >= GFX10) {
4061          desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
4062                       S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
4063                       S_008F0C_RESOURCE_LEVEL(1);
4064       } else {
4065          desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
4066                       S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
4067       }
4068       Temp upper_dwords = bld.pseudo(aco_opcode::p_create_vector, bld.def(s3),
4069                                      Operand(S_008F04_BASE_ADDRESS_HI(ctx->options->address32_hi)),
4070                                      Operand(0xFFFFFFFFu),
4071                                      Operand(desc_type));
4072       rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
4073                         rsrc, upper_dwords);
4074    } else {
4075       rsrc = convert_pointer_to_64_bit(ctx, rsrc);
4076       rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
4077    }
4078
4079    load_buffer(ctx, instr->num_components, dst, rsrc, get_ssa_temp(ctx, instr->src[1].ssa));
4080 }
4081
4082 void visit_load_push_constant(isel_context *ctx, nir_intrinsic_instr *instr)
4083 {
4084    Builder bld(ctx->program, ctx->block);
4085    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4086
4087    unsigned offset = nir_intrinsic_base(instr);
4088    nir_const_value *index_cv = nir_src_as_const_value(instr->src[0]);
4089    if (index_cv && instr->dest.ssa.bit_size == 32) {
4090
4091       unsigned count = instr->dest.ssa.num_components;
4092       unsigned start = (offset + index_cv->u32) / 4u;
4093       start -= ctx->args->ac.base_inline_push_consts;
4094       if (start + count <= ctx->args->ac.num_inline_push_consts) {
4095          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
4096          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
4097          for (unsigned i = 0; i < count; ++i) {
4098             elems[i] = get_arg(ctx, ctx->args->ac.inline_push_consts[start + i]);
4099             vec->operands[i] = Operand{elems[i]};
4100          }
4101          vec->definitions[0] = Definition(dst);
4102          ctx->block->instructions.emplace_back(std::move(vec));
4103          ctx->allocated_vec.emplace(dst.id(), elems);
4104          return;
4105       }
4106    }
4107
4108    Temp index = bld.as_uniform(get_ssa_temp(ctx, instr->src[0].ssa));
4109    if (offset != 0) // TODO check if index != 0 as well
4110       index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset), index);
4111    Temp ptr = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->ac.push_constants));
4112    Temp vec = dst;
4113    bool trim = false;
4114    aco_opcode op;
4115
4116    switch (dst.size()) {
4117    case 1:
4118       op = aco_opcode::s_load_dword;
4119       break;
4120    case 2:
4121       op = aco_opcode::s_load_dwordx2;
4122       break;
4123    case 3:
4124       vec = bld.tmp(s4);
4125       trim = true;
4126    case 4:
4127       op = aco_opcode::s_load_dwordx4;
4128       break;
4129    case 6:
4130       vec = bld.tmp(s8);
4131       trim = true;
4132    case 8:
4133       op = aco_opcode::s_load_dwordx8;
4134       break;
4135    default:
4136       unreachable("unimplemented or forbidden load_push_constant.");
4137    }
4138
4139    bld.smem(op, Definition(vec), ptr, index);
4140
4141    if (trim) {
4142       emit_split_vector(ctx, vec, 4);
4143       RegClass rc = dst.size() == 3 ? s1 : s2;
4144       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4145                  emit_extract_vector(ctx, vec, 0, rc),
4146                  emit_extract_vector(ctx, vec, 1, rc),
4147                  emit_extract_vector(ctx, vec, 2, rc));
4148
4149    }
4150    emit_split_vector(ctx, dst, instr->dest.ssa.num_components);
4151 }
4152
4153 void visit_load_constant(isel_context *ctx, nir_intrinsic_instr *instr)
4154 {
4155    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4156
4157    Builder bld(ctx->program, ctx->block);
4158
4159    uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
4160                         S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
4161                         S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
4162                         S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
4163    if (ctx->options->chip_class >= GFX10) {
4164       desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
4165                    S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
4166                    S_008F0C_RESOURCE_LEVEL(1);
4167    } else {
4168       desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
4169                    S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
4170    }
4171
4172    unsigned base = nir_intrinsic_base(instr);
4173    unsigned range = nir_intrinsic_range(instr);
4174
4175    Temp offset = get_ssa_temp(ctx, instr->src[0].ssa);
4176    if (base && offset.type() == RegType::sgpr)
4177       offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), offset, Operand(base));
4178    else if (base && offset.type() == RegType::vgpr)
4179       offset = bld.vadd32(bld.def(v1), Operand(base), offset);
4180
4181    Temp rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
4182                           bld.sop1(aco_opcode::p_constaddr, bld.def(s2), bld.def(s1, scc), Operand(ctx->constant_data_offset)),
4183                           Operand(MIN2(base + range, ctx->shader->constant_data_size)),
4184                           Operand(desc_type));
4185
4186    load_buffer(ctx, instr->num_components, dst, rsrc, offset);
4187 }
4188
4189 void visit_discard_if(isel_context *ctx, nir_intrinsic_instr *instr)
4190 {
4191    if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
4192       ctx->cf_info.exec_potentially_empty_discard = true;
4193
4194    ctx->program->needs_exact = true;
4195
4196    // TODO: optimize uniform conditions
4197    Builder bld(ctx->program, ctx->block);
4198    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
4199    assert(src.regClass() == bld.lm);
4200    src = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
4201    bld.pseudo(aco_opcode::p_discard_if, src);
4202    ctx->block->kind |= block_kind_uses_discard_if;
4203    return;
4204 }
4205
4206 void visit_discard(isel_context* ctx, nir_intrinsic_instr *instr)
4207 {
4208    Builder bld(ctx->program, ctx->block);
4209
4210    if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
4211       ctx->cf_info.exec_potentially_empty_discard = true;
4212
4213    bool divergent = ctx->cf_info.parent_if.is_divergent ||
4214                     ctx->cf_info.parent_loop.has_divergent_continue;
4215
4216    if (ctx->block->loop_nest_depth &&
4217        ((nir_instr_is_last(&instr->instr) && !divergent) || divergent)) {
4218       /* we handle discards the same way as jump instructions */
4219       append_logical_end(ctx->block);
4220
4221       /* in loops, discard behaves like break */
4222       Block *linear_target = ctx->cf_info.parent_loop.exit;
4223       ctx->block->kind |= block_kind_discard;
4224
4225       if (!divergent) {
4226          /* uniform discard - loop ends here */
4227          assert(nir_instr_is_last(&instr->instr));
4228          ctx->block->kind |= block_kind_uniform;
4229          ctx->cf_info.has_branch = true;
4230          bld.branch(aco_opcode::p_branch);
4231          add_linear_edge(ctx->block->index, linear_target);
4232          return;
4233       }
4234
4235       /* we add a break right behind the discard() instructions */
4236       ctx->block->kind |= block_kind_break;
4237       unsigned idx = ctx->block->index;
4238
4239       /* remove critical edges from linear CFG */
4240       bld.branch(aco_opcode::p_branch);
4241       Block* break_block = ctx->program->create_and_insert_block();
4242       break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
4243       break_block->kind |= block_kind_uniform;
4244       add_linear_edge(idx, break_block);
4245       add_linear_edge(break_block->index, linear_target);
4246       bld.reset(break_block);
4247       bld.branch(aco_opcode::p_branch);
4248
4249       Block* continue_block = ctx->program->create_and_insert_block();
4250       continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
4251       add_linear_edge(idx, continue_block);
4252       append_logical_start(continue_block);
4253       ctx->block = continue_block;
4254
4255       return;
4256    }
4257
4258    /* it can currently happen that NIR doesn't remove the unreachable code */
4259    if (!nir_instr_is_last(&instr->instr)) {
4260       ctx->program->needs_exact = true;
4261       /* save exec somewhere temporarily so that it doesn't get
4262        * overwritten before the discard from outer exec masks */
4263       Temp cond = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), Operand(0xFFFFFFFF), Operand(exec, bld.lm));
4264       bld.pseudo(aco_opcode::p_discard_if, cond);
4265       ctx->block->kind |= block_kind_uses_discard_if;
4266       return;
4267    }
4268
4269    /* This condition is incorrect for uniformly branched discards in a loop
4270     * predicated by a divergent condition, but the above code catches that case
4271     * and the discard would end up turning into a discard_if.
4272     * For example:
4273     * if (divergent) {
4274     *    while (...) {
4275     *       if (uniform) {
4276     *          discard;
4277     *       }
4278     *    }
4279     * }
4280     */
4281    if (!ctx->cf_info.parent_if.is_divergent) {
4282       /* program just ends here */
4283       ctx->block->kind |= block_kind_uniform;
4284       bld.exp(aco_opcode::exp, Operand(v1), Operand(v1), Operand(v1), Operand(v1),
4285               0 /* enabled mask */, 9 /* dest */,
4286               false /* compressed */, true/* done */, true /* valid mask */);
4287       bld.sopp(aco_opcode::s_endpgm);
4288       // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
4289    } else {
4290       ctx->block->kind |= block_kind_discard;
4291       /* branch and linear edge is added by visit_if() */
4292    }
4293 }
4294
4295 enum aco_descriptor_type {
4296    ACO_DESC_IMAGE,
4297    ACO_DESC_FMASK,
4298    ACO_DESC_SAMPLER,
4299    ACO_DESC_BUFFER,
4300    ACO_DESC_PLANE_0,
4301    ACO_DESC_PLANE_1,
4302    ACO_DESC_PLANE_2,
4303 };
4304
4305 static bool
4306 should_declare_array(isel_context *ctx, enum glsl_sampler_dim sampler_dim, bool is_array) {
4307    if (sampler_dim == GLSL_SAMPLER_DIM_BUF)
4308       return false;
4309    ac_image_dim dim = ac_get_sampler_dim(ctx->options->chip_class, sampler_dim, is_array);
4310    return dim == ac_image_cube ||
4311           dim == ac_image_1darray ||
4312           dim == ac_image_2darray ||
4313           dim == ac_image_2darraymsaa;
4314 }
4315
4316 Temp get_sampler_desc(isel_context *ctx, nir_deref_instr *deref_instr,
4317                       enum aco_descriptor_type desc_type,
4318                       const nir_tex_instr *tex_instr, bool image, bool write)
4319 {
4320 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
4321    std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
4322    if (it != ctx->tex_desc.end())
4323       return it->second;
4324 */
4325    Temp index = Temp();
4326    bool index_set = false;
4327    unsigned constant_index = 0;
4328    unsigned descriptor_set;
4329    unsigned base_index;
4330    Builder bld(ctx->program, ctx->block);
4331
4332    if (!deref_instr) {
4333       assert(tex_instr && !image);
4334       descriptor_set = 0;
4335       base_index = tex_instr->sampler_index;
4336    } else {
4337       while(deref_instr->deref_type != nir_deref_type_var) {
4338          unsigned array_size = glsl_get_aoa_size(deref_instr->type);
4339          if (!array_size)
4340             array_size = 1;
4341
4342          assert(deref_instr->deref_type == nir_deref_type_array);
4343          nir_const_value *const_value = nir_src_as_const_value(deref_instr->arr.index);
4344          if (const_value) {
4345             constant_index += array_size * const_value->u32;
4346          } else {
4347             Temp indirect = get_ssa_temp(ctx, deref_instr->arr.index.ssa);
4348             if (indirect.type() == RegType::vgpr)
4349                indirect = bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), indirect);
4350
4351             if (array_size != 1)
4352                indirect = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(array_size), indirect);
4353
4354             if (!index_set) {
4355                index = indirect;
4356                index_set = true;
4357             } else {
4358                index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), index, indirect);
4359             }
4360          }
4361
4362          deref_instr = nir_src_as_deref(deref_instr->parent);
4363       }
4364       descriptor_set = deref_instr->var->data.descriptor_set;
4365       base_index = deref_instr->var->data.binding;
4366    }
4367
4368    Temp list = load_desc_ptr(ctx, descriptor_set);
4369    list = convert_pointer_to_64_bit(ctx, list);
4370
4371    struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4372    struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4373    unsigned offset = binding->offset;
4374    unsigned stride = binding->size;
4375    aco_opcode opcode;
4376    RegClass type;
4377
4378    assert(base_index < layout->binding_count);
4379
4380    switch (desc_type) {
4381    case ACO_DESC_IMAGE:
4382       type = s8;
4383       opcode = aco_opcode::s_load_dwordx8;
4384       break;
4385    case ACO_DESC_FMASK:
4386       type = s8;
4387       opcode = aco_opcode::s_load_dwordx8;
4388       offset += 32;
4389       break;
4390    case ACO_DESC_SAMPLER:
4391       type = s4;
4392       opcode = aco_opcode::s_load_dwordx4;
4393       if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4394          offset += radv_combined_image_descriptor_sampler_offset(binding);
4395       break;
4396    case ACO_DESC_BUFFER:
4397       type = s4;
4398       opcode = aco_opcode::s_load_dwordx4;
4399       break;
4400    case ACO_DESC_PLANE_0:
4401    case ACO_DESC_PLANE_1:
4402       type = s8;
4403       opcode = aco_opcode::s_load_dwordx8;
4404       offset += 32 * (desc_type - ACO_DESC_PLANE_0);
4405       break;
4406    case ACO_DESC_PLANE_2:
4407       type = s4;
4408       opcode = aco_opcode::s_load_dwordx4;
4409       offset += 64;
4410       break;
4411    default:
4412       unreachable("invalid desc_type\n");
4413    }
4414
4415    offset += constant_index * stride;
4416
4417    if (desc_type == ACO_DESC_SAMPLER && binding->immutable_samplers_offset &&
4418       (!index_set || binding->immutable_samplers_equal)) {
4419       if (binding->immutable_samplers_equal)
4420          constant_index = 0;
4421
4422       const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4423       return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
4424                         Operand(samplers[constant_index * 4 + 0]),
4425                         Operand(samplers[constant_index * 4 + 1]),
4426                         Operand(samplers[constant_index * 4 + 2]),
4427                         Operand(samplers[constant_index * 4 + 3]));
4428    }
4429
4430    Operand off;
4431    if (!index_set) {
4432       off = bld.copy(bld.def(s1), Operand(offset));
4433    } else {
4434       off = Operand((Temp)bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset),
4435                                    bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), index)));
4436    }
4437
4438    Temp res = bld.smem(opcode, bld.def(type), list, off);
4439
4440    if (desc_type == ACO_DESC_PLANE_2) {
4441       Temp components[8];
4442       for (unsigned i = 0; i < 8; i++)
4443          components[i] = bld.tmp(s1);
4444       bld.pseudo(aco_opcode::p_split_vector,
4445                  Definition(components[0]),
4446                  Definition(components[1]),
4447                  Definition(components[2]),
4448                  Definition(components[3]),
4449                  res);
4450
4451       Temp desc2 = get_sampler_desc(ctx, deref_instr, ACO_DESC_PLANE_1, tex_instr, image, write);
4452       bld.pseudo(aco_opcode::p_split_vector,
4453                  bld.def(s1), bld.def(s1), bld.def(s1), bld.def(s1),
4454                  Definition(components[4]),
4455                  Definition(components[5]),
4456                  Definition(components[6]),
4457                  Definition(components[7]),
4458                  desc2);
4459
4460       res = bld.pseudo(aco_opcode::p_create_vector, bld.def(s8),
4461                        components[0], components[1], components[2], components[3],
4462                        components[4], components[5], components[6], components[7]);
4463    }
4464
4465    return res;
4466 }
4467
4468 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
4469 {
4470    switch (dim) {
4471    case GLSL_SAMPLER_DIM_BUF:
4472       return 1;
4473    case GLSL_SAMPLER_DIM_1D:
4474       return array ? 2 : 1;
4475    case GLSL_SAMPLER_DIM_2D:
4476       return array ? 3 : 2;
4477    case GLSL_SAMPLER_DIM_MS:
4478       return array ? 4 : 3;
4479    case GLSL_SAMPLER_DIM_3D:
4480    case GLSL_SAMPLER_DIM_CUBE:
4481       return 3;
4482    case GLSL_SAMPLER_DIM_RECT:
4483    case GLSL_SAMPLER_DIM_SUBPASS:
4484       return 2;
4485    case GLSL_SAMPLER_DIM_SUBPASS_MS:
4486       return 3;
4487    default:
4488       break;
4489    }
4490    return 0;
4491 }
4492
4493
4494 /* Adjust the sample index according to FMASK.
4495  *
4496  * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4497  * which is the identity mapping. Each nibble says which physical sample
4498  * should be fetched to get that sample.
4499  *
4500  * For example, 0x11111100 means there are only 2 samples stored and
4501  * the second sample covers 3/4 of the pixel. When reading samples 0
4502  * and 1, return physical sample 0 (determined by the first two 0s
4503  * in FMASK), otherwise return physical sample 1.
4504  *
4505  * The sample index should be adjusted as follows:
4506  *   sample_index = (fmask >> (sample_index * 4)) & 0xF;
4507  */
4508 static Temp adjust_sample_index_using_fmask(isel_context *ctx, bool da, std::vector<Temp>& coords, Operand sample_index, Temp fmask_desc_ptr)
4509 {
4510    Builder bld(ctx->program, ctx->block);
4511    Temp fmask = bld.tmp(v1);
4512    unsigned dim = ctx->options->chip_class >= GFX10
4513                   ? ac_get_sampler_dim(ctx->options->chip_class, GLSL_SAMPLER_DIM_2D, da)
4514                   : 0;
4515
4516    Temp coord = da ? bld.pseudo(aco_opcode::p_create_vector, bld.def(v3), coords[0], coords[1], coords[2]) :
4517                      bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), coords[0], coords[1]);
4518    aco_ptr<MIMG_instruction> load{create_instruction<MIMG_instruction>(aco_opcode::image_load, Format::MIMG, 3, 1)};
4519    load->operands[0] = Operand(fmask_desc_ptr);
4520    load->operands[1] = Operand(s4); /* no sampler */
4521    load->operands[2] = Operand(coord);
4522    load->definitions[0] = Definition(fmask);
4523    load->glc = false;
4524    load->dlc = false;
4525    load->dmask = 0x1;
4526    load->unrm = true;
4527    load->da = da;
4528    load->dim = dim;
4529    load->can_reorder = true; /* fmask images shouldn't be modified */
4530    ctx->block->instructions.emplace_back(std::move(load));
4531
4532    Operand sample_index4;
4533    if (sample_index.isConstant() && sample_index.constantValue() < 16) {
4534       sample_index4 = Operand(sample_index.constantValue() << 2);
4535    } else if (sample_index.regClass() == s1) {
4536       sample_index4 = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), sample_index, Operand(2u));
4537    } else {
4538       assert(sample_index.regClass() == v1);
4539       sample_index4 = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), sample_index);
4540    }
4541
4542    Temp final_sample;
4543    if (sample_index4.isConstant() && sample_index4.constantValue() == 0)
4544       final_sample = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(15u), fmask);
4545    else if (sample_index4.isConstant() && sample_index4.constantValue() == 28)
4546       final_sample = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(28u), fmask);
4547    else
4548       final_sample = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1), fmask, sample_index4, Operand(4u));
4549
4550    /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4551     * resource descriptor is 0 (invalid),
4552     */
4553    Temp compare = bld.tmp(bld.lm);
4554    bld.vopc_e64(aco_opcode::v_cmp_lg_u32, Definition(compare),
4555                 Operand(0u), emit_extract_vector(ctx, fmask_desc_ptr, 1, s1)).def(0).setHint(vcc);
4556
4557    Temp sample_index_v = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), sample_index);
4558
4559    /* Replace the MSAA sample index. */
4560    return bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), sample_index_v, final_sample, compare);
4561 }
4562
4563 static Temp get_image_coords(isel_context *ctx, const nir_intrinsic_instr *instr, const struct glsl_type *type)
4564 {
4565
4566    Temp src0 = get_ssa_temp(ctx, instr->src[1].ssa);
4567    enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4568    bool is_array = glsl_sampler_type_is_array(type);
4569    ASSERTED bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS || dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
4570    assert(!add_frag_pos && "Input attachments should be lowered.");
4571    bool is_ms = (dim == GLSL_SAMPLER_DIM_MS || dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
4572    bool gfx9_1d = ctx->options->chip_class == GFX9 && dim == GLSL_SAMPLER_DIM_1D;
4573    int count = image_type_to_components_count(dim, is_array);
4574    std::vector<Temp> coords(count);
4575    Builder bld(ctx->program, ctx->block);
4576
4577    if (is_ms) {
4578       count--;
4579       Temp src2 = get_ssa_temp(ctx, instr->src[2].ssa);
4580       /* get sample index */
4581       if (instr->intrinsic == nir_intrinsic_image_deref_load) {
4582          nir_const_value *sample_cv = nir_src_as_const_value(instr->src[2]);
4583          Operand sample_index = sample_cv ? Operand(sample_cv->u32) : Operand(emit_extract_vector(ctx, src2, 0, v1));
4584          std::vector<Temp> fmask_load_address;
4585          for (unsigned i = 0; i < (is_array ? 3 : 2); i++)
4586             fmask_load_address.emplace_back(emit_extract_vector(ctx, src0, i, v1));
4587
4588          Temp fmask_desc_ptr = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_FMASK, nullptr, false, false);
4589          coords[count] = adjust_sample_index_using_fmask(ctx, is_array, fmask_load_address, sample_index, fmask_desc_ptr);
4590       } else {
4591          coords[count] = emit_extract_vector(ctx, src2, 0, v1);
4592       }
4593    }
4594
4595    if (gfx9_1d) {
4596       coords[0] = emit_extract_vector(ctx, src0, 0, v1);
4597       coords.resize(coords.size() + 1);
4598       coords[1] = bld.copy(bld.def(v1), Operand(0u));
4599       if (is_array)
4600          coords[2] = emit_extract_vector(ctx, src0, 1, v1);
4601    } else {
4602       for (int i = 0; i < count; i++)
4603          coords[i] = emit_extract_vector(ctx, src0, i, v1);
4604    }
4605
4606    if (instr->intrinsic == nir_intrinsic_image_deref_load ||
4607        instr->intrinsic == nir_intrinsic_image_deref_store) {
4608       int lod_index = instr->intrinsic == nir_intrinsic_image_deref_load ? 3 : 4;
4609       bool level_zero = nir_src_is_const(instr->src[lod_index]) && nir_src_as_uint(instr->src[lod_index]) == 0;
4610
4611       if (!level_zero)
4612          coords.emplace_back(get_ssa_temp(ctx, instr->src[lod_index].ssa));
4613    }
4614
4615    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, coords.size(), 1)};
4616    for (unsigned i = 0; i < coords.size(); i++)
4617       vec->operands[i] = Operand(coords[i]);
4618    Temp res = {ctx->program->allocateId(), RegClass(RegType::vgpr, coords.size())};
4619    vec->definitions[0] = Definition(res);
4620    ctx->block->instructions.emplace_back(std::move(vec));
4621    return res;
4622 }
4623
4624
4625 void visit_image_load(isel_context *ctx, nir_intrinsic_instr *instr)
4626 {
4627    Builder bld(ctx->program, ctx->block);
4628    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4629    const struct glsl_type *type = glsl_without_array(var->type);
4630    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4631    bool is_array = glsl_sampler_type_is_array(type);
4632    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4633
4634    if (dim == GLSL_SAMPLER_DIM_BUF) {
4635       unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
4636       unsigned num_channels = util_last_bit(mask);
4637       Temp rsrc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4638       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4639
4640       aco_opcode opcode;
4641       switch (num_channels) {
4642       case 1:
4643          opcode = aco_opcode::buffer_load_format_x;
4644          break;
4645       case 2:
4646          opcode = aco_opcode::buffer_load_format_xy;
4647          break;
4648       case 3:
4649          opcode = aco_opcode::buffer_load_format_xyz;
4650          break;
4651       case 4:
4652          opcode = aco_opcode::buffer_load_format_xyzw;
4653          break;
4654       default:
4655          unreachable(">4 channel buffer image load");
4656       }
4657       aco_ptr<MUBUF_instruction> load{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 3, 1)};
4658       load->operands[0] = Operand(rsrc);
4659       load->operands[1] = Operand(vindex);
4660       load->operands[2] = Operand((uint32_t) 0);
4661       Temp tmp;
4662       if (num_channels == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
4663          tmp = dst;
4664       else
4665          tmp = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_channels)};
4666       load->definitions[0] = Definition(tmp);
4667       load->idxen = true;
4668       load->glc = var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT);
4669       load->dlc = load->glc && ctx->options->chip_class >= GFX10;
4670       load->barrier = barrier_image;
4671       ctx->block->instructions.emplace_back(std::move(load));
4672
4673       expand_vector(ctx, tmp, dst, instr->dest.ssa.num_components, (1 << num_channels) - 1);
4674       return;
4675    }
4676
4677    Temp coords = get_image_coords(ctx, instr, type);
4678    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
4679
4680    unsigned dmask = nir_ssa_def_components_read(&instr->dest.ssa);
4681    unsigned num_components = util_bitcount(dmask);
4682    Temp tmp;
4683    if (num_components == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
4684       tmp = dst;
4685    else
4686       tmp = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_components)};
4687
4688    bool level_zero = nir_src_is_const(instr->src[3]) && nir_src_as_uint(instr->src[3]) == 0;
4689    aco_opcode opcode = level_zero ? aco_opcode::image_load : aco_opcode::image_load_mip;
4690
4691    aco_ptr<MIMG_instruction> load{create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 1)};
4692    load->operands[0] = Operand(resource);
4693    load->operands[1] = Operand(s4); /* no sampler */
4694    load->operands[2] = Operand(coords);
4695    load->definitions[0] = Definition(tmp);
4696    load->glc = var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT) ? 1 : 0;
4697    load->dlc = load->glc && ctx->options->chip_class >= GFX10;
4698    load->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4699    load->dmask = dmask;
4700    load->unrm = true;
4701    load->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
4702    load->barrier = barrier_image;
4703    ctx->block->instructions.emplace_back(std::move(load));
4704
4705    expand_vector(ctx, tmp, dst, instr->dest.ssa.num_components, dmask);
4706    return;
4707 }
4708
4709 void visit_image_store(isel_context *ctx, nir_intrinsic_instr *instr)
4710 {
4711    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4712    const struct glsl_type *type = glsl_without_array(var->type);
4713    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4714    bool is_array = glsl_sampler_type_is_array(type);
4715    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[3].ssa));
4716
4717    bool glc = ctx->options->chip_class == GFX6 || var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE) ? 1 : 0;
4718
4719    if (dim == GLSL_SAMPLER_DIM_BUF) {
4720       Temp rsrc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4721       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4722       aco_opcode opcode;
4723       switch (data.size()) {
4724       case 1:
4725          opcode = aco_opcode::buffer_store_format_x;
4726          break;
4727       case 2:
4728          opcode = aco_opcode::buffer_store_format_xy;
4729          break;
4730       case 3:
4731          opcode = aco_opcode::buffer_store_format_xyz;
4732          break;
4733       case 4:
4734          opcode = aco_opcode::buffer_store_format_xyzw;
4735          break;
4736       default:
4737          unreachable(">4 channel buffer image store");
4738       }
4739       aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 4, 0)};
4740       store->operands[0] = Operand(rsrc);
4741       store->operands[1] = Operand(vindex);
4742       store->operands[2] = Operand((uint32_t) 0);
4743       store->operands[3] = Operand(data);
4744       store->idxen = true;
4745       store->glc = glc;
4746       store->dlc = false;
4747       store->disable_wqm = true;
4748       store->barrier = barrier_image;
4749       ctx->program->needs_exact = true;
4750       ctx->block->instructions.emplace_back(std::move(store));
4751       return;
4752    }
4753
4754    assert(data.type() == RegType::vgpr);
4755    Temp coords = get_image_coords(ctx, instr, type);
4756    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
4757
4758    bool level_zero = nir_src_is_const(instr->src[4]) && nir_src_as_uint(instr->src[4]) == 0;
4759    aco_opcode opcode = level_zero ? aco_opcode::image_store : aco_opcode::image_store_mip;
4760
4761    aco_ptr<MIMG_instruction> store{create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 0)};
4762    store->operands[0] = Operand(resource);
4763    store->operands[1] = Operand(data);
4764    store->operands[2] = Operand(coords);
4765    store->glc = glc;
4766    store->dlc = false;
4767    store->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4768    store->dmask = (1 << data.size()) - 1;
4769    store->unrm = true;
4770    store->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
4771    store->disable_wqm = true;
4772    store->barrier = barrier_image;
4773    ctx->program->needs_exact = true;
4774    ctx->block->instructions.emplace_back(std::move(store));
4775    return;
4776 }
4777
4778 void visit_image_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
4779 {
4780    /* return the previous value if dest is ever used */
4781    bool return_previous = false;
4782    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
4783       return_previous = true;
4784       break;
4785    }
4786    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
4787       return_previous = true;
4788       break;
4789    }
4790
4791    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4792    const struct glsl_type *type = glsl_without_array(var->type);
4793    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4794    bool is_array = glsl_sampler_type_is_array(type);
4795    Builder bld(ctx->program, ctx->block);
4796
4797    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[3].ssa));
4798    assert(data.size() == 1 && "64bit ssbo atomics not yet implemented.");
4799
4800    if (instr->intrinsic == nir_intrinsic_image_deref_atomic_comp_swap)
4801       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), get_ssa_temp(ctx, instr->src[4].ssa), data);
4802
4803    aco_opcode buf_op, image_op;
4804    switch (instr->intrinsic) {
4805       case nir_intrinsic_image_deref_atomic_add:
4806          buf_op = aco_opcode::buffer_atomic_add;
4807          image_op = aco_opcode::image_atomic_add;
4808          break;
4809       case nir_intrinsic_image_deref_atomic_umin:
4810          buf_op = aco_opcode::buffer_atomic_umin;
4811          image_op = aco_opcode::image_atomic_umin;
4812          break;
4813       case nir_intrinsic_image_deref_atomic_imin:
4814          buf_op = aco_opcode::buffer_atomic_smin;
4815          image_op = aco_opcode::image_atomic_smin;
4816          break;
4817       case nir_intrinsic_image_deref_atomic_umax:
4818          buf_op = aco_opcode::buffer_atomic_umax;
4819          image_op = aco_opcode::image_atomic_umax;
4820          break;
4821       case nir_intrinsic_image_deref_atomic_imax:
4822          buf_op = aco_opcode::buffer_atomic_smax;
4823          image_op = aco_opcode::image_atomic_smax;
4824          break;
4825       case nir_intrinsic_image_deref_atomic_and:
4826          buf_op = aco_opcode::buffer_atomic_and;
4827          image_op = aco_opcode::image_atomic_and;
4828          break;
4829       case nir_intrinsic_image_deref_atomic_or:
4830          buf_op = aco_opcode::buffer_atomic_or;
4831          image_op = aco_opcode::image_atomic_or;
4832          break;
4833       case nir_intrinsic_image_deref_atomic_xor:
4834          buf_op = aco_opcode::buffer_atomic_xor;
4835          image_op = aco_opcode::image_atomic_xor;
4836          break;
4837       case nir_intrinsic_image_deref_atomic_exchange:
4838          buf_op = aco_opcode::buffer_atomic_swap;
4839          image_op = aco_opcode::image_atomic_swap;
4840          break;
4841       case nir_intrinsic_image_deref_atomic_comp_swap:
4842          buf_op = aco_opcode::buffer_atomic_cmpswap;
4843          image_op = aco_opcode::image_atomic_cmpswap;
4844          break;
4845       default:
4846          unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
4847    }
4848
4849    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4850
4851    if (dim == GLSL_SAMPLER_DIM_BUF) {
4852       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4853       Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4854       //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
4855       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(buf_op, Format::MUBUF, 4, return_previous ? 1 : 0)};
4856       mubuf->operands[0] = Operand(resource);
4857       mubuf->operands[1] = Operand(vindex);
4858       mubuf->operands[2] = Operand((uint32_t)0);
4859       mubuf->operands[3] = Operand(data);
4860       if (return_previous)
4861          mubuf->definitions[0] = Definition(dst);
4862       mubuf->offset = 0;
4863       mubuf->idxen = true;
4864       mubuf->glc = return_previous;
4865       mubuf->dlc = false; /* Not needed for atomics */
4866       mubuf->disable_wqm = true;
4867       mubuf->barrier = barrier_image;
4868       ctx->program->needs_exact = true;
4869       ctx->block->instructions.emplace_back(std::move(mubuf));
4870       return;
4871    }
4872
4873    Temp coords = get_image_coords(ctx, instr, type);
4874    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
4875    aco_ptr<MIMG_instruction> mimg{create_instruction<MIMG_instruction>(image_op, Format::MIMG, 3, return_previous ? 1 : 0)};
4876    mimg->operands[0] = Operand(resource);
4877    mimg->operands[1] = Operand(data);
4878    mimg->operands[2] = Operand(coords);
4879    if (return_previous)
4880       mimg->definitions[0] = Definition(dst);
4881    mimg->glc = return_previous;
4882    mimg->dlc = false; /* Not needed for atomics */
4883    mimg->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4884    mimg->dmask = (1 << data.size()) - 1;
4885    mimg->unrm = true;
4886    mimg->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
4887    mimg->disable_wqm = true;
4888    mimg->barrier = barrier_image;
4889    ctx->program->needs_exact = true;
4890    ctx->block->instructions.emplace_back(std::move(mimg));
4891    return;
4892 }
4893
4894 void get_buffer_size(isel_context *ctx, Temp desc, Temp dst, bool in_elements)
4895 {
4896    if (in_elements && ctx->options->chip_class == GFX8) {
4897       /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
4898       Builder bld(ctx->program, ctx->block);
4899
4900       Temp size = emit_extract_vector(ctx, desc, 2, s1);
4901
4902       Temp size_div3 = bld.vop3(aco_opcode::v_mul_hi_u32, bld.def(v1), bld.copy(bld.def(v1), Operand(0xaaaaaaabu)), size);
4903       size_div3 = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.as_uniform(size_div3), Operand(1u));
4904
4905       Temp stride = emit_extract_vector(ctx, desc, 1, s1);
4906       stride = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), stride, Operand((5u << 16) | 16u));
4907
4908       Temp is12 = bld.sopc(aco_opcode::s_cmp_eq_i32, bld.def(s1, scc), stride, Operand(12u));
4909       size = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), size_div3, size, bld.scc(is12));
4910
4911       Temp shr_dst = dst.type() == RegType::vgpr ? bld.tmp(s1) : dst;
4912       bld.sop2(aco_opcode::s_lshr_b32, Definition(shr_dst), bld.def(s1, scc),
4913                size, bld.sop1(aco_opcode::s_ff1_i32_b32, bld.def(s1), stride));
4914       if (dst.type() == RegType::vgpr)
4915          bld.copy(Definition(dst), shr_dst);
4916
4917       /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
4918    } else {
4919       emit_extract_vector(ctx, desc, 2, dst);
4920    }
4921 }
4922
4923 void visit_image_size(isel_context *ctx, nir_intrinsic_instr *instr)
4924 {
4925    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4926    const struct glsl_type *type = glsl_without_array(var->type);
4927    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4928    bool is_array = glsl_sampler_type_is_array(type);
4929    Builder bld(ctx->program, ctx->block);
4930
4931    if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
4932       Temp desc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, NULL, true, false);
4933       return get_buffer_size(ctx, desc, get_ssa_temp(ctx, &instr->dest.ssa), true);
4934    }
4935
4936    /* LOD */
4937    Temp lod = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
4938
4939    /* Resource */
4940    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, NULL, true, false);
4941
4942    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4943
4944    aco_ptr<MIMG_instruction> mimg{create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 3, 1)};
4945    mimg->operands[0] = Operand(resource);
4946    mimg->operands[1] = Operand(s4); /* no sampler */
4947    mimg->operands[2] = Operand(lod);
4948    uint8_t& dmask = mimg->dmask;
4949    mimg->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4950    mimg->dmask = (1 << instr->dest.ssa.num_components) - 1;
4951    mimg->da = glsl_sampler_type_is_array(type);
4952    mimg->can_reorder = true;
4953    Definition& def = mimg->definitions[0];
4954    ctx->block->instructions.emplace_back(std::move(mimg));
4955
4956    if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
4957        glsl_sampler_type_is_array(type)) {
4958
4959       assert(instr->dest.ssa.num_components == 3);
4960       Temp tmp = {ctx->program->allocateId(), v3};
4961       def = Definition(tmp);
4962       emit_split_vector(ctx, tmp, 3);
4963
4964       /* divide 3rd value by 6 by multiplying with magic number */
4965       Temp c = bld.copy(bld.def(s1), Operand((uint32_t) 0x2AAAAAAB));
4966       Temp by_6 = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), emit_extract_vector(ctx, tmp, 2, v1), c);
4967
4968       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4969                  emit_extract_vector(ctx, tmp, 0, v1),
4970                  emit_extract_vector(ctx, tmp, 1, v1),
4971                  by_6);
4972
4973    } else if (ctx->options->chip_class == GFX9 &&
4974               glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
4975               glsl_sampler_type_is_array(type)) {
4976       assert(instr->dest.ssa.num_components == 2);
4977       def = Definition(dst);
4978       dmask = 0x5;
4979    } else {
4980       def = Definition(dst);
4981    }
4982
4983    emit_split_vector(ctx, dst, instr->dest.ssa.num_components);
4984 }
4985
4986 void visit_load_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
4987 {
4988    Builder bld(ctx->program, ctx->block);
4989    unsigned num_components = instr->num_components;
4990
4991    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4992    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4993    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
4994
4995    bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT);
4996    load_buffer(ctx, num_components, dst, rsrc, get_ssa_temp(ctx, instr->src[1].ssa), glc, false);
4997 }
4998
4999 void visit_store_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
5000 {
5001    Builder bld(ctx->program, ctx->block);
5002    Temp data = get_ssa_temp(ctx, instr->src[0].ssa);
5003    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
5004    unsigned writemask = nir_intrinsic_write_mask(instr);
5005    Temp offset = get_ssa_temp(ctx, instr->src[2].ssa);
5006
5007    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5008    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
5009
5010    bool smem = !ctx->divergent_vals[instr->src[2].ssa->index] &&
5011                ctx->options->chip_class >= GFX8;
5012    if (smem)
5013       offset = bld.as_uniform(offset);
5014    bool smem_nonfs = smem && ctx->stage != fragment_fs;
5015
5016    while (writemask) {
5017       int start, count;
5018       u_bit_scan_consecutive_range(&writemask, &start, &count);
5019       if (count == 3 && (smem || ctx->options->chip_class == GFX6)) {
5020          /* GFX6 doesn't support storing vec3, split it. */
5021          writemask |= 1u << (start + 2);
5022          count = 2;
5023       }
5024       int num_bytes = count * elem_size_bytes;
5025
5026       if (num_bytes > 16) {
5027          assert(elem_size_bytes == 8);
5028          writemask |= (((count - 2) << 1) - 1) << (start + 2);
5029          count = 2;
5030          num_bytes = 16;
5031       }
5032
5033       // TODO: check alignment of sub-dword stores
5034       // TODO: split 3 bytes. there is no store instruction for that
5035
5036       Temp write_data;
5037       if (count != instr->num_components) {
5038          emit_split_vector(ctx, data, instr->num_components);
5039          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
5040          for (int i = 0; i < count; i++) {
5041             Temp elem = emit_extract_vector(ctx, data, start + i, RegClass(data.type(), elem_size_bytes / 4));
5042             vec->operands[i] = Operand(smem_nonfs ? bld.as_uniform(elem) : elem);
5043          }
5044          write_data = bld.tmp(!smem ? RegType::vgpr : smem_nonfs ? RegType::sgpr : data.type(), count * elem_size_bytes / 4);
5045          vec->definitions[0] = Definition(write_data);
5046          ctx->block->instructions.emplace_back(std::move(vec));
5047       } else if (!smem && data.type() != RegType::vgpr) {
5048          assert(num_bytes % 4 == 0);
5049          write_data = bld.copy(bld.def(RegType::vgpr, num_bytes / 4), data);
5050       } else if (smem_nonfs && data.type() == RegType::vgpr) {
5051          assert(num_bytes % 4 == 0);
5052          write_data = bld.as_uniform(data);
5053       } else {
5054          write_data = data;
5055       }
5056
5057       aco_opcode vmem_op, smem_op;
5058       switch (num_bytes) {
5059          case 4:
5060             vmem_op = aco_opcode::buffer_store_dword;
5061             smem_op = aco_opcode::s_buffer_store_dword;
5062             break;
5063          case 8:
5064             vmem_op = aco_opcode::buffer_store_dwordx2;
5065             smem_op = aco_opcode::s_buffer_store_dwordx2;
5066             break;
5067          case 12:
5068             vmem_op = aco_opcode::buffer_store_dwordx3;
5069             smem_op = aco_opcode::last_opcode;
5070             assert(!smem && ctx->options->chip_class > GFX6);
5071             break;
5072          case 16:
5073             vmem_op = aco_opcode::buffer_store_dwordx4;
5074             smem_op = aco_opcode::s_buffer_store_dwordx4;
5075             break;
5076          default:
5077             unreachable("Store SSBO not implemented for this size.");
5078       }
5079       if (ctx->stage == fragment_fs)
5080          smem_op = aco_opcode::p_fs_buffer_store_smem;
5081
5082       if (smem) {
5083          aco_ptr<SMEM_instruction> store{create_instruction<SMEM_instruction>(smem_op, Format::SMEM, 3, 0)};
5084          store->operands[0] = Operand(rsrc);
5085          if (start) {
5086             Temp off = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
5087                                 offset, Operand(start * elem_size_bytes));
5088             store->operands[1] = Operand(off);
5089          } else {
5090             store->operands[1] = Operand(offset);
5091          }
5092          if (smem_op != aco_opcode::p_fs_buffer_store_smem)
5093             store->operands[1].setFixed(m0);
5094          store->operands[2] = Operand(write_data);
5095          store->glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
5096          store->dlc = false;
5097          store->disable_wqm = true;
5098          store->barrier = barrier_buffer;
5099          ctx->block->instructions.emplace_back(std::move(store));
5100          ctx->program->wb_smem_l1_on_end = true;
5101          if (smem_op == aco_opcode::p_fs_buffer_store_smem) {
5102             ctx->block->kind |= block_kind_needs_lowering;
5103             ctx->program->needs_exact = true;
5104          }
5105       } else {
5106          aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(vmem_op, Format::MUBUF, 4, 0)};
5107          store->operands[0] = Operand(rsrc);
5108          store->operands[1] = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
5109          store->operands[2] = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
5110          store->operands[3] = Operand(write_data);
5111          store->offset = start * elem_size_bytes;
5112          store->offen = (offset.type() == RegType::vgpr);
5113          store->glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
5114          store->dlc = false;
5115          store->disable_wqm = true;
5116          store->barrier = barrier_buffer;
5117          ctx->program->needs_exact = true;
5118          ctx->block->instructions.emplace_back(std::move(store));
5119       }
5120    }
5121 }
5122
5123 void visit_atomic_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
5124 {
5125    /* return the previous value if dest is ever used */
5126    bool return_previous = false;
5127    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
5128       return_previous = true;
5129       break;
5130    }
5131    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
5132       return_previous = true;
5133       break;
5134    }
5135
5136    Builder bld(ctx->program, ctx->block);
5137    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[2].ssa));
5138
5139    if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap)
5140       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(RegType::vgpr, data.size() * 2),
5141                         get_ssa_temp(ctx, instr->src[3].ssa), data);
5142
5143    Temp offset = get_ssa_temp(ctx, instr->src[1].ssa);
5144    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5145    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
5146
5147    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5148
5149    aco_opcode op32, op64;
5150    switch (instr->intrinsic) {
5151       case nir_intrinsic_ssbo_atomic_add:
5152          op32 = aco_opcode::buffer_atomic_add;
5153          op64 = aco_opcode::buffer_atomic_add_x2;
5154          break;
5155       case nir_intrinsic_ssbo_atomic_imin:
5156          op32 = aco_opcode::buffer_atomic_smin;
5157          op64 = aco_opcode::buffer_atomic_smin_x2;
5158          break;
5159       case nir_intrinsic_ssbo_atomic_umin:
5160          op32 = aco_opcode::buffer_atomic_umin;
5161          op64 = aco_opcode::buffer_atomic_umin_x2;
5162          break;
5163       case nir_intrinsic_ssbo_atomic_imax:
5164          op32 = aco_opcode::buffer_atomic_smax;
5165          op64 = aco_opcode::buffer_atomic_smax_x2;
5166          break;
5167       case nir_intrinsic_ssbo_atomic_umax:
5168          op32 = aco_opcode::buffer_atomic_umax;
5169          op64 = aco_opcode::buffer_atomic_umax_x2;
5170          break;
5171       case nir_intrinsic_ssbo_atomic_and:
5172          op32 = aco_opcode::buffer_atomic_and;
5173          op64 = aco_opcode::buffer_atomic_and_x2;
5174          break;
5175       case nir_intrinsic_ssbo_atomic_or:
5176          op32 = aco_opcode::buffer_atomic_or;
5177          op64 = aco_opcode::buffer_atomic_or_x2;
5178          break;
5179       case nir_intrinsic_ssbo_atomic_xor:
5180          op32 = aco_opcode::buffer_atomic_xor;
5181          op64 = aco_opcode::buffer_atomic_xor_x2;
5182          break;
5183       case nir_intrinsic_ssbo_atomic_exchange:
5184          op32 = aco_opcode::buffer_atomic_swap;
5185          op64 = aco_opcode::buffer_atomic_swap_x2;
5186          break;
5187       case nir_intrinsic_ssbo_atomic_comp_swap:
5188          op32 = aco_opcode::buffer_atomic_cmpswap;
5189          op64 = aco_opcode::buffer_atomic_cmpswap_x2;
5190          break;
5191       default:
5192          unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
5193    }
5194    aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
5195    aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, return_previous ? 1 : 0)};
5196    mubuf->operands[0] = Operand(rsrc);
5197    mubuf->operands[1] = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
5198    mubuf->operands[2] = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
5199    mubuf->operands[3] = Operand(data);
5200    if (return_previous)
5201       mubuf->definitions[0] = Definition(dst);
5202    mubuf->offset = 0;
5203    mubuf->offen = (offset.type() == RegType::vgpr);
5204    mubuf->glc = return_previous;
5205    mubuf->dlc = false; /* Not needed for atomics */
5206    mubuf->disable_wqm = true;
5207    mubuf->barrier = barrier_buffer;
5208    ctx->program->needs_exact = true;
5209    ctx->block->instructions.emplace_back(std::move(mubuf));
5210 }
5211
5212 void visit_get_buffer_size(isel_context *ctx, nir_intrinsic_instr *instr) {
5213
5214    Temp index = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5215    Builder bld(ctx->program, ctx->block);
5216    Temp desc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), index, Operand(0u));
5217    get_buffer_size(ctx, desc, get_ssa_temp(ctx, &instr->dest.ssa), false);
5218 }
5219
5220 Temp get_gfx6_global_rsrc(Builder& bld, Temp addr)
5221 {
5222    uint32_t rsrc_conf = S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5223                         S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
5224
5225    if (addr.type() == RegType::vgpr)
5226       return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf));
5227    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), addr, Operand(-1u), Operand(rsrc_conf));
5228 }
5229
5230 void visit_load_global(isel_context *ctx, nir_intrinsic_instr *instr)
5231 {
5232    Builder bld(ctx->program, ctx->block);
5233    unsigned num_components = instr->num_components;
5234    unsigned num_bytes = num_components * instr->dest.ssa.bit_size / 8;
5235
5236    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5237    Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
5238
5239    bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT);
5240    bool dlc = glc && ctx->options->chip_class >= GFX10;
5241    aco_opcode op;
5242    if (dst.type() == RegType::vgpr || (glc && ctx->options->chip_class < GFX8)) {
5243       bool global = ctx->options->chip_class >= GFX9;
5244
5245       if (ctx->options->chip_class >= GFX7) {
5246          aco_opcode op;
5247          switch (num_bytes) {
5248          case 4:
5249             op = global ? aco_opcode::global_load_dword : aco_opcode::flat_load_dword;
5250             break;
5251          case 8:
5252             op = global ? aco_opcode::global_load_dwordx2 : aco_opcode::flat_load_dwordx2;
5253             break;
5254          case 12:
5255             op = global ? aco_opcode::global_load_dwordx3 : aco_opcode::flat_load_dwordx3;
5256             break;
5257          case 16:
5258             op = global ? aco_opcode::global_load_dwordx4 : aco_opcode::flat_load_dwordx4;
5259             break;
5260          default:
5261             unreachable("load_global not implemented for this size.");
5262          }
5263
5264          aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 2, 1)};
5265          flat->operands[0] = Operand(addr);
5266          flat->operands[1] = Operand(s1);
5267          flat->glc = glc;
5268          flat->dlc = dlc;
5269          flat->barrier = barrier_buffer;
5270
5271          if (dst.type() == RegType::sgpr) {
5272             Temp vec = bld.tmp(RegType::vgpr, dst.size());
5273             flat->definitions[0] = Definition(vec);
5274             ctx->block->instructions.emplace_back(std::move(flat));
5275             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec);
5276          } else {
5277             flat->definitions[0] = Definition(dst);
5278             ctx->block->instructions.emplace_back(std::move(flat));
5279          }
5280          emit_split_vector(ctx, dst, num_components);
5281       } else {
5282          assert(ctx->options->chip_class == GFX6);
5283
5284          /* GFX6 doesn't support loading vec3, expand to vec4. */
5285          num_bytes = num_bytes == 12 ? 16 : num_bytes;
5286
5287          aco_opcode op;
5288          switch (num_bytes) {
5289          case 4:
5290             op = aco_opcode::buffer_load_dword;
5291             break;
5292          case 8:
5293             op = aco_opcode::buffer_load_dwordx2;
5294             break;
5295          case 16:
5296             op = aco_opcode::buffer_load_dwordx4;
5297             break;
5298          default:
5299             unreachable("load_global not implemented for this size.");
5300          }
5301
5302          Temp rsrc = get_gfx6_global_rsrc(bld, addr);
5303
5304          aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
5305          mubuf->operands[0] = Operand(rsrc);
5306          mubuf->operands[1] = addr.type() == RegType::vgpr ? Operand(addr) : Operand(v1);
5307          mubuf->operands[2] = Operand(0u);
5308          mubuf->glc = glc;
5309          mubuf->dlc = false;
5310          mubuf->offset = 0;
5311          mubuf->addr64 = addr.type() == RegType::vgpr;
5312          mubuf->disable_wqm = false;
5313          mubuf->barrier = barrier_buffer;
5314          aco_ptr<Instruction> instr = std::move(mubuf);
5315
5316          /* expand vector */
5317          if (dst.size() == 3) {
5318             Temp vec = bld.tmp(v4);
5319             instr->definitions[0] = Definition(vec);
5320             bld.insert(std::move(instr));
5321             emit_split_vector(ctx, vec, 4);
5322
5323             instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, 3, 1));
5324             instr->operands[0] = Operand(emit_extract_vector(ctx, vec, 0, v1));
5325             instr->operands[1] = Operand(emit_extract_vector(ctx, vec, 1, v1));
5326             instr->operands[2] = Operand(emit_extract_vector(ctx, vec, 2, v1));
5327          }
5328
5329          if (dst.type() == RegType::sgpr) {
5330             Temp vec = bld.tmp(RegType::vgpr, dst.size());
5331             instr->definitions[0] = Definition(vec);
5332             bld.insert(std::move(instr));
5333             expand_vector(ctx, vec, dst, num_components, (1 << num_components) - 1);
5334             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec);
5335          } else {
5336             instr->definitions[0] = Definition(dst);
5337             bld.insert(std::move(instr));
5338             emit_split_vector(ctx, dst, num_components);
5339          }
5340       }
5341    } else {
5342       switch (num_bytes) {
5343          case 4:
5344             op = aco_opcode::s_load_dword;
5345             break;
5346          case 8:
5347             op = aco_opcode::s_load_dwordx2;
5348             break;
5349          case 12:
5350          case 16:
5351             op = aco_opcode::s_load_dwordx4;
5352             break;
5353          default:
5354             unreachable("load_global not implemented for this size.");
5355       }
5356       aco_ptr<SMEM_instruction> load{create_instruction<SMEM_instruction>(op, Format::SMEM, 2, 1)};
5357       load->operands[0] = Operand(addr);
5358       load->operands[1] = Operand(0u);
5359       load->definitions[0] = Definition(dst);
5360       load->glc = glc;
5361       load->dlc = dlc;
5362       load->barrier = barrier_buffer;
5363       assert(ctx->options->chip_class >= GFX8 || !glc);
5364
5365       if (dst.size() == 3) {
5366          /* trim vector */
5367          Temp vec = bld.tmp(s4);
5368          load->definitions[0] = Definition(vec);
5369          ctx->block->instructions.emplace_back(std::move(load));
5370          emit_split_vector(ctx, vec, 4);
5371
5372          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
5373                     emit_extract_vector(ctx, vec, 0, s1),
5374                     emit_extract_vector(ctx, vec, 1, s1),
5375                     emit_extract_vector(ctx, vec, 2, s1));
5376       } else {
5377          ctx->block->instructions.emplace_back(std::move(load));
5378       }
5379    }
5380 }
5381
5382 void visit_store_global(isel_context *ctx, nir_intrinsic_instr *instr)
5383 {
5384    Builder bld(ctx->program, ctx->block);
5385    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
5386
5387    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5388    Temp addr = get_ssa_temp(ctx, instr->src[1].ssa);
5389
5390    if (ctx->options->chip_class >= GFX7)
5391       addr = as_vgpr(ctx, addr);
5392
5393    unsigned writemask = nir_intrinsic_write_mask(instr);
5394    while (writemask) {
5395       int start, count;
5396       u_bit_scan_consecutive_range(&writemask, &start, &count);
5397       if (count == 3 && ctx->options->chip_class == GFX6) {
5398          /* GFX6 doesn't support storing vec3, split it. */
5399          writemask |= 1u << (start + 2);
5400          count = 2;
5401       }
5402       unsigned num_bytes = count * elem_size_bytes;
5403
5404       Temp write_data = data;
5405       if (count != instr->num_components) {
5406          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
5407          for (int i = 0; i < count; i++)
5408             vec->operands[i] = Operand(emit_extract_vector(ctx, data, start + i, v1));
5409          write_data = bld.tmp(RegType::vgpr, count);
5410          vec->definitions[0] = Definition(write_data);
5411          ctx->block->instructions.emplace_back(std::move(vec));
5412       }
5413
5414       bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
5415       unsigned offset = start * elem_size_bytes;
5416
5417       if (ctx->options->chip_class >= GFX7) {
5418          if (offset > 0 && ctx->options->chip_class < GFX9) {
5419             Temp addr0 = bld.tmp(v1), addr1 = bld.tmp(v1);
5420             Temp new_addr0 = bld.tmp(v1), new_addr1 = bld.tmp(v1);
5421             Temp carry = bld.tmp(bld.lm);
5422             bld.pseudo(aco_opcode::p_split_vector, Definition(addr0), Definition(addr1), addr);
5423
5424             bld.vop2(aco_opcode::v_add_co_u32, Definition(new_addr0), bld.hint_vcc(Definition(carry)),
5425                      Operand(offset), addr0);
5426             bld.vop2(aco_opcode::v_addc_co_u32, Definition(new_addr1), bld.def(bld.lm),
5427                      Operand(0u), addr1,
5428                      carry).def(1).setHint(vcc);
5429
5430             addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), new_addr0, new_addr1);
5431
5432             offset = 0;
5433          }
5434
5435          bool global = ctx->options->chip_class >= GFX9;
5436          aco_opcode op;
5437          switch (num_bytes) {
5438          case 4:
5439             op = global ? aco_opcode::global_store_dword : aco_opcode::flat_store_dword;
5440             break;
5441          case 8:
5442             op = global ? aco_opcode::global_store_dwordx2 : aco_opcode::flat_store_dwordx2;
5443             break;
5444          case 12:
5445             op = global ? aco_opcode::global_store_dwordx3 : aco_opcode::flat_store_dwordx3;
5446             break;
5447          case 16:
5448             op = global ? aco_opcode::global_store_dwordx4 : aco_opcode::flat_store_dwordx4;
5449             break;
5450          default:
5451             unreachable("store_global not implemented for this size.");
5452          }
5453
5454          aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 3, 0)};
5455          flat->operands[0] = Operand(addr);
5456          flat->operands[1] = Operand(s1);
5457          flat->operands[2] = Operand(data);
5458          flat->glc = glc;
5459          flat->dlc = false;
5460          flat->offset = offset;
5461          flat->disable_wqm = true;
5462          flat->barrier = barrier_buffer;
5463          ctx->program->needs_exact = true;
5464          ctx->block->instructions.emplace_back(std::move(flat));
5465       } else {
5466          assert(ctx->options->chip_class == GFX6);
5467
5468          aco_opcode op;
5469          switch (num_bytes) {
5470          case 4:
5471             op = aco_opcode::buffer_store_dword;
5472             break;
5473          case 8:
5474             op = aco_opcode::buffer_store_dwordx2;
5475             break;
5476          case 16:
5477             op = aco_opcode::buffer_store_dwordx4;
5478             break;
5479          default:
5480             unreachable("store_global not implemented for this size.");
5481          }
5482
5483          Temp rsrc = get_gfx6_global_rsrc(bld, addr);
5484
5485          aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, 0)};
5486          mubuf->operands[0] = Operand(rsrc);
5487          mubuf->operands[1] = addr.type() == RegType::vgpr ? Operand(addr) : Operand(v1);
5488          mubuf->operands[2] = Operand(0u);
5489          mubuf->operands[3] = Operand(write_data);
5490          mubuf->glc = glc;
5491          mubuf->dlc = false;
5492          mubuf->offset = offset;
5493          mubuf->addr64 = addr.type() == RegType::vgpr;
5494          mubuf->disable_wqm = true;
5495          mubuf->barrier = barrier_buffer;
5496          ctx->program->needs_exact = true;
5497          ctx->block->instructions.emplace_back(std::move(mubuf));
5498       }
5499    }
5500 }
5501
5502 void visit_global_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
5503 {
5504    /* return the previous value if dest is ever used */
5505    bool return_previous = false;
5506    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
5507       return_previous = true;
5508       break;
5509    }
5510    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
5511       return_previous = true;
5512       break;
5513    }
5514
5515    Builder bld(ctx->program, ctx->block);
5516    Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
5517    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5518
5519    if (ctx->options->chip_class >= GFX7)
5520       addr = as_vgpr(ctx, addr);
5521
5522    if (instr->intrinsic == nir_intrinsic_global_atomic_comp_swap)
5523       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(RegType::vgpr, data.size() * 2),
5524                         get_ssa_temp(ctx, instr->src[2].ssa), data);
5525
5526    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5527
5528    aco_opcode op32, op64;
5529
5530    if (ctx->options->chip_class >= GFX7) {
5531       bool global = ctx->options->chip_class >= GFX9;
5532       switch (instr->intrinsic) {
5533          case nir_intrinsic_global_atomic_add:
5534             op32 = global ? aco_opcode::global_atomic_add : aco_opcode::flat_atomic_add;
5535             op64 = global ? aco_opcode::global_atomic_add_x2 : aco_opcode::flat_atomic_add_x2;
5536             break;
5537          case nir_intrinsic_global_atomic_imin:
5538             op32 = global ? aco_opcode::global_atomic_smin : aco_opcode::flat_atomic_smin;
5539             op64 = global ? aco_opcode::global_atomic_smin_x2 : aco_opcode::flat_atomic_smin_x2;
5540             break;
5541          case nir_intrinsic_global_atomic_umin:
5542             op32 = global ? aco_opcode::global_atomic_umin : aco_opcode::flat_atomic_umin;
5543             op64 = global ? aco_opcode::global_atomic_umin_x2 : aco_opcode::flat_atomic_umin_x2;
5544             break;
5545          case nir_intrinsic_global_atomic_imax:
5546             op32 = global ? aco_opcode::global_atomic_smax : aco_opcode::flat_atomic_smax;
5547             op64 = global ? aco_opcode::global_atomic_smax_x2 : aco_opcode::flat_atomic_smax_x2;
5548             break;
5549          case nir_intrinsic_global_atomic_umax:
5550             op32 = global ? aco_opcode::global_atomic_umax : aco_opcode::flat_atomic_umax;
5551             op64 = global ? aco_opcode::global_atomic_umax_x2 : aco_opcode::flat_atomic_umax_x2;
5552             break;
5553          case nir_intrinsic_global_atomic_and:
5554             op32 = global ? aco_opcode::global_atomic_and : aco_opcode::flat_atomic_and;
5555             op64 = global ? aco_opcode::global_atomic_and_x2 : aco_opcode::flat_atomic_and_x2;
5556             break;
5557          case nir_intrinsic_global_atomic_or:
5558             op32 = global ? aco_opcode::global_atomic_or : aco_opcode::flat_atomic_or;
5559             op64 = global ? aco_opcode::global_atomic_or_x2 : aco_opcode::flat_atomic_or_x2;
5560             break;
5561          case nir_intrinsic_global_atomic_xor:
5562             op32 = global ? aco_opcode::global_atomic_xor : aco_opcode::flat_atomic_xor;
5563             op64 = global ? aco_opcode::global_atomic_xor_x2 : aco_opcode::flat_atomic_xor_x2;
5564             break;
5565          case nir_intrinsic_global_atomic_exchange:
5566             op32 = global ? aco_opcode::global_atomic_swap : aco_opcode::flat_atomic_swap;
5567             op64 = global ? aco_opcode::global_atomic_swap_x2 : aco_opcode::flat_atomic_swap_x2;
5568             break;
5569          case nir_intrinsic_global_atomic_comp_swap:
5570             op32 = global ? aco_opcode::global_atomic_cmpswap : aco_opcode::flat_atomic_cmpswap;
5571             op64 = global ? aco_opcode::global_atomic_cmpswap_x2 : aco_opcode::flat_atomic_cmpswap_x2;
5572             break;
5573          default:
5574             unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
5575       }
5576
5577       aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
5578       aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 3, return_previous ? 1 : 0)};
5579       flat->operands[0] = Operand(addr);
5580       flat->operands[1] = Operand(s1);
5581       flat->operands[2] = Operand(data);
5582       if (return_previous)
5583          flat->definitions[0] = Definition(dst);
5584       flat->glc = return_previous;
5585       flat->dlc = false; /* Not needed for atomics */
5586       flat->offset = 0;
5587       flat->disable_wqm = true;
5588       flat->barrier = barrier_buffer;
5589       ctx->program->needs_exact = true;
5590       ctx->block->instructions.emplace_back(std::move(flat));
5591    } else {
5592       assert(ctx->options->chip_class == GFX6);
5593
5594       switch (instr->intrinsic) {
5595          case nir_intrinsic_global_atomic_add:
5596             op32 = aco_opcode::buffer_atomic_add;
5597             op64 = aco_opcode::buffer_atomic_add_x2;
5598             break;
5599          case nir_intrinsic_global_atomic_imin:
5600             op32 = aco_opcode::buffer_atomic_smin;
5601             op64 = aco_opcode::buffer_atomic_smin_x2;
5602             break;
5603          case nir_intrinsic_global_atomic_umin:
5604             op32 = aco_opcode::buffer_atomic_umin;
5605             op64 = aco_opcode::buffer_atomic_umin_x2;
5606             break;
5607          case nir_intrinsic_global_atomic_imax:
5608             op32 = aco_opcode::buffer_atomic_smax;
5609             op64 = aco_opcode::buffer_atomic_smax_x2;
5610             break;
5611          case nir_intrinsic_global_atomic_umax:
5612             op32 = aco_opcode::buffer_atomic_umax;
5613             op64 = aco_opcode::buffer_atomic_umax_x2;
5614             break;
5615          case nir_intrinsic_global_atomic_and:
5616             op32 = aco_opcode::buffer_atomic_and;
5617             op64 = aco_opcode::buffer_atomic_and_x2;
5618             break;
5619          case nir_intrinsic_global_atomic_or:
5620             op32 = aco_opcode::buffer_atomic_or;
5621             op64 = aco_opcode::buffer_atomic_or_x2;
5622             break;
5623          case nir_intrinsic_global_atomic_xor:
5624             op32 = aco_opcode::buffer_atomic_xor;
5625             op64 = aco_opcode::buffer_atomic_xor_x2;
5626             break;
5627          case nir_intrinsic_global_atomic_exchange:
5628             op32 = aco_opcode::buffer_atomic_swap;
5629             op64 = aco_opcode::buffer_atomic_swap_x2;
5630             break;
5631          case nir_intrinsic_global_atomic_comp_swap:
5632             op32 = aco_opcode::buffer_atomic_cmpswap;
5633             op64 = aco_opcode::buffer_atomic_cmpswap_x2;
5634             break;
5635          default:
5636             unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
5637       }
5638
5639       Temp rsrc = get_gfx6_global_rsrc(bld, addr);
5640
5641       aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
5642
5643       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, return_previous ? 1 : 0)};
5644       mubuf->operands[0] = Operand(rsrc);
5645       mubuf->operands[1] = addr.type() == RegType::vgpr ? Operand(addr) : Operand(v1);
5646       mubuf->operands[2] = Operand(0u);
5647       mubuf->operands[3] = Operand(data);
5648       if (return_previous)
5649          mubuf->definitions[0] = Definition(dst);
5650       mubuf->glc = return_previous;
5651       mubuf->dlc = false;
5652       mubuf->offset = 0;
5653       mubuf->addr64 = addr.type() == RegType::vgpr;
5654       mubuf->disable_wqm = true;
5655       mubuf->barrier = barrier_buffer;
5656       ctx->program->needs_exact = true;
5657       ctx->block->instructions.emplace_back(std::move(mubuf));
5658    }
5659 }
5660
5661 void emit_memory_barrier(isel_context *ctx, nir_intrinsic_instr *instr) {
5662    Builder bld(ctx->program, ctx->block);
5663    switch(instr->intrinsic) {
5664       case nir_intrinsic_group_memory_barrier:
5665       case nir_intrinsic_memory_barrier:
5666          bld.barrier(aco_opcode::p_memory_barrier_common);
5667          break;
5668       case nir_intrinsic_memory_barrier_buffer:
5669          bld.barrier(aco_opcode::p_memory_barrier_buffer);
5670          break;
5671       case nir_intrinsic_memory_barrier_image:
5672          bld.barrier(aco_opcode::p_memory_barrier_image);
5673          break;
5674       case nir_intrinsic_memory_barrier_tcs_patch:
5675       case nir_intrinsic_memory_barrier_shared:
5676          bld.barrier(aco_opcode::p_memory_barrier_shared);
5677          break;
5678       default:
5679          unreachable("Unimplemented memory barrier intrinsic");
5680          break;
5681    }
5682 }
5683
5684 void visit_load_shared(isel_context *ctx, nir_intrinsic_instr *instr)
5685 {
5686    // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
5687    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5688    assert(instr->dest.ssa.bit_size >= 32 && "Bitsize not supported in load_shared.");
5689    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5690    Builder bld(ctx->program, ctx->block);
5691
5692    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
5693    unsigned align = nir_intrinsic_align_mul(instr) ? nir_intrinsic_align(instr) : elem_size_bytes;
5694    load_lds(ctx, elem_size_bytes, dst, address, nir_intrinsic_base(instr), align);
5695 }
5696
5697 void visit_store_shared(isel_context *ctx, nir_intrinsic_instr *instr)
5698 {
5699    unsigned writemask = nir_intrinsic_write_mask(instr);
5700    Temp data = get_ssa_temp(ctx, instr->src[0].ssa);
5701    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5702    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
5703    assert(elem_size_bytes >= 4 && "Only 32bit & 64bit store_shared currently supported.");
5704
5705    unsigned align = nir_intrinsic_align_mul(instr) ? nir_intrinsic_align(instr) : elem_size_bytes;
5706    store_lds(ctx, elem_size_bytes, data, writemask, address, nir_intrinsic_base(instr), align);
5707 }
5708
5709 void visit_shared_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
5710 {
5711    unsigned offset = nir_intrinsic_base(instr);
5712    Operand m = load_lds_size_m0(ctx);
5713    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5714    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5715
5716    unsigned num_operands = 3;
5717    aco_opcode op32, op64, op32_rtn, op64_rtn;
5718    switch(instr->intrinsic) {
5719       case nir_intrinsic_shared_atomic_add:
5720          op32 = aco_opcode::ds_add_u32;
5721          op64 = aco_opcode::ds_add_u64;
5722          op32_rtn = aco_opcode::ds_add_rtn_u32;
5723          op64_rtn = aco_opcode::ds_add_rtn_u64;
5724          break;
5725       case nir_intrinsic_shared_atomic_imin:
5726          op32 = aco_opcode::ds_min_i32;
5727          op64 = aco_opcode::ds_min_i64;
5728          op32_rtn = aco_opcode::ds_min_rtn_i32;
5729          op64_rtn = aco_opcode::ds_min_rtn_i64;
5730          break;
5731       case nir_intrinsic_shared_atomic_umin:
5732          op32 = aco_opcode::ds_min_u32;
5733          op64 = aco_opcode::ds_min_u64;
5734          op32_rtn = aco_opcode::ds_min_rtn_u32;
5735          op64_rtn = aco_opcode::ds_min_rtn_u64;
5736          break;
5737       case nir_intrinsic_shared_atomic_imax:
5738          op32 = aco_opcode::ds_max_i32;
5739          op64 = aco_opcode::ds_max_i64;
5740          op32_rtn = aco_opcode::ds_max_rtn_i32;
5741          op64_rtn = aco_opcode::ds_max_rtn_i64;
5742          break;
5743       case nir_intrinsic_shared_atomic_umax:
5744          op32 = aco_opcode::ds_max_u32;
5745          op64 = aco_opcode::ds_max_u64;
5746          op32_rtn = aco_opcode::ds_max_rtn_u32;
5747          op64_rtn = aco_opcode::ds_max_rtn_u64;
5748          break;
5749       case nir_intrinsic_shared_atomic_and:
5750          op32 = aco_opcode::ds_and_b32;
5751          op64 = aco_opcode::ds_and_b64;
5752          op32_rtn = aco_opcode::ds_and_rtn_b32;
5753          op64_rtn = aco_opcode::ds_and_rtn_b64;
5754          break;
5755       case nir_intrinsic_shared_atomic_or:
5756          op32 = aco_opcode::ds_or_b32;
5757          op64 = aco_opcode::ds_or_b64;
5758          op32_rtn = aco_opcode::ds_or_rtn_b32;
5759          op64_rtn = aco_opcode::ds_or_rtn_b64;
5760          break;
5761       case nir_intrinsic_shared_atomic_xor:
5762          op32 = aco_opcode::ds_xor_b32;
5763          op64 = aco_opcode::ds_xor_b64;
5764          op32_rtn = aco_opcode::ds_xor_rtn_b32;
5765          op64_rtn = aco_opcode::ds_xor_rtn_b64;
5766          break;
5767       case nir_intrinsic_shared_atomic_exchange:
5768          op32 = aco_opcode::ds_write_b32;
5769          op64 = aco_opcode::ds_write_b64;
5770          op32_rtn = aco_opcode::ds_wrxchg_rtn_b32;
5771          op64_rtn = aco_opcode::ds_wrxchg2_rtn_b64;
5772          break;
5773       case nir_intrinsic_shared_atomic_comp_swap:
5774          op32 = aco_opcode::ds_cmpst_b32;
5775          op64 = aco_opcode::ds_cmpst_b64;
5776          op32_rtn = aco_opcode::ds_cmpst_rtn_b32;
5777          op64_rtn = aco_opcode::ds_cmpst_rtn_b64;
5778          num_operands = 4;
5779          break;
5780       default:
5781          unreachable("Unhandled shared atomic intrinsic");
5782    }
5783
5784    /* return the previous value if dest is ever used */
5785    bool return_previous = false;
5786    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
5787       return_previous = true;
5788       break;
5789    }
5790    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
5791       return_previous = true;
5792       break;
5793    }
5794
5795    aco_opcode op;
5796    if (data.size() == 1) {
5797       assert(instr->dest.ssa.bit_size == 32);
5798       op = return_previous ? op32_rtn : op32;
5799    } else {
5800       assert(instr->dest.ssa.bit_size == 64);
5801       op = return_previous ? op64_rtn : op64;
5802    }
5803
5804    if (offset > 65535) {
5805       Builder bld(ctx->program, ctx->block);
5806       address = bld.vadd32(bld.def(v1), Operand(offset), address);
5807       offset = 0;
5808    }
5809
5810    aco_ptr<DS_instruction> ds;
5811    ds.reset(create_instruction<DS_instruction>(op, Format::DS, num_operands, return_previous ? 1 : 0));
5812    ds->operands[0] = Operand(address);
5813    ds->operands[1] = Operand(data);
5814    if (num_operands == 4)
5815       ds->operands[2] = Operand(get_ssa_temp(ctx, instr->src[2].ssa));
5816    ds->operands[num_operands - 1] = m;
5817    ds->offset0 = offset;
5818    if (return_previous)
5819       ds->definitions[0] = Definition(get_ssa_temp(ctx, &instr->dest.ssa));
5820    ctx->block->instructions.emplace_back(std::move(ds));
5821 }
5822
5823 Temp get_scratch_resource(isel_context *ctx)
5824 {
5825    Builder bld(ctx->program, ctx->block);
5826    Temp scratch_addr = ctx->program->private_segment_buffer;
5827    if (ctx->stage != compute_cs)
5828       scratch_addr = bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), scratch_addr, Operand(0u));
5829
5830    uint32_t rsrc_conf = S_008F0C_ADD_TID_ENABLE(1) |
5831                         S_008F0C_INDEX_STRIDE(ctx->program->wave_size == 64 ? 3 : 2);;
5832
5833    if (ctx->program->chip_class >= GFX10) {
5834       rsrc_conf |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
5835                    S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
5836                    S_008F0C_RESOURCE_LEVEL(1);
5837    } else if (ctx->program->chip_class <= GFX7) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
5838       rsrc_conf |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5839                    S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
5840    }
5841
5842    /* older generations need element size = 16 bytes. element size removed in GFX9 */
5843    if (ctx->program->chip_class <= GFX8)
5844       rsrc_conf |= S_008F0C_ELEMENT_SIZE(3);
5845
5846    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), scratch_addr, Operand(-1u), Operand(rsrc_conf));
5847 }
5848
5849 void visit_load_scratch(isel_context *ctx, nir_intrinsic_instr *instr) {
5850    assert(instr->dest.ssa.bit_size == 32 || instr->dest.ssa.bit_size == 64);
5851    Builder bld(ctx->program, ctx->block);
5852    Temp rsrc = get_scratch_resource(ctx);
5853    Temp offset = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5854    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5855
5856    aco_opcode op;
5857    switch (dst.size()) {
5858       case 1:
5859          op = aco_opcode::buffer_load_dword;
5860          break;
5861       case 2:
5862          op = aco_opcode::buffer_load_dwordx2;
5863          break;
5864       case 3:
5865          op = aco_opcode::buffer_load_dwordx3;
5866          break;
5867       case 4:
5868          op = aco_opcode::buffer_load_dwordx4;
5869          break;
5870       case 6:
5871       case 8: {
5872          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
5873          Temp lower = bld.mubuf(aco_opcode::buffer_load_dwordx4,
5874                                 bld.def(v4), rsrc, offset,
5875                                 ctx->program->scratch_offset, 0, true);
5876          Temp upper = bld.mubuf(dst.size() == 6 ? aco_opcode::buffer_load_dwordx2 :
5877                                                   aco_opcode::buffer_load_dwordx4,
5878                                 dst.size() == 6 ? bld.def(v2) : bld.def(v4),
5879                                 rsrc, offset, ctx->program->scratch_offset, 16, true);
5880          emit_split_vector(ctx, lower, 2);
5881          elems[0] = emit_extract_vector(ctx, lower, 0, v2);
5882          elems[1] = emit_extract_vector(ctx, lower, 1, v2);
5883          if (dst.size() == 8) {
5884             emit_split_vector(ctx, upper, 2);
5885             elems[2] = emit_extract_vector(ctx, upper, 0, v2);
5886             elems[3] = emit_extract_vector(ctx, upper, 1, v2);
5887          } else {
5888             elems[2] = upper;
5889          }
5890
5891          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector,
5892                                                                          Format::PSEUDO, dst.size() / 2, 1)};
5893          for (unsigned i = 0; i < dst.size() / 2; i++)
5894             vec->operands[i] = Operand(elems[i]);
5895          vec->definitions[0] = Definition(dst);
5896          bld.insert(std::move(vec));
5897          ctx->allocated_vec.emplace(dst.id(), elems);
5898          return;
5899       }
5900       default:
5901          unreachable("Wrong dst size for nir_intrinsic_load_scratch");
5902    }
5903
5904    bld.mubuf(op, Definition(dst), rsrc, offset, ctx->program->scratch_offset, 0, true);
5905    emit_split_vector(ctx, dst, instr->num_components);
5906 }
5907
5908 void visit_store_scratch(isel_context *ctx, nir_intrinsic_instr *instr) {
5909    assert(instr->src[0].ssa->bit_size == 32 || instr->src[0].ssa->bit_size == 64);
5910    Builder bld(ctx->program, ctx->block);
5911    Temp rsrc = get_scratch_resource(ctx);
5912    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5913    Temp offset = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5914
5915    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
5916    unsigned writemask = nir_intrinsic_write_mask(instr);
5917
5918    while (writemask) {
5919       int start, count;
5920       u_bit_scan_consecutive_range(&writemask, &start, &count);
5921       int num_bytes = count * elem_size_bytes;
5922
5923       if (num_bytes > 16) {
5924          assert(elem_size_bytes == 8);
5925          writemask |= (((count - 2) << 1) - 1) << (start + 2);
5926          count = 2;
5927          num_bytes = 16;
5928       }
5929
5930       // TODO: check alignment of sub-dword stores
5931       // TODO: split 3 bytes. there is no store instruction for that
5932
5933       Temp write_data;
5934       if (count != instr->num_components) {
5935          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
5936          for (int i = 0; i < count; i++) {
5937             Temp elem = emit_extract_vector(ctx, data, start + i, RegClass(RegType::vgpr, elem_size_bytes / 4));
5938             vec->operands[i] = Operand(elem);
5939          }
5940          write_data = bld.tmp(RegClass(RegType::vgpr, count * elem_size_bytes / 4));
5941          vec->definitions[0] = Definition(write_data);
5942          ctx->block->instructions.emplace_back(std::move(vec));
5943       } else {
5944          write_data = data;
5945       }
5946
5947       aco_opcode op;
5948       switch (num_bytes) {
5949          case 4:
5950             op = aco_opcode::buffer_store_dword;
5951             break;
5952          case 8:
5953             op = aco_opcode::buffer_store_dwordx2;
5954             break;
5955          case 12:
5956             op = aco_opcode::buffer_store_dwordx3;
5957             break;
5958          case 16:
5959             op = aco_opcode::buffer_store_dwordx4;
5960             break;
5961          default:
5962             unreachable("Invalid data size for nir_intrinsic_store_scratch.");
5963       }
5964
5965       bld.mubuf(op, rsrc, offset, ctx->program->scratch_offset, write_data, start * elem_size_bytes, true);
5966    }
5967 }
5968
5969 void visit_load_sample_mask_in(isel_context *ctx, nir_intrinsic_instr *instr) {
5970    uint8_t log2_ps_iter_samples;
5971    if (ctx->program->info->ps.force_persample) {
5972       log2_ps_iter_samples =
5973          util_logbase2(ctx->options->key.fs.num_samples);
5974    } else {
5975       log2_ps_iter_samples = ctx->options->key.fs.log2_ps_iter_samples;
5976    }
5977
5978    /* The bit pattern matches that used by fixed function fragment
5979     * processing. */
5980    static const unsigned ps_iter_masks[] = {
5981       0xffff, /* not used */
5982       0x5555,
5983       0x1111,
5984       0x0101,
5985       0x0001,
5986    };
5987    assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
5988
5989    Builder bld(ctx->program, ctx->block);
5990
5991    Temp sample_id = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1),
5992                              get_arg(ctx, ctx->args->ac.ancillary), Operand(8u), Operand(4u));
5993    Temp ps_iter_mask = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(ps_iter_masks[log2_ps_iter_samples]));
5994    Temp mask = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), sample_id, ps_iter_mask);
5995    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5996    bld.vop2(aco_opcode::v_and_b32, Definition(dst), mask, get_arg(ctx, ctx->args->ac.sample_coverage));
5997 }
5998
5999 void visit_emit_vertex_with_counter(isel_context *ctx, nir_intrinsic_instr *instr) {
6000    Builder bld(ctx->program, ctx->block);
6001
6002    unsigned stream = nir_intrinsic_stream_id(instr);
6003    Temp next_vertex = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
6004    next_vertex = bld.v_mul_imm(bld.def(v1), next_vertex, 4u);
6005    nir_const_value *next_vertex_cv = nir_src_as_const_value(instr->src[0]);
6006
6007    /* get GSVS ring */
6008    Temp gsvs_ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_GSVS_GS * 16u));
6009
6010    unsigned num_components =
6011       ctx->program->info->gs.num_stream_output_components[stream];
6012    assert(num_components);
6013
6014    unsigned stride = 4u * num_components * ctx->shader->info.gs.vertices_out;
6015    unsigned stream_offset = 0;
6016    for (unsigned i = 0; i < stream; i++) {
6017       unsigned prev_stride = 4u * ctx->program->info->gs.num_stream_output_components[i] * ctx->shader->info.gs.vertices_out;
6018       stream_offset += prev_stride * ctx->program->wave_size;
6019    }
6020
6021    /* Limit on the stride field for <= GFX7. */
6022    assert(stride < (1 << 14));
6023
6024    Temp gsvs_dwords[4];
6025    for (unsigned i = 0; i < 4; i++)
6026       gsvs_dwords[i] = bld.tmp(s1);
6027    bld.pseudo(aco_opcode::p_split_vector,
6028               Definition(gsvs_dwords[0]),
6029               Definition(gsvs_dwords[1]),
6030               Definition(gsvs_dwords[2]),
6031               Definition(gsvs_dwords[3]),
6032               gsvs_ring);
6033
6034    if (stream_offset) {
6035       Temp stream_offset_tmp = bld.copy(bld.def(s1), Operand(stream_offset));
6036
6037       Temp carry = bld.tmp(s1);
6038       gsvs_dwords[0] = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), gsvs_dwords[0], stream_offset_tmp);
6039       gsvs_dwords[1] = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), gsvs_dwords[1], Operand(0u), bld.scc(carry));
6040    }
6041
6042    gsvs_dwords[1] = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), gsvs_dwords[1], Operand(S_008F04_STRIDE(stride)));
6043    gsvs_dwords[2] = bld.copy(bld.def(s1), Operand((uint32_t)ctx->program->wave_size));
6044
6045    gsvs_ring = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
6046                           gsvs_dwords[0], gsvs_dwords[1], gsvs_dwords[2], gsvs_dwords[3]);
6047
6048    unsigned offset = 0;
6049    for (unsigned i = 0; i <= VARYING_SLOT_VAR31; i++) {
6050       if (ctx->program->info->gs.output_streams[i] != stream)
6051          continue;
6052
6053       for (unsigned j = 0; j < 4; j++) {
6054          if (!(ctx->program->info->gs.output_usage_mask[i] & (1 << j)))
6055             continue;
6056
6057          if (ctx->outputs.mask[i] & (1 << j)) {
6058             Operand vaddr_offset = next_vertex_cv ? Operand(v1) : Operand(next_vertex);
6059             unsigned const_offset = (offset + (next_vertex_cv ? next_vertex_cv->u32 : 0u)) * 4u;
6060             if (const_offset >= 4096u) {
6061                if (vaddr_offset.isUndefined())
6062                   vaddr_offset = bld.copy(bld.def(v1), Operand(const_offset / 4096u * 4096u));
6063                else
6064                   vaddr_offset = bld.vadd32(bld.def(v1), Operand(const_offset / 4096u * 4096u), vaddr_offset);
6065                const_offset %= 4096u;
6066             }
6067
6068             aco_ptr<MTBUF_instruction> mtbuf{create_instruction<MTBUF_instruction>(aco_opcode::tbuffer_store_format_x, Format::MTBUF, 4, 0)};
6069             mtbuf->operands[0] = Operand(gsvs_ring);
6070             mtbuf->operands[1] = vaddr_offset;
6071             mtbuf->operands[2] = Operand(get_arg(ctx, ctx->args->gs2vs_offset));
6072             mtbuf->operands[3] = Operand(ctx->outputs.outputs[i][j]);
6073             mtbuf->offen = !vaddr_offset.isUndefined();
6074             mtbuf->dfmt = V_008F0C_BUF_DATA_FORMAT_32;
6075             mtbuf->nfmt = V_008F0C_BUF_NUM_FORMAT_UINT;
6076             mtbuf->offset = const_offset;
6077             mtbuf->glc = true;
6078             mtbuf->slc = true;
6079             mtbuf->barrier = barrier_gs_data;
6080             mtbuf->can_reorder = true;
6081             bld.insert(std::move(mtbuf));
6082          }
6083
6084          offset += ctx->shader->info.gs.vertices_out;
6085       }
6086
6087       /* outputs for the next vertex are undefined and keeping them around can
6088        * create invalid IR with control flow */
6089       ctx->outputs.mask[i] = 0;
6090    }
6091
6092    bld.sopp(aco_opcode::s_sendmsg, bld.m0(ctx->gs_wave_id), -1, sendmsg_gs(false, true, stream));
6093 }
6094
6095 Temp emit_boolean_reduce(isel_context *ctx, nir_op op, unsigned cluster_size, Temp src)
6096 {
6097    Builder bld(ctx->program, ctx->block);
6098
6099    if (cluster_size == 1) {
6100       return src;
6101    } if (op == nir_op_iand && cluster_size == 4) {
6102       //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6103       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src);
6104       return bld.sop1(Builder::s_not, bld.def(bld.lm), bld.def(s1, scc),
6105                       bld.sop1(Builder::s_wqm, bld.def(bld.lm), bld.def(s1, scc), tmp));
6106    } else if (op == nir_op_ior && cluster_size == 4) {
6107       //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6108       return bld.sop1(Builder::s_wqm, bld.def(bld.lm), bld.def(s1, scc),
6109                       bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm)));
6110    } else if (op == nir_op_iand && cluster_size == ctx->program->wave_size) {
6111       //subgroupAnd(val) -> (exec & ~val) == 0
6112       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src).def(1).getTemp();
6113       Temp cond = bool_to_vector_condition(ctx, emit_wqm(ctx, tmp));
6114       return bld.sop1(Builder::s_not, bld.def(bld.lm), bld.def(s1, scc), cond);
6115    } else if (op == nir_op_ior && cluster_size == ctx->program->wave_size) {
6116       //subgroupOr(val) -> (val & exec) != 0
6117       Temp tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm)).def(1).getTemp();
6118       return bool_to_vector_condition(ctx, tmp);
6119    } else if (op == nir_op_ixor && cluster_size == ctx->program->wave_size) {
6120       //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6121       Temp tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
6122       tmp = bld.sop1(Builder::s_bcnt1_i32, bld.def(s1), bld.def(s1, scc), tmp);
6123       tmp = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), tmp, Operand(1u)).def(1).getTemp();
6124       return bool_to_vector_condition(ctx, tmp);
6125    } else {
6126       //subgroupClustered{And,Or,Xor}(val, n) ->
6127       //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ;  just v_mbcnt_lo_u32_b32 on wave32
6128       //cluster_offset = ~(n - 1) & lane_id
6129       //cluster_mask = ((1 << n) - 1)
6130       //subgroupClusteredAnd():
6131       //   return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6132       //subgroupClusteredOr():
6133       //   return ((val & exec) >> cluster_offset) & cluster_mask != 0
6134       //subgroupClusteredXor():
6135       //   return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6136       Temp lane_id = emit_mbcnt(ctx, bld.def(v1));
6137       Temp cluster_offset = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(~uint32_t(cluster_size - 1)), lane_id);
6138
6139       Temp tmp;
6140       if (op == nir_op_iand)
6141          tmp = bld.sop2(Builder::s_orn2, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
6142       else
6143          tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
6144
6145       uint32_t cluster_mask = cluster_size == 32 ? -1 : (1u << cluster_size) - 1u;
6146
6147       if (ctx->program->chip_class <= GFX7)
6148          tmp = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), tmp, cluster_offset);
6149       else if (ctx->program->wave_size == 64)
6150          tmp = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), cluster_offset, tmp);
6151       else
6152          tmp = bld.vop2_e64(aco_opcode::v_lshrrev_b32, bld.def(v1), cluster_offset, tmp);
6153       tmp = emit_extract_vector(ctx, tmp, 0, v1);
6154       if (cluster_mask != 0xffffffff)
6155          tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(cluster_mask), tmp);
6156
6157       Definition cmp_def = Definition();
6158       if (op == nir_op_iand) {
6159          cmp_def = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm), Operand(cluster_mask), tmp).def(0);
6160       } else if (op == nir_op_ior) {
6161          cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp).def(0);
6162       } else if (op == nir_op_ixor) {
6163          tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u),
6164                         bld.vop3(aco_opcode::v_bcnt_u32_b32, bld.def(v1), tmp, Operand(0u)));
6165          cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp).def(0);
6166       }
6167       cmp_def.setHint(vcc);
6168       return cmp_def.getTemp();
6169    }
6170 }
6171
6172 Temp emit_boolean_exclusive_scan(isel_context *ctx, nir_op op, Temp src)
6173 {
6174    Builder bld(ctx->program, ctx->block);
6175
6176    //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
6177    //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
6178    //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
6179    Temp tmp;
6180    if (op == nir_op_iand)
6181       tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src);
6182    else
6183       tmp = bld.sop2(Builder::s_and, bld.def(s2), bld.def(s1, scc), src, Operand(exec, bld.lm));
6184
6185    Builder::Result lohi = bld.pseudo(aco_opcode::p_split_vector, bld.def(s1), bld.def(s1), tmp);
6186    Temp lo = lohi.def(0).getTemp();
6187    Temp hi = lohi.def(1).getTemp();
6188    Temp mbcnt = emit_mbcnt(ctx, bld.def(v1), Operand(lo), Operand(hi));
6189
6190    Definition cmp_def = Definition();
6191    if (op == nir_op_iand)
6192       cmp_def = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm), Operand(0u), mbcnt).def(0);
6193    else if (op == nir_op_ior)
6194       cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), mbcnt).def(0);
6195    else if (op == nir_op_ixor)
6196       cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u),
6197                          bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u), mbcnt)).def(0);
6198    cmp_def.setHint(vcc);
6199    return cmp_def.getTemp();
6200 }
6201
6202 Temp emit_boolean_inclusive_scan(isel_context *ctx, nir_op op, Temp src)
6203 {
6204    Builder bld(ctx->program, ctx->block);
6205
6206    //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
6207    //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
6208    //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
6209    Temp tmp = emit_boolean_exclusive_scan(ctx, op, src);
6210    if (op == nir_op_iand)
6211       return bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
6212    else if (op == nir_op_ior)
6213       return bld.sop2(Builder::s_or, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
6214    else if (op == nir_op_ixor)
6215       return bld.sop2(Builder::s_xor, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
6216
6217    assert(false);
6218    return Temp();
6219 }
6220
6221 void emit_uniform_subgroup(isel_context *ctx, nir_intrinsic_instr *instr, Temp src)
6222 {
6223    Builder bld(ctx->program, ctx->block);
6224    Definition dst(get_ssa_temp(ctx, &instr->dest.ssa));
6225    if (src.regClass().type() == RegType::vgpr) {
6226       bld.pseudo(aco_opcode::p_as_uniform, dst, src);
6227    } else if (src.regClass() == s1) {
6228       bld.sop1(aco_opcode::s_mov_b32, dst, src);
6229    } else if (src.regClass() == s2) {
6230       bld.sop1(aco_opcode::s_mov_b64, dst, src);
6231    } else {
6232       fprintf(stderr, "Unimplemented NIR instr bit size: ");
6233       nir_print_instr(&instr->instr, stderr);
6234       fprintf(stderr, "\n");
6235    }
6236 }
6237
6238 void emit_interp_center(isel_context *ctx, Temp dst, Temp pos1, Temp pos2)
6239 {
6240    Builder bld(ctx->program, ctx->block);
6241    Temp persp_center = get_arg(ctx, ctx->args->ac.persp_center);
6242    Temp p1 = emit_extract_vector(ctx, persp_center, 0, v1);
6243    Temp p2 = emit_extract_vector(ctx, persp_center, 1, v1);
6244
6245    Temp ddx_1, ddx_2, ddy_1, ddy_2;
6246    uint32_t dpp_ctrl0 = dpp_quad_perm(0, 0, 0, 0);
6247    uint32_t dpp_ctrl1 = dpp_quad_perm(1, 1, 1, 1);
6248    uint32_t dpp_ctrl2 = dpp_quad_perm(2, 2, 2, 2);
6249
6250    /* Build DD X/Y */
6251    if (ctx->program->chip_class >= GFX8) {
6252       Temp tl_1 = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), p1, dpp_ctrl0);
6253       ddx_1 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p1, tl_1, dpp_ctrl1);
6254       ddy_1 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p1, tl_1, dpp_ctrl2);
6255       Temp tl_2 = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), p2, dpp_ctrl0);
6256       ddx_2 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p2, tl_2, dpp_ctrl1);
6257       ddy_2 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p2, tl_2, dpp_ctrl2);
6258    } else {
6259       Temp tl_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl0);
6260       ddx_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl1);
6261       ddx_1 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddx_1, tl_1);
6262       ddx_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl2);
6263       ddx_2 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddx_2, tl_1);
6264       Temp tl_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl0);
6265       ddy_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl1);
6266       ddy_1 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddy_1, tl_2);
6267       ddy_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl2);
6268       ddy_2 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddy_2, tl_2);
6269    }
6270
6271    /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
6272    Temp tmp1 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddx_1, pos1, p1);
6273    Temp tmp2 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddx_2, pos1, p2);
6274    tmp1 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddy_1, pos2, tmp1);
6275    tmp2 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddy_2, pos2, tmp2);
6276    Temp wqm1 = bld.tmp(v1);
6277    emit_wqm(ctx, tmp1, wqm1, true);
6278    Temp wqm2 = bld.tmp(v1);
6279    emit_wqm(ctx, tmp2, wqm2, true);
6280    bld.pseudo(aco_opcode::p_create_vector, Definition(dst), wqm1, wqm2);
6281    return;
6282 }
6283
6284 void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr)
6285 {
6286    Builder bld(ctx->program, ctx->block);
6287    switch(instr->intrinsic) {
6288    case nir_intrinsic_load_barycentric_sample:
6289    case nir_intrinsic_load_barycentric_pixel:
6290    case nir_intrinsic_load_barycentric_centroid: {
6291       glsl_interp_mode mode = (glsl_interp_mode)nir_intrinsic_interp_mode(instr);
6292       Temp bary = Temp(0, s2);
6293       switch (mode) {
6294       case INTERP_MODE_SMOOTH:
6295       case INTERP_MODE_NONE:
6296          if (instr->intrinsic == nir_intrinsic_load_barycentric_pixel)
6297             bary = get_arg(ctx, ctx->args->ac.persp_center);
6298          else if (instr->intrinsic == nir_intrinsic_load_barycentric_centroid)
6299             bary = ctx->persp_centroid;
6300          else if (instr->intrinsic == nir_intrinsic_load_barycentric_sample)
6301             bary = get_arg(ctx, ctx->args->ac.persp_sample);
6302          break;
6303       case INTERP_MODE_NOPERSPECTIVE:
6304          if (instr->intrinsic == nir_intrinsic_load_barycentric_pixel)
6305             bary = get_arg(ctx, ctx->args->ac.linear_center);
6306          else if (instr->intrinsic == nir_intrinsic_load_barycentric_centroid)
6307             bary = ctx->linear_centroid;
6308          else if (instr->intrinsic == nir_intrinsic_load_barycentric_sample)
6309             bary = get_arg(ctx, ctx->args->ac.linear_sample);
6310          break;
6311       default:
6312          break;
6313       }
6314       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6315       Temp p1 = emit_extract_vector(ctx, bary, 0, v1);
6316       Temp p2 = emit_extract_vector(ctx, bary, 1, v1);
6317       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
6318                  Operand(p1), Operand(p2));
6319       emit_split_vector(ctx, dst, 2);
6320       break;
6321    }
6322    case nir_intrinsic_load_barycentric_model: {
6323       Temp model = get_arg(ctx, ctx->args->ac.pull_model);
6324
6325       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6326       Temp p1 = emit_extract_vector(ctx, model, 0, v1);
6327       Temp p2 = emit_extract_vector(ctx, model, 1, v1);
6328       Temp p3 = emit_extract_vector(ctx, model, 2, v1);
6329       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
6330                  Operand(p1), Operand(p2), Operand(p3));
6331       emit_split_vector(ctx, dst, 3);
6332       break;
6333    }
6334    case nir_intrinsic_load_barycentric_at_sample: {
6335       uint32_t sample_pos_offset = RING_PS_SAMPLE_POSITIONS * 16;
6336       switch (ctx->options->key.fs.num_samples) {
6337          case 2: sample_pos_offset += 1 << 3; break;
6338          case 4: sample_pos_offset += 3 << 3; break;
6339          case 8: sample_pos_offset += 7 << 3; break;
6340          default: break;
6341       }
6342       Temp sample_pos;
6343       Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
6344       nir_const_value* const_addr = nir_src_as_const_value(instr->src[0]);
6345       Temp private_segment_buffer = ctx->program->private_segment_buffer;
6346       if (addr.type() == RegType::sgpr) {
6347          Operand offset;
6348          if (const_addr) {
6349             sample_pos_offset += const_addr->u32 << 3;
6350             offset = Operand(sample_pos_offset);
6351          } else if (ctx->options->chip_class >= GFX9) {
6352             offset = bld.sop2(aco_opcode::s_lshl3_add_u32, bld.def(s1), bld.def(s1, scc), addr, Operand(sample_pos_offset));
6353          } else {
6354             offset = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), addr, Operand(3u));
6355             offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), addr, Operand(sample_pos_offset));
6356          }
6357
6358          Operand off = bld.copy(bld.def(s1), Operand(offset));
6359          sample_pos = bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), private_segment_buffer, off);
6360
6361       } else if (ctx->options->chip_class >= GFX9) {
6362          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
6363          sample_pos = bld.global(aco_opcode::global_load_dwordx2, bld.def(v2), addr, private_segment_buffer, sample_pos_offset);
6364       } else if (ctx->options->chip_class >= GFX7) {
6365          /* addr += private_segment_buffer + sample_pos_offset */
6366          Temp tmp0 = bld.tmp(s1);
6367          Temp tmp1 = bld.tmp(s1);
6368          bld.pseudo(aco_opcode::p_split_vector, Definition(tmp0), Definition(tmp1), private_segment_buffer);
6369          Definition scc_tmp = bld.def(s1, scc);
6370          tmp0 = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), scc_tmp, tmp0, Operand(sample_pos_offset));
6371          tmp1 = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), tmp1, Operand(0u), bld.scc(scc_tmp.getTemp()));
6372          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
6373          Temp pck0 = bld.tmp(v1);
6374          Temp carry = bld.vadd32(Definition(pck0), tmp0, addr, true).def(1).getTemp();
6375          tmp1 = as_vgpr(ctx, tmp1);
6376          Temp pck1 = bld.vop2_e64(aco_opcode::v_addc_co_u32, bld.def(v1), bld.hint_vcc(bld.def(bld.lm)), tmp1, Operand(0u), carry);
6377          addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), pck0, pck1);
6378
6379          /* sample_pos = flat_load_dwordx2 addr */
6380          sample_pos = bld.flat(aco_opcode::flat_load_dwordx2, bld.def(v2), addr, Operand(s1));
6381       } else {
6382          assert(ctx->options->chip_class == GFX6);
6383
6384          uint32_t rsrc_conf = S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
6385                               S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
6386          Temp rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), private_segment_buffer, Operand(0u), Operand(rsrc_conf));
6387
6388          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
6389          addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), addr, Operand(0u));
6390
6391          sample_pos = bld.tmp(v2);
6392
6393          aco_ptr<MUBUF_instruction> load{create_instruction<MUBUF_instruction>(aco_opcode::buffer_load_dwordx2, Format::MUBUF, 3, 1)};
6394          load->definitions[0] = Definition(sample_pos);
6395          load->operands[0] = Operand(rsrc);
6396          load->operands[1] = Operand(addr);
6397          load->operands[2] = Operand(0u);
6398          load->offset = sample_pos_offset;
6399          load->offen = 0;
6400          load->addr64 = true;
6401          load->glc = false;
6402          load->dlc = false;
6403          load->disable_wqm = false;
6404          load->barrier = barrier_none;
6405          load->can_reorder = true;
6406          ctx->block->instructions.emplace_back(std::move(load));
6407       }
6408
6409       /* sample_pos -= 0.5 */
6410       Temp pos1 = bld.tmp(RegClass(sample_pos.type(), 1));
6411       Temp pos2 = bld.tmp(RegClass(sample_pos.type(), 1));
6412       bld.pseudo(aco_opcode::p_split_vector, Definition(pos1), Definition(pos2), sample_pos);
6413       pos1 = bld.vop2_e64(aco_opcode::v_sub_f32, bld.def(v1), pos1, Operand(0x3f000000u));
6414       pos2 = bld.vop2_e64(aco_opcode::v_sub_f32, bld.def(v1), pos2, Operand(0x3f000000u));
6415
6416       emit_interp_center(ctx, get_ssa_temp(ctx, &instr->dest.ssa), pos1, pos2);
6417       break;
6418    }
6419    case nir_intrinsic_load_barycentric_at_offset: {
6420       Temp offset = get_ssa_temp(ctx, instr->src[0].ssa);
6421       RegClass rc = RegClass(offset.type(), 1);
6422       Temp pos1 = bld.tmp(rc), pos2 = bld.tmp(rc);
6423       bld.pseudo(aco_opcode::p_split_vector, Definition(pos1), Definition(pos2), offset);
6424       emit_interp_center(ctx, get_ssa_temp(ctx, &instr->dest.ssa), pos1, pos2);
6425       break;
6426    }
6427    case nir_intrinsic_load_front_face: {
6428       bld.vopc(aco_opcode::v_cmp_lg_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6429                Operand(0u), get_arg(ctx, ctx->args->ac.front_face)).def(0).setHint(vcc);
6430       break;
6431    }
6432    case nir_intrinsic_load_view_index: {
6433       if (ctx->stage & (sw_vs | sw_gs | sw_tcs | sw_tes)) {
6434          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6435          bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.view_index)));
6436          break;
6437       }
6438
6439       /* fallthrough */
6440    }
6441    case nir_intrinsic_load_layer_id: {
6442       unsigned idx = nir_intrinsic_base(instr);
6443       bld.vintrp(aco_opcode::v_interp_mov_f32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6444                  Operand(2u), bld.m0(get_arg(ctx, ctx->args->ac.prim_mask)), idx, 0);
6445       break;
6446    }
6447    case nir_intrinsic_load_frag_coord: {
6448       emit_load_frag_coord(ctx, get_ssa_temp(ctx, &instr->dest.ssa), 4);
6449       break;
6450    }
6451    case nir_intrinsic_load_sample_pos: {
6452       Temp posx = get_arg(ctx, ctx->args->ac.frag_pos[0]);
6453       Temp posy = get_arg(ctx, ctx->args->ac.frag_pos[1]);
6454       bld.pseudo(aco_opcode::p_create_vector, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6455                  posx.id() ? bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), posx) : Operand(0u),
6456                  posy.id() ? bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), posy) : Operand(0u));
6457       break;
6458    }
6459    case nir_intrinsic_load_tess_coord:
6460       visit_load_tess_coord(ctx, instr);
6461       break;
6462    case nir_intrinsic_load_interpolated_input:
6463       visit_load_interpolated_input(ctx, instr);
6464       break;
6465    case nir_intrinsic_store_output:
6466       visit_store_output(ctx, instr);
6467       break;
6468    case nir_intrinsic_load_input:
6469    case nir_intrinsic_load_input_vertex:
6470       visit_load_input(ctx, instr);
6471       break;
6472    case nir_intrinsic_load_per_vertex_input:
6473       visit_load_per_vertex_input(ctx, instr);
6474       break;
6475    case nir_intrinsic_load_ubo:
6476       visit_load_ubo(ctx, instr);
6477       break;
6478    case nir_intrinsic_load_push_constant:
6479       visit_load_push_constant(ctx, instr);
6480       break;
6481    case nir_intrinsic_load_constant:
6482       visit_load_constant(ctx, instr);
6483       break;
6484    case nir_intrinsic_vulkan_resource_index:
6485       visit_load_resource(ctx, instr);
6486       break;
6487    case nir_intrinsic_discard:
6488       visit_discard(ctx, instr);
6489       break;
6490    case nir_intrinsic_discard_if:
6491       visit_discard_if(ctx, instr);
6492       break;
6493    case nir_intrinsic_load_shared:
6494       visit_load_shared(ctx, instr);
6495       break;
6496    case nir_intrinsic_store_shared:
6497       visit_store_shared(ctx, instr);
6498       break;
6499    case nir_intrinsic_shared_atomic_add:
6500    case nir_intrinsic_shared_atomic_imin:
6501    case nir_intrinsic_shared_atomic_umin:
6502    case nir_intrinsic_shared_atomic_imax:
6503    case nir_intrinsic_shared_atomic_umax:
6504    case nir_intrinsic_shared_atomic_and:
6505    case nir_intrinsic_shared_atomic_or:
6506    case nir_intrinsic_shared_atomic_xor:
6507    case nir_intrinsic_shared_atomic_exchange:
6508    case nir_intrinsic_shared_atomic_comp_swap:
6509       visit_shared_atomic(ctx, instr);
6510       break;
6511    case nir_intrinsic_image_deref_load:
6512       visit_image_load(ctx, instr);
6513       break;
6514    case nir_intrinsic_image_deref_store:
6515       visit_image_store(ctx, instr);
6516       break;
6517    case nir_intrinsic_image_deref_atomic_add:
6518    case nir_intrinsic_image_deref_atomic_umin:
6519    case nir_intrinsic_image_deref_atomic_imin:
6520    case nir_intrinsic_image_deref_atomic_umax:
6521    case nir_intrinsic_image_deref_atomic_imax:
6522    case nir_intrinsic_image_deref_atomic_and:
6523    case nir_intrinsic_image_deref_atomic_or:
6524    case nir_intrinsic_image_deref_atomic_xor:
6525    case nir_intrinsic_image_deref_atomic_exchange:
6526    case nir_intrinsic_image_deref_atomic_comp_swap:
6527       visit_image_atomic(ctx, instr);
6528       break;
6529    case nir_intrinsic_image_deref_size:
6530       visit_image_size(ctx, instr);
6531       break;
6532    case nir_intrinsic_load_ssbo:
6533       visit_load_ssbo(ctx, instr);
6534       break;
6535    case nir_intrinsic_store_ssbo:
6536       visit_store_ssbo(ctx, instr);
6537       break;
6538    case nir_intrinsic_load_global:
6539       visit_load_global(ctx, instr);
6540       break;
6541    case nir_intrinsic_store_global:
6542       visit_store_global(ctx, instr);
6543       break;
6544    case nir_intrinsic_global_atomic_add:
6545    case nir_intrinsic_global_atomic_imin:
6546    case nir_intrinsic_global_atomic_umin:
6547    case nir_intrinsic_global_atomic_imax:
6548    case nir_intrinsic_global_atomic_umax:
6549    case nir_intrinsic_global_atomic_and:
6550    case nir_intrinsic_global_atomic_or:
6551    case nir_intrinsic_global_atomic_xor:
6552    case nir_intrinsic_global_atomic_exchange:
6553    case nir_intrinsic_global_atomic_comp_swap:
6554       visit_global_atomic(ctx, instr);
6555       break;
6556    case nir_intrinsic_ssbo_atomic_add:
6557    case nir_intrinsic_ssbo_atomic_imin:
6558    case nir_intrinsic_ssbo_atomic_umin:
6559    case nir_intrinsic_ssbo_atomic_imax:
6560    case nir_intrinsic_ssbo_atomic_umax:
6561    case nir_intrinsic_ssbo_atomic_and:
6562    case nir_intrinsic_ssbo_atomic_or:
6563    case nir_intrinsic_ssbo_atomic_xor:
6564    case nir_intrinsic_ssbo_atomic_exchange:
6565    case nir_intrinsic_ssbo_atomic_comp_swap:
6566       visit_atomic_ssbo(ctx, instr);
6567       break;
6568    case nir_intrinsic_load_scratch:
6569       visit_load_scratch(ctx, instr);
6570       break;
6571    case nir_intrinsic_store_scratch:
6572       visit_store_scratch(ctx, instr);
6573       break;
6574    case nir_intrinsic_get_buffer_size:
6575       visit_get_buffer_size(ctx, instr);
6576       break;
6577    case nir_intrinsic_control_barrier: {
6578       if (ctx->program->chip_class == GFX6 && ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) {
6579          /* GFX6 only (thanks to a hw bug workaround):
6580           * The real barrier instruction isn’t needed, because an entire patch
6581           * always fits into a single wave.
6582           */
6583          break;
6584       }
6585
6586       if (ctx->shader->info.stage == MESA_SHADER_COMPUTE) {
6587          unsigned* bsize = ctx->program->info->cs.block_size;
6588          unsigned workgroup_size = bsize[0] * bsize[1] * bsize[2];
6589          if (workgroup_size > ctx->program->wave_size)
6590             bld.sopp(aco_opcode::s_barrier);
6591       } else if (ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) {
6592          /* For each patch provided during rendering, n TCS shader invocations will be processed,
6593           * where n is the number of vertices in the output patch.
6594           */
6595          unsigned workgroup_size = ctx->tcs_num_patches * ctx->shader->info.tess.tcs_vertices_out;
6596          if (workgroup_size > ctx->program->wave_size)
6597             bld.sopp(aco_opcode::s_barrier);
6598       } else {
6599          /* We don't know the workgroup size, so always emit the s_barrier. */
6600          bld.sopp(aco_opcode::s_barrier);
6601       }
6602
6603       break;
6604    }
6605    case nir_intrinsic_memory_barrier_tcs_patch:
6606    case nir_intrinsic_group_memory_barrier:
6607    case nir_intrinsic_memory_barrier:
6608    case nir_intrinsic_memory_barrier_buffer:
6609    case nir_intrinsic_memory_barrier_image:
6610    case nir_intrinsic_memory_barrier_shared:
6611       emit_memory_barrier(ctx, instr);
6612       break;
6613    case nir_intrinsic_load_num_work_groups: {
6614       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6615       bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.num_work_groups)));
6616       emit_split_vector(ctx, dst, 3);
6617       break;
6618    }
6619    case nir_intrinsic_load_local_invocation_id: {
6620       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6621       bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.local_invocation_ids)));
6622       emit_split_vector(ctx, dst, 3);
6623       break;
6624    }
6625    case nir_intrinsic_load_work_group_id: {
6626       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6627       struct ac_arg *args = ctx->args->ac.workgroup_ids;
6628       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
6629                  args[0].used ? Operand(get_arg(ctx, args[0])) : Operand(0u),
6630                  args[1].used ? Operand(get_arg(ctx, args[1])) : Operand(0u),
6631                  args[2].used ? Operand(get_arg(ctx, args[2])) : Operand(0u));
6632       emit_split_vector(ctx, dst, 3);
6633       break;
6634    }
6635    case nir_intrinsic_load_local_invocation_index: {
6636       Temp id = emit_mbcnt(ctx, bld.def(v1));
6637
6638       /* The tg_size bits [6:11] contain the subgroup id,
6639        * we need this multiplied by the wave size, and then OR the thread id to it.
6640        */
6641       if (ctx->program->wave_size == 64) {
6642          /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
6643          Temp tg_num = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0xfc0u),
6644                                 get_arg(ctx, ctx->args->ac.tg_size));
6645          bld.vop2(aco_opcode::v_or_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), tg_num, id);
6646       } else {
6647          /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR  */
6648          Temp tg_num = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
6649                                 get_arg(ctx, ctx->args->ac.tg_size), Operand(0x6u | (0x6u << 16)));
6650          bld.vop3(aco_opcode::v_lshl_or_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), tg_num, Operand(0x5u), id);
6651       }
6652       break;
6653    }
6654    case nir_intrinsic_load_subgroup_id: {
6655       if (ctx->stage == compute_cs) {
6656          bld.sop2(aco_opcode::s_bfe_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), bld.def(s1, scc),
6657                   get_arg(ctx, ctx->args->ac.tg_size), Operand(0x6u | (0x6u << 16)));
6658       } else {
6659          bld.sop1(aco_opcode::s_mov_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand(0x0u));
6660       }
6661       break;
6662    }
6663    case nir_intrinsic_load_subgroup_invocation: {
6664       emit_mbcnt(ctx, Definition(get_ssa_temp(ctx, &instr->dest.ssa)));
6665       break;
6666    }
6667    case nir_intrinsic_load_num_subgroups: {
6668       if (ctx->stage == compute_cs)
6669          bld.sop2(aco_opcode::s_and_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), bld.def(s1, scc), Operand(0x3fu),
6670                   get_arg(ctx, ctx->args->ac.tg_size));
6671       else
6672          bld.sop1(aco_opcode::s_mov_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand(0x1u));
6673       break;
6674    }
6675    case nir_intrinsic_ballot: {
6676       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6677       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6678       Definition tmp = bld.def(dst.regClass());
6679       Definition lanemask_tmp = dst.size() == bld.lm.size() ? tmp : bld.def(src.regClass());
6680       if (instr->src[0].ssa->bit_size == 1) {
6681          assert(src.regClass() == bld.lm);
6682          bld.sop2(Builder::s_and, lanemask_tmp, bld.def(s1, scc), Operand(exec, bld.lm), src);
6683       } else if (instr->src[0].ssa->bit_size == 32 && src.regClass() == v1) {
6684          bld.vopc(aco_opcode::v_cmp_lg_u32, lanemask_tmp, Operand(0u), src);
6685       } else if (instr->src[0].ssa->bit_size == 64 && src.regClass() == v2) {
6686          bld.vopc(aco_opcode::v_cmp_lg_u64, lanemask_tmp, Operand(0u), src);
6687       } else {
6688          fprintf(stderr, "Unimplemented NIR instr bit size: ");
6689          nir_print_instr(&instr->instr, stderr);
6690          fprintf(stderr, "\n");
6691       }
6692       if (dst.size() != bld.lm.size()) {
6693          /* Wave32 with ballot size set to 64 */
6694          bld.pseudo(aco_opcode::p_create_vector, Definition(tmp), lanemask_tmp.getTemp(), Operand(0u));
6695       }
6696       emit_wqm(ctx, tmp.getTemp(), dst);
6697       break;
6698    }
6699    case nir_intrinsic_shuffle:
6700    case nir_intrinsic_read_invocation: {
6701       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6702       if (!ctx->divergent_vals[instr->src[0].ssa->index]) {
6703          emit_uniform_subgroup(ctx, instr, src);
6704       } else {
6705          Temp tid = get_ssa_temp(ctx, instr->src[1].ssa);
6706          if (instr->intrinsic == nir_intrinsic_read_invocation || !ctx->divergent_vals[instr->src[1].ssa->index])
6707             tid = bld.as_uniform(tid);
6708          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6709          if (src.regClass() == v1) {
6710             emit_wqm(ctx, emit_bpermute(ctx, bld, tid, src), dst);
6711          } else if (src.regClass() == v2) {
6712             Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6713             bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6714             lo = emit_wqm(ctx, emit_bpermute(ctx, bld, tid, lo));
6715             hi = emit_wqm(ctx, emit_bpermute(ctx, bld, tid, hi));
6716             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6717             emit_split_vector(ctx, dst, 2);
6718          } else if (instr->dest.ssa.bit_size == 1 && tid.regClass() == s1) {
6719             assert(src.regClass() == bld.lm);
6720             Temp tmp = bld.sopc(Builder::s_bitcmp1, bld.def(s1, scc), src, tid);
6721             bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
6722          } else if (instr->dest.ssa.bit_size == 1 && tid.regClass() == v1) {
6723             assert(src.regClass() == bld.lm);
6724             Temp tmp;
6725             if (ctx->program->chip_class <= GFX7)
6726                tmp = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), src, tid);
6727             else if (ctx->program->wave_size == 64)
6728                tmp = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), tid, src);
6729             else
6730                tmp = bld.vop2_e64(aco_opcode::v_lshrrev_b32, bld.def(v1), tid, src);
6731             tmp = emit_extract_vector(ctx, tmp, 0, v1);
6732             tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u), tmp);
6733             emit_wqm(ctx, bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp), dst);
6734          } else {
6735             fprintf(stderr, "Unimplemented NIR instr bit size: ");
6736             nir_print_instr(&instr->instr, stderr);
6737             fprintf(stderr, "\n");
6738          }
6739       }
6740       break;
6741    }
6742    case nir_intrinsic_load_sample_id: {
6743       bld.vop3(aco_opcode::v_bfe_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6744                get_arg(ctx, ctx->args->ac.ancillary), Operand(8u), Operand(4u));
6745       break;
6746    }
6747    case nir_intrinsic_load_sample_mask_in: {
6748       visit_load_sample_mask_in(ctx, instr);
6749       break;
6750    }
6751    case nir_intrinsic_read_first_invocation: {
6752       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6753       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6754       if (src.regClass() == v1) {
6755          emit_wqm(ctx,
6756                   bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), src),
6757                   dst);
6758       } else if (src.regClass() == v2) {
6759          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6760          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6761          lo = emit_wqm(ctx, bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), lo));
6762          hi = emit_wqm(ctx, bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), hi));
6763          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6764          emit_split_vector(ctx, dst, 2);
6765       } else if (instr->dest.ssa.bit_size == 1) {
6766          assert(src.regClass() == bld.lm);
6767          Temp tmp = bld.sopc(Builder::s_bitcmp1, bld.def(s1, scc), src,
6768                              bld.sop1(Builder::s_ff1_i32, bld.def(s1), Operand(exec, bld.lm)));
6769          bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
6770       } else if (src.regClass() == s1) {
6771          bld.sop1(aco_opcode::s_mov_b32, Definition(dst), src);
6772       } else if (src.regClass() == s2) {
6773          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src);
6774       } else {
6775          fprintf(stderr, "Unimplemented NIR instr bit size: ");
6776          nir_print_instr(&instr->instr, stderr);
6777          fprintf(stderr, "\n");
6778       }
6779       break;
6780    }
6781    case nir_intrinsic_vote_all: {
6782       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6783       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6784       assert(src.regClass() == bld.lm);
6785       assert(dst.regClass() == bld.lm);
6786
6787       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src).def(1).getTemp();
6788       Temp cond = bool_to_vector_condition(ctx, emit_wqm(ctx, tmp));
6789       bld.sop1(Builder::s_not, Definition(dst), bld.def(s1, scc), cond);
6790       break;
6791    }
6792    case nir_intrinsic_vote_any: {
6793       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6794       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6795       assert(src.regClass() == bld.lm);
6796       assert(dst.regClass() == bld.lm);
6797
6798       Temp tmp = bool_to_scalar_condition(ctx, src);
6799       bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
6800       break;
6801    }
6802    case nir_intrinsic_reduce:
6803    case nir_intrinsic_inclusive_scan:
6804    case nir_intrinsic_exclusive_scan: {
6805       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6806       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6807       nir_op op = (nir_op) nir_intrinsic_reduction_op(instr);
6808       unsigned cluster_size = instr->intrinsic == nir_intrinsic_reduce ?
6809          nir_intrinsic_cluster_size(instr) : 0;
6810       cluster_size = util_next_power_of_two(MIN2(cluster_size ? cluster_size : ctx->program->wave_size, ctx->program->wave_size));
6811
6812       if (!ctx->divergent_vals[instr->src[0].ssa->index] && (op == nir_op_ior || op == nir_op_iand)) {
6813          emit_uniform_subgroup(ctx, instr, src);
6814       } else if (instr->dest.ssa.bit_size == 1) {
6815          if (op == nir_op_imul || op == nir_op_umin || op == nir_op_imin)
6816             op = nir_op_iand;
6817          else if (op == nir_op_iadd)
6818             op = nir_op_ixor;
6819          else if (op == nir_op_umax || op == nir_op_imax)
6820             op = nir_op_ior;
6821          assert(op == nir_op_iand || op == nir_op_ior || op == nir_op_ixor);
6822
6823          switch (instr->intrinsic) {
6824          case nir_intrinsic_reduce:
6825             emit_wqm(ctx, emit_boolean_reduce(ctx, op, cluster_size, src), dst);
6826             break;
6827          case nir_intrinsic_exclusive_scan:
6828             emit_wqm(ctx, emit_boolean_exclusive_scan(ctx, op, src), dst);
6829             break;
6830          case nir_intrinsic_inclusive_scan:
6831             emit_wqm(ctx, emit_boolean_inclusive_scan(ctx, op, src), dst);
6832             break;
6833          default:
6834             assert(false);
6835          }
6836       } else if (cluster_size == 1) {
6837          bld.copy(Definition(dst), src);
6838       } else {
6839          src = as_vgpr(ctx, src);
6840
6841          ReduceOp reduce_op;
6842          switch (op) {
6843          #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
6844             CASE(iadd)
6845             CASE(imul)
6846             CASE(fadd)
6847             CASE(fmul)
6848             CASE(imin)
6849             CASE(umin)
6850             CASE(fmin)
6851             CASE(imax)
6852             CASE(umax)
6853             CASE(fmax)
6854             CASE(iand)
6855             CASE(ior)
6856             CASE(ixor)
6857             default:
6858                unreachable("unknown reduction op");
6859          #undef CASE
6860          }
6861
6862          aco_opcode aco_op;
6863          switch (instr->intrinsic) {
6864             case nir_intrinsic_reduce: aco_op = aco_opcode::p_reduce; break;
6865             case nir_intrinsic_inclusive_scan: aco_op = aco_opcode::p_inclusive_scan; break;
6866             case nir_intrinsic_exclusive_scan: aco_op = aco_opcode::p_exclusive_scan; break;
6867             default:
6868                unreachable("unknown reduce intrinsic");
6869          }
6870
6871          aco_ptr<Pseudo_reduction_instruction> reduce{create_instruction<Pseudo_reduction_instruction>(aco_op, Format::PSEUDO_REDUCTION, 3, 5)};
6872          reduce->operands[0] = Operand(src);
6873          // filled in by aco_reduce_assign.cpp, used internally as part of the
6874          // reduce sequence
6875          assert(dst.size() == 1 || dst.size() == 2);
6876          reduce->operands[1] = Operand(RegClass(RegType::vgpr, dst.size()).as_linear());
6877          reduce->operands[2] = Operand(v1.as_linear());
6878
6879          Temp tmp_dst = bld.tmp(dst.regClass());
6880          reduce->definitions[0] = Definition(tmp_dst);
6881          reduce->definitions[1] = bld.def(ctx->program->lane_mask); // used internally
6882          reduce->definitions[2] = Definition();
6883          reduce->definitions[3] = Definition(scc, s1);
6884          reduce->definitions[4] = Definition();
6885          reduce->reduce_op = reduce_op;
6886          reduce->cluster_size = cluster_size;
6887          ctx->block->instructions.emplace_back(std::move(reduce));
6888
6889          emit_wqm(ctx, tmp_dst, dst);
6890       }
6891       break;
6892    }
6893    case nir_intrinsic_quad_broadcast: {
6894       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6895       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
6896          emit_uniform_subgroup(ctx, instr, src);
6897       } else {
6898          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6899          unsigned lane = nir_src_as_const_value(instr->src[1])->u32;
6900          uint32_t dpp_ctrl = dpp_quad_perm(lane, lane, lane, lane);
6901
6902          if (instr->dest.ssa.bit_size == 1) {
6903             assert(src.regClass() == bld.lm);
6904             assert(dst.regClass() == bld.lm);
6905             uint32_t half_mask = 0x11111111u << lane;
6906             Temp mask_tmp = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(half_mask), Operand(half_mask));
6907             Temp tmp = bld.tmp(bld.lm);
6908             bld.sop1(Builder::s_wqm, Definition(tmp),
6909                      bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), mask_tmp,
6910                               bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm))));
6911             emit_wqm(ctx, tmp, dst);
6912          } else if (instr->dest.ssa.bit_size == 32) {
6913             if (ctx->program->chip_class >= GFX8)
6914                emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl), dst);
6915             else
6916                emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl), dst);
6917          } else if (instr->dest.ssa.bit_size == 64) {
6918             Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6919             bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6920             if (ctx->program->chip_class >= GFX8) {
6921                lo = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), lo, dpp_ctrl));
6922                hi = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), hi, dpp_ctrl));
6923             } else {
6924                lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, (1 << 15) | dpp_ctrl));
6925                hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, (1 << 15) | dpp_ctrl));
6926             }
6927             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6928             emit_split_vector(ctx, dst, 2);
6929          } else {
6930             fprintf(stderr, "Unimplemented NIR instr bit size: ");
6931             nir_print_instr(&instr->instr, stderr);
6932             fprintf(stderr, "\n");
6933          }
6934       }
6935       break;
6936    }
6937    case nir_intrinsic_quad_swap_horizontal:
6938    case nir_intrinsic_quad_swap_vertical:
6939    case nir_intrinsic_quad_swap_diagonal:
6940    case nir_intrinsic_quad_swizzle_amd: {
6941       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6942       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
6943          emit_uniform_subgroup(ctx, instr, src);
6944          break;
6945       }
6946       uint16_t dpp_ctrl = 0;
6947       switch (instr->intrinsic) {
6948       case nir_intrinsic_quad_swap_horizontal:
6949          dpp_ctrl = dpp_quad_perm(1, 0, 3, 2);
6950          break;
6951       case nir_intrinsic_quad_swap_vertical:
6952          dpp_ctrl = dpp_quad_perm(2, 3, 0, 1);
6953          break;
6954       case nir_intrinsic_quad_swap_diagonal:
6955          dpp_ctrl = dpp_quad_perm(3, 2, 1, 0);
6956          break;
6957       case nir_intrinsic_quad_swizzle_amd:
6958          dpp_ctrl = nir_intrinsic_swizzle_mask(instr);
6959          break;
6960       default:
6961          break;
6962       }
6963       if (ctx->program->chip_class < GFX8)
6964          dpp_ctrl |= (1 << 15);
6965
6966       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6967       if (instr->dest.ssa.bit_size == 1) {
6968          assert(src.regClass() == bld.lm);
6969          src = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand((uint32_t)-1), src);
6970          if (ctx->program->chip_class >= GFX8)
6971             src = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl);
6972          else
6973             src = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, dpp_ctrl);
6974          Temp tmp = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), src);
6975          emit_wqm(ctx, tmp, dst);
6976       } else if (instr->dest.ssa.bit_size == 32) {
6977          Temp tmp;
6978          if (ctx->program->chip_class >= GFX8)
6979             tmp = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl);
6980          else
6981             tmp = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, dpp_ctrl);
6982          emit_wqm(ctx, tmp, dst);
6983       } else if (instr->dest.ssa.bit_size == 64) {
6984          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6985          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6986          if (ctx->program->chip_class >= GFX8) {
6987             lo = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), lo, dpp_ctrl));
6988             hi = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), hi, dpp_ctrl));
6989          } else {
6990             lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, dpp_ctrl));
6991             hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, dpp_ctrl));
6992          }
6993          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6994          emit_split_vector(ctx, dst, 2);
6995       } else {
6996          fprintf(stderr, "Unimplemented NIR instr bit size: ");
6997          nir_print_instr(&instr->instr, stderr);
6998          fprintf(stderr, "\n");
6999       }
7000       break;
7001    }
7002    case nir_intrinsic_masked_swizzle_amd: {
7003       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7004       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
7005          emit_uniform_subgroup(ctx, instr, src);
7006          break;
7007       }
7008       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7009       uint32_t mask = nir_intrinsic_swizzle_mask(instr);
7010       if (dst.regClass() == v1) {
7011          emit_wqm(ctx,
7012                   bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, mask, 0, false),
7013                   dst);
7014       } else if (dst.regClass() == v2) {
7015          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
7016          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
7017          lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, mask, 0, false));
7018          hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, mask, 0, false));
7019          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
7020          emit_split_vector(ctx, dst, 2);
7021       } else {
7022          fprintf(stderr, "Unimplemented NIR instr bit size: ");
7023          nir_print_instr(&instr->instr, stderr);
7024          fprintf(stderr, "\n");
7025       }
7026       break;
7027    }
7028    case nir_intrinsic_write_invocation_amd: {
7029       Temp src = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
7030       Temp val = bld.as_uniform(get_ssa_temp(ctx, instr->src[1].ssa));
7031       Temp lane = bld.as_uniform(get_ssa_temp(ctx, instr->src[2].ssa));
7032       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7033       if (dst.regClass() == v1) {
7034          /* src2 is ignored for writelane. RA assigns the same reg for dst */
7035          emit_wqm(ctx, bld.writelane(bld.def(v1), val, lane, src), dst);
7036       } else if (dst.regClass() == v2) {
7037          Temp src_lo = bld.tmp(v1), src_hi = bld.tmp(v1);
7038          Temp val_lo = bld.tmp(s1), val_hi = bld.tmp(s1);
7039          bld.pseudo(aco_opcode::p_split_vector, Definition(src_lo), Definition(src_hi), src);
7040          bld.pseudo(aco_opcode::p_split_vector, Definition(val_lo), Definition(val_hi), val);
7041          Temp lo = emit_wqm(ctx, bld.writelane(bld.def(v1), val_lo, lane, src_hi));
7042          Temp hi = emit_wqm(ctx, bld.writelane(bld.def(v1), val_hi, lane, src_hi));
7043          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
7044          emit_split_vector(ctx, dst, 2);
7045       } else {
7046          fprintf(stderr, "Unimplemented NIR instr bit size: ");
7047          nir_print_instr(&instr->instr, stderr);
7048          fprintf(stderr, "\n");
7049       }
7050       break;
7051    }
7052    case nir_intrinsic_mbcnt_amd: {
7053       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7054       RegClass rc = RegClass(src.type(), 1);
7055       Temp mask_lo = bld.tmp(rc), mask_hi = bld.tmp(rc);
7056       bld.pseudo(aco_opcode::p_split_vector, Definition(mask_lo), Definition(mask_hi), src);
7057       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7058       Temp wqm_tmp = emit_mbcnt(ctx, bld.def(v1), Operand(mask_lo), Operand(mask_hi));
7059       emit_wqm(ctx, wqm_tmp, dst);
7060       break;
7061    }
7062    case nir_intrinsic_load_helper_invocation: {
7063       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7064       bld.pseudo(aco_opcode::p_load_helper, Definition(dst));
7065       ctx->block->kind |= block_kind_needs_lowering;
7066       ctx->program->needs_exact = true;
7067       break;
7068    }
7069    case nir_intrinsic_is_helper_invocation: {
7070       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7071       bld.pseudo(aco_opcode::p_is_helper, Definition(dst));
7072       ctx->block->kind |= block_kind_needs_lowering;
7073       ctx->program->needs_exact = true;
7074       break;
7075    }
7076    case nir_intrinsic_demote:
7077       bld.pseudo(aco_opcode::p_demote_to_helper, Operand(-1u));
7078
7079       if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
7080          ctx->cf_info.exec_potentially_empty_discard = true;
7081       ctx->block->kind |= block_kind_uses_demote;
7082       ctx->program->needs_exact = true;
7083       break;
7084    case nir_intrinsic_demote_if: {
7085       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7086       assert(src.regClass() == bld.lm);
7087       Temp cond = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
7088       bld.pseudo(aco_opcode::p_demote_to_helper, cond);
7089
7090       if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
7091          ctx->cf_info.exec_potentially_empty_discard = true;
7092       ctx->block->kind |= block_kind_uses_demote;
7093       ctx->program->needs_exact = true;
7094       break;
7095    }
7096    case nir_intrinsic_first_invocation: {
7097       emit_wqm(ctx, bld.sop1(Builder::s_ff1_i32, bld.def(s1), Operand(exec, bld.lm)),
7098                get_ssa_temp(ctx, &instr->dest.ssa));
7099       break;
7100    }
7101    case nir_intrinsic_shader_clock:
7102       bld.smem(aco_opcode::s_memtime, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), false);
7103       emit_split_vector(ctx, get_ssa_temp(ctx, &instr->dest.ssa), 2);
7104       break;
7105    case nir_intrinsic_load_vertex_id_zero_base: {
7106       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7107       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.vertex_id));
7108       break;
7109    }
7110    case nir_intrinsic_load_first_vertex: {
7111       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7112       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.base_vertex));
7113       break;
7114    }
7115    case nir_intrinsic_load_base_instance: {
7116       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7117       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.start_instance));
7118       break;
7119    }
7120    case nir_intrinsic_load_instance_id: {
7121       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7122       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.instance_id));
7123       break;
7124    }
7125    case nir_intrinsic_load_draw_id: {
7126       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7127       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.draw_id));
7128       break;
7129    }
7130    case nir_intrinsic_load_invocation_id: {
7131       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7132
7133       if (ctx->shader->info.stage == MESA_SHADER_GEOMETRY) {
7134          if (ctx->options->chip_class >= GFX10)
7135             bld.vop2_e64(aco_opcode::v_and_b32, Definition(dst), Operand(127u), get_arg(ctx, ctx->args->ac.gs_invocation_id));
7136          else
7137             bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.gs_invocation_id));
7138       } else if (ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) {
7139          bld.vop3(aco_opcode::v_bfe_u32, Definition(dst),
7140                   get_arg(ctx, ctx->args->ac.tcs_rel_ids), Operand(8u), Operand(5u));
7141       } else {
7142          unreachable("Unsupported stage for load_invocation_id");
7143       }
7144
7145       break;
7146    }
7147    case nir_intrinsic_load_primitive_id: {
7148       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7149
7150       switch (ctx->shader->info.stage) {
7151       case MESA_SHADER_GEOMETRY:
7152          bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.gs_prim_id));
7153          break;
7154       case MESA_SHADER_TESS_CTRL:
7155          bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.tcs_patch_id));
7156          break;
7157       case MESA_SHADER_TESS_EVAL:
7158          bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.tes_patch_id));
7159          break;
7160       default:
7161          unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
7162       }
7163
7164       break;
7165    }
7166    case nir_intrinsic_load_patch_vertices_in: {
7167       assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL ||
7168              ctx->shader->info.stage == MESA_SHADER_TESS_EVAL);
7169
7170       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7171       bld.copy(Definition(dst), Operand(ctx->args->options->key.tcs.input_vertices));
7172       break;
7173    }
7174    case nir_intrinsic_emit_vertex_with_counter: {
7175       visit_emit_vertex_with_counter(ctx, instr);
7176       break;
7177    }
7178    case nir_intrinsic_end_primitive_with_counter: {
7179       unsigned stream = nir_intrinsic_stream_id(instr);
7180       bld.sopp(aco_opcode::s_sendmsg, bld.m0(ctx->gs_wave_id), -1, sendmsg_gs(true, false, stream));
7181       break;
7182    }
7183    case nir_intrinsic_set_vertex_count: {
7184       /* unused, the HW keeps track of this for us */
7185       break;
7186    }
7187    default:
7188       fprintf(stderr, "Unimplemented intrinsic instr: ");
7189       nir_print_instr(&instr->instr, stderr);
7190       fprintf(stderr, "\n");
7191       abort();
7192
7193       break;
7194    }
7195 }
7196
7197
7198 void tex_fetch_ptrs(isel_context *ctx, nir_tex_instr *instr,
7199                     Temp *res_ptr, Temp *samp_ptr, Temp *fmask_ptr,
7200                     enum glsl_base_type *stype)
7201 {
7202    nir_deref_instr *texture_deref_instr = NULL;
7203    nir_deref_instr *sampler_deref_instr = NULL;
7204    int plane = -1;
7205
7206    for (unsigned i = 0; i < instr->num_srcs; i++) {
7207       switch (instr->src[i].src_type) {
7208       case nir_tex_src_texture_deref:
7209          texture_deref_instr = nir_src_as_deref(instr->src[i].src);
7210          break;
7211       case nir_tex_src_sampler_deref:
7212          sampler_deref_instr = nir_src_as_deref(instr->src[i].src);
7213          break;
7214       case nir_tex_src_plane:
7215          plane = nir_src_as_int(instr->src[i].src);
7216          break;
7217       default:
7218          break;
7219       }
7220    }
7221
7222    *stype = glsl_get_sampler_result_type(texture_deref_instr->type);
7223
7224    if (!sampler_deref_instr)
7225       sampler_deref_instr = texture_deref_instr;
7226
7227    if (plane >= 0) {
7228       assert(instr->op != nir_texop_txf_ms &&
7229              instr->op != nir_texop_samples_identical);
7230       assert(instr->sampler_dim  != GLSL_SAMPLER_DIM_BUF);
7231       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, (aco_descriptor_type)(ACO_DESC_PLANE_0 + plane), instr, false, false);
7232    } else if (instr->sampler_dim  == GLSL_SAMPLER_DIM_BUF) {
7233       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_BUFFER, instr, false, false);
7234    } else if (instr->op == nir_texop_fragment_mask_fetch) {
7235       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_FMASK, instr, false, false);
7236    } else {
7237       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_IMAGE, instr, false, false);
7238    }
7239    if (samp_ptr) {
7240       *samp_ptr = get_sampler_desc(ctx, sampler_deref_instr, ACO_DESC_SAMPLER, instr, false, false);
7241
7242       if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT && ctx->options->chip_class < GFX8) {
7243          /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
7244          Builder bld(ctx->program, ctx->block);
7245
7246          /* to avoid unnecessary moves, we split and recombine sampler and image */
7247          Temp img[8] = {bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1),
7248                         bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1)};
7249          Temp samp[4] = {bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1)};
7250          bld.pseudo(aco_opcode::p_split_vector, Definition(img[0]), Definition(img[1]),
7251                     Definition(img[2]), Definition(img[3]), Definition(img[4]),
7252                     Definition(img[5]), Definition(img[6]), Definition(img[7]), *res_ptr);
7253          bld.pseudo(aco_opcode::p_split_vector, Definition(samp[0]), Definition(samp[1]),
7254                     Definition(samp[2]), Definition(samp[3]), *samp_ptr);
7255
7256          samp[0] = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), samp[0], img[7]);
7257          *res_ptr = bld.pseudo(aco_opcode::p_create_vector, bld.def(s8),
7258                                img[0], img[1], img[2], img[3],
7259                                img[4], img[5], img[6], img[7]);
7260          *samp_ptr = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
7261                                 samp[0], samp[1], samp[2], samp[3]);
7262       }
7263    }
7264    if (fmask_ptr && (instr->op == nir_texop_txf_ms ||
7265                      instr->op == nir_texop_samples_identical))
7266       *fmask_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_FMASK, instr, false, false);
7267 }
7268
7269 void build_cube_select(isel_context *ctx, Temp ma, Temp id, Temp deriv,
7270                        Temp *out_ma, Temp *out_sc, Temp *out_tc)
7271 {
7272    Builder bld(ctx->program, ctx->block);
7273
7274    Temp deriv_x = emit_extract_vector(ctx, deriv, 0, v1);
7275    Temp deriv_y = emit_extract_vector(ctx, deriv, 1, v1);
7276    Temp deriv_z = emit_extract_vector(ctx, deriv, 2, v1);
7277
7278    Operand neg_one(0xbf800000u);
7279    Operand one(0x3f800000u);
7280    Operand two(0x40000000u);
7281    Operand four(0x40800000u);
7282
7283    Temp is_ma_positive = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), ma);
7284    Temp sgn_ma = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), neg_one, one, is_ma_positive);
7285    Temp neg_sgn_ma = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), Operand(0u), sgn_ma);
7286
7287    Temp is_ma_z = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), four, id);
7288    Temp is_ma_y = bld.vopc(aco_opcode::v_cmp_le_f32, bld.def(bld.lm), two, id);
7289    is_ma_y = bld.sop2(Builder::s_andn2, bld.hint_vcc(bld.def(bld.lm)), is_ma_y, is_ma_z);
7290    Temp is_not_ma_x = bld.sop2(aco_opcode::s_or_b64, bld.hint_vcc(bld.def(bld.lm)), bld.def(s1, scc), is_ma_z, is_ma_y);
7291
7292    // select sc
7293    Temp tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_z, deriv_x, is_not_ma_x);
7294    Temp sgn = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1),
7295                        bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), neg_sgn_ma, sgn_ma, is_ma_z),
7296                        one, is_ma_y);
7297    *out_sc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tmp, sgn);
7298
7299    // select tc
7300    tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_y, deriv_z, is_ma_y);
7301    sgn = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), neg_one, sgn_ma, is_ma_y);
7302    *out_tc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tmp, sgn);
7303
7304    // select ma
7305    tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
7306                   bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_x, deriv_y, is_ma_y),
7307                   deriv_z, is_ma_z);
7308    tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffffu), tmp);
7309    *out_ma = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), two, tmp);
7310 }
7311
7312 void prepare_cube_coords(isel_context *ctx, std::vector<Temp>& coords, Temp* ddx, Temp* ddy, bool is_deriv, bool is_array)
7313 {
7314    Builder bld(ctx->program, ctx->block);
7315    Temp ma, tc, sc, id;
7316
7317    if (is_array) {
7318       coords[3] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coords[3]);
7319
7320       // see comment in ac_prepare_cube_coords()
7321       if (ctx->options->chip_class <= GFX8)
7322          coords[3] = bld.vop2(aco_opcode::v_max_f32, bld.def(v1), Operand(0u), coords[3]);
7323    }
7324
7325    ma = bld.vop3(aco_opcode::v_cubema_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7326
7327    aco_ptr<VOP3A_instruction> vop3a{create_instruction<VOP3A_instruction>(aco_opcode::v_rcp_f32, asVOP3(Format::VOP1), 1, 1)};
7328    vop3a->operands[0] = Operand(ma);
7329    vop3a->abs[0] = true;
7330    Temp invma = bld.tmp(v1);
7331    vop3a->definitions[0] = Definition(invma);
7332    ctx->block->instructions.emplace_back(std::move(vop3a));
7333
7334    sc = bld.vop3(aco_opcode::v_cubesc_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7335    if (!is_deriv)
7336       sc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), sc, invma, Operand(0x3fc00000u/*1.5*/));
7337
7338    tc = bld.vop3(aco_opcode::v_cubetc_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7339    if (!is_deriv)
7340       tc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), tc, invma, Operand(0x3fc00000u/*1.5*/));
7341
7342    id = bld.vop3(aco_opcode::v_cubeid_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7343
7344    if (is_deriv) {
7345       sc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), sc, invma);
7346       tc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tc, invma);
7347
7348       for (unsigned i = 0; i < 2; i++) {
7349          // see comment in ac_prepare_cube_coords()
7350          Temp deriv_ma;
7351          Temp deriv_sc, deriv_tc;
7352          build_cube_select(ctx, ma, id, i ? *ddy : *ddx,
7353                            &deriv_ma, &deriv_sc, &deriv_tc);
7354
7355          deriv_ma = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, invma);
7356
7357          Temp x = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1),
7358                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_sc, invma),
7359                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, sc));
7360          Temp y = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1),
7361                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_tc, invma),
7362                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, tc));
7363          *(i ? ddy : ddx) = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), x, y);
7364       }
7365
7366       sc = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), Operand(0x3fc00000u/*1.5*/), sc);
7367       tc = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), Operand(0x3fc00000u/*1.5*/), tc);
7368    }
7369
7370    if (is_array)
7371       id = bld.vop2(aco_opcode::v_madmk_f32, bld.def(v1), coords[3], id, Operand(0x41000000u/*8.0*/));
7372    coords.resize(3);
7373    coords[0] = sc;
7374    coords[1] = tc;
7375    coords[2] = id;
7376 }
7377
7378 void get_const_vec(nir_ssa_def *vec, nir_const_value *cv[4])
7379 {
7380    if (vec->parent_instr->type != nir_instr_type_alu)
7381       return;
7382    nir_alu_instr *vec_instr = nir_instr_as_alu(vec->parent_instr);
7383    if (vec_instr->op != nir_op_vec(vec->num_components))
7384       return;
7385
7386    for (unsigned i = 0; i < vec->num_components; i++) {
7387       cv[i] = vec_instr->src[i].swizzle[0] == 0 ?
7388               nir_src_as_const_value(vec_instr->src[i].src) : NULL;
7389    }
7390 }
7391
7392 void visit_tex(isel_context *ctx, nir_tex_instr *instr)
7393 {
7394    Builder bld(ctx->program, ctx->block);
7395    bool has_bias = false, has_lod = false, level_zero = false, has_compare = false,
7396         has_offset = false, has_ddx = false, has_ddy = false, has_derivs = false, has_sample_index = false;
7397    Temp resource, sampler, fmask_ptr, bias = Temp(), compare = Temp(), sample_index = Temp(),
7398         lod = Temp(), offset = Temp(), ddx = Temp(), ddy = Temp();
7399    std::vector<Temp> coords;
7400    std::vector<Temp> derivs;
7401    nir_const_value *sample_index_cv = NULL;
7402    nir_const_value *const_offset[4] = {NULL, NULL, NULL, NULL};
7403    enum glsl_base_type stype;
7404    tex_fetch_ptrs(ctx, instr, &resource, &sampler, &fmask_ptr, &stype);
7405
7406    bool tg4_integer_workarounds = ctx->options->chip_class <= GFX8 && instr->op == nir_texop_tg4 &&
7407                                   (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT);
7408    bool tg4_integer_cube_workaround = tg4_integer_workarounds &&
7409                                       instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
7410
7411    for (unsigned i = 0; i < instr->num_srcs; i++) {
7412       switch (instr->src[i].src_type) {
7413       case nir_tex_src_coord: {
7414          Temp coord = get_ssa_temp(ctx, instr->src[i].src.ssa);
7415          for (unsigned i = 0; i < coord.size(); i++)
7416             coords.emplace_back(emit_extract_vector(ctx, coord, i, v1));
7417          break;
7418       }
7419       case nir_tex_src_bias:
7420          if (instr->op == nir_texop_txb) {
7421             bias = get_ssa_temp(ctx, instr->src[i].src.ssa);
7422             has_bias = true;
7423          }
7424          break;
7425       case nir_tex_src_lod: {
7426          nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
7427
7428          if (val && val->f32 <= 0.0) {
7429             level_zero = true;
7430          } else {
7431             lod = get_ssa_temp(ctx, instr->src[i].src.ssa);
7432             has_lod = true;
7433          }
7434          break;
7435       }
7436       case nir_tex_src_comparator:
7437          if (instr->is_shadow) {
7438             compare = get_ssa_temp(ctx, instr->src[i].src.ssa);
7439             has_compare = true;
7440          }
7441          break;
7442       case nir_tex_src_offset:
7443          offset = get_ssa_temp(ctx, instr->src[i].src.ssa);
7444          get_const_vec(instr->src[i].src.ssa, const_offset);
7445          has_offset = true;
7446          break;
7447       case nir_tex_src_ddx:
7448          ddx = get_ssa_temp(ctx, instr->src[i].src.ssa);
7449          has_ddx = true;
7450          break;
7451       case nir_tex_src_ddy:
7452          ddy = get_ssa_temp(ctx, instr->src[i].src.ssa);
7453          has_ddy = true;
7454          break;
7455       case nir_tex_src_ms_index:
7456          sample_index = get_ssa_temp(ctx, instr->src[i].src.ssa);
7457          sample_index_cv = nir_src_as_const_value(instr->src[i].src);
7458          has_sample_index = true;
7459          break;
7460       case nir_tex_src_texture_offset:
7461       case nir_tex_src_sampler_offset:
7462       default:
7463          break;
7464       }
7465    }
7466
7467    if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
7468       return get_buffer_size(ctx, resource, get_ssa_temp(ctx, &instr->dest.ssa), true);
7469
7470    if (instr->op == nir_texop_texture_samples) {
7471       Temp dword3 = emit_extract_vector(ctx, resource, 3, s1);
7472
7473       Temp samples_log2 = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), dword3, Operand(16u | 4u<<16));
7474       Temp samples = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), Operand(1u), samples_log2);
7475       Temp type = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), dword3, Operand(28u | 4u<<16 /* offset=28, width=4 */));
7476       Temp is_msaa = bld.sopc(aco_opcode::s_cmp_ge_u32, bld.def(s1, scc), type, Operand(14u));
7477
7478       bld.sop2(aco_opcode::s_cselect_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
7479                samples, Operand(1u), bld.scc(is_msaa));
7480       return;
7481    }
7482
7483    if (has_offset && instr->op != nir_texop_txf && instr->op != nir_texop_txf_ms) {
7484       aco_ptr<Instruction> tmp_instr;
7485       Temp acc, pack = Temp();
7486
7487       uint32_t pack_const = 0;
7488       for (unsigned i = 0; i < offset.size(); i++) {
7489          if (!const_offset[i])
7490             continue;
7491          pack_const |= (const_offset[i]->u32 & 0x3Fu) << (8u * i);
7492       }
7493
7494       if (offset.type() == RegType::sgpr) {
7495          for (unsigned i = 0; i < offset.size(); i++) {
7496             if (const_offset[i])
7497                continue;
7498
7499             acc = emit_extract_vector(ctx, offset, i, s1);
7500             acc = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), acc, Operand(0x3Fu));
7501
7502             if (i) {
7503                acc = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), acc, Operand(8u * i));
7504             }
7505
7506             if (pack == Temp()) {
7507                pack = acc;
7508             } else {
7509                pack = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), pack, acc);
7510             }
7511          }
7512
7513          if (pack_const && pack != Temp())
7514             pack = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(pack_const), pack);
7515       } else {
7516          for (unsigned i = 0; i < offset.size(); i++) {
7517             if (const_offset[i])
7518                continue;
7519
7520             acc = emit_extract_vector(ctx, offset, i, v1);
7521             acc = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x3Fu), acc);
7522
7523             if (i) {
7524                acc = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(8u * i), acc);
7525             }
7526
7527             if (pack == Temp()) {
7528                pack = acc;
7529             } else {
7530                pack = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), pack, acc);
7531             }
7532          }
7533
7534          if (pack_const && pack != Temp())
7535             pack = bld.sop2(aco_opcode::v_or_b32, bld.def(v1), Operand(pack_const), pack);
7536       }
7537       if (pack_const && pack == Temp())
7538          offset = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(pack_const));
7539       else if (pack == Temp())
7540          has_offset = false;
7541       else
7542          offset = pack;
7543    }
7544
7545    if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && instr->coord_components)
7546       prepare_cube_coords(ctx, coords, &ddx, &ddy, instr->op == nir_texop_txd, instr->is_array && instr->op != nir_texop_lod);
7547
7548    /* pack derivatives */
7549    if (has_ddx || has_ddy) {
7550       if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && ctx->options->chip_class == GFX9) {
7551          assert(has_ddx && has_ddy && ddx.size() == 1 && ddy.size() == 1);
7552          Temp zero = bld.copy(bld.def(v1), Operand(0u));
7553          derivs = {ddy, zero, ddy, zero};
7554       } else {
7555          for (unsigned i = 0; has_ddx && i < ddx.size(); i++)
7556             derivs.emplace_back(emit_extract_vector(ctx, ddx, i, v1));
7557          for (unsigned i = 0; has_ddy && i < ddy.size(); i++)
7558             derivs.emplace_back(emit_extract_vector(ctx, ddy, i, v1));
7559       }
7560       has_derivs = true;
7561    }
7562
7563    if (instr->coord_components > 1 &&
7564        instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
7565        instr->is_array &&
7566        instr->op != nir_texop_txf)
7567       coords[1] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coords[1]);
7568
7569    if (instr->coord_components > 2 &&
7570       (instr->sampler_dim == GLSL_SAMPLER_DIM_2D ||
7571        instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
7572        instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS ||
7573        instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
7574        instr->is_array &&
7575        instr->op != nir_texop_txf &&
7576        instr->op != nir_texop_txf_ms &&
7577        instr->op != nir_texop_fragment_fetch &&
7578        instr->op != nir_texop_fragment_mask_fetch)
7579       coords[2] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coords[2]);
7580
7581    if (ctx->options->chip_class == GFX9 &&
7582        instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
7583        instr->op != nir_texop_lod && instr->coord_components) {
7584       assert(coords.size() > 0 && coords.size() < 3);
7585
7586       coords.insert(std::next(coords.begin()), bld.copy(bld.def(v1), instr->op == nir_texop_txf ?
7587                                                                      Operand((uint32_t) 0) :
7588                                                                      Operand((uint32_t) 0x3f000000)));
7589    }
7590
7591    bool da = should_declare_array(ctx, instr->sampler_dim, instr->is_array);
7592
7593    if (instr->op == nir_texop_samples_identical)
7594       resource = fmask_ptr;
7595
7596    else if ((instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
7597              instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
7598             instr->op != nir_texop_txs &&
7599             instr->op != nir_texop_fragment_fetch &&
7600             instr->op != nir_texop_fragment_mask_fetch) {
7601       assert(has_sample_index);
7602       Operand op(sample_index);
7603       if (sample_index_cv)
7604          op = Operand(sample_index_cv->u32);
7605       sample_index = adjust_sample_index_using_fmask(ctx, da, coords, op, fmask_ptr);
7606    }
7607
7608    if (has_offset && (instr->op == nir_texop_txf || instr->op == nir_texop_txf_ms)) {
7609       for (unsigned i = 0; i < std::min(offset.size(), instr->coord_components); i++) {
7610          Temp off = emit_extract_vector(ctx, offset, i, v1);
7611          coords[i] = bld.vadd32(bld.def(v1), coords[i], off);
7612       }
7613       has_offset = false;
7614    }
7615
7616    /* Build tex instruction */
7617    unsigned dmask = nir_ssa_def_components_read(&instr->dest.ssa);
7618    unsigned dim = ctx->options->chip_class >= GFX10 && instr->sampler_dim != GLSL_SAMPLER_DIM_BUF
7619                   ? ac_get_sampler_dim(ctx->options->chip_class, instr->sampler_dim, instr->is_array)
7620                   : 0;
7621    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7622    Temp tmp_dst = dst;
7623
7624    /* gather4 selects the component by dmask and always returns vec4 */
7625    if (instr->op == nir_texop_tg4) {
7626       assert(instr->dest.ssa.num_components == 4);
7627       if (instr->is_shadow)
7628          dmask = 1;
7629       else
7630          dmask = 1 << instr->component;
7631       if (tg4_integer_cube_workaround || dst.type() == RegType::sgpr)
7632          tmp_dst = bld.tmp(v4);
7633    } else if (instr->op == nir_texop_samples_identical) {
7634       tmp_dst = bld.tmp(v1);
7635    } else if (util_bitcount(dmask) != instr->dest.ssa.num_components || dst.type() == RegType::sgpr) {
7636       tmp_dst = bld.tmp(RegClass(RegType::vgpr, util_bitcount(dmask)));
7637    }
7638
7639    aco_ptr<MIMG_instruction> tex;
7640    if (instr->op == nir_texop_txs || instr->op == nir_texop_query_levels) {
7641       if (!has_lod)
7642          lod = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
7643
7644       bool div_by_6 = instr->op == nir_texop_txs &&
7645                       instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
7646                       instr->is_array &&
7647                       (dmask & (1 << 2));
7648       if (tmp_dst.id() == dst.id() && div_by_6)
7649          tmp_dst = bld.tmp(tmp_dst.regClass());
7650
7651       tex.reset(create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 3, 1));
7652       tex->operands[0] = Operand(resource);
7653       tex->operands[1] = Operand(s4); /* no sampler */
7654       tex->operands[2] = Operand(as_vgpr(ctx,lod));
7655       if (ctx->options->chip_class == GFX9 &&
7656           instr->op == nir_texop_txs &&
7657           instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
7658           instr->is_array) {
7659          tex->dmask = (dmask & 0x1) | ((dmask & 0x2) << 1);
7660       } else if (instr->op == nir_texop_query_levels) {
7661          tex->dmask = 1 << 3;
7662       } else {
7663          tex->dmask = dmask;
7664       }
7665       tex->da = da;
7666       tex->definitions[0] = Definition(tmp_dst);
7667       tex->dim = dim;
7668       tex->can_reorder = true;
7669       ctx->block->instructions.emplace_back(std::move(tex));
7670
7671       if (div_by_6) {
7672          /* divide 3rd value by 6 by multiplying with magic number */
7673          emit_split_vector(ctx, tmp_dst, tmp_dst.size());
7674          Temp c = bld.copy(bld.def(s1), Operand((uint32_t) 0x2AAAAAAB));
7675          Temp by_6 = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), emit_extract_vector(ctx, tmp_dst, 2, v1), c);
7676          assert(instr->dest.ssa.num_components == 3);
7677          Temp tmp = dst.type() == RegType::vgpr ? dst : bld.tmp(v3);
7678          tmp_dst = bld.pseudo(aco_opcode::p_create_vector, Definition(tmp),
7679                               emit_extract_vector(ctx, tmp_dst, 0, v1),
7680                               emit_extract_vector(ctx, tmp_dst, 1, v1),
7681                               by_6);
7682
7683       }
7684
7685       expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, dmask);
7686       return;
7687    }
7688
7689    Temp tg4_compare_cube_wa64 = Temp();
7690
7691    if (tg4_integer_workarounds) {
7692       tex.reset(create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 3, 1));
7693       tex->operands[0] = Operand(resource);
7694       tex->operands[1] = Operand(s4); /* no sampler */
7695       tex->operands[2] = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
7696       tex->dim = dim;
7697       tex->dmask = 0x3;
7698       tex->da = da;
7699       Temp size = bld.tmp(v2);
7700       tex->definitions[0] = Definition(size);
7701       tex->can_reorder = true;
7702       ctx->block->instructions.emplace_back(std::move(tex));
7703       emit_split_vector(ctx, size, size.size());
7704
7705       Temp half_texel[2];
7706       for (unsigned i = 0; i < 2; i++) {
7707          half_texel[i] = emit_extract_vector(ctx, size, i, v1);
7708          half_texel[i] = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), half_texel[i]);
7709          half_texel[i] = bld.vop1(aco_opcode::v_rcp_iflag_f32, bld.def(v1), half_texel[i]);
7710          half_texel[i] = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0xbf000000/*-0.5*/), half_texel[i]);
7711       }
7712
7713       Temp new_coords[2] = {
7714          bld.vop2(aco_opcode::v_add_f32, bld.def(v1), coords[0], half_texel[0]),
7715          bld.vop2(aco_opcode::v_add_f32, bld.def(v1), coords[1], half_texel[1])
7716       };
7717
7718       if (tg4_integer_cube_workaround) {
7719          // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
7720          Temp desc[resource.size()];
7721          aco_ptr<Instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector,
7722                                                                            Format::PSEUDO, 1, resource.size())};
7723          split->operands[0] = Operand(resource);
7724          for (unsigned i = 0; i < resource.size(); i++) {
7725             desc[i] = bld.tmp(s1);
7726             split->definitions[i] = Definition(desc[i]);
7727          }
7728          ctx->block->instructions.emplace_back(std::move(split));
7729
7730          Temp dfmt = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), desc[1], Operand(20u | (6u << 16)));
7731          Temp compare_cube_wa = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), dfmt,
7732                                          Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8));
7733
7734          Temp nfmt;
7735          if (stype == GLSL_TYPE_UINT) {
7736             nfmt = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1),
7737                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED),
7738                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT),
7739                             bld.scc(compare_cube_wa));
7740          } else {
7741             nfmt = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1),
7742                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED),
7743                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT),
7744                             bld.scc(compare_cube_wa));
7745          }
7746          tg4_compare_cube_wa64 = bld.tmp(bld.lm);
7747          bool_to_vector_condition(ctx, compare_cube_wa, tg4_compare_cube_wa64);
7748
7749          nfmt = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), nfmt, Operand(26u));
7750
7751          desc[1] = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), desc[1],
7752                             Operand((uint32_t)C_008F14_NUM_FORMAT));
7753          desc[1] = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), desc[1], nfmt);
7754
7755          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector,
7756                                                                          Format::PSEUDO, resource.size(), 1)};
7757          for (unsigned i = 0; i < resource.size(); i++)
7758             vec->operands[i] = Operand(desc[i]);
7759          resource = bld.tmp(resource.regClass());
7760          vec->definitions[0] = Definition(resource);
7761          ctx->block->instructions.emplace_back(std::move(vec));
7762
7763          new_coords[0] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
7764                                   new_coords[0], coords[0], tg4_compare_cube_wa64);
7765          new_coords[1] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
7766                                   new_coords[1], coords[1], tg4_compare_cube_wa64);
7767       }
7768       coords[0] = new_coords[0];
7769       coords[1] = new_coords[1];
7770    }
7771
7772    if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
7773       //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
7774
7775       assert(coords.size() == 1);
7776       unsigned last_bit = util_last_bit(nir_ssa_def_components_read(&instr->dest.ssa));
7777       aco_opcode op;
7778       switch (last_bit) {
7779       case 1:
7780          op = aco_opcode::buffer_load_format_x; break;
7781       case 2:
7782          op = aco_opcode::buffer_load_format_xy; break;
7783       case 3:
7784          op = aco_opcode::buffer_load_format_xyz; break;
7785       case 4:
7786          op = aco_opcode::buffer_load_format_xyzw; break;
7787       default:
7788          unreachable("Tex instruction loads more than 4 components.");
7789       }
7790
7791       /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
7792       if (last_bit == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
7793          tmp_dst = dst;
7794       else
7795          tmp_dst = bld.tmp(RegType::vgpr, last_bit);
7796
7797       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
7798       mubuf->operands[0] = Operand(resource);
7799       mubuf->operands[1] = Operand(coords[0]);
7800       mubuf->operands[2] = Operand((uint32_t) 0);
7801       mubuf->definitions[0] = Definition(tmp_dst);
7802       mubuf->idxen = true;
7803       mubuf->can_reorder = true;
7804       ctx->block->instructions.emplace_back(std::move(mubuf));
7805
7806       expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, (1 << last_bit) - 1);
7807       return;
7808    }
7809
7810    /* gather MIMG address components */
7811    std::vector<Temp> args;
7812    if (has_offset)
7813       args.emplace_back(offset);
7814    if (has_bias)
7815       args.emplace_back(bias);
7816    if (has_compare)
7817       args.emplace_back(compare);
7818    if (has_derivs)
7819       args.insert(args.end(), derivs.begin(), derivs.end());
7820
7821    args.insert(args.end(), coords.begin(), coords.end());
7822    if (has_sample_index)
7823       args.emplace_back(sample_index);
7824    if (has_lod)
7825       args.emplace_back(lod);
7826
7827    Temp arg = bld.tmp(RegClass(RegType::vgpr, args.size()));
7828    aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, args.size(), 1)};
7829    vec->definitions[0] = Definition(arg);
7830    for (unsigned i = 0; i < args.size(); i++)
7831       vec->operands[i] = Operand(args[i]);
7832    ctx->block->instructions.emplace_back(std::move(vec));
7833
7834
7835    if (instr->op == nir_texop_txf ||
7836        instr->op == nir_texop_txf_ms ||
7837        instr->op == nir_texop_samples_identical ||
7838        instr->op == nir_texop_fragment_fetch ||
7839        instr->op == nir_texop_fragment_mask_fetch) {
7840       aco_opcode op = level_zero || instr->sampler_dim == GLSL_SAMPLER_DIM_MS || instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS ? aco_opcode::image_load : aco_opcode::image_load_mip;
7841       tex.reset(create_instruction<MIMG_instruction>(op, Format::MIMG, 3, 1));
7842       tex->operands[0] = Operand(resource);
7843       tex->operands[1] = Operand(s4); /* no sampler */
7844       tex->operands[2] = Operand(arg);
7845       tex->dim = dim;
7846       tex->dmask = dmask;
7847       tex->unrm = true;
7848       tex->da = da;
7849       tex->definitions[0] = Definition(tmp_dst);
7850       tex->can_reorder = true;
7851       ctx->block->instructions.emplace_back(std::move(tex));
7852
7853       if (instr->op == nir_texop_samples_identical) {
7854          assert(dmask == 1 && dst.regClass() == v1);
7855          assert(dst.id() != tmp_dst.id());
7856
7857          Temp tmp = bld.tmp(bld.lm);
7858          bld.vopc(aco_opcode::v_cmp_eq_u32, Definition(tmp), Operand(0u), tmp_dst).def(0).setHint(vcc);
7859          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand((uint32_t)-1), tmp);
7860
7861       } else {
7862          expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, dmask);
7863       }
7864       return;
7865    }
7866
7867    // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
7868    aco_opcode opcode = aco_opcode::image_sample;
7869    if (has_offset) { /* image_sample_*_o */
7870       if (has_compare) {
7871          opcode = aco_opcode::image_sample_c_o;
7872          if (has_derivs)
7873             opcode = aco_opcode::image_sample_c_d_o;
7874          if (has_bias)
7875             opcode = aco_opcode::image_sample_c_b_o;
7876          if (level_zero)
7877             opcode = aco_opcode::image_sample_c_lz_o;
7878          if (has_lod)
7879             opcode = aco_opcode::image_sample_c_l_o;
7880       } else {
7881          opcode = aco_opcode::image_sample_o;
7882          if (has_derivs)
7883             opcode = aco_opcode::image_sample_d_o;
7884          if (has_bias)
7885             opcode = aco_opcode::image_sample_b_o;
7886          if (level_zero)
7887             opcode = aco_opcode::image_sample_lz_o;
7888          if (has_lod)
7889             opcode = aco_opcode::image_sample_l_o;
7890       }
7891    } else { /* no offset */
7892       if (has_compare) {
7893          opcode = aco_opcode::image_sample_c;
7894          if (has_derivs)
7895             opcode = aco_opcode::image_sample_c_d;
7896          if (has_bias)
7897             opcode = aco_opcode::image_sample_c_b;
7898          if (level_zero)
7899             opcode = aco_opcode::image_sample_c_lz;
7900          if (has_lod)
7901             opcode = aco_opcode::image_sample_c_l;
7902       } else {
7903          opcode = aco_opcode::image_sample;
7904          if (has_derivs)
7905             opcode = aco_opcode::image_sample_d;
7906          if (has_bias)
7907             opcode = aco_opcode::image_sample_b;
7908          if (level_zero)
7909             opcode = aco_opcode::image_sample_lz;
7910          if (has_lod)
7911             opcode = aco_opcode::image_sample_l;
7912       }
7913    }
7914
7915    if (instr->op == nir_texop_tg4) {
7916       if (has_offset) {
7917          opcode = aco_opcode::image_gather4_lz_o;
7918          if (has_compare)
7919             opcode = aco_opcode::image_gather4_c_lz_o;
7920       } else {
7921          opcode = aco_opcode::image_gather4_lz;
7922          if (has_compare)
7923             opcode = aco_opcode::image_gather4_c_lz;
7924       }
7925    } else if (instr->op == nir_texop_lod) {
7926       opcode = aco_opcode::image_get_lod;
7927    }
7928
7929    /* we don't need the bias, sample index, compare value or offset to be
7930     * computed in WQM but if the p_create_vector copies the coordinates, then it
7931     * needs to be in WQM */
7932    if (ctx->stage == fragment_fs &&
7933        !has_derivs && !has_lod && !level_zero &&
7934        instr->sampler_dim != GLSL_SAMPLER_DIM_MS &&
7935        instr->sampler_dim != GLSL_SAMPLER_DIM_SUBPASS_MS)
7936       arg = emit_wqm(ctx, arg, bld.tmp(arg.regClass()), true);
7937
7938    tex.reset(create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 1));
7939    tex->operands[0] = Operand(resource);
7940    tex->operands[1] = Operand(sampler);
7941    tex->operands[2] = Operand(arg);
7942    tex->dim = dim;
7943    tex->dmask = dmask;
7944    tex->da = da;
7945    tex->definitions[0] = Definition(tmp_dst);
7946    tex->can_reorder = true;
7947    ctx->block->instructions.emplace_back(std::move(tex));
7948
7949    if (tg4_integer_cube_workaround) {
7950       assert(tmp_dst.id() != dst.id());
7951       assert(tmp_dst.size() == dst.size() && dst.size() == 4);
7952
7953       emit_split_vector(ctx, tmp_dst, tmp_dst.size());
7954       Temp val[4];
7955       for (unsigned i = 0; i < dst.size(); i++) {
7956          val[i] = emit_extract_vector(ctx, tmp_dst, i, v1);
7957          Temp cvt_val;
7958          if (stype == GLSL_TYPE_UINT)
7959             cvt_val = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), val[i]);
7960          else
7961             cvt_val = bld.vop1(aco_opcode::v_cvt_i32_f32, bld.def(v1), val[i]);
7962          val[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), val[i], cvt_val, tg4_compare_cube_wa64);
7963       }
7964       Temp tmp = dst.regClass() == v4 ? dst : bld.tmp(v4);
7965       tmp_dst = bld.pseudo(aco_opcode::p_create_vector, Definition(tmp),
7966                            val[0], val[1], val[2], val[3]);
7967    }
7968    unsigned mask = instr->op == nir_texop_tg4 ? 0xF : dmask;
7969    expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, mask);
7970
7971 }
7972
7973
7974 Operand get_phi_operand(isel_context *ctx, nir_ssa_def *ssa)
7975 {
7976    Temp tmp = get_ssa_temp(ctx, ssa);
7977    if (ssa->parent_instr->type == nir_instr_type_ssa_undef)
7978       return Operand(tmp.regClass());
7979    else
7980       return Operand(tmp);
7981 }
7982
7983 void visit_phi(isel_context *ctx, nir_phi_instr *instr)
7984 {
7985    aco_ptr<Pseudo_instruction> phi;
7986    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7987    assert(instr->dest.ssa.bit_size != 1 || dst.regClass() == ctx->program->lane_mask);
7988
7989    bool logical = !dst.is_linear() || ctx->divergent_vals[instr->dest.ssa.index];
7990    logical |= ctx->block->kind & block_kind_merge;
7991    aco_opcode opcode = logical ? aco_opcode::p_phi : aco_opcode::p_linear_phi;
7992
7993    /* we want a sorted list of sources, since the predecessor list is also sorted */
7994    std::map<unsigned, nir_ssa_def*> phi_src;
7995    nir_foreach_phi_src(src, instr)
7996       phi_src[src->pred->index] = src->src.ssa;
7997
7998    std::vector<unsigned>& preds = logical ? ctx->block->logical_preds : ctx->block->linear_preds;
7999    unsigned num_operands = 0;
8000    Operand operands[std::max(exec_list_length(&instr->srcs), (unsigned)preds.size())];
8001    unsigned num_defined = 0;
8002    unsigned cur_pred_idx = 0;
8003    for (std::pair<unsigned, nir_ssa_def *> src : phi_src) {
8004       if (cur_pred_idx < preds.size()) {
8005          /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8006          unsigned block = ctx->cf_info.nir_to_aco[src.first];
8007          unsigned skipped = 0;
8008          while (cur_pred_idx + skipped < preds.size() && preds[cur_pred_idx + skipped] != block)
8009             skipped++;
8010          if (cur_pred_idx + skipped < preds.size()) {
8011             for (unsigned i = 0; i < skipped; i++)
8012                operands[num_operands++] = Operand(dst.regClass());
8013             cur_pred_idx += skipped;
8014          } else {
8015             continue;
8016          }
8017       }
8018       cur_pred_idx++;
8019       Operand op = get_phi_operand(ctx, src.second);
8020       operands[num_operands++] = op;
8021       num_defined += !op.isUndefined();
8022    }
8023    /* handle block_kind_continue_or_break at loop exit blocks */
8024    while (cur_pred_idx++ < preds.size())
8025       operands[num_operands++] = Operand(dst.regClass());
8026
8027    if (num_defined == 0) {
8028       Builder bld(ctx->program, ctx->block);
8029       if (dst.regClass() == s1) {
8030          bld.sop1(aco_opcode::s_mov_b32, Definition(dst), Operand(0u));
8031       } else if (dst.regClass() == v1) {
8032          bld.vop1(aco_opcode::v_mov_b32, Definition(dst), Operand(0u));
8033       } else {
8034          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
8035          for (unsigned i = 0; i < dst.size(); i++)
8036             vec->operands[i] = Operand(0u);
8037          vec->definitions[0] = Definition(dst);
8038          ctx->block->instructions.emplace_back(std::move(vec));
8039       }
8040       return;
8041    }
8042
8043    /* we can use a linear phi in some cases if one src is undef */
8044    if (dst.is_linear() && ctx->block->kind & block_kind_merge && num_defined == 1) {
8045       phi.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_linear_phi, Format::PSEUDO, num_operands, 1));
8046
8047       Block *linear_else = &ctx->program->blocks[ctx->block->linear_preds[1]];
8048       Block *invert = &ctx->program->blocks[linear_else->linear_preds[0]];
8049       assert(invert->kind & block_kind_invert);
8050
8051       unsigned then_block = invert->linear_preds[0];
8052
8053       Block* insert_block = NULL;
8054       for (unsigned i = 0; i < num_operands; i++) {
8055          Operand op = operands[i];
8056          if (op.isUndefined())
8057             continue;
8058          insert_block = ctx->block->logical_preds[i] == then_block ? invert : ctx->block;
8059          phi->operands[0] = op;
8060          break;
8061       }
8062       assert(insert_block); /* should be handled by the "num_defined == 0" case above */
8063       phi->operands[1] = Operand(dst.regClass());
8064       phi->definitions[0] = Definition(dst);
8065       insert_block->instructions.emplace(insert_block->instructions.begin(), std::move(phi));
8066       return;
8067    }
8068
8069    /* try to scalarize vector phis */
8070    if (instr->dest.ssa.bit_size != 1 && dst.size() > 1) {
8071       // TODO: scalarize linear phis on divergent ifs
8072       bool can_scalarize = (opcode == aco_opcode::p_phi || !(ctx->block->kind & block_kind_merge));
8073       std::array<Temp, NIR_MAX_VEC_COMPONENTS> new_vec;
8074       for (unsigned i = 0; can_scalarize && (i < num_operands); i++) {
8075          Operand src = operands[i];
8076          if (src.isTemp() && ctx->allocated_vec.find(src.tempId()) == ctx->allocated_vec.end())
8077             can_scalarize = false;
8078       }
8079       if (can_scalarize) {
8080          unsigned num_components = instr->dest.ssa.num_components;
8081          assert(dst.size() % num_components == 0);
8082          RegClass rc = RegClass(dst.type(), dst.size() / num_components);
8083
8084          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1)};
8085          for (unsigned k = 0; k < num_components; k++) {
8086             phi.reset(create_instruction<Pseudo_instruction>(opcode, Format::PSEUDO, num_operands, 1));
8087             for (unsigned i = 0; i < num_operands; i++) {
8088                Operand src = operands[i];
8089                phi->operands[i] = src.isTemp() ? Operand(ctx->allocated_vec[src.tempId()][k]) : Operand(rc);
8090             }
8091             Temp phi_dst = {ctx->program->allocateId(), rc};
8092             phi->definitions[0] = Definition(phi_dst);
8093             ctx->block->instructions.emplace(ctx->block->instructions.begin(), std::move(phi));
8094             new_vec[k] = phi_dst;
8095             vec->operands[k] = Operand(phi_dst);
8096          }
8097          vec->definitions[0] = Definition(dst);
8098          ctx->block->instructions.emplace_back(std::move(vec));
8099          ctx->allocated_vec.emplace(dst.id(), new_vec);
8100          return;
8101       }
8102    }
8103
8104    phi.reset(create_instruction<Pseudo_instruction>(opcode, Format::PSEUDO, num_operands, 1));
8105    for (unsigned i = 0; i < num_operands; i++)
8106       phi->operands[i] = operands[i];
8107    phi->definitions[0] = Definition(dst);
8108    ctx->block->instructions.emplace(ctx->block->instructions.begin(), std::move(phi));
8109 }
8110
8111
8112 void visit_undef(isel_context *ctx, nir_ssa_undef_instr *instr)
8113 {
8114    Temp dst = get_ssa_temp(ctx, &instr->def);
8115
8116    assert(dst.type() == RegType::sgpr);
8117
8118    if (dst.size() == 1) {
8119       Builder(ctx->program, ctx->block).copy(Definition(dst), Operand(0u));
8120    } else {
8121       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
8122       for (unsigned i = 0; i < dst.size(); i++)
8123          vec->operands[i] = Operand(0u);
8124       vec->definitions[0] = Definition(dst);
8125       ctx->block->instructions.emplace_back(std::move(vec));
8126    }
8127 }
8128
8129 void visit_jump(isel_context *ctx, nir_jump_instr *instr)
8130 {
8131    Builder bld(ctx->program, ctx->block);
8132    Block *logical_target;
8133    append_logical_end(ctx->block);
8134    unsigned idx = ctx->block->index;
8135
8136    switch (instr->type) {
8137    case nir_jump_break:
8138       logical_target = ctx->cf_info.parent_loop.exit;
8139       add_logical_edge(idx, logical_target);
8140       ctx->block->kind |= block_kind_break;
8141
8142       if (!ctx->cf_info.parent_if.is_divergent &&
8143           !ctx->cf_info.parent_loop.has_divergent_continue) {
8144          /* uniform break - directly jump out of the loop */
8145          ctx->block->kind |= block_kind_uniform;
8146          ctx->cf_info.has_branch = true;
8147          bld.branch(aco_opcode::p_branch);
8148          add_linear_edge(idx, logical_target);
8149          return;
8150       }
8151       ctx->cf_info.parent_loop.has_divergent_branch = true;
8152       ctx->cf_info.nir_to_aco[instr->instr.block->index] = ctx->block->index;
8153       break;
8154    case nir_jump_continue:
8155       logical_target = &ctx->program->blocks[ctx->cf_info.parent_loop.header_idx];
8156       add_logical_edge(idx, logical_target);
8157       ctx->block->kind |= block_kind_continue;
8158
8159       if (ctx->cf_info.parent_if.is_divergent) {
8160          /* for potential uniform breaks after this continue,
8161             we must ensure that they are handled correctly */
8162          ctx->cf_info.parent_loop.has_divergent_continue = true;
8163          ctx->cf_info.parent_loop.has_divergent_branch = true;
8164          ctx->cf_info.nir_to_aco[instr->instr.block->index] = ctx->block->index;
8165       } else {
8166          /* uniform continue - directly jump to the loop header */
8167          ctx->block->kind |= block_kind_uniform;
8168          ctx->cf_info.has_branch = true;
8169          bld.branch(aco_opcode::p_branch);
8170          add_linear_edge(idx, logical_target);
8171          return;
8172       }
8173       break;
8174    default:
8175       fprintf(stderr, "Unknown NIR jump instr: ");
8176       nir_print_instr(&instr->instr, stderr);
8177       fprintf(stderr, "\n");
8178       abort();
8179    }
8180
8181    if (ctx->cf_info.parent_if.is_divergent && !ctx->cf_info.exec_potentially_empty_break) {
8182       ctx->cf_info.exec_potentially_empty_break = true;
8183       ctx->cf_info.exec_potentially_empty_break_depth = ctx->cf_info.loop_nest_depth;
8184    }
8185
8186    /* remove critical edges from linear CFG */
8187    bld.branch(aco_opcode::p_branch);
8188    Block* break_block = ctx->program->create_and_insert_block();
8189    break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8190    break_block->kind |= block_kind_uniform;
8191    add_linear_edge(idx, break_block);
8192    /* the loop_header pointer might be invalidated by this point */
8193    if (instr->type == nir_jump_continue)
8194       logical_target = &ctx->program->blocks[ctx->cf_info.parent_loop.header_idx];
8195    add_linear_edge(break_block->index, logical_target);
8196    bld.reset(break_block);
8197    bld.branch(aco_opcode::p_branch);
8198
8199    Block* continue_block = ctx->program->create_and_insert_block();
8200    continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8201    add_linear_edge(idx, continue_block);
8202    append_logical_start(continue_block);
8203    ctx->block = continue_block;
8204    return;
8205 }
8206
8207 void visit_block(isel_context *ctx, nir_block *block)
8208 {
8209    nir_foreach_instr(instr, block) {
8210       switch (instr->type) {
8211       case nir_instr_type_alu:
8212          visit_alu_instr(ctx, nir_instr_as_alu(instr));
8213          break;
8214       case nir_instr_type_load_const:
8215          visit_load_const(ctx, nir_instr_as_load_const(instr));
8216          break;
8217       case nir_instr_type_intrinsic:
8218          visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
8219          break;
8220       case nir_instr_type_tex:
8221          visit_tex(ctx, nir_instr_as_tex(instr));
8222          break;
8223       case nir_instr_type_phi:
8224          visit_phi(ctx, nir_instr_as_phi(instr));
8225          break;
8226       case nir_instr_type_ssa_undef:
8227          visit_undef(ctx, nir_instr_as_ssa_undef(instr));
8228          break;
8229       case nir_instr_type_deref:
8230          break;
8231       case nir_instr_type_jump:
8232          visit_jump(ctx, nir_instr_as_jump(instr));
8233          break;
8234       default:
8235          fprintf(stderr, "Unknown NIR instr type: ");
8236          nir_print_instr(instr, stderr);
8237          fprintf(stderr, "\n");
8238          //abort();
8239       }
8240    }
8241
8242    if (!ctx->cf_info.parent_loop.has_divergent_branch)
8243       ctx->cf_info.nir_to_aco[block->index] = ctx->block->index;
8244 }
8245
8246
8247
8248 static void visit_loop(isel_context *ctx, nir_loop *loop)
8249 {
8250    //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
8251    append_logical_end(ctx->block);
8252    ctx->block->kind |= block_kind_loop_preheader | block_kind_uniform;
8253    Builder bld(ctx->program, ctx->block);
8254    bld.branch(aco_opcode::p_branch);
8255    unsigned loop_preheader_idx = ctx->block->index;
8256
8257    Block loop_exit = Block();
8258    loop_exit.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8259    loop_exit.kind |= (block_kind_loop_exit | (ctx->block->kind & block_kind_top_level));
8260
8261    Block* loop_header = ctx->program->create_and_insert_block();
8262    loop_header->loop_nest_depth = ctx->cf_info.loop_nest_depth + 1;
8263    loop_header->kind |= block_kind_loop_header;
8264    add_edge(loop_preheader_idx, loop_header);
8265    ctx->block = loop_header;
8266
8267    /* emit loop body */
8268    unsigned loop_header_idx = loop_header->index;
8269    loop_info_RAII loop_raii(ctx, loop_header_idx, &loop_exit);
8270    append_logical_start(ctx->block);
8271    visit_cf_list(ctx, &loop->body);
8272
8273    //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
8274    if (!ctx->cf_info.has_branch) {
8275       append_logical_end(ctx->block);
8276       if (ctx->cf_info.exec_potentially_empty_discard || ctx->cf_info.exec_potentially_empty_break) {
8277          /* Discards can result in code running with an empty exec mask.
8278           * This would result in divergent breaks not ever being taken. As a
8279           * workaround, break the loop when the loop mask is empty instead of
8280           * always continuing. */
8281          ctx->block->kind |= (block_kind_continue_or_break | block_kind_uniform);
8282          unsigned block_idx = ctx->block->index;
8283
8284          /* create helper blocks to avoid critical edges */
8285          Block *break_block = ctx->program->create_and_insert_block();
8286          break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8287          break_block->kind = block_kind_uniform;
8288          bld.reset(break_block);
8289          bld.branch(aco_opcode::p_branch);
8290          add_linear_edge(block_idx, break_block);
8291          add_linear_edge(break_block->index, &loop_exit);
8292
8293          Block *continue_block = ctx->program->create_and_insert_block();
8294          continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8295          continue_block->kind = block_kind_uniform;
8296          bld.reset(continue_block);
8297          bld.branch(aco_opcode::p_branch);
8298          add_linear_edge(block_idx, continue_block);
8299          add_linear_edge(continue_block->index, &ctx->program->blocks[loop_header_idx]);
8300
8301          if (!ctx->cf_info.parent_loop.has_divergent_branch)
8302             add_logical_edge(block_idx, &ctx->program->blocks[loop_header_idx]);
8303          ctx->block = &ctx->program->blocks[block_idx];
8304       } else {
8305          ctx->block->kind |= (block_kind_continue | block_kind_uniform);
8306          if (!ctx->cf_info.parent_loop.has_divergent_branch)
8307             add_edge(ctx->block->index, &ctx->program->blocks[loop_header_idx]);
8308          else
8309             add_linear_edge(ctx->block->index, &ctx->program->blocks[loop_header_idx]);
8310       }
8311
8312       bld.reset(ctx->block);
8313       bld.branch(aco_opcode::p_branch);
8314    }
8315
8316    /* fixup phis in loop header from unreachable blocks */
8317    if (ctx->cf_info.has_branch || ctx->cf_info.parent_loop.has_divergent_branch) {
8318       bool linear = ctx->cf_info.has_branch;
8319       bool logical = ctx->cf_info.has_branch || ctx->cf_info.parent_loop.has_divergent_branch;
8320       for (aco_ptr<Instruction>& instr : ctx->program->blocks[loop_header_idx].instructions) {
8321          if ((logical && instr->opcode == aco_opcode::p_phi) ||
8322              (linear && instr->opcode == aco_opcode::p_linear_phi)) {
8323             /* the last operand should be the one that needs to be removed */
8324             instr->operands.pop_back();
8325          } else if (!is_phi(instr)) {
8326             break;
8327          }
8328       }
8329    }
8330
8331    ctx->cf_info.has_branch = false;
8332
8333    // TODO: if the loop has not a single exit, we must add one °°
8334    /* emit loop successor block */
8335    ctx->block = ctx->program->insert_block(std::move(loop_exit));
8336    append_logical_start(ctx->block);
8337
8338    #if 0
8339    // TODO: check if it is beneficial to not branch on continues
8340    /* trim linear phis in loop header */
8341    for (auto&& instr : loop_entry->instructions) {
8342       if (instr->opcode == aco_opcode::p_linear_phi) {
8343          aco_ptr<Pseudo_instruction> new_phi{create_instruction<Pseudo_instruction>(aco_opcode::p_linear_phi, Format::PSEUDO, loop_entry->linear_predecessors.size(), 1)};
8344          new_phi->definitions[0] = instr->definitions[0];
8345          for (unsigned i = 0; i < new_phi->operands.size(); i++)
8346             new_phi->operands[i] = instr->operands[i];
8347          /* check that the remaining operands are all the same */
8348          for (unsigned i = new_phi->operands.size(); i < instr->operands.size(); i++)
8349             assert(instr->operands[i].tempId() == instr->operands.back().tempId());
8350          instr.swap(new_phi);
8351       } else if (instr->opcode == aco_opcode::p_phi) {
8352          continue;
8353       } else {
8354          break;
8355       }
8356    }
8357    #endif
8358 }
8359
8360 static void begin_divergent_if_then(isel_context *ctx, if_context *ic, Temp cond)
8361 {
8362    ic->cond = cond;
8363
8364    append_logical_end(ctx->block);
8365    ctx->block->kind |= block_kind_branch;
8366
8367    /* branch to linear then block */
8368    assert(cond.regClass() == ctx->program->lane_mask);
8369    aco_ptr<Pseudo_branch_instruction> branch;
8370    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_z, Format::PSEUDO_BRANCH, 1, 0));
8371    branch->operands[0] = Operand(cond);
8372    ctx->block->instructions.push_back(std::move(branch));
8373
8374    ic->BB_if_idx = ctx->block->index;
8375    ic->BB_invert = Block();
8376    ic->BB_invert.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8377    /* Invert blocks are intentionally not marked as top level because they
8378     * are not part of the logical cfg. */
8379    ic->BB_invert.kind |= block_kind_invert;
8380    ic->BB_endif = Block();
8381    ic->BB_endif.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8382    ic->BB_endif.kind |= (block_kind_merge | (ctx->block->kind & block_kind_top_level));
8383
8384    ic->exec_potentially_empty_discard_old = ctx->cf_info.exec_potentially_empty_discard;
8385    ic->exec_potentially_empty_break_old = ctx->cf_info.exec_potentially_empty_break;
8386    ic->exec_potentially_empty_break_depth_old = ctx->cf_info.exec_potentially_empty_break_depth;
8387    ic->divergent_old = ctx->cf_info.parent_if.is_divergent;
8388    ctx->cf_info.parent_if.is_divergent = true;
8389
8390    /* divergent branches use cbranch_execz */
8391    ctx->cf_info.exec_potentially_empty_discard = false;
8392    ctx->cf_info.exec_potentially_empty_break = false;
8393    ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8394
8395    /** emit logical then block */
8396    Block* BB_then_logical = ctx->program->create_and_insert_block();
8397    BB_then_logical->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8398    add_edge(ic->BB_if_idx, BB_then_logical);
8399    ctx->block = BB_then_logical;
8400    append_logical_start(BB_then_logical);
8401 }
8402
8403 static void begin_divergent_if_else(isel_context *ctx, if_context *ic)
8404 {
8405    Block *BB_then_logical = ctx->block;
8406    append_logical_end(BB_then_logical);
8407     /* branch from logical then block to invert block */
8408    aco_ptr<Pseudo_branch_instruction> branch;
8409    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8410    BB_then_logical->instructions.emplace_back(std::move(branch));
8411    add_linear_edge(BB_then_logical->index, &ic->BB_invert);
8412    if (!ctx->cf_info.parent_loop.has_divergent_branch)
8413       add_logical_edge(BB_then_logical->index, &ic->BB_endif);
8414    BB_then_logical->kind |= block_kind_uniform;
8415    assert(!ctx->cf_info.has_branch);
8416    ic->then_branch_divergent = ctx->cf_info.parent_loop.has_divergent_branch;
8417    ctx->cf_info.parent_loop.has_divergent_branch = false;
8418
8419    /** emit linear then block */
8420    Block* BB_then_linear = ctx->program->create_and_insert_block();
8421    BB_then_linear->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8422    BB_then_linear->kind |= block_kind_uniform;
8423    add_linear_edge(ic->BB_if_idx, BB_then_linear);
8424    /* branch from linear then block to invert block */
8425    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8426    BB_then_linear->instructions.emplace_back(std::move(branch));
8427    add_linear_edge(BB_then_linear->index, &ic->BB_invert);
8428
8429    /** emit invert merge block */
8430    ctx->block = ctx->program->insert_block(std::move(ic->BB_invert));
8431    ic->invert_idx = ctx->block->index;
8432
8433    /* branch to linear else block (skip else) */
8434    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_nz, Format::PSEUDO_BRANCH, 1, 0));
8435    branch->operands[0] = Operand(ic->cond);
8436    ctx->block->instructions.push_back(std::move(branch));
8437
8438    ic->exec_potentially_empty_discard_old |= ctx->cf_info.exec_potentially_empty_discard;
8439    ic->exec_potentially_empty_break_old |= ctx->cf_info.exec_potentially_empty_break;
8440    ic->exec_potentially_empty_break_depth_old =
8441       std::min(ic->exec_potentially_empty_break_depth_old, ctx->cf_info.exec_potentially_empty_break_depth);
8442    /* divergent branches use cbranch_execz */
8443    ctx->cf_info.exec_potentially_empty_discard = false;
8444    ctx->cf_info.exec_potentially_empty_break = false;
8445    ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8446
8447    /** emit logical else block */
8448    Block* BB_else_logical = ctx->program->create_and_insert_block();
8449    BB_else_logical->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8450    add_logical_edge(ic->BB_if_idx, BB_else_logical);
8451    add_linear_edge(ic->invert_idx, BB_else_logical);
8452    ctx->block = BB_else_logical;
8453    append_logical_start(BB_else_logical);
8454 }
8455
8456 static void end_divergent_if(isel_context *ctx, if_context *ic)
8457 {
8458    Block *BB_else_logical = ctx->block;
8459    append_logical_end(BB_else_logical);
8460
8461    /* branch from logical else block to endif block */
8462    aco_ptr<Pseudo_branch_instruction> branch;
8463    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8464    BB_else_logical->instructions.emplace_back(std::move(branch));
8465    add_linear_edge(BB_else_logical->index, &ic->BB_endif);
8466    if (!ctx->cf_info.parent_loop.has_divergent_branch)
8467       add_logical_edge(BB_else_logical->index, &ic->BB_endif);
8468    BB_else_logical->kind |= block_kind_uniform;
8469
8470    assert(!ctx->cf_info.has_branch);
8471    ctx->cf_info.parent_loop.has_divergent_branch &= ic->then_branch_divergent;
8472
8473
8474    /** emit linear else block */
8475    Block* BB_else_linear = ctx->program->create_and_insert_block();
8476    BB_else_linear->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8477    BB_else_linear->kind |= block_kind_uniform;
8478    add_linear_edge(ic->invert_idx, BB_else_linear);
8479
8480    /* branch from linear else block to endif block */
8481    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8482    BB_else_linear->instructions.emplace_back(std::move(branch));
8483    add_linear_edge(BB_else_linear->index, &ic->BB_endif);
8484
8485
8486    /** emit endif merge block */
8487    ctx->block = ctx->program->insert_block(std::move(ic->BB_endif));
8488    append_logical_start(ctx->block);
8489
8490
8491    ctx->cf_info.parent_if.is_divergent = ic->divergent_old;
8492    ctx->cf_info.exec_potentially_empty_discard |= ic->exec_potentially_empty_discard_old;
8493    ctx->cf_info.exec_potentially_empty_break |= ic->exec_potentially_empty_break_old;
8494    ctx->cf_info.exec_potentially_empty_break_depth =
8495       std::min(ic->exec_potentially_empty_break_depth_old, ctx->cf_info.exec_potentially_empty_break_depth);
8496    if (ctx->cf_info.loop_nest_depth == ctx->cf_info.exec_potentially_empty_break_depth &&
8497        !ctx->cf_info.parent_if.is_divergent) {
8498       ctx->cf_info.exec_potentially_empty_break = false;
8499       ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8500    }
8501    /* uniform control flow never has an empty exec-mask */
8502    if (!ctx->cf_info.loop_nest_depth && !ctx->cf_info.parent_if.is_divergent) {
8503       ctx->cf_info.exec_potentially_empty_discard = false;
8504       ctx->cf_info.exec_potentially_empty_break = false;
8505       ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8506    }
8507 }
8508
8509 static void visit_if(isel_context *ctx, nir_if *if_stmt)
8510 {
8511    Temp cond = get_ssa_temp(ctx, if_stmt->condition.ssa);
8512    Builder bld(ctx->program, ctx->block);
8513    aco_ptr<Pseudo_branch_instruction> branch;
8514
8515    if (!ctx->divergent_vals[if_stmt->condition.ssa->index]) { /* uniform condition */
8516       /**
8517        * Uniform conditionals are represented in the following way*) :
8518        *
8519        * The linear and logical CFG:
8520        *                        BB_IF
8521        *                        /    \
8522        *       BB_THEN (logical)      BB_ELSE (logical)
8523        *                        \    /
8524        *                        BB_ENDIF
8525        *
8526        * *) Exceptions may be due to break and continue statements within loops
8527        *    If a break/continue happens within uniform control flow, it branches
8528        *    to the loop exit/entry block. Otherwise, it branches to the next
8529        *    merge block.
8530        **/
8531       append_logical_end(ctx->block);
8532       ctx->block->kind |= block_kind_uniform;
8533
8534       /* emit branch */
8535       assert(cond.regClass() == bld.lm);
8536       // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
8537       cond = bool_to_scalar_condition(ctx, cond);
8538
8539       branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_z, Format::PSEUDO_BRANCH, 1, 0));
8540       branch->operands[0] = Operand(cond);
8541       branch->operands[0].setFixed(scc);
8542       ctx->block->instructions.emplace_back(std::move(branch));
8543
8544       unsigned BB_if_idx = ctx->block->index;
8545       Block BB_endif = Block();
8546       BB_endif.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8547       BB_endif.kind |= ctx->block->kind & block_kind_top_level;
8548
8549       /** emit then block */
8550       Block* BB_then = ctx->program->create_and_insert_block();
8551       BB_then->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8552       add_edge(BB_if_idx, BB_then);
8553       append_logical_start(BB_then);
8554       ctx->block = BB_then;
8555       visit_cf_list(ctx, &if_stmt->then_list);
8556       BB_then = ctx->block;
8557       bool then_branch = ctx->cf_info.has_branch;
8558       bool then_branch_divergent = ctx->cf_info.parent_loop.has_divergent_branch;
8559
8560       if (!then_branch) {
8561          append_logical_end(BB_then);
8562          /* branch from then block to endif block */
8563          branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8564          BB_then->instructions.emplace_back(std::move(branch));
8565          add_linear_edge(BB_then->index, &BB_endif);
8566          if (!then_branch_divergent)
8567             add_logical_edge(BB_then->index, &BB_endif);
8568          BB_then->kind |= block_kind_uniform;
8569       }
8570
8571       ctx->cf_info.has_branch = false;
8572       ctx->cf_info.parent_loop.has_divergent_branch = false;
8573
8574       /** emit else block */
8575       Block* BB_else = ctx->program->create_and_insert_block();
8576       BB_else->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8577       add_edge(BB_if_idx, BB_else);
8578       append_logical_start(BB_else);
8579       ctx->block = BB_else;
8580       visit_cf_list(ctx, &if_stmt->else_list);
8581       BB_else = ctx->block;
8582
8583       if (!ctx->cf_info.has_branch) {
8584          append_logical_end(BB_else);
8585          /* branch from then block to endif block */
8586          branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8587          BB_else->instructions.emplace_back(std::move(branch));
8588          add_linear_edge(BB_else->index, &BB_endif);
8589          if (!ctx->cf_info.parent_loop.has_divergent_branch)
8590             add_logical_edge(BB_else->index, &BB_endif);
8591          BB_else->kind |= block_kind_uniform;
8592       }
8593
8594       ctx->cf_info.has_branch &= then_branch;
8595       ctx->cf_info.parent_loop.has_divergent_branch &= then_branch_divergent;
8596
8597       /** emit endif merge block */
8598       if (!ctx->cf_info.has_branch) {
8599          ctx->block = ctx->program->insert_block(std::move(BB_endif));
8600          append_logical_start(ctx->block);
8601       }
8602    } else { /* non-uniform condition */
8603       /**
8604        * To maintain a logical and linear CFG without critical edges,
8605        * non-uniform conditionals are represented in the following way*) :
8606        *
8607        * The linear CFG:
8608        *                        BB_IF
8609        *                        /    \
8610        *       BB_THEN (logical)      BB_THEN (linear)
8611        *                        \    /
8612        *                        BB_INVERT (linear)
8613        *                        /    \
8614        *       BB_ELSE (logical)      BB_ELSE (linear)
8615        *                        \    /
8616        *                        BB_ENDIF
8617        *
8618        * The logical CFG:
8619        *                        BB_IF
8620        *                        /    \
8621        *       BB_THEN (logical)      BB_ELSE (logical)
8622        *                        \    /
8623        *                        BB_ENDIF
8624        *
8625        * *) Exceptions may be due to break and continue statements within loops
8626        **/
8627
8628       if_context ic;
8629
8630       begin_divergent_if_then(ctx, &ic, cond);
8631       visit_cf_list(ctx, &if_stmt->then_list);
8632
8633       begin_divergent_if_else(ctx, &ic);
8634       visit_cf_list(ctx, &if_stmt->else_list);
8635
8636       end_divergent_if(ctx, &ic);
8637    }
8638 }
8639
8640 static void visit_cf_list(isel_context *ctx,
8641                           struct exec_list *list)
8642 {
8643    foreach_list_typed(nir_cf_node, node, node, list) {
8644       switch (node->type) {
8645       case nir_cf_node_block:
8646          visit_block(ctx, nir_cf_node_as_block(node));
8647          break;
8648       case nir_cf_node_if:
8649          visit_if(ctx, nir_cf_node_as_if(node));
8650          break;
8651       case nir_cf_node_loop:
8652          visit_loop(ctx, nir_cf_node_as_loop(node));
8653          break;
8654       default:
8655          unreachable("unimplemented cf list type");
8656       }
8657    }
8658 }
8659
8660 static void export_vs_varying(isel_context *ctx, int slot, bool is_pos, int *next_pos)
8661 {
8662    int offset = ctx->program->info->vs.outinfo.vs_output_param_offset[slot];
8663    uint64_t mask = ctx->outputs.mask[slot];
8664    if (!is_pos && !mask)
8665       return;
8666    if (!is_pos && offset == AC_EXP_PARAM_UNDEFINED)
8667       return;
8668    aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
8669    exp->enabled_mask = mask;
8670    for (unsigned i = 0; i < 4; ++i) {
8671       if (mask & (1 << i))
8672          exp->operands[i] = Operand(ctx->outputs.outputs[slot][i]);
8673       else
8674          exp->operands[i] = Operand(v1);
8675    }
8676    /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
8677     * Setting valid_mask=1 prevents it and has no other effect.
8678     */
8679    exp->valid_mask = ctx->options->chip_class >= GFX10 && is_pos && *next_pos == 0;
8680    exp->done = false;
8681    exp->compressed = false;
8682    if (is_pos)
8683       exp->dest = V_008DFC_SQ_EXP_POS + (*next_pos)++;
8684    else
8685       exp->dest = V_008DFC_SQ_EXP_PARAM + offset;
8686    ctx->block->instructions.emplace_back(std::move(exp));
8687 }
8688
8689 static void export_vs_psiz_layer_viewport(isel_context *ctx, int *next_pos)
8690 {
8691    aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
8692    exp->enabled_mask = 0;
8693    for (unsigned i = 0; i < 4; ++i)
8694       exp->operands[i] = Operand(v1);
8695    if (ctx->outputs.mask[VARYING_SLOT_PSIZ]) {
8696       exp->operands[0] = Operand(ctx->outputs.outputs[VARYING_SLOT_PSIZ][0]);
8697       exp->enabled_mask |= 0x1;
8698    }
8699    if (ctx->outputs.mask[VARYING_SLOT_LAYER]) {
8700       exp->operands[2] = Operand(ctx->outputs.outputs[VARYING_SLOT_LAYER][0]);
8701       exp->enabled_mask |= 0x4;
8702    }
8703    if (ctx->outputs.mask[VARYING_SLOT_VIEWPORT]) {
8704       if (ctx->options->chip_class < GFX9) {
8705          exp->operands[3] = Operand(ctx->outputs.outputs[VARYING_SLOT_VIEWPORT][0]);
8706          exp->enabled_mask |= 0x8;
8707       } else {
8708          Builder bld(ctx->program, ctx->block);
8709
8710          Temp out = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(16u),
8711                              Operand(ctx->outputs.outputs[VARYING_SLOT_VIEWPORT][0]));
8712          if (exp->operands[2].isTemp())
8713             out = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(out), exp->operands[2]);
8714
8715          exp->operands[2] = Operand(out);
8716          exp->enabled_mask |= 0x4;
8717       }
8718    }
8719    exp->valid_mask = ctx->options->chip_class >= GFX10 && *next_pos == 0;
8720    exp->done = false;
8721    exp->compressed = false;
8722    exp->dest = V_008DFC_SQ_EXP_POS + (*next_pos)++;
8723    ctx->block->instructions.emplace_back(std::move(exp));
8724 }
8725
8726 static void create_vs_exports(isel_context *ctx)
8727 {
8728    radv_vs_output_info *outinfo = &ctx->program->info->vs.outinfo;
8729
8730    if (outinfo->export_prim_id) {
8731       ctx->outputs.mask[VARYING_SLOT_PRIMITIVE_ID] |= 0x1;
8732       ctx->outputs.outputs[VARYING_SLOT_PRIMITIVE_ID][0] = get_arg(ctx, ctx->args->vs_prim_id);
8733    }
8734
8735    if (ctx->options->key.has_multiview_view_index) {
8736       ctx->outputs.mask[VARYING_SLOT_LAYER] |= 0x1;
8737       ctx->outputs.outputs[VARYING_SLOT_LAYER][0] = as_vgpr(ctx, get_arg(ctx, ctx->args->ac.view_index));
8738    }
8739
8740    /* the order these position exports are created is important */
8741    int next_pos = 0;
8742    export_vs_varying(ctx, VARYING_SLOT_POS, true, &next_pos);
8743    if (outinfo->writes_pointsize || outinfo->writes_layer || outinfo->writes_viewport_index) {
8744       export_vs_psiz_layer_viewport(ctx, &next_pos);
8745    }
8746    if (ctx->num_clip_distances + ctx->num_cull_distances > 0)
8747       export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST0, true, &next_pos);
8748    if (ctx->num_clip_distances + ctx->num_cull_distances > 4)
8749       export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST1, true, &next_pos);
8750
8751    if (ctx->export_clip_dists) {
8752       if (ctx->num_clip_distances + ctx->num_cull_distances > 0)
8753          export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST0, false, &next_pos);
8754       if (ctx->num_clip_distances + ctx->num_cull_distances > 4)
8755          export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST1, false, &next_pos);
8756    }
8757
8758    for (unsigned i = 0; i <= VARYING_SLOT_VAR31; ++i) {
8759       if (i < VARYING_SLOT_VAR0 && i != VARYING_SLOT_LAYER &&
8760           i != VARYING_SLOT_PRIMITIVE_ID)
8761          continue;
8762
8763       export_vs_varying(ctx, i, false, NULL);
8764    }
8765 }
8766
8767 static void export_fs_mrt_z(isel_context *ctx)
8768 {
8769    Builder bld(ctx->program, ctx->block);
8770    unsigned enabled_channels = 0;
8771    bool compr = false;
8772    Operand values[4];
8773
8774    for (unsigned i = 0; i < 4; ++i) {
8775       values[i] = Operand(v1);
8776    }
8777
8778    /* Both stencil and sample mask only need 16-bits. */
8779    if (!ctx->program->info->ps.writes_z &&
8780        (ctx->program->info->ps.writes_stencil ||
8781         ctx->program->info->ps.writes_sample_mask)) {
8782       compr = true; /* COMPR flag */
8783
8784       if (ctx->program->info->ps.writes_stencil) {
8785          /* Stencil should be in X[23:16]. */
8786          values[0] = Operand(ctx->outputs.outputs[FRAG_RESULT_STENCIL][0]);
8787          values[0] = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(16u), values[0]);
8788          enabled_channels |= 0x3;
8789       }
8790
8791       if (ctx->program->info->ps.writes_sample_mask) {
8792          /* SampleMask should be in Y[15:0]. */
8793          values[1] = Operand(ctx->outputs.outputs[FRAG_RESULT_SAMPLE_MASK][0]);
8794          enabled_channels |= 0xc;
8795      }
8796    } else {
8797       if (ctx->program->info->ps.writes_z) {
8798          values[0] = Operand(ctx->outputs.outputs[FRAG_RESULT_DEPTH][0]);
8799          enabled_channels |= 0x1;
8800       }
8801
8802       if (ctx->program->info->ps.writes_stencil) {
8803          values[1] = Operand(ctx->outputs.outputs[FRAG_RESULT_STENCIL][0]);
8804          enabled_channels |= 0x2;
8805       }
8806
8807       if (ctx->program->info->ps.writes_sample_mask) {
8808          values[2] = Operand(ctx->outputs.outputs[FRAG_RESULT_SAMPLE_MASK][0]);
8809          enabled_channels |= 0x4;
8810       }
8811    }
8812
8813    /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
8814     * writemask component.
8815     */
8816    if (ctx->options->chip_class == GFX6 &&
8817        ctx->options->family != CHIP_OLAND &&
8818        ctx->options->family != CHIP_HAINAN) {
8819             enabled_channels |= 0x1;
8820    }
8821
8822    bld.exp(aco_opcode::exp, values[0], values[1], values[2], values[3],
8823            enabled_channels, V_008DFC_SQ_EXP_MRTZ, compr);
8824 }
8825
8826 static void export_fs_mrt_color(isel_context *ctx, int slot)
8827 {
8828    Builder bld(ctx->program, ctx->block);
8829    unsigned write_mask = ctx->outputs.mask[slot];
8830    Operand values[4];
8831
8832    for (unsigned i = 0; i < 4; ++i) {
8833       if (write_mask & (1 << i)) {
8834          values[i] = Operand(ctx->outputs.outputs[slot][i]);
8835       } else {
8836          values[i] = Operand(v1);
8837       }
8838    }
8839
8840    unsigned target, col_format;
8841    unsigned enabled_channels = 0;
8842    aco_opcode compr_op = (aco_opcode)0;
8843
8844    slot -= FRAG_RESULT_DATA0;
8845    target = V_008DFC_SQ_EXP_MRT + slot;
8846    col_format = (ctx->options->key.fs.col_format >> (4 * slot)) & 0xf;
8847
8848    bool is_int8 = (ctx->options->key.fs.is_int8 >> slot) & 1;
8849    bool is_int10 = (ctx->options->key.fs.is_int10 >> slot) & 1;
8850
8851    switch (col_format)
8852    {
8853    case V_028714_SPI_SHADER_ZERO:
8854       enabled_channels = 0; /* writemask */
8855       target = V_008DFC_SQ_EXP_NULL;
8856       break;
8857
8858    case V_028714_SPI_SHADER_32_R:
8859       enabled_channels = 1;
8860       break;
8861
8862    case V_028714_SPI_SHADER_32_GR:
8863       enabled_channels = 0x3;
8864       break;
8865
8866    case V_028714_SPI_SHADER_32_AR:
8867       if (ctx->options->chip_class >= GFX10) {
8868          /* Special case: on GFX10, the outputs are different for 32_AR */
8869          enabled_channels = 0x3;
8870          values[1] = values[3];
8871          values[3] = Operand(v1);
8872       } else {
8873          enabled_channels = 0x9;
8874       }
8875       break;
8876
8877    case V_028714_SPI_SHADER_FP16_ABGR:
8878       enabled_channels = 0x5;
8879       compr_op = aco_opcode::v_cvt_pkrtz_f16_f32;
8880       break;
8881
8882    case V_028714_SPI_SHADER_UNORM16_ABGR:
8883       enabled_channels = 0x5;
8884       compr_op = aco_opcode::v_cvt_pknorm_u16_f32;
8885       break;
8886
8887    case V_028714_SPI_SHADER_SNORM16_ABGR:
8888       enabled_channels = 0x5;
8889       compr_op = aco_opcode::v_cvt_pknorm_i16_f32;
8890       break;
8891
8892    case V_028714_SPI_SHADER_UINT16_ABGR: {
8893       enabled_channels = 0x5;
8894       compr_op = aco_opcode::v_cvt_pk_u16_u32;
8895       if (is_int8 || is_int10) {
8896          /* clamp */
8897          uint32_t max_rgb = is_int8 ? 255 : is_int10 ? 1023 : 0;
8898          Temp max_rgb_val = bld.copy(bld.def(s1), Operand(max_rgb));
8899
8900          for (unsigned i = 0; i < 4; i++) {
8901             if ((write_mask >> i) & 1) {
8902                values[i] = bld.vop2(aco_opcode::v_min_u32, bld.def(v1),
8903                                     i == 3 && is_int10 ? Operand(3u) : Operand(max_rgb_val),
8904                                     values[i]);
8905             }
8906          }
8907       }
8908       break;
8909    }
8910
8911    case V_028714_SPI_SHADER_SINT16_ABGR:
8912       enabled_channels = 0x5;
8913       compr_op = aco_opcode::v_cvt_pk_i16_i32;
8914       if (is_int8 || is_int10) {
8915          /* clamp */
8916          uint32_t max_rgb = is_int8 ? 127 : is_int10 ? 511 : 0;
8917          uint32_t min_rgb = is_int8 ? -128 :is_int10 ? -512 : 0;
8918          Temp max_rgb_val = bld.copy(bld.def(s1), Operand(max_rgb));
8919          Temp min_rgb_val = bld.copy(bld.def(s1), Operand(min_rgb));
8920
8921          for (unsigned i = 0; i < 4; i++) {
8922             if ((write_mask >> i) & 1) {
8923                values[i] = bld.vop2(aco_opcode::v_min_i32, bld.def(v1),
8924                                     i == 3 && is_int10 ? Operand(1u) : Operand(max_rgb_val),
8925                                     values[i]);
8926                values[i] = bld.vop2(aco_opcode::v_max_i32, bld.def(v1),
8927                                     i == 3 && is_int10 ? Operand(-2u) : Operand(min_rgb_val),
8928                                     values[i]);
8929             }
8930          }
8931       }
8932       break;
8933
8934    case V_028714_SPI_SHADER_32_ABGR:
8935       enabled_channels = 0xF;
8936       break;
8937
8938    default:
8939       break;
8940    }
8941
8942    if (target == V_008DFC_SQ_EXP_NULL)
8943       return;
8944
8945    if ((bool) compr_op) {
8946       for (int i = 0; i < 2; i++) {
8947          /* check if at least one of the values to be compressed is enabled */
8948          unsigned enabled = (write_mask >> (i*2) | write_mask >> (i*2+1)) & 0x1;
8949          if (enabled) {
8950             enabled_channels |= enabled << (i*2);
8951             values[i] = bld.vop3(compr_op, bld.def(v1),
8952                                  values[i*2].isUndefined() ? Operand(0u) : values[i*2],
8953                                  values[i*2+1].isUndefined() ? Operand(0u): values[i*2+1]);
8954          } else {
8955             values[i] = Operand(v1);
8956          }
8957       }
8958       values[2] = Operand(v1);
8959       values[3] = Operand(v1);
8960    } else {
8961       for (int i = 0; i < 4; i++)
8962          values[i] = enabled_channels & (1 << i) ? values[i] : Operand(v1);
8963    }
8964
8965    bld.exp(aco_opcode::exp, values[0], values[1], values[2], values[3],
8966            enabled_channels, target, (bool) compr_op);
8967 }
8968
8969 static void create_fs_exports(isel_context *ctx)
8970 {
8971    /* Export depth, stencil and sample mask. */
8972    if (ctx->outputs.mask[FRAG_RESULT_DEPTH] ||
8973        ctx->outputs.mask[FRAG_RESULT_STENCIL] ||
8974        ctx->outputs.mask[FRAG_RESULT_SAMPLE_MASK]) {
8975       export_fs_mrt_z(ctx);
8976    }
8977
8978    /* Export all color render targets. */
8979    for (unsigned i = FRAG_RESULT_DATA0; i < FRAG_RESULT_DATA7 + 1; ++i) {
8980       if (ctx->outputs.mask[i])
8981          export_fs_mrt_color(ctx, i);
8982    }
8983 }
8984
8985 static void emit_stream_output(isel_context *ctx,
8986                                Temp const *so_buffers,
8987                                Temp const *so_write_offset,
8988                                const struct radv_stream_output *output)
8989 {
8990    unsigned num_comps = util_bitcount(output->component_mask);
8991    unsigned writemask = (1 << num_comps) - 1;
8992    unsigned loc = output->location;
8993    unsigned buf = output->buffer;
8994
8995    assert(num_comps && num_comps <= 4);
8996    if (!num_comps || num_comps > 4)
8997       return;
8998
8999    unsigned start = ffs(output->component_mask) - 1;
9000
9001    Temp out[4];
9002    bool all_undef = true;
9003    assert(ctx->stage == vertex_vs || ctx->stage == gs_copy_vs);
9004    for (unsigned i = 0; i < num_comps; i++) {
9005       out[i] = ctx->outputs.outputs[loc][start + i];
9006       all_undef = all_undef && !out[i].id();
9007    }
9008    if (all_undef)
9009       return;
9010
9011    while (writemask) {
9012       int start, count;
9013       u_bit_scan_consecutive_range(&writemask, &start, &count);
9014       if (count == 3 && ctx->options->chip_class == GFX6) {
9015          /* GFX6 doesn't support storing vec3, split it. */
9016          writemask |= 1u << (start + 2);
9017          count = 2;
9018       }
9019
9020       unsigned offset = output->offset + start * 4;
9021
9022       Temp write_data = {ctx->program->allocateId(), RegClass(RegType::vgpr, count)};
9023       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
9024       for (int i = 0; i < count; ++i)
9025          vec->operands[i] = (ctx->outputs.mask[loc] & 1 << (start + i)) ? Operand(out[start + i]) : Operand(0u);
9026       vec->definitions[0] = Definition(write_data);
9027       ctx->block->instructions.emplace_back(std::move(vec));
9028
9029       aco_opcode opcode;
9030       switch (count) {
9031       case 1:
9032          opcode = aco_opcode::buffer_store_dword;
9033          break;
9034       case 2:
9035          opcode = aco_opcode::buffer_store_dwordx2;
9036          break;
9037       case 3:
9038          opcode = aco_opcode::buffer_store_dwordx3;
9039          break;
9040       case 4:
9041          opcode = aco_opcode::buffer_store_dwordx4;
9042          break;
9043       default:
9044          unreachable("Unsupported dword count.");
9045       }
9046
9047       aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 4, 0)};
9048       store->operands[0] = Operand(so_buffers[buf]);
9049       store->operands[1] = Operand(so_write_offset[buf]);
9050       store->operands[2] = Operand((uint32_t) 0);
9051       store->operands[3] = Operand(write_data);
9052       if (offset > 4095) {
9053          /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
9054          Builder bld(ctx->program, ctx->block);
9055          store->operands[0] = bld.vadd32(bld.def(v1), Operand(offset), Operand(so_write_offset[buf]));
9056       } else {
9057          store->offset = offset;
9058       }
9059       store->offen = true;
9060       store->glc = true;
9061       store->dlc = false;
9062       store->slc = true;
9063       store->can_reorder = true;
9064       ctx->block->instructions.emplace_back(std::move(store));
9065    }
9066 }
9067
9068 static void emit_streamout(isel_context *ctx, unsigned stream)
9069 {
9070    Builder bld(ctx->program, ctx->block);
9071
9072    Temp so_buffers[4];
9073    Temp buf_ptr = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->streamout_buffers));
9074    for (unsigned i = 0; i < 4; i++) {
9075       unsigned stride = ctx->program->info->so.strides[i];
9076       if (!stride)
9077          continue;
9078
9079       Operand off = bld.copy(bld.def(s1), Operand(i * 16u));
9080       so_buffers[i] = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), buf_ptr, off);
9081    }
9082
9083    Temp so_vtx_count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
9084                                 get_arg(ctx, ctx->args->streamout_config), Operand(0x70010u));
9085
9086    Temp tid = emit_mbcnt(ctx, bld.def(v1));
9087
9088    Temp can_emit = bld.vopc(aco_opcode::v_cmp_gt_i32, bld.def(bld.lm), so_vtx_count, tid);
9089
9090    if_context ic;
9091    begin_divergent_if_then(ctx, &ic, can_emit);
9092
9093    bld.reset(ctx->block);
9094
9095    Temp so_write_index = bld.vadd32(bld.def(v1), get_arg(ctx, ctx->args->streamout_write_idx), tid);
9096
9097    Temp so_write_offset[4];
9098
9099    for (unsigned i = 0; i < 4; i++) {
9100       unsigned stride = ctx->program->info->so.strides[i];
9101       if (!stride)
9102          continue;
9103
9104       if (stride == 1) {
9105          Temp offset = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
9106                                 get_arg(ctx, ctx->args->streamout_write_idx),
9107                                 get_arg(ctx, ctx->args->streamout_offset[i]));
9108          Temp new_offset = bld.vadd32(bld.def(v1), offset, tid);
9109
9110          so_write_offset[i] = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), new_offset);
9111       } else {
9112          Temp offset = bld.v_mul_imm(bld.def(v1), so_write_index, stride * 4u);
9113          Temp offset2 = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(4u),
9114                                  get_arg(ctx, ctx->args->streamout_offset[i]));
9115          so_write_offset[i] = bld.vadd32(bld.def(v1), offset, offset2);
9116       }
9117    }
9118
9119    for (unsigned i = 0; i < ctx->program->info->so.num_outputs; i++) {
9120       struct radv_stream_output *output =
9121          &ctx->program->info->so.outputs[i];
9122       if (stream != output->stream)
9123          continue;
9124
9125       emit_stream_output(ctx, so_buffers, so_write_offset, output);
9126    }
9127
9128    begin_divergent_if_else(ctx, &ic);
9129    end_divergent_if(ctx, &ic);
9130 }
9131
9132 } /* end namespace */
9133
9134 void split_arguments(isel_context *ctx, Pseudo_instruction *startpgm)
9135 {
9136    /* Split all arguments except for the first (ring_offsets) and the last
9137     * (exec) so that the dead channels don't stay live throughout the program.
9138     */
9139    for (int i = 1; i < startpgm->definitions.size() - 1; i++) {
9140       if (startpgm->definitions[i].regClass().size() > 1) {
9141          emit_split_vector(ctx, startpgm->definitions[i].getTemp(),
9142                            startpgm->definitions[i].regClass().size());
9143       }
9144    }
9145 }
9146
9147 void handle_bc_optimize(isel_context *ctx)
9148 {
9149    /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
9150    Builder bld(ctx->program, ctx->block);
9151    uint32_t spi_ps_input_ena = ctx->program->config->spi_ps_input_ena;
9152    bool uses_center = G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena);
9153    bool uses_centroid = G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena);
9154    ctx->persp_centroid = get_arg(ctx, ctx->args->ac.persp_centroid);
9155    ctx->linear_centroid = get_arg(ctx, ctx->args->ac.linear_centroid);
9156    if (uses_center && uses_centroid) {
9157       Temp sel = bld.vopc_e64(aco_opcode::v_cmp_lt_i32, bld.hint_vcc(bld.def(bld.lm)),
9158                               get_arg(ctx, ctx->args->ac.prim_mask), Operand(0u));
9159
9160       if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena)) {
9161          Temp new_coord[2];
9162          for (unsigned i = 0; i < 2; i++) {
9163             Temp persp_centroid = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.persp_centroid), i, v1);
9164             Temp persp_center = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.persp_center), i, v1);
9165             new_coord[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
9166                                     persp_centroid, persp_center, sel);
9167          }
9168          ctx->persp_centroid = bld.tmp(v2);
9169          bld.pseudo(aco_opcode::p_create_vector, Definition(ctx->persp_centroid),
9170                     Operand(new_coord[0]), Operand(new_coord[1]));
9171          emit_split_vector(ctx, ctx->persp_centroid, 2);
9172       }
9173
9174       if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena)) {
9175          Temp new_coord[2];
9176          for (unsigned i = 0; i < 2; i++) {
9177             Temp linear_centroid = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.linear_centroid), i, v1);
9178             Temp linear_center = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.linear_center), i, v1);
9179             new_coord[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
9180                                     linear_centroid, linear_center, sel);
9181          }
9182          ctx->linear_centroid = bld.tmp(v2);
9183          bld.pseudo(aco_opcode::p_create_vector, Definition(ctx->linear_centroid),
9184                     Operand(new_coord[0]), Operand(new_coord[1]));
9185          emit_split_vector(ctx, ctx->linear_centroid, 2);
9186       }
9187    }
9188 }
9189
9190 void setup_fp_mode(isel_context *ctx, nir_shader *shader)
9191 {
9192    Program *program = ctx->program;
9193
9194    unsigned float_controls = shader->info.float_controls_execution_mode;
9195
9196    program->next_fp_mode.preserve_signed_zero_inf_nan32 =
9197       float_controls & FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32;
9198    program->next_fp_mode.preserve_signed_zero_inf_nan16_64 =
9199       float_controls & (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16 |
9200                         FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64);
9201
9202    program->next_fp_mode.must_flush_denorms32 =
9203       float_controls & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32;
9204    program->next_fp_mode.must_flush_denorms16_64 =
9205       float_controls & (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16 |
9206                         FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64);
9207
9208    program->next_fp_mode.care_about_round32 =
9209       float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32 | FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32);
9210
9211    program->next_fp_mode.care_about_round16_64 =
9212       float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64 |
9213                         FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64);
9214
9215    /* default to preserving fp16 and fp64 denorms, since it's free */
9216    if (program->next_fp_mode.must_flush_denorms16_64)
9217       program->next_fp_mode.denorm16_64 = 0;
9218    else
9219       program->next_fp_mode.denorm16_64 = fp_denorm_keep;
9220
9221    /* preserving fp32 denorms is expensive, so only do it if asked */
9222    if (float_controls & FLOAT_CONTROLS_DENORM_PRESERVE_FP32)
9223       program->next_fp_mode.denorm32 = fp_denorm_keep;
9224    else
9225       program->next_fp_mode.denorm32 = 0;
9226
9227    if (float_controls & FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32)
9228       program->next_fp_mode.round32 = fp_round_tz;
9229    else
9230       program->next_fp_mode.round32 = fp_round_ne;
9231
9232    if (float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64))
9233       program->next_fp_mode.round16_64 = fp_round_tz;
9234    else
9235       program->next_fp_mode.round16_64 = fp_round_ne;
9236
9237    ctx->block->fp_mode = program->next_fp_mode;
9238 }
9239
9240 void cleanup_cfg(Program *program)
9241 {
9242    /* create linear_succs/logical_succs */
9243    for (Block& BB : program->blocks) {
9244       for (unsigned idx : BB.linear_preds)
9245          program->blocks[idx].linear_succs.emplace_back(BB.index);
9246       for (unsigned idx : BB.logical_preds)
9247          program->blocks[idx].logical_succs.emplace_back(BB.index);
9248    }
9249 }
9250
9251 void select_program(Program *program,
9252                     unsigned shader_count,
9253                     struct nir_shader *const *shaders,
9254                     ac_shader_config* config,
9255                     struct radv_shader_args *args)
9256 {
9257    isel_context ctx = setup_isel_context(program, shader_count, shaders, config, args, false);
9258
9259    for (unsigned i = 0; i < shader_count; i++) {
9260       nir_shader *nir = shaders[i];
9261       init_context(&ctx, nir);
9262
9263       setup_fp_mode(&ctx, nir);
9264
9265       if (!i) {
9266          /* needs to be after init_context() for FS */
9267          Pseudo_instruction *startpgm = add_startpgm(&ctx);
9268          append_logical_start(ctx.block);
9269          split_arguments(&ctx, startpgm);
9270       }
9271
9272       if_context ic;
9273       if (shader_count >= 2) {
9274          Builder bld(ctx.program, ctx.block);
9275          Temp count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), get_arg(&ctx, args->merged_wave_info), Operand((8u << 16) | (i * 8u)));
9276          Temp thread_id = emit_mbcnt(&ctx, bld.def(v1));
9277          Temp cond = bld.vopc(aco_opcode::v_cmp_gt_u32, bld.hint_vcc(bld.def(bld.lm)), count, thread_id);
9278
9279          begin_divergent_if_then(&ctx, &ic, cond);
9280       }
9281
9282       if (i) {
9283          Builder bld(ctx.program, ctx.block);
9284
9285          bld.barrier(aco_opcode::p_memory_barrier_shared);
9286          bld.sopp(aco_opcode::s_barrier);
9287
9288          if (ctx.stage == vertex_geometry_gs) {
9289             ctx.gs_wave_id = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1, m0), bld.def(s1, scc), get_arg(&ctx, args->merged_wave_info), Operand((8u << 16) | 16u));
9290          }
9291       } else if (ctx.stage == geometry_gs)
9292          ctx.gs_wave_id = get_arg(&ctx, args->gs_wave_id);
9293
9294       if (ctx.stage == fragment_fs)
9295          handle_bc_optimize(&ctx);
9296
9297       nir_function_impl *func = nir_shader_get_entrypoint(nir);
9298       visit_cf_list(&ctx, &func->body);
9299
9300       if (ctx.program->info->so.num_outputs && ctx.stage == vertex_vs)
9301          emit_streamout(&ctx, 0);
9302
9303       if (ctx.stage == vertex_vs) {
9304          create_vs_exports(&ctx);
9305       } else if (nir->info.stage == MESA_SHADER_GEOMETRY) {
9306          Builder bld(ctx.program, ctx.block);
9307          bld.barrier(aco_opcode::p_memory_barrier_gs_data);
9308          bld.sopp(aco_opcode::s_sendmsg, bld.m0(ctx.gs_wave_id), -1, sendmsg_gs_done(false, false, 0));
9309       }
9310
9311       if (ctx.stage == fragment_fs)
9312          create_fs_exports(&ctx);
9313
9314       if (shader_count >= 2) {
9315          begin_divergent_if_else(&ctx, &ic);
9316          end_divergent_if(&ctx, &ic);
9317       }
9318
9319       ralloc_free(ctx.divergent_vals);
9320    }
9321
9322    program->config->float_mode = program->blocks[0].fp_mode.val;
9323
9324    append_logical_end(ctx.block);
9325    ctx.block->kind |= block_kind_uniform | block_kind_export_end;
9326    Builder bld(ctx.program, ctx.block);
9327    if (ctx.program->wb_smem_l1_on_end)
9328       bld.smem(aco_opcode::s_dcache_wb, false);
9329    bld.sopp(aco_opcode::s_endpgm);
9330
9331    cleanup_cfg(program);
9332 }
9333
9334 void select_gs_copy_shader(Program *program, struct nir_shader *gs_shader,
9335                            ac_shader_config* config,
9336                            struct radv_shader_args *args)
9337 {
9338    isel_context ctx = setup_isel_context(program, 1, &gs_shader, config, args, true);
9339
9340    program->next_fp_mode.preserve_signed_zero_inf_nan32 = false;
9341    program->next_fp_mode.preserve_signed_zero_inf_nan16_64 = false;
9342    program->next_fp_mode.must_flush_denorms32 = false;
9343    program->next_fp_mode.must_flush_denorms16_64 = false;
9344    program->next_fp_mode.care_about_round32 = false;
9345    program->next_fp_mode.care_about_round16_64 = false;
9346    program->next_fp_mode.denorm16_64 = fp_denorm_keep;
9347    program->next_fp_mode.denorm32 = 0;
9348    program->next_fp_mode.round32 = fp_round_ne;
9349    program->next_fp_mode.round16_64 = fp_round_ne;
9350    ctx.block->fp_mode = program->next_fp_mode;
9351
9352    add_startpgm(&ctx);
9353    append_logical_start(ctx.block);
9354
9355    Builder bld(ctx.program, ctx.block);
9356
9357    Temp gsvs_ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), program->private_segment_buffer, Operand(RING_GSVS_VS * 16u));
9358
9359    Operand stream_id(0u);
9360    if (args->shader_info->so.num_outputs)
9361       stream_id = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
9362                            get_arg(&ctx, ctx.args->streamout_config), Operand(0x20018u));
9363
9364    Temp vtx_offset = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), get_arg(&ctx, ctx.args->ac.vertex_id));
9365
9366    std::stack<Block> endif_blocks;
9367
9368    for (unsigned stream = 0; stream < 4; stream++) {
9369       if (stream_id.isConstant() && stream != stream_id.constantValue())
9370          continue;
9371
9372       unsigned num_components = args->shader_info->gs.num_stream_output_components[stream];
9373       if (stream > 0 && (!num_components || !args->shader_info->so.num_outputs))
9374          continue;
9375
9376       memset(ctx.outputs.mask, 0, sizeof(ctx.outputs.mask));
9377
9378       unsigned BB_if_idx = ctx.block->index;
9379       Block BB_endif = Block();
9380       if (!stream_id.isConstant()) {
9381          /* begin IF */
9382          Temp cond = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), stream_id, Operand(stream));
9383          append_logical_end(ctx.block);
9384          ctx.block->kind |= block_kind_uniform;
9385          bld.branch(aco_opcode::p_cbranch_z, cond);
9386
9387          BB_endif.kind |= ctx.block->kind & block_kind_top_level;
9388
9389          ctx.block = ctx.program->create_and_insert_block();
9390          add_edge(BB_if_idx, ctx.block);
9391          bld.reset(ctx.block);
9392          append_logical_start(ctx.block);
9393       }
9394
9395       unsigned offset = 0;
9396       for (unsigned i = 0; i <= VARYING_SLOT_VAR31; ++i) {
9397          if (args->shader_info->gs.output_streams[i] != stream)
9398             continue;
9399
9400          unsigned output_usage_mask = args->shader_info->gs.output_usage_mask[i];
9401          unsigned length = util_last_bit(output_usage_mask);
9402          for (unsigned j = 0; j < length; ++j) {
9403             if (!(output_usage_mask & (1 << j)))
9404                continue;
9405
9406             unsigned const_offset = offset * args->shader_info->gs.vertices_out * 16 * 4;
9407             Temp voffset = vtx_offset;
9408             if (const_offset >= 4096u) {
9409                voffset = bld.vadd32(bld.def(v1), Operand(const_offset / 4096u * 4096u), voffset);
9410                const_offset %= 4096u;
9411             }
9412
9413             aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(aco_opcode::buffer_load_dword, Format::MUBUF, 3, 1)};
9414             mubuf->definitions[0] = bld.def(v1);
9415             mubuf->operands[0] = Operand(gsvs_ring);
9416             mubuf->operands[1] = Operand(voffset);
9417             mubuf->operands[2] = Operand(0u);
9418             mubuf->offen = true;
9419             mubuf->offset = const_offset;
9420             mubuf->glc = true;
9421             mubuf->slc = true;
9422             mubuf->dlc = args->options->chip_class >= GFX10;
9423             mubuf->barrier = barrier_none;
9424             mubuf->can_reorder = true;
9425
9426             ctx.outputs.mask[i] |= 1 << j;
9427             ctx.outputs.outputs[i][j] = mubuf->definitions[0].getTemp();
9428
9429             bld.insert(std::move(mubuf));
9430
9431             offset++;
9432          }
9433       }
9434
9435       if (args->shader_info->so.num_outputs) {
9436          emit_streamout(&ctx, stream);
9437          bld.reset(ctx.block);
9438       }
9439
9440       if (stream == 0) {
9441          create_vs_exports(&ctx);
9442          ctx.block->kind |= block_kind_export_end;
9443       }
9444
9445       if (!stream_id.isConstant()) {
9446          append_logical_end(ctx.block);
9447
9448          /* branch from then block to endif block */
9449          bld.branch(aco_opcode::p_branch);
9450          add_edge(ctx.block->index, &BB_endif);
9451          ctx.block->kind |= block_kind_uniform;
9452
9453          /* emit else block */
9454          ctx.block = ctx.program->create_and_insert_block();
9455          add_edge(BB_if_idx, ctx.block);
9456          bld.reset(ctx.block);
9457          append_logical_start(ctx.block);
9458
9459          endif_blocks.push(std::move(BB_endif));
9460       }
9461    }
9462
9463    while (!endif_blocks.empty()) {
9464       Block BB_endif = std::move(endif_blocks.top());
9465       endif_blocks.pop();
9466
9467       Block *BB_else = ctx.block;
9468
9469       append_logical_end(BB_else);
9470       /* branch from else block to endif block */
9471       bld.branch(aco_opcode::p_branch);
9472       add_edge(BB_else->index, &BB_endif);
9473       BB_else->kind |= block_kind_uniform;
9474
9475       /** emit endif merge block */
9476       ctx.block = program->insert_block(std::move(BB_endif));
9477       bld.reset(ctx.block);
9478       append_logical_start(ctx.block);
9479    }
9480
9481    program->config->float_mode = program->blocks[0].fp_mode.val;
9482
9483    append_logical_end(ctx.block);
9484    ctx.block->kind |= block_kind_uniform;
9485    bld.sopp(aco_opcode::s_endpgm);
9486
9487    cleanup_cfg(program);
9488 }
9489 }