src/amd/compiler/aco_instruction_selection.cpp

   1 /*
   2  * Copyright © 2018 Valve Corporation
   3  * Copyright © 2018 Google
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <algorithm>
  27 #include <array>
  28 #include <stack>
  29 #include <map>
  30
  31 #include "ac_shader_util.h"
  32 #include "aco_ir.h"
  33 #include "aco_builder.h"
  34 #include "aco_interface.h"
  35 #include "aco_instruction_selection_setup.cpp"
  36 #include "util/fast_idiv_by_const.h"
  37
  38 namespace aco {
  39 namespace {
  40
  41 class loop_info_RAII {
  42    isel_context* ctx;
  43    unsigned header_idx_old;
  44    Block* exit_old;
  45    bool divergent_cont_old;
  46    bool divergent_branch_old;
  47    bool divergent_if_old;
  48
  49 public:
  50    loop_info_RAII(isel_context* ctx, unsigned loop_header_idx, Block* loop_exit)
  51       : ctx(ctx),
  52         header_idx_old(ctx->cf_info.parent_loop.header_idx), exit_old(ctx->cf_info.parent_loop.exit),
  53         divergent_cont_old(ctx->cf_info.parent_loop.has_divergent_continue),
  54         divergent_branch_old(ctx->cf_info.parent_loop.has_divergent_branch),
  55         divergent_if_old(ctx->cf_info.parent_if.is_divergent)
  56    {
  57       ctx->cf_info.parent_loop.header_idx = loop_header_idx;
  58       ctx->cf_info.parent_loop.exit = loop_exit;
  59       ctx->cf_info.parent_loop.has_divergent_continue = false;
  60       ctx->cf_info.parent_loop.has_divergent_branch = false;
  61       ctx->cf_info.parent_if.is_divergent = false;
  62       ctx->cf_info.loop_nest_depth = ctx->cf_info.loop_nest_depth + 1;
  63    }
  64
  65    ~loop_info_RAII()
  66    {
  67       ctx->cf_info.parent_loop.header_idx = header_idx_old;
  68       ctx->cf_info.parent_loop.exit = exit_old;
  69       ctx->cf_info.parent_loop.has_divergent_continue = divergent_cont_old;
  70       ctx->cf_info.parent_loop.has_divergent_branch = divergent_branch_old;
  71       ctx->cf_info.parent_if.is_divergent = divergent_if_old;
  72       ctx->cf_info.loop_nest_depth = ctx->cf_info.loop_nest_depth - 1;
  73       if (!ctx->cf_info.loop_nest_depth && !ctx->cf_info.parent_if.is_divergent)
  74          ctx->cf_info.exec_potentially_empty_discard = false;
  75    }
  76 };
  77
  78 struct if_context {
  79    Temp cond;
  80
  81    bool divergent_old;
  82    bool exec_potentially_empty_discard_old;
  83    bool exec_potentially_empty_break_old;
  84    uint16_t exec_potentially_empty_break_depth_old;
  85
  86    unsigned BB_if_idx;
  87    unsigned invert_idx;
  88    bool then_branch_divergent;
  89    Block BB_invert;
  90    Block BB_endif;
  91 };
  92
  93 static bool visit_cf_list(struct isel_context *ctx,
  94                           struct exec_list *list);
  95
  96 static void add_logical_edge(unsigned pred_idx, Block *succ)
  97 {
  98    succ->logical_preds.emplace_back(pred_idx);
  99 }
 100
 101
 102 static void add_linear_edge(unsigned pred_idx, Block *succ)
 103 {
 104    succ->linear_preds.emplace_back(pred_idx);
 105 }
 106
 107 static void add_edge(unsigned pred_idx, Block *succ)
 108 {
 109    add_logical_edge(pred_idx, succ);
 110    add_linear_edge(pred_idx, succ);
 111 }
 112
 113 static void append_logical_start(Block *b)
 114 {
 115    Builder(NULL, b).pseudo(aco_opcode::p_logical_start);
 116 }
 117
 118 static void append_logical_end(Block *b)
 119 {
 120    Builder(NULL, b).pseudo(aco_opcode::p_logical_end);
 121 }
 122
 123 Temp get_ssa_temp(struct isel_context *ctx, nir_ssa_def *def)
 124 {
 125    assert(ctx->allocated[def->index].id());
 126    return ctx->allocated[def->index];
 127 }
 128
 129 Temp emit_mbcnt(isel_context *ctx, Definition dst,
 130                 Operand mask_lo = Operand((uint32_t) -1), Operand mask_hi = Operand((uint32_t) -1))
 131 {
 132    Builder bld(ctx->program, ctx->block);
 133    Definition lo_def = ctx->program->wave_size == 32 ? dst : bld.def(v1);
 134    Temp thread_id_lo = bld.vop3(aco_opcode::v_mbcnt_lo_u32_b32, lo_def, mask_lo, Operand(0u));
 135
 136    if (ctx->program->wave_size == 32) {
 137       return thread_id_lo;
 138    } else {
 139       Temp thread_id_hi = bld.vop3(aco_opcode::v_mbcnt_hi_u32_b32, dst, mask_hi, thread_id_lo);
 140       return thread_id_hi;
 141    }
 142 }
 143
 144 Temp emit_wqm(isel_context *ctx, Temp src, Temp dst=Temp(0, s1), bool program_needs_wqm = false)
 145 {
 146    Builder bld(ctx->program, ctx->block);
 147
 148    if (!dst.id())
 149       dst = bld.tmp(src.regClass());
 150
 151    assert(src.size() == dst.size());
 152
 153    if (ctx->stage != fragment_fs) {
 154       if (!dst.id())
 155          return src;
 156
 157       bld.copy(Definition(dst), src);
 158       return dst;
 159    }
 160
 161    bld.pseudo(aco_opcode::p_wqm, Definition(dst), src);
 162    ctx->program->needs_wqm |= program_needs_wqm;
 163    return dst;
 164 }
 165
 166 static Temp emit_bpermute(isel_context *ctx, Builder &bld, Temp index, Temp data)
 167 {
 168    if (index.regClass() == s1)
 169       return bld.readlane(bld.def(s1), data, index);
 170
 171    Temp index_x4 = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), index);
 172
 173    /* Currently not implemented on GFX6-7 */
 174    assert(ctx->options->chip_class >= GFX8);
 175
 176    if (ctx->options->chip_class <= GFX9 || ctx->program->wave_size == 32) {
 177       return bld.ds(aco_opcode::ds_bpermute_b32, bld.def(v1), index_x4, data);
 178    }
 179
 180    /* GFX10, wave64 mode:
 181     * The bpermute instruction is limited to half-wave operation, which means that it can't
 182     * properly support subgroup shuffle like older generations (or wave32 mode), so we
 183     * emulate it here.
 184     */
 185    if (!ctx->has_gfx10_wave64_bpermute) {
 186       ctx->has_gfx10_wave64_bpermute = true;
 187       ctx->program->config->num_shared_vgprs = 8; /* Shared VGPRs are allocated in groups of 8 */
 188       ctx->program->vgpr_limit -= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
 189    }
 190
 191    Temp lane_id = emit_mbcnt(ctx, bld.def(v1));
 192    Temp lane_is_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x20u), lane_id);
 193    Temp index_is_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x20u), index);
 194    Temp cmp = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm, vcc), lane_is_hi, index_is_hi);
 195
 196    return bld.reduction(aco_opcode::p_wave64_bpermute, bld.def(v1), bld.def(s2), bld.def(s1, scc),
 197                         bld.vcc(cmp), Operand(v2.as_linear()), index_x4, data, gfx10_wave64_bpermute);
 198 }
 199
 200 Temp as_vgpr(isel_context *ctx, Temp val)
 201 {
 202    if (val.type() == RegType::sgpr) {
 203       Builder bld(ctx->program, ctx->block);
 204       return bld.copy(bld.def(RegType::vgpr, val.size()), val);
 205    }
 206    assert(val.type() == RegType::vgpr);
 207    return val;
 208 }
 209
 210 //assumes a != 0xffffffff
 211 void emit_v_div_u32(isel_context *ctx, Temp dst, Temp a, uint32_t b)
 212 {
 213    assert(b != 0);
 214    Builder bld(ctx->program, ctx->block);
 215
 216    if (util_is_power_of_two_or_zero(b)) {
 217       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(dst), Operand((uint32_t)util_logbase2(b)), a);
 218       return;
 219    }
 220
 221    util_fast_udiv_info info = util_compute_fast_udiv_info(b, 32, 32);
 222
 223    assert(info.multiplier <= 0xffffffff);
 224
 225    bool pre_shift = info.pre_shift != 0;
 226    bool increment = info.increment != 0;
 227    bool multiply = true;
 228    bool post_shift = info.post_shift != 0;
 229
 230    if (!pre_shift && !increment && !multiply && !post_shift) {
 231       bld.vop1(aco_opcode::v_mov_b32, Definition(dst), a);
 232       return;
 233    }
 234
 235    Temp pre_shift_dst = a;
 236    if (pre_shift) {
 237       pre_shift_dst = (increment || multiply || post_shift) ? bld.tmp(v1) : dst;
 238       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(pre_shift_dst), Operand((uint32_t)info.pre_shift), a);
 239    }
 240
 241    Temp increment_dst = pre_shift_dst;
 242    if (increment) {
 243       increment_dst = (post_shift || multiply) ? bld.tmp(v1) : dst;
 244       bld.vadd32(Definition(increment_dst), Operand((uint32_t) info.increment), pre_shift_dst);
 245    }
 246
 247    Temp multiply_dst = increment_dst;
 248    if (multiply) {
 249       multiply_dst = post_shift ? bld.tmp(v1) : dst;
 250       bld.vop3(aco_opcode::v_mul_hi_u32, Definition(multiply_dst), increment_dst,
 251                bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand((uint32_t)info.multiplier)));
 252    }
 253
 254    if (post_shift) {
 255       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(dst), Operand((uint32_t)info.post_shift), multiply_dst);
 256    }
 257 }
 258
 259 void emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, Temp dst)
 260 {
 261    Builder bld(ctx->program, ctx->block);
 262    bld.pseudo(aco_opcode::p_extract_vector, Definition(dst), src, Operand(idx));
 263 }
 264
 265
 266 Temp emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, RegClass dst_rc)
 267 {
 268    /* no need to extract the whole vector */
 269    if (src.regClass() == dst_rc) {
 270       assert(idx == 0);
 271       return src;
 272    }
 273    assert(src.size() > idx);
 274    Builder bld(ctx->program, ctx->block);
 275    auto it = ctx->allocated_vec.find(src.id());
 276    /* the size check needs to be early because elements other than 0 may be garbage */
 277    if (it != ctx->allocated_vec.end() && it->second[0].size() == dst_rc.size()) {
 278       if (it->second[idx].regClass() == dst_rc) {
 279          return it->second[idx];
 280       } else {
 281          assert(dst_rc.size() == it->second[idx].regClass().size());
 282          assert(dst_rc.type() == RegType::vgpr && it->second[idx].type() == RegType::sgpr);
 283          return bld.copy(bld.def(dst_rc), it->second[idx]);
 284       }
 285    }
 286
 287    if (src.size() == dst_rc.size()) {
 288       assert(idx == 0);
 289       return bld.copy(bld.def(dst_rc), src);
 290    } else {
 291       Temp dst = bld.tmp(dst_rc);
 292       emit_extract_vector(ctx, src, idx, dst);
 293       return dst;
 294    }
 295 }
 296
 297 void emit_split_vector(isel_context* ctx, Temp vec_src, unsigned num_components)
 298 {
 299    if (num_components == 1)
 300       return;
 301    if (ctx->allocated_vec.find(vec_src.id()) != ctx->allocated_vec.end())
 302       return;
 303    aco_ptr<Pseudo_instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector, Format::PSEUDO, 1, num_components)};
 304    split->operands[0] = Operand(vec_src);
 305    std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 306    for (unsigned i = 0; i < num_components; i++) {
 307       elems[i] = {ctx->program->allocateId(), RegClass(vec_src.type(), vec_src.size() / num_components)};
 308       split->definitions[i] = Definition(elems[i]);
 309    }
 310    ctx->block->instructions.emplace_back(std::move(split));
 311    ctx->allocated_vec.emplace(vec_src.id(), elems);
 312 }
 313
 314 /* This vector expansion uses a mask to determine which elements in the new vector
 315  * come from the original vector. The other elements are undefined. */
 316 void expand_vector(isel_context* ctx, Temp vec_src, Temp dst, unsigned num_components, unsigned mask)
 317 {
 318    emit_split_vector(ctx, vec_src, util_bitcount(mask));
 319
 320    if (vec_src == dst)
 321       return;
 322
 323    Builder bld(ctx->program, ctx->block);
 324    if (num_components == 1) {
 325       if (dst.type() == RegType::sgpr)
 326          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec_src);
 327       else
 328          bld.copy(Definition(dst), vec_src);
 329       return;
 330    }
 331
 332    unsigned component_size = dst.size() / num_components;
 333    std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 334
 335    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1)};
 336    vec->definitions[0] = Definition(dst);
 337    unsigned k = 0;
 338    for (unsigned i = 0; i < num_components; i++) {
 339       if (mask & (1 << i)) {
 340          Temp src = emit_extract_vector(ctx, vec_src, k++, RegClass(vec_src.type(), component_size));
 341          if (dst.type() == RegType::sgpr)
 342             src = bld.as_uniform(src);
 343          vec->operands[i] = Operand(src);
 344       } else {
 345          vec->operands[i] = Operand(0u);
 346       }
 347       elems[i] = vec->operands[i].getTemp();
 348    }
 349    ctx->block->instructions.emplace_back(std::move(vec));
 350    ctx->allocated_vec.emplace(dst.id(), elems);
 351 }
 352
 353 Temp bool_to_vector_condition(isel_context *ctx, Temp val, Temp dst = Temp(0, s2))
 354 {
 355    Builder bld(ctx->program, ctx->block);
 356    if (!dst.id())
 357       dst = bld.tmp(bld.lm);
 358
 359    assert(val.regClass() == s1);
 360    assert(dst.regClass() == bld.lm);
 361
 362    return bld.sop2(Builder::s_cselect, Definition(dst), Operand((uint32_t) -1), Operand(0u), bld.scc(val));
 363 }
 364
 365 Temp bool_to_scalar_condition(isel_context *ctx, Temp val, Temp dst = Temp(0, s1))
 366 {
 367    Builder bld(ctx->program, ctx->block);
 368    if (!dst.id())
 369       dst = bld.tmp(s1);
 370
 371    assert(val.regClass() == bld.lm);
 372    assert(dst.regClass() == s1);
 373
 374    /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
 375    Temp tmp = bld.tmp(s1);
 376    bld.sop2(Builder::s_and, bld.def(bld.lm), bld.scc(Definition(tmp)), val, Operand(exec, bld.lm));
 377    return emit_wqm(ctx, tmp, dst);
 378 }
 379
 380 Temp get_alu_src(struct isel_context *ctx, nir_alu_src src, unsigned size=1)
 381 {
 382    if (src.src.ssa->num_components == 1 && src.swizzle[0] == 0 && size == 1)
 383       return get_ssa_temp(ctx, src.src.ssa);
 384
 385    if (src.src.ssa->num_components == size) {
 386       bool identity_swizzle = true;
 387       for (unsigned i = 0; identity_swizzle && i < size; i++) {
 388          if (src.swizzle[i] != i)
 389             identity_swizzle = false;
 390       }
 391       if (identity_swizzle)
 392          return get_ssa_temp(ctx, src.src.ssa);
 393    }
 394
 395    Temp vec = get_ssa_temp(ctx, src.src.ssa);
 396    unsigned elem_size = vec.size() / src.src.ssa->num_components;
 397    assert(elem_size > 0); /* TODO: 8 and 16-bit vectors not supported */
 398    assert(vec.size() % elem_size == 0);
 399
 400    RegClass elem_rc = RegClass(vec.type(), elem_size);
 401    if (size == 1) {
 402       return emit_extract_vector(ctx, vec, src.swizzle[0], elem_rc);
 403    } else {
 404       assert(size <= 4);
 405       std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 406       aco_ptr<Pseudo_instruction> vec_instr{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, size, 1)};
 407       for (unsigned i = 0; i < size; ++i) {
 408          elems[i] = emit_extract_vector(ctx, vec, src.swizzle[i], elem_rc);
 409          vec_instr->operands[i] = Operand{elems[i]};
 410       }
 411       Temp dst{ctx->program->allocateId(), RegClass(vec.type(), elem_size * size)};
 412       vec_instr->definitions[0] = Definition(dst);
 413       ctx->block->instructions.emplace_back(std::move(vec_instr));
 414       ctx->allocated_vec.emplace(dst.id(), elems);
 415       return dst;
 416    }
 417 }
 418
 419 Temp convert_pointer_to_64_bit(isel_context *ctx, Temp ptr)
 420 {
 421    if (ptr.size() == 2)
 422       return ptr;
 423    Builder bld(ctx->program, ctx->block);
 424    if (ptr.type() == RegType::vgpr)
 425       ptr = bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), ptr);
 426    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s2),
 427                      ptr, Operand((unsigned)ctx->options->address32_hi));
 428 }
 429
 430 void emit_sop2_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst, bool writes_scc)
 431 {
 432    aco_ptr<SOP2_instruction> sop2{create_instruction<SOP2_instruction>(op, Format::SOP2, 2, writes_scc ? 2 : 1)};
 433    sop2->operands[0] = Operand(get_alu_src(ctx, instr->src[0]));
 434    sop2->operands[1] = Operand(get_alu_src(ctx, instr->src[1]));
 435    sop2->definitions[0] = Definition(dst);
 436    if (writes_scc)
 437       sop2->definitions[1] = Definition(ctx->program->allocateId(), scc, s1);
 438    ctx->block->instructions.emplace_back(std::move(sop2));
 439 }
 440
 441 void emit_vop2_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst,
 442                            bool commutative, bool swap_srcs=false, bool flush_denorms = false)
 443 {
 444    Builder bld(ctx->program, ctx->block);
 445    Temp src0 = get_alu_src(ctx, instr->src[swap_srcs ? 1 : 0]);
 446    Temp src1 = get_alu_src(ctx, instr->src[swap_srcs ? 0 : 1]);
 447    if (src1.type() == RegType::sgpr) {
 448       if (commutative && src0.type() == RegType::vgpr) {
 449          Temp t = src0;
 450          src0 = src1;
 451          src1 = t;
 452       } else if (src0.type() == RegType::vgpr &&
 453                  op != aco_opcode::v_madmk_f32 &&
 454                  op != aco_opcode::v_madak_f32 &&
 455                  op != aco_opcode::v_madmk_f16 &&
 456                  op != aco_opcode::v_madak_f16) {
 457          /* If the instruction is not commutative, we emit a VOP3A instruction */
 458          bld.vop2_e64(op, Definition(dst), src0, src1);
 459          return;
 460       } else {
 461          src1 = bld.copy(bld.def(RegType::vgpr, src1.size()), src1); //TODO: as_vgpr
 462       }
 463    }
 464
 465    if (flush_denorms && ctx->program->chip_class < GFX9) {
 466       assert(dst.size() == 1);
 467       Temp tmp = bld.vop2(op, bld.def(v1), src0, src1);
 468       bld.vop2(aco_opcode::v_mul_f32, Definition(dst), Operand(0x3f800000u), tmp);
 469    } else {
 470       bld.vop2(op, Definition(dst), src0, src1);
 471    }
 472 }
 473
 474 void emit_vop3a_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst,
 475                             bool flush_denorms = false)
 476 {
 477    Temp src0 = get_alu_src(ctx, instr->src[0]);
 478    Temp src1 = get_alu_src(ctx, instr->src[1]);
 479    Temp src2 = get_alu_src(ctx, instr->src[2]);
 480
 481    /* ensure that the instruction has at most 1 sgpr operand
 482     * The optimizer will inline constants for us */
 483    if (src0.type() == RegType::sgpr && src1.type() == RegType::sgpr)
 484       src0 = as_vgpr(ctx, src0);
 485    if (src1.type() == RegType::sgpr && src2.type() == RegType::sgpr)
 486       src1 = as_vgpr(ctx, src1);
 487    if (src2.type() == RegType::sgpr && src0.type() == RegType::sgpr)
 488       src2 = as_vgpr(ctx, src2);
 489
 490    Builder bld(ctx->program, ctx->block);
 491    if (flush_denorms && ctx->program->chip_class < GFX9) {
 492       assert(dst.size() == 1);
 493       Temp tmp = bld.vop3(op, Definition(dst), src0, src1, src2);
 494       bld.vop2(aco_opcode::v_mul_f32, Definition(dst), Operand(0x3f800000u), tmp);
 495    } else {
 496       bld.vop3(op, Definition(dst), src0, src1, src2);
 497    }
 498 }
 499
 500 void emit_vop1_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 501 {
 502    Builder bld(ctx->program, ctx->block);
 503    bld.vop1(op, Definition(dst), get_alu_src(ctx, instr->src[0]));
 504 }
 505
 506 void emit_vopc_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 507 {
 508    Temp src0 = get_alu_src(ctx, instr->src[0]);
 509    Temp src1 = get_alu_src(ctx, instr->src[1]);
 510    assert(src0.size() == src1.size());
 511
 512    aco_ptr<Instruction> vopc;
 513    if (src1.type() == RegType::sgpr) {
 514       if (src0.type() == RegType::vgpr) {
 515          /* to swap the operands, we might also have to change the opcode */
 516          switch (op) {
 517             case aco_opcode::v_cmp_lt_f32:
 518                op = aco_opcode::v_cmp_gt_f32;
 519                break;
 520             case aco_opcode::v_cmp_ge_f32:
 521                op = aco_opcode::v_cmp_le_f32;
 522                break;
 523             case aco_opcode::v_cmp_lt_i32:
 524                op = aco_opcode::v_cmp_gt_i32;
 525                break;
 526             case aco_opcode::v_cmp_ge_i32:
 527                op = aco_opcode::v_cmp_le_i32;
 528                break;
 529             case aco_opcode::v_cmp_lt_u32:
 530                op = aco_opcode::v_cmp_gt_u32;
 531                break;
 532             case aco_opcode::v_cmp_ge_u32:
 533                op = aco_opcode::v_cmp_le_u32;
 534                break;
 535             case aco_opcode::v_cmp_lt_f64:
 536                op = aco_opcode::v_cmp_gt_f64;
 537                break;
 538             case aco_opcode::v_cmp_ge_f64:
 539                op = aco_opcode::v_cmp_le_f64;
 540                break;
 541             case aco_opcode::v_cmp_lt_i64:
 542                op = aco_opcode::v_cmp_gt_i64;
 543                break;
 544             case aco_opcode::v_cmp_ge_i64:
 545                op = aco_opcode::v_cmp_le_i64;
 546                break;
 547             case aco_opcode::v_cmp_lt_u64:
 548                op = aco_opcode::v_cmp_gt_u64;
 549                break;
 550             case aco_opcode::v_cmp_ge_u64:
 551                op = aco_opcode::v_cmp_le_u64;
 552                break;
 553             default: /* eq and ne are commutative */
 554                break;
 555          }
 556          Temp t = src0;
 557          src0 = src1;
 558          src1 = t;
 559       } else {
 560          src1 = as_vgpr(ctx, src1);
 561       }
 562    }
 563
 564    Builder bld(ctx->program, ctx->block);
 565    bld.vopc(op, bld.hint_vcc(Definition(dst)), src0, src1);
 566 }
 567
 568 void emit_sopc_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 569 {
 570    Temp src0 = get_alu_src(ctx, instr->src[0]);
 571    Temp src1 = get_alu_src(ctx, instr->src[1]);
 572    Builder bld(ctx->program, ctx->block);
 573
 574    assert(dst.regClass() == bld.lm);
 575    assert(src0.type() == RegType::sgpr);
 576    assert(src1.type() == RegType::sgpr);
 577    assert(src0.regClass() == src1.regClass());
 578
 579    /* Emit the SALU comparison instruction */
 580    Temp cmp = bld.sopc(op, bld.scc(bld.def(s1)), src0, src1);
 581    /* Turn the result into a per-lane bool */
 582    bool_to_vector_condition(ctx, cmp, dst);
 583 }
 584
 585 void emit_comparison(isel_context *ctx, nir_alu_instr *instr, Temp dst,
 586                      aco_opcode v32_op, aco_opcode v64_op, aco_opcode s32_op = aco_opcode::num_opcodes, aco_opcode s64_op = aco_opcode::num_opcodes)
 587 {
 588    aco_opcode s_op = instr->src[0].src.ssa->bit_size == 64 ? s64_op : s32_op;
 589    aco_opcode v_op = instr->src[0].src.ssa->bit_size == 64 ? v64_op : v32_op;
 590    bool divergent_vals = ctx->divergent_vals[instr->dest.dest.ssa.index];
 591    bool use_valu = s_op == aco_opcode::num_opcodes ||
 592                    divergent_vals ||
 593                    ctx->allocated[instr->src[0].src.ssa->index].type() == RegType::vgpr ||
 594                    ctx->allocated[instr->src[1].src.ssa->index].type() == RegType::vgpr;
 595    aco_opcode op = use_valu ? v_op : s_op;
 596    assert(op != aco_opcode::num_opcodes);
 597    assert(dst.regClass() == ctx->program->lane_mask);
 598
 599    if (use_valu)
 600       emit_vopc_instruction(ctx, instr, op, dst);
 601    else
 602       emit_sopc_instruction(ctx, instr, op, dst);
 603 }
 604
 605 void emit_boolean_logic(isel_context *ctx, nir_alu_instr *instr, Builder::WaveSpecificOpcode op, Temp dst)
 606 {
 607    Builder bld(ctx->program, ctx->block);
 608    Temp src0 = get_alu_src(ctx, instr->src[0]);
 609    Temp src1 = get_alu_src(ctx, instr->src[1]);
 610
 611    assert(dst.regClass() == bld.lm);
 612    assert(src0.regClass() == bld.lm);
 613    assert(src1.regClass() == bld.lm);
 614
 615    bld.sop2(op, Definition(dst), bld.def(s1, scc), src0, src1);
 616 }
 617
 618 void emit_bcsel(isel_context *ctx, nir_alu_instr *instr, Temp dst)
 619 {
 620    Builder bld(ctx->program, ctx->block);
 621    Temp cond = get_alu_src(ctx, instr->src[0]);
 622    Temp then = get_alu_src(ctx, instr->src[1]);
 623    Temp els = get_alu_src(ctx, instr->src[2]);
 624
 625    assert(cond.regClass() == bld.lm);
 626
 627    if (dst.type() == RegType::vgpr) {
 628       aco_ptr<Instruction> bcsel;
 629       if (dst.size() == 1) {
 630          then = as_vgpr(ctx, then);
 631          els = as_vgpr(ctx, els);
 632
 633          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), els, then, cond);
 634       } else if (dst.size() == 2) {
 635          Temp then_lo = bld.tmp(v1), then_hi = bld.tmp(v1);
 636          bld.pseudo(aco_opcode::p_split_vector, Definition(then_lo), Definition(then_hi), then);
 637          Temp else_lo = bld.tmp(v1), else_hi = bld.tmp(v1);
 638          bld.pseudo(aco_opcode::p_split_vector, Definition(else_lo), Definition(else_hi), els);
 639
 640          Temp dst0 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_lo, then_lo, cond);
 641          Temp dst1 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_hi, then_hi, cond);
 642
 643          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
 644       } else {
 645          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 646          nir_print_instr(&instr->instr, stderr);
 647          fprintf(stderr, "\n");
 648       }
 649       return;
 650    }
 651
 652    if (instr->dest.dest.ssa.bit_size == 1) {
 653       assert(dst.regClass() == bld.lm);
 654       assert(then.regClass() == bld.lm);
 655       assert(els.regClass() == bld.lm);
 656    }
 657
 658    if (!ctx->divergent_vals[instr->src[0].src.ssa->index]) { /* uniform condition and values in sgpr */
 659       if (dst.regClass() == s1 || dst.regClass() == s2) {
 660          assert((then.regClass() == s1 || then.regClass() == s2) && els.regClass() == then.regClass());
 661          assert(dst.size() == then.size());
 662          aco_opcode op = dst.regClass() == s1 ? aco_opcode::s_cselect_b32 : aco_opcode::s_cselect_b64;
 663          bld.sop2(op, Definition(dst), then, els, bld.scc(bool_to_scalar_condition(ctx, cond)));
 664       } else {
 665          fprintf(stderr, "Unimplemented uniform bcsel bit size: ");
 666          nir_print_instr(&instr->instr, stderr);
 667          fprintf(stderr, "\n");
 668       }
 669       return;
 670    }
 671
 672    /* divergent boolean bcsel
 673     * this implements bcsel on bools: dst = s0 ? s1 : s2
 674     * are going to be: dst = (s0 & s1) | (~s0 & s2) */
 675    assert(instr->dest.dest.ssa.bit_size == 1);
 676
 677    if (cond.id() != then.id())
 678       then = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), cond, then);
 679
 680    if (cond.id() == els.id())
 681       bld.sop1(Builder::s_mov, Definition(dst), then);
 682    else
 683       bld.sop2(Builder::s_or, Definition(dst), bld.def(s1, scc), then,
 684                bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), els, cond));
 685 }
 686
 687 void emit_scaled_op(isel_context *ctx, Builder& bld, Definition dst, Temp val,
 688                     aco_opcode op, uint32_t undo)
 689 {
 690    /* multiply by 16777216 to handle denormals */
 691    Temp is_denormal = bld.vopc(aco_opcode::v_cmp_class_f32, bld.hint_vcc(bld.def(bld.lm)),
 692                                as_vgpr(ctx, val), bld.copy(bld.def(v1), Operand((1u << 7) | (1u << 4))));
 693    Temp scaled = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x4b800000u), val);
 694    scaled = bld.vop1(op, bld.def(v1), scaled);
 695    scaled = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(undo), scaled);
 696
 697    Temp not_scaled = bld.vop1(op, bld.def(v1), val);
 698
 699    bld.vop2(aco_opcode::v_cndmask_b32, dst, not_scaled, scaled, is_denormal);
 700 }
 701
 702 void emit_rcp(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 703 {
 704    if (ctx->block->fp_mode.denorm32 == 0) {
 705       bld.vop1(aco_opcode::v_rcp_f32, dst, val);
 706       return;
 707    }
 708
 709    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_rcp_f32, 0x4b800000u);
 710 }
 711
 712 void emit_rsq(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 713 {
 714    if (ctx->block->fp_mode.denorm32 == 0) {
 715       bld.vop1(aco_opcode::v_rsq_f32, dst, val);
 716       return;
 717    }
 718
 719    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_rsq_f32, 0x45800000u);
 720 }
 721
 722 void emit_sqrt(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 723 {
 724    if (ctx->block->fp_mode.denorm32 == 0) {
 725       bld.vop1(aco_opcode::v_sqrt_f32, dst, val);
 726       return;
 727    }
 728
 729    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_sqrt_f32, 0x39800000u);
 730 }
 731
 732 void emit_log2(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 733 {
 734    if (ctx->block->fp_mode.denorm32 == 0) {
 735       bld.vop1(aco_opcode::v_log_f32, dst, val);
 736       return;
 737    }
 738
 739    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_log_f32, 0xc1c00000u);
 740 }
 741
 742 Temp emit_trunc_f64(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 743 {
 744    if (ctx->options->chip_class >= GFX7)
 745       return bld.vop1(aco_opcode::v_trunc_f64, Definition(dst), val);
 746
 747    /* GFX6 doesn't support V_TRUNC_F64, lower it. */
 748    /* TODO: create more efficient code! */
 749    if (val.type() == RegType::sgpr)
 750       val = as_vgpr(ctx, val);
 751
 752    /* Split the input value. */
 753    Temp val_lo = bld.tmp(v1), val_hi = bld.tmp(v1);
 754    bld.pseudo(aco_opcode::p_split_vector, Definition(val_lo), Definition(val_hi), val);
 755
 756    /* Extract the exponent and compute the unbiased value. */
 757    Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f64, bld.def(v1), val);
 758
 759    /* Extract the fractional part. */
 760    Temp fract_mask = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(-1u), Operand(0x000fffffu));
 761    fract_mask = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), fract_mask, exponent);
 762
 763    Temp fract_mask_lo = bld.tmp(v1), fract_mask_hi = bld.tmp(v1);
 764    bld.pseudo(aco_opcode::p_split_vector, Definition(fract_mask_lo), Definition(fract_mask_hi), fract_mask);
 765
 766    Temp fract_lo = bld.tmp(v1), fract_hi = bld.tmp(v1);
 767    Temp tmp = bld.vop1(aco_opcode::v_not_b32, bld.def(v1), fract_mask_lo);
 768    fract_lo = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), val_lo, tmp);
 769    tmp = bld.vop1(aco_opcode::v_not_b32, bld.def(v1), fract_mask_hi);
 770    fract_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), val_hi, tmp);
 771
 772    /* Get the sign bit. */
 773    Temp sign = bld.vop2(aco_opcode::v_ashr_i32, bld.def(v1), Operand(31u), val_hi);
 774
 775    /* Decide the operation to apply depending on the unbiased exponent. */
 776    Temp exp_lt0 = bld.vopc_e64(aco_opcode::v_cmp_lt_i32, bld.hint_vcc(bld.def(bld.lm)), exponent, Operand(0u));
 777    Temp dst_lo = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), fract_lo, bld.copy(bld.def(v1), Operand(0u)), exp_lt0);
 778    Temp dst_hi = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), fract_hi, sign, exp_lt0);
 779    Temp exp_gt51 = bld.vopc_e64(aco_opcode::v_cmp_gt_i32, bld.def(s2), exponent, Operand(51u));
 780    dst_lo = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), dst_lo, val_lo, exp_gt51);
 781    dst_hi = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), dst_hi, val_hi, exp_gt51);
 782
 783    return bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst_lo, dst_hi);
 784 }
 785
 786 Temp emit_floor_f64(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 787 {
 788    if (ctx->options->chip_class >= GFX7)
 789       return bld.vop1(aco_opcode::v_floor_f64, Definition(dst), val);
 790
 791    /* GFX6 doesn't support V_FLOOR_F64, lower it. */
 792    Temp src0 = as_vgpr(ctx, val);
 793
 794    Temp mask = bld.copy(bld.def(s1), Operand(3u)); /* isnan */
 795    Temp min_val = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(-1u), Operand(0x3fefffffu));
 796
 797    Temp isnan = bld.vopc_e64(aco_opcode::v_cmp_class_f64, bld.hint_vcc(bld.def(bld.lm)), src0, mask);
 798    Temp fract = bld.vop1(aco_opcode::v_fract_f64, bld.def(v2), src0);
 799    Temp min = bld.vop3(aco_opcode::v_min_f64, bld.def(v2), fract, min_val);
 800
 801    Temp then_lo = bld.tmp(v1), then_hi = bld.tmp(v1);
 802    bld.pseudo(aco_opcode::p_split_vector, Definition(then_lo), Definition(then_hi), src0);
 803    Temp else_lo = bld.tmp(v1), else_hi = bld.tmp(v1);
 804    bld.pseudo(aco_opcode::p_split_vector, Definition(else_lo), Definition(else_hi), min);
 805
 806    Temp dst0 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_lo, then_lo, isnan);
 807    Temp dst1 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_hi, then_hi, isnan);
 808
 809    Temp v = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), dst0, dst1);
 810
 811    Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst), src0, v);
 812    static_cast<VOP3A_instruction*>(add)->neg[1] = true;
 813
 814    return add->definitions[0].getTemp();
 815 }
 816
 817 void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
 818 {
 819    if (!instr->dest.dest.is_ssa) {
 820       fprintf(stderr, "nir alu dst not in ssa: ");
 821       nir_print_instr(&instr->instr, stderr);
 822       fprintf(stderr, "\n");
 823       abort();
 824    }
 825    Builder bld(ctx->program, ctx->block);
 826    Temp dst = get_ssa_temp(ctx, &instr->dest.dest.ssa);
 827    switch(instr->op) {
 828    case nir_op_vec2:
 829    case nir_op_vec3:
 830    case nir_op_vec4: {
 831       std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 832       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.dest.ssa.num_components, 1)};
 833       for (unsigned i = 0; i < instr->dest.dest.ssa.num_components; ++i) {
 834          elems[i] = get_alu_src(ctx, instr->src[i]);
 835          vec->operands[i] = Operand{elems[i]};
 836       }
 837       vec->definitions[0] = Definition(dst);
 838       ctx->block->instructions.emplace_back(std::move(vec));
 839       ctx->allocated_vec.emplace(dst.id(), elems);
 840       break;
 841    }
 842    case nir_op_mov: {
 843       Temp src = get_alu_src(ctx, instr->src[0]);
 844       aco_ptr<Instruction> mov;
 845       if (dst.type() == RegType::sgpr) {
 846          if (src.type() == RegType::vgpr)
 847             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), src);
 848          else if (src.regClass() == s1)
 849             bld.sop1(aco_opcode::s_mov_b32, Definition(dst), src);
 850          else if (src.regClass() == s2)
 851             bld.sop1(aco_opcode::s_mov_b64, Definition(dst), src);
 852          else
 853             unreachable("wrong src register class for nir_op_imov");
 854       } else if (dst.regClass() == v1) {
 855          bld.vop1(aco_opcode::v_mov_b32, Definition(dst), src);
 856       } else if (dst.regClass() == v2) {
 857          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src);
 858       } else {
 859          nir_print_instr(&instr->instr, stderr);
 860          unreachable("Should have been lowered to scalar.");
 861       }
 862       break;
 863    }
 864    case nir_op_inot: {
 865       Temp src = get_alu_src(ctx, instr->src[0]);
 866       if (instr->dest.dest.ssa.bit_size == 1) {
 867          assert(src.regClass() == bld.lm);
 868          assert(dst.regClass() == bld.lm);
 869          /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
 870          Temp tmp = bld.sop1(Builder::s_not, bld.def(bld.lm), bld.def(s1, scc), src);
 871          bld.sop2(Builder::s_and, Definition(dst), bld.def(s1, scc), tmp, Operand(exec, bld.lm));
 872       } else if (dst.regClass() == v1) {
 873          emit_vop1_instruction(ctx, instr, aco_opcode::v_not_b32, dst);
 874       } else if (dst.type() == RegType::sgpr) {
 875          aco_opcode opcode = dst.size() == 1 ? aco_opcode::s_not_b32 : aco_opcode::s_not_b64;
 876          bld.sop1(opcode, Definition(dst), bld.def(s1, scc), src);
 877       } else {
 878          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 879          nir_print_instr(&instr->instr, stderr);
 880          fprintf(stderr, "\n");
 881       }
 882       break;
 883    }
 884    case nir_op_ineg: {
 885       Temp src = get_alu_src(ctx, instr->src[0]);
 886       if (dst.regClass() == v1) {
 887          bld.vsub32(Definition(dst), Operand(0u), Operand(src));
 888       } else if (dst.regClass() == s1) {
 889          bld.sop2(aco_opcode::s_mul_i32, Definition(dst), Operand((uint32_t) -1), src);
 890       } else if (dst.size() == 2) {
 891          Temp src0 = bld.tmp(dst.type(), 1);
 892          Temp src1 = bld.tmp(dst.type(), 1);
 893          bld.pseudo(aco_opcode::p_split_vector, Definition(src0), Definition(src1), src);
 894
 895          if (dst.regClass() == s2) {
 896             Temp carry = bld.tmp(s1);
 897             Temp dst0 = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(carry)), Operand(0u), src0);
 898             Temp dst1 = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), src1, carry);
 899             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
 900          } else {
 901             Temp lower = bld.tmp(v1);
 902             Temp borrow = bld.vsub32(Definition(lower), Operand(0u), src0, true).def(1).getTemp();
 903             Temp upper = bld.vsub32(bld.def(v1), Operand(0u), src1, false, borrow);
 904             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
 905          }
 906       } else {
 907          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 908          nir_print_instr(&instr->instr, stderr);
 909          fprintf(stderr, "\n");
 910       }
 911       break;
 912    }
 913    case nir_op_iabs: {
 914       if (dst.regClass() == s1) {
 915          bld.sop1(aco_opcode::s_abs_i32, Definition(dst), bld.def(s1, scc), get_alu_src(ctx, instr->src[0]));
 916       } else if (dst.regClass() == v1) {
 917          Temp src = get_alu_src(ctx, instr->src[0]);
 918          bld.vop2(aco_opcode::v_max_i32, Definition(dst), src, bld.vsub32(bld.def(v1), Operand(0u), src));
 919       } else {
 920          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 921          nir_print_instr(&instr->instr, stderr);
 922          fprintf(stderr, "\n");
 923       }
 924       break;
 925    }
 926    case nir_op_isign: {
 927       Temp src = get_alu_src(ctx, instr->src[0]);
 928       if (dst.regClass() == s1) {
 929          Temp tmp = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
 930          Temp gtz = bld.sopc(aco_opcode::s_cmp_gt_i32, bld.def(s1, scc), src, Operand(0u));
 931          bld.sop2(aco_opcode::s_add_i32, Definition(dst), bld.def(s1, scc), gtz, tmp);
 932       } else if (dst.regClass() == s2) {
 933          Temp neg = bld.sop2(aco_opcode::s_ashr_i64, bld.def(s2), bld.def(s1, scc), src, Operand(63u));
 934          Temp neqz;
 935          if (ctx->program->chip_class >= GFX8)
 936             neqz = bld.sopc(aco_opcode::s_cmp_lg_u64, bld.def(s1, scc), src, Operand(0u));
 937          else
 938             neqz = bld.sop2(aco_opcode::s_or_b64, bld.def(s2), bld.def(s1, scc), src, Operand(0u)).def(1).getTemp();
 939          /* SCC gets zero-extended to 64 bit */
 940          bld.sop2(aco_opcode::s_or_b64, Definition(dst), bld.def(s1, scc), neg, bld.scc(neqz));
 941       } else if (dst.regClass() == v1) {
 942          Temp tmp = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
 943          Temp gtz = bld.vopc(aco_opcode::v_cmp_ge_i32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
 944          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(1u), tmp, gtz);
 945       } else if (dst.regClass() == v2) {
 946          Temp upper = emit_extract_vector(ctx, src, 1, v1);
 947          Temp neg = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), upper);
 948          Temp gtz = bld.vopc(aco_opcode::v_cmp_ge_i64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
 949          Temp lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(1u), neg, gtz);
 950          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), neg, gtz);
 951          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
 952       } else {
 953          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 954          nir_print_instr(&instr->instr, stderr);
 955          fprintf(stderr, "\n");
 956       }
 957       break;
 958    }
 959    case nir_op_imax: {
 960       if (dst.regClass() == v1) {
 961          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_i32, dst, true);
 962       } else if (dst.regClass() == s1) {
 963          emit_sop2_instruction(ctx, instr, aco_opcode::s_max_i32, dst, true);
 964       } else {
 965          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 966          nir_print_instr(&instr->instr, stderr);
 967          fprintf(stderr, "\n");
 968       }
 969       break;
 970    }
 971    case nir_op_umax: {
 972       if (dst.regClass() == v1) {
 973          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_u32, dst, true);
 974       } else if (dst.regClass() == s1) {
 975          emit_sop2_instruction(ctx, instr, aco_opcode::s_max_u32, dst, true);
 976       } else {
 977          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 978          nir_print_instr(&instr->instr, stderr);
 979          fprintf(stderr, "\n");
 980       }
 981       break;
 982    }
 983    case nir_op_imin: {
 984       if (dst.regClass() == v1) {
 985          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_i32, dst, true);
 986       } else if (dst.regClass() == s1) {
 987          emit_sop2_instruction(ctx, instr, aco_opcode::s_min_i32, dst, true);
 988       } else {
 989          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 990          nir_print_instr(&instr->instr, stderr);
 991          fprintf(stderr, "\n");
 992       }
 993       break;
 994    }
 995    case nir_op_umin: {
 996       if (dst.regClass() == v1) {
 997          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_u32, dst, true);
 998       } else if (dst.regClass() == s1) {
 999          emit_sop2_instruction(ctx, instr, aco_opcode::s_min_u32, dst, true);
1000       } else {
1001          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1002          nir_print_instr(&instr->instr, stderr);
1003          fprintf(stderr, "\n");
1004       }
1005       break;
1006    }
1007    case nir_op_ior: {
1008       if (instr->dest.dest.ssa.bit_size == 1) {
1009          emit_boolean_logic(ctx, instr, Builder::s_or, dst);
1010       } else if (dst.regClass() == v1) {
1011          emit_vop2_instruction(ctx, instr, aco_opcode::v_or_b32, dst, true);
1012       } else if (dst.regClass() == s1) {
1013          emit_sop2_instruction(ctx, instr, aco_opcode::s_or_b32, dst, true);
1014       } else if (dst.regClass() == s2) {
1015          emit_sop2_instruction(ctx, instr, aco_opcode::s_or_b64, dst, true);
1016       } else {
1017          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1018          nir_print_instr(&instr->instr, stderr);
1019          fprintf(stderr, "\n");
1020       }
1021       break;
1022    }
1023    case nir_op_iand: {
1024       if (instr->dest.dest.ssa.bit_size == 1) {
1025          emit_boolean_logic(ctx, instr, Builder::s_and, dst);
1026       } else if (dst.regClass() == v1) {
1027          emit_vop2_instruction(ctx, instr, aco_opcode::v_and_b32, dst, true);
1028       } else if (dst.regClass() == s1) {
1029          emit_sop2_instruction(ctx, instr, aco_opcode::s_and_b32, dst, true);
1030       } else if (dst.regClass() == s2) {
1031          emit_sop2_instruction(ctx, instr, aco_opcode::s_and_b64, dst, true);
1032       } else {
1033          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1034          nir_print_instr(&instr->instr, stderr);
1035          fprintf(stderr, "\n");
1036       }
1037       break;
1038    }
1039    case nir_op_ixor: {
1040       if (instr->dest.dest.ssa.bit_size == 1) {
1041          emit_boolean_logic(ctx, instr, Builder::s_xor, dst);
1042       } else if (dst.regClass() == v1) {
1043          emit_vop2_instruction(ctx, instr, aco_opcode::v_xor_b32, dst, true);
1044       } else if (dst.regClass() == s1) {
1045          emit_sop2_instruction(ctx, instr, aco_opcode::s_xor_b32, dst, true);
1046       } else if (dst.regClass() == s2) {
1047          emit_sop2_instruction(ctx, instr, aco_opcode::s_xor_b64, dst, true);
1048       } else {
1049          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1050          nir_print_instr(&instr->instr, stderr);
1051          fprintf(stderr, "\n");
1052       }
1053       break;
1054    }
1055    case nir_op_ushr: {
1056       if (dst.regClass() == v1) {
1057          emit_vop2_instruction(ctx, instr, aco_opcode::v_lshrrev_b32, dst, false, true);
1058       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
1059          bld.vop3(aco_opcode::v_lshrrev_b64, Definition(dst),
1060                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
1061       } else if (dst.regClass() == v2) {
1062          bld.vop3(aco_opcode::v_lshr_b64, Definition(dst),
1063                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1064       } else if (dst.regClass() == s2) {
1065          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshr_b64, dst, true);
1066       } else if (dst.regClass() == s1) {
1067          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshr_b32, dst, true);
1068       } else {
1069          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1070          nir_print_instr(&instr->instr, stderr);
1071          fprintf(stderr, "\n");
1072       }
1073       break;
1074    }
1075    case nir_op_ishl: {
1076       if (dst.regClass() == v1) {
1077          emit_vop2_instruction(ctx, instr, aco_opcode::v_lshlrev_b32, dst, false, true);
1078       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
1079          bld.vop3(aco_opcode::v_lshlrev_b64, Definition(dst),
1080                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
1081       } else if (dst.regClass() == v2) {
1082          bld.vop3(aco_opcode::v_lshl_b64, Definition(dst),
1083                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1084       } else if (dst.regClass() == s1) {
1085          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshl_b32, dst, true);
1086       } else if (dst.regClass() == s2) {
1087          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshl_b64, dst, true);
1088       } else {
1089          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1090          nir_print_instr(&instr->instr, stderr);
1091          fprintf(stderr, "\n");
1092       }
1093       break;
1094    }
1095    case nir_op_ishr: {
1096       if (dst.regClass() == v1) {
1097          emit_vop2_instruction(ctx, instr, aco_opcode::v_ashrrev_i32, dst, false, true);
1098       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
1099          bld.vop3(aco_opcode::v_ashrrev_i64, Definition(dst),
1100                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
1101       } else if (dst.regClass() == v2) {
1102          bld.vop3(aco_opcode::v_ashr_i64, Definition(dst),
1103                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1104       } else if (dst.regClass() == s1) {
1105          emit_sop2_instruction(ctx, instr, aco_opcode::s_ashr_i32, dst, true);
1106       } else if (dst.regClass() == s2) {
1107          emit_sop2_instruction(ctx, instr, aco_opcode::s_ashr_i64, dst, true);
1108       } else {
1109          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1110          nir_print_instr(&instr->instr, stderr);
1111          fprintf(stderr, "\n");
1112       }
1113       break;
1114    }
1115    case nir_op_find_lsb: {
1116       Temp src = get_alu_src(ctx, instr->src[0]);
1117       if (src.regClass() == s1) {
1118          bld.sop1(aco_opcode::s_ff1_i32_b32, Definition(dst), src);
1119       } else if (src.regClass() == v1) {
1120          emit_vop1_instruction(ctx, instr, aco_opcode::v_ffbl_b32, dst);
1121       } else if (src.regClass() == s2) {
1122          bld.sop1(aco_opcode::s_ff1_i32_b64, Definition(dst), src);
1123       } else {
1124          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1125          nir_print_instr(&instr->instr, stderr);
1126          fprintf(stderr, "\n");
1127       }
1128       break;
1129    }
1130    case nir_op_ufind_msb:
1131    case nir_op_ifind_msb: {
1132       Temp src = get_alu_src(ctx, instr->src[0]);
1133       if (src.regClass() == s1 || src.regClass() == s2) {
1134          aco_opcode op = src.regClass() == s2 ?
1135                          (instr->op == nir_op_ufind_msb ? aco_opcode::s_flbit_i32_b64 : aco_opcode::s_flbit_i32_i64) :
1136                          (instr->op == nir_op_ufind_msb ? aco_opcode::s_flbit_i32_b32 : aco_opcode::s_flbit_i32);
1137          Temp msb_rev = bld.sop1(op, bld.def(s1), src);
1138
1139          Builder::Result sub = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc),
1140                                         Operand(src.size() * 32u - 1u), msb_rev);
1141          Temp msb = sub.def(0).getTemp();
1142          Temp carry = sub.def(1).getTemp();
1143
1144          bld.sop2(aco_opcode::s_cselect_b32, Definition(dst), Operand((uint32_t)-1), msb, bld.scc(carry));
1145       } else if (src.regClass() == v1) {
1146          aco_opcode op = instr->op == nir_op_ufind_msb ? aco_opcode::v_ffbh_u32 : aco_opcode::v_ffbh_i32;
1147          Temp msb_rev = bld.tmp(v1);
1148          emit_vop1_instruction(ctx, instr, op, msb_rev);
1149          Temp msb = bld.tmp(v1);
1150          Temp carry = bld.vsub32(Definition(msb), Operand(31u), Operand(msb_rev), true).def(1).getTemp();
1151          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), msb, Operand((uint32_t)-1), carry);
1152       } else {
1153          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1154          nir_print_instr(&instr->instr, stderr);
1155          fprintf(stderr, "\n");
1156       }
1157       break;
1158    }
1159    case nir_op_bitfield_reverse: {
1160       if (dst.regClass() == s1) {
1161          bld.sop1(aco_opcode::s_brev_b32, Definition(dst), get_alu_src(ctx, instr->src[0]));
1162       } else if (dst.regClass() == v1) {
1163          bld.vop1(aco_opcode::v_bfrev_b32, Definition(dst), get_alu_src(ctx, instr->src[0]));
1164       } else {
1165          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1166          nir_print_instr(&instr->instr, stderr);
1167          fprintf(stderr, "\n");
1168       }
1169       break;
1170    }
1171    case nir_op_iadd: {
1172       if (dst.regClass() == s1) {
1173          emit_sop2_instruction(ctx, instr, aco_opcode::s_add_u32, dst, true);
1174          break;
1175       }
1176
1177       Temp src0 = get_alu_src(ctx, instr->src[0]);
1178       Temp src1 = get_alu_src(ctx, instr->src[1]);
1179       if (dst.regClass() == v1) {
1180          bld.vadd32(Definition(dst), Operand(src0), Operand(src1));
1181          break;
1182       }
1183
1184       assert(src0.size() == 2 && src1.size() == 2);
1185       Temp src00 = bld.tmp(src0.type(), 1);
1186       Temp src01 = bld.tmp(dst.type(), 1);
1187       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1188       Temp src10 = bld.tmp(src1.type(), 1);
1189       Temp src11 = bld.tmp(dst.type(), 1);
1190       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1191
1192       if (dst.regClass() == s2) {
1193          Temp carry = bld.tmp(s1);
1194          Temp dst0 = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1195          Temp dst1 = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), src01, src11, bld.scc(carry));
1196          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1197       } else if (dst.regClass() == v2) {
1198          Temp dst0 = bld.tmp(v1);
1199          Temp carry = bld.vadd32(Definition(dst0), src00, src10, true).def(1).getTemp();
1200          Temp dst1 = bld.vadd32(bld.def(v1), src01, src11, false, carry);
1201          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1202       } else {
1203          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1204          nir_print_instr(&instr->instr, stderr);
1205          fprintf(stderr, "\n");
1206       }
1207       break;
1208    }
1209    case nir_op_uadd_sat: {
1210       Temp src0 = get_alu_src(ctx, instr->src[0]);
1211       Temp src1 = get_alu_src(ctx, instr->src[1]);
1212       if (dst.regClass() == s1) {
1213          Temp tmp = bld.tmp(s1), carry = bld.tmp(s1);
1214          bld.sop2(aco_opcode::s_add_u32, Definition(tmp), bld.scc(Definition(carry)),
1215                   src0, src1);
1216          bld.sop2(aco_opcode::s_cselect_b32, Definition(dst), Operand((uint32_t) -1), tmp, bld.scc(carry));
1217       } else if (dst.regClass() == v1) {
1218          if (ctx->options->chip_class >= GFX9) {
1219             aco_ptr<VOP3A_instruction> add{create_instruction<VOP3A_instruction>(aco_opcode::v_add_u32, asVOP3(Format::VOP2), 2, 1)};
1220             add->operands[0] = Operand(src0);
1221             add->operands[1] = Operand(src1);
1222             add->definitions[0] = Definition(dst);
1223             add->clamp = 1;
1224             ctx->block->instructions.emplace_back(std::move(add));
1225          } else {
1226             if (src1.regClass() != v1)
1227                std::swap(src0, src1);
1228             assert(src1.regClass() == v1);
1229             Temp tmp = bld.tmp(v1);
1230             Temp carry = bld.vadd32(Definition(tmp), src0, src1, true).def(1).getTemp();
1231             bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), tmp, Operand((uint32_t) -1), carry);
1232          }
1233       } else {
1234          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1235          nir_print_instr(&instr->instr, stderr);
1236          fprintf(stderr, "\n");
1237       }
1238       break;
1239    }
1240    case nir_op_uadd_carry: {
1241       Temp src0 = get_alu_src(ctx, instr->src[0]);
1242       Temp src1 = get_alu_src(ctx, instr->src[1]);
1243       if (dst.regClass() == s1) {
1244          bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(dst)), src0, src1);
1245          break;
1246       }
1247       if (dst.regClass() == v1) {
1248          Temp carry = bld.vadd32(bld.def(v1), src0, src1, true).def(1).getTemp();
1249          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), carry);
1250          break;
1251       }
1252
1253       Temp src00 = bld.tmp(src0.type(), 1);
1254       Temp src01 = bld.tmp(dst.type(), 1);
1255       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1256       Temp src10 = bld.tmp(src1.type(), 1);
1257       Temp src11 = bld.tmp(dst.type(), 1);
1258       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1259       if (dst.regClass() == s2) {
1260          Temp carry = bld.tmp(s1);
1261          bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1262          carry = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.scc(bld.def(s1)), src01, src11, bld.scc(carry)).def(1).getTemp();
1263          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), carry, Operand(0u));
1264       } else if (dst.regClass() == v2) {
1265          Temp carry = bld.vadd32(bld.def(v1), src00, src10, true).def(1).getTemp();
1266          carry = bld.vadd32(bld.def(v1), src01, src11, true, carry).def(1).getTemp();
1267          carry = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand(1u), carry);
1268          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), carry, Operand(0u));
1269       } else {
1270          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1271          nir_print_instr(&instr->instr, stderr);
1272          fprintf(stderr, "\n");
1273       }
1274       break;
1275    }
1276    case nir_op_isub: {
1277       if (dst.regClass() == s1) {
1278          emit_sop2_instruction(ctx, instr, aco_opcode::s_sub_i32, dst, true);
1279          break;
1280       }
1281
1282       Temp src0 = get_alu_src(ctx, instr->src[0]);
1283       Temp src1 = get_alu_src(ctx, instr->src[1]);
1284       if (dst.regClass() == v1) {
1285          bld.vsub32(Definition(dst), src0, src1);
1286          break;
1287       }
1288
1289       Temp src00 = bld.tmp(src0.type(), 1);
1290       Temp src01 = bld.tmp(dst.type(), 1);
1291       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1292       Temp src10 = bld.tmp(src1.type(), 1);
1293       Temp src11 = bld.tmp(dst.type(), 1);
1294       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1295       if (dst.regClass() == s2) {
1296          Temp carry = bld.tmp(s1);
1297          Temp dst0 = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1298          Temp dst1 = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), src01, src11, carry);
1299          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1300       } else if (dst.regClass() == v2) {
1301          Temp lower = bld.tmp(v1);
1302          Temp borrow = bld.vsub32(Definition(lower), src00, src10, true).def(1).getTemp();
1303          Temp upper = bld.vsub32(bld.def(v1), src01, src11, false, borrow);
1304          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1305       } else {
1306          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1307          nir_print_instr(&instr->instr, stderr);
1308          fprintf(stderr, "\n");
1309       }
1310       break;
1311    }
1312    case nir_op_usub_borrow: {
1313       Temp src0 = get_alu_src(ctx, instr->src[0]);
1314       Temp src1 = get_alu_src(ctx, instr->src[1]);
1315       if (dst.regClass() == s1) {
1316          bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(dst)), src0, src1);
1317          break;
1318       } else if (dst.regClass() == v1) {
1319          Temp borrow = bld.vsub32(bld.def(v1), src0, src1, true).def(1).getTemp();
1320          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), borrow);
1321          break;
1322       }
1323
1324       Temp src00 = bld.tmp(src0.type(), 1);
1325       Temp src01 = bld.tmp(dst.type(), 1);
1326       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1327       Temp src10 = bld.tmp(src1.type(), 1);
1328       Temp src11 = bld.tmp(dst.type(), 1);
1329       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1330       if (dst.regClass() == s2) {
1331          Temp borrow = bld.tmp(s1);
1332          bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(borrow)), src00, src10);
1333          borrow = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.scc(bld.def(s1)), src01, src11, bld.scc(borrow)).def(1).getTemp();
1334          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), borrow, Operand(0u));
1335       } else if (dst.regClass() == v2) {
1336          Temp borrow = bld.vsub32(bld.def(v1), src00, src10, true).def(1).getTemp();
1337          borrow = bld.vsub32(bld.def(v1), src01, src11, true, Operand(borrow)).def(1).getTemp();
1338          borrow = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand(1u), borrow);
1339          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), borrow, Operand(0u));
1340       } else {
1341          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1342          nir_print_instr(&instr->instr, stderr);
1343          fprintf(stderr, "\n");
1344       }
1345       break;
1346    }
1347    case nir_op_imul: {
1348       if (dst.regClass() == v1) {
1349          bld.vop3(aco_opcode::v_mul_lo_u32, Definition(dst),
1350                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1351       } else if (dst.regClass() == s1) {
1352          emit_sop2_instruction(ctx, instr, aco_opcode::s_mul_i32, dst, false);
1353       } else {
1354          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1355          nir_print_instr(&instr->instr, stderr);
1356          fprintf(stderr, "\n");
1357       }
1358       break;
1359    }
1360    case nir_op_umul_high: {
1361       if (dst.regClass() == v1) {
1362          bld.vop3(aco_opcode::v_mul_hi_u32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1363       } else if (dst.regClass() == s1 && ctx->options->chip_class >= GFX9) {
1364          bld.sop2(aco_opcode::s_mul_hi_u32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1365       } else if (dst.regClass() == s1) {
1366          Temp tmp = bld.vop3(aco_opcode::v_mul_hi_u32, bld.def(v1), get_alu_src(ctx, instr->src[0]),
1367                              as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1368          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), tmp);
1369       } else {
1370          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1371          nir_print_instr(&instr->instr, stderr);
1372          fprintf(stderr, "\n");
1373       }
1374       break;
1375    }
1376    case nir_op_imul_high: {
1377       if (dst.regClass() == v1) {
1378          bld.vop3(aco_opcode::v_mul_hi_i32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1379       } else if (dst.regClass() == s1 && ctx->options->chip_class >= GFX9) {
1380          bld.sop2(aco_opcode::s_mul_hi_i32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1381       } else if (dst.regClass() == s1) {
1382          Temp tmp = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), get_alu_src(ctx, instr->src[0]),
1383                              as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1384          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), tmp);
1385       } else {
1386          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1387          nir_print_instr(&instr->instr, stderr);
1388          fprintf(stderr, "\n");
1389       }
1390       break;
1391    }
1392    case nir_op_fmul: {
1393       if (dst.size() == 1) {
1394          emit_vop2_instruction(ctx, instr, aco_opcode::v_mul_f32, dst, true);
1395       } else if (dst.size() == 2) {
1396          bld.vop3(aco_opcode::v_mul_f64, Definition(dst), get_alu_src(ctx, instr->src[0]),
1397                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1398       } else {
1399          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1400          nir_print_instr(&instr->instr, stderr);
1401          fprintf(stderr, "\n");
1402       }
1403       break;
1404    }
1405    case nir_op_fadd: {
1406       if (dst.size() == 1) {
1407          emit_vop2_instruction(ctx, instr, aco_opcode::v_add_f32, dst, true);
1408       } else if (dst.size() == 2) {
1409          bld.vop3(aco_opcode::v_add_f64, Definition(dst), get_alu_src(ctx, instr->src[0]),
1410                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1411       } else {
1412          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1413          nir_print_instr(&instr->instr, stderr);
1414          fprintf(stderr, "\n");
1415       }
1416       break;
1417    }
1418    case nir_op_fsub: {
1419       Temp src0 = get_alu_src(ctx, instr->src[0]);
1420       Temp src1 = get_alu_src(ctx, instr->src[1]);
1421       if (dst.size() == 1) {
1422          if (src1.type() == RegType::vgpr || src0.type() != RegType::vgpr)
1423             emit_vop2_instruction(ctx, instr, aco_opcode::v_sub_f32, dst, false);
1424          else
1425             emit_vop2_instruction(ctx, instr, aco_opcode::v_subrev_f32, dst, true);
1426       } else if (dst.size() == 2) {
1427          Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst),
1428                                      get_alu_src(ctx, instr->src[0]),
1429                                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1430          VOP3A_instruction* sub = static_cast<VOP3A_instruction*>(add);
1431          sub->neg[1] = true;
1432       } else {
1433          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1434          nir_print_instr(&instr->instr, stderr);
1435          fprintf(stderr, "\n");
1436       }
1437       break;
1438    }
1439    case nir_op_fmax: {
1440       if (dst.size() == 1) {
1441          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_f32, dst, true, false, ctx->block->fp_mode.must_flush_denorms32);
1442       } else if (dst.size() == 2) {
1443          if (ctx->block->fp_mode.must_flush_denorms16_64 && ctx->program->chip_class < GFX9) {
1444             Temp tmp = bld.vop3(aco_opcode::v_max_f64, bld.def(v2),
1445                                 get_alu_src(ctx, instr->src[0]),
1446                                 as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1447             bld.vop3(aco_opcode::v_mul_f64, Definition(dst), Operand(0x3FF0000000000000lu), tmp);
1448          } else {
1449             bld.vop3(aco_opcode::v_max_f64, Definition(dst),
1450                      get_alu_src(ctx, instr->src[0]),
1451                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1452          }
1453       } else {
1454          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1455          nir_print_instr(&instr->instr, stderr);
1456          fprintf(stderr, "\n");
1457       }
1458       break;
1459    }
1460    case nir_op_fmin: {
1461       if (dst.size() == 1) {
1462          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_f32, dst, true, false, ctx->block->fp_mode.must_flush_denorms32);
1463       } else if (dst.size() == 2) {
1464          if (ctx->block->fp_mode.must_flush_denorms16_64 && ctx->program->chip_class < GFX9) {
1465             Temp tmp = bld.vop3(aco_opcode::v_min_f64, bld.def(v2),
1466                                 get_alu_src(ctx, instr->src[0]),
1467                                 as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1468             bld.vop3(aco_opcode::v_mul_f64, Definition(dst), Operand(0x3FF0000000000000lu), tmp);
1469          } else {
1470             bld.vop3(aco_opcode::v_min_f64, Definition(dst),
1471                      get_alu_src(ctx, instr->src[0]),
1472                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1473          }
1474       } else {
1475          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1476          nir_print_instr(&instr->instr, stderr);
1477          fprintf(stderr, "\n");
1478       }
1479       break;
1480    }
1481    case nir_op_fmax3: {
1482       if (dst.size() == 1) {
1483          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_f32, dst, ctx->block->fp_mode.must_flush_denorms32);
1484       } else {
1485          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1486          nir_print_instr(&instr->instr, stderr);
1487          fprintf(stderr, "\n");
1488       }
1489       break;
1490    }
1491    case nir_op_fmin3: {
1492       if (dst.size() == 1) {
1493          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_f32, dst, ctx->block->fp_mode.must_flush_denorms32);
1494       } else {
1495          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1496          nir_print_instr(&instr->instr, stderr);
1497          fprintf(stderr, "\n");
1498       }
1499       break;
1500    }
1501    case nir_op_fmed3: {
1502       if (dst.size() == 1) {
1503          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_f32, dst, ctx->block->fp_mode.must_flush_denorms32);
1504       } else {
1505          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1506          nir_print_instr(&instr->instr, stderr);
1507          fprintf(stderr, "\n");
1508       }
1509       break;
1510    }
1511    case nir_op_umax3: {
1512       if (dst.size() == 1) {
1513          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_u32, dst);
1514       } else {
1515          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1516          nir_print_instr(&instr->instr, stderr);
1517          fprintf(stderr, "\n");
1518       }
1519       break;
1520    }
1521    case nir_op_umin3: {
1522       if (dst.size() == 1) {
1523          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_u32, dst);
1524       } else {
1525          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1526          nir_print_instr(&instr->instr, stderr);
1527          fprintf(stderr, "\n");
1528       }
1529       break;
1530    }
1531    case nir_op_umed3: {
1532       if (dst.size() == 1) {
1533          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_u32, dst);
1534       } else {
1535          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1536          nir_print_instr(&instr->instr, stderr);
1537          fprintf(stderr, "\n");
1538       }
1539       break;
1540    }
1541    case nir_op_imax3: {
1542       if (dst.size() == 1) {
1543          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_i32, dst);
1544       } else {
1545          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1546          nir_print_instr(&instr->instr, stderr);
1547          fprintf(stderr, "\n");
1548       }
1549       break;
1550    }
1551    case nir_op_imin3: {
1552       if (dst.size() == 1) {
1553          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_i32, dst);
1554       } else {
1555          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1556          nir_print_instr(&instr->instr, stderr);
1557          fprintf(stderr, "\n");
1558       }
1559       break;
1560    }
1561    case nir_op_imed3: {
1562       if (dst.size() == 1) {
1563          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_i32, dst);
1564       } else {
1565          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1566          nir_print_instr(&instr->instr, stderr);
1567          fprintf(stderr, "\n");
1568       }
1569       break;
1570    }
1571    case nir_op_cube_face_coord: {
1572       Temp in = get_alu_src(ctx, instr->src[0], 3);
1573       Temp src[3] = { emit_extract_vector(ctx, in, 0, v1),
1574                       emit_extract_vector(ctx, in, 1, v1),
1575                       emit_extract_vector(ctx, in, 2, v1) };
1576       Temp ma = bld.vop3(aco_opcode::v_cubema_f32, bld.def(v1), src[0], src[1], src[2]);
1577       ma = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), ma);
1578       Temp sc = bld.vop3(aco_opcode::v_cubesc_f32, bld.def(v1), src[0], src[1], src[2]);
1579       Temp tc = bld.vop3(aco_opcode::v_cubetc_f32, bld.def(v1), src[0], src[1], src[2]);
1580       sc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), sc, ma, Operand(0x3f000000u/*0.5*/));
1581       tc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), tc, ma, Operand(0x3f000000u/*0.5*/));
1582       bld.pseudo(aco_opcode::p_create_vector, Definition(dst), sc, tc);
1583       break;
1584    }
1585    case nir_op_cube_face_index: {
1586       Temp in = get_alu_src(ctx, instr->src[0], 3);
1587       Temp src[3] = { emit_extract_vector(ctx, in, 0, v1),
1588                       emit_extract_vector(ctx, in, 1, v1),
1589                       emit_extract_vector(ctx, in, 2, v1) };
1590       bld.vop3(aco_opcode::v_cubeid_f32, Definition(dst), src[0], src[1], src[2]);
1591       break;
1592    }
1593    case nir_op_bcsel: {
1594       emit_bcsel(ctx, instr, dst);
1595       break;
1596    }
1597    case nir_op_frsq: {
1598       if (dst.size() == 1) {
1599          emit_rsq(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1600       } else if (dst.size() == 2) {
1601          emit_vop1_instruction(ctx, instr, aco_opcode::v_rsq_f64, dst);
1602       } else {
1603          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1604          nir_print_instr(&instr->instr, stderr);
1605          fprintf(stderr, "\n");
1606       }
1607       break;
1608    }
1609    case nir_op_fneg: {
1610       Temp src = get_alu_src(ctx, instr->src[0]);
1611       if (dst.size() == 1) {
1612          if (ctx->block->fp_mode.must_flush_denorms32)
1613             src = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x3f800000u), as_vgpr(ctx, src));
1614          bld.vop2(aco_opcode::v_xor_b32, Definition(dst), Operand(0x80000000u), as_vgpr(ctx, src));
1615       } else if (dst.size() == 2) {
1616          if (ctx->block->fp_mode.must_flush_denorms16_64)
1617             src = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), Operand(0x3FF0000000000000lu), as_vgpr(ctx, src));
1618          Temp upper = bld.tmp(v1), lower = bld.tmp(v1);
1619          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1620          upper = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), Operand(0x80000000u), upper);
1621          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1622       } else {
1623          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1624          nir_print_instr(&instr->instr, stderr);
1625          fprintf(stderr, "\n");
1626       }
1627       break;
1628    }
1629    case nir_op_fabs: {
1630       Temp src = get_alu_src(ctx, instr->src[0]);
1631       if (dst.size() == 1) {
1632          if (ctx->block->fp_mode.must_flush_denorms32)
1633             src = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x3f800000u), as_vgpr(ctx, src));
1634          bld.vop2(aco_opcode::v_and_b32, Definition(dst), Operand(0x7FFFFFFFu), as_vgpr(ctx, src));
1635       } else if (dst.size() == 2) {
1636          if (ctx->block->fp_mode.must_flush_denorms16_64)
1637             src = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), Operand(0x3FF0000000000000lu), as_vgpr(ctx, src));
1638          Temp upper = bld.tmp(v1), lower = bld.tmp(v1);
1639          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1640          upper = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7FFFFFFFu), upper);
1641          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1642       } else {
1643          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1644          nir_print_instr(&instr->instr, stderr);
1645          fprintf(stderr, "\n");
1646       }
1647       break;
1648    }
1649    case nir_op_fsat: {
1650       Temp src = get_alu_src(ctx, instr->src[0]);
1651       if (dst.size() == 1) {
1652          bld.vop3(aco_opcode::v_med3_f32, Definition(dst), Operand(0u), Operand(0x3f800000u), src);
1653          /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1654          // TODO: confirm that this holds under any circumstances
1655       } else if (dst.size() == 2) {
1656          Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst), src, Operand(0u));
1657          VOP3A_instruction* vop3 = static_cast<VOP3A_instruction*>(add);
1658          vop3->clamp = true;
1659       } else {
1660          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1661          nir_print_instr(&instr->instr, stderr);
1662          fprintf(stderr, "\n");
1663       }
1664       break;
1665    }
1666    case nir_op_flog2: {
1667       if (dst.size() == 1) {
1668          emit_log2(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1669       } else {
1670          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1671          nir_print_instr(&instr->instr, stderr);
1672          fprintf(stderr, "\n");
1673       }
1674       break;
1675    }
1676    case nir_op_frcp: {
1677       if (dst.size() == 1) {
1678          emit_rcp(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1679       } else if (dst.size() == 2) {
1680          emit_vop1_instruction(ctx, instr, aco_opcode::v_rcp_f64, dst);
1681       } else {
1682          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1683          nir_print_instr(&instr->instr, stderr);
1684          fprintf(stderr, "\n");
1685       }
1686       break;
1687    }
1688    case nir_op_fexp2: {
1689       if (dst.size() == 1) {
1690          emit_vop1_instruction(ctx, instr, aco_opcode::v_exp_f32, dst);
1691       } else {
1692          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1693          nir_print_instr(&instr->instr, stderr);
1694          fprintf(stderr, "\n");
1695       }
1696       break;
1697    }
1698    case nir_op_fsqrt: {
1699       if (dst.size() == 1) {
1700          emit_sqrt(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1701       } else if (dst.size() == 2) {
1702          emit_vop1_instruction(ctx, instr, aco_opcode::v_sqrt_f64, dst);
1703       } else {
1704          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1705          nir_print_instr(&instr->instr, stderr);
1706          fprintf(stderr, "\n");
1707       }
1708       break;
1709    }
1710    case nir_op_ffract: {
1711       if (dst.size() == 1) {
1712          emit_vop1_instruction(ctx, instr, aco_opcode::v_fract_f32, dst);
1713       } else if (dst.size() == 2) {
1714          emit_vop1_instruction(ctx, instr, aco_opcode::v_fract_f64, dst);
1715       } else {
1716          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1717          nir_print_instr(&instr->instr, stderr);
1718          fprintf(stderr, "\n");
1719       }
1720       break;
1721    }
1722    case nir_op_ffloor: {
1723       if (dst.size() == 1) {
1724          emit_vop1_instruction(ctx, instr, aco_opcode::v_floor_f32, dst);
1725       } else if (dst.size() == 2) {
1726          emit_floor_f64(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1727       } else {
1728          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1729          nir_print_instr(&instr->instr, stderr);
1730          fprintf(stderr, "\n");
1731       }
1732       break;
1733    }
1734    case nir_op_fceil: {
1735       if (dst.size() == 1) {
1736          emit_vop1_instruction(ctx, instr, aco_opcode::v_ceil_f32, dst);
1737       } else if (dst.size() == 2) {
1738          if (ctx->options->chip_class >= GFX7) {
1739             emit_vop1_instruction(ctx, instr, aco_opcode::v_ceil_f64, dst);
1740          } else {
1741             /* GFX6 doesn't support V_CEIL_F64, lower it. */
1742             Temp src0 = get_alu_src(ctx, instr->src[0]);
1743
1744             /* trunc = trunc(src0)
1745              * if (src0 > 0.0 && src0 != trunc)
1746              *    trunc += 1.0
1747              */
1748             Temp trunc = emit_trunc_f64(ctx, bld, bld.def(v2), src0);
1749             Temp tmp0 = bld.vopc_e64(aco_opcode::v_cmp_gt_f64, bld.def(bld.lm), src0, Operand(0u));
1750             Temp tmp1 = bld.vopc(aco_opcode::v_cmp_lg_f64, bld.hint_vcc(bld.def(bld.lm)), src0, trunc);
1751             Temp cond = bld.sop2(aco_opcode::s_and_b64, bld.hint_vcc(bld.def(s2)), bld.def(s1, scc), tmp0, tmp1);
1752             Temp add = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), bld.copy(bld.def(v1), Operand(0u)), bld.copy(bld.def(v1), Operand(0x3ff00000u)), cond);
1753             add = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), bld.copy(bld.def(v1), Operand(0u)), add);
1754             bld.vop3(aco_opcode::v_add_f64, Definition(dst), trunc, add);
1755          }
1756       } else {
1757          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1758          nir_print_instr(&instr->instr, stderr);
1759          fprintf(stderr, "\n");
1760       }
1761       break;
1762    }
1763    case nir_op_ftrunc: {
1764       if (dst.size() == 1) {
1765          emit_vop1_instruction(ctx, instr, aco_opcode::v_trunc_f32, dst);
1766       } else if (dst.size() == 2) {
1767          emit_trunc_f64(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1768       } else {
1769          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1770          nir_print_instr(&instr->instr, stderr);
1771          fprintf(stderr, "\n");
1772       }
1773       break;
1774    }
1775    case nir_op_fround_even: {
1776       if (dst.size() == 1) {
1777          emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f32, dst);
1778       } else if (dst.size() == 2) {
1779          if (ctx->options->chip_class >= GFX7) {
1780             emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f64, dst);
1781          } else {
1782             /* GFX6 doesn't support V_RNDNE_F64, lower it. */
1783             Temp src0 = get_alu_src(ctx, instr->src[0]);
1784
1785             Temp src0_lo = bld.tmp(v1), src0_hi = bld.tmp(v1);
1786             bld.pseudo(aco_opcode::p_split_vector, Definition(src0_lo), Definition(src0_hi), src0);
1787
1788             Temp bitmask = bld.sop1(aco_opcode::s_brev_b32, bld.def(s1), bld.copy(bld.def(s1), Operand(-2u)));
1789             Temp bfi = bld.vop3(aco_opcode::v_bfi_b32, bld.def(v1), bitmask, bld.copy(bld.def(v1), Operand(0x43300000u)), as_vgpr(ctx, src0_hi));
1790             Temp tmp = bld.vop3(aco_opcode::v_add_f64, bld.def(v2), src0, bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), bfi));
1791             Instruction *sub = bld.vop3(aco_opcode::v_add_f64, bld.def(v2), tmp, bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), bfi));
1792             static_cast<VOP3A_instruction*>(sub)->neg[1] = true;
1793             tmp = sub->definitions[0].getTemp();
1794
1795             Temp v = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(-1u), Operand(0x432fffffu));
1796             Instruction* vop3 = bld.vopc_e64(aco_opcode::v_cmp_gt_f64, bld.hint_vcc(bld.def(bld.lm)), src0, v);
1797             static_cast<VOP3A_instruction*>(vop3)->abs[0] = true;
1798             Temp cond = vop3->definitions[0].getTemp();
1799
1800             Temp tmp_lo = bld.tmp(v1), tmp_hi = bld.tmp(v1);
1801             bld.pseudo(aco_opcode::p_split_vector, Definition(tmp_lo), Definition(tmp_hi), tmp);
1802             Temp dst0 = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), tmp_lo, as_vgpr(ctx, src0_lo), cond);
1803             Temp dst1 = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), tmp_hi, as_vgpr(ctx, src0_hi), cond);
1804
1805             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1806          }
1807       } else {
1808          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1809          nir_print_instr(&instr->instr, stderr);
1810          fprintf(stderr, "\n");
1811       }
1812       break;
1813    }
1814    case nir_op_fsin:
1815    case nir_op_fcos: {
1816       Temp src = get_alu_src(ctx, instr->src[0]);
1817       aco_ptr<Instruction> norm;
1818       if (dst.size() == 1) {
1819          Temp half_pi = bld.copy(bld.def(s1), Operand(0x3e22f983u));
1820          Temp tmp = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), half_pi, as_vgpr(ctx, src));
1821
1822          /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
1823          if (ctx->options->chip_class < GFX9)
1824             tmp = bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), tmp);
1825
1826          aco_opcode opcode = instr->op == nir_op_fsin ? aco_opcode::v_sin_f32 : aco_opcode::v_cos_f32;
1827          bld.vop1(opcode, Definition(dst), tmp);
1828       } else {
1829          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1830          nir_print_instr(&instr->instr, stderr);
1831          fprintf(stderr, "\n");
1832       }
1833       break;
1834    }
1835    case nir_op_ldexp: {
1836       if (dst.size() == 1) {
1837          bld.vop3(aco_opcode::v_ldexp_f32, Definition(dst),
1838                   as_vgpr(ctx, get_alu_src(ctx, instr->src[0])),
1839                   get_alu_src(ctx, instr->src[1]));
1840       } else if (dst.size() == 2) {
1841          bld.vop3(aco_opcode::v_ldexp_f64, Definition(dst),
1842                   as_vgpr(ctx, get_alu_src(ctx, instr->src[0])),
1843                   get_alu_src(ctx, instr->src[1]));
1844       } else {
1845          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1846          nir_print_instr(&instr->instr, stderr);
1847          fprintf(stderr, "\n");
1848       }
1849       break;
1850    }
1851    case nir_op_frexp_sig: {
1852       if (dst.size() == 1) {
1853          bld.vop1(aco_opcode::v_frexp_mant_f32, Definition(dst),
1854                   get_alu_src(ctx, instr->src[0]));
1855       } else if (dst.size() == 2) {
1856          bld.vop1(aco_opcode::v_frexp_mant_f64, Definition(dst),
1857                   get_alu_src(ctx, instr->src[0]));
1858       } else {
1859          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1860          nir_print_instr(&instr->instr, stderr);
1861          fprintf(stderr, "\n");
1862       }
1863       break;
1864    }
1865    case nir_op_frexp_exp: {
1866       if (instr->src[0].src.ssa->bit_size == 32) {
1867          bld.vop1(aco_opcode::v_frexp_exp_i32_f32, Definition(dst),
1868                   get_alu_src(ctx, instr->src[0]));
1869       } else if (instr->src[0].src.ssa->bit_size == 64) {
1870          bld.vop1(aco_opcode::v_frexp_exp_i32_f64, Definition(dst),
1871                   get_alu_src(ctx, instr->src[0]));
1872       } else {
1873          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1874          nir_print_instr(&instr->instr, stderr);
1875          fprintf(stderr, "\n");
1876       }
1877       break;
1878    }
1879    case nir_op_fsign: {
1880       Temp src = as_vgpr(ctx, get_alu_src(ctx, instr->src[0]));
1881       if (dst.size() == 1) {
1882          Temp cond = bld.vopc(aco_opcode::v_cmp_nlt_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1883          src = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0x3f800000u), src, cond);
1884          cond = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1885          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0xbf800000u), src, cond);
1886       } else if (dst.size() == 2) {
1887          Temp cond = bld.vopc(aco_opcode::v_cmp_nlt_f64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1888          Temp tmp = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0x3FF00000u));
1889          Temp upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), tmp, emit_extract_vector(ctx, src, 1, v1), cond);
1890
1891          cond = bld.vopc(aco_opcode::v_cmp_le_f64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1892          tmp = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0xBFF00000u));
1893          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), tmp, upper, cond);
1894
1895          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), Operand(0u), upper);
1896       } else {
1897          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1898          nir_print_instr(&instr->instr, stderr);
1899          fprintf(stderr, "\n");
1900       }
1901       break;
1902    }
1903    case nir_op_f2f32: {
1904       if (instr->src[0].src.ssa->bit_size == 64) {
1905          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_f64, dst);
1906       } else {
1907          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1908          nir_print_instr(&instr->instr, stderr);
1909          fprintf(stderr, "\n");
1910       }
1911       break;
1912    }
1913    case nir_op_f2f64: {
1914       if (instr->src[0].src.ssa->bit_size == 32) {
1915          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_f32, dst);
1916       } else {
1917          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1918          nir_print_instr(&instr->instr, stderr);
1919          fprintf(stderr, "\n");
1920       }
1921       break;
1922    }
1923    case nir_op_i2f32: {
1924       assert(dst.size() == 1);
1925       emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_i32, dst);
1926       break;
1927    }
1928    case nir_op_i2f64: {
1929       if (instr->src[0].src.ssa->bit_size == 32) {
1930          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_i32, dst);
1931       } else if (instr->src[0].src.ssa->bit_size == 64) {
1932          Temp src = get_alu_src(ctx, instr->src[0]);
1933          RegClass rc = RegClass(src.type(), 1);
1934          Temp lower = bld.tmp(rc), upper = bld.tmp(rc);
1935          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1936          lower = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), lower);
1937          upper = bld.vop1(aco_opcode::v_cvt_f64_i32, bld.def(v2), upper);
1938          upper = bld.vop3(aco_opcode::v_ldexp_f64, bld.def(v2), upper, Operand(32u));
1939          bld.vop3(aco_opcode::v_add_f64, Definition(dst), lower, upper);
1940
1941       } else {
1942          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1943          nir_print_instr(&instr->instr, stderr);
1944          fprintf(stderr, "\n");
1945       }
1946       break;
1947    }
1948    case nir_op_u2f32: {
1949       assert(dst.size() == 1);
1950       emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_u32, dst);
1951       break;
1952    }
1953    case nir_op_u2f64: {
1954       if (instr->src[0].src.ssa->bit_size == 32) {
1955          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_u32, dst);
1956       } else if (instr->src[0].src.ssa->bit_size == 64) {
1957          Temp src = get_alu_src(ctx, instr->src[0]);
1958          RegClass rc = RegClass(src.type(), 1);
1959          Temp lower = bld.tmp(rc), upper = bld.tmp(rc);
1960          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1961          lower = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), lower);
1962          upper = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), upper);
1963          upper = bld.vop3(aco_opcode::v_ldexp_f64, bld.def(v2), upper, Operand(32u));
1964          bld.vop3(aco_opcode::v_add_f64, Definition(dst), lower, upper);
1965       } else {
1966          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1967          nir_print_instr(&instr->instr, stderr);
1968          fprintf(stderr, "\n");
1969       }
1970       break;
1971    }
1972    case nir_op_f2i32: {
1973       Temp src = get_alu_src(ctx, instr->src[0]);
1974       if (instr->src[0].src.ssa->bit_size == 32) {
1975          if (dst.type() == RegType::vgpr)
1976             bld.vop1(aco_opcode::v_cvt_i32_f32, Definition(dst), src);
1977          else
1978             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1979                        bld.vop1(aco_opcode::v_cvt_i32_f32, bld.def(v1), src));
1980
1981       } else if (instr->src[0].src.ssa->bit_size == 64) {
1982          if (dst.type() == RegType::vgpr)
1983             bld.vop1(aco_opcode::v_cvt_i32_f64, Definition(dst), src);
1984          else
1985             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1986                        bld.vop1(aco_opcode::v_cvt_i32_f64, bld.def(v1), src));
1987
1988       } else {
1989          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1990          nir_print_instr(&instr->instr, stderr);
1991          fprintf(stderr, "\n");
1992       }
1993       break;
1994    }
1995    case nir_op_f2u32: {
1996       Temp src = get_alu_src(ctx, instr->src[0]);
1997       if (instr->src[0].src.ssa->bit_size == 32) {
1998          if (dst.type() == RegType::vgpr)
1999             bld.vop1(aco_opcode::v_cvt_u32_f32, Definition(dst), src);
2000          else
2001             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
2002                        bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), src));
2003
2004       } else if (instr->src[0].src.ssa->bit_size == 64) {
2005          if (dst.type() == RegType::vgpr)
2006             bld.vop1(aco_opcode::v_cvt_u32_f64, Definition(dst), src);
2007          else
2008             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
2009                        bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), src));
2010
2011       } else {
2012          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2013          nir_print_instr(&instr->instr, stderr);
2014          fprintf(stderr, "\n");
2015       }
2016       break;
2017    }
2018    case nir_op_f2i64: {
2019       Temp src = get_alu_src(ctx, instr->src[0]);
2020       if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::vgpr) {
2021          Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f32, bld.def(v1), src);
2022          exponent = bld.vop3(aco_opcode::v_med3_i32, bld.def(v1), Operand(0x0u), exponent, Operand(64u));
2023          Temp mantissa = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffu), src);
2024          Temp sign = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
2025          mantissa = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(0x800000u), mantissa);
2026          mantissa = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(7u), mantissa);
2027          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), mantissa);
2028          Temp new_exponent = bld.tmp(v1);
2029          Temp borrow = bld.vsub32(Definition(new_exponent), Operand(63u), exponent, true).def(1).getTemp();
2030          if (ctx->program->chip_class >= GFX8)
2031             mantissa = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), new_exponent, mantissa);
2032          else
2033             mantissa = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), mantissa, new_exponent);
2034          Temp saturate = bld.vop1(aco_opcode::v_bfrev_b32, bld.def(v1), Operand(0xfffffffeu));
2035          Temp lower = bld.tmp(v1), upper = bld.tmp(v1);
2036          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2037          lower = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), lower, Operand(0xffffffffu), borrow);
2038          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), upper, saturate, borrow);
2039          lower = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), sign, lower);
2040          upper = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), sign, upper);
2041          Temp new_lower = bld.tmp(v1);
2042          borrow = bld.vsub32(Definition(new_lower), lower, sign, true).def(1).getTemp();
2043          Temp new_upper = bld.vsub32(bld.def(v1), upper, sign, false, borrow);
2044          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), new_lower, new_upper);
2045
2046       } else if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::sgpr) {
2047          if (src.type() == RegType::vgpr)
2048             src = bld.as_uniform(src);
2049          Temp exponent = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), src, Operand(0x80017u));
2050          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(126u));
2051          exponent = bld.sop2(aco_opcode::s_max_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), exponent);
2052          exponent = bld.sop2(aco_opcode::s_min_u32, bld.def(s1), bld.def(s1, scc), Operand(64u), exponent);
2053          Temp mantissa = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0x7fffffu), src);
2054          Temp sign = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
2055          mantissa = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(0x800000u), mantissa);
2056          mantissa = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), mantissa, Operand(7u));
2057          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), mantissa);
2058          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), Operand(63u), exponent);
2059          mantissa = bld.sop2(aco_opcode::s_lshr_b64, bld.def(s2), bld.def(s1, scc), mantissa, exponent);
2060          Temp cond = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), exponent, Operand(0xffffffffu)); // exp >= 64
2061          Temp saturate = bld.sop1(aco_opcode::s_brev_b64, bld.def(s2), Operand(0xfffffffeu));
2062          mantissa = bld.sop2(aco_opcode::s_cselect_b64, bld.def(s2), saturate, mantissa, cond);
2063          Temp lower = bld.tmp(s1), upper = bld.tmp(s1);
2064          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2065          lower = bld.sop2(aco_opcode::s_xor_b32, bld.def(s1), bld.def(s1, scc), sign, lower);
2066          upper = bld.sop2(aco_opcode::s_xor_b32, bld.def(s1), bld.def(s1, scc), sign, upper);
2067          Temp borrow = bld.tmp(s1);
2068          lower = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(borrow)), lower, sign);
2069          upper = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), upper, sign, borrow);
2070          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2071
2072       } else if (instr->src[0].src.ssa->bit_size == 64) {
2073          Temp vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0x3df00000u));
2074          Temp trunc = emit_trunc_f64(ctx, bld, bld.def(v2), src);
2075          Temp mul = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), trunc, vec);
2076          vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0xc1f00000u));
2077          Temp floor = emit_floor_f64(ctx, bld, bld.def(v2), mul);
2078          Temp fma = bld.vop3(aco_opcode::v_fma_f64, bld.def(v2), floor, vec, trunc);
2079          Temp lower = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), fma);
2080          Temp upper = bld.vop1(aco_opcode::v_cvt_i32_f64, bld.def(v1), floor);
2081          if (dst.type() == RegType::sgpr) {
2082             lower = bld.as_uniform(lower);
2083             upper = bld.as_uniform(upper);
2084          }
2085          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2086
2087       } else {
2088          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2089          nir_print_instr(&instr->instr, stderr);
2090          fprintf(stderr, "\n");
2091       }
2092       break;
2093    }
2094    case nir_op_f2u64: {
2095       Temp src = get_alu_src(ctx, instr->src[0]);
2096       if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::vgpr) {
2097          Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f32, bld.def(v1), src);
2098          Temp exponent_in_range = bld.vopc(aco_opcode::v_cmp_ge_i32, bld.hint_vcc(bld.def(bld.lm)), Operand(64u), exponent);
2099          exponent = bld.vop2(aco_opcode::v_max_i32, bld.def(v1), Operand(0x0u), exponent);
2100          Temp mantissa = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffu), src);
2101          mantissa = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(0x800000u), mantissa);
2102          Temp exponent_small = bld.vsub32(bld.def(v1), Operand(24u), exponent);
2103          Temp small = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), exponent_small, mantissa);
2104          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), mantissa);
2105          Temp new_exponent = bld.tmp(v1);
2106          Temp cond_small = bld.vsub32(Definition(new_exponent), exponent, Operand(24u), true).def(1).getTemp();
2107          if (ctx->program->chip_class >= GFX8)
2108             mantissa = bld.vop3(aco_opcode::v_lshlrev_b64, bld.def(v2), new_exponent, mantissa);
2109          else
2110             mantissa = bld.vop3(aco_opcode::v_lshl_b64, bld.def(v2), mantissa, new_exponent);
2111          Temp lower = bld.tmp(v1), upper = bld.tmp(v1);
2112          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2113          lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), lower, small, cond_small);
2114          upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), upper, Operand(0u), cond_small);
2115          lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xffffffffu), lower, exponent_in_range);
2116          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xffffffffu), upper, exponent_in_range);
2117          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2118
2119       } else if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::sgpr) {
2120          if (src.type() == RegType::vgpr)
2121             src = bld.as_uniform(src);
2122          Temp exponent = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), src, Operand(0x80017u));
2123          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(126u));
2124          exponent = bld.sop2(aco_opcode::s_max_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), exponent);
2125          Temp mantissa = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0x7fffffu), src);
2126          mantissa = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(0x800000u), mantissa);
2127          Temp exponent_small = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), Operand(24u), exponent);
2128          Temp small = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), mantissa, exponent_small);
2129          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), mantissa);
2130          Temp exponent_large = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(24u));
2131          mantissa = bld.sop2(aco_opcode::s_lshl_b64, bld.def(s2), bld.def(s1, scc), mantissa, exponent_large);
2132          Temp cond = bld.sopc(aco_opcode::s_cmp_ge_i32, bld.def(s1, scc), Operand(64u), exponent);
2133          mantissa = bld.sop2(aco_opcode::s_cselect_b64, bld.def(s2), mantissa, Operand(0xffffffffu), cond);
2134          Temp lower = bld.tmp(s1), upper = bld.tmp(s1);
2135          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2136          Temp cond_small = bld.sopc(aco_opcode::s_cmp_le_i32, bld.def(s1, scc), exponent, Operand(24u));
2137          lower = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), small, lower, cond_small);
2138          upper = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), Operand(0u), upper, cond_small);
2139          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2140
2141       } else if (instr->src[0].src.ssa->bit_size == 64) {
2142          Temp vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0x3df00000u));
2143          Temp trunc = emit_trunc_f64(ctx, bld, bld.def(v2), src);
2144          Temp mul = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), trunc, vec);
2145          vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0xc1f00000u));
2146          Temp floor = emit_floor_f64(ctx, bld, bld.def(v2), mul);
2147          Temp fma = bld.vop3(aco_opcode::v_fma_f64, bld.def(v2), floor, vec, trunc);
2148          Temp lower = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), fma);
2149          Temp upper = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), floor);
2150          if (dst.type() == RegType::sgpr) {
2151             lower = bld.as_uniform(lower);
2152             upper = bld.as_uniform(upper);
2153          }
2154          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2155
2156       } else {
2157          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2158          nir_print_instr(&instr->instr, stderr);
2159          fprintf(stderr, "\n");
2160       }
2161       break;
2162    }
2163    case nir_op_b2f32: {
2164       Temp src = get_alu_src(ctx, instr->src[0]);
2165       assert(src.regClass() == bld.lm);
2166
2167       if (dst.regClass() == s1) {
2168          src = bool_to_scalar_condition(ctx, src);
2169          bld.sop2(aco_opcode::s_mul_i32, Definition(dst), Operand(0x3f800000u), src);
2170       } else if (dst.regClass() == v1) {
2171          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(0x3f800000u), src);
2172       } else {
2173          unreachable("Wrong destination register class for nir_op_b2f32.");
2174       }
2175       break;
2176    }
2177    case nir_op_b2f64: {
2178       Temp src = get_alu_src(ctx, instr->src[0]);
2179       assert(src.regClass() == bld.lm);
2180
2181       if (dst.regClass() == s2) {
2182          src = bool_to_scalar_condition(ctx, src);
2183          bld.sop2(aco_opcode::s_cselect_b64, Definition(dst), Operand(0x3f800000u), Operand(0u), bld.scc(src));
2184       } else if (dst.regClass() == v2) {
2185          Temp one = bld.vop1(aco_opcode::v_mov_b32, bld.def(v2), Operand(0x3FF00000u));
2186          Temp upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), one, src);
2187          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), Operand(0u), upper);
2188       } else {
2189          unreachable("Wrong destination register class for nir_op_b2f64.");
2190       }
2191       break;
2192    }
2193    case nir_op_i2i32: {
2194       Temp src = get_alu_src(ctx, instr->src[0]);
2195       if (instr->src[0].src.ssa->bit_size == 64) {
2196          /* we can actually just say dst = src, as it would map the lower register */
2197          emit_extract_vector(ctx, src, 0, dst);
2198       } else {
2199          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2200          nir_print_instr(&instr->instr, stderr);
2201          fprintf(stderr, "\n");
2202       }
2203       break;
2204    }
2205    case nir_op_u2u32: {
2206       Temp src = get_alu_src(ctx, instr->src[0]);
2207       if (instr->src[0].src.ssa->bit_size == 16) {
2208          if (dst.regClass() == s1) {
2209             bld.sop2(aco_opcode::s_and_b32, Definition(dst), bld.def(s1, scc), Operand(0xFFFFu), src);
2210          } else {
2211             // TODO: do better with SDWA
2212             bld.vop2(aco_opcode::v_and_b32, Definition(dst), Operand(0xFFFFu), src);
2213          }
2214       } else if (instr->src[0].src.ssa->bit_size == 64) {
2215          /* we can actually just say dst = src, as it would map the lower register */
2216          emit_extract_vector(ctx, src, 0, dst);
2217       } else {
2218          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2219          nir_print_instr(&instr->instr, stderr);
2220          fprintf(stderr, "\n");
2221       }
2222       break;
2223    }
2224    case nir_op_i2i64: {
2225       Temp src = get_alu_src(ctx, instr->src[0]);
2226       if (src.regClass() == s1) {
2227          Temp high = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
2228          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, high);
2229       } else if (src.regClass() == v1) {
2230          Temp high = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
2231          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, high);
2232       } else {
2233          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2234          nir_print_instr(&instr->instr, stderr);
2235          fprintf(stderr, "\n");
2236       }
2237       break;
2238    }
2239    case nir_op_u2u64: {
2240       Temp src = get_alu_src(ctx, instr->src[0]);
2241       if (instr->src[0].src.ssa->bit_size == 32) {
2242          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, Operand(0u));
2243       } else {
2244          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2245          nir_print_instr(&instr->instr, stderr);
2246          fprintf(stderr, "\n");
2247       }
2248       break;
2249    }
2250    case nir_op_b2i32: {
2251       Temp src = get_alu_src(ctx, instr->src[0]);
2252       assert(src.regClass() == bld.lm);
2253
2254       if (dst.regClass() == s1) {
2255          // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2256          bool_to_scalar_condition(ctx, src, dst);
2257       } else if (dst.regClass() == v1) {
2258          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), src);
2259       } else {
2260          unreachable("Invalid register class for b2i32");
2261       }
2262       break;
2263    }
2264    case nir_op_i2b1: {
2265       Temp src = get_alu_src(ctx, instr->src[0]);
2266       assert(dst.regClass() == bld.lm);
2267
2268       if (src.type() == RegType::vgpr) {
2269          assert(src.regClass() == v1 || src.regClass() == v2);
2270          assert(dst.regClass() == bld.lm);
2271          bld.vopc(src.size() == 2 ? aco_opcode::v_cmp_lg_u64 : aco_opcode::v_cmp_lg_u32,
2272                   Definition(dst), Operand(0u), src).def(0).setHint(vcc);
2273       } else {
2274          assert(src.regClass() == s1 || src.regClass() == s2);
2275          Temp tmp;
2276          if (src.regClass() == s2 && ctx->program->chip_class <= GFX7) {
2277             tmp = bld.sop2(aco_opcode::s_or_b64, bld.def(s2), bld.def(s1, scc), Operand(0u), src).def(1).getTemp();
2278          } else {
2279             tmp = bld.sopc(src.size() == 2 ? aco_opcode::s_cmp_lg_u64 : aco_opcode::s_cmp_lg_u32,
2280                            bld.scc(bld.def(s1)), Operand(0u), src);
2281          }
2282          bool_to_vector_condition(ctx, tmp, dst);
2283       }
2284       break;
2285    }
2286    case nir_op_pack_64_2x32_split: {
2287       Temp src0 = get_alu_src(ctx, instr->src[0]);
2288       Temp src1 = get_alu_src(ctx, instr->src[1]);
2289
2290       bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src0, src1);
2291       break;
2292    }
2293    case nir_op_unpack_64_2x32_split_x:
2294       bld.pseudo(aco_opcode::p_split_vector, Definition(dst), bld.def(dst.regClass()), get_alu_src(ctx, instr->src[0]));
2295       break;
2296    case nir_op_unpack_64_2x32_split_y:
2297       bld.pseudo(aco_opcode::p_split_vector, bld.def(dst.regClass()), Definition(dst), get_alu_src(ctx, instr->src[0]));
2298       break;
2299    case nir_op_pack_half_2x16: {
2300       Temp src = get_alu_src(ctx, instr->src[0], 2);
2301
2302       if (dst.regClass() == v1) {
2303          Temp src0 = bld.tmp(v1);
2304          Temp src1 = bld.tmp(v1);
2305          bld.pseudo(aco_opcode::p_split_vector, Definition(src0), Definition(src1), src);
2306          if (!ctx->block->fp_mode.care_about_round32 || ctx->block->fp_mode.round32 == fp_round_tz)
2307             bld.vop3(aco_opcode::v_cvt_pkrtz_f16_f32, Definition(dst), src0, src1);
2308          else
2309             bld.vop3(aco_opcode::v_cvt_pk_u16_u32, Definition(dst),
2310                      bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src0),
2311                      bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src1));
2312       } else {
2313          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2314          nir_print_instr(&instr->instr, stderr);
2315          fprintf(stderr, "\n");
2316       }
2317       break;
2318    }
2319    case nir_op_unpack_half_2x16_split_x: {
2320       if (dst.regClass() == v1) {
2321          Builder bld(ctx->program, ctx->block);
2322          bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst), get_alu_src(ctx, instr->src[0]));
2323       } else {
2324          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2325          nir_print_instr(&instr->instr, stderr);
2326          fprintf(stderr, "\n");
2327       }
2328       break;
2329    }
2330    case nir_op_unpack_half_2x16_split_y: {
2331       if (dst.regClass() == v1) {
2332          Builder bld(ctx->program, ctx->block);
2333          /* TODO: use SDWA here */
2334          bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst),
2335                   bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(16u), as_vgpr(ctx, get_alu_src(ctx, instr->src[0]))));
2336       } else {
2337          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2338          nir_print_instr(&instr->instr, stderr);
2339          fprintf(stderr, "\n");
2340       }
2341       break;
2342    }
2343    case nir_op_fquantize2f16: {
2344       Temp src = get_alu_src(ctx, instr->src[0]);
2345       Temp f16 = bld.vop1(aco_opcode::v_cvt_f16_f32, bld.def(v1), src);
2346       Temp f32, cmp_res;
2347
2348       if (ctx->program->chip_class >= GFX8) {
2349          Temp mask = bld.copy(bld.def(s1), Operand(0x36Fu)); /* value is NOT negative/positive denormal value */
2350          cmp_res = bld.vopc_e64(aco_opcode::v_cmp_class_f16, bld.hint_vcc(bld.def(bld.lm)), f16, mask);
2351          f32 = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), f16);
2352       } else {
2353          /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2354           * so compare the result and flush to 0 if it's smaller.
2355           */
2356          f32 = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), f16);
2357          Temp smallest = bld.copy(bld.def(s1), Operand(0x38800000u));
2358          Instruction* vop3 = bld.vopc_e64(aco_opcode::v_cmp_nlt_f32, bld.hint_vcc(bld.def(bld.lm)), f32, smallest);
2359          static_cast<VOP3A_instruction*>(vop3)->abs[0] = true;
2360          cmp_res = vop3->definitions[0].getTemp();
2361       }
2362
2363       if (ctx->block->fp_mode.preserve_signed_zero_inf_nan32 || ctx->program->chip_class < GFX8) {
2364          Temp copysign_0 = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0u), as_vgpr(ctx, src));
2365          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), copysign_0, f32, cmp_res);
2366       } else {
2367          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), f32, cmp_res);
2368       }
2369       break;
2370    }
2371    case nir_op_bfm: {
2372       Temp bits = get_alu_src(ctx, instr->src[0]);
2373       Temp offset = get_alu_src(ctx, instr->src[1]);
2374
2375       if (dst.regClass() == s1) {
2376          bld.sop2(aco_opcode::s_bfm_b32, Definition(dst), bits, offset);
2377       } else if (dst.regClass() == v1) {
2378          bld.vop3(aco_opcode::v_bfm_b32, Definition(dst), bits, offset);
2379       } else {
2380          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2381          nir_print_instr(&instr->instr, stderr);
2382          fprintf(stderr, "\n");
2383       }
2384       break;
2385    }
2386    case nir_op_bitfield_select: {
2387       /* (mask & insert) | (~mask & base) */
2388       Temp bitmask = get_alu_src(ctx, instr->src[0]);
2389       Temp insert = get_alu_src(ctx, instr->src[1]);
2390       Temp base = get_alu_src(ctx, instr->src[2]);
2391
2392       /* dst = (insert & bitmask) | (base & ~bitmask) */
2393       if (dst.regClass() == s1) {
2394          aco_ptr<Instruction> sop2;
2395          nir_const_value* const_bitmask = nir_src_as_const_value(instr->src[0].src);
2396          nir_const_value* const_insert = nir_src_as_const_value(instr->src[1].src);
2397          Operand lhs;
2398          if (const_insert && const_bitmask) {
2399             lhs = Operand(const_insert->u32 & const_bitmask->u32);
2400          } else {
2401             insert = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), insert, bitmask);
2402             lhs = Operand(insert);
2403          }
2404
2405          Operand rhs;
2406          nir_const_value* const_base = nir_src_as_const_value(instr->src[2].src);
2407          if (const_base && const_bitmask) {
2408             rhs = Operand(const_base->u32 & ~const_bitmask->u32);
2409          } else {
2410             base = bld.sop2(aco_opcode::s_andn2_b32, bld.def(s1), bld.def(s1, scc), base, bitmask);
2411             rhs = Operand(base);
2412          }
2413
2414          bld.sop2(aco_opcode::s_or_b32, Definition(dst), bld.def(s1, scc), rhs, lhs);
2415
2416       } else if (dst.regClass() == v1) {
2417          if (base.type() == RegType::sgpr && (bitmask.type() == RegType::sgpr || (insert.type() == RegType::sgpr)))
2418             base = as_vgpr(ctx, base);
2419          if (insert.type() == RegType::sgpr && bitmask.type() == RegType::sgpr)
2420             insert = as_vgpr(ctx, insert);
2421
2422          bld.vop3(aco_opcode::v_bfi_b32, Definition(dst), bitmask, insert, base);
2423
2424       } else {
2425          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2426          nir_print_instr(&instr->instr, stderr);
2427          fprintf(stderr, "\n");
2428       }
2429       break;
2430    }
2431    case nir_op_ubfe:
2432    case nir_op_ibfe: {
2433       Temp base = get_alu_src(ctx, instr->src[0]);
2434       Temp offset = get_alu_src(ctx, instr->src[1]);
2435       Temp bits = get_alu_src(ctx, instr->src[2]);
2436
2437       if (dst.type() == RegType::sgpr) {
2438          Operand extract;
2439          nir_const_value* const_offset = nir_src_as_const_value(instr->src[1].src);
2440          nir_const_value* const_bits = nir_src_as_const_value(instr->src[2].src);
2441          if (const_offset && const_bits) {
2442             uint32_t const_extract = (const_bits->u32 << 16) | const_offset->u32;
2443             extract = Operand(const_extract);
2444          } else {
2445             Operand width;
2446             if (const_bits) {
2447                width = Operand(const_bits->u32 << 16);
2448             } else {
2449                width = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), bits, Operand(16u));
2450             }
2451             extract = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), offset, width);
2452          }
2453
2454          aco_opcode opcode;
2455          if (dst.regClass() == s1) {
2456             if (instr->op == nir_op_ubfe)
2457                opcode = aco_opcode::s_bfe_u32;
2458             else
2459                opcode = aco_opcode::s_bfe_i32;
2460          } else if (dst.regClass() == s2) {
2461             if (instr->op == nir_op_ubfe)
2462                opcode = aco_opcode::s_bfe_u64;
2463             else
2464                opcode = aco_opcode::s_bfe_i64;
2465          } else {
2466             unreachable("Unsupported BFE bit size");
2467          }
2468
2469          bld.sop2(opcode, Definition(dst), bld.def(s1, scc), base, extract);
2470
2471       } else {
2472          aco_opcode opcode;
2473          if (dst.regClass() == v1) {
2474             if (instr->op == nir_op_ubfe)
2475                opcode = aco_opcode::v_bfe_u32;
2476             else
2477                opcode = aco_opcode::v_bfe_i32;
2478          } else {
2479             unreachable("Unsupported BFE bit size");
2480          }
2481
2482          emit_vop3a_instruction(ctx, instr, opcode, dst);
2483       }
2484       break;
2485    }
2486    case nir_op_bit_count: {
2487       Temp src = get_alu_src(ctx, instr->src[0]);
2488       if (src.regClass() == s1) {
2489          bld.sop1(aco_opcode::s_bcnt1_i32_b32, Definition(dst), bld.def(s1, scc), src);
2490       } else if (src.regClass() == v1) {
2491          bld.vop3(aco_opcode::v_bcnt_u32_b32, Definition(dst), src, Operand(0u));
2492       } else if (src.regClass() == v2) {
2493          bld.vop3(aco_opcode::v_bcnt_u32_b32, Definition(dst),
2494                   emit_extract_vector(ctx, src, 1, v1),
2495                   bld.vop3(aco_opcode::v_bcnt_u32_b32, bld.def(v1),
2496                            emit_extract_vector(ctx, src, 0, v1), Operand(0u)));
2497       } else if (src.regClass() == s2) {
2498          bld.sop1(aco_opcode::s_bcnt1_i32_b64, Definition(dst), bld.def(s1, scc), src);
2499       } else {
2500          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2501          nir_print_instr(&instr->instr, stderr);
2502          fprintf(stderr, "\n");
2503       }
2504       break;
2505    }
2506    case nir_op_flt: {
2507       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_f32, aco_opcode::v_cmp_lt_f64);
2508       break;
2509    }
2510    case nir_op_fge: {
2511       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_f32, aco_opcode::v_cmp_ge_f64);
2512       break;
2513    }
2514    case nir_op_feq: {
2515       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_eq_f32, aco_opcode::v_cmp_eq_f64);
2516       break;
2517    }
2518    case nir_op_fne: {
2519       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_neq_f32, aco_opcode::v_cmp_neq_f64);
2520       break;
2521    }
2522    case nir_op_ilt: {
2523       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_i32, aco_opcode::v_cmp_lt_i64, aco_opcode::s_cmp_lt_i32);
2524       break;
2525    }
2526    case nir_op_ige: {
2527       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_i32, aco_opcode::v_cmp_ge_i64, aco_opcode::s_cmp_ge_i32);
2528       break;
2529    }
2530    case nir_op_ieq: {
2531       if (instr->src[0].src.ssa->bit_size == 1)
2532          emit_boolean_logic(ctx, instr, Builder::s_xnor, dst);
2533       else
2534          emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_eq_i32, aco_opcode::v_cmp_eq_i64, aco_opcode::s_cmp_eq_i32,
2535                          ctx->program->chip_class >= GFX8 ? aco_opcode::s_cmp_eq_u64 : aco_opcode::num_opcodes);
2536       break;
2537    }
2538    case nir_op_ine: {
2539       if (instr->src[0].src.ssa->bit_size == 1)
2540          emit_boolean_logic(ctx, instr, Builder::s_xor, dst);
2541       else
2542          emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lg_i32, aco_opcode::v_cmp_lg_i64, aco_opcode::s_cmp_lg_i32,
2543                          ctx->program->chip_class >= GFX8 ? aco_opcode::s_cmp_lg_u64 : aco_opcode::num_opcodes);
2544       break;
2545    }
2546    case nir_op_ult: {
2547       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_u32, aco_opcode::v_cmp_lt_u64, aco_opcode::s_cmp_lt_u32);
2548       break;
2549    }
2550    case nir_op_uge: {
2551       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_u32, aco_opcode::v_cmp_ge_u64, aco_opcode::s_cmp_ge_u32);
2552       break;
2553    }
2554    case nir_op_fddx:
2555    case nir_op_fddy:
2556    case nir_op_fddx_fine:
2557    case nir_op_fddy_fine:
2558    case nir_op_fddx_coarse:
2559    case nir_op_fddy_coarse: {
2560       Temp src = get_alu_src(ctx, instr->src[0]);
2561       uint16_t dpp_ctrl1, dpp_ctrl2;
2562       if (instr->op == nir_op_fddx_fine) {
2563          dpp_ctrl1 = dpp_quad_perm(0, 0, 2, 2);
2564          dpp_ctrl2 = dpp_quad_perm(1, 1, 3, 3);
2565       } else if (instr->op == nir_op_fddy_fine) {
2566          dpp_ctrl1 = dpp_quad_perm(0, 1, 0, 1);
2567          dpp_ctrl2 = dpp_quad_perm(2, 3, 2, 3);
2568       } else {
2569          dpp_ctrl1 = dpp_quad_perm(0, 0, 0, 0);
2570          if (instr->op == nir_op_fddx || instr->op == nir_op_fddx_coarse)
2571             dpp_ctrl2 = dpp_quad_perm(1, 1, 1, 1);
2572          else
2573             dpp_ctrl2 = dpp_quad_perm(2, 2, 2, 2);
2574       }
2575
2576       Temp tmp;
2577       if (ctx->program->chip_class >= GFX8) {
2578          Temp tl = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl1);
2579          tmp = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), src, tl, dpp_ctrl2);
2580       } else {
2581          Temp tl = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl1);
2582          Temp tr = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl2);
2583          tmp = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), tr, tl);
2584       }
2585       emit_wqm(ctx, tmp, dst, true);
2586       break;
2587    }
2588    default:
2589       fprintf(stderr, "Unknown NIR ALU instr: ");
2590       nir_print_instr(&instr->instr, stderr);
2591       fprintf(stderr, "\n");
2592    }
2593 }
2594
2595 void visit_load_const(isel_context *ctx, nir_load_const_instr *instr)
2596 {
2597    Temp dst = get_ssa_temp(ctx, &instr->def);
2598
2599    // TODO: we really want to have the resulting type as this would allow for 64bit literals
2600    // which get truncated the lsb if double and msb if int
2601    // for now, we only use s_mov_b64 with 64bit inline constants
2602    assert(instr->def.num_components == 1 && "Vector load_const should be lowered to scalar.");
2603    assert(dst.type() == RegType::sgpr);
2604
2605    Builder bld(ctx->program, ctx->block);
2606
2607    if (instr->def.bit_size == 1) {
2608       assert(dst.regClass() == bld.lm);
2609       int val = instr->value[0].b ? -1 : 0;
2610       Operand op = bld.lm.size() == 1 ? Operand((uint32_t) val) : Operand((uint64_t) val);
2611       bld.sop1(Builder::s_mov, Definition(dst), op);
2612    } else if (dst.size() == 1) {
2613       bld.copy(Definition(dst), Operand(instr->value[0].u32));
2614    } else {
2615       assert(dst.size() != 1);
2616       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
2617       if (instr->def.bit_size == 64)
2618          for (unsigned i = 0; i < dst.size(); i++)
2619             vec->operands[i] = Operand{(uint32_t)(instr->value[0].u64 >> i * 32)};
2620       else {
2621          for (unsigned i = 0; i < dst.size(); i++)
2622             vec->operands[i] = Operand{instr->value[i].u32};
2623       }
2624       vec->definitions[0] = Definition(dst);
2625       ctx->block->instructions.emplace_back(std::move(vec));
2626    }
2627 }
2628
2629 uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2630 {
2631    uint32_t new_mask = 0;
2632    for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2633       if (mask & (1u << i))
2634          new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2635    return new_mask;
2636 }
2637
2638 Operand load_lds_size_m0(isel_context *ctx)
2639 {
2640    /* TODO: m0 does not need to be initialized on GFX9+ */
2641    Builder bld(ctx->program, ctx->block);
2642    return bld.m0((Temp)bld.sopk(aco_opcode::s_movk_i32, bld.def(s1, m0), 0xffff));
2643 }
2644
2645 Temp load_lds(isel_context *ctx, unsigned elem_size_bytes, Temp dst,
2646               Temp address, unsigned base_offset, unsigned align)
2647 {
2648    assert(util_is_power_of_two_nonzero(align) && align >= 4);
2649
2650    Builder bld(ctx->program, ctx->block);
2651
2652    Operand m = load_lds_size_m0(ctx);
2653
2654    unsigned num_components = dst.size() * 4u / elem_size_bytes;
2655    unsigned bytes_read = 0;
2656    unsigned result_size = 0;
2657    unsigned total_bytes = num_components * elem_size_bytes;
2658    std::array<Temp, NIR_MAX_VEC_COMPONENTS> result;
2659    bool large_ds_read = ctx->options->chip_class >= GFX7;
2660    bool usable_read2 = ctx->options->chip_class >= GFX7;
2661
2662    while (bytes_read < total_bytes) {
2663       unsigned todo = total_bytes - bytes_read;
2664       bool aligned8 = bytes_read % 8 == 0 && align % 8 == 0;
2665       bool aligned16 = bytes_read % 16 == 0 && align % 16 == 0;
2666
2667       aco_opcode op = aco_opcode::last_opcode;
2668       bool read2 = false;
2669       if (todo >= 16 && aligned16 && large_ds_read) {
2670          op = aco_opcode::ds_read_b128;
2671          todo = 16;
2672       } else if (todo >= 16 && aligned8 && usable_read2) {
2673          op = aco_opcode::ds_read2_b64;
2674          read2 = true;
2675          todo = 16;
2676       } else if (todo >= 12 && aligned16 && large_ds_read) {
2677          op = aco_opcode::ds_read_b96;
2678          todo = 12;
2679       } else if (todo >= 8 && aligned8) {
2680          op = aco_opcode::ds_read_b64;
2681          todo = 8;
2682       } else if (todo >= 8 && usable_read2) {
2683          op = aco_opcode::ds_read2_b32;
2684          read2 = true;
2685          todo = 8;
2686       } else if (todo >= 4) {
2687          op = aco_opcode::ds_read_b32;
2688          todo = 4;
2689       } else {
2690          assert(false);
2691       }
2692       assert(todo % elem_size_bytes == 0);
2693       unsigned num_elements = todo / elem_size_bytes;
2694       unsigned offset = base_offset + bytes_read;
2695       unsigned max_offset = read2 ? 1019 : 65535;
2696
2697       Temp address_offset = address;
2698       if (offset > max_offset) {
2699          address_offset = bld.vadd32(bld.def(v1), Operand(base_offset), address_offset);
2700          offset = bytes_read;
2701       }
2702       assert(offset <= max_offset); /* bytes_read shouldn't be large enough for this to happen */
2703
2704       Temp res;
2705       if (num_components == 1 && dst.type() == RegType::vgpr)
2706          res = dst;
2707       else
2708          res = bld.tmp(RegClass(RegType::vgpr, todo / 4));
2709
2710       if (read2)
2711          res = bld.ds(op, Definition(res), address_offset, m, offset / (todo / 2), (offset / (todo / 2)) + 1);
2712       else
2713          res = bld.ds(op, Definition(res), address_offset, m, offset);
2714
2715       if (num_components == 1) {
2716          assert(todo == total_bytes);
2717          if (dst.type() == RegType::sgpr)
2718             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), res);
2719          return dst;
2720       }
2721
2722       if (dst.type() == RegType::sgpr) {
2723          Temp new_res = bld.tmp(RegType::sgpr, res.size());
2724          expand_vector(ctx, res, new_res, res.size(), (1 << res.size()) - 1);
2725          res = new_res;
2726       }
2727
2728       if (num_elements == 1) {
2729          result[result_size++] = res;
2730       } else {
2731          assert(res != dst && res.size() % num_elements == 0);
2732          aco_ptr<Pseudo_instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector, Format::PSEUDO, 1, num_elements)};
2733          split->operands[0] = Operand(res);
2734          for (unsigned i = 0; i < num_elements; i++)
2735             split->definitions[i] = Definition(result[result_size++] = bld.tmp(res.type(), elem_size_bytes / 4));
2736          ctx->block->instructions.emplace_back(std::move(split));
2737       }
2738
2739       bytes_read += todo;
2740    }
2741
2742    assert(result_size == num_components && result_size > 1);
2743    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, result_size, 1)};
2744    for (unsigned i = 0; i < result_size; i++)
2745       vec->operands[i] = Operand(result[i]);
2746    vec->definitions[0] = Definition(dst);
2747    ctx->block->instructions.emplace_back(std::move(vec));
2748    ctx->allocated_vec.emplace(dst.id(), result);
2749
2750    return dst;
2751 }
2752
2753 Temp extract_subvector(isel_context *ctx, Temp data, unsigned start, unsigned size, RegType type)
2754 {
2755    if (start == 0 && size == data.size())
2756       return type == RegType::vgpr ? as_vgpr(ctx, data) : data;
2757
2758    unsigned size_hint = 1;
2759    auto it = ctx->allocated_vec.find(data.id());
2760    if (it != ctx->allocated_vec.end())
2761       size_hint = it->second[0].size();
2762    if (size % size_hint || start % size_hint)
2763       size_hint = 1;
2764
2765    start /= size_hint;
2766    size /= size_hint;
2767
2768    Temp elems[size];
2769    for (unsigned i = 0; i < size; i++)
2770       elems[i] = emit_extract_vector(ctx, data, start + i, RegClass(type, size_hint));
2771
2772    if (size == 1)
2773       return type == RegType::vgpr ? as_vgpr(ctx, elems[0]) : elems[0];
2774
2775    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, size, 1)};
2776    for (unsigned i = 0; i < size; i++)
2777       vec->operands[i] = Operand(elems[i]);
2778    Temp res = {ctx->program->allocateId(), RegClass(type, size * size_hint)};
2779    vec->definitions[0] = Definition(res);
2780    ctx->block->instructions.emplace_back(std::move(vec));
2781    return res;
2782 }
2783
2784 void ds_write_helper(isel_context *ctx, Operand m, Temp address, Temp data, unsigned data_start, unsigned total_size, unsigned offset0, unsigned offset1, unsigned align)
2785 {
2786    Builder bld(ctx->program, ctx->block);
2787    unsigned bytes_written = 0;
2788    bool large_ds_write = ctx->options->chip_class >= GFX7;
2789    bool usable_write2 = ctx->options->chip_class >= GFX7;
2790
2791    while (bytes_written < total_size * 4) {
2792       unsigned todo = total_size * 4 - bytes_written;
2793       bool aligned8 = bytes_written % 8 == 0 && align % 8 == 0;
2794       bool aligned16 = bytes_written % 16 == 0 && align % 16 == 0;
2795
2796       aco_opcode op = aco_opcode::last_opcode;
2797       bool write2 = false;
2798       unsigned size = 0;
2799       if (todo >= 16 && aligned16 && large_ds_write) {
2800          op = aco_opcode::ds_write_b128;
2801          size = 4;
2802       } else if (todo >= 16 && aligned8 && usable_write2) {
2803          op = aco_opcode::ds_write2_b64;
2804          write2 = true;
2805          size = 4;
2806       } else if (todo >= 12 && aligned16 && large_ds_write) {
2807          op = aco_opcode::ds_write_b96;
2808          size = 3;
2809       } else if (todo >= 8 && aligned8) {
2810          op = aco_opcode::ds_write_b64;
2811          size = 2;
2812       } else if (todo >= 8 && usable_write2) {
2813          op = aco_opcode::ds_write2_b32;
2814          write2 = true;
2815          size = 2;
2816       } else if (todo >= 4) {
2817          op = aco_opcode::ds_write_b32;
2818          size = 1;
2819       } else {
2820          assert(false);
2821       }
2822
2823       unsigned offset = offset0 + offset1 + bytes_written;
2824       unsigned max_offset = write2 ? 1020 : 65535;
2825       Temp address_offset = address;
2826       if (offset > max_offset) {
2827          address_offset = bld.vadd32(bld.def(v1), Operand(offset0), address_offset);
2828          offset = offset1 + bytes_written;
2829       }
2830       assert(offset <= max_offset); /* offset1 shouldn't be large enough for this to happen */
2831
2832       if (write2) {
2833          Temp val0 = extract_subvector(ctx, data, data_start + (bytes_written >> 2), size / 2, RegType::vgpr);
2834          Temp val1 = extract_subvector(ctx, data, data_start + (bytes_written >> 2) + 1, size / 2, RegType::vgpr);
2835          bld.ds(op, address_offset, val0, val1, m, offset / size / 2, (offset / size / 2) + 1);
2836       } else {
2837          Temp val = extract_subvector(ctx, data, data_start + (bytes_written >> 2), size, RegType::vgpr);
2838          bld.ds(op, address_offset, val, m, offset);
2839       }
2840
2841       bytes_written += size * 4;
2842    }
2843 }
2844
2845 void store_lds(isel_context *ctx, unsigned elem_size_bytes, Temp data, uint32_t wrmask,
2846                Temp address, unsigned base_offset, unsigned align)
2847 {
2848    assert(util_is_power_of_two_nonzero(align) && align >= 4);
2849    assert(elem_size_bytes == 4 || elem_size_bytes == 8);
2850
2851    Operand m = load_lds_size_m0(ctx);
2852
2853    /* we need at most two stores, assuming that the writemask is at most 4 bits wide */
2854    assert(wrmask <= 0x0f);
2855    int start[2], count[2];
2856    u_bit_scan_consecutive_range(&wrmask, &start[0], &count[0]);
2857    u_bit_scan_consecutive_range(&wrmask, &start[1], &count[1]);
2858    assert(wrmask == 0);
2859
2860    /* one combined store is sufficient */
2861    if (count[0] == count[1] && (align % elem_size_bytes) == 0 && (base_offset % elem_size_bytes) == 0) {
2862       Builder bld(ctx->program, ctx->block);
2863
2864       Temp address_offset = address;
2865       if ((base_offset / elem_size_bytes) + start[1] > 255) {
2866          address_offset = bld.vadd32(bld.def(v1), Operand(base_offset), address_offset);
2867          base_offset = 0;
2868       }
2869
2870       assert(count[0] == 1);
2871       RegClass xtract_rc(RegType::vgpr, elem_size_bytes / 4);
2872
2873       Temp val0 = emit_extract_vector(ctx, data, start[0], xtract_rc);
2874       Temp val1 = emit_extract_vector(ctx, data, start[1], xtract_rc);
2875       aco_opcode op = elem_size_bytes == 4 ? aco_opcode::ds_write2_b32 : aco_opcode::ds_write2_b64;
2876       base_offset = base_offset / elem_size_bytes;
2877       bld.ds(op, address_offset, val0, val1, m,
2878              base_offset + start[0], base_offset + start[1]);
2879       return;
2880    }
2881
2882    for (unsigned i = 0; i < 2; i++) {
2883       if (count[i] == 0)
2884          continue;
2885
2886       unsigned elem_size_words = elem_size_bytes / 4;
2887       ds_write_helper(ctx, m, address, data, start[i] * elem_size_words, count[i] * elem_size_words,
2888                       base_offset, start[i] * elem_size_bytes, align);
2889    }
2890    return;
2891 }
2892
2893 unsigned calculate_lds_alignment(isel_context *ctx, unsigned const_offset)
2894 {
2895    unsigned align = 16;
2896    if (const_offset)
2897       align = std::min(align, 1u << (ffs(const_offset) - 1));
2898
2899    return align;
2900 }
2901
2902
2903 Temp create_vec_from_array(isel_context *ctx, Temp arr[], unsigned cnt, RegType reg_type, unsigned split_cnt = 0u, Temp dst = Temp())
2904 {
2905    Builder bld(ctx->program, ctx->block);
2906
2907    if (!dst.id())
2908       dst = bld.tmp(RegClass(reg_type, cnt * arr[0].size()));
2909
2910    std::array<Temp, NIR_MAX_VEC_COMPONENTS> allocated_vec;
2911    aco_ptr<Pseudo_instruction> instr {create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, cnt, 1)};
2912    instr->definitions[0] = Definition(dst);
2913
2914    for (unsigned i = 0; i < cnt; ++i) {
2915       assert(arr[i].size() == arr[0].size());
2916       allocated_vec[i] = arr[i];
2917       instr->operands[i] = Operand(arr[i]);
2918    }
2919
2920    bld.insert(std::move(instr));
2921
2922    if (split_cnt)
2923       emit_split_vector(ctx, dst, split_cnt);
2924    else
2925       ctx->allocated_vec.emplace(dst.id(), allocated_vec); /* emit_split_vector already does this */
2926
2927    return dst;
2928 }
2929
2930 inline unsigned resolve_excess_vmem_const_offset(Builder &bld, Temp &voffset, unsigned const_offset)
2931 {
2932    if (const_offset >= 4096) {
2933       unsigned excess_const_offset = const_offset / 4096u * 4096u;
2934       const_offset %= 4096u;
2935
2936       if (!voffset.id())
2937          voffset = bld.copy(bld.def(v1), Operand(excess_const_offset));
2938       else if (unlikely(voffset.regClass() == s1))
2939          voffset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), Operand(excess_const_offset), Operand(voffset));
2940       else if (likely(voffset.regClass() == v1))
2941          voffset = bld.vadd32(bld.def(v1), Operand(voffset), Operand(excess_const_offset));
2942       else
2943          unreachable("Unsupported register class of voffset");
2944    }
2945
2946    return const_offset;
2947 }
2948
2949 void emit_single_mubuf_store(isel_context *ctx, Temp descriptor, Temp voffset, Temp soffset, Temp vdata,
2950                              unsigned const_offset = 0u, bool allow_reorder = true, bool slc = false)
2951 {
2952    assert(vdata.id());
2953    assert(vdata.size() != 3 || ctx->program->chip_class != GFX6);
2954    assert(vdata.size() >= 1 && vdata.size() <= 4);
2955
2956    Builder bld(ctx->program, ctx->block);
2957    aco_opcode op = (aco_opcode) ((unsigned) aco_opcode::buffer_store_dword + vdata.size() - 1);
2958    const_offset = resolve_excess_vmem_const_offset(bld, voffset, const_offset);
2959
2960    Operand voffset_op = voffset.id() ? Operand(as_vgpr(ctx, voffset)) : Operand(v1);
2961    Operand soffset_op = soffset.id() ? Operand(soffset) : Operand(0u);
2962    Builder::Result r = bld.mubuf(op, Operand(descriptor), voffset_op, soffset_op, Operand(vdata), const_offset,
2963                                  /* offen */ !voffset_op.isUndefined(), /* idxen*/ false, /* addr64 */ false,
2964                                  /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc);
2965
2966    static_cast<MUBUF_instruction *>(r.instr)->can_reorder = allow_reorder;
2967 }
2968
2969 void store_vmem_mubuf(isel_context *ctx, Temp src, Temp descriptor, Temp voffset, Temp soffset,
2970                                    unsigned base_const_offset, unsigned elem_size_bytes, unsigned write_mask,
2971                                    bool allow_combining = true, bool reorder = true, bool slc = false)
2972 {
2973    Builder bld(ctx->program, ctx->block);
2974    assert(elem_size_bytes == 4 || elem_size_bytes == 8);
2975    assert(write_mask);
2976
2977    if (elem_size_bytes == 8) {
2978       elem_size_bytes = 4;
2979       write_mask = widen_mask(write_mask, 2);
2980    }
2981
2982    while (write_mask) {
2983       int start = 0;
2984       int count = 0;
2985       u_bit_scan_consecutive_range(&write_mask, &start, &count);
2986       assert(count > 0);
2987       assert(start >= 0);
2988
2989       while (count > 0) {
2990          unsigned sub_count = allow_combining ? MIN2(count, 4) : 1;
2991          unsigned const_offset = (unsigned) start * elem_size_bytes + base_const_offset;
2992
2993          /* GFX6 doesn't have buffer_store_dwordx3, so make sure not to emit that here either. */
2994          if (unlikely(ctx->program->chip_class == GFX6 && sub_count == 3))
2995             sub_count = 2;
2996
2997          Temp elem = extract_subvector(ctx, src, start, sub_count, RegType::vgpr);
2998          emit_single_mubuf_store(ctx, descriptor, voffset, soffset, elem, const_offset, reorder, slc);
2999
3000          count -= sub_count;
3001          start += sub_count;
3002       }
3003
3004       assert(count == 0);
3005    }
3006 }
3007
3008 Temp emit_single_mubuf_load(isel_context *ctx, Temp descriptor, Temp voffset, Temp soffset,
3009                             unsigned const_offset, unsigned size_dwords, bool allow_reorder = true)
3010 {
3011    assert(size_dwords != 3 || ctx->program->chip_class != GFX6);
3012    assert(size_dwords >= 1 && size_dwords <= 4);
3013
3014    Builder bld(ctx->program, ctx->block);
3015    Temp vdata = bld.tmp(RegClass(RegType::vgpr, size_dwords));
3016    aco_opcode op = (aco_opcode) ((unsigned) aco_opcode::buffer_load_dword + size_dwords - 1);
3017    const_offset = resolve_excess_vmem_const_offset(bld, voffset, const_offset);
3018
3019    Operand voffset_op = voffset.id() ? Operand(as_vgpr(ctx, voffset)) : Operand(v1);
3020    Operand soffset_op = soffset.id() ? Operand(soffset) : Operand(0u);
3021    Builder::Result r = bld.mubuf(op, Definition(vdata), Operand(descriptor), voffset_op, soffset_op, const_offset,
3022                                  /* offen */ !voffset_op.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3023                                  /* disable_wqm */ false, /* glc */ true,
3024                                  /* dlc*/ ctx->program->chip_class >= GFX10, /* slc */ false);
3025
3026    static_cast<MUBUF_instruction *>(r.instr)->can_reorder = allow_reorder;
3027
3028    return vdata;
3029 }
3030
3031 void load_vmem_mubuf(isel_context *ctx, Temp dst, Temp descriptor, Temp voffset, Temp soffset,
3032                      unsigned base_const_offset, unsigned elem_size_bytes, unsigned num_components,
3033                      unsigned stride = 0u, bool allow_combining = true, bool allow_reorder = true)
3034 {
3035    assert(elem_size_bytes == 4 || elem_size_bytes == 8);
3036    assert((num_components * elem_size_bytes / 4) == dst.size());
3037    assert(!!stride != allow_combining);
3038
3039    Builder bld(ctx->program, ctx->block);
3040    unsigned split_cnt = num_components;
3041
3042    if (elem_size_bytes == 8) {
3043       elem_size_bytes = 4;
3044       num_components *= 2;
3045    }
3046
3047    if (!stride)
3048       stride = elem_size_bytes;
3049
3050    unsigned load_size = 1;
3051    if (allow_combining) {
3052       if ((num_components % 4) == 0)
3053          load_size = 4;
3054       else if ((num_components % 3) == 0 && ctx->program->chip_class != GFX6)
3055          load_size = 3;
3056       else if ((num_components % 2) == 0)
3057          load_size = 2;
3058    }
3059
3060    unsigned num_loads = num_components / load_size;
3061    std::array<Temp, NIR_MAX_VEC_COMPONENTS> elems;
3062
3063    for (unsigned i = 0; i < num_loads; ++i) {
3064       unsigned const_offset = i * stride * load_size + base_const_offset;
3065       elems[i] = emit_single_mubuf_load(ctx, descriptor, voffset, soffset, const_offset, load_size, allow_reorder);
3066    }
3067
3068    create_vec_from_array(ctx, elems.data(), num_loads, RegType::vgpr, split_cnt, dst);
3069 }
3070
3071 std::pair<Temp, unsigned> offset_add_from_nir(isel_context *ctx, const std::pair<Temp, unsigned> &base_offset, nir_src *off_src, unsigned stride = 1u)
3072 {
3073    Builder bld(ctx->program, ctx->block);
3074    Temp offset = base_offset.first;
3075    unsigned const_offset = base_offset.second;
3076
3077    if (!nir_src_is_const(*off_src)) {
3078       Temp indirect_offset_arg = get_ssa_temp(ctx, off_src->ssa);
3079       Temp with_stride;
3080
3081       /* Calculate indirect offset with stride */
3082       if (likely(indirect_offset_arg.regClass() == v1))
3083          with_stride = bld.v_mul_imm(bld.def(v1), indirect_offset_arg, stride);
3084       else if (indirect_offset_arg.regClass() == s1)
3085          with_stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), indirect_offset_arg);
3086       else
3087          unreachable("Unsupported register class of indirect offset");
3088
3089       /* Add to the supplied base offset */
3090       if (offset.id() == 0)
3091          offset = with_stride;
3092       else if (unlikely(offset.regClass() == s1 && with_stride.regClass() == s1))
3093          offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), with_stride, offset);
3094       else if (offset.size() == 1 && with_stride.size() == 1)
3095          offset = bld.vadd32(bld.def(v1), with_stride, offset);
3096       else
3097          unreachable("Unsupported register class of indirect offset");
3098    } else {
3099       unsigned const_offset_arg = nir_src_as_uint(*off_src);
3100       const_offset += const_offset_arg * stride;
3101    }
3102
3103    return std::make_pair(offset, const_offset);
3104 }
3105
3106 std::pair<Temp, unsigned> offset_add(isel_context *ctx, const std::pair<Temp, unsigned> &off1, const std::pair<Temp, unsigned> &off2)
3107 {
3108    Builder bld(ctx->program, ctx->block);
3109    Temp offset;
3110
3111    if (off1.first.id() && off2.first.id()) {
3112       if (unlikely(off1.first.regClass() == s1 && off2.first.regClass() == s1))
3113          offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), off1.first, off2.first);
3114       else if (off1.first.size() == 1 && off2.first.size() == 1)
3115          offset = bld.vadd32(bld.def(v1), off1.first, off2.first);
3116       else
3117          unreachable("Unsupported register class of indirect offset");
3118    } else {
3119       offset = off1.first.id() ? off1.first : off2.first;
3120    }
3121
3122    return std::make_pair(offset, off1.second + off2.second);
3123 }
3124
3125 std::pair<Temp, unsigned> offset_mul(isel_context *ctx, const std::pair<Temp, unsigned> &offs, unsigned multiplier)
3126 {
3127    Builder bld(ctx->program, ctx->block);
3128    unsigned const_offset = offs.second * multiplier;
3129
3130    if (!offs.first.id())
3131       return std::make_pair(offs.first, const_offset);
3132
3133    Temp offset = unlikely(offs.first.regClass() == s1)
3134                  ? bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(multiplier), offs.first)
3135                  : bld.v_mul_imm(bld.def(v1), offs.first, multiplier);
3136
3137    return std::make_pair(offset, const_offset);
3138 }
3139
3140 std::pair<Temp, unsigned> get_intrinsic_io_basic_offset(isel_context *ctx, nir_intrinsic_instr *instr, unsigned base_stride, unsigned component_stride)
3141 {
3142    Builder bld(ctx->program, ctx->block);
3143
3144    /* base is the driver_location, which is already multiplied by 4, so is in dwords */
3145    unsigned const_offset = nir_intrinsic_base(instr) * base_stride;
3146    /* component is in bytes */
3147    const_offset += nir_intrinsic_component(instr) * component_stride;
3148
3149    /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
3150    nir_src *off_src = nir_get_io_offset_src(instr);
3151    return offset_add_from_nir(ctx, std::make_pair(Temp(), const_offset), off_src, 4u * base_stride);
3152 }
3153
3154 std::pair<Temp, unsigned> get_intrinsic_io_basic_offset(isel_context *ctx, nir_intrinsic_instr *instr, unsigned stride = 1u)
3155 {
3156    return get_intrinsic_io_basic_offset(ctx, instr, stride, stride);
3157 }
3158
3159 Temp get_tess_rel_patch_id(isel_context *ctx)
3160 {
3161    Builder bld(ctx->program, ctx->block);
3162
3163    switch (ctx->shader->info.stage) {
3164    case MESA_SHADER_TESS_CTRL:
3165       return bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0xffu),
3166                       get_arg(ctx, ctx->args->ac.tcs_rel_ids));
3167    case MESA_SHADER_TESS_EVAL:
3168       return get_arg(ctx, ctx->args->tes_rel_patch_id);
3169    default:
3170       unreachable("Unsupported stage in get_tess_rel_patch_id");
3171    }
3172 }
3173
3174 std::pair<Temp, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context *ctx, nir_intrinsic_instr *instr)
3175 {
3176    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
3177    Builder bld(ctx->program, ctx->block);
3178
3179    uint32_t tcs_in_patch_stride = ctx->args->options->key.tcs.input_vertices * ctx->tcs_num_inputs * 4;
3180    uint32_t tcs_in_vertex_stride = ctx->tcs_num_inputs * 4;
3181
3182    std::pair<Temp, unsigned> offs = get_intrinsic_io_basic_offset(ctx, instr);
3183
3184    nir_src *vertex_index_src = nir_get_io_vertex_index_src(instr);
3185    offs = offset_add_from_nir(ctx, offs, vertex_index_src, tcs_in_vertex_stride);
3186
3187    Temp rel_patch_id = get_tess_rel_patch_id(ctx);
3188    Temp tcs_in_current_patch_offset = bld.v_mul24_imm(bld.def(v1), rel_patch_id, tcs_in_patch_stride);
3189    offs = offset_add(ctx, offs, std::make_pair(tcs_in_current_patch_offset, 0));
3190
3191    return offset_mul(ctx, offs, 4u);
3192 }
3193
3194 std::pair<Temp, unsigned> get_tcs_output_lds_offset(isel_context *ctx, nir_intrinsic_instr *instr = nullptr, bool per_vertex = false)
3195 {
3196    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
3197    Builder bld(ctx->program, ctx->block);
3198
3199    uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * ctx->tcs_num_inputs * 16;
3200    uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
3201    uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->args->shader_info->tcs.patch_outputs_written);
3202    uint32_t output_vertex_size = num_tcs_outputs * 16;
3203    uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
3204    uint32_t output_patch_stride = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
3205
3206    std::pair<Temp, unsigned> offs = instr
3207                                     ? get_intrinsic_io_basic_offset(ctx, instr, 4u)
3208                                     : std::make_pair(Temp(), 0u);
3209
3210    Temp rel_patch_id = get_tess_rel_patch_id(ctx);
3211    Temp patch_off = bld.v_mul24_imm(bld.def(v1), rel_patch_id, output_patch_stride);
3212
3213    if (per_vertex) {
3214       assert(instr);
3215
3216       nir_src *vertex_index_src = nir_get_io_vertex_index_src(instr);
3217       offs = offset_add_from_nir(ctx, offs, vertex_index_src, output_vertex_size);
3218
3219       uint32_t output_patch0_offset = (input_patch_size * ctx->tcs_num_patches);
3220       offs = offset_add(ctx, offs, std::make_pair(patch_off, output_patch0_offset));
3221    } else {
3222       uint32_t output_patch0_patch_data_offset = (input_patch_size * ctx->tcs_num_patches + pervertex_output_patch_size);
3223       offs = offset_add(ctx, offs, std::make_pair(patch_off, output_patch0_patch_data_offset));
3224    }
3225
3226    return offs;
3227 }
3228
3229 std::pair<Temp, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context *ctx, nir_intrinsic_instr *instr)
3230 {
3231    Builder bld(ctx->program, ctx->block);
3232
3233    unsigned vertices_per_patch = ctx->shader->info.tess.tcs_vertices_out;
3234    unsigned attr_stride = vertices_per_patch * ctx->tcs_num_patches;
3235
3236    std::pair<Temp, unsigned> offs = get_intrinsic_io_basic_offset(ctx, instr, attr_stride * 4u, 4u);
3237
3238    Temp rel_patch_id = get_tess_rel_patch_id(ctx);
3239    Temp patch_off = bld.v_mul24_imm(bld.def(v1), rel_patch_id, vertices_per_patch * 16u);
3240    offs = offset_add(ctx, offs, std::make_pair(patch_off, 0u));
3241
3242    nir_src *vertex_index_src = nir_get_io_vertex_index_src(instr);
3243    offs = offset_add_from_nir(ctx, offs, vertex_index_src, 16u);
3244
3245    return offs;
3246 }
3247
3248 std::pair<Temp, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context *ctx, nir_intrinsic_instr *instr = nullptr, unsigned const_base_offset = 0u)
3249 {
3250    Builder bld(ctx->program, ctx->block);
3251
3252    unsigned num_tcs_outputs = ctx->shader->info.stage == MESA_SHADER_TESS_CTRL
3253                               ? util_last_bit64(ctx->args->shader_info->tcs.outputs_written)
3254                               : ctx->args->options->key.tes.tcs_num_outputs;
3255
3256    unsigned output_vertex_size = num_tcs_outputs * 16;
3257    unsigned per_vertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
3258    unsigned per_patch_data_offset = per_vertex_output_patch_size * ctx->tcs_num_patches;
3259    unsigned attr_stride = ctx->tcs_num_patches;
3260
3261    std::pair<Temp, unsigned> offs = instr
3262                                     ? get_intrinsic_io_basic_offset(ctx, instr, attr_stride * 4u, 4u)
3263                                     : std::make_pair(Temp(), 0u);
3264
3265    if (const_base_offset)
3266       offs.second += const_base_offset * attr_stride;
3267
3268    Temp rel_patch_id = get_tess_rel_patch_id(ctx);
3269    Temp patch_off = bld.v_mul_imm(bld.def(v1), rel_patch_id, 16u);
3270    offs = offset_add(ctx, offs, std::make_pair(patch_off, per_patch_data_offset));
3271
3272    return offs;
3273 }
3274
3275 bool tcs_driver_location_matches_api_mask(isel_context *ctx, nir_intrinsic_instr *instr, bool per_vertex, uint64_t mask, bool *indirect)
3276 {
3277    unsigned off = nir_intrinsic_base(instr) * 4u;
3278    nir_src *off_src = nir_get_io_offset_src(instr);
3279
3280    if (!nir_src_is_const(*off_src)) {
3281       *indirect = true;
3282       return false;
3283    }
3284
3285    *indirect = false;
3286    off += nir_src_as_uint(*off_src) * 16u;
3287
3288    while (mask) {
3289       unsigned slot = u_bit_scan64(&mask) + (per_vertex ? 0 : VARYING_SLOT_PATCH0);
3290       if (off == shader_io_get_unique_index((gl_varying_slot) slot) * 16u)
3291          return true;
3292    }
3293
3294    return false;
3295 }
3296
3297 void visit_store_ls_or_es_output(isel_context *ctx, nir_intrinsic_instr *instr)
3298 {
3299    Builder bld(ctx->program, ctx->block);
3300
3301    std::pair<Temp, unsigned> offs = get_intrinsic_io_basic_offset(ctx, instr, 4u);
3302    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
3303    unsigned write_mask = nir_intrinsic_write_mask(instr);
3304    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8u;
3305
3306    if (ctx->stage == vertex_es || ctx->stage == tess_eval_es) {
3307       /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
3308       Temp esgs_ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_ESGS_VS * 16u));
3309       Temp es2gs_offset = get_arg(ctx, ctx->args->es2gs_offset);
3310       store_vmem_mubuf(ctx, src, esgs_ring, offs.first, es2gs_offset, offs.second, elem_size_bytes, write_mask, false, true, true);
3311    } else {
3312       Temp lds_base;
3313
3314       if (ctx->stage == vertex_geometry_gs || ctx->stage == tess_eval_geometry_gs) {
3315          /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
3316          unsigned itemsize = ctx->stage == vertex_geometry_gs
3317                              ? ctx->program->info->vs.es_info.esgs_itemsize
3318                              : ctx->program->info->tes.es_info.esgs_itemsize;
3319          Temp thread_id = emit_mbcnt(ctx, bld.def(v1));
3320          Temp wave_idx = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), get_arg(ctx, ctx->args->merged_wave_info), Operand(4u << 16 | 24));
3321          Temp vertex_idx = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), thread_id,
3322                                bld.v_mul24_imm(bld.def(v1), as_vgpr(ctx, wave_idx), ctx->program->wave_size));
3323          lds_base = bld.v_mul24_imm(bld.def(v1), vertex_idx, itemsize);
3324       } else if (ctx->stage == vertex_ls || ctx->stage == vertex_tess_control_hs) {
3325          /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
3326           * GFX9+: LS is merged into HS, but still uses the same LDS layout.
3327           */
3328          unsigned num_tcs_inputs = util_last_bit64(ctx->args->shader_info->vs.ls_outputs_written);
3329          Temp vertex_idx = get_arg(ctx, ctx->args->rel_auto_id);
3330          lds_base = bld.v_mul_imm(bld.def(v1), vertex_idx, num_tcs_inputs * 16u);
3331       } else {
3332          unreachable("Invalid LS or ES stage");
3333       }
3334
3335       offs = offset_add(ctx, offs, std::make_pair(lds_base, 0u));
3336       unsigned lds_align = calculate_lds_alignment(ctx, offs.second);
3337       store_lds(ctx, elem_size_bytes, src, write_mask, offs.first, offs.second, lds_align);
3338    }
3339 }
3340
3341 bool should_write_tcs_patch_output_to_vmem(isel_context *ctx, nir_intrinsic_instr *instr)
3342 {
3343    unsigned off = nir_intrinsic_base(instr) * 4u;
3344    return off != ctx->tcs_tess_lvl_out_loc &&
3345           off != ctx->tcs_tess_lvl_in_loc;
3346 }
3347
3348 bool should_write_tcs_output_to_lds(isel_context *ctx, nir_intrinsic_instr *instr, bool per_vertex)
3349 {
3350    /* When none of the appropriate outputs are read, we are OK to never write to LDS */
3351    if (per_vertex ? ctx->shader->info.outputs_read == 0U : ctx->shader->info.patch_outputs_read == 0u)
3352       return false;
3353
3354    uint64_t mask = per_vertex
3355                    ? ctx->shader->info.outputs_read
3356                    : ctx->shader->info.patch_outputs_read;
3357    bool indirect_write;
3358    bool output_read = tcs_driver_location_matches_api_mask(ctx, instr, per_vertex, mask, &indirect_write);
3359    return indirect_write || output_read;
3360 }
3361
3362 void visit_store_tcs_output(isel_context *ctx, nir_intrinsic_instr *instr, bool per_vertex)
3363 {
3364    assert(ctx->stage == tess_control_hs || ctx->stage == vertex_tess_control_hs);
3365    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
3366
3367    Builder bld(ctx->program, ctx->block);
3368
3369    Temp store_val = get_ssa_temp(ctx, instr->src[0].ssa);
3370    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
3371    unsigned write_mask = nir_intrinsic_write_mask(instr);
3372
3373    /* Only write to VMEM if the output is per-vertex or it's per-patch non tess factor */
3374    bool write_to_vmem = per_vertex || should_write_tcs_patch_output_to_vmem(ctx, instr);
3375    /* Only write to LDS if the output is read by the shader, or it's per-patch tess factor */
3376    bool write_to_lds = !write_to_vmem || should_write_tcs_output_to_lds(ctx, instr, per_vertex);
3377
3378    if (write_to_vmem) {
3379       std::pair<Temp, unsigned> vmem_offs = per_vertex
3380                                             ? get_tcs_per_vertex_output_vmem_offset(ctx, instr)
3381                                             : get_tcs_per_patch_output_vmem_offset(ctx, instr);
3382
3383       Temp hs_ring_tess_offchip = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_HS_TESS_OFFCHIP * 16u));
3384       Temp oc_lds = get_arg(ctx, ctx->args->oc_lds);
3385       store_vmem_mubuf(ctx, store_val, hs_ring_tess_offchip, vmem_offs.first, oc_lds, vmem_offs.second, elem_size_bytes, write_mask, true, false);
3386    }
3387
3388    if (write_to_lds) {
3389       std::pair<Temp, unsigned> lds_offs = get_tcs_output_lds_offset(ctx, instr, per_vertex);
3390       unsigned lds_align = calculate_lds_alignment(ctx, lds_offs.second);
3391       store_lds(ctx, elem_size_bytes, store_val, write_mask, lds_offs.first, lds_offs.second, lds_align);
3392    }
3393 }
3394
3395 void visit_load_tcs_output(isel_context *ctx, nir_intrinsic_instr *instr, bool per_vertex)
3396 {
3397    assert(ctx->stage == tess_control_hs || ctx->stage == vertex_tess_control_hs);
3398    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
3399
3400    Builder bld(ctx->program, ctx->block);
3401
3402    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3403    std::pair<Temp, unsigned> lds_offs = get_tcs_output_lds_offset(ctx, instr, per_vertex);
3404    unsigned lds_align = calculate_lds_alignment(ctx, lds_offs.second);
3405    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
3406
3407    load_lds(ctx, elem_size_bytes, dst, lds_offs.first, lds_offs.second, lds_align);
3408 }
3409
3410 void visit_store_output(isel_context *ctx, nir_intrinsic_instr *instr)
3411 {
3412    if (ctx->stage == vertex_vs ||
3413        ctx->stage == tess_eval_vs ||
3414        ctx->stage == fragment_fs ||
3415        ctx->shader->info.stage == MESA_SHADER_GEOMETRY) {
3416       unsigned write_mask = nir_intrinsic_write_mask(instr);
3417       unsigned component = nir_intrinsic_component(instr);
3418       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
3419       unsigned idx = nir_intrinsic_base(instr) + component;
3420
3421       nir_instr *off_instr = instr->src[1].ssa->parent_instr;
3422       if (off_instr->type != nir_instr_type_load_const) {
3423          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
3424          nir_print_instr(off_instr, stderr);
3425          fprintf(stderr, "\n");
3426       }
3427       idx += nir_instr_as_load_const(off_instr)->value[0].u32 * 4u;
3428
3429       if (instr->src[0].ssa->bit_size == 64)
3430          write_mask = widen_mask(write_mask, 2);
3431
3432       for (unsigned i = 0; i < 8; ++i) {
3433          if (write_mask & (1 << i)) {
3434             ctx->outputs.mask[idx / 4u] |= 1 << (idx % 4u);
3435             ctx->outputs.outputs[idx / 4u][idx % 4u] = emit_extract_vector(ctx, src, i, v1);
3436          }
3437          idx++;
3438       }
3439    } else if (ctx->stage == vertex_es ||
3440               ctx->stage == vertex_ls ||
3441               ctx->stage == tess_eval_es ||
3442               (ctx->stage == vertex_tess_control_hs && ctx->shader->info.stage == MESA_SHADER_VERTEX) ||
3443               (ctx->stage == vertex_geometry_gs && ctx->shader->info.stage == MESA_SHADER_VERTEX) ||
3444               (ctx->stage == tess_eval_geometry_gs && ctx->shader->info.stage == MESA_SHADER_TESS_EVAL)) {
3445       visit_store_ls_or_es_output(ctx, instr);
3446    } else if (ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) {
3447       visit_store_tcs_output(ctx, instr, false);
3448    } else {
3449       unreachable("Shader stage not implemented");
3450    }
3451 }
3452
3453 void visit_load_output(isel_context *ctx, nir_intrinsic_instr *instr)
3454 {
3455    visit_load_tcs_output(ctx, instr, false);
3456 }
3457
3458 void emit_interp_instr(isel_context *ctx, unsigned idx, unsigned component, Temp src, Temp dst, Temp prim_mask)
3459 {
3460    Temp coord1 = emit_extract_vector(ctx, src, 0, v1);
3461    Temp coord2 = emit_extract_vector(ctx, src, 1, v1);
3462
3463    Builder bld(ctx->program, ctx->block);
3464    Builder::Result interp_p1 = bld.vintrp(aco_opcode::v_interp_p1_f32, bld.def(v1), coord1, bld.m0(prim_mask), idx, component);
3465    if (ctx->program->has_16bank_lds)
3466       interp_p1.instr->operands[0].setLateKill(true);
3467    bld.vintrp(aco_opcode::v_interp_p2_f32, Definition(dst), coord2, bld.m0(prim_mask), interp_p1, idx, component);
3468 }
3469
3470 void emit_load_frag_coord(isel_context *ctx, Temp dst, unsigned num_components)
3471 {
3472    aco_ptr<Pseudo_instruction> vec(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1));
3473    for (unsigned i = 0; i < num_components; i++)
3474       vec->operands[i] = Operand(get_arg(ctx, ctx->args->ac.frag_pos[i]));
3475    if (G_0286CC_POS_W_FLOAT_ENA(ctx->program->config->spi_ps_input_ena)) {
3476       assert(num_components == 4);
3477       Builder bld(ctx->program, ctx->block);
3478       vec->operands[3] = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), get_arg(ctx, ctx->args->ac.frag_pos[3]));
3479    }
3480
3481    for (Operand& op : vec->operands)
3482       op = op.isUndefined() ? Operand(0u) : op;
3483
3484    vec->definitions[0] = Definition(dst);
3485    ctx->block->instructions.emplace_back(std::move(vec));
3486    emit_split_vector(ctx, dst, num_components);
3487    return;
3488 }
3489
3490 void visit_load_interpolated_input(isel_context *ctx, nir_intrinsic_instr *instr)
3491 {
3492    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3493    Temp coords = get_ssa_temp(ctx, instr->src[0].ssa);
3494    unsigned idx = nir_intrinsic_base(instr);
3495    unsigned component = nir_intrinsic_component(instr);
3496    Temp prim_mask = get_arg(ctx, ctx->args->ac.prim_mask);
3497
3498    nir_const_value* offset = nir_src_as_const_value(instr->src[1]);
3499    if (offset) {
3500       assert(offset->u32 == 0);
3501    } else {
3502       /* the lower 15bit of the prim_mask contain the offset into LDS
3503        * while the upper bits contain the number of prims */
3504       Temp offset_src = get_ssa_temp(ctx, instr->src[1].ssa);
3505       assert(offset_src.regClass() == s1 && "TODO: divergent offsets...");
3506       Builder bld(ctx->program, ctx->block);
3507       Temp stride = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), prim_mask, Operand(16u));
3508       stride = bld.sop1(aco_opcode::s_bcnt1_i32_b32, bld.def(s1), bld.def(s1, scc), stride);
3509       stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, Operand(48u));
3510       offset_src = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, offset_src);
3511       prim_mask = bld.sop2(aco_opcode::s_add_i32, bld.def(s1, m0), bld.def(s1, scc), offset_src, prim_mask);
3512    }
3513
3514    if (instr->dest.ssa.num_components == 1) {
3515       emit_interp_instr(ctx, idx, component, coords, dst, prim_mask);
3516    } else {
3517       aco_ptr<Pseudo_instruction> vec(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.ssa.num_components, 1));
3518       for (unsigned i = 0; i < instr->dest.ssa.num_components; i++)
3519       {
3520          Temp tmp = {ctx->program->allocateId(), v1};
3521          emit_interp_instr(ctx, idx, component+i, coords, tmp, prim_mask);
3522          vec->operands[i] = Operand(tmp);
3523       }
3524       vec->definitions[0] = Definition(dst);
3525       ctx->block->instructions.emplace_back(std::move(vec));
3526    }
3527 }
3528
3529 bool check_vertex_fetch_size(isel_context *ctx, const ac_data_format_info *vtx_info,
3530                              unsigned offset, unsigned stride, unsigned channels)
3531 {
3532    unsigned vertex_byte_size = vtx_info->chan_byte_size * channels;
3533    if (vtx_info->chan_byte_size != 4 && channels == 3)
3534       return false;
3535    return (ctx->options->chip_class != GFX6 && ctx->options->chip_class != GFX10) ||
3536           (offset % vertex_byte_size == 0 && stride % vertex_byte_size == 0);
3537 }
3538
3539 uint8_t get_fetch_data_format(isel_context *ctx, const ac_data_format_info *vtx_info,
3540                               unsigned offset, unsigned stride, unsigned *channels)
3541 {
3542    if (!vtx_info->chan_byte_size) {
3543       *channels = vtx_info->num_channels;
3544       return vtx_info->chan_format;
3545    }
3546
3547    unsigned num_channels = *channels;
3548    if (!check_vertex_fetch_size(ctx, vtx_info, offset, stride, *channels)) {
3549       unsigned new_channels = num_channels + 1;
3550       /* first, assume more loads is worse and try using a larger data format */
3551       while (new_channels <= 4 && !check_vertex_fetch_size(ctx, vtx_info, offset, stride, new_channels)) {
3552          new_channels++;
3553          /* don't make the attribute potentially out-of-bounds */
3554          if (offset + new_channels * vtx_info->chan_byte_size > stride)
3555             new_channels = 5;
3556       }
3557
3558       if (new_channels == 5) {
3559          /* then try decreasing load size (at the cost of more loads) */
3560          new_channels = *channels;
3561          while (new_channels > 1 && !check_vertex_fetch_size(ctx, vtx_info, offset, stride, new_channels))
3562             new_channels--;
3563       }
3564
3565       if (new_channels < *channels)
3566          *channels = new_channels;
3567       num_channels = new_channels;
3568    }
3569
3570    switch (vtx_info->chan_format) {
3571    case V_008F0C_BUF_DATA_FORMAT_8:
3572       return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8, V_008F0C_BUF_DATA_FORMAT_8_8,
3573                          V_008F0C_BUF_DATA_FORMAT_INVALID, V_008F0C_BUF_DATA_FORMAT_8_8_8_8}[num_channels - 1];
3574    case V_008F0C_BUF_DATA_FORMAT_16:
3575       return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16, V_008F0C_BUF_DATA_FORMAT_16_16,
3576                          V_008F0C_BUF_DATA_FORMAT_INVALID, V_008F0C_BUF_DATA_FORMAT_16_16_16_16}[num_channels - 1];
3577    case V_008F0C_BUF_DATA_FORMAT_32:
3578       return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32, V_008F0C_BUF_DATA_FORMAT_32_32,
3579                          V_008F0C_BUF_DATA_FORMAT_32_32_32, V_008F0C_BUF_DATA_FORMAT_32_32_32_32}[num_channels - 1];
3580    }
3581    unreachable("shouldn't reach here");
3582    return V_008F0C_BUF_DATA_FORMAT_INVALID;
3583 }
3584
3585 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
3586  * so we may need to fix it up. */
3587 Temp adjust_vertex_fetch_alpha(isel_context *ctx, unsigned adjustment, Temp alpha)
3588 {
3589    Builder bld(ctx->program, ctx->block);
3590
3591    if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
3592       alpha = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), alpha);
3593
3594    /* For the integer-like cases, do a natural sign extension.
3595     *
3596     * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
3597     * and happen to contain 0, 1, 2, 3 as the two LSBs of the
3598     * exponent.
3599     */
3600    alpha = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(adjustment == RADV_ALPHA_ADJUST_SNORM ? 7u : 30u), alpha);
3601    alpha = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(30u), alpha);
3602
3603    /* Convert back to the right type. */
3604    if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
3605       alpha = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), alpha);
3606       Temp clamp = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0xbf800000u), alpha);
3607       alpha = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xbf800000u), alpha, clamp);
3608    } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
3609       alpha = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), alpha);
3610    }
3611
3612    return alpha;
3613 }
3614
3615 void visit_load_input(isel_context *ctx, nir_intrinsic_instr *instr)
3616 {
3617    Builder bld(ctx->program, ctx->block);
3618    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3619    if (ctx->shader->info.stage == MESA_SHADER_VERTEX) {
3620
3621       nir_instr *off_instr = instr->src[0].ssa->parent_instr;
3622       if (off_instr->type != nir_instr_type_load_const) {
3623          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
3624          nir_print_instr(off_instr, stderr);
3625          fprintf(stderr, "\n");
3626       }
3627       uint32_t offset = nir_instr_as_load_const(off_instr)->value[0].u32;
3628
3629       Temp vertex_buffers = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->vertex_buffers));
3630
3631       unsigned location = nir_intrinsic_base(instr) / 4 - VERT_ATTRIB_GENERIC0 + offset;
3632       unsigned component = nir_intrinsic_component(instr);
3633       unsigned attrib_binding = ctx->options->key.vs.vertex_attribute_bindings[location];
3634       uint32_t attrib_offset = ctx->options->key.vs.vertex_attribute_offsets[location];
3635       uint32_t attrib_stride = ctx->options->key.vs.vertex_attribute_strides[location];
3636       unsigned attrib_format = ctx->options->key.vs.vertex_attribute_formats[location];
3637
3638       unsigned dfmt = attrib_format & 0xf;
3639       unsigned nfmt = (attrib_format >> 4) & 0x7;
3640       const struct ac_data_format_info *vtx_info = ac_get_data_format_info(dfmt);
3641
3642       unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa) << component;
3643       unsigned num_channels = MIN2(util_last_bit(mask), vtx_info->num_channels);
3644       unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> (location * 2)) & 3;
3645       bool post_shuffle = ctx->options->key.vs.post_shuffle & (1 << location);
3646       if (post_shuffle)
3647          num_channels = MAX2(num_channels, 3);
3648
3649       Operand off = bld.copy(bld.def(s1), Operand(attrib_binding * 16u));
3650       Temp list = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), vertex_buffers, off);
3651
3652       Temp index;
3653       if (ctx->options->key.vs.instance_rate_inputs & (1u << location)) {
3654          uint32_t divisor = ctx->options->key.vs.instance_rate_divisors[location];
3655          Temp start_instance = get_arg(ctx, ctx->args->ac.start_instance);
3656          if (divisor) {
3657             Temp instance_id = get_arg(ctx, ctx->args->ac.instance_id);
3658             if (divisor != 1) {
3659                Temp divided = bld.tmp(v1);
3660                emit_v_div_u32(ctx, divided, as_vgpr(ctx, instance_id), divisor);
3661                index = bld.vadd32(bld.def(v1), start_instance, divided);
3662             } else {
3663                index = bld.vadd32(bld.def(v1), start_instance, instance_id);
3664             }
3665          } else {
3666             index = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), start_instance);
3667          }
3668       } else {
3669          index = bld.vadd32(bld.def(v1),
3670                             get_arg(ctx, ctx->args->ac.base_vertex),
3671                             get_arg(ctx, ctx->args->ac.vertex_id));
3672       }
3673
3674       Temp channels[num_channels];
3675       unsigned channel_start = 0;
3676       bool direct_fetch = false;
3677
3678       /* skip unused channels at the start */
3679       if (vtx_info->chan_byte_size && !post_shuffle) {
3680          channel_start = ffs(mask) - 1;
3681          for (unsigned i = 0; i < channel_start; i++)
3682             channels[i] = Temp(0, s1);
3683       } else if (vtx_info->chan_byte_size && post_shuffle && !(mask & 0x8)) {
3684          num_channels = 3 - (ffs(mask) - 1);
3685       }
3686
3687       /* load channels */
3688       while (channel_start < num_channels) {
3689          unsigned fetch_size = num_channels - channel_start;
3690          unsigned fetch_offset = attrib_offset + channel_start * vtx_info->chan_byte_size;
3691          bool expanded = false;
3692
3693          /* use MUBUF when possible to avoid possible alignment issues */
3694          /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
3695          bool use_mubuf = (nfmt == V_008F0C_BUF_NUM_FORMAT_FLOAT ||
3696                            nfmt == V_008F0C_BUF_NUM_FORMAT_UINT ||
3697                            nfmt == V_008F0C_BUF_NUM_FORMAT_SINT) &&
3698                           vtx_info->chan_byte_size == 4;
3699          unsigned fetch_dfmt = V_008F0C_BUF_DATA_FORMAT_INVALID;
3700          if (!use_mubuf) {
3701             fetch_dfmt = get_fetch_data_format(ctx, vtx_info, fetch_offset, attrib_stride, &fetch_size);
3702          } else {
3703             if (fetch_size == 3 && ctx->options->chip_class == GFX6) {
3704                /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
3705                fetch_size = 4;
3706                expanded = true;
3707             }
3708          }
3709
3710          Temp fetch_index = index;
3711          if (attrib_stride != 0 && fetch_offset > attrib_stride) {
3712             fetch_index = bld.vadd32(bld.def(v1), Operand(fetch_offset / attrib_stride), fetch_index);
3713             fetch_offset = fetch_offset % attrib_stride;
3714          }
3715
3716          Operand soffset(0u);
3717          if (fetch_offset >= 4096) {
3718             soffset = bld.copy(bld.def(s1), Operand(fetch_offset / 4096 * 4096));
3719             fetch_offset %= 4096;
3720          }
3721
3722          aco_opcode opcode;
3723          switch (fetch_size) {
3724          case 1:
3725             opcode = use_mubuf ? aco_opcode::buffer_load_dword : aco_opcode::tbuffer_load_format_x;
3726             break;
3727          case 2:
3728             opcode = use_mubuf ? aco_opcode::buffer_load_dwordx2 : aco_opcode::tbuffer_load_format_xy;
3729             break;
3730          case 3:
3731             assert(ctx->options->chip_class >= GFX7 ||
3732                    (!use_mubuf && ctx->options->chip_class == GFX6));
3733             opcode = use_mubuf ? aco_opcode::buffer_load_dwordx3 : aco_opcode::tbuffer_load_format_xyz;
3734             break;
3735          case 4:
3736             opcode = use_mubuf ? aco_opcode::buffer_load_dwordx4 : aco_opcode::tbuffer_load_format_xyzw;
3737             break;
3738          default:
3739             unreachable("Unimplemented load_input vector size");
3740          }
3741
3742          Temp fetch_dst;
3743          if (channel_start == 0 && fetch_size == dst.size() && !post_shuffle &&
3744              !expanded && (alpha_adjust == RADV_ALPHA_ADJUST_NONE ||
3745                            num_channels <= 3)) {
3746             direct_fetch = true;
3747             fetch_dst = dst;
3748          } else {
3749             fetch_dst = bld.tmp(RegType::vgpr, fetch_size);
3750          }
3751
3752          if (use_mubuf) {
3753             Instruction *mubuf = bld.mubuf(opcode,
3754                                            Definition(fetch_dst), list, fetch_index, soffset,
3755                                            fetch_offset, false, true).instr;
3756             static_cast<MUBUF_instruction*>(mubuf)->can_reorder = true;
3757          } else {
3758             Instruction *mtbuf = bld.mtbuf(opcode,
3759                                            Definition(fetch_dst), list, fetch_index, soffset,
3760                                            fetch_dfmt, nfmt, fetch_offset, false, true).instr;
3761             static_cast<MTBUF_instruction*>(mtbuf)->can_reorder = true;
3762          }
3763
3764          emit_split_vector(ctx, fetch_dst, fetch_dst.size());
3765
3766          if (fetch_size == 1) {
3767             channels[channel_start] = fetch_dst;
3768          } else {
3769             for (unsigned i = 0; i < MIN2(fetch_size, num_channels - channel_start); i++)
3770                channels[channel_start + i] = emit_extract_vector(ctx, fetch_dst, i, v1);
3771          }
3772
3773          channel_start += fetch_size;
3774       }
3775
3776       if (!direct_fetch) {
3777          bool is_float = nfmt != V_008F0C_BUF_NUM_FORMAT_UINT &&
3778                          nfmt != V_008F0C_BUF_NUM_FORMAT_SINT;
3779
3780          static const unsigned swizzle_normal[4] = {0, 1, 2, 3};
3781          static const unsigned swizzle_post_shuffle[4] = {2, 1, 0, 3};
3782          const unsigned *swizzle = post_shuffle ? swizzle_post_shuffle : swizzle_normal;
3783
3784          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
3785          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
3786          unsigned num_temp = 0;
3787          for (unsigned i = 0; i < dst.size(); i++) {
3788             unsigned idx = i + component;
3789             if (swizzle[idx] < num_channels && channels[swizzle[idx]].id()) {
3790                Temp channel = channels[swizzle[idx]];
3791                if (idx == 3 && alpha_adjust != RADV_ALPHA_ADJUST_NONE)
3792                   channel = adjust_vertex_fetch_alpha(ctx, alpha_adjust, channel);
3793                vec->operands[i] = Operand(channel);
3794
3795                num_temp++;
3796                elems[i] = channel;
3797             } else if (is_float && idx == 3) {
3798                vec->operands[i] = Operand(0x3f800000u);
3799             } else if (!is_float && idx == 3) {
3800                vec->operands[i] = Operand(1u);
3801             } else {
3802                vec->operands[i] = Operand(0u);
3803             }
3804          }
3805          vec->definitions[0] = Definition(dst);
3806          ctx->block->instructions.emplace_back(std::move(vec));
3807          emit_split_vector(ctx, dst, dst.size());
3808
3809          if (num_temp == dst.size())
3810             ctx->allocated_vec.emplace(dst.id(), elems);
3811       }
3812    } else if (ctx->shader->info.stage == MESA_SHADER_FRAGMENT) {
3813       unsigned offset_idx = instr->intrinsic == nir_intrinsic_load_input ? 0 : 1;
3814       nir_instr *off_instr = instr->src[offset_idx].ssa->parent_instr;
3815       if (off_instr->type != nir_instr_type_load_const ||
3816           nir_instr_as_load_const(off_instr)->value[0].u32 != 0) {
3817          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
3818          nir_print_instr(off_instr, stderr);
3819          fprintf(stderr, "\n");
3820       }
3821
3822       Temp prim_mask = get_arg(ctx, ctx->args->ac.prim_mask);
3823       nir_const_value* offset = nir_src_as_const_value(instr->src[offset_idx]);
3824       if (offset) {
3825          assert(offset->u32 == 0);
3826       } else {
3827          /* the lower 15bit of the prim_mask contain the offset into LDS
3828           * while the upper bits contain the number of prims */
3829          Temp offset_src = get_ssa_temp(ctx, instr->src[offset_idx].ssa);
3830          assert(offset_src.regClass() == s1 && "TODO: divergent offsets...");
3831          Builder bld(ctx->program, ctx->block);
3832          Temp stride = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), prim_mask, Operand(16u));
3833          stride = bld.sop1(aco_opcode::s_bcnt1_i32_b32, bld.def(s1), bld.def(s1, scc), stride);
3834          stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, Operand(48u));
3835          offset_src = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, offset_src);
3836          prim_mask = bld.sop2(aco_opcode::s_add_i32, bld.def(s1, m0), bld.def(s1, scc), offset_src, prim_mask);
3837       }
3838
3839       unsigned idx = nir_intrinsic_base(instr);
3840       unsigned component = nir_intrinsic_component(instr);
3841       unsigned vertex_id = 2; /* P0 */
3842
3843       if (instr->intrinsic == nir_intrinsic_load_input_vertex) {
3844          nir_const_value* src0 = nir_src_as_const_value(instr->src[0]);
3845          switch (src0->u32) {
3846          case 0:
3847             vertex_id = 2; /* P0 */
3848             break;
3849          case 1:
3850             vertex_id = 0; /* P10 */
3851             break;
3852          case 2:
3853             vertex_id = 1; /* P20 */
3854             break;
3855          default:
3856             unreachable("invalid vertex index");
3857          }
3858       }
3859
3860       if (dst.size() == 1) {
3861          bld.vintrp(aco_opcode::v_interp_mov_f32, Definition(dst), Operand(vertex_id), bld.m0(prim_mask), idx, component);
3862       } else {
3863          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
3864          for (unsigned i = 0; i < dst.size(); i++)
3865             vec->operands[i] = bld.vintrp(aco_opcode::v_interp_mov_f32, bld.def(v1), Operand(vertex_id), bld.m0(prim_mask), idx, component + i);
3866          vec->definitions[0] = Definition(dst);
3867          bld.insert(std::move(vec));
3868       }
3869
3870    } else if (ctx->shader->info.stage == MESA_SHADER_TESS_EVAL) {
3871       Temp ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_HS_TESS_OFFCHIP * 16u));
3872       Temp soffset = get_arg(ctx, ctx->args->oc_lds);
3873       std::pair<Temp, unsigned> offs = get_tcs_per_patch_output_vmem_offset(ctx, instr);
3874       unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8u;
3875
3876       load_vmem_mubuf(ctx, dst, ring, offs.first, soffset, offs.second, elem_size_bytes, instr->dest.ssa.num_components);
3877    } else {
3878       unreachable("Shader stage not implemented");
3879    }
3880 }
3881
3882 std::pair<Temp, unsigned> get_gs_per_vertex_input_offset(isel_context *ctx, nir_intrinsic_instr *instr, unsigned base_stride = 1u)
3883 {
3884    assert(ctx->shader->info.stage == MESA_SHADER_GEOMETRY);
3885
3886    Builder bld(ctx->program, ctx->block);
3887    nir_src *vertex_src = nir_get_io_vertex_index_src(instr);
3888    Temp vertex_offset;
3889
3890    if (!nir_src_is_const(*vertex_src)) {
3891       /* better code could be created, but this case probably doesn't happen
3892        * much in practice */
3893       Temp indirect_vertex = as_vgpr(ctx, get_ssa_temp(ctx, vertex_src->ssa));
3894       for (unsigned i = 0; i < ctx->shader->info.gs.vertices_in; i++) {
3895          Temp elem;
3896
3897          if (ctx->stage == vertex_geometry_gs || ctx->stage == tess_eval_geometry_gs) {
3898             elem = get_arg(ctx, ctx->args->gs_vtx_offset[i / 2u * 2u]);
3899             if (i % 2u)
3900                elem = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(16u), elem);
3901          } else {
3902             elem = get_arg(ctx, ctx->args->gs_vtx_offset[i]);
3903          }
3904
3905          if (vertex_offset.id()) {
3906             Temp cond = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.hint_vcc(bld.def(bld.lm)),
3907                                  Operand(i), indirect_vertex);
3908             vertex_offset = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), vertex_offset, elem, cond);
3909          } else {
3910             vertex_offset = elem;
3911          }
3912       }
3913
3914       if (ctx->stage == vertex_geometry_gs || ctx->stage == tess_eval_geometry_gs)
3915          vertex_offset = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0xffffu), vertex_offset);
3916    } else {
3917       unsigned vertex = nir_src_as_uint(*vertex_src);
3918       if (ctx->stage == vertex_geometry_gs || ctx->stage == tess_eval_geometry_gs)
3919          vertex_offset = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1),
3920                                   get_arg(ctx, ctx->args->gs_vtx_offset[vertex / 2u * 2u]),
3921                                   Operand((vertex % 2u) * 16u), Operand(16u));
3922       else
3923          vertex_offset = get_arg(ctx, ctx->args->gs_vtx_offset[vertex]);
3924    }
3925
3926    std::pair<Temp, unsigned> offs = get_intrinsic_io_basic_offset(ctx, instr, base_stride);
3927    offs = offset_add(ctx, offs, std::make_pair(vertex_offset, 0u));
3928    return offset_mul(ctx, offs, 4u);
3929 }
3930
3931 void visit_load_gs_per_vertex_input(isel_context *ctx, nir_intrinsic_instr *instr)
3932 {
3933    assert(ctx->shader->info.stage == MESA_SHADER_GEOMETRY);
3934
3935    Builder bld(ctx->program, ctx->block);
3936    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3937    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
3938
3939    if (ctx->stage == geometry_gs) {
3940       std::pair<Temp, unsigned> offs = get_gs_per_vertex_input_offset(ctx, instr, ctx->program->wave_size);
3941       Temp ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_ESGS_GS * 16u));
3942       load_vmem_mubuf(ctx, dst, ring, offs.first, Temp(), offs.second, elem_size_bytes, instr->dest.ssa.num_components, 4u * ctx->program->wave_size, false, true);
3943    } else if (ctx->stage == vertex_geometry_gs || ctx->stage == tess_eval_geometry_gs) {
3944       std::pair<Temp, unsigned> offs = get_gs_per_vertex_input_offset(ctx, instr);
3945       unsigned lds_align = calculate_lds_alignment(ctx, offs.second);
3946       load_lds(ctx, elem_size_bytes, dst, offs.first, offs.second, lds_align);
3947    } else {
3948       unreachable("Unsupported GS stage.");
3949    }
3950 }
3951
3952 void visit_load_tcs_per_vertex_input(isel_context *ctx, nir_intrinsic_instr *instr)
3953 {
3954    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
3955
3956    Builder bld(ctx->program, ctx->block);
3957    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3958    std::pair<Temp, unsigned> offs = get_tcs_per_vertex_input_lds_offset(ctx, instr);
3959    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
3960    unsigned lds_align = calculate_lds_alignment(ctx, offs.second);
3961
3962    load_lds(ctx, elem_size_bytes, dst, offs.first, offs.second, lds_align);
3963 }
3964
3965 void visit_load_tes_per_vertex_input(isel_context *ctx, nir_intrinsic_instr *instr)
3966 {
3967    assert(ctx->shader->info.stage == MESA_SHADER_TESS_EVAL);
3968
3969    Builder bld(ctx->program, ctx->block);
3970
3971    Temp ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_HS_TESS_OFFCHIP * 16u));
3972    Temp oc_lds = get_arg(ctx, ctx->args->oc_lds);
3973    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3974
3975    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
3976    std::pair<Temp, unsigned> offs = get_tcs_per_vertex_output_vmem_offset(ctx, instr);
3977
3978    load_vmem_mubuf(ctx, dst, ring, offs.first, oc_lds, offs.second, elem_size_bytes, instr->dest.ssa.num_components, 0u, true, true);
3979 }
3980
3981 void visit_load_per_vertex_input(isel_context *ctx, nir_intrinsic_instr *instr)
3982 {
3983    switch (ctx->shader->info.stage) {
3984    case MESA_SHADER_GEOMETRY:
3985       visit_load_gs_per_vertex_input(ctx, instr);
3986       break;
3987    case MESA_SHADER_TESS_CTRL:
3988       visit_load_tcs_per_vertex_input(ctx, instr);
3989       break;
3990    case MESA_SHADER_TESS_EVAL:
3991       visit_load_tes_per_vertex_input(ctx, instr);
3992       break;
3993    default:
3994       unreachable("Unimplemented shader stage");
3995    }
3996 }
3997
3998 void visit_load_per_vertex_output(isel_context *ctx, nir_intrinsic_instr *instr)
3999 {
4000    visit_load_tcs_output(ctx, instr, true);
4001 }
4002
4003 void visit_store_per_vertex_output(isel_context *ctx, nir_intrinsic_instr *instr)
4004 {
4005    assert(ctx->stage == tess_control_hs || ctx->stage == vertex_tess_control_hs);
4006    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
4007
4008    visit_store_tcs_output(ctx, instr, true);
4009 }
4010
4011 void visit_load_tess_coord(isel_context *ctx, nir_intrinsic_instr *instr)
4012 {
4013    assert(ctx->shader->info.stage == MESA_SHADER_TESS_EVAL);
4014
4015    Builder bld(ctx->program, ctx->block);
4016    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4017
4018    Operand tes_u(get_arg(ctx, ctx->args->tes_u));
4019    Operand tes_v(get_arg(ctx, ctx->args->tes_v));
4020    Operand tes_w(0u);
4021
4022    if (ctx->shader->info.tess.primitive_mode == GL_TRIANGLES) {
4023       Temp tmp = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), tes_u, tes_v);
4024       tmp = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), Operand(0x3f800000u /* 1.0f */), tmp);
4025       tes_w = Operand(tmp);
4026    }
4027
4028    Temp tess_coord = bld.pseudo(aco_opcode::p_create_vector, Definition(dst), tes_u, tes_v, tes_w);
4029    emit_split_vector(ctx, tess_coord, 3);
4030 }
4031
4032 Temp load_desc_ptr(isel_context *ctx, unsigned desc_set)
4033 {
4034    if (ctx->program->info->need_indirect_descriptor_sets) {
4035       Builder bld(ctx->program, ctx->block);
4036       Temp ptr64 = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->descriptor_sets[0]));
4037       Operand off = bld.copy(bld.def(s1), Operand(desc_set << 2));
4038       return bld.smem(aco_opcode::s_load_dword, bld.def(s1), ptr64, off);//, false, false, false);
4039    }
4040
4041    return get_arg(ctx, ctx->args->descriptor_sets[desc_set]);
4042 }
4043
4044
4045 void visit_load_resource(isel_context *ctx, nir_intrinsic_instr *instr)
4046 {
4047    Builder bld(ctx->program, ctx->block);
4048    Temp index = get_ssa_temp(ctx, instr->src[0].ssa);
4049    if (!ctx->divergent_vals[instr->dest.ssa.index])
4050       index = bld.as_uniform(index);
4051    unsigned desc_set = nir_intrinsic_desc_set(instr);
4052    unsigned binding = nir_intrinsic_binding(instr);
4053
4054    Temp desc_ptr;
4055    radv_pipeline_layout *pipeline_layout = ctx->options->layout;
4056    radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
4057    unsigned offset = layout->binding[binding].offset;
4058    unsigned stride;
4059    if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
4060        layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
4061       unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start + layout->binding[binding].dynamic_offset_offset;
4062       desc_ptr = get_arg(ctx, ctx->args->ac.push_constants);
4063       offset = pipeline_layout->push_constant_size + 16 * idx;
4064       stride = 16;
4065    } else {
4066       desc_ptr = load_desc_ptr(ctx, desc_set);
4067       stride = layout->binding[binding].size;
4068    }
4069
4070    nir_const_value* nir_const_index = nir_src_as_const_value(instr->src[0]);
4071    unsigned const_index = nir_const_index ? nir_const_index->u32 : 0;
4072    if (stride != 1) {
4073       if (nir_const_index) {
4074          const_index = const_index * stride;
4075       } else if (index.type() == RegType::vgpr) {
4076          bool index24bit = layout->binding[binding].array_size <= 0x1000000;
4077          index = bld.v_mul_imm(bld.def(v1), index, stride, index24bit);
4078       } else {
4079          index = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), Operand(index));
4080       }
4081    }
4082    if (offset) {
4083       if (nir_const_index) {
4084          const_index = const_index + offset;
4085       } else if (index.type() == RegType::vgpr) {
4086          index = bld.vadd32(bld.def(v1), Operand(offset), index);
4087       } else {
4088          index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset), Operand(index));
4089       }
4090    }
4091
4092    if (nir_const_index && const_index == 0) {
4093       index = desc_ptr;
4094    } else if (index.type() == RegType::vgpr) {
4095       index = bld.vadd32(bld.def(v1),
4096                          nir_const_index ? Operand(const_index) : Operand(index),
4097                          Operand(desc_ptr));
4098    } else {
4099       index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
4100                        nir_const_index ? Operand(const_index) : Operand(index),
4101                        Operand(desc_ptr));
4102    }
4103
4104    bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), index);
4105 }
4106
4107 void load_buffer(isel_context *ctx, unsigned num_components, Temp dst,
4108                  Temp rsrc, Temp offset, bool glc=false, bool readonly=true)
4109 {
4110    Builder bld(ctx->program, ctx->block);
4111
4112    unsigned num_bytes = dst.size() * 4;
4113    bool dlc = glc && ctx->options->chip_class >= GFX10;
4114
4115    aco_opcode op;
4116    if (dst.type() == RegType::vgpr || (ctx->options->chip_class < GFX8 && !readonly)) {
4117       Operand vaddr = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
4118       Operand soffset = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
4119       unsigned const_offset = 0;
4120
4121       Temp lower = Temp();
4122       if (num_bytes > 16) {
4123          assert(num_components == 3 || num_components == 4);
4124          op = aco_opcode::buffer_load_dwordx4;
4125          lower = bld.tmp(v4);
4126          aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
4127          mubuf->definitions[0] = Definition(lower);
4128          mubuf->operands[0] = Operand(rsrc);
4129          mubuf->operands[1] = vaddr;
4130          mubuf->operands[2] = soffset;
4131          mubuf->offen = (offset.type() == RegType::vgpr);
4132          mubuf->glc = glc;
4133          mubuf->dlc = dlc;
4134          mubuf->barrier = readonly ? barrier_none : barrier_buffer;
4135          mubuf->can_reorder = readonly;
4136          bld.insert(std::move(mubuf));
4137          emit_split_vector(ctx, lower, 2);
4138          num_bytes -= 16;
4139          const_offset = 16;
4140       } else if (num_bytes == 12 && ctx->options->chip_class == GFX6) {
4141          /* GFX6 doesn't support loading vec3, expand to vec4. */
4142          num_bytes = 16;
4143       }
4144
4145       switch (num_bytes) {
4146          case 4:
4147             op = aco_opcode::buffer_load_dword;
4148             break;
4149          case 8:
4150             op = aco_opcode::buffer_load_dwordx2;
4151             break;
4152          case 12:
4153             assert(ctx->options->chip_class > GFX6);
4154             op = aco_opcode::buffer_load_dwordx3;
4155             break;
4156          case 16:
4157             op = aco_opcode::buffer_load_dwordx4;
4158             break;
4159          default:
4160             unreachable("Load SSBO not implemented for this size.");
4161       }
4162       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
4163       mubuf->operands[0] = Operand(rsrc);
4164       mubuf->operands[1] = vaddr;
4165       mubuf->operands[2] = soffset;
4166       mubuf->offen = (offset.type() == RegType::vgpr);
4167       mubuf->glc = glc;
4168       mubuf->dlc = dlc;
4169       mubuf->barrier = readonly ? barrier_none : barrier_buffer;
4170       mubuf->can_reorder = readonly;
4171       mubuf->offset = const_offset;
4172       aco_ptr<Instruction> instr = std::move(mubuf);
4173
4174       if (dst.size() > 4) {
4175          assert(lower != Temp());
4176          Temp upper = bld.tmp(RegType::vgpr, dst.size() - lower.size());
4177          instr->definitions[0] = Definition(upper);
4178          bld.insert(std::move(instr));
4179          if (dst.size() == 8)
4180             emit_split_vector(ctx, upper, 2);
4181          instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size() / 2, 1));
4182          instr->operands[0] = Operand(emit_extract_vector(ctx, lower, 0, v2));
4183          instr->operands[1] = Operand(emit_extract_vector(ctx, lower, 1, v2));
4184          instr->operands[2] = Operand(emit_extract_vector(ctx, upper, 0, v2));
4185          if (dst.size() == 8)
4186             instr->operands[3] = Operand(emit_extract_vector(ctx, upper, 1, v2));
4187       } else if (dst.size() == 3 && ctx->options->chip_class == GFX6) {
4188          Temp vec = bld.tmp(v4);
4189          instr->definitions[0] = Definition(vec);
4190          bld.insert(std::move(instr));
4191          emit_split_vector(ctx, vec, 4);
4192
4193          instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, 3, 1));
4194          instr->operands[0] = Operand(emit_extract_vector(ctx, vec, 0, v1));
4195          instr->operands[1] = Operand(emit_extract_vector(ctx, vec, 1, v1));
4196          instr->operands[2] = Operand(emit_extract_vector(ctx, vec, 2, v1));
4197       }
4198
4199       if (dst.type() == RegType::sgpr) {
4200          Temp vec = bld.tmp(RegType::vgpr, dst.size());
4201          instr->definitions[0] = Definition(vec);
4202          bld.insert(std::move(instr));
4203          expand_vector(ctx, vec, dst, num_components, (1 << num_components) - 1);
4204       } else {
4205          instr->definitions[0] = Definition(dst);
4206          bld.insert(std::move(instr));
4207          emit_split_vector(ctx, dst, num_components);
4208       }
4209    } else {
4210       switch (num_bytes) {
4211          case 4:
4212             op = aco_opcode::s_buffer_load_dword;
4213             break;
4214          case 8:
4215             op = aco_opcode::s_buffer_load_dwordx2;
4216             break;
4217          case 12:
4218          case 16:
4219             op = aco_opcode::s_buffer_load_dwordx4;
4220             break;
4221          case 24:
4222          case 32:
4223             op = aco_opcode::s_buffer_load_dwordx8;
4224             break;
4225          default:
4226             unreachable("Load SSBO not implemented for this size.");
4227       }
4228       aco_ptr<SMEM_instruction> load{create_instruction<SMEM_instruction>(op, Format::SMEM, 2, 1)};
4229       load->operands[0] = Operand(rsrc);
4230       load->operands[1] = Operand(bld.as_uniform(offset));
4231       assert(load->operands[1].getTemp().type() == RegType::sgpr);
4232       load->definitions[0] = Definition(dst);
4233       load->glc = glc;
4234       load->dlc = dlc;
4235       load->barrier = readonly ? barrier_none : barrier_buffer;
4236       load->can_reorder = false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
4237       assert(ctx->options->chip_class >= GFX8 || !glc);
4238
4239       /* trim vector */
4240       if (dst.size() == 3) {
4241          Temp vec = bld.tmp(s4);
4242          load->definitions[0] = Definition(vec);
4243          bld.insert(std::move(load));
4244          emit_split_vector(ctx, vec, 4);
4245
4246          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4247                     emit_extract_vector(ctx, vec, 0, s1),
4248                     emit_extract_vector(ctx, vec, 1, s1),
4249                     emit_extract_vector(ctx, vec, 2, s1));
4250       } else if (dst.size() == 6) {
4251          Temp vec = bld.tmp(s8);
4252          load->definitions[0] = Definition(vec);
4253          bld.insert(std::move(load));
4254          emit_split_vector(ctx, vec, 4);
4255
4256          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4257                     emit_extract_vector(ctx, vec, 0, s2),
4258                     emit_extract_vector(ctx, vec, 1, s2),
4259                     emit_extract_vector(ctx, vec, 2, s2));
4260       } else {
4261          bld.insert(std::move(load));
4262       }
4263       emit_split_vector(ctx, dst, num_components);
4264    }
4265 }
4266
4267 void visit_load_ubo(isel_context *ctx, nir_intrinsic_instr *instr)
4268 {
4269    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4270    Temp rsrc = get_ssa_temp(ctx, instr->src[0].ssa);
4271
4272    Builder bld(ctx->program, ctx->block);
4273
4274    nir_intrinsic_instr* idx_instr = nir_instr_as_intrinsic(instr->src[0].ssa->parent_instr);
4275    unsigned desc_set = nir_intrinsic_desc_set(idx_instr);
4276    unsigned binding = nir_intrinsic_binding(idx_instr);
4277    radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
4278
4279    if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
4280       uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
4281                            S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
4282                            S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
4283                            S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
4284       if (ctx->options->chip_class >= GFX10) {
4285          desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
4286                       S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
4287                       S_008F0C_RESOURCE_LEVEL(1);
4288       } else {
4289          desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
4290                       S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
4291       }
4292       Temp upper_dwords = bld.pseudo(aco_opcode::p_create_vector, bld.def(s3),
4293                                      Operand(S_008F04_BASE_ADDRESS_HI(ctx->options->address32_hi)),
4294                                      Operand(0xFFFFFFFFu),
4295                                      Operand(desc_type));
4296       rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
4297                         rsrc, upper_dwords);
4298    } else {
4299       rsrc = convert_pointer_to_64_bit(ctx, rsrc);
4300       rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
4301    }
4302
4303    load_buffer(ctx, instr->num_components, dst, rsrc, get_ssa_temp(ctx, instr->src[1].ssa));
4304 }
4305
4306 void visit_load_push_constant(isel_context *ctx, nir_intrinsic_instr *instr)
4307 {
4308    Builder bld(ctx->program, ctx->block);
4309    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4310
4311    unsigned offset = nir_intrinsic_base(instr);
4312    nir_const_value *index_cv = nir_src_as_const_value(instr->src[0]);
4313    if (index_cv && instr->dest.ssa.bit_size == 32) {
4314
4315       unsigned count = instr->dest.ssa.num_components;
4316       unsigned start = (offset + index_cv->u32) / 4u;
4317       start -= ctx->args->ac.base_inline_push_consts;
4318       if (start + count <= ctx->args->ac.num_inline_push_consts) {
4319          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
4320          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
4321          for (unsigned i = 0; i < count; ++i) {
4322             elems[i] = get_arg(ctx, ctx->args->ac.inline_push_consts[start + i]);
4323             vec->operands[i] = Operand{elems[i]};
4324          }
4325          vec->definitions[0] = Definition(dst);
4326          ctx->block->instructions.emplace_back(std::move(vec));
4327          ctx->allocated_vec.emplace(dst.id(), elems);
4328          return;
4329       }
4330    }
4331
4332    Temp index = bld.as_uniform(get_ssa_temp(ctx, instr->src[0].ssa));
4333    if (offset != 0) // TODO check if index != 0 as well
4334       index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset), index);
4335    Temp ptr = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->ac.push_constants));
4336    Temp vec = dst;
4337    bool trim = false;
4338    aco_opcode op;
4339
4340    switch (dst.size()) {
4341    case 1:
4342       op = aco_opcode::s_load_dword;
4343       break;
4344    case 2:
4345       op = aco_opcode::s_load_dwordx2;
4346       break;
4347    case 3:
4348       vec = bld.tmp(s4);
4349       trim = true;
4350    case 4:
4351       op = aco_opcode::s_load_dwordx4;
4352       break;
4353    case 6:
4354       vec = bld.tmp(s8);
4355       trim = true;
4356    case 8:
4357       op = aco_opcode::s_load_dwordx8;
4358       break;
4359    default:
4360       unreachable("unimplemented or forbidden load_push_constant.");
4361    }
4362
4363    bld.smem(op, Definition(vec), ptr, index);
4364
4365    if (trim) {
4366       emit_split_vector(ctx, vec, 4);
4367       RegClass rc = dst.size() == 3 ? s1 : s2;
4368       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4369                  emit_extract_vector(ctx, vec, 0, rc),
4370                  emit_extract_vector(ctx, vec, 1, rc),
4371                  emit_extract_vector(ctx, vec, 2, rc));
4372
4373    }
4374    emit_split_vector(ctx, dst, instr->dest.ssa.num_components);
4375 }
4376
4377 void visit_load_constant(isel_context *ctx, nir_intrinsic_instr *instr)
4378 {
4379    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4380
4381    Builder bld(ctx->program, ctx->block);
4382
4383    uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
4384                         S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
4385                         S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
4386                         S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
4387    if (ctx->options->chip_class >= GFX10) {
4388       desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
4389                    S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
4390                    S_008F0C_RESOURCE_LEVEL(1);
4391    } else {
4392       desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
4393                    S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
4394    }
4395
4396    unsigned base = nir_intrinsic_base(instr);
4397    unsigned range = nir_intrinsic_range(instr);
4398
4399    Temp offset = get_ssa_temp(ctx, instr->src[0].ssa);
4400    if (base && offset.type() == RegType::sgpr)
4401       offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), offset, Operand(base));
4402    else if (base && offset.type() == RegType::vgpr)
4403       offset = bld.vadd32(bld.def(v1), Operand(base), offset);
4404
4405    Temp rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
4406                           bld.sop1(aco_opcode::p_constaddr, bld.def(s2), bld.def(s1, scc), Operand(ctx->constant_data_offset)),
4407                           Operand(MIN2(base + range, ctx->shader->constant_data_size)),
4408                           Operand(desc_type));
4409
4410    load_buffer(ctx, instr->num_components, dst, rsrc, offset);
4411 }
4412
4413 void visit_discard_if(isel_context *ctx, nir_intrinsic_instr *instr)
4414 {
4415    if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
4416       ctx->cf_info.exec_potentially_empty_discard = true;
4417
4418    ctx->program->needs_exact = true;
4419
4420    // TODO: optimize uniform conditions
4421    Builder bld(ctx->program, ctx->block);
4422    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
4423    assert(src.regClass() == bld.lm);
4424    src = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
4425    bld.pseudo(aco_opcode::p_discard_if, src);
4426    ctx->block->kind |= block_kind_uses_discard_if;
4427    return;
4428 }
4429
4430 void visit_discard(isel_context* ctx, nir_intrinsic_instr *instr)
4431 {
4432    Builder bld(ctx->program, ctx->block);
4433
4434    if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
4435       ctx->cf_info.exec_potentially_empty_discard = true;
4436
4437    bool divergent = ctx->cf_info.parent_if.is_divergent ||
4438                     ctx->cf_info.parent_loop.has_divergent_continue;
4439
4440    if (ctx->block->loop_nest_depth &&
4441        ((nir_instr_is_last(&instr->instr) && !divergent) || divergent)) {
4442       /* we handle discards the same way as jump instructions */
4443       append_logical_end(ctx->block);
4444
4445       /* in loops, discard behaves like break */
4446       Block *linear_target = ctx->cf_info.parent_loop.exit;
4447       ctx->block->kind |= block_kind_discard;
4448
4449       if (!divergent) {
4450          /* uniform discard - loop ends here */
4451          assert(nir_instr_is_last(&instr->instr));
4452          ctx->block->kind |= block_kind_uniform;
4453          ctx->cf_info.has_branch = true;
4454          bld.branch(aco_opcode::p_branch);
4455          add_linear_edge(ctx->block->index, linear_target);
4456          return;
4457       }
4458
4459       /* we add a break right behind the discard() instructions */
4460       ctx->block->kind |= block_kind_break;
4461       unsigned idx = ctx->block->index;
4462
4463       ctx->cf_info.parent_loop.has_divergent_branch = true;
4464       ctx->cf_info.nir_to_aco[instr->instr.block->index] = idx;
4465
4466       /* remove critical edges from linear CFG */
4467       bld.branch(aco_opcode::p_branch);
4468       Block* break_block = ctx->program->create_and_insert_block();
4469       break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
4470       break_block->kind |= block_kind_uniform;
4471       add_linear_edge(idx, break_block);
4472       add_linear_edge(break_block->index, linear_target);
4473       bld.reset(break_block);
4474       bld.branch(aco_opcode::p_branch);
4475
4476       Block* continue_block = ctx->program->create_and_insert_block();
4477       continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
4478       add_linear_edge(idx, continue_block);
4479       append_logical_start(continue_block);
4480       ctx->block = continue_block;
4481
4482       return;
4483    }
4484
4485    /* it can currently happen that NIR doesn't remove the unreachable code */
4486    if (!nir_instr_is_last(&instr->instr)) {
4487       ctx->program->needs_exact = true;
4488       /* save exec somewhere temporarily so that it doesn't get
4489        * overwritten before the discard from outer exec masks */
4490       Temp cond = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), Operand(0xFFFFFFFF), Operand(exec, bld.lm));
4491       bld.pseudo(aco_opcode::p_discard_if, cond);
4492       ctx->block->kind |= block_kind_uses_discard_if;
4493       return;
4494    }
4495
4496    /* This condition is incorrect for uniformly branched discards in a loop
4497     * predicated by a divergent condition, but the above code catches that case
4498     * and the discard would end up turning into a discard_if.
4499     * For example:
4500     * if (divergent) {
4501     *    while (...) {
4502     *       if (uniform) {
4503     *          discard;
4504     *       }
4505     *    }
4506     * }
4507     */
4508    if (!ctx->cf_info.parent_if.is_divergent) {
4509       /* program just ends here */
4510       ctx->block->kind |= block_kind_uniform;
4511       bld.exp(aco_opcode::exp, Operand(v1), Operand(v1), Operand(v1), Operand(v1),
4512               0 /* enabled mask */, 9 /* dest */,
4513               false /* compressed */, true/* done */, true /* valid mask */);
4514       bld.sopp(aco_opcode::s_endpgm);
4515       // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
4516    } else {
4517       ctx->block->kind |= block_kind_discard;
4518       /* branch and linear edge is added by visit_if() */
4519    }
4520 }
4521
4522 enum aco_descriptor_type {
4523    ACO_DESC_IMAGE,
4524    ACO_DESC_FMASK,
4525    ACO_DESC_SAMPLER,
4526    ACO_DESC_BUFFER,
4527    ACO_DESC_PLANE_0,
4528    ACO_DESC_PLANE_1,
4529    ACO_DESC_PLANE_2,
4530 };
4531
4532 static bool
4533 should_declare_array(isel_context *ctx, enum glsl_sampler_dim sampler_dim, bool is_array) {
4534    if (sampler_dim == GLSL_SAMPLER_DIM_BUF)
4535       return false;
4536    ac_image_dim dim = ac_get_sampler_dim(ctx->options->chip_class, sampler_dim, is_array);
4537    return dim == ac_image_cube ||
4538           dim == ac_image_1darray ||
4539           dim == ac_image_2darray ||
4540           dim == ac_image_2darraymsaa;
4541 }
4542
4543 Temp get_sampler_desc(isel_context *ctx, nir_deref_instr *deref_instr,
4544                       enum aco_descriptor_type desc_type,
4545                       const nir_tex_instr *tex_instr, bool image, bool write)
4546 {
4547 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
4548    std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
4549    if (it != ctx->tex_desc.end())
4550       return it->second;
4551 */
4552    Temp index = Temp();
4553    bool index_set = false;
4554    unsigned constant_index = 0;
4555    unsigned descriptor_set;
4556    unsigned base_index;
4557    Builder bld(ctx->program, ctx->block);
4558
4559    if (!deref_instr) {
4560       assert(tex_instr && !image);
4561       descriptor_set = 0;
4562       base_index = tex_instr->sampler_index;
4563    } else {
4564       while(deref_instr->deref_type != nir_deref_type_var) {
4565          unsigned array_size = glsl_get_aoa_size(deref_instr->type);
4566          if (!array_size)
4567             array_size = 1;
4568
4569          assert(deref_instr->deref_type == nir_deref_type_array);
4570          nir_const_value *const_value = nir_src_as_const_value(deref_instr->arr.index);
4571          if (const_value) {
4572             constant_index += array_size * const_value->u32;
4573          } else {
4574             Temp indirect = get_ssa_temp(ctx, deref_instr->arr.index.ssa);
4575             if (indirect.type() == RegType::vgpr)
4576                indirect = bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), indirect);
4577
4578             if (array_size != 1)
4579                indirect = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(array_size), indirect);
4580
4581             if (!index_set) {
4582                index = indirect;
4583                index_set = true;
4584             } else {
4585                index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), index, indirect);
4586             }
4587          }
4588
4589          deref_instr = nir_src_as_deref(deref_instr->parent);
4590       }
4591       descriptor_set = deref_instr->var->data.descriptor_set;
4592       base_index = deref_instr->var->data.binding;
4593    }
4594
4595    Temp list = load_desc_ptr(ctx, descriptor_set);
4596    list = convert_pointer_to_64_bit(ctx, list);
4597
4598    struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4599    struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4600    unsigned offset = binding->offset;
4601    unsigned stride = binding->size;
4602    aco_opcode opcode;
4603    RegClass type;
4604
4605    assert(base_index < layout->binding_count);
4606
4607    switch (desc_type) {
4608    case ACO_DESC_IMAGE:
4609       type = s8;
4610       opcode = aco_opcode::s_load_dwordx8;
4611       break;
4612    case ACO_DESC_FMASK:
4613       type = s8;
4614       opcode = aco_opcode::s_load_dwordx8;
4615       offset += 32;
4616       break;
4617    case ACO_DESC_SAMPLER:
4618       type = s4;
4619       opcode = aco_opcode::s_load_dwordx4;
4620       if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4621          offset += radv_combined_image_descriptor_sampler_offset(binding);
4622       break;
4623    case ACO_DESC_BUFFER:
4624       type = s4;
4625       opcode = aco_opcode::s_load_dwordx4;
4626       break;
4627    case ACO_DESC_PLANE_0:
4628    case ACO_DESC_PLANE_1:
4629       type = s8;
4630       opcode = aco_opcode::s_load_dwordx8;
4631       offset += 32 * (desc_type - ACO_DESC_PLANE_0);
4632       break;
4633    case ACO_DESC_PLANE_2:
4634       type = s4;
4635       opcode = aco_opcode::s_load_dwordx4;
4636       offset += 64;
4637       break;
4638    default:
4639       unreachable("invalid desc_type\n");
4640    }
4641
4642    offset += constant_index * stride;
4643
4644    if (desc_type == ACO_DESC_SAMPLER && binding->immutable_samplers_offset &&
4645       (!index_set || binding->immutable_samplers_equal)) {
4646       if (binding->immutable_samplers_equal)
4647          constant_index = 0;
4648
4649       const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4650       return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
4651                         Operand(samplers[constant_index * 4 + 0]),
4652                         Operand(samplers[constant_index * 4 + 1]),
4653                         Operand(samplers[constant_index * 4 + 2]),
4654                         Operand(samplers[constant_index * 4 + 3]));
4655    }
4656
4657    Operand off;
4658    if (!index_set) {
4659       off = bld.copy(bld.def(s1), Operand(offset));
4660    } else {
4661       off = Operand((Temp)bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset),
4662                                    bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), index)));
4663    }
4664
4665    Temp res = bld.smem(opcode, bld.def(type), list, off);
4666
4667    if (desc_type == ACO_DESC_PLANE_2) {
4668       Temp components[8];
4669       for (unsigned i = 0; i < 8; i++)
4670          components[i] = bld.tmp(s1);
4671       bld.pseudo(aco_opcode::p_split_vector,
4672                  Definition(components[0]),
4673                  Definition(components[1]),
4674                  Definition(components[2]),
4675                  Definition(components[3]),
4676                  res);
4677
4678       Temp desc2 = get_sampler_desc(ctx, deref_instr, ACO_DESC_PLANE_1, tex_instr, image, write);
4679       bld.pseudo(aco_opcode::p_split_vector,
4680                  bld.def(s1), bld.def(s1), bld.def(s1), bld.def(s1),
4681                  Definition(components[4]),
4682                  Definition(components[5]),
4683                  Definition(components[6]),
4684                  Definition(components[7]),
4685                  desc2);
4686
4687       res = bld.pseudo(aco_opcode::p_create_vector, bld.def(s8),
4688                        components[0], components[1], components[2], components[3],
4689                        components[4], components[5], components[6], components[7]);
4690    }
4691
4692    return res;
4693 }
4694
4695 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
4696 {
4697    switch (dim) {
4698    case GLSL_SAMPLER_DIM_BUF:
4699       return 1;
4700    case GLSL_SAMPLER_DIM_1D:
4701       return array ? 2 : 1;
4702    case GLSL_SAMPLER_DIM_2D:
4703       return array ? 3 : 2;
4704    case GLSL_SAMPLER_DIM_MS:
4705       return array ? 4 : 3;
4706    case GLSL_SAMPLER_DIM_3D:
4707    case GLSL_SAMPLER_DIM_CUBE:
4708       return 3;
4709    case GLSL_SAMPLER_DIM_RECT:
4710    case GLSL_SAMPLER_DIM_SUBPASS:
4711       return 2;
4712    case GLSL_SAMPLER_DIM_SUBPASS_MS:
4713       return 3;
4714    default:
4715       break;
4716    }
4717    return 0;
4718 }
4719
4720
4721 /* Adjust the sample index according to FMASK.
4722  *
4723  * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4724  * which is the identity mapping. Each nibble says which physical sample
4725  * should be fetched to get that sample.
4726  *
4727  * For example, 0x11111100 means there are only 2 samples stored and
4728  * the second sample covers 3/4 of the pixel. When reading samples 0
4729  * and 1, return physical sample 0 (determined by the first two 0s
4730  * in FMASK), otherwise return physical sample 1.
4731  *
4732  * The sample index should be adjusted as follows:
4733  *   sample_index = (fmask >> (sample_index * 4)) & 0xF;
4734  */
4735 static Temp adjust_sample_index_using_fmask(isel_context *ctx, bool da, std::vector<Temp>& coords, Operand sample_index, Temp fmask_desc_ptr)
4736 {
4737    Builder bld(ctx->program, ctx->block);
4738    Temp fmask = bld.tmp(v1);
4739    unsigned dim = ctx->options->chip_class >= GFX10
4740                   ? ac_get_sampler_dim(ctx->options->chip_class, GLSL_SAMPLER_DIM_2D, da)
4741                   : 0;
4742
4743    Temp coord = da ? bld.pseudo(aco_opcode::p_create_vector, bld.def(v3), coords[0], coords[1], coords[2]) :
4744                      bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), coords[0], coords[1]);
4745    aco_ptr<MIMG_instruction> load{create_instruction<MIMG_instruction>(aco_opcode::image_load, Format::MIMG, 3, 1)};
4746    load->operands[0] = Operand(fmask_desc_ptr);
4747    load->operands[1] = Operand(s4); /* no sampler */
4748    load->operands[2] = Operand(coord);
4749    load->definitions[0] = Definition(fmask);
4750    load->glc = false;
4751    load->dlc = false;
4752    load->dmask = 0x1;
4753    load->unrm = true;
4754    load->da = da;
4755    load->dim = dim;
4756    load->can_reorder = true; /* fmask images shouldn't be modified */
4757    ctx->block->instructions.emplace_back(std::move(load));
4758
4759    Operand sample_index4;
4760    if (sample_index.isConstant() && sample_index.constantValue() < 16) {
4761       sample_index4 = Operand(sample_index.constantValue() << 2);
4762    } else if (sample_index.regClass() == s1) {
4763       sample_index4 = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), sample_index, Operand(2u));
4764    } else {
4765       assert(sample_index.regClass() == v1);
4766       sample_index4 = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), sample_index);
4767    }
4768
4769    Temp final_sample;
4770    if (sample_index4.isConstant() && sample_index4.constantValue() == 0)
4771       final_sample = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(15u), fmask);
4772    else if (sample_index4.isConstant() && sample_index4.constantValue() == 28)
4773       final_sample = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(28u), fmask);
4774    else
4775       final_sample = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1), fmask, sample_index4, Operand(4u));
4776
4777    /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4778     * resource descriptor is 0 (invalid),
4779     */
4780    Temp compare = bld.tmp(bld.lm);
4781    bld.vopc_e64(aco_opcode::v_cmp_lg_u32, Definition(compare),
4782                 Operand(0u), emit_extract_vector(ctx, fmask_desc_ptr, 1, s1)).def(0).setHint(vcc);
4783
4784    Temp sample_index_v = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), sample_index);
4785
4786    /* Replace the MSAA sample index. */
4787    return bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), sample_index_v, final_sample, compare);
4788 }
4789
4790 static Temp get_image_coords(isel_context *ctx, const nir_intrinsic_instr *instr, const struct glsl_type *type)
4791 {
4792
4793    Temp src0 = get_ssa_temp(ctx, instr->src[1].ssa);
4794    enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4795    bool is_array = glsl_sampler_type_is_array(type);
4796    ASSERTED bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS || dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
4797    assert(!add_frag_pos && "Input attachments should be lowered.");
4798    bool is_ms = (dim == GLSL_SAMPLER_DIM_MS || dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
4799    bool gfx9_1d = ctx->options->chip_class == GFX9 && dim == GLSL_SAMPLER_DIM_1D;
4800    int count = image_type_to_components_count(dim, is_array);
4801    std::vector<Temp> coords(count);
4802    Builder bld(ctx->program, ctx->block);
4803
4804    if (is_ms) {
4805       count--;
4806       Temp src2 = get_ssa_temp(ctx, instr->src[2].ssa);
4807       /* get sample index */
4808       if (instr->intrinsic == nir_intrinsic_image_deref_load) {
4809          nir_const_value *sample_cv = nir_src_as_const_value(instr->src[2]);
4810          Operand sample_index = sample_cv ? Operand(sample_cv->u32) : Operand(emit_extract_vector(ctx, src2, 0, v1));
4811          std::vector<Temp> fmask_load_address;
4812          for (unsigned i = 0; i < (is_array ? 3 : 2); i++)
4813             fmask_load_address.emplace_back(emit_extract_vector(ctx, src0, i, v1));
4814
4815          Temp fmask_desc_ptr = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_FMASK, nullptr, false, false);
4816          coords[count] = adjust_sample_index_using_fmask(ctx, is_array, fmask_load_address, sample_index, fmask_desc_ptr);
4817       } else {
4818          coords[count] = emit_extract_vector(ctx, src2, 0, v1);
4819       }
4820    }
4821
4822    if (gfx9_1d) {
4823       coords[0] = emit_extract_vector(ctx, src0, 0, v1);
4824       coords.resize(coords.size() + 1);
4825       coords[1] = bld.copy(bld.def(v1), Operand(0u));
4826       if (is_array)
4827          coords[2] = emit_extract_vector(ctx, src0, 1, v1);
4828    } else {
4829       for (int i = 0; i < count; i++)
4830          coords[i] = emit_extract_vector(ctx, src0, i, v1);
4831    }
4832
4833    if (instr->intrinsic == nir_intrinsic_image_deref_load ||
4834        instr->intrinsic == nir_intrinsic_image_deref_store) {
4835       int lod_index = instr->intrinsic == nir_intrinsic_image_deref_load ? 3 : 4;
4836       bool level_zero = nir_src_is_const(instr->src[lod_index]) && nir_src_as_uint(instr->src[lod_index]) == 0;
4837
4838       if (!level_zero)
4839          coords.emplace_back(get_ssa_temp(ctx, instr->src[lod_index].ssa));
4840    }
4841
4842    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, coords.size(), 1)};
4843    for (unsigned i = 0; i < coords.size(); i++)
4844       vec->operands[i] = Operand(coords[i]);
4845    Temp res = {ctx->program->allocateId(), RegClass(RegType::vgpr, coords.size())};
4846    vec->definitions[0] = Definition(res);
4847    ctx->block->instructions.emplace_back(std::move(vec));
4848    return res;
4849 }
4850
4851
4852 void visit_image_load(isel_context *ctx, nir_intrinsic_instr *instr)
4853 {
4854    Builder bld(ctx->program, ctx->block);
4855    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4856    const struct glsl_type *type = glsl_without_array(var->type);
4857    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4858    bool is_array = glsl_sampler_type_is_array(type);
4859    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4860
4861    if (dim == GLSL_SAMPLER_DIM_BUF) {
4862       unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
4863       unsigned num_channels = util_last_bit(mask);
4864       Temp rsrc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4865       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4866
4867       aco_opcode opcode;
4868       switch (num_channels) {
4869       case 1:
4870          opcode = aco_opcode::buffer_load_format_x;
4871          break;
4872       case 2:
4873          opcode = aco_opcode::buffer_load_format_xy;
4874          break;
4875       case 3:
4876          opcode = aco_opcode::buffer_load_format_xyz;
4877          break;
4878       case 4:
4879          opcode = aco_opcode::buffer_load_format_xyzw;
4880          break;
4881       default:
4882          unreachable(">4 channel buffer image load");
4883       }
4884       aco_ptr<MUBUF_instruction> load{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 3, 1)};
4885       load->operands[0] = Operand(rsrc);
4886       load->operands[1] = Operand(vindex);
4887       load->operands[2] = Operand((uint32_t) 0);
4888       Temp tmp;
4889       if (num_channels == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
4890          tmp = dst;
4891       else
4892          tmp = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_channels)};
4893       load->definitions[0] = Definition(tmp);
4894       load->idxen = true;
4895       load->glc = var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT);
4896       load->dlc = load->glc && ctx->options->chip_class >= GFX10;
4897       load->barrier = barrier_image;
4898       ctx->block->instructions.emplace_back(std::move(load));
4899
4900       expand_vector(ctx, tmp, dst, instr->dest.ssa.num_components, (1 << num_channels) - 1);
4901       return;
4902    }
4903
4904    Temp coords = get_image_coords(ctx, instr, type);
4905    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
4906
4907    unsigned dmask = nir_ssa_def_components_read(&instr->dest.ssa);
4908    unsigned num_components = util_bitcount(dmask);
4909    Temp tmp;
4910    if (num_components == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
4911       tmp = dst;
4912    else
4913       tmp = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_components)};
4914
4915    bool level_zero = nir_src_is_const(instr->src[3]) && nir_src_as_uint(instr->src[3]) == 0;
4916    aco_opcode opcode = level_zero ? aco_opcode::image_load : aco_opcode::image_load_mip;
4917
4918    aco_ptr<MIMG_instruction> load{create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 1)};
4919    load->operands[0] = Operand(resource);
4920    load->operands[1] = Operand(s4); /* no sampler */
4921    load->operands[2] = Operand(coords);
4922    load->definitions[0] = Definition(tmp);
4923    load->glc = var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT) ? 1 : 0;
4924    load->dlc = load->glc && ctx->options->chip_class >= GFX10;
4925    load->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4926    load->dmask = dmask;
4927    load->unrm = true;
4928    load->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
4929    load->barrier = barrier_image;
4930    ctx->block->instructions.emplace_back(std::move(load));
4931
4932    expand_vector(ctx, tmp, dst, instr->dest.ssa.num_components, dmask);
4933    return;
4934 }
4935
4936 void visit_image_store(isel_context *ctx, nir_intrinsic_instr *instr)
4937 {
4938    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4939    const struct glsl_type *type = glsl_without_array(var->type);
4940    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4941    bool is_array = glsl_sampler_type_is_array(type);
4942    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[3].ssa));
4943
4944    bool glc = ctx->options->chip_class == GFX6 || var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE) ? 1 : 0;
4945
4946    if (dim == GLSL_SAMPLER_DIM_BUF) {
4947       Temp rsrc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4948       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4949       aco_opcode opcode;
4950       switch (data.size()) {
4951       case 1:
4952          opcode = aco_opcode::buffer_store_format_x;
4953          break;
4954       case 2:
4955          opcode = aco_opcode::buffer_store_format_xy;
4956          break;
4957       case 3:
4958          opcode = aco_opcode::buffer_store_format_xyz;
4959          break;
4960       case 4:
4961          opcode = aco_opcode::buffer_store_format_xyzw;
4962          break;
4963       default:
4964          unreachable(">4 channel buffer image store");
4965       }
4966       aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 4, 0)};
4967       store->operands[0] = Operand(rsrc);
4968       store->operands[1] = Operand(vindex);
4969       store->operands[2] = Operand((uint32_t) 0);
4970       store->operands[3] = Operand(data);
4971       store->idxen = true;
4972       store->glc = glc;
4973       store->dlc = false;
4974       store->disable_wqm = true;
4975       store->barrier = barrier_image;
4976       ctx->program->needs_exact = true;
4977       ctx->block->instructions.emplace_back(std::move(store));
4978       return;
4979    }
4980
4981    assert(data.type() == RegType::vgpr);
4982    Temp coords = get_image_coords(ctx, instr, type);
4983    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
4984
4985    bool level_zero = nir_src_is_const(instr->src[4]) && nir_src_as_uint(instr->src[4]) == 0;
4986    aco_opcode opcode = level_zero ? aco_opcode::image_store : aco_opcode::image_store_mip;
4987
4988    aco_ptr<MIMG_instruction> store{create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 0)};
4989    store->operands[0] = Operand(resource);
4990    store->operands[1] = Operand(data);
4991    store->operands[2] = Operand(coords);
4992    store->glc = glc;
4993    store->dlc = false;
4994    store->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4995    store->dmask = (1 << data.size()) - 1;
4996    store->unrm = true;
4997    store->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
4998    store->disable_wqm = true;
4999    store->barrier = barrier_image;
5000    ctx->program->needs_exact = true;
5001    ctx->block->instructions.emplace_back(std::move(store));
5002    return;
5003 }
5004
5005 void visit_image_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
5006 {
5007    /* return the previous value if dest is ever used */
5008    bool return_previous = false;
5009    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
5010       return_previous = true;
5011       break;
5012    }
5013    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
5014       return_previous = true;
5015       break;
5016    }
5017
5018    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
5019    const struct glsl_type *type = glsl_without_array(var->type);
5020    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
5021    bool is_array = glsl_sampler_type_is_array(type);
5022    Builder bld(ctx->program, ctx->block);
5023
5024    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[3].ssa));
5025    assert(data.size() == 1 && "64bit ssbo atomics not yet implemented.");
5026
5027    if (instr->intrinsic == nir_intrinsic_image_deref_atomic_comp_swap)
5028       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), get_ssa_temp(ctx, instr->src[4].ssa), data);
5029
5030    aco_opcode buf_op, image_op;
5031    switch (instr->intrinsic) {
5032       case nir_intrinsic_image_deref_atomic_add:
5033          buf_op = aco_opcode::buffer_atomic_add;
5034          image_op = aco_opcode::image_atomic_add;
5035          break;
5036       case nir_intrinsic_image_deref_atomic_umin:
5037          buf_op = aco_opcode::buffer_atomic_umin;
5038          image_op = aco_opcode::image_atomic_umin;
5039          break;
5040       case nir_intrinsic_image_deref_atomic_imin:
5041          buf_op = aco_opcode::buffer_atomic_smin;
5042          image_op = aco_opcode::image_atomic_smin;
5043          break;
5044       case nir_intrinsic_image_deref_atomic_umax:
5045          buf_op = aco_opcode::buffer_atomic_umax;
5046          image_op = aco_opcode::image_atomic_umax;
5047          break;
5048       case nir_intrinsic_image_deref_atomic_imax:
5049          buf_op = aco_opcode::buffer_atomic_smax;
5050          image_op = aco_opcode::image_atomic_smax;
5051          break;
5052       case nir_intrinsic_image_deref_atomic_and:
5053          buf_op = aco_opcode::buffer_atomic_and;
5054          image_op = aco_opcode::image_atomic_and;
5055          break;
5056       case nir_intrinsic_image_deref_atomic_or:
5057          buf_op = aco_opcode::buffer_atomic_or;
5058          image_op = aco_opcode::image_atomic_or;
5059          break;
5060       case nir_intrinsic_image_deref_atomic_xor:
5061          buf_op = aco_opcode::buffer_atomic_xor;
5062          image_op = aco_opcode::image_atomic_xor;
5063          break;
5064       case nir_intrinsic_image_deref_atomic_exchange:
5065          buf_op = aco_opcode::buffer_atomic_swap;
5066          image_op = aco_opcode::image_atomic_swap;
5067          break;
5068       case nir_intrinsic_image_deref_atomic_comp_swap:
5069          buf_op = aco_opcode::buffer_atomic_cmpswap;
5070          image_op = aco_opcode::image_atomic_cmpswap;
5071          break;
5072       default:
5073          unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5074    }
5075
5076    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5077
5078    if (dim == GLSL_SAMPLER_DIM_BUF) {
5079       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
5080       Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
5081       //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5082       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(buf_op, Format::MUBUF, 4, return_previous ? 1 : 0)};
5083       mubuf->operands[0] = Operand(resource);
5084       mubuf->operands[1] = Operand(vindex);
5085       mubuf->operands[2] = Operand((uint32_t)0);
5086       mubuf->operands[3] = Operand(data);
5087       if (return_previous)
5088          mubuf->definitions[0] = Definition(dst);
5089       mubuf->offset = 0;
5090       mubuf->idxen = true;
5091       mubuf->glc = return_previous;
5092       mubuf->dlc = false; /* Not needed for atomics */
5093       mubuf->disable_wqm = true;
5094       mubuf->barrier = barrier_image;
5095       ctx->program->needs_exact = true;
5096       ctx->block->instructions.emplace_back(std::move(mubuf));
5097       return;
5098    }
5099
5100    Temp coords = get_image_coords(ctx, instr, type);
5101    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
5102    aco_ptr<MIMG_instruction> mimg{create_instruction<MIMG_instruction>(image_op, Format::MIMG, 3, return_previous ? 1 : 0)};
5103    mimg->operands[0] = Operand(resource);
5104    mimg->operands[1] = Operand(data);
5105    mimg->operands[2] = Operand(coords);
5106    if (return_previous)
5107       mimg->definitions[0] = Definition(dst);
5108    mimg->glc = return_previous;
5109    mimg->dlc = false; /* Not needed for atomics */
5110    mimg->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
5111    mimg->dmask = (1 << data.size()) - 1;
5112    mimg->unrm = true;
5113    mimg->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
5114    mimg->disable_wqm = true;
5115    mimg->barrier = barrier_image;
5116    ctx->program->needs_exact = true;
5117    ctx->block->instructions.emplace_back(std::move(mimg));
5118    return;
5119 }
5120
5121 void get_buffer_size(isel_context *ctx, Temp desc, Temp dst, bool in_elements)
5122 {
5123    if (in_elements && ctx->options->chip_class == GFX8) {
5124       /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
5125       Builder bld(ctx->program, ctx->block);
5126
5127       Temp size = emit_extract_vector(ctx, desc, 2, s1);
5128
5129       Temp size_div3 = bld.vop3(aco_opcode::v_mul_hi_u32, bld.def(v1), bld.copy(bld.def(v1), Operand(0xaaaaaaabu)), size);
5130       size_div3 = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.as_uniform(size_div3), Operand(1u));
5131
5132       Temp stride = emit_extract_vector(ctx, desc, 1, s1);
5133       stride = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), stride, Operand((5u << 16) | 16u));
5134
5135       Temp is12 = bld.sopc(aco_opcode::s_cmp_eq_i32, bld.def(s1, scc), stride, Operand(12u));
5136       size = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), size_div3, size, bld.scc(is12));
5137
5138       Temp shr_dst = dst.type() == RegType::vgpr ? bld.tmp(s1) : dst;
5139       bld.sop2(aco_opcode::s_lshr_b32, Definition(shr_dst), bld.def(s1, scc),
5140                size, bld.sop1(aco_opcode::s_ff1_i32_b32, bld.def(s1), stride));
5141       if (dst.type() == RegType::vgpr)
5142          bld.copy(Definition(dst), shr_dst);
5143
5144       /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
5145    } else {
5146       emit_extract_vector(ctx, desc, 2, dst);
5147    }
5148 }
5149
5150 void visit_image_size(isel_context *ctx, nir_intrinsic_instr *instr)
5151 {
5152    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
5153    const struct glsl_type *type = glsl_without_array(var->type);
5154    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
5155    bool is_array = glsl_sampler_type_is_array(type);
5156    Builder bld(ctx->program, ctx->block);
5157
5158    if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
5159       Temp desc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, NULL, true, false);
5160       return get_buffer_size(ctx, desc, get_ssa_temp(ctx, &instr->dest.ssa), true);
5161    }
5162
5163    /* LOD */
5164    Temp lod = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
5165
5166    /* Resource */
5167    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, NULL, true, false);
5168
5169    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5170
5171    aco_ptr<MIMG_instruction> mimg{create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 3, 1)};
5172    mimg->operands[0] = Operand(resource);
5173    mimg->operands[1] = Operand(s4); /* no sampler */
5174    mimg->operands[2] = Operand(lod);
5175    uint8_t& dmask = mimg->dmask;
5176    mimg->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
5177    mimg->dmask = (1 << instr->dest.ssa.num_components) - 1;
5178    mimg->da = glsl_sampler_type_is_array(type);
5179    mimg->can_reorder = true;
5180    Definition& def = mimg->definitions[0];
5181    ctx->block->instructions.emplace_back(std::move(mimg));
5182
5183    if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
5184        glsl_sampler_type_is_array(type)) {
5185
5186       assert(instr->dest.ssa.num_components == 3);
5187       Temp tmp = {ctx->program->allocateId(), v3};
5188       def = Definition(tmp);
5189       emit_split_vector(ctx, tmp, 3);
5190
5191       /* divide 3rd value by 6 by multiplying with magic number */
5192       Temp c = bld.copy(bld.def(s1), Operand((uint32_t) 0x2AAAAAAB));
5193       Temp by_6 = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), emit_extract_vector(ctx, tmp, 2, v1), c);
5194
5195       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
5196                  emit_extract_vector(ctx, tmp, 0, v1),
5197                  emit_extract_vector(ctx, tmp, 1, v1),
5198                  by_6);
5199
5200    } else if (ctx->options->chip_class == GFX9 &&
5201               glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
5202               glsl_sampler_type_is_array(type)) {
5203       assert(instr->dest.ssa.num_components == 2);
5204       def = Definition(dst);
5205       dmask = 0x5;
5206    } else {
5207       def = Definition(dst);
5208    }
5209
5210    emit_split_vector(ctx, dst, instr->dest.ssa.num_components);
5211 }
5212
5213 void visit_load_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
5214 {
5215    Builder bld(ctx->program, ctx->block);
5216    unsigned num_components = instr->num_components;
5217
5218    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5219    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5220    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
5221
5222    bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT);
5223    load_buffer(ctx, num_components, dst, rsrc, get_ssa_temp(ctx, instr->src[1].ssa), glc, false);
5224 }
5225
5226 void visit_store_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
5227 {
5228    Builder bld(ctx->program, ctx->block);
5229    Temp data = get_ssa_temp(ctx, instr->src[0].ssa);
5230    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
5231    unsigned writemask = nir_intrinsic_write_mask(instr);
5232    Temp offset = get_ssa_temp(ctx, instr->src[2].ssa);
5233
5234    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5235    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
5236
5237    bool smem = !ctx->divergent_vals[instr->src[2].ssa->index] &&
5238                ctx->options->chip_class >= GFX8;
5239    if (smem)
5240       offset = bld.as_uniform(offset);
5241    bool smem_nonfs = smem && ctx->stage != fragment_fs;
5242
5243    while (writemask) {
5244       int start, count;
5245       u_bit_scan_consecutive_range(&writemask, &start, &count);
5246       if (count == 3 && (smem || ctx->options->chip_class == GFX6)) {
5247          /* GFX6 doesn't support storing vec3, split it. */
5248          writemask |= 1u << (start + 2);
5249          count = 2;
5250       }
5251       int num_bytes = count * elem_size_bytes;
5252
5253       if (num_bytes > 16) {
5254          assert(elem_size_bytes == 8);
5255          writemask |= (((count - 2) << 1) - 1) << (start + 2);
5256          count = 2;
5257          num_bytes = 16;
5258       }
5259
5260       // TODO: check alignment of sub-dword stores
5261       // TODO: split 3 bytes. there is no store instruction for that
5262
5263       Temp write_data;
5264       if (count != instr->num_components) {
5265          emit_split_vector(ctx, data, instr->num_components);
5266          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
5267          for (int i = 0; i < count; i++) {
5268             Temp elem = emit_extract_vector(ctx, data, start + i, RegClass(data.type(), elem_size_bytes / 4));
5269             vec->operands[i] = Operand(smem_nonfs ? bld.as_uniform(elem) : elem);
5270          }
5271          write_data = bld.tmp(!smem ? RegType::vgpr : smem_nonfs ? RegType::sgpr : data.type(), count * elem_size_bytes / 4);
5272          vec->definitions[0] = Definition(write_data);
5273          ctx->block->instructions.emplace_back(std::move(vec));
5274       } else if (!smem && data.type() != RegType::vgpr) {
5275          assert(num_bytes % 4 == 0);
5276          write_data = bld.copy(bld.def(RegType::vgpr, num_bytes / 4), data);
5277       } else if (smem_nonfs && data.type() == RegType::vgpr) {
5278          assert(num_bytes % 4 == 0);
5279          write_data = bld.as_uniform(data);
5280       } else {
5281          write_data = data;
5282       }
5283
5284       aco_opcode vmem_op, smem_op;
5285       switch (num_bytes) {
5286          case 4:
5287             vmem_op = aco_opcode::buffer_store_dword;
5288             smem_op = aco_opcode::s_buffer_store_dword;
5289             break;
5290          case 8:
5291             vmem_op = aco_opcode::buffer_store_dwordx2;
5292             smem_op = aco_opcode::s_buffer_store_dwordx2;
5293             break;
5294          case 12:
5295             vmem_op = aco_opcode::buffer_store_dwordx3;
5296             smem_op = aco_opcode::last_opcode;
5297             assert(!smem && ctx->options->chip_class > GFX6);
5298             break;
5299          case 16:
5300             vmem_op = aco_opcode::buffer_store_dwordx4;
5301             smem_op = aco_opcode::s_buffer_store_dwordx4;
5302             break;
5303          default:
5304             unreachable("Store SSBO not implemented for this size.");
5305       }
5306       if (ctx->stage == fragment_fs)
5307          smem_op = aco_opcode::p_fs_buffer_store_smem;
5308
5309       if (smem) {
5310          aco_ptr<SMEM_instruction> store{create_instruction<SMEM_instruction>(smem_op, Format::SMEM, 3, 0)};
5311          store->operands[0] = Operand(rsrc);
5312          if (start) {
5313             Temp off = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
5314                                 offset, Operand(start * elem_size_bytes));
5315             store->operands[1] = Operand(off);
5316          } else {
5317             store->operands[1] = Operand(offset);
5318          }
5319          if (smem_op != aco_opcode::p_fs_buffer_store_smem)
5320             store->operands[1].setFixed(m0);
5321          store->operands[2] = Operand(write_data);
5322          store->glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
5323          store->dlc = false;
5324          store->disable_wqm = true;
5325          store->barrier = barrier_buffer;
5326          ctx->block->instructions.emplace_back(std::move(store));
5327          ctx->program->wb_smem_l1_on_end = true;
5328          if (smem_op == aco_opcode::p_fs_buffer_store_smem) {
5329             ctx->block->kind |= block_kind_needs_lowering;
5330             ctx->program->needs_exact = true;
5331          }
5332       } else {
5333          aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(vmem_op, Format::MUBUF, 4, 0)};
5334          store->operands[0] = Operand(rsrc);
5335          store->operands[1] = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
5336          store->operands[2] = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
5337          store->operands[3] = Operand(write_data);
5338          store->offset = start * elem_size_bytes;
5339          store->offen = (offset.type() == RegType::vgpr);
5340          store->glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
5341          store->dlc = false;
5342          store->disable_wqm = true;
5343          store->barrier = barrier_buffer;
5344          ctx->program->needs_exact = true;
5345          ctx->block->instructions.emplace_back(std::move(store));
5346       }
5347    }
5348 }
5349
5350 void visit_atomic_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
5351 {
5352    /* return the previous value if dest is ever used */
5353    bool return_previous = false;
5354    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
5355       return_previous = true;
5356       break;
5357    }
5358    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
5359       return_previous = true;
5360       break;
5361    }
5362
5363    Builder bld(ctx->program, ctx->block);
5364    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[2].ssa));
5365
5366    if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap)
5367       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(RegType::vgpr, data.size() * 2),
5368                         get_ssa_temp(ctx, instr->src[3].ssa), data);
5369
5370    Temp offset = get_ssa_temp(ctx, instr->src[1].ssa);
5371    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5372    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
5373
5374    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5375
5376    aco_opcode op32, op64;
5377    switch (instr->intrinsic) {
5378       case nir_intrinsic_ssbo_atomic_add:
5379          op32 = aco_opcode::buffer_atomic_add;
5380          op64 = aco_opcode::buffer_atomic_add_x2;
5381          break;
5382       case nir_intrinsic_ssbo_atomic_imin:
5383          op32 = aco_opcode::buffer_atomic_smin;
5384          op64 = aco_opcode::buffer_atomic_smin_x2;
5385          break;
5386       case nir_intrinsic_ssbo_atomic_umin:
5387          op32 = aco_opcode::buffer_atomic_umin;
5388          op64 = aco_opcode::buffer_atomic_umin_x2;
5389          break;
5390       case nir_intrinsic_ssbo_atomic_imax:
5391          op32 = aco_opcode::buffer_atomic_smax;
5392          op64 = aco_opcode::buffer_atomic_smax_x2;
5393          break;
5394       case nir_intrinsic_ssbo_atomic_umax:
5395          op32 = aco_opcode::buffer_atomic_umax;
5396          op64 = aco_opcode::buffer_atomic_umax_x2;
5397          break;
5398       case nir_intrinsic_ssbo_atomic_and:
5399          op32 = aco_opcode::buffer_atomic_and;
5400          op64 = aco_opcode::buffer_atomic_and_x2;
5401          break;
5402       case nir_intrinsic_ssbo_atomic_or:
5403          op32 = aco_opcode::buffer_atomic_or;
5404          op64 = aco_opcode::buffer_atomic_or_x2;
5405          break;
5406       case nir_intrinsic_ssbo_atomic_xor:
5407          op32 = aco_opcode::buffer_atomic_xor;
5408          op64 = aco_opcode::buffer_atomic_xor_x2;
5409          break;
5410       case nir_intrinsic_ssbo_atomic_exchange:
5411          op32 = aco_opcode::buffer_atomic_swap;
5412          op64 = aco_opcode::buffer_atomic_swap_x2;
5413          break;
5414       case nir_intrinsic_ssbo_atomic_comp_swap:
5415          op32 = aco_opcode::buffer_atomic_cmpswap;
5416          op64 = aco_opcode::buffer_atomic_cmpswap_x2;
5417          break;
5418       default:
5419          unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
5420    }
5421    aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
5422    aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, return_previous ? 1 : 0)};
5423    mubuf->operands[0] = Operand(rsrc);
5424    mubuf->operands[1] = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
5425    mubuf->operands[2] = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
5426    mubuf->operands[3] = Operand(data);
5427    if (return_previous)
5428       mubuf->definitions[0] = Definition(dst);
5429    mubuf->offset = 0;
5430    mubuf->offen = (offset.type() == RegType::vgpr);
5431    mubuf->glc = return_previous;
5432    mubuf->dlc = false; /* Not needed for atomics */
5433    mubuf->disable_wqm = true;
5434    mubuf->barrier = barrier_buffer;
5435    ctx->program->needs_exact = true;
5436    ctx->block->instructions.emplace_back(std::move(mubuf));
5437 }
5438
5439 void visit_get_buffer_size(isel_context *ctx, nir_intrinsic_instr *instr) {
5440
5441    Temp index = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5442    Builder bld(ctx->program, ctx->block);
5443    Temp desc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), index, Operand(0u));
5444    get_buffer_size(ctx, desc, get_ssa_temp(ctx, &instr->dest.ssa), false);
5445 }
5446
5447 Temp get_gfx6_global_rsrc(Builder& bld, Temp addr)
5448 {
5449    uint32_t rsrc_conf = S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5450                         S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
5451
5452    if (addr.type() == RegType::vgpr)
5453       return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf));
5454    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), addr, Operand(-1u), Operand(rsrc_conf));
5455 }
5456
5457 void visit_load_global(isel_context *ctx, nir_intrinsic_instr *instr)
5458 {
5459    Builder bld(ctx->program, ctx->block);
5460    unsigned num_components = instr->num_components;
5461    unsigned num_bytes = num_components * instr->dest.ssa.bit_size / 8;
5462
5463    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5464    Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
5465
5466    bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT);
5467    bool dlc = glc && ctx->options->chip_class >= GFX10;
5468    aco_opcode op;
5469    if (dst.type() == RegType::vgpr || (glc && ctx->options->chip_class < GFX8)) {
5470       bool global = ctx->options->chip_class >= GFX9;
5471
5472       if (ctx->options->chip_class >= GFX7) {
5473          aco_opcode op;
5474          switch (num_bytes) {
5475          case 4:
5476             op = global ? aco_opcode::global_load_dword : aco_opcode::flat_load_dword;
5477             break;
5478          case 8:
5479             op = global ? aco_opcode::global_load_dwordx2 : aco_opcode::flat_load_dwordx2;
5480             break;
5481          case 12:
5482             op = global ? aco_opcode::global_load_dwordx3 : aco_opcode::flat_load_dwordx3;
5483             break;
5484          case 16:
5485             op = global ? aco_opcode::global_load_dwordx4 : aco_opcode::flat_load_dwordx4;
5486             break;
5487          default:
5488             unreachable("load_global not implemented for this size.");
5489          }
5490
5491          aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 2, 1)};
5492          flat->operands[0] = Operand(addr);
5493          flat->operands[1] = Operand(s1);
5494          flat->glc = glc;
5495          flat->dlc = dlc;
5496          flat->barrier = barrier_buffer;
5497
5498          if (dst.type() == RegType::sgpr) {
5499             Temp vec = bld.tmp(RegType::vgpr, dst.size());
5500             flat->definitions[0] = Definition(vec);
5501             ctx->block->instructions.emplace_back(std::move(flat));
5502             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec);
5503          } else {
5504             flat->definitions[0] = Definition(dst);
5505             ctx->block->instructions.emplace_back(std::move(flat));
5506          }
5507          emit_split_vector(ctx, dst, num_components);
5508       } else {
5509          assert(ctx->options->chip_class == GFX6);
5510
5511          /* GFX6 doesn't support loading vec3, expand to vec4. */
5512          num_bytes = num_bytes == 12 ? 16 : num_bytes;
5513
5514          aco_opcode op;
5515          switch (num_bytes) {
5516          case 4:
5517             op = aco_opcode::buffer_load_dword;
5518             break;
5519          case 8:
5520             op = aco_opcode::buffer_load_dwordx2;
5521             break;
5522          case 16:
5523             op = aco_opcode::buffer_load_dwordx4;
5524             break;
5525          default:
5526             unreachable("load_global not implemented for this size.");
5527          }
5528
5529          Temp rsrc = get_gfx6_global_rsrc(bld, addr);
5530
5531          aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
5532          mubuf->operands[0] = Operand(rsrc);
5533          mubuf->operands[1] = addr.type() == RegType::vgpr ? Operand(addr) : Operand(v1);
5534          mubuf->operands[2] = Operand(0u);
5535          mubuf->glc = glc;
5536          mubuf->dlc = false;
5537          mubuf->offset = 0;
5538          mubuf->addr64 = addr.type() == RegType::vgpr;
5539          mubuf->disable_wqm = false;
5540          mubuf->barrier = barrier_buffer;
5541          aco_ptr<Instruction> instr = std::move(mubuf);
5542
5543          /* expand vector */
5544          if (dst.size() == 3) {
5545             Temp vec = bld.tmp(v4);
5546             instr->definitions[0] = Definition(vec);
5547             bld.insert(std::move(instr));
5548             emit_split_vector(ctx, vec, 4);
5549
5550             instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, 3, 1));
5551             instr->operands[0] = Operand(emit_extract_vector(ctx, vec, 0, v1));
5552             instr->operands[1] = Operand(emit_extract_vector(ctx, vec, 1, v1));
5553             instr->operands[2] = Operand(emit_extract_vector(ctx, vec, 2, v1));
5554          }
5555
5556          if (dst.type() == RegType::sgpr) {
5557             Temp vec = bld.tmp(RegType::vgpr, dst.size());
5558             instr->definitions[0] = Definition(vec);
5559             bld.insert(std::move(instr));
5560             expand_vector(ctx, vec, dst, num_components, (1 << num_components) - 1);
5561             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec);
5562          } else {
5563             instr->definitions[0] = Definition(dst);
5564             bld.insert(std::move(instr));
5565             emit_split_vector(ctx, dst, num_components);
5566          }
5567       }
5568    } else {
5569       switch (num_bytes) {
5570          case 4:
5571             op = aco_opcode::s_load_dword;
5572             break;
5573          case 8:
5574             op = aco_opcode::s_load_dwordx2;
5575             break;
5576          case 12:
5577          case 16:
5578             op = aco_opcode::s_load_dwordx4;
5579             break;
5580          default:
5581             unreachable("load_global not implemented for this size.");
5582       }
5583       aco_ptr<SMEM_instruction> load{create_instruction<SMEM_instruction>(op, Format::SMEM, 2, 1)};
5584       load->operands[0] = Operand(addr);
5585       load->operands[1] = Operand(0u);
5586       load->definitions[0] = Definition(dst);
5587       load->glc = glc;
5588       load->dlc = dlc;
5589       load->barrier = barrier_buffer;
5590       assert(ctx->options->chip_class >= GFX8 || !glc);
5591
5592       if (dst.size() == 3) {
5593          /* trim vector */
5594          Temp vec = bld.tmp(s4);
5595          load->definitions[0] = Definition(vec);
5596          ctx->block->instructions.emplace_back(std::move(load));
5597          emit_split_vector(ctx, vec, 4);
5598
5599          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
5600                     emit_extract_vector(ctx, vec, 0, s1),
5601                     emit_extract_vector(ctx, vec, 1, s1),
5602                     emit_extract_vector(ctx, vec, 2, s1));
5603       } else {
5604          ctx->block->instructions.emplace_back(std::move(load));
5605       }
5606    }
5607 }
5608
5609 void visit_store_global(isel_context *ctx, nir_intrinsic_instr *instr)
5610 {
5611    Builder bld(ctx->program, ctx->block);
5612    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
5613
5614    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5615    Temp addr = get_ssa_temp(ctx, instr->src[1].ssa);
5616
5617    if (ctx->options->chip_class >= GFX7)
5618       addr = as_vgpr(ctx, addr);
5619
5620    unsigned writemask = nir_intrinsic_write_mask(instr);
5621    while (writemask) {
5622       int start, count;
5623       u_bit_scan_consecutive_range(&writemask, &start, &count);
5624       if (count == 3 && ctx->options->chip_class == GFX6) {
5625          /* GFX6 doesn't support storing vec3, split it. */
5626          writemask |= 1u << (start + 2);
5627          count = 2;
5628       }
5629       unsigned num_bytes = count * elem_size_bytes;
5630
5631       Temp write_data = data;
5632       if (count != instr->num_components) {
5633          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
5634          for (int i = 0; i < count; i++)
5635             vec->operands[i] = Operand(emit_extract_vector(ctx, data, start + i, v1));
5636          write_data = bld.tmp(RegType::vgpr, count);
5637          vec->definitions[0] = Definition(write_data);
5638          ctx->block->instructions.emplace_back(std::move(vec));
5639       }
5640
5641       bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
5642       unsigned offset = start * elem_size_bytes;
5643
5644       if (ctx->options->chip_class >= GFX7) {
5645          if (offset > 0 && ctx->options->chip_class < GFX9) {
5646             Temp addr0 = bld.tmp(v1), addr1 = bld.tmp(v1);
5647             Temp new_addr0 = bld.tmp(v1), new_addr1 = bld.tmp(v1);
5648             Temp carry = bld.tmp(bld.lm);
5649             bld.pseudo(aco_opcode::p_split_vector, Definition(addr0), Definition(addr1), addr);
5650
5651             bld.vop2(aco_opcode::v_add_co_u32, Definition(new_addr0), bld.hint_vcc(Definition(carry)),
5652                      Operand(offset), addr0);
5653             bld.vop2(aco_opcode::v_addc_co_u32, Definition(new_addr1), bld.def(bld.lm),
5654                      Operand(0u), addr1,
5655                      carry).def(1).setHint(vcc);
5656
5657             addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), new_addr0, new_addr1);
5658
5659             offset = 0;
5660          }
5661
5662          bool global = ctx->options->chip_class >= GFX9;
5663          aco_opcode op;
5664          switch (num_bytes) {
5665          case 4:
5666             op = global ? aco_opcode::global_store_dword : aco_opcode::flat_store_dword;
5667             break;
5668          case 8:
5669             op = global ? aco_opcode::global_store_dwordx2 : aco_opcode::flat_store_dwordx2;
5670             break;
5671          case 12:
5672             op = global ? aco_opcode::global_store_dwordx3 : aco_opcode::flat_store_dwordx3;
5673             break;
5674          case 16:
5675             op = global ? aco_opcode::global_store_dwordx4 : aco_opcode::flat_store_dwordx4;
5676             break;
5677          default:
5678             unreachable("store_global not implemented for this size.");
5679          }
5680
5681          aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 3, 0)};
5682          flat->operands[0] = Operand(addr);
5683          flat->operands[1] = Operand(s1);
5684          flat->operands[2] = Operand(data);
5685          flat->glc = glc;
5686          flat->dlc = false;
5687          flat->offset = offset;
5688          flat->disable_wqm = true;
5689          flat->barrier = barrier_buffer;
5690          ctx->program->needs_exact = true;
5691          ctx->block->instructions.emplace_back(std::move(flat));
5692       } else {
5693          assert(ctx->options->chip_class == GFX6);
5694
5695          aco_opcode op;
5696          switch (num_bytes) {
5697          case 4:
5698             op = aco_opcode::buffer_store_dword;
5699             break;
5700          case 8:
5701             op = aco_opcode::buffer_store_dwordx2;
5702             break;
5703          case 16:
5704             op = aco_opcode::buffer_store_dwordx4;
5705             break;
5706          default:
5707             unreachable("store_global not implemented for this size.");
5708          }
5709
5710          Temp rsrc = get_gfx6_global_rsrc(bld, addr);
5711
5712          aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, 0)};
5713          mubuf->operands[0] = Operand(rsrc);
5714          mubuf->operands[1] = addr.type() == RegType::vgpr ? Operand(addr) : Operand(v1);
5715          mubuf->operands[2] = Operand(0u);
5716          mubuf->operands[3] = Operand(write_data);
5717          mubuf->glc = glc;
5718          mubuf->dlc = false;
5719          mubuf->offset = offset;
5720          mubuf->addr64 = addr.type() == RegType::vgpr;
5721          mubuf->disable_wqm = true;
5722          mubuf->barrier = barrier_buffer;
5723          ctx->program->needs_exact = true;
5724          ctx->block->instructions.emplace_back(std::move(mubuf));
5725       }
5726    }
5727 }
5728
5729 void visit_global_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
5730 {
5731    /* return the previous value if dest is ever used */
5732    bool return_previous = false;
5733    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
5734       return_previous = true;
5735       break;
5736    }
5737    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
5738       return_previous = true;
5739       break;
5740    }
5741
5742    Builder bld(ctx->program, ctx->block);
5743    Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
5744    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5745
5746    if (ctx->options->chip_class >= GFX7)
5747       addr = as_vgpr(ctx, addr);
5748
5749    if (instr->intrinsic == nir_intrinsic_global_atomic_comp_swap)
5750       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(RegType::vgpr, data.size() * 2),
5751                         get_ssa_temp(ctx, instr->src[2].ssa), data);
5752
5753    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5754
5755    aco_opcode op32, op64;
5756
5757    if (ctx->options->chip_class >= GFX7) {
5758       bool global = ctx->options->chip_class >= GFX9;
5759       switch (instr->intrinsic) {
5760          case nir_intrinsic_global_atomic_add:
5761             op32 = global ? aco_opcode::global_atomic_add : aco_opcode::flat_atomic_add;
5762             op64 = global ? aco_opcode::global_atomic_add_x2 : aco_opcode::flat_atomic_add_x2;
5763             break;
5764          case nir_intrinsic_global_atomic_imin:
5765             op32 = global ? aco_opcode::global_atomic_smin : aco_opcode::flat_atomic_smin;
5766             op64 = global ? aco_opcode::global_atomic_smin_x2 : aco_opcode::flat_atomic_smin_x2;
5767             break;
5768          case nir_intrinsic_global_atomic_umin:
5769             op32 = global ? aco_opcode::global_atomic_umin : aco_opcode::flat_atomic_umin;
5770             op64 = global ? aco_opcode::global_atomic_umin_x2 : aco_opcode::flat_atomic_umin_x2;
5771             break;
5772          case nir_intrinsic_global_atomic_imax:
5773             op32 = global ? aco_opcode::global_atomic_smax : aco_opcode::flat_atomic_smax;
5774             op64 = global ? aco_opcode::global_atomic_smax_x2 : aco_opcode::flat_atomic_smax_x2;
5775             break;
5776          case nir_intrinsic_global_atomic_umax:
5777             op32 = global ? aco_opcode::global_atomic_umax : aco_opcode::flat_atomic_umax;
5778             op64 = global ? aco_opcode::global_atomic_umax_x2 : aco_opcode::flat_atomic_umax_x2;
5779             break;
5780          case nir_intrinsic_global_atomic_and:
5781             op32 = global ? aco_opcode::global_atomic_and : aco_opcode::flat_atomic_and;
5782             op64 = global ? aco_opcode::global_atomic_and_x2 : aco_opcode::flat_atomic_and_x2;
5783             break;
5784          case nir_intrinsic_global_atomic_or:
5785             op32 = global ? aco_opcode::global_atomic_or : aco_opcode::flat_atomic_or;
5786             op64 = global ? aco_opcode::global_atomic_or_x2 : aco_opcode::flat_atomic_or_x2;
5787             break;
5788          case nir_intrinsic_global_atomic_xor:
5789             op32 = global ? aco_opcode::global_atomic_xor : aco_opcode::flat_atomic_xor;
5790             op64 = global ? aco_opcode::global_atomic_xor_x2 : aco_opcode::flat_atomic_xor_x2;
5791             break;
5792          case nir_intrinsic_global_atomic_exchange:
5793             op32 = global ? aco_opcode::global_atomic_swap : aco_opcode::flat_atomic_swap;
5794             op64 = global ? aco_opcode::global_atomic_swap_x2 : aco_opcode::flat_atomic_swap_x2;
5795             break;
5796          case nir_intrinsic_global_atomic_comp_swap:
5797             op32 = global ? aco_opcode::global_atomic_cmpswap : aco_opcode::flat_atomic_cmpswap;
5798             op64 = global ? aco_opcode::global_atomic_cmpswap_x2 : aco_opcode::flat_atomic_cmpswap_x2;
5799             break;
5800          default:
5801             unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
5802       }
5803
5804       aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
5805       aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 3, return_previous ? 1 : 0)};
5806       flat->operands[0] = Operand(addr);
5807       flat->operands[1] = Operand(s1);
5808       flat->operands[2] = Operand(data);
5809       if (return_previous)
5810          flat->definitions[0] = Definition(dst);
5811       flat->glc = return_previous;
5812       flat->dlc = false; /* Not needed for atomics */
5813       flat->offset = 0;
5814       flat->disable_wqm = true;
5815       flat->barrier = barrier_buffer;
5816       ctx->program->needs_exact = true;
5817       ctx->block->instructions.emplace_back(std::move(flat));
5818    } else {
5819       assert(ctx->options->chip_class == GFX6);
5820
5821       switch (instr->intrinsic) {
5822          case nir_intrinsic_global_atomic_add:
5823             op32 = aco_opcode::buffer_atomic_add;
5824             op64 = aco_opcode::buffer_atomic_add_x2;
5825             break;
5826          case nir_intrinsic_global_atomic_imin:
5827             op32 = aco_opcode::buffer_atomic_smin;
5828             op64 = aco_opcode::buffer_atomic_smin_x2;
5829             break;
5830          case nir_intrinsic_global_atomic_umin:
5831             op32 = aco_opcode::buffer_atomic_umin;
5832             op64 = aco_opcode::buffer_atomic_umin_x2;
5833             break;
5834          case nir_intrinsic_global_atomic_imax:
5835             op32 = aco_opcode::buffer_atomic_smax;
5836             op64 = aco_opcode::buffer_atomic_smax_x2;
5837             break;
5838          case nir_intrinsic_global_atomic_umax:
5839             op32 = aco_opcode::buffer_atomic_umax;
5840             op64 = aco_opcode::buffer_atomic_umax_x2;
5841             break;
5842          case nir_intrinsic_global_atomic_and:
5843             op32 = aco_opcode::buffer_atomic_and;
5844             op64 = aco_opcode::buffer_atomic_and_x2;
5845             break;
5846          case nir_intrinsic_global_atomic_or:
5847             op32 = aco_opcode::buffer_atomic_or;
5848             op64 = aco_opcode::buffer_atomic_or_x2;
5849             break;
5850          case nir_intrinsic_global_atomic_xor:
5851             op32 = aco_opcode::buffer_atomic_xor;
5852             op64 = aco_opcode::buffer_atomic_xor_x2;
5853             break;
5854          case nir_intrinsic_global_atomic_exchange:
5855             op32 = aco_opcode::buffer_atomic_swap;
5856             op64 = aco_opcode::buffer_atomic_swap_x2;
5857             break;
5858          case nir_intrinsic_global_atomic_comp_swap:
5859             op32 = aco_opcode::buffer_atomic_cmpswap;
5860             op64 = aco_opcode::buffer_atomic_cmpswap_x2;
5861             break;
5862          default:
5863             unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
5864       }
5865
5866       Temp rsrc = get_gfx6_global_rsrc(bld, addr);
5867
5868       aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
5869
5870       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, return_previous ? 1 : 0)};
5871       mubuf->operands[0] = Operand(rsrc);
5872       mubuf->operands[1] = addr.type() == RegType::vgpr ? Operand(addr) : Operand(v1);
5873       mubuf->operands[2] = Operand(0u);
5874       mubuf->operands[3] = Operand(data);
5875       if (return_previous)
5876          mubuf->definitions[0] = Definition(dst);
5877       mubuf->glc = return_previous;
5878       mubuf->dlc = false;
5879       mubuf->offset = 0;
5880       mubuf->addr64 = addr.type() == RegType::vgpr;
5881       mubuf->disable_wqm = true;
5882       mubuf->barrier = barrier_buffer;
5883       ctx->program->needs_exact = true;
5884       ctx->block->instructions.emplace_back(std::move(mubuf));
5885    }
5886 }
5887
5888 void emit_memory_barrier(isel_context *ctx, nir_intrinsic_instr *instr) {
5889    Builder bld(ctx->program, ctx->block);
5890    switch(instr->intrinsic) {
5891       case nir_intrinsic_group_memory_barrier:
5892       case nir_intrinsic_memory_barrier:
5893          bld.barrier(aco_opcode::p_memory_barrier_common);
5894          break;
5895       case nir_intrinsic_memory_barrier_buffer:
5896          bld.barrier(aco_opcode::p_memory_barrier_buffer);
5897          break;
5898       case nir_intrinsic_memory_barrier_image:
5899          bld.barrier(aco_opcode::p_memory_barrier_image);
5900          break;
5901       case nir_intrinsic_memory_barrier_tcs_patch:
5902       case nir_intrinsic_memory_barrier_shared:
5903          bld.barrier(aco_opcode::p_memory_barrier_shared);
5904          break;
5905       default:
5906          unreachable("Unimplemented memory barrier intrinsic");
5907          break;
5908    }
5909 }
5910
5911 void visit_load_shared(isel_context *ctx, nir_intrinsic_instr *instr)
5912 {
5913    // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
5914    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5915    assert(instr->dest.ssa.bit_size >= 32 && "Bitsize not supported in load_shared.");
5916    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5917    Builder bld(ctx->program, ctx->block);
5918
5919    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
5920    unsigned align = nir_intrinsic_align_mul(instr) ? nir_intrinsic_align(instr) : elem_size_bytes;
5921    load_lds(ctx, elem_size_bytes, dst, address, nir_intrinsic_base(instr), align);
5922 }
5923
5924 void visit_store_shared(isel_context *ctx, nir_intrinsic_instr *instr)
5925 {
5926    unsigned writemask = nir_intrinsic_write_mask(instr);
5927    Temp data = get_ssa_temp(ctx, instr->src[0].ssa);
5928    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5929    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
5930    assert(elem_size_bytes >= 4 && "Only 32bit & 64bit store_shared currently supported.");
5931
5932    unsigned align = nir_intrinsic_align_mul(instr) ? nir_intrinsic_align(instr) : elem_size_bytes;
5933    store_lds(ctx, elem_size_bytes, data, writemask, address, nir_intrinsic_base(instr), align);
5934 }
5935
5936 void visit_shared_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
5937 {
5938    unsigned offset = nir_intrinsic_base(instr);
5939    Operand m = load_lds_size_m0(ctx);
5940    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5941    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5942
5943    unsigned num_operands = 3;
5944    aco_opcode op32, op64, op32_rtn, op64_rtn;
5945    switch(instr->intrinsic) {
5946       case nir_intrinsic_shared_atomic_add:
5947          op32 = aco_opcode::ds_add_u32;
5948          op64 = aco_opcode::ds_add_u64;
5949          op32_rtn = aco_opcode::ds_add_rtn_u32;
5950          op64_rtn = aco_opcode::ds_add_rtn_u64;
5951          break;
5952       case nir_intrinsic_shared_atomic_imin:
5953          op32 = aco_opcode::ds_min_i32;
5954          op64 = aco_opcode::ds_min_i64;
5955          op32_rtn = aco_opcode::ds_min_rtn_i32;
5956          op64_rtn = aco_opcode::ds_min_rtn_i64;
5957          break;
5958       case nir_intrinsic_shared_atomic_umin:
5959          op32 = aco_opcode::ds_min_u32;
5960          op64 = aco_opcode::ds_min_u64;
5961          op32_rtn = aco_opcode::ds_min_rtn_u32;
5962          op64_rtn = aco_opcode::ds_min_rtn_u64;
5963          break;
5964       case nir_intrinsic_shared_atomic_imax:
5965          op32 = aco_opcode::ds_max_i32;
5966          op64 = aco_opcode::ds_max_i64;
5967          op32_rtn = aco_opcode::ds_max_rtn_i32;
5968          op64_rtn = aco_opcode::ds_max_rtn_i64;
5969          break;
5970       case nir_intrinsic_shared_atomic_umax:
5971          op32 = aco_opcode::ds_max_u32;
5972          op64 = aco_opcode::ds_max_u64;
5973          op32_rtn = aco_opcode::ds_max_rtn_u32;
5974          op64_rtn = aco_opcode::ds_max_rtn_u64;
5975          break;
5976       case nir_intrinsic_shared_atomic_and:
5977          op32 = aco_opcode::ds_and_b32;
5978          op64 = aco_opcode::ds_and_b64;
5979          op32_rtn = aco_opcode::ds_and_rtn_b32;
5980          op64_rtn = aco_opcode::ds_and_rtn_b64;
5981          break;
5982       case nir_intrinsic_shared_atomic_or:
5983          op32 = aco_opcode::ds_or_b32;
5984          op64 = aco_opcode::ds_or_b64;
5985          op32_rtn = aco_opcode::ds_or_rtn_b32;
5986          op64_rtn = aco_opcode::ds_or_rtn_b64;
5987          break;
5988       case nir_intrinsic_shared_atomic_xor:
5989          op32 = aco_opcode::ds_xor_b32;
5990          op64 = aco_opcode::ds_xor_b64;
5991          op32_rtn = aco_opcode::ds_xor_rtn_b32;
5992          op64_rtn = aco_opcode::ds_xor_rtn_b64;
5993          break;
5994       case nir_intrinsic_shared_atomic_exchange:
5995          op32 = aco_opcode::ds_write_b32;
5996          op64 = aco_opcode::ds_write_b64;
5997          op32_rtn = aco_opcode::ds_wrxchg_rtn_b32;
5998          op64_rtn = aco_opcode::ds_wrxchg2_rtn_b64;
5999          break;
6000       case nir_intrinsic_shared_atomic_comp_swap:
6001          op32 = aco_opcode::ds_cmpst_b32;
6002          op64 = aco_opcode::ds_cmpst_b64;
6003          op32_rtn = aco_opcode::ds_cmpst_rtn_b32;
6004          op64_rtn = aco_opcode::ds_cmpst_rtn_b64;
6005          num_operands = 4;
6006          break;
6007       default:
6008          unreachable("Unhandled shared atomic intrinsic");
6009    }
6010
6011    /* return the previous value if dest is ever used */
6012    bool return_previous = false;
6013    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
6014       return_previous = true;
6015       break;
6016    }
6017    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
6018       return_previous = true;
6019       break;
6020    }
6021
6022    aco_opcode op;
6023    if (data.size() == 1) {
6024       assert(instr->dest.ssa.bit_size == 32);
6025       op = return_previous ? op32_rtn : op32;
6026    } else {
6027       assert(instr->dest.ssa.bit_size == 64);
6028       op = return_previous ? op64_rtn : op64;
6029    }
6030
6031    if (offset > 65535) {
6032       Builder bld(ctx->program, ctx->block);
6033       address = bld.vadd32(bld.def(v1), Operand(offset), address);
6034       offset = 0;
6035    }
6036
6037    aco_ptr<DS_instruction> ds;
6038    ds.reset(create_instruction<DS_instruction>(op, Format::DS, num_operands, return_previous ? 1 : 0));
6039    ds->operands[0] = Operand(address);
6040    ds->operands[1] = Operand(data);
6041    if (num_operands == 4)
6042       ds->operands[2] = Operand(get_ssa_temp(ctx, instr->src[2].ssa));
6043    ds->operands[num_operands - 1] = m;
6044    ds->offset0 = offset;
6045    if (return_previous)
6046       ds->definitions[0] = Definition(get_ssa_temp(ctx, &instr->dest.ssa));
6047    ctx->block->instructions.emplace_back(std::move(ds));
6048 }
6049
6050 Temp get_scratch_resource(isel_context *ctx)
6051 {
6052    Builder bld(ctx->program, ctx->block);
6053    Temp scratch_addr = ctx->program->private_segment_buffer;
6054    if (ctx->stage != compute_cs)
6055       scratch_addr = bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), scratch_addr, Operand(0u));
6056
6057    uint32_t rsrc_conf = S_008F0C_ADD_TID_ENABLE(1) |
6058                         S_008F0C_INDEX_STRIDE(ctx->program->wave_size == 64 ? 3 : 2);;
6059
6060    if (ctx->program->chip_class >= GFX10) {
6061       rsrc_conf |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
6062                    S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
6063                    S_008F0C_RESOURCE_LEVEL(1);
6064    } else if (ctx->program->chip_class <= GFX7) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6065       rsrc_conf |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
6066                    S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
6067    }
6068
6069    /* older generations need element size = 16 bytes. element size removed in GFX9 */
6070    if (ctx->program->chip_class <= GFX8)
6071       rsrc_conf |= S_008F0C_ELEMENT_SIZE(3);
6072
6073    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), scratch_addr, Operand(-1u), Operand(rsrc_conf));
6074 }
6075
6076 void visit_load_scratch(isel_context *ctx, nir_intrinsic_instr *instr) {
6077    assert(instr->dest.ssa.bit_size == 32 || instr->dest.ssa.bit_size == 64);
6078    Builder bld(ctx->program, ctx->block);
6079    Temp rsrc = get_scratch_resource(ctx);
6080    Temp offset = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
6081    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6082
6083    aco_opcode op;
6084    switch (dst.size()) {
6085       case 1:
6086          op = aco_opcode::buffer_load_dword;
6087          break;
6088       case 2:
6089          op = aco_opcode::buffer_load_dwordx2;
6090          break;
6091       case 3:
6092          op = aco_opcode::buffer_load_dwordx3;
6093          break;
6094       case 4:
6095          op = aco_opcode::buffer_load_dwordx4;
6096          break;
6097       case 6:
6098       case 8: {
6099          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
6100          Temp lower = bld.mubuf(aco_opcode::buffer_load_dwordx4,
6101                                 bld.def(v4), rsrc, offset,
6102                                 ctx->program->scratch_offset, 0, true);
6103          Temp upper = bld.mubuf(dst.size() == 6 ? aco_opcode::buffer_load_dwordx2 :
6104                                                   aco_opcode::buffer_load_dwordx4,
6105                                 dst.size() == 6 ? bld.def(v2) : bld.def(v4),
6106                                 rsrc, offset, ctx->program->scratch_offset, 16, true);
6107          emit_split_vector(ctx, lower, 2);
6108          elems[0] = emit_extract_vector(ctx, lower, 0, v2);
6109          elems[1] = emit_extract_vector(ctx, lower, 1, v2);
6110          if (dst.size() == 8) {
6111             emit_split_vector(ctx, upper, 2);
6112             elems[2] = emit_extract_vector(ctx, upper, 0, v2);
6113             elems[3] = emit_extract_vector(ctx, upper, 1, v2);
6114          } else {
6115             elems[2] = upper;
6116          }
6117
6118          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector,
6119                                                                          Format::PSEUDO, dst.size() / 2, 1)};
6120          for (unsigned i = 0; i < dst.size() / 2; i++)
6121             vec->operands[i] = Operand(elems[i]);
6122          vec->definitions[0] = Definition(dst);
6123          bld.insert(std::move(vec));
6124          ctx->allocated_vec.emplace(dst.id(), elems);
6125          return;
6126       }
6127       default:
6128          unreachable("Wrong dst size for nir_intrinsic_load_scratch");
6129    }
6130
6131    bld.mubuf(op, Definition(dst), rsrc, offset, ctx->program->scratch_offset, 0, true);
6132    emit_split_vector(ctx, dst, instr->num_components);
6133 }
6134
6135 void visit_store_scratch(isel_context *ctx, nir_intrinsic_instr *instr) {
6136    assert(instr->src[0].ssa->bit_size == 32 || instr->src[0].ssa->bit_size == 64);
6137    Builder bld(ctx->program, ctx->block);
6138    Temp rsrc = get_scratch_resource(ctx);
6139    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
6140    Temp offset = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
6141
6142    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
6143    unsigned writemask = nir_intrinsic_write_mask(instr);
6144
6145    while (writemask) {
6146       int start, count;
6147       u_bit_scan_consecutive_range(&writemask, &start, &count);
6148       int num_bytes = count * elem_size_bytes;
6149
6150       if (num_bytes > 16) {
6151          assert(elem_size_bytes == 8);
6152          writemask |= (((count - 2) << 1) - 1) << (start + 2);
6153          count = 2;
6154          num_bytes = 16;
6155       }
6156
6157       // TODO: check alignment of sub-dword stores
6158       // TODO: split 3 bytes. there is no store instruction for that
6159
6160       Temp write_data;
6161       if (count != instr->num_components) {
6162          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
6163          for (int i = 0; i < count; i++) {
6164             Temp elem = emit_extract_vector(ctx, data, start + i, RegClass(RegType::vgpr, elem_size_bytes / 4));
6165             vec->operands[i] = Operand(elem);
6166          }
6167          write_data = bld.tmp(RegClass(RegType::vgpr, count * elem_size_bytes / 4));
6168          vec->definitions[0] = Definition(write_data);
6169          ctx->block->instructions.emplace_back(std::move(vec));
6170       } else {
6171          write_data = data;
6172       }
6173
6174       aco_opcode op;
6175       switch (num_bytes) {
6176          case 4:
6177             op = aco_opcode::buffer_store_dword;
6178             break;
6179          case 8:
6180             op = aco_opcode::buffer_store_dwordx2;
6181             break;
6182          case 12:
6183             op = aco_opcode::buffer_store_dwordx3;
6184             break;
6185          case 16:
6186             op = aco_opcode::buffer_store_dwordx4;
6187             break;
6188          default:
6189             unreachable("Invalid data size for nir_intrinsic_store_scratch.");
6190       }
6191
6192       bld.mubuf(op, rsrc, offset, ctx->program->scratch_offset, write_data, start * elem_size_bytes, true);
6193    }
6194 }
6195
6196 void visit_load_sample_mask_in(isel_context *ctx, nir_intrinsic_instr *instr) {
6197    uint8_t log2_ps_iter_samples;
6198    if (ctx->program->info->ps.force_persample) {
6199       log2_ps_iter_samples =
6200          util_logbase2(ctx->options->key.fs.num_samples);
6201    } else {
6202       log2_ps_iter_samples = ctx->options->key.fs.log2_ps_iter_samples;
6203    }
6204
6205    /* The bit pattern matches that used by fixed function fragment
6206     * processing. */
6207    static const unsigned ps_iter_masks[] = {
6208       0xffff, /* not used */
6209       0x5555,
6210       0x1111,
6211       0x0101,
6212       0x0001,
6213    };
6214    assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
6215
6216    Builder bld(ctx->program, ctx->block);
6217
6218    Temp sample_id = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1),
6219                              get_arg(ctx, ctx->args->ac.ancillary), Operand(8u), Operand(4u));
6220    Temp ps_iter_mask = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(ps_iter_masks[log2_ps_iter_samples]));
6221    Temp mask = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), sample_id, ps_iter_mask);
6222    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6223    bld.vop2(aco_opcode::v_and_b32, Definition(dst), mask, get_arg(ctx, ctx->args->ac.sample_coverage));
6224 }
6225
6226 void visit_emit_vertex_with_counter(isel_context *ctx, nir_intrinsic_instr *instr) {
6227    Builder bld(ctx->program, ctx->block);
6228
6229    unsigned stream = nir_intrinsic_stream_id(instr);
6230    Temp next_vertex = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
6231    next_vertex = bld.v_mul_imm(bld.def(v1), next_vertex, 4u);
6232    nir_const_value *next_vertex_cv = nir_src_as_const_value(instr->src[0]);
6233
6234    /* get GSVS ring */
6235    Temp gsvs_ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_GSVS_GS * 16u));
6236
6237    unsigned num_components =
6238       ctx->program->info->gs.num_stream_output_components[stream];
6239    assert(num_components);
6240
6241    unsigned stride = 4u * num_components * ctx->shader->info.gs.vertices_out;
6242    unsigned stream_offset = 0;
6243    for (unsigned i = 0; i < stream; i++) {
6244       unsigned prev_stride = 4u * ctx->program->info->gs.num_stream_output_components[i] * ctx->shader->info.gs.vertices_out;
6245       stream_offset += prev_stride * ctx->program->wave_size;
6246    }
6247
6248    /* Limit on the stride field for <= GFX7. */
6249    assert(stride < (1 << 14));
6250
6251    Temp gsvs_dwords[4];
6252    for (unsigned i = 0; i < 4; i++)
6253       gsvs_dwords[i] = bld.tmp(s1);
6254    bld.pseudo(aco_opcode::p_split_vector,
6255               Definition(gsvs_dwords[0]),
6256               Definition(gsvs_dwords[1]),
6257               Definition(gsvs_dwords[2]),
6258               Definition(gsvs_dwords[3]),
6259               gsvs_ring);
6260
6261    if (stream_offset) {
6262       Temp stream_offset_tmp = bld.copy(bld.def(s1), Operand(stream_offset));
6263
6264       Temp carry = bld.tmp(s1);
6265       gsvs_dwords[0] = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), gsvs_dwords[0], stream_offset_tmp);
6266       gsvs_dwords[1] = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), gsvs_dwords[1], Operand(0u), bld.scc(carry));
6267    }
6268
6269    gsvs_dwords[1] = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), gsvs_dwords[1], Operand(S_008F04_STRIDE(stride)));
6270    gsvs_dwords[2] = bld.copy(bld.def(s1), Operand((uint32_t)ctx->program->wave_size));
6271
6272    gsvs_ring = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
6273                           gsvs_dwords[0], gsvs_dwords[1], gsvs_dwords[2], gsvs_dwords[3]);
6274
6275    unsigned offset = 0;
6276    for (unsigned i = 0; i <= VARYING_SLOT_VAR31; i++) {
6277       if (ctx->program->info->gs.output_streams[i] != stream)
6278          continue;
6279
6280       for (unsigned j = 0; j < 4; j++) {
6281          if (!(ctx->program->info->gs.output_usage_mask[i] & (1 << j)))
6282             continue;
6283
6284          if (ctx->outputs.mask[i] & (1 << j)) {
6285             Operand vaddr_offset = next_vertex_cv ? Operand(v1) : Operand(next_vertex);
6286             unsigned const_offset = (offset + (next_vertex_cv ? next_vertex_cv->u32 : 0u)) * 4u;
6287             if (const_offset >= 4096u) {
6288                if (vaddr_offset.isUndefined())
6289                   vaddr_offset = bld.copy(bld.def(v1), Operand(const_offset / 4096u * 4096u));
6290                else
6291                   vaddr_offset = bld.vadd32(bld.def(v1), Operand(const_offset / 4096u * 4096u), vaddr_offset);
6292                const_offset %= 4096u;
6293             }
6294
6295             aco_ptr<MTBUF_instruction> mtbuf{create_instruction<MTBUF_instruction>(aco_opcode::tbuffer_store_format_x, Format::MTBUF, 4, 0)};
6296             mtbuf->operands[0] = Operand(gsvs_ring);
6297             mtbuf->operands[1] = vaddr_offset;
6298             mtbuf->operands[2] = Operand(get_arg(ctx, ctx->args->gs2vs_offset));
6299             mtbuf->operands[3] = Operand(ctx->outputs.outputs[i][j]);
6300             mtbuf->offen = !vaddr_offset.isUndefined();
6301             mtbuf->dfmt = V_008F0C_BUF_DATA_FORMAT_32;
6302             mtbuf->nfmt = V_008F0C_BUF_NUM_FORMAT_UINT;
6303             mtbuf->offset = const_offset;
6304             mtbuf->glc = true;
6305             mtbuf->slc = true;
6306             mtbuf->barrier = barrier_gs_data;
6307             mtbuf->can_reorder = true;
6308             bld.insert(std::move(mtbuf));
6309          }
6310
6311          offset += ctx->shader->info.gs.vertices_out;
6312       }
6313
6314       /* outputs for the next vertex are undefined and keeping them around can
6315        * create invalid IR with control flow */
6316       ctx->outputs.mask[i] = 0;
6317    }
6318
6319    bld.sopp(aco_opcode::s_sendmsg, bld.m0(ctx->gs_wave_id), -1, sendmsg_gs(false, true, stream));
6320 }
6321
6322 Temp emit_boolean_reduce(isel_context *ctx, nir_op op, unsigned cluster_size, Temp src)
6323 {
6324    Builder bld(ctx->program, ctx->block);
6325
6326    if (cluster_size == 1) {
6327       return src;
6328    } if (op == nir_op_iand && cluster_size == 4) {
6329       //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6330       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src);
6331       return bld.sop1(Builder::s_not, bld.def(bld.lm), bld.def(s1, scc),
6332                       bld.sop1(Builder::s_wqm, bld.def(bld.lm), bld.def(s1, scc), tmp));
6333    } else if (op == nir_op_ior && cluster_size == 4) {
6334       //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6335       return bld.sop1(Builder::s_wqm, bld.def(bld.lm), bld.def(s1, scc),
6336                       bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm)));
6337    } else if (op == nir_op_iand && cluster_size == ctx->program->wave_size) {
6338       //subgroupAnd(val) -> (exec & ~val) == 0
6339       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src).def(1).getTemp();
6340       Temp cond = bool_to_vector_condition(ctx, emit_wqm(ctx, tmp));
6341       return bld.sop1(Builder::s_not, bld.def(bld.lm), bld.def(s1, scc), cond);
6342    } else if (op == nir_op_ior && cluster_size == ctx->program->wave_size) {
6343       //subgroupOr(val) -> (val & exec) != 0
6344       Temp tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm)).def(1).getTemp();
6345       return bool_to_vector_condition(ctx, tmp);
6346    } else if (op == nir_op_ixor && cluster_size == ctx->program->wave_size) {
6347       //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6348       Temp tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
6349       tmp = bld.sop1(Builder::s_bcnt1_i32, bld.def(s1), bld.def(s1, scc), tmp);
6350       tmp = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), tmp, Operand(1u)).def(1).getTemp();
6351       return bool_to_vector_condition(ctx, tmp);
6352    } else {
6353       //subgroupClustered{And,Or,Xor}(val, n) ->
6354       //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ;  just v_mbcnt_lo_u32_b32 on wave32
6355       //cluster_offset = ~(n - 1) & lane_id
6356       //cluster_mask = ((1 << n) - 1)
6357       //subgroupClusteredAnd():
6358       //   return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6359       //subgroupClusteredOr():
6360       //   return ((val & exec) >> cluster_offset) & cluster_mask != 0
6361       //subgroupClusteredXor():
6362       //   return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6363       Temp lane_id = emit_mbcnt(ctx, bld.def(v1));
6364       Temp cluster_offset = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(~uint32_t(cluster_size - 1)), lane_id);
6365
6366       Temp tmp;
6367       if (op == nir_op_iand)
6368          tmp = bld.sop2(Builder::s_orn2, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
6369       else
6370          tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
6371
6372       uint32_t cluster_mask = cluster_size == 32 ? -1 : (1u << cluster_size) - 1u;
6373
6374       if (ctx->program->chip_class <= GFX7)
6375          tmp = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), tmp, cluster_offset);
6376       else if (ctx->program->wave_size == 64)
6377          tmp = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), cluster_offset, tmp);
6378       else
6379          tmp = bld.vop2_e64(aco_opcode::v_lshrrev_b32, bld.def(v1), cluster_offset, tmp);
6380       tmp = emit_extract_vector(ctx, tmp, 0, v1);
6381       if (cluster_mask != 0xffffffff)
6382          tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(cluster_mask), tmp);
6383
6384       Definition cmp_def = Definition();
6385       if (op == nir_op_iand) {
6386          cmp_def = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm), Operand(cluster_mask), tmp).def(0);
6387       } else if (op == nir_op_ior) {
6388          cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp).def(0);
6389       } else if (op == nir_op_ixor) {
6390          tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u),
6391                         bld.vop3(aco_opcode::v_bcnt_u32_b32, bld.def(v1), tmp, Operand(0u)));
6392          cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp).def(0);
6393       }
6394       cmp_def.setHint(vcc);
6395       return cmp_def.getTemp();
6396    }
6397 }
6398
6399 Temp emit_boolean_exclusive_scan(isel_context *ctx, nir_op op, Temp src)
6400 {
6401    Builder bld(ctx->program, ctx->block);
6402
6403    //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
6404    //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
6405    //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
6406    Temp tmp;
6407    if (op == nir_op_iand)
6408       tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src);
6409    else
6410       tmp = bld.sop2(Builder::s_and, bld.def(s2), bld.def(s1, scc), src, Operand(exec, bld.lm));
6411
6412    Builder::Result lohi = bld.pseudo(aco_opcode::p_split_vector, bld.def(s1), bld.def(s1), tmp);
6413    Temp lo = lohi.def(0).getTemp();
6414    Temp hi = lohi.def(1).getTemp();
6415    Temp mbcnt = emit_mbcnt(ctx, bld.def(v1), Operand(lo), Operand(hi));
6416
6417    Definition cmp_def = Definition();
6418    if (op == nir_op_iand)
6419       cmp_def = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm), Operand(0u), mbcnt).def(0);
6420    else if (op == nir_op_ior)
6421       cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), mbcnt).def(0);
6422    else if (op == nir_op_ixor)
6423       cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u),
6424                          bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u), mbcnt)).def(0);
6425    cmp_def.setHint(vcc);
6426    return cmp_def.getTemp();
6427 }
6428
6429 Temp emit_boolean_inclusive_scan(isel_context *ctx, nir_op op, Temp src)
6430 {
6431    Builder bld(ctx->program, ctx->block);
6432
6433    //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
6434    //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
6435    //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
6436    Temp tmp = emit_boolean_exclusive_scan(ctx, op, src);
6437    if (op == nir_op_iand)
6438       return bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
6439    else if (op == nir_op_ior)
6440       return bld.sop2(Builder::s_or, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
6441    else if (op == nir_op_ixor)
6442       return bld.sop2(Builder::s_xor, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
6443
6444    assert(false);
6445    return Temp();
6446 }
6447
6448 void emit_uniform_subgroup(isel_context *ctx, nir_intrinsic_instr *instr, Temp src)
6449 {
6450    Builder bld(ctx->program, ctx->block);
6451    Definition dst(get_ssa_temp(ctx, &instr->dest.ssa));
6452    if (src.regClass().type() == RegType::vgpr) {
6453       bld.pseudo(aco_opcode::p_as_uniform, dst, src);
6454    } else if (src.regClass() == s1) {
6455       bld.sop1(aco_opcode::s_mov_b32, dst, src);
6456    } else if (src.regClass() == s2) {
6457       bld.sop1(aco_opcode::s_mov_b64, dst, src);
6458    } else {
6459       fprintf(stderr, "Unimplemented NIR instr bit size: ");
6460       nir_print_instr(&instr->instr, stderr);
6461       fprintf(stderr, "\n");
6462    }
6463 }
6464
6465 void emit_interp_center(isel_context *ctx, Temp dst, Temp pos1, Temp pos2)
6466 {
6467    Builder bld(ctx->program, ctx->block);
6468    Temp persp_center = get_arg(ctx, ctx->args->ac.persp_center);
6469    Temp p1 = emit_extract_vector(ctx, persp_center, 0, v1);
6470    Temp p2 = emit_extract_vector(ctx, persp_center, 1, v1);
6471
6472    Temp ddx_1, ddx_2, ddy_1, ddy_2;
6473    uint32_t dpp_ctrl0 = dpp_quad_perm(0, 0, 0, 0);
6474    uint32_t dpp_ctrl1 = dpp_quad_perm(1, 1, 1, 1);
6475    uint32_t dpp_ctrl2 = dpp_quad_perm(2, 2, 2, 2);
6476
6477    /* Build DD X/Y */
6478    if (ctx->program->chip_class >= GFX8) {
6479       Temp tl_1 = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), p1, dpp_ctrl0);
6480       ddx_1 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p1, tl_1, dpp_ctrl1);
6481       ddy_1 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p1, tl_1, dpp_ctrl2);
6482       Temp tl_2 = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), p2, dpp_ctrl0);
6483       ddx_2 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p2, tl_2, dpp_ctrl1);
6484       ddy_2 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p2, tl_2, dpp_ctrl2);
6485    } else {
6486       Temp tl_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl0);
6487       ddx_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl1);
6488       ddx_1 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddx_1, tl_1);
6489       ddx_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl2);
6490       ddx_2 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddx_2, tl_1);
6491       Temp tl_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl0);
6492       ddy_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl1);
6493       ddy_1 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddy_1, tl_2);
6494       ddy_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl2);
6495       ddy_2 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddy_2, tl_2);
6496    }
6497
6498    /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
6499    Temp tmp1 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddx_1, pos1, p1);
6500    Temp tmp2 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddx_2, pos1, p2);
6501    tmp1 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddy_1, pos2, tmp1);
6502    tmp2 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddy_2, pos2, tmp2);
6503    Temp wqm1 = bld.tmp(v1);
6504    emit_wqm(ctx, tmp1, wqm1, true);
6505    Temp wqm2 = bld.tmp(v1);
6506    emit_wqm(ctx, tmp2, wqm2, true);
6507    bld.pseudo(aco_opcode::p_create_vector, Definition(dst), wqm1, wqm2);
6508    return;
6509 }
6510
6511 void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr)
6512 {
6513    Builder bld(ctx->program, ctx->block);
6514    switch(instr->intrinsic) {
6515    case nir_intrinsic_load_barycentric_sample:
6516    case nir_intrinsic_load_barycentric_pixel:
6517    case nir_intrinsic_load_barycentric_centroid: {
6518       glsl_interp_mode mode = (glsl_interp_mode)nir_intrinsic_interp_mode(instr);
6519       Temp bary = Temp(0, s2);
6520       switch (mode) {
6521       case INTERP_MODE_SMOOTH:
6522       case INTERP_MODE_NONE:
6523          if (instr->intrinsic == nir_intrinsic_load_barycentric_pixel)
6524             bary = get_arg(ctx, ctx->args->ac.persp_center);
6525          else if (instr->intrinsic == nir_intrinsic_load_barycentric_centroid)
6526             bary = ctx->persp_centroid;
6527          else if (instr->intrinsic == nir_intrinsic_load_barycentric_sample)
6528             bary = get_arg(ctx, ctx->args->ac.persp_sample);
6529          break;
6530       case INTERP_MODE_NOPERSPECTIVE:
6531          if (instr->intrinsic == nir_intrinsic_load_barycentric_pixel)
6532             bary = get_arg(ctx, ctx->args->ac.linear_center);
6533          else if (instr->intrinsic == nir_intrinsic_load_barycentric_centroid)
6534             bary = ctx->linear_centroid;
6535          else if (instr->intrinsic == nir_intrinsic_load_barycentric_sample)
6536             bary = get_arg(ctx, ctx->args->ac.linear_sample);
6537          break;
6538       default:
6539          break;
6540       }
6541       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6542       Temp p1 = emit_extract_vector(ctx, bary, 0, v1);
6543       Temp p2 = emit_extract_vector(ctx, bary, 1, v1);
6544       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
6545                  Operand(p1), Operand(p2));
6546       emit_split_vector(ctx, dst, 2);
6547       break;
6548    }
6549    case nir_intrinsic_load_barycentric_model: {
6550       Temp model = get_arg(ctx, ctx->args->ac.pull_model);
6551
6552       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6553       Temp p1 = emit_extract_vector(ctx, model, 0, v1);
6554       Temp p2 = emit_extract_vector(ctx, model, 1, v1);
6555       Temp p3 = emit_extract_vector(ctx, model, 2, v1);
6556       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
6557                  Operand(p1), Operand(p2), Operand(p3));
6558       emit_split_vector(ctx, dst, 3);
6559       break;
6560    }
6561    case nir_intrinsic_load_barycentric_at_sample: {
6562       uint32_t sample_pos_offset = RING_PS_SAMPLE_POSITIONS * 16;
6563       switch (ctx->options->key.fs.num_samples) {
6564          case 2: sample_pos_offset += 1 << 3; break;
6565          case 4: sample_pos_offset += 3 << 3; break;
6566          case 8: sample_pos_offset += 7 << 3; break;
6567          default: break;
6568       }
6569       Temp sample_pos;
6570       Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
6571       nir_const_value* const_addr = nir_src_as_const_value(instr->src[0]);
6572       Temp private_segment_buffer = ctx->program->private_segment_buffer;
6573       if (addr.type() == RegType::sgpr) {
6574          Operand offset;
6575          if (const_addr) {
6576             sample_pos_offset += const_addr->u32 << 3;
6577             offset = Operand(sample_pos_offset);
6578          } else if (ctx->options->chip_class >= GFX9) {
6579             offset = bld.sop2(aco_opcode::s_lshl3_add_u32, bld.def(s1), bld.def(s1, scc), addr, Operand(sample_pos_offset));
6580          } else {
6581             offset = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), addr, Operand(3u));
6582             offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), addr, Operand(sample_pos_offset));
6583          }
6584
6585          Operand off = bld.copy(bld.def(s1), Operand(offset));
6586          sample_pos = bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), private_segment_buffer, off);
6587
6588       } else if (ctx->options->chip_class >= GFX9) {
6589          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
6590          sample_pos = bld.global(aco_opcode::global_load_dwordx2, bld.def(v2), addr, private_segment_buffer, sample_pos_offset);
6591       } else if (ctx->options->chip_class >= GFX7) {
6592          /* addr += private_segment_buffer + sample_pos_offset */
6593          Temp tmp0 = bld.tmp(s1);
6594          Temp tmp1 = bld.tmp(s1);
6595          bld.pseudo(aco_opcode::p_split_vector, Definition(tmp0), Definition(tmp1), private_segment_buffer);
6596          Definition scc_tmp = bld.def(s1, scc);
6597          tmp0 = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), scc_tmp, tmp0, Operand(sample_pos_offset));
6598          tmp1 = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), tmp1, Operand(0u), bld.scc(scc_tmp.getTemp()));
6599          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
6600          Temp pck0 = bld.tmp(v1);
6601          Temp carry = bld.vadd32(Definition(pck0), tmp0, addr, true).def(1).getTemp();
6602          tmp1 = as_vgpr(ctx, tmp1);
6603          Temp pck1 = bld.vop2_e64(aco_opcode::v_addc_co_u32, bld.def(v1), bld.hint_vcc(bld.def(bld.lm)), tmp1, Operand(0u), carry);
6604          addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), pck0, pck1);
6605
6606          /* sample_pos = flat_load_dwordx2 addr */
6607          sample_pos = bld.flat(aco_opcode::flat_load_dwordx2, bld.def(v2), addr, Operand(s1));
6608       } else {
6609          assert(ctx->options->chip_class == GFX6);
6610
6611          uint32_t rsrc_conf = S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
6612                               S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
6613          Temp rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), private_segment_buffer, Operand(0u), Operand(rsrc_conf));
6614
6615          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
6616          addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), addr, Operand(0u));
6617
6618          sample_pos = bld.tmp(v2);
6619
6620          aco_ptr<MUBUF_instruction> load{create_instruction<MUBUF_instruction>(aco_opcode::buffer_load_dwordx2, Format::MUBUF, 3, 1)};
6621          load->definitions[0] = Definition(sample_pos);
6622          load->operands[0] = Operand(rsrc);
6623          load->operands[1] = Operand(addr);
6624          load->operands[2] = Operand(0u);
6625          load->offset = sample_pos_offset;
6626          load->offen = 0;
6627          load->addr64 = true;
6628          load->glc = false;
6629          load->dlc = false;
6630          load->disable_wqm = false;
6631          load->barrier = barrier_none;
6632          load->can_reorder = true;
6633          ctx->block->instructions.emplace_back(std::move(load));
6634       }
6635
6636       /* sample_pos -= 0.5 */
6637       Temp pos1 = bld.tmp(RegClass(sample_pos.type(), 1));
6638       Temp pos2 = bld.tmp(RegClass(sample_pos.type(), 1));
6639       bld.pseudo(aco_opcode::p_split_vector, Definition(pos1), Definition(pos2), sample_pos);
6640       pos1 = bld.vop2_e64(aco_opcode::v_sub_f32, bld.def(v1), pos1, Operand(0x3f000000u));
6641       pos2 = bld.vop2_e64(aco_opcode::v_sub_f32, bld.def(v1), pos2, Operand(0x3f000000u));
6642
6643       emit_interp_center(ctx, get_ssa_temp(ctx, &instr->dest.ssa), pos1, pos2);
6644       break;
6645    }
6646    case nir_intrinsic_load_barycentric_at_offset: {
6647       Temp offset = get_ssa_temp(ctx, instr->src[0].ssa);
6648       RegClass rc = RegClass(offset.type(), 1);
6649       Temp pos1 = bld.tmp(rc), pos2 = bld.tmp(rc);
6650       bld.pseudo(aco_opcode::p_split_vector, Definition(pos1), Definition(pos2), offset);
6651       emit_interp_center(ctx, get_ssa_temp(ctx, &instr->dest.ssa), pos1, pos2);
6652       break;
6653    }
6654    case nir_intrinsic_load_front_face: {
6655       bld.vopc(aco_opcode::v_cmp_lg_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6656                Operand(0u), get_arg(ctx, ctx->args->ac.front_face)).def(0).setHint(vcc);
6657       break;
6658    }
6659    case nir_intrinsic_load_view_index: {
6660       if (ctx->stage & (sw_vs | sw_gs | sw_tcs | sw_tes)) {
6661          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6662          bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.view_index)));
6663          break;
6664       }
6665
6666       /* fallthrough */
6667    }
6668    case nir_intrinsic_load_layer_id: {
6669       unsigned idx = nir_intrinsic_base(instr);
6670       bld.vintrp(aco_opcode::v_interp_mov_f32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6671                  Operand(2u), bld.m0(get_arg(ctx, ctx->args->ac.prim_mask)), idx, 0);
6672       break;
6673    }
6674    case nir_intrinsic_load_frag_coord: {
6675       emit_load_frag_coord(ctx, get_ssa_temp(ctx, &instr->dest.ssa), 4);
6676       break;
6677    }
6678    case nir_intrinsic_load_sample_pos: {
6679       Temp posx = get_arg(ctx, ctx->args->ac.frag_pos[0]);
6680       Temp posy = get_arg(ctx, ctx->args->ac.frag_pos[1]);
6681       bld.pseudo(aco_opcode::p_create_vector, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6682                  posx.id() ? bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), posx) : Operand(0u),
6683                  posy.id() ? bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), posy) : Operand(0u));
6684       break;
6685    }
6686    case nir_intrinsic_load_tess_coord:
6687       visit_load_tess_coord(ctx, instr);
6688       break;
6689    case nir_intrinsic_load_interpolated_input:
6690       visit_load_interpolated_input(ctx, instr);
6691       break;
6692    case nir_intrinsic_store_output:
6693       visit_store_output(ctx, instr);
6694       break;
6695    case nir_intrinsic_load_input:
6696    case nir_intrinsic_load_input_vertex:
6697       visit_load_input(ctx, instr);
6698       break;
6699    case nir_intrinsic_load_output:
6700       visit_load_output(ctx, instr);
6701       break;
6702    case nir_intrinsic_load_per_vertex_input:
6703       visit_load_per_vertex_input(ctx, instr);
6704       break;
6705    case nir_intrinsic_load_per_vertex_output:
6706       visit_load_per_vertex_output(ctx, instr);
6707       break;
6708    case nir_intrinsic_store_per_vertex_output:
6709       visit_store_per_vertex_output(ctx, instr);
6710       break;
6711    case nir_intrinsic_load_ubo:
6712       visit_load_ubo(ctx, instr);
6713       break;
6714    case nir_intrinsic_load_push_constant:
6715       visit_load_push_constant(ctx, instr);
6716       break;
6717    case nir_intrinsic_load_constant:
6718       visit_load_constant(ctx, instr);
6719       break;
6720    case nir_intrinsic_vulkan_resource_index:
6721       visit_load_resource(ctx, instr);
6722       break;
6723    case nir_intrinsic_discard:
6724       visit_discard(ctx, instr);
6725       break;
6726    case nir_intrinsic_discard_if:
6727       visit_discard_if(ctx, instr);
6728       break;
6729    case nir_intrinsic_load_shared:
6730       visit_load_shared(ctx, instr);
6731       break;
6732    case nir_intrinsic_store_shared:
6733       visit_store_shared(ctx, instr);
6734       break;
6735    case nir_intrinsic_shared_atomic_add:
6736    case nir_intrinsic_shared_atomic_imin:
6737    case nir_intrinsic_shared_atomic_umin:
6738    case nir_intrinsic_shared_atomic_imax:
6739    case nir_intrinsic_shared_atomic_umax:
6740    case nir_intrinsic_shared_atomic_and:
6741    case nir_intrinsic_shared_atomic_or:
6742    case nir_intrinsic_shared_atomic_xor:
6743    case nir_intrinsic_shared_atomic_exchange:
6744    case nir_intrinsic_shared_atomic_comp_swap:
6745       visit_shared_atomic(ctx, instr);
6746       break;
6747    case nir_intrinsic_image_deref_load:
6748       visit_image_load(ctx, instr);
6749       break;
6750    case nir_intrinsic_image_deref_store:
6751       visit_image_store(ctx, instr);
6752       break;
6753    case nir_intrinsic_image_deref_atomic_add:
6754    case nir_intrinsic_image_deref_atomic_umin:
6755    case nir_intrinsic_image_deref_atomic_imin:
6756    case nir_intrinsic_image_deref_atomic_umax:
6757    case nir_intrinsic_image_deref_atomic_imax:
6758    case nir_intrinsic_image_deref_atomic_and:
6759    case nir_intrinsic_image_deref_atomic_or:
6760    case nir_intrinsic_image_deref_atomic_xor:
6761    case nir_intrinsic_image_deref_atomic_exchange:
6762    case nir_intrinsic_image_deref_atomic_comp_swap:
6763       visit_image_atomic(ctx, instr);
6764       break;
6765    case nir_intrinsic_image_deref_size:
6766       visit_image_size(ctx, instr);
6767       break;
6768    case nir_intrinsic_load_ssbo:
6769       visit_load_ssbo(ctx, instr);
6770       break;
6771    case nir_intrinsic_store_ssbo:
6772       visit_store_ssbo(ctx, instr);
6773       break;
6774    case nir_intrinsic_load_global:
6775       visit_load_global(ctx, instr);
6776       break;
6777    case nir_intrinsic_store_global:
6778       visit_store_global(ctx, instr);
6779       break;
6780    case nir_intrinsic_global_atomic_add:
6781    case nir_intrinsic_global_atomic_imin:
6782    case nir_intrinsic_global_atomic_umin:
6783    case nir_intrinsic_global_atomic_imax:
6784    case nir_intrinsic_global_atomic_umax:
6785    case nir_intrinsic_global_atomic_and:
6786    case nir_intrinsic_global_atomic_or:
6787    case nir_intrinsic_global_atomic_xor:
6788    case nir_intrinsic_global_atomic_exchange:
6789    case nir_intrinsic_global_atomic_comp_swap:
6790       visit_global_atomic(ctx, instr);
6791       break;
6792    case nir_intrinsic_ssbo_atomic_add:
6793    case nir_intrinsic_ssbo_atomic_imin:
6794    case nir_intrinsic_ssbo_atomic_umin:
6795    case nir_intrinsic_ssbo_atomic_imax:
6796    case nir_intrinsic_ssbo_atomic_umax:
6797    case nir_intrinsic_ssbo_atomic_and:
6798    case nir_intrinsic_ssbo_atomic_or:
6799    case nir_intrinsic_ssbo_atomic_xor:
6800    case nir_intrinsic_ssbo_atomic_exchange:
6801    case nir_intrinsic_ssbo_atomic_comp_swap:
6802       visit_atomic_ssbo(ctx, instr);
6803       break;
6804    case nir_intrinsic_load_scratch:
6805       visit_load_scratch(ctx, instr);
6806       break;
6807    case nir_intrinsic_store_scratch:
6808       visit_store_scratch(ctx, instr);
6809       break;
6810    case nir_intrinsic_get_buffer_size:
6811       visit_get_buffer_size(ctx, instr);
6812       break;
6813    case nir_intrinsic_control_barrier: {
6814       if (ctx->program->chip_class == GFX6 && ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) {
6815          /* GFX6 only (thanks to a hw bug workaround):
6816           * The real barrier instruction isn’t needed, because an entire patch
6817           * always fits into a single wave.
6818           */
6819          break;
6820       }
6821
6822       if (ctx->shader->info.stage == MESA_SHADER_COMPUTE) {
6823          unsigned* bsize = ctx->program->info->cs.block_size;
6824          unsigned workgroup_size = bsize[0] * bsize[1] * bsize[2];
6825          if (workgroup_size > ctx->program->wave_size)
6826             bld.sopp(aco_opcode::s_barrier);
6827       } else if (ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) {
6828          /* For each patch provided during rendering, n TCS shader invocations will be processed,
6829           * where n is the number of vertices in the output patch.
6830           */
6831          unsigned workgroup_size = ctx->tcs_num_patches * ctx->shader->info.tess.tcs_vertices_out;
6832          if (workgroup_size > ctx->program->wave_size)
6833             bld.sopp(aco_opcode::s_barrier);
6834       } else {
6835          /* We don't know the workgroup size, so always emit the s_barrier. */
6836          bld.sopp(aco_opcode::s_barrier);
6837       }
6838
6839       break;
6840    }
6841    case nir_intrinsic_memory_barrier_tcs_patch:
6842    case nir_intrinsic_group_memory_barrier:
6843    case nir_intrinsic_memory_barrier:
6844    case nir_intrinsic_memory_barrier_buffer:
6845    case nir_intrinsic_memory_barrier_image:
6846    case nir_intrinsic_memory_barrier_shared:
6847       emit_memory_barrier(ctx, instr);
6848       break;
6849    case nir_intrinsic_load_num_work_groups: {
6850       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6851       bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.num_work_groups)));
6852       emit_split_vector(ctx, dst, 3);
6853       break;
6854    }
6855    case nir_intrinsic_load_local_invocation_id: {
6856       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6857       bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.local_invocation_ids)));
6858       emit_split_vector(ctx, dst, 3);
6859       break;
6860    }
6861    case nir_intrinsic_load_work_group_id: {
6862       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6863       struct ac_arg *args = ctx->args->ac.workgroup_ids;
6864       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
6865                  args[0].used ? Operand(get_arg(ctx, args[0])) : Operand(0u),
6866                  args[1].used ? Operand(get_arg(ctx, args[1])) : Operand(0u),
6867                  args[2].used ? Operand(get_arg(ctx, args[2])) : Operand(0u));
6868       emit_split_vector(ctx, dst, 3);
6869       break;
6870    }
6871    case nir_intrinsic_load_local_invocation_index: {
6872       Temp id = emit_mbcnt(ctx, bld.def(v1));
6873
6874       /* The tg_size bits [6:11] contain the subgroup id,
6875        * we need this multiplied by the wave size, and then OR the thread id to it.
6876        */
6877       if (ctx->program->wave_size == 64) {
6878          /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
6879          Temp tg_num = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0xfc0u),
6880                                 get_arg(ctx, ctx->args->ac.tg_size));
6881          bld.vop2(aco_opcode::v_or_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), tg_num, id);
6882       } else {
6883          /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR  */
6884          Temp tg_num = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
6885                                 get_arg(ctx, ctx->args->ac.tg_size), Operand(0x6u | (0x6u << 16)));
6886          bld.vop3(aco_opcode::v_lshl_or_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), tg_num, Operand(0x5u), id);
6887       }
6888       break;
6889    }
6890    case nir_intrinsic_load_subgroup_id: {
6891       if (ctx->stage == compute_cs) {
6892          bld.sop2(aco_opcode::s_bfe_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), bld.def(s1, scc),
6893                   get_arg(ctx, ctx->args->ac.tg_size), Operand(0x6u | (0x6u << 16)));
6894       } else {
6895          bld.sop1(aco_opcode::s_mov_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand(0x0u));
6896       }
6897       break;
6898    }
6899    case nir_intrinsic_load_subgroup_invocation: {
6900       emit_mbcnt(ctx, Definition(get_ssa_temp(ctx, &instr->dest.ssa)));
6901       break;
6902    }
6903    case nir_intrinsic_load_num_subgroups: {
6904       if (ctx->stage == compute_cs)
6905          bld.sop2(aco_opcode::s_and_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), bld.def(s1, scc), Operand(0x3fu),
6906                   get_arg(ctx, ctx->args->ac.tg_size));
6907       else
6908          bld.sop1(aco_opcode::s_mov_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand(0x1u));
6909       break;
6910    }
6911    case nir_intrinsic_ballot: {
6912       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6913       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6914       Definition tmp = bld.def(dst.regClass());
6915       Definition lanemask_tmp = dst.size() == bld.lm.size() ? tmp : bld.def(src.regClass());
6916       if (instr->src[0].ssa->bit_size == 1) {
6917          assert(src.regClass() == bld.lm);
6918          bld.sop2(Builder::s_and, lanemask_tmp, bld.def(s1, scc), Operand(exec, bld.lm), src);
6919       } else if (instr->src[0].ssa->bit_size == 32 && src.regClass() == v1) {
6920          bld.vopc(aco_opcode::v_cmp_lg_u32, lanemask_tmp, Operand(0u), src);
6921       } else if (instr->src[0].ssa->bit_size == 64 && src.regClass() == v2) {
6922          bld.vopc(aco_opcode::v_cmp_lg_u64, lanemask_tmp, Operand(0u), src);
6923       } else {
6924          fprintf(stderr, "Unimplemented NIR instr bit size: ");
6925          nir_print_instr(&instr->instr, stderr);
6926          fprintf(stderr, "\n");
6927       }
6928       if (dst.size() != bld.lm.size()) {
6929          /* Wave32 with ballot size set to 64 */
6930          bld.pseudo(aco_opcode::p_create_vector, Definition(tmp), lanemask_tmp.getTemp(), Operand(0u));
6931       }
6932       emit_wqm(ctx, tmp.getTemp(), dst);
6933       break;
6934    }
6935    case nir_intrinsic_shuffle:
6936    case nir_intrinsic_read_invocation: {
6937       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6938       if (!ctx->divergent_vals[instr->src[0].ssa->index]) {
6939          emit_uniform_subgroup(ctx, instr, src);
6940       } else {
6941          Temp tid = get_ssa_temp(ctx, instr->src[1].ssa);
6942          if (instr->intrinsic == nir_intrinsic_read_invocation || !ctx->divergent_vals[instr->src[1].ssa->index])
6943             tid = bld.as_uniform(tid);
6944          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6945          if (src.regClass() == v1) {
6946             emit_wqm(ctx, emit_bpermute(ctx, bld, tid, src), dst);
6947          } else if (src.regClass() == v2) {
6948             Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6949             bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6950             lo = emit_wqm(ctx, emit_bpermute(ctx, bld, tid, lo));
6951             hi = emit_wqm(ctx, emit_bpermute(ctx, bld, tid, hi));
6952             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6953             emit_split_vector(ctx, dst, 2);
6954          } else if (instr->dest.ssa.bit_size == 1 && tid.regClass() == s1) {
6955             assert(src.regClass() == bld.lm);
6956             Temp tmp = bld.sopc(Builder::s_bitcmp1, bld.def(s1, scc), src, tid);
6957             bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
6958          } else if (instr->dest.ssa.bit_size == 1 && tid.regClass() == v1) {
6959             assert(src.regClass() == bld.lm);
6960             Temp tmp;
6961             if (ctx->program->chip_class <= GFX7)
6962                tmp = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), src, tid);
6963             else if (ctx->program->wave_size == 64)
6964                tmp = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), tid, src);
6965             else
6966                tmp = bld.vop2_e64(aco_opcode::v_lshrrev_b32, bld.def(v1), tid, src);
6967             tmp = emit_extract_vector(ctx, tmp, 0, v1);
6968             tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u), tmp);
6969             emit_wqm(ctx, bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp), dst);
6970          } else {
6971             fprintf(stderr, "Unimplemented NIR instr bit size: ");
6972             nir_print_instr(&instr->instr, stderr);
6973             fprintf(stderr, "\n");
6974          }
6975       }
6976       break;
6977    }
6978    case nir_intrinsic_load_sample_id: {
6979       bld.vop3(aco_opcode::v_bfe_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6980                get_arg(ctx, ctx->args->ac.ancillary), Operand(8u), Operand(4u));
6981       break;
6982    }
6983    case nir_intrinsic_load_sample_mask_in: {
6984       visit_load_sample_mask_in(ctx, instr);
6985       break;
6986    }
6987    case nir_intrinsic_read_first_invocation: {
6988       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6989       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6990       if (src.regClass() == v1) {
6991          emit_wqm(ctx,
6992                   bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), src),
6993                   dst);
6994       } else if (src.regClass() == v2) {
6995          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6996          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6997          lo = emit_wqm(ctx, bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), lo));
6998          hi = emit_wqm(ctx, bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), hi));
6999          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
7000          emit_split_vector(ctx, dst, 2);
7001       } else if (instr->dest.ssa.bit_size == 1) {
7002          assert(src.regClass() == bld.lm);
7003          Temp tmp = bld.sopc(Builder::s_bitcmp1, bld.def(s1, scc), src,
7004                              bld.sop1(Builder::s_ff1_i32, bld.def(s1), Operand(exec, bld.lm)));
7005          bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
7006       } else if (src.regClass() == s1) {
7007          bld.sop1(aco_opcode::s_mov_b32, Definition(dst), src);
7008       } else if (src.regClass() == s2) {
7009          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src);
7010       } else {
7011          fprintf(stderr, "Unimplemented NIR instr bit size: ");
7012          nir_print_instr(&instr->instr, stderr);
7013          fprintf(stderr, "\n");
7014       }
7015       break;
7016    }
7017    case nir_intrinsic_vote_all: {
7018       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7019       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7020       assert(src.regClass() == bld.lm);
7021       assert(dst.regClass() == bld.lm);
7022
7023       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src).def(1).getTemp();
7024       Temp cond = bool_to_vector_condition(ctx, emit_wqm(ctx, tmp));
7025       bld.sop1(Builder::s_not, Definition(dst), bld.def(s1, scc), cond);
7026       break;
7027    }
7028    case nir_intrinsic_vote_any: {
7029       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7030       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7031       assert(src.regClass() == bld.lm);
7032       assert(dst.regClass() == bld.lm);
7033
7034       Temp tmp = bool_to_scalar_condition(ctx, src);
7035       bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
7036       break;
7037    }
7038    case nir_intrinsic_reduce:
7039    case nir_intrinsic_inclusive_scan:
7040    case nir_intrinsic_exclusive_scan: {
7041       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7042       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7043       nir_op op = (nir_op) nir_intrinsic_reduction_op(instr);
7044       unsigned cluster_size = instr->intrinsic == nir_intrinsic_reduce ?
7045          nir_intrinsic_cluster_size(instr) : 0;
7046       cluster_size = util_next_power_of_two(MIN2(cluster_size ? cluster_size : ctx->program->wave_size, ctx->program->wave_size));
7047
7048       if (!ctx->divergent_vals[instr->src[0].ssa->index] && (op == nir_op_ior || op == nir_op_iand)) {
7049          emit_uniform_subgroup(ctx, instr, src);
7050       } else if (instr->dest.ssa.bit_size == 1) {
7051          if (op == nir_op_imul || op == nir_op_umin || op == nir_op_imin)
7052             op = nir_op_iand;
7053          else if (op == nir_op_iadd)
7054             op = nir_op_ixor;
7055          else if (op == nir_op_umax || op == nir_op_imax)
7056             op = nir_op_ior;
7057          assert(op == nir_op_iand || op == nir_op_ior || op == nir_op_ixor);
7058
7059          switch (instr->intrinsic) {
7060          case nir_intrinsic_reduce:
7061             emit_wqm(ctx, emit_boolean_reduce(ctx, op, cluster_size, src), dst);
7062             break;
7063          case nir_intrinsic_exclusive_scan:
7064             emit_wqm(ctx, emit_boolean_exclusive_scan(ctx, op, src), dst);
7065             break;
7066          case nir_intrinsic_inclusive_scan:
7067             emit_wqm(ctx, emit_boolean_inclusive_scan(ctx, op, src), dst);
7068             break;
7069          default:
7070             assert(false);
7071          }
7072       } else if (cluster_size == 1) {
7073          bld.copy(Definition(dst), src);
7074       } else {
7075          src = as_vgpr(ctx, src);
7076
7077          ReduceOp reduce_op;
7078          switch (op) {
7079          #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
7080             CASE(iadd)
7081             CASE(imul)
7082             CASE(fadd)
7083             CASE(fmul)
7084             CASE(imin)
7085             CASE(umin)
7086             CASE(fmin)
7087             CASE(imax)
7088             CASE(umax)
7089             CASE(fmax)
7090             CASE(iand)
7091             CASE(ior)
7092             CASE(ixor)
7093             default:
7094                unreachable("unknown reduction op");
7095          #undef CASE
7096          }
7097
7098          aco_opcode aco_op;
7099          switch (instr->intrinsic) {
7100             case nir_intrinsic_reduce: aco_op = aco_opcode::p_reduce; break;
7101             case nir_intrinsic_inclusive_scan: aco_op = aco_opcode::p_inclusive_scan; break;
7102             case nir_intrinsic_exclusive_scan: aco_op = aco_opcode::p_exclusive_scan; break;
7103             default:
7104                unreachable("unknown reduce intrinsic");
7105          }
7106
7107          aco_ptr<Pseudo_reduction_instruction> reduce{create_instruction<Pseudo_reduction_instruction>(aco_op, Format::PSEUDO_REDUCTION, 3, 5)};
7108          reduce->operands[0] = Operand(src);
7109          // filled in by aco_reduce_assign.cpp, used internally as part of the
7110          // reduce sequence
7111          assert(dst.size() == 1 || dst.size() == 2);
7112          reduce->operands[1] = Operand(RegClass(RegType::vgpr, dst.size()).as_linear());
7113          reduce->operands[2] = Operand(v1.as_linear());
7114
7115          Temp tmp_dst = bld.tmp(dst.regClass());
7116          reduce->definitions[0] = Definition(tmp_dst);
7117          reduce->definitions[1] = bld.def(ctx->program->lane_mask); // used internally
7118          reduce->definitions[2] = Definition();
7119          reduce->definitions[3] = Definition(scc, s1);
7120          reduce->definitions[4] = Definition();
7121          reduce->reduce_op = reduce_op;
7122          reduce->cluster_size = cluster_size;
7123          ctx->block->instructions.emplace_back(std::move(reduce));
7124
7125          emit_wqm(ctx, tmp_dst, dst);
7126       }
7127       break;
7128    }
7129    case nir_intrinsic_quad_broadcast: {
7130       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7131       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
7132          emit_uniform_subgroup(ctx, instr, src);
7133       } else {
7134          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7135          unsigned lane = nir_src_as_const_value(instr->src[1])->u32;
7136          uint32_t dpp_ctrl = dpp_quad_perm(lane, lane, lane, lane);
7137
7138          if (instr->dest.ssa.bit_size == 1) {
7139             assert(src.regClass() == bld.lm);
7140             assert(dst.regClass() == bld.lm);
7141             uint32_t half_mask = 0x11111111u << lane;
7142             Temp mask_tmp = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(half_mask), Operand(half_mask));
7143             Temp tmp = bld.tmp(bld.lm);
7144             bld.sop1(Builder::s_wqm, Definition(tmp),
7145                      bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), mask_tmp,
7146                               bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm))));
7147             emit_wqm(ctx, tmp, dst);
7148          } else if (instr->dest.ssa.bit_size == 32) {
7149             if (ctx->program->chip_class >= GFX8)
7150                emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl), dst);
7151             else
7152                emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl), dst);
7153          } else if (instr->dest.ssa.bit_size == 64) {
7154             Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
7155             bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
7156             if (ctx->program->chip_class >= GFX8) {
7157                lo = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), lo, dpp_ctrl));
7158                hi = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), hi, dpp_ctrl));
7159             } else {
7160                lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, (1 << 15) | dpp_ctrl));
7161                hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, (1 << 15) | dpp_ctrl));
7162             }
7163             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
7164             emit_split_vector(ctx, dst, 2);
7165          } else {
7166             fprintf(stderr, "Unimplemented NIR instr bit size: ");
7167             nir_print_instr(&instr->instr, stderr);
7168             fprintf(stderr, "\n");
7169          }
7170       }
7171       break;
7172    }
7173    case nir_intrinsic_quad_swap_horizontal:
7174    case nir_intrinsic_quad_swap_vertical:
7175    case nir_intrinsic_quad_swap_diagonal:
7176    case nir_intrinsic_quad_swizzle_amd: {
7177       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7178       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
7179          emit_uniform_subgroup(ctx, instr, src);
7180          break;
7181       }
7182       uint16_t dpp_ctrl = 0;
7183       switch (instr->intrinsic) {
7184       case nir_intrinsic_quad_swap_horizontal:
7185          dpp_ctrl = dpp_quad_perm(1, 0, 3, 2);
7186          break;
7187       case nir_intrinsic_quad_swap_vertical:
7188          dpp_ctrl = dpp_quad_perm(2, 3, 0, 1);
7189          break;
7190       case nir_intrinsic_quad_swap_diagonal:
7191          dpp_ctrl = dpp_quad_perm(3, 2, 1, 0);
7192          break;
7193       case nir_intrinsic_quad_swizzle_amd:
7194          dpp_ctrl = nir_intrinsic_swizzle_mask(instr);
7195          break;
7196       default:
7197          break;
7198       }
7199       if (ctx->program->chip_class < GFX8)
7200          dpp_ctrl |= (1 << 15);
7201
7202       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7203       if (instr->dest.ssa.bit_size == 1) {
7204          assert(src.regClass() == bld.lm);
7205          src = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand((uint32_t)-1), src);
7206          if (ctx->program->chip_class >= GFX8)
7207             src = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl);
7208          else
7209             src = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, dpp_ctrl);
7210          Temp tmp = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), src);
7211          emit_wqm(ctx, tmp, dst);
7212       } else if (instr->dest.ssa.bit_size == 32) {
7213          Temp tmp;
7214          if (ctx->program->chip_class >= GFX8)
7215             tmp = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl);
7216          else
7217             tmp = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, dpp_ctrl);
7218          emit_wqm(ctx, tmp, dst);
7219       } else if (instr->dest.ssa.bit_size == 64) {
7220          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
7221          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
7222          if (ctx->program->chip_class >= GFX8) {
7223             lo = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), lo, dpp_ctrl));
7224             hi = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), hi, dpp_ctrl));
7225          } else {
7226             lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, dpp_ctrl));
7227             hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, dpp_ctrl));
7228          }
7229          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
7230          emit_split_vector(ctx, dst, 2);
7231       } else {
7232          fprintf(stderr, "Unimplemented NIR instr bit size: ");
7233          nir_print_instr(&instr->instr, stderr);
7234          fprintf(stderr, "\n");
7235       }
7236       break;
7237    }
7238    case nir_intrinsic_masked_swizzle_amd: {
7239       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7240       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
7241          emit_uniform_subgroup(ctx, instr, src);
7242          break;
7243       }
7244       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7245       uint32_t mask = nir_intrinsic_swizzle_mask(instr);
7246       if (dst.regClass() == v1) {
7247          emit_wqm(ctx,
7248                   bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, mask, 0, false),
7249                   dst);
7250       } else if (dst.regClass() == v2) {
7251          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
7252          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
7253          lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, mask, 0, false));
7254          hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, mask, 0, false));
7255          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
7256          emit_split_vector(ctx, dst, 2);
7257       } else {
7258          fprintf(stderr, "Unimplemented NIR instr bit size: ");
7259          nir_print_instr(&instr->instr, stderr);
7260          fprintf(stderr, "\n");
7261       }
7262       break;
7263    }
7264    case nir_intrinsic_write_invocation_amd: {
7265       Temp src = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
7266       Temp val = bld.as_uniform(get_ssa_temp(ctx, instr->src[1].ssa));
7267       Temp lane = bld.as_uniform(get_ssa_temp(ctx, instr->src[2].ssa));
7268       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7269       if (dst.regClass() == v1) {
7270          /* src2 is ignored for writelane. RA assigns the same reg for dst */
7271          emit_wqm(ctx, bld.writelane(bld.def(v1), val, lane, src), dst);
7272       } else if (dst.regClass() == v2) {
7273          Temp src_lo = bld.tmp(v1), src_hi = bld.tmp(v1);
7274          Temp val_lo = bld.tmp(s1), val_hi = bld.tmp(s1);
7275          bld.pseudo(aco_opcode::p_split_vector, Definition(src_lo), Definition(src_hi), src);
7276          bld.pseudo(aco_opcode::p_split_vector, Definition(val_lo), Definition(val_hi), val);
7277          Temp lo = emit_wqm(ctx, bld.writelane(bld.def(v1), val_lo, lane, src_hi));
7278          Temp hi = emit_wqm(ctx, bld.writelane(bld.def(v1), val_hi, lane, src_hi));
7279          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
7280          emit_split_vector(ctx, dst, 2);
7281       } else {
7282          fprintf(stderr, "Unimplemented NIR instr bit size: ");
7283          nir_print_instr(&instr->instr, stderr);
7284          fprintf(stderr, "\n");
7285       }
7286       break;
7287    }
7288    case nir_intrinsic_mbcnt_amd: {
7289       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7290       RegClass rc = RegClass(src.type(), 1);
7291       Temp mask_lo = bld.tmp(rc), mask_hi = bld.tmp(rc);
7292       bld.pseudo(aco_opcode::p_split_vector, Definition(mask_lo), Definition(mask_hi), src);
7293       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7294       Temp wqm_tmp = emit_mbcnt(ctx, bld.def(v1), Operand(mask_lo), Operand(mask_hi));
7295       emit_wqm(ctx, wqm_tmp, dst);
7296       break;
7297    }
7298    case nir_intrinsic_load_helper_invocation: {
7299       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7300       bld.pseudo(aco_opcode::p_load_helper, Definition(dst));
7301       ctx->block->kind |= block_kind_needs_lowering;
7302       ctx->program->needs_exact = true;
7303       break;
7304    }
7305    case nir_intrinsic_is_helper_invocation: {
7306       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7307       bld.pseudo(aco_opcode::p_is_helper, Definition(dst));
7308       ctx->block->kind |= block_kind_needs_lowering;
7309       ctx->program->needs_exact = true;
7310       break;
7311    }
7312    case nir_intrinsic_demote:
7313       bld.pseudo(aco_opcode::p_demote_to_helper, Operand(-1u));
7314
7315       if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
7316          ctx->cf_info.exec_potentially_empty_discard = true;
7317       ctx->block->kind |= block_kind_uses_demote;
7318       ctx->program->needs_exact = true;
7319       break;
7320    case nir_intrinsic_demote_if: {
7321       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7322       assert(src.regClass() == bld.lm);
7323       Temp cond = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
7324       bld.pseudo(aco_opcode::p_demote_to_helper, cond);
7325
7326       if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
7327          ctx->cf_info.exec_potentially_empty_discard = true;
7328       ctx->block->kind |= block_kind_uses_demote;
7329       ctx->program->needs_exact = true;
7330       break;
7331    }
7332    case nir_intrinsic_first_invocation: {
7333       emit_wqm(ctx, bld.sop1(Builder::s_ff1_i32, bld.def(s1), Operand(exec, bld.lm)),
7334                get_ssa_temp(ctx, &instr->dest.ssa));
7335       break;
7336    }
7337    case nir_intrinsic_shader_clock:
7338       bld.smem(aco_opcode::s_memtime, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), false);
7339       emit_split_vector(ctx, get_ssa_temp(ctx, &instr->dest.ssa), 2);
7340       break;
7341    case nir_intrinsic_load_vertex_id_zero_base: {
7342       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7343       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.vertex_id));
7344       break;
7345    }
7346    case nir_intrinsic_load_first_vertex: {
7347       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7348       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.base_vertex));
7349       break;
7350    }
7351    case nir_intrinsic_load_base_instance: {
7352       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7353       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.start_instance));
7354       break;
7355    }
7356    case nir_intrinsic_load_instance_id: {
7357       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7358       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.instance_id));
7359       break;
7360    }
7361    case nir_intrinsic_load_draw_id: {
7362       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7363       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.draw_id));
7364       break;
7365    }
7366    case nir_intrinsic_load_invocation_id: {
7367       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7368
7369       if (ctx->shader->info.stage == MESA_SHADER_GEOMETRY) {
7370          if (ctx->options->chip_class >= GFX10)
7371             bld.vop2_e64(aco_opcode::v_and_b32, Definition(dst), Operand(127u), get_arg(ctx, ctx->args->ac.gs_invocation_id));
7372          else
7373             bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.gs_invocation_id));
7374       } else if (ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) {
7375          bld.vop3(aco_opcode::v_bfe_u32, Definition(dst),
7376                   get_arg(ctx, ctx->args->ac.tcs_rel_ids), Operand(8u), Operand(5u));
7377       } else {
7378          unreachable("Unsupported stage for load_invocation_id");
7379       }
7380
7381       break;
7382    }
7383    case nir_intrinsic_load_primitive_id: {
7384       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7385
7386       switch (ctx->shader->info.stage) {
7387       case MESA_SHADER_GEOMETRY:
7388          bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.gs_prim_id));
7389          break;
7390       case MESA_SHADER_TESS_CTRL:
7391          bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.tcs_patch_id));
7392          break;
7393       case MESA_SHADER_TESS_EVAL:
7394          bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.tes_patch_id));
7395          break;
7396       default:
7397          unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
7398       }
7399
7400       break;
7401    }
7402    case nir_intrinsic_load_patch_vertices_in: {
7403       assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL ||
7404              ctx->shader->info.stage == MESA_SHADER_TESS_EVAL);
7405
7406       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7407       bld.copy(Definition(dst), Operand(ctx->args->options->key.tcs.input_vertices));
7408       break;
7409    }
7410    case nir_intrinsic_emit_vertex_with_counter: {
7411       visit_emit_vertex_with_counter(ctx, instr);
7412       break;
7413    }
7414    case nir_intrinsic_end_primitive_with_counter: {
7415       unsigned stream = nir_intrinsic_stream_id(instr);
7416       bld.sopp(aco_opcode::s_sendmsg, bld.m0(ctx->gs_wave_id), -1, sendmsg_gs(true, false, stream));
7417       break;
7418    }
7419    case nir_intrinsic_set_vertex_count: {
7420       /* unused, the HW keeps track of this for us */
7421       break;
7422    }
7423    default:
7424       fprintf(stderr, "Unimplemented intrinsic instr: ");
7425       nir_print_instr(&instr->instr, stderr);
7426       fprintf(stderr, "\n");
7427       abort();
7428
7429       break;
7430    }
7431 }
7432
7433
7434 void tex_fetch_ptrs(isel_context *ctx, nir_tex_instr *instr,
7435                     Temp *res_ptr, Temp *samp_ptr, Temp *fmask_ptr,
7436                     enum glsl_base_type *stype)
7437 {
7438    nir_deref_instr *texture_deref_instr = NULL;
7439    nir_deref_instr *sampler_deref_instr = NULL;
7440    int plane = -1;
7441
7442    for (unsigned i = 0; i < instr->num_srcs; i++) {
7443       switch (instr->src[i].src_type) {
7444       case nir_tex_src_texture_deref:
7445          texture_deref_instr = nir_src_as_deref(instr->src[i].src);
7446          break;
7447       case nir_tex_src_sampler_deref:
7448          sampler_deref_instr = nir_src_as_deref(instr->src[i].src);
7449          break;
7450       case nir_tex_src_plane:
7451          plane = nir_src_as_int(instr->src[i].src);
7452          break;
7453       default:
7454          break;
7455       }
7456    }
7457
7458    *stype = glsl_get_sampler_result_type(texture_deref_instr->type);
7459
7460    if (!sampler_deref_instr)
7461       sampler_deref_instr = texture_deref_instr;
7462
7463    if (plane >= 0) {
7464       assert(instr->op != nir_texop_txf_ms &&
7465              instr->op != nir_texop_samples_identical);
7466       assert(instr->sampler_dim  != GLSL_SAMPLER_DIM_BUF);
7467       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, (aco_descriptor_type)(ACO_DESC_PLANE_0 + plane), instr, false, false);
7468    } else if (instr->sampler_dim  == GLSL_SAMPLER_DIM_BUF) {
7469       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_BUFFER, instr, false, false);
7470    } else if (instr->op == nir_texop_fragment_mask_fetch) {
7471       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_FMASK, instr, false, false);
7472    } else {
7473       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_IMAGE, instr, false, false);
7474    }
7475    if (samp_ptr) {
7476       *samp_ptr = get_sampler_desc(ctx, sampler_deref_instr, ACO_DESC_SAMPLER, instr, false, false);
7477
7478       if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT && ctx->options->chip_class < GFX8) {
7479          /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
7480          Builder bld(ctx->program, ctx->block);
7481
7482          /* to avoid unnecessary moves, we split and recombine sampler and image */
7483          Temp img[8] = {bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1),
7484                         bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1)};
7485          Temp samp[4] = {bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1)};
7486          bld.pseudo(aco_opcode::p_split_vector, Definition(img[0]), Definition(img[1]),
7487                     Definition(img[2]), Definition(img[3]), Definition(img[4]),
7488                     Definition(img[5]), Definition(img[6]), Definition(img[7]), *res_ptr);
7489          bld.pseudo(aco_opcode::p_split_vector, Definition(samp[0]), Definition(samp[1]),
7490                     Definition(samp[2]), Definition(samp[3]), *samp_ptr);
7491
7492          samp[0] = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), samp[0], img[7]);
7493          *res_ptr = bld.pseudo(aco_opcode::p_create_vector, bld.def(s8),
7494                                img[0], img[1], img[2], img[3],
7495                                img[4], img[5], img[6], img[7]);
7496          *samp_ptr = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
7497                                 samp[0], samp[1], samp[2], samp[3]);
7498       }
7499    }
7500    if (fmask_ptr && (instr->op == nir_texop_txf_ms ||
7501                      instr->op == nir_texop_samples_identical))
7502       *fmask_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_FMASK, instr, false, false);
7503 }
7504
7505 void build_cube_select(isel_context *ctx, Temp ma, Temp id, Temp deriv,
7506                        Temp *out_ma, Temp *out_sc, Temp *out_tc)
7507 {
7508    Builder bld(ctx->program, ctx->block);
7509
7510    Temp deriv_x = emit_extract_vector(ctx, deriv, 0, v1);
7511    Temp deriv_y = emit_extract_vector(ctx, deriv, 1, v1);
7512    Temp deriv_z = emit_extract_vector(ctx, deriv, 2, v1);
7513
7514    Operand neg_one(0xbf800000u);
7515    Operand one(0x3f800000u);
7516    Operand two(0x40000000u);
7517    Operand four(0x40800000u);
7518
7519    Temp is_ma_positive = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), ma);
7520    Temp sgn_ma = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), neg_one, one, is_ma_positive);
7521    Temp neg_sgn_ma = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), Operand(0u), sgn_ma);
7522
7523    Temp is_ma_z = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), four, id);
7524    Temp is_ma_y = bld.vopc(aco_opcode::v_cmp_le_f32, bld.def(bld.lm), two, id);
7525    is_ma_y = bld.sop2(Builder::s_andn2, bld.hint_vcc(bld.def(bld.lm)), is_ma_y, is_ma_z);
7526    Temp is_not_ma_x = bld.sop2(aco_opcode::s_or_b64, bld.hint_vcc(bld.def(bld.lm)), bld.def(s1, scc), is_ma_z, is_ma_y);
7527
7528    // select sc
7529    Temp tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_z, deriv_x, is_not_ma_x);
7530    Temp sgn = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1),
7531                        bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), neg_sgn_ma, sgn_ma, is_ma_z),
7532                        one, is_ma_y);
7533    *out_sc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tmp, sgn);
7534
7535    // select tc
7536    tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_y, deriv_z, is_ma_y);
7537    sgn = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), neg_one, sgn_ma, is_ma_y);
7538    *out_tc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tmp, sgn);
7539
7540    // select ma
7541    tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
7542                   bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_x, deriv_y, is_ma_y),
7543                   deriv_z, is_ma_z);
7544    tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffffu), tmp);
7545    *out_ma = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), two, tmp);
7546 }
7547
7548 void prepare_cube_coords(isel_context *ctx, std::vector<Temp>& coords, Temp* ddx, Temp* ddy, bool is_deriv, bool is_array)
7549 {
7550    Builder bld(ctx->program, ctx->block);
7551    Temp ma, tc, sc, id;
7552
7553    if (is_array) {
7554       coords[3] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coords[3]);
7555
7556       // see comment in ac_prepare_cube_coords()
7557       if (ctx->options->chip_class <= GFX8)
7558          coords[3] = bld.vop2(aco_opcode::v_max_f32, bld.def(v1), Operand(0u), coords[3]);
7559    }
7560
7561    ma = bld.vop3(aco_opcode::v_cubema_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7562
7563    aco_ptr<VOP3A_instruction> vop3a{create_instruction<VOP3A_instruction>(aco_opcode::v_rcp_f32, asVOP3(Format::VOP1), 1, 1)};
7564    vop3a->operands[0] = Operand(ma);
7565    vop3a->abs[0] = true;
7566    Temp invma = bld.tmp(v1);
7567    vop3a->definitions[0] = Definition(invma);
7568    ctx->block->instructions.emplace_back(std::move(vop3a));
7569
7570    sc = bld.vop3(aco_opcode::v_cubesc_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7571    if (!is_deriv)
7572       sc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), sc, invma, Operand(0x3fc00000u/*1.5*/));
7573
7574    tc = bld.vop3(aco_opcode::v_cubetc_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7575    if (!is_deriv)
7576       tc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), tc, invma, Operand(0x3fc00000u/*1.5*/));
7577
7578    id = bld.vop3(aco_opcode::v_cubeid_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7579
7580    if (is_deriv) {
7581       sc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), sc, invma);
7582       tc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tc, invma);
7583
7584       for (unsigned i = 0; i < 2; i++) {
7585          // see comment in ac_prepare_cube_coords()
7586          Temp deriv_ma;
7587          Temp deriv_sc, deriv_tc;
7588          build_cube_select(ctx, ma, id, i ? *ddy : *ddx,
7589                            &deriv_ma, &deriv_sc, &deriv_tc);
7590
7591          deriv_ma = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, invma);
7592
7593          Temp x = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1),
7594                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_sc, invma),
7595                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, sc));
7596          Temp y = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1),
7597                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_tc, invma),
7598                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, tc));
7599          *(i ? ddy : ddx) = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), x, y);
7600       }
7601
7602       sc = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), Operand(0x3fc00000u/*1.5*/), sc);
7603       tc = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), Operand(0x3fc00000u/*1.5*/), tc);
7604    }
7605
7606    if (is_array)
7607       id = bld.vop2(aco_opcode::v_madmk_f32, bld.def(v1), coords[3], id, Operand(0x41000000u/*8.0*/));
7608    coords.resize(3);
7609    coords[0] = sc;
7610    coords[1] = tc;
7611    coords[2] = id;
7612 }
7613
7614 void get_const_vec(nir_ssa_def *vec, nir_const_value *cv[4])
7615 {
7616    if (vec->parent_instr->type != nir_instr_type_alu)
7617       return;
7618    nir_alu_instr *vec_instr = nir_instr_as_alu(vec->parent_instr);
7619    if (vec_instr->op != nir_op_vec(vec->num_components))
7620       return;
7621
7622    for (unsigned i = 0; i < vec->num_components; i++) {
7623       cv[i] = vec_instr->src[i].swizzle[0] == 0 ?
7624               nir_src_as_const_value(vec_instr->src[i].src) : NULL;
7625    }
7626 }
7627
7628 void visit_tex(isel_context *ctx, nir_tex_instr *instr)
7629 {
7630    Builder bld(ctx->program, ctx->block);
7631    bool has_bias = false, has_lod = false, level_zero = false, has_compare = false,
7632         has_offset = false, has_ddx = false, has_ddy = false, has_derivs = false, has_sample_index = false;
7633    Temp resource, sampler, fmask_ptr, bias = Temp(), compare = Temp(), sample_index = Temp(),
7634         lod = Temp(), offset = Temp(), ddx = Temp(), ddy = Temp();
7635    std::vector<Temp> coords;
7636    std::vector<Temp> derivs;
7637    nir_const_value *sample_index_cv = NULL;
7638    nir_const_value *const_offset[4] = {NULL, NULL, NULL, NULL};
7639    enum glsl_base_type stype;
7640    tex_fetch_ptrs(ctx, instr, &resource, &sampler, &fmask_ptr, &stype);
7641
7642    bool tg4_integer_workarounds = ctx->options->chip_class <= GFX8 && instr->op == nir_texop_tg4 &&
7643                                   (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT);
7644    bool tg4_integer_cube_workaround = tg4_integer_workarounds &&
7645                                       instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
7646
7647    for (unsigned i = 0; i < instr->num_srcs; i++) {
7648       switch (instr->src[i].src_type) {
7649       case nir_tex_src_coord: {
7650          Temp coord = get_ssa_temp(ctx, instr->src[i].src.ssa);
7651          for (unsigned i = 0; i < coord.size(); i++)
7652             coords.emplace_back(emit_extract_vector(ctx, coord, i, v1));
7653          break;
7654       }
7655       case nir_tex_src_bias:
7656          if (instr->op == nir_texop_txb) {
7657             bias = get_ssa_temp(ctx, instr->src[i].src.ssa);
7658             has_bias = true;
7659          }
7660          break;
7661       case nir_tex_src_lod: {
7662          nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
7663
7664          if (val && val->f32 <= 0.0) {
7665             level_zero = true;
7666          } else {
7667             lod = get_ssa_temp(ctx, instr->src[i].src.ssa);
7668             has_lod = true;
7669          }
7670          break;
7671       }
7672       case nir_tex_src_comparator:
7673          if (instr->is_shadow) {
7674             compare = get_ssa_temp(ctx, instr->src[i].src.ssa);
7675             has_compare = true;
7676          }
7677          break;
7678       case nir_tex_src_offset:
7679          offset = get_ssa_temp(ctx, instr->src[i].src.ssa);
7680          get_const_vec(instr->src[i].src.ssa, const_offset);
7681          has_offset = true;
7682          break;
7683       case nir_tex_src_ddx:
7684          ddx = get_ssa_temp(ctx, instr->src[i].src.ssa);
7685          has_ddx = true;
7686          break;
7687       case nir_tex_src_ddy:
7688          ddy = get_ssa_temp(ctx, instr->src[i].src.ssa);
7689          has_ddy = true;
7690          break;
7691       case nir_tex_src_ms_index:
7692          sample_index = get_ssa_temp(ctx, instr->src[i].src.ssa);
7693          sample_index_cv = nir_src_as_const_value(instr->src[i].src);
7694          has_sample_index = true;
7695          break;
7696       case nir_tex_src_texture_offset:
7697       case nir_tex_src_sampler_offset:
7698       default:
7699          break;
7700       }
7701    }
7702
7703    if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
7704       return get_buffer_size(ctx, resource, get_ssa_temp(ctx, &instr->dest.ssa), true);
7705
7706    if (instr->op == nir_texop_texture_samples) {
7707       Temp dword3 = emit_extract_vector(ctx, resource, 3, s1);
7708
7709       Temp samples_log2 = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), dword3, Operand(16u | 4u<<16));
7710       Temp samples = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), Operand(1u), samples_log2);
7711       Temp type = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), dword3, Operand(28u | 4u<<16 /* offset=28, width=4 */));
7712       Temp is_msaa = bld.sopc(aco_opcode::s_cmp_ge_u32, bld.def(s1, scc), type, Operand(14u));
7713
7714       bld.sop2(aco_opcode::s_cselect_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
7715                samples, Operand(1u), bld.scc(is_msaa));
7716       return;
7717    }
7718
7719    if (has_offset && instr->op != nir_texop_txf && instr->op != nir_texop_txf_ms) {
7720       aco_ptr<Instruction> tmp_instr;
7721       Temp acc, pack = Temp();
7722
7723       uint32_t pack_const = 0;
7724       for (unsigned i = 0; i < offset.size(); i++) {
7725          if (!const_offset[i])
7726             continue;
7727          pack_const |= (const_offset[i]->u32 & 0x3Fu) << (8u * i);
7728       }
7729
7730       if (offset.type() == RegType::sgpr) {
7731          for (unsigned i = 0; i < offset.size(); i++) {
7732             if (const_offset[i])
7733                continue;
7734
7735             acc = emit_extract_vector(ctx, offset, i, s1);
7736             acc = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), acc, Operand(0x3Fu));
7737
7738             if (i) {
7739                acc = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), acc, Operand(8u * i));
7740             }
7741
7742             if (pack == Temp()) {
7743                pack = acc;
7744             } else {
7745                pack = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), pack, acc);
7746             }
7747          }
7748
7749          if (pack_const && pack != Temp())
7750             pack = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(pack_const), pack);
7751       } else {
7752          for (unsigned i = 0; i < offset.size(); i++) {
7753             if (const_offset[i])
7754                continue;
7755
7756             acc = emit_extract_vector(ctx, offset, i, v1);
7757             acc = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x3Fu), acc);
7758
7759             if (i) {
7760                acc = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(8u * i), acc);
7761             }
7762
7763             if (pack == Temp()) {
7764                pack = acc;
7765             } else {
7766                pack = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), pack, acc);
7767             }
7768          }
7769
7770          if (pack_const && pack != Temp())
7771             pack = bld.sop2(aco_opcode::v_or_b32, bld.def(v1), Operand(pack_const), pack);
7772       }
7773       if (pack_const && pack == Temp())
7774          offset = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(pack_const));
7775       else if (pack == Temp())
7776          has_offset = false;
7777       else
7778          offset = pack;
7779    }
7780
7781    if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && instr->coord_components)
7782       prepare_cube_coords(ctx, coords, &ddx, &ddy, instr->op == nir_texop_txd, instr->is_array && instr->op != nir_texop_lod);
7783
7784    /* pack derivatives */
7785    if (has_ddx || has_ddy) {
7786       if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && ctx->options->chip_class == GFX9) {
7787          assert(has_ddx && has_ddy && ddx.size() == 1 && ddy.size() == 1);
7788          Temp zero = bld.copy(bld.def(v1), Operand(0u));
7789          derivs = {ddy, zero, ddy, zero};
7790       } else {
7791          for (unsigned i = 0; has_ddx && i < ddx.size(); i++)
7792             derivs.emplace_back(emit_extract_vector(ctx, ddx, i, v1));
7793          for (unsigned i = 0; has_ddy && i < ddy.size(); i++)
7794             derivs.emplace_back(emit_extract_vector(ctx, ddy, i, v1));
7795       }
7796       has_derivs = true;
7797    }
7798
7799    if (instr->coord_components > 1 &&
7800        instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
7801        instr->is_array &&
7802        instr->op != nir_texop_txf)
7803       coords[1] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coords[1]);
7804
7805    if (instr->coord_components > 2 &&
7806       (instr->sampler_dim == GLSL_SAMPLER_DIM_2D ||
7807        instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
7808        instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS ||
7809        instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
7810        instr->is_array &&
7811        instr->op != nir_texop_txf &&
7812        instr->op != nir_texop_txf_ms &&
7813        instr->op != nir_texop_fragment_fetch &&
7814        instr->op != nir_texop_fragment_mask_fetch)
7815       coords[2] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coords[2]);
7816
7817    if (ctx->options->chip_class == GFX9 &&
7818        instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
7819        instr->op != nir_texop_lod && instr->coord_components) {
7820       assert(coords.size() > 0 && coords.size() < 3);
7821
7822       coords.insert(std::next(coords.begin()), bld.copy(bld.def(v1), instr->op == nir_texop_txf ?
7823                                                                      Operand((uint32_t) 0) :
7824                                                                      Operand((uint32_t) 0x3f000000)));
7825    }
7826
7827    bool da = should_declare_array(ctx, instr->sampler_dim, instr->is_array);
7828
7829    if (instr->op == nir_texop_samples_identical)
7830       resource = fmask_ptr;
7831
7832    else if ((instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
7833              instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
7834             instr->op != nir_texop_txs &&
7835             instr->op != nir_texop_fragment_fetch &&
7836             instr->op != nir_texop_fragment_mask_fetch) {
7837       assert(has_sample_index);
7838       Operand op(sample_index);
7839       if (sample_index_cv)
7840          op = Operand(sample_index_cv->u32);
7841       sample_index = adjust_sample_index_using_fmask(ctx, da, coords, op, fmask_ptr);
7842    }
7843
7844    if (has_offset && (instr->op == nir_texop_txf || instr->op == nir_texop_txf_ms)) {
7845       for (unsigned i = 0; i < std::min(offset.size(), instr->coord_components); i++) {
7846          Temp off = emit_extract_vector(ctx, offset, i, v1);
7847          coords[i] = bld.vadd32(bld.def(v1), coords[i], off);
7848       }
7849       has_offset = false;
7850    }
7851
7852    /* Build tex instruction */
7853    unsigned dmask = nir_ssa_def_components_read(&instr->dest.ssa);
7854    unsigned dim = ctx->options->chip_class >= GFX10 && instr->sampler_dim != GLSL_SAMPLER_DIM_BUF
7855                   ? ac_get_sampler_dim(ctx->options->chip_class, instr->sampler_dim, instr->is_array)
7856                   : 0;
7857    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7858    Temp tmp_dst = dst;
7859
7860    /* gather4 selects the component by dmask and always returns vec4 */
7861    if (instr->op == nir_texop_tg4) {
7862       assert(instr->dest.ssa.num_components == 4);
7863       if (instr->is_shadow)
7864          dmask = 1;
7865       else
7866          dmask = 1 << instr->component;
7867       if (tg4_integer_cube_workaround || dst.type() == RegType::sgpr)
7868          tmp_dst = bld.tmp(v4);
7869    } else if (instr->op == nir_texop_samples_identical) {
7870       tmp_dst = bld.tmp(v1);
7871    } else if (util_bitcount(dmask) != instr->dest.ssa.num_components || dst.type() == RegType::sgpr) {
7872       tmp_dst = bld.tmp(RegClass(RegType::vgpr, util_bitcount(dmask)));
7873    }
7874
7875    aco_ptr<MIMG_instruction> tex;
7876    if (instr->op == nir_texop_txs || instr->op == nir_texop_query_levels) {
7877       if (!has_lod)
7878          lod = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
7879
7880       bool div_by_6 = instr->op == nir_texop_txs &&
7881                       instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
7882                       instr->is_array &&
7883                       (dmask & (1 << 2));
7884       if (tmp_dst.id() == dst.id() && div_by_6)
7885          tmp_dst = bld.tmp(tmp_dst.regClass());
7886
7887       tex.reset(create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 3, 1));
7888       tex->operands[0] = Operand(resource);
7889       tex->operands[1] = Operand(s4); /* no sampler */
7890       tex->operands[2] = Operand(as_vgpr(ctx,lod));
7891       if (ctx->options->chip_class == GFX9 &&
7892           instr->op == nir_texop_txs &&
7893           instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
7894           instr->is_array) {
7895          tex->dmask = (dmask & 0x1) | ((dmask & 0x2) << 1);
7896       } else if (instr->op == nir_texop_query_levels) {
7897          tex->dmask = 1 << 3;
7898       } else {
7899          tex->dmask = dmask;
7900       }
7901       tex->da = da;
7902       tex->definitions[0] = Definition(tmp_dst);
7903       tex->dim = dim;
7904       tex->can_reorder = true;
7905       ctx->block->instructions.emplace_back(std::move(tex));
7906
7907       if (div_by_6) {
7908          /* divide 3rd value by 6 by multiplying with magic number */
7909          emit_split_vector(ctx, tmp_dst, tmp_dst.size());
7910          Temp c = bld.copy(bld.def(s1), Operand((uint32_t) 0x2AAAAAAB));
7911          Temp by_6 = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), emit_extract_vector(ctx, tmp_dst, 2, v1), c);
7912          assert(instr->dest.ssa.num_components == 3);
7913          Temp tmp = dst.type() == RegType::vgpr ? dst : bld.tmp(v3);
7914          tmp_dst = bld.pseudo(aco_opcode::p_create_vector, Definition(tmp),
7915                               emit_extract_vector(ctx, tmp_dst, 0, v1),
7916                               emit_extract_vector(ctx, tmp_dst, 1, v1),
7917                               by_6);
7918
7919       }
7920
7921       expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, dmask);
7922       return;
7923    }
7924
7925    Temp tg4_compare_cube_wa64 = Temp();
7926
7927    if (tg4_integer_workarounds) {
7928       tex.reset(create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 3, 1));
7929       tex->operands[0] = Operand(resource);
7930       tex->operands[1] = Operand(s4); /* no sampler */
7931       tex->operands[2] = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
7932       tex->dim = dim;
7933       tex->dmask = 0x3;
7934       tex->da = da;
7935       Temp size = bld.tmp(v2);
7936       tex->definitions[0] = Definition(size);
7937       tex->can_reorder = true;
7938       ctx->block->instructions.emplace_back(std::move(tex));
7939       emit_split_vector(ctx, size, size.size());
7940
7941       Temp half_texel[2];
7942       for (unsigned i = 0; i < 2; i++) {
7943          half_texel[i] = emit_extract_vector(ctx, size, i, v1);
7944          half_texel[i] = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), half_texel[i]);
7945          half_texel[i] = bld.vop1(aco_opcode::v_rcp_iflag_f32, bld.def(v1), half_texel[i]);
7946          half_texel[i] = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0xbf000000/*-0.5*/), half_texel[i]);
7947       }
7948
7949       Temp new_coords[2] = {
7950          bld.vop2(aco_opcode::v_add_f32, bld.def(v1), coords[0], half_texel[0]),
7951          bld.vop2(aco_opcode::v_add_f32, bld.def(v1), coords[1], half_texel[1])
7952       };
7953
7954       if (tg4_integer_cube_workaround) {
7955          // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
7956          Temp desc[resource.size()];
7957          aco_ptr<Instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector,
7958                                                                            Format::PSEUDO, 1, resource.size())};
7959          split->operands[0] = Operand(resource);
7960          for (unsigned i = 0; i < resource.size(); i++) {
7961             desc[i] = bld.tmp(s1);
7962             split->definitions[i] = Definition(desc[i]);
7963          }
7964          ctx->block->instructions.emplace_back(std::move(split));
7965
7966          Temp dfmt = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), desc[1], Operand(20u | (6u << 16)));
7967          Temp compare_cube_wa = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), dfmt,
7968                                          Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8));
7969
7970          Temp nfmt;
7971          if (stype == GLSL_TYPE_UINT) {
7972             nfmt = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1),
7973                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED),
7974                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT),
7975                             bld.scc(compare_cube_wa));
7976          } else {
7977             nfmt = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1),
7978                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED),
7979                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT),
7980                             bld.scc(compare_cube_wa));
7981          }
7982          tg4_compare_cube_wa64 = bld.tmp(bld.lm);
7983          bool_to_vector_condition(ctx, compare_cube_wa, tg4_compare_cube_wa64);
7984
7985          nfmt = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), nfmt, Operand(26u));
7986
7987          desc[1] = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), desc[1],
7988                             Operand((uint32_t)C_008F14_NUM_FORMAT));
7989          desc[1] = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), desc[1], nfmt);
7990
7991          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector,
7992                                                                          Format::PSEUDO, resource.size(), 1)};
7993          for (unsigned i = 0; i < resource.size(); i++)
7994             vec->operands[i] = Operand(desc[i]);
7995          resource = bld.tmp(resource.regClass());
7996          vec->definitions[0] = Definition(resource);
7997          ctx->block->instructions.emplace_back(std::move(vec));
7998
7999          new_coords[0] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
8000                                   new_coords[0], coords[0], tg4_compare_cube_wa64);
8001          new_coords[1] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
8002                                   new_coords[1], coords[1], tg4_compare_cube_wa64);
8003       }
8004       coords[0] = new_coords[0];
8005       coords[1] = new_coords[1];
8006    }
8007
8008    if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
8009       //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8010
8011       assert(coords.size() == 1);
8012       unsigned last_bit = util_last_bit(nir_ssa_def_components_read(&instr->dest.ssa));
8013       aco_opcode op;
8014       switch (last_bit) {
8015       case 1:
8016          op = aco_opcode::buffer_load_format_x; break;
8017       case 2:
8018          op = aco_opcode::buffer_load_format_xy; break;
8019       case 3:
8020          op = aco_opcode::buffer_load_format_xyz; break;
8021       case 4:
8022          op = aco_opcode::buffer_load_format_xyzw; break;
8023       default:
8024          unreachable("Tex instruction loads more than 4 components.");
8025       }
8026
8027       /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8028       if (last_bit == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
8029          tmp_dst = dst;
8030       else
8031          tmp_dst = bld.tmp(RegType::vgpr, last_bit);
8032
8033       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
8034       mubuf->operands[0] = Operand(resource);
8035       mubuf->operands[1] = Operand(coords[0]);
8036       mubuf->operands[2] = Operand((uint32_t) 0);
8037       mubuf->definitions[0] = Definition(tmp_dst);
8038       mubuf->idxen = true;
8039       mubuf->can_reorder = true;
8040       ctx->block->instructions.emplace_back(std::move(mubuf));
8041
8042       expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, (1 << last_bit) - 1);
8043       return;
8044    }
8045
8046    /* gather MIMG address components */
8047    std::vector<Temp> args;
8048    if (has_offset)
8049       args.emplace_back(offset);
8050    if (has_bias)
8051       args.emplace_back(bias);
8052    if (has_compare)
8053       args.emplace_back(compare);
8054    if (has_derivs)
8055       args.insert(args.end(), derivs.begin(), derivs.end());
8056
8057    args.insert(args.end(), coords.begin(), coords.end());
8058    if (has_sample_index)
8059       args.emplace_back(sample_index);
8060    if (has_lod)
8061       args.emplace_back(lod);
8062
8063    Temp arg = bld.tmp(RegClass(RegType::vgpr, args.size()));
8064    aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, args.size(), 1)};
8065    vec->definitions[0] = Definition(arg);
8066    for (unsigned i = 0; i < args.size(); i++)
8067       vec->operands[i] = Operand(args[i]);
8068    ctx->block->instructions.emplace_back(std::move(vec));
8069
8070
8071    if (instr->op == nir_texop_txf ||
8072        instr->op == nir_texop_txf_ms ||
8073        instr->op == nir_texop_samples_identical ||
8074        instr->op == nir_texop_fragment_fetch ||
8075        instr->op == nir_texop_fragment_mask_fetch) {
8076       aco_opcode op = level_zero || instr->sampler_dim == GLSL_SAMPLER_DIM_MS || instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS ? aco_opcode::image_load : aco_opcode::image_load_mip;
8077       tex.reset(create_instruction<MIMG_instruction>(op, Format::MIMG, 3, 1));
8078       tex->operands[0] = Operand(resource);
8079       tex->operands[1] = Operand(s4); /* no sampler */
8080       tex->operands[2] = Operand(arg);
8081       tex->dim = dim;
8082       tex->dmask = dmask;
8083       tex->unrm = true;
8084       tex->da = da;
8085       tex->definitions[0] = Definition(tmp_dst);
8086       tex->can_reorder = true;
8087       ctx->block->instructions.emplace_back(std::move(tex));
8088
8089       if (instr->op == nir_texop_samples_identical) {
8090          assert(dmask == 1 && dst.regClass() == v1);
8091          assert(dst.id() != tmp_dst.id());
8092
8093          Temp tmp = bld.tmp(bld.lm);
8094          bld.vopc(aco_opcode::v_cmp_eq_u32, Definition(tmp), Operand(0u), tmp_dst).def(0).setHint(vcc);
8095          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand((uint32_t)-1), tmp);
8096
8097       } else {
8098          expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, dmask);
8099       }
8100       return;
8101    }
8102
8103    // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8104    aco_opcode opcode = aco_opcode::image_sample;
8105    if (has_offset) { /* image_sample_*_o */
8106       if (has_compare) {
8107          opcode = aco_opcode::image_sample_c_o;
8108          if (has_derivs)
8109             opcode = aco_opcode::image_sample_c_d_o;
8110          if (has_bias)
8111             opcode = aco_opcode::image_sample_c_b_o;
8112          if (level_zero)
8113             opcode = aco_opcode::image_sample_c_lz_o;
8114          if (has_lod)
8115             opcode = aco_opcode::image_sample_c_l_o;
8116       } else {
8117          opcode = aco_opcode::image_sample_o;
8118          if (has_derivs)
8119             opcode = aco_opcode::image_sample_d_o;
8120          if (has_bias)
8121             opcode = aco_opcode::image_sample_b_o;
8122          if (level_zero)
8123             opcode = aco_opcode::image_sample_lz_o;
8124          if (has_lod)
8125             opcode = aco_opcode::image_sample_l_o;
8126       }
8127    } else { /* no offset */
8128       if (has_compare) {
8129          opcode = aco_opcode::image_sample_c;
8130          if (has_derivs)
8131             opcode = aco_opcode::image_sample_c_d;
8132          if (has_bias)
8133             opcode = aco_opcode::image_sample_c_b;
8134          if (level_zero)
8135             opcode = aco_opcode::image_sample_c_lz;
8136          if (has_lod)
8137             opcode = aco_opcode::image_sample_c_l;
8138       } else {
8139          opcode = aco_opcode::image_sample;
8140          if (has_derivs)
8141             opcode = aco_opcode::image_sample_d;
8142          if (has_bias)
8143             opcode = aco_opcode::image_sample_b;
8144          if (level_zero)
8145             opcode = aco_opcode::image_sample_lz;
8146          if (has_lod)
8147             opcode = aco_opcode::image_sample_l;
8148       }
8149    }
8150
8151    if (instr->op == nir_texop_tg4) {
8152       if (has_offset) {
8153          opcode = aco_opcode::image_gather4_lz_o;
8154          if (has_compare)
8155             opcode = aco_opcode::image_gather4_c_lz_o;
8156       } else {
8157          opcode = aco_opcode::image_gather4_lz;
8158          if (has_compare)
8159             opcode = aco_opcode::image_gather4_c_lz;
8160       }
8161    } else if (instr->op == nir_texop_lod) {
8162       opcode = aco_opcode::image_get_lod;
8163    }
8164
8165    /* we don't need the bias, sample index, compare value or offset to be
8166     * computed in WQM but if the p_create_vector copies the coordinates, then it
8167     * needs to be in WQM */
8168    if (ctx->stage == fragment_fs &&
8169        !has_derivs && !has_lod && !level_zero &&
8170        instr->sampler_dim != GLSL_SAMPLER_DIM_MS &&
8171        instr->sampler_dim != GLSL_SAMPLER_DIM_SUBPASS_MS)
8172       arg = emit_wqm(ctx, arg, bld.tmp(arg.regClass()), true);
8173
8174    tex.reset(create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 1));
8175    tex->operands[0] = Operand(resource);
8176    tex->operands[1] = Operand(sampler);
8177    tex->operands[2] = Operand(arg);
8178    tex->dim = dim;
8179    tex->dmask = dmask;
8180    tex->da = da;
8181    tex->definitions[0] = Definition(tmp_dst);
8182    tex->can_reorder = true;
8183    ctx->block->instructions.emplace_back(std::move(tex));
8184
8185    if (tg4_integer_cube_workaround) {
8186       assert(tmp_dst.id() != dst.id());
8187       assert(tmp_dst.size() == dst.size() && dst.size() == 4);
8188
8189       emit_split_vector(ctx, tmp_dst, tmp_dst.size());
8190       Temp val[4];
8191       for (unsigned i = 0; i < dst.size(); i++) {
8192          val[i] = emit_extract_vector(ctx, tmp_dst, i, v1);
8193          Temp cvt_val;
8194          if (stype == GLSL_TYPE_UINT)
8195             cvt_val = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), val[i]);
8196          else
8197             cvt_val = bld.vop1(aco_opcode::v_cvt_i32_f32, bld.def(v1), val[i]);
8198          val[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), val[i], cvt_val, tg4_compare_cube_wa64);
8199       }
8200       Temp tmp = dst.regClass() == v4 ? dst : bld.tmp(v4);
8201       tmp_dst = bld.pseudo(aco_opcode::p_create_vector, Definition(tmp),
8202                            val[0], val[1], val[2], val[3]);
8203    }
8204    unsigned mask = instr->op == nir_texop_tg4 ? 0xF : dmask;
8205    expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, mask);
8206
8207 }
8208
8209
8210 Operand get_phi_operand(isel_context *ctx, nir_ssa_def *ssa)
8211 {
8212    Temp tmp = get_ssa_temp(ctx, ssa);
8213    if (ssa->parent_instr->type == nir_instr_type_ssa_undef)
8214       return Operand(tmp.regClass());
8215    else
8216       return Operand(tmp);
8217 }
8218
8219 void visit_phi(isel_context *ctx, nir_phi_instr *instr)
8220 {
8221    aco_ptr<Pseudo_instruction> phi;
8222    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
8223    assert(instr->dest.ssa.bit_size != 1 || dst.regClass() == ctx->program->lane_mask);
8224
8225    bool logical = !dst.is_linear() || ctx->divergent_vals[instr->dest.ssa.index];
8226    logical |= ctx->block->kind & block_kind_merge;
8227    aco_opcode opcode = logical ? aco_opcode::p_phi : aco_opcode::p_linear_phi;
8228
8229    /* we want a sorted list of sources, since the predecessor list is also sorted */
8230    std::map<unsigned, nir_ssa_def*> phi_src;
8231    nir_foreach_phi_src(src, instr)
8232       phi_src[src->pred->index] = src->src.ssa;
8233
8234    std::vector<unsigned>& preds = logical ? ctx->block->logical_preds : ctx->block->linear_preds;
8235    unsigned num_operands = 0;
8236    Operand operands[std::max(exec_list_length(&instr->srcs), (unsigned)preds.size()) + 1];
8237    unsigned num_defined = 0;
8238    unsigned cur_pred_idx = 0;
8239    for (std::pair<unsigned, nir_ssa_def *> src : phi_src) {
8240       if (cur_pred_idx < preds.size()) {
8241          /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8242          unsigned block = ctx->cf_info.nir_to_aco[src.first];
8243          unsigned skipped = 0;
8244          while (cur_pred_idx + skipped < preds.size() && preds[cur_pred_idx + skipped] != block)
8245             skipped++;
8246          if (cur_pred_idx + skipped < preds.size()) {
8247             for (unsigned i = 0; i < skipped; i++)
8248                operands[num_operands++] = Operand(dst.regClass());
8249             cur_pred_idx += skipped;
8250          } else {
8251             continue;
8252          }
8253       }
8254       /* Handle missing predecessors at the end. This shouldn't happen with loop
8255        * headers and we can't ignore these sources for loop header phis. */
8256       if (!(ctx->block->kind & block_kind_loop_header) && cur_pred_idx >= preds.size())
8257          continue;
8258       cur_pred_idx++;
8259       Operand op = get_phi_operand(ctx, src.second);
8260       operands[num_operands++] = op;
8261       num_defined += !op.isUndefined();
8262    }
8263    /* handle block_kind_continue_or_break at loop exit blocks */
8264    while (cur_pred_idx++ < preds.size())
8265       operands[num_operands++] = Operand(dst.regClass());
8266
8267    /* If the loop ends with a break, still add a linear continue edge in case
8268     * that break is divergent or continue_or_break is used. We'll either remove
8269     * this operand later in visit_loop() if it's not necessary or replace the
8270     * undef with something correct. */
8271    if (!logical && ctx->block->kind & block_kind_loop_header) {
8272       nir_loop *loop = nir_cf_node_as_loop(instr->instr.block->cf_node.parent);
8273       nir_block *last = nir_loop_last_block(loop);
8274       if (last->successors[0] != instr->instr.block)
8275          operands[num_operands++] = Operand(RegClass());
8276    }
8277
8278    if (num_defined == 0) {
8279       Builder bld(ctx->program, ctx->block);
8280       if (dst.regClass() == s1) {
8281          bld.sop1(aco_opcode::s_mov_b32, Definition(dst), Operand(0u));
8282       } else if (dst.regClass() == v1) {
8283          bld.vop1(aco_opcode::v_mov_b32, Definition(dst), Operand(0u));
8284       } else {
8285          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
8286          for (unsigned i = 0; i < dst.size(); i++)
8287             vec->operands[i] = Operand(0u);
8288          vec->definitions[0] = Definition(dst);
8289          ctx->block->instructions.emplace_back(std::move(vec));
8290       }
8291       return;
8292    }
8293
8294    /* we can use a linear phi in some cases if one src is undef */
8295    if (dst.is_linear() && ctx->block->kind & block_kind_merge && num_defined == 1) {
8296       phi.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_linear_phi, Format::PSEUDO, num_operands, 1));
8297
8298       Block *linear_else = &ctx->program->blocks[ctx->block->linear_preds[1]];
8299       Block *invert = &ctx->program->blocks[linear_else->linear_preds[0]];
8300       assert(invert->kind & block_kind_invert);
8301
8302       unsigned then_block = invert->linear_preds[0];
8303
8304       Block* insert_block = NULL;
8305       for (unsigned i = 0; i < num_operands; i++) {
8306          Operand op = operands[i];
8307          if (op.isUndefined())
8308             continue;
8309          insert_block = ctx->block->logical_preds[i] == then_block ? invert : ctx->block;
8310          phi->operands[0] = op;
8311          break;
8312       }
8313       assert(insert_block); /* should be handled by the "num_defined == 0" case above */
8314       phi->operands[1] = Operand(dst.regClass());
8315       phi->definitions[0] = Definition(dst);
8316       insert_block->instructions.emplace(insert_block->instructions.begin(), std::move(phi));
8317       return;
8318    }
8319
8320    /* try to scalarize vector phis */
8321    if (instr->dest.ssa.bit_size != 1 && dst.size() > 1) {
8322       // TODO: scalarize linear phis on divergent ifs
8323       bool can_scalarize = (opcode == aco_opcode::p_phi || !(ctx->block->kind & block_kind_merge));
8324       std::array<Temp, NIR_MAX_VEC_COMPONENTS> new_vec;
8325       for (unsigned i = 0; can_scalarize && (i < num_operands); i++) {
8326          Operand src = operands[i];
8327          if (src.isTemp() && ctx->allocated_vec.find(src.tempId()) == ctx->allocated_vec.end())
8328             can_scalarize = false;
8329       }
8330       if (can_scalarize) {
8331          unsigned num_components = instr->dest.ssa.num_components;
8332          assert(dst.size() % num_components == 0);
8333          RegClass rc = RegClass(dst.type(), dst.size() / num_components);
8334
8335          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1)};
8336          for (unsigned k = 0; k < num_components; k++) {
8337             phi.reset(create_instruction<Pseudo_instruction>(opcode, Format::PSEUDO, num_operands, 1));
8338             for (unsigned i = 0; i < num_operands; i++) {
8339                Operand src = operands[i];
8340                phi->operands[i] = src.isTemp() ? Operand(ctx->allocated_vec[src.tempId()][k]) : Operand(rc);
8341             }
8342             Temp phi_dst = {ctx->program->allocateId(), rc};
8343             phi->definitions[0] = Definition(phi_dst);
8344             ctx->block->instructions.emplace(ctx->block->instructions.begin(), std::move(phi));
8345             new_vec[k] = phi_dst;
8346             vec->operands[k] = Operand(phi_dst);
8347          }
8348          vec->definitions[0] = Definition(dst);
8349          ctx->block->instructions.emplace_back(std::move(vec));
8350          ctx->allocated_vec.emplace(dst.id(), new_vec);
8351          return;
8352       }
8353    }
8354
8355    phi.reset(create_instruction<Pseudo_instruction>(opcode, Format::PSEUDO, num_operands, 1));
8356    for (unsigned i = 0; i < num_operands; i++)
8357       phi->operands[i] = operands[i];
8358    phi->definitions[0] = Definition(dst);
8359    ctx->block->instructions.emplace(ctx->block->instructions.begin(), std::move(phi));
8360 }
8361
8362
8363 void visit_undef(isel_context *ctx, nir_ssa_undef_instr *instr)
8364 {
8365    Temp dst = get_ssa_temp(ctx, &instr->def);
8366
8367    assert(dst.type() == RegType::sgpr);
8368
8369    if (dst.size() == 1) {
8370       Builder(ctx->program, ctx->block).copy(Definition(dst), Operand(0u));
8371    } else {
8372       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
8373       for (unsigned i = 0; i < dst.size(); i++)
8374          vec->operands[i] = Operand(0u);
8375       vec->definitions[0] = Definition(dst);
8376       ctx->block->instructions.emplace_back(std::move(vec));
8377    }
8378 }
8379
8380 void visit_jump(isel_context *ctx, nir_jump_instr *instr)
8381 {
8382    Builder bld(ctx->program, ctx->block);
8383    Block *logical_target;
8384    append_logical_end(ctx->block);
8385    unsigned idx = ctx->block->index;
8386
8387    switch (instr->type) {
8388    case nir_jump_break:
8389       logical_target = ctx->cf_info.parent_loop.exit;
8390       add_logical_edge(idx, logical_target);
8391       ctx->block->kind |= block_kind_break;
8392
8393       if (!ctx->cf_info.parent_if.is_divergent &&
8394           !ctx->cf_info.parent_loop.has_divergent_continue) {
8395          /* uniform break - directly jump out of the loop */
8396          ctx->block->kind |= block_kind_uniform;
8397          ctx->cf_info.has_branch = true;
8398          bld.branch(aco_opcode::p_branch);
8399          add_linear_edge(idx, logical_target);
8400          return;
8401       }
8402       ctx->cf_info.parent_loop.has_divergent_branch = true;
8403       ctx->cf_info.nir_to_aco[instr->instr.block->index] = ctx->block->index;
8404       break;
8405    case nir_jump_continue:
8406       logical_target = &ctx->program->blocks[ctx->cf_info.parent_loop.header_idx];
8407       add_logical_edge(idx, logical_target);
8408       ctx->block->kind |= block_kind_continue;
8409
8410       if (ctx->cf_info.parent_if.is_divergent) {
8411          /* for potential uniform breaks after this continue,
8412             we must ensure that they are handled correctly */
8413          ctx->cf_info.parent_loop.has_divergent_continue = true;
8414          ctx->cf_info.parent_loop.has_divergent_branch = true;
8415          ctx->cf_info.nir_to_aco[instr->instr.block->index] = ctx->block->index;
8416       } else {
8417          /* uniform continue - directly jump to the loop header */
8418          ctx->block->kind |= block_kind_uniform;
8419          ctx->cf_info.has_branch = true;
8420          bld.branch(aco_opcode::p_branch);
8421          add_linear_edge(idx, logical_target);
8422          return;
8423       }
8424       break;
8425    default:
8426       fprintf(stderr, "Unknown NIR jump instr: ");
8427       nir_print_instr(&instr->instr, stderr);
8428       fprintf(stderr, "\n");
8429       abort();
8430    }
8431
8432    if (ctx->cf_info.parent_if.is_divergent && !ctx->cf_info.exec_potentially_empty_break) {
8433       ctx->cf_info.exec_potentially_empty_break = true;
8434       ctx->cf_info.exec_potentially_empty_break_depth = ctx->cf_info.loop_nest_depth;
8435    }
8436
8437    /* remove critical edges from linear CFG */
8438    bld.branch(aco_opcode::p_branch);
8439    Block* break_block = ctx->program->create_and_insert_block();
8440    break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8441    break_block->kind |= block_kind_uniform;
8442    add_linear_edge(idx, break_block);
8443    /* the loop_header pointer might be invalidated by this point */
8444    if (instr->type == nir_jump_continue)
8445       logical_target = &ctx->program->blocks[ctx->cf_info.parent_loop.header_idx];
8446    add_linear_edge(break_block->index, logical_target);
8447    bld.reset(break_block);
8448    bld.branch(aco_opcode::p_branch);
8449
8450    Block* continue_block = ctx->program->create_and_insert_block();
8451    continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8452    add_linear_edge(idx, continue_block);
8453    append_logical_start(continue_block);
8454    ctx->block = continue_block;
8455    return;
8456 }
8457
8458 void visit_block(isel_context *ctx, nir_block *block)
8459 {
8460    nir_foreach_instr(instr, block) {
8461       switch (instr->type) {
8462       case nir_instr_type_alu:
8463          visit_alu_instr(ctx, nir_instr_as_alu(instr));
8464          break;
8465       case nir_instr_type_load_const:
8466          visit_load_const(ctx, nir_instr_as_load_const(instr));
8467          break;
8468       case nir_instr_type_intrinsic:
8469          visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
8470          break;
8471       case nir_instr_type_tex:
8472          visit_tex(ctx, nir_instr_as_tex(instr));
8473          break;
8474       case nir_instr_type_phi:
8475          visit_phi(ctx, nir_instr_as_phi(instr));
8476          break;
8477       case nir_instr_type_ssa_undef:
8478          visit_undef(ctx, nir_instr_as_ssa_undef(instr));
8479          break;
8480       case nir_instr_type_deref:
8481          break;
8482       case nir_instr_type_jump:
8483          visit_jump(ctx, nir_instr_as_jump(instr));
8484          break;
8485       default:
8486          fprintf(stderr, "Unknown NIR instr type: ");
8487          nir_print_instr(instr, stderr);
8488          fprintf(stderr, "\n");
8489          //abort();
8490       }
8491    }
8492
8493    if (!ctx->cf_info.parent_loop.has_divergent_branch)
8494       ctx->cf_info.nir_to_aco[block->index] = ctx->block->index;
8495 }
8496
8497
8498
8499 static Operand create_continue_phis(isel_context *ctx, unsigned first, unsigned last,
8500                                     aco_ptr<Instruction>& header_phi, Operand *vals)
8501 {
8502    vals[0] = Operand(header_phi->definitions[0].getTemp());
8503    RegClass rc = vals[0].regClass();
8504
8505    unsigned loop_nest_depth = ctx->program->blocks[first].loop_nest_depth;
8506
8507    unsigned next_pred = 1;
8508
8509    for (unsigned idx = first + 1; idx <= last; idx++) {
8510       Block& block = ctx->program->blocks[idx];
8511       if (block.loop_nest_depth != loop_nest_depth) {
8512          vals[idx - first] = vals[idx - 1 - first];
8513          continue;
8514       }
8515
8516       if (block.kind & block_kind_continue) {
8517          vals[idx - first] = header_phi->operands[next_pred];
8518          next_pred++;
8519          continue;
8520       }
8521
8522       bool all_same = true;
8523       for (unsigned i = 1; all_same && (i < block.linear_preds.size()); i++)
8524          all_same = vals[block.linear_preds[i] - first] == vals[block.linear_preds[0] - first];
8525
8526       Operand val;
8527       if (all_same) {
8528          val = vals[block.linear_preds[0] - first];
8529       } else {
8530          aco_ptr<Instruction> phi(create_instruction<Pseudo_instruction>(
8531             aco_opcode::p_linear_phi, Format::PSEUDO, block.linear_preds.size(), 1));
8532          for (unsigned i = 0; i < block.linear_preds.size(); i++)
8533             phi->operands[i] = vals[block.linear_preds[i] - first];
8534          val = Operand(Temp(ctx->program->allocateId(), rc));
8535          phi->definitions[0] = Definition(val.getTemp());
8536          block.instructions.emplace(block.instructions.begin(), std::move(phi));
8537       }
8538       vals[idx - first] = val;
8539    }
8540
8541    return vals[last - first];
8542 }
8543
8544 static void visit_loop(isel_context *ctx, nir_loop *loop)
8545 {
8546    //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
8547    append_logical_end(ctx->block);
8548    ctx->block->kind |= block_kind_loop_preheader | block_kind_uniform;
8549    Builder bld(ctx->program, ctx->block);
8550    bld.branch(aco_opcode::p_branch);
8551    unsigned loop_preheader_idx = ctx->block->index;
8552
8553    Block loop_exit = Block();
8554    loop_exit.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8555    loop_exit.kind |= (block_kind_loop_exit | (ctx->block->kind & block_kind_top_level));
8556
8557    Block* loop_header = ctx->program->create_and_insert_block();
8558    loop_header->loop_nest_depth = ctx->cf_info.loop_nest_depth + 1;
8559    loop_header->kind |= block_kind_loop_header;
8560    add_edge(loop_preheader_idx, loop_header);
8561    ctx->block = loop_header;
8562
8563    /* emit loop body */
8564    unsigned loop_header_idx = loop_header->index;
8565    loop_info_RAII loop_raii(ctx, loop_header_idx, &loop_exit);
8566    append_logical_start(ctx->block);
8567    bool unreachable = visit_cf_list(ctx, &loop->body);
8568
8569    //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
8570    if (!ctx->cf_info.has_branch) {
8571       append_logical_end(ctx->block);
8572       if (ctx->cf_info.exec_potentially_empty_discard || ctx->cf_info.exec_potentially_empty_break) {
8573          /* Discards can result in code running with an empty exec mask.
8574           * This would result in divergent breaks not ever being taken. As a
8575           * workaround, break the loop when the loop mask is empty instead of
8576           * always continuing. */
8577          ctx->block->kind |= (block_kind_continue_or_break | block_kind_uniform);
8578          unsigned block_idx = ctx->block->index;
8579
8580          /* create helper blocks to avoid critical edges */
8581          Block *break_block = ctx->program->create_and_insert_block();
8582          break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8583          break_block->kind = block_kind_uniform;
8584          bld.reset(break_block);
8585          bld.branch(aco_opcode::p_branch);
8586          add_linear_edge(block_idx, break_block);
8587          add_linear_edge(break_block->index, &loop_exit);
8588
8589          Block *continue_block = ctx->program->create_and_insert_block();
8590          continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8591          continue_block->kind = block_kind_uniform;
8592          bld.reset(continue_block);
8593          bld.branch(aco_opcode::p_branch);
8594          add_linear_edge(block_idx, continue_block);
8595          add_linear_edge(continue_block->index, &ctx->program->blocks[loop_header_idx]);
8596
8597          if (!ctx->cf_info.parent_loop.has_divergent_branch)
8598             add_logical_edge(block_idx, &ctx->program->blocks[loop_header_idx]);
8599          ctx->block = &ctx->program->blocks[block_idx];
8600       } else {
8601          ctx->block->kind |= (block_kind_continue | block_kind_uniform);
8602          if (!ctx->cf_info.parent_loop.has_divergent_branch)
8603             add_edge(ctx->block->index, &ctx->program->blocks[loop_header_idx]);
8604          else
8605             add_linear_edge(ctx->block->index, &ctx->program->blocks[loop_header_idx]);
8606       }
8607
8608       bld.reset(ctx->block);
8609       bld.branch(aco_opcode::p_branch);
8610    }
8611
8612    /* Fixup phis in loop header from unreachable blocks.
8613     * has_branch/has_divergent_branch also indicates if the loop ends with a
8614     * break/continue instruction, but we don't emit those if unreachable=true */
8615    if (unreachable) {
8616       assert(ctx->cf_info.has_branch || ctx->cf_info.parent_loop.has_divergent_branch);
8617       bool linear = ctx->cf_info.has_branch;
8618       bool logical = ctx->cf_info.has_branch || ctx->cf_info.parent_loop.has_divergent_branch;
8619       for (aco_ptr<Instruction>& instr : ctx->program->blocks[loop_header_idx].instructions) {
8620          if ((logical && instr->opcode == aco_opcode::p_phi) ||
8621              (linear && instr->opcode == aco_opcode::p_linear_phi)) {
8622             /* the last operand should be the one that needs to be removed */
8623             instr->operands.pop_back();
8624          } else if (!is_phi(instr)) {
8625             break;
8626          }
8627       }
8628    }
8629
8630    /* Fixup linear phis in loop header from expecting a continue. Both this fixup
8631     * and the previous one shouldn't both happen at once because a break in the
8632     * merge block would get CSE'd */
8633    if (nir_loop_last_block(loop)->successors[0] != nir_loop_first_block(loop)) {
8634       unsigned num_vals = ctx->cf_info.has_branch ? 1 : (ctx->block->index - loop_header_idx + 1);
8635       Operand vals[num_vals];
8636       for (aco_ptr<Instruction>& instr : ctx->program->blocks[loop_header_idx].instructions) {
8637          if (instr->opcode == aco_opcode::p_linear_phi) {
8638             if (ctx->cf_info.has_branch)
8639                instr->operands.pop_back();
8640             else
8641                instr->operands.back() = create_continue_phis(ctx, loop_header_idx, ctx->block->index, instr, vals);
8642          } else if (!is_phi(instr)) {
8643             break;
8644          }
8645       }
8646    }
8647
8648    ctx->cf_info.has_branch = false;
8649
8650    // TODO: if the loop has not a single exit, we must add one °°
8651    /* emit loop successor block */
8652    ctx->block = ctx->program->insert_block(std::move(loop_exit));
8653    append_logical_start(ctx->block);
8654
8655    #if 0
8656    // TODO: check if it is beneficial to not branch on continues
8657    /* trim linear phis in loop header */
8658    for (auto&& instr : loop_entry->instructions) {
8659       if (instr->opcode == aco_opcode::p_linear_phi) {
8660          aco_ptr<Pseudo_instruction> new_phi{create_instruction<Pseudo_instruction>(aco_opcode::p_linear_phi, Format::PSEUDO, loop_entry->linear_predecessors.size(), 1)};
8661          new_phi->definitions[0] = instr->definitions[0];
8662          for (unsigned i = 0; i < new_phi->operands.size(); i++)
8663             new_phi->operands[i] = instr->operands[i];
8664          /* check that the remaining operands are all the same */
8665          for (unsigned i = new_phi->operands.size(); i < instr->operands.size(); i++)
8666             assert(instr->operands[i].tempId() == instr->operands.back().tempId());
8667          instr.swap(new_phi);
8668       } else if (instr->opcode == aco_opcode::p_phi) {
8669          continue;
8670       } else {
8671          break;
8672       }
8673    }
8674    #endif
8675 }
8676
8677 static void begin_divergent_if_then(isel_context *ctx, if_context *ic, Temp cond)
8678 {
8679    ic->cond = cond;
8680
8681    append_logical_end(ctx->block);
8682    ctx->block->kind |= block_kind_branch;
8683
8684    /* branch to linear then block */
8685    assert(cond.regClass() == ctx->program->lane_mask);
8686    aco_ptr<Pseudo_branch_instruction> branch;
8687    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_z, Format::PSEUDO_BRANCH, 1, 0));
8688    branch->operands[0] = Operand(cond);
8689    ctx->block->instructions.push_back(std::move(branch));
8690
8691    ic->BB_if_idx = ctx->block->index;
8692    ic->BB_invert = Block();
8693    ic->BB_invert.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8694    /* Invert blocks are intentionally not marked as top level because they
8695     * are not part of the logical cfg. */
8696    ic->BB_invert.kind |= block_kind_invert;
8697    ic->BB_endif = Block();
8698    ic->BB_endif.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8699    ic->BB_endif.kind |= (block_kind_merge | (ctx->block->kind & block_kind_top_level));
8700
8701    ic->exec_potentially_empty_discard_old = ctx->cf_info.exec_potentially_empty_discard;
8702    ic->exec_potentially_empty_break_old = ctx->cf_info.exec_potentially_empty_break;
8703    ic->exec_potentially_empty_break_depth_old = ctx->cf_info.exec_potentially_empty_break_depth;
8704    ic->divergent_old = ctx->cf_info.parent_if.is_divergent;
8705    ctx->cf_info.parent_if.is_divergent = true;
8706
8707    /* divergent branches use cbranch_execz */
8708    ctx->cf_info.exec_potentially_empty_discard = false;
8709    ctx->cf_info.exec_potentially_empty_break = false;
8710    ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8711
8712    /** emit logical then block */
8713    Block* BB_then_logical = ctx->program->create_and_insert_block();
8714    BB_then_logical->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8715    add_edge(ic->BB_if_idx, BB_then_logical);
8716    ctx->block = BB_then_logical;
8717    append_logical_start(BB_then_logical);
8718 }
8719
8720 static void begin_divergent_if_else(isel_context *ctx, if_context *ic)
8721 {
8722    Block *BB_then_logical = ctx->block;
8723    append_logical_end(BB_then_logical);
8724     /* branch from logical then block to invert block */
8725    aco_ptr<Pseudo_branch_instruction> branch;
8726    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8727    BB_then_logical->instructions.emplace_back(std::move(branch));
8728    add_linear_edge(BB_then_logical->index, &ic->BB_invert);
8729    if (!ctx->cf_info.parent_loop.has_divergent_branch)
8730       add_logical_edge(BB_then_logical->index, &ic->BB_endif);
8731    BB_then_logical->kind |= block_kind_uniform;
8732    assert(!ctx->cf_info.has_branch);
8733    ic->then_branch_divergent = ctx->cf_info.parent_loop.has_divergent_branch;
8734    ctx->cf_info.parent_loop.has_divergent_branch = false;
8735
8736    /** emit linear then block */
8737    Block* BB_then_linear = ctx->program->create_and_insert_block();
8738    BB_then_linear->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8739    BB_then_linear->kind |= block_kind_uniform;
8740    add_linear_edge(ic->BB_if_idx, BB_then_linear);
8741    /* branch from linear then block to invert block */
8742    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8743    BB_then_linear->instructions.emplace_back(std::move(branch));
8744    add_linear_edge(BB_then_linear->index, &ic->BB_invert);
8745
8746    /** emit invert merge block */
8747    ctx->block = ctx->program->insert_block(std::move(ic->BB_invert));
8748    ic->invert_idx = ctx->block->index;
8749
8750    /* branch to linear else block (skip else) */
8751    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_nz, Format::PSEUDO_BRANCH, 1, 0));
8752    branch->operands[0] = Operand(ic->cond);
8753    ctx->block->instructions.push_back(std::move(branch));
8754
8755    ic->exec_potentially_empty_discard_old |= ctx->cf_info.exec_potentially_empty_discard;
8756    ic->exec_potentially_empty_break_old |= ctx->cf_info.exec_potentially_empty_break;
8757    ic->exec_potentially_empty_break_depth_old =
8758       std::min(ic->exec_potentially_empty_break_depth_old, ctx->cf_info.exec_potentially_empty_break_depth);
8759    /* divergent branches use cbranch_execz */
8760    ctx->cf_info.exec_potentially_empty_discard = false;
8761    ctx->cf_info.exec_potentially_empty_break = false;
8762    ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8763
8764    /** emit logical else block */
8765    Block* BB_else_logical = ctx->program->create_and_insert_block();
8766    BB_else_logical->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8767    add_logical_edge(ic->BB_if_idx, BB_else_logical);
8768    add_linear_edge(ic->invert_idx, BB_else_logical);
8769    ctx->block = BB_else_logical;
8770    append_logical_start(BB_else_logical);
8771 }
8772
8773 static void end_divergent_if(isel_context *ctx, if_context *ic)
8774 {
8775    Block *BB_else_logical = ctx->block;
8776    append_logical_end(BB_else_logical);
8777
8778    /* branch from logical else block to endif block */
8779    aco_ptr<Pseudo_branch_instruction> branch;
8780    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8781    BB_else_logical->instructions.emplace_back(std::move(branch));
8782    add_linear_edge(BB_else_logical->index, &ic->BB_endif);
8783    if (!ctx->cf_info.parent_loop.has_divergent_branch)
8784       add_logical_edge(BB_else_logical->index, &ic->BB_endif);
8785    BB_else_logical->kind |= block_kind_uniform;
8786
8787    assert(!ctx->cf_info.has_branch);
8788    ctx->cf_info.parent_loop.has_divergent_branch &= ic->then_branch_divergent;
8789
8790
8791    /** emit linear else block */
8792    Block* BB_else_linear = ctx->program->create_and_insert_block();
8793    BB_else_linear->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8794    BB_else_linear->kind |= block_kind_uniform;
8795    add_linear_edge(ic->invert_idx, BB_else_linear);
8796
8797    /* branch from linear else block to endif block */
8798    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8799    BB_else_linear->instructions.emplace_back(std::move(branch));
8800    add_linear_edge(BB_else_linear->index, &ic->BB_endif);
8801
8802
8803    /** emit endif merge block */
8804    ctx->block = ctx->program->insert_block(std::move(ic->BB_endif));
8805    append_logical_start(ctx->block);
8806
8807
8808    ctx->cf_info.parent_if.is_divergent = ic->divergent_old;
8809    ctx->cf_info.exec_potentially_empty_discard |= ic->exec_potentially_empty_discard_old;
8810    ctx->cf_info.exec_potentially_empty_break |= ic->exec_potentially_empty_break_old;
8811    ctx->cf_info.exec_potentially_empty_break_depth =
8812       std::min(ic->exec_potentially_empty_break_depth_old, ctx->cf_info.exec_potentially_empty_break_depth);
8813    if (ctx->cf_info.loop_nest_depth == ctx->cf_info.exec_potentially_empty_break_depth &&
8814        !ctx->cf_info.parent_if.is_divergent) {
8815       ctx->cf_info.exec_potentially_empty_break = false;
8816       ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8817    }
8818    /* uniform control flow never has an empty exec-mask */
8819    if (!ctx->cf_info.loop_nest_depth && !ctx->cf_info.parent_if.is_divergent) {
8820       ctx->cf_info.exec_potentially_empty_discard = false;
8821       ctx->cf_info.exec_potentially_empty_break = false;
8822       ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8823    }
8824 }
8825
8826 static bool visit_if(isel_context *ctx, nir_if *if_stmt)
8827 {
8828    Temp cond = get_ssa_temp(ctx, if_stmt->condition.ssa);
8829    Builder bld(ctx->program, ctx->block);
8830    aco_ptr<Pseudo_branch_instruction> branch;
8831
8832    if (!ctx->divergent_vals[if_stmt->condition.ssa->index]) { /* uniform condition */
8833       /**
8834        * Uniform conditionals are represented in the following way*) :
8835        *
8836        * The linear and logical CFG:
8837        *                        BB_IF
8838        *                        /    \
8839        *       BB_THEN (logical)      BB_ELSE (logical)
8840        *                        \    /
8841        *                        BB_ENDIF
8842        *
8843        * *) Exceptions may be due to break and continue statements within loops
8844        *    If a break/continue happens within uniform control flow, it branches
8845        *    to the loop exit/entry block. Otherwise, it branches to the next
8846        *    merge block.
8847        **/
8848       append_logical_end(ctx->block);
8849       ctx->block->kind |= block_kind_uniform;
8850
8851       /* emit branch */
8852       assert(cond.regClass() == bld.lm);
8853       // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
8854       cond = bool_to_scalar_condition(ctx, cond);
8855
8856       branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_z, Format::PSEUDO_BRANCH, 1, 0));
8857       branch->operands[0] = Operand(cond);
8858       branch->operands[0].setFixed(scc);
8859       ctx->block->instructions.emplace_back(std::move(branch));
8860
8861       unsigned BB_if_idx = ctx->block->index;
8862       Block BB_endif = Block();
8863       BB_endif.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8864       BB_endif.kind |= ctx->block->kind & block_kind_top_level;
8865
8866       /** emit then block */
8867       Block* BB_then = ctx->program->create_and_insert_block();
8868       BB_then->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8869       add_edge(BB_if_idx, BB_then);
8870       append_logical_start(BB_then);
8871       ctx->block = BB_then;
8872       visit_cf_list(ctx, &if_stmt->then_list);
8873       BB_then = ctx->block;
8874       bool then_branch = ctx->cf_info.has_branch;
8875       bool then_branch_divergent = ctx->cf_info.parent_loop.has_divergent_branch;
8876
8877       if (!then_branch) {
8878          append_logical_end(BB_then);
8879          /* branch from then block to endif block */
8880          branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8881          BB_then->instructions.emplace_back(std::move(branch));
8882          add_linear_edge(BB_then->index, &BB_endif);
8883          if (!then_branch_divergent)
8884             add_logical_edge(BB_then->index, &BB_endif);
8885          BB_then->kind |= block_kind_uniform;
8886       }
8887
8888       ctx->cf_info.has_branch = false;
8889       ctx->cf_info.parent_loop.has_divergent_branch = false;
8890
8891       /** emit else block */
8892       Block* BB_else = ctx->program->create_and_insert_block();
8893       BB_else->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8894       add_edge(BB_if_idx, BB_else);
8895       append_logical_start(BB_else);
8896       ctx->block = BB_else;
8897       visit_cf_list(ctx, &if_stmt->else_list);
8898       BB_else = ctx->block;
8899
8900       if (!ctx->cf_info.has_branch) {
8901          append_logical_end(BB_else);
8902          /* branch from then block to endif block */
8903          branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8904          BB_else->instructions.emplace_back(std::move(branch));
8905          add_linear_edge(BB_else->index, &BB_endif);
8906          if (!ctx->cf_info.parent_loop.has_divergent_branch)
8907             add_logical_edge(BB_else->index, &BB_endif);
8908          BB_else->kind |= block_kind_uniform;
8909       }
8910
8911       ctx->cf_info.has_branch &= then_branch;
8912       ctx->cf_info.parent_loop.has_divergent_branch &= then_branch_divergent;
8913
8914       /** emit endif merge block */
8915       if (!ctx->cf_info.has_branch) {
8916          ctx->block = ctx->program->insert_block(std::move(BB_endif));
8917          append_logical_start(ctx->block);
8918       }
8919       return !ctx->cf_info.has_branch;
8920    } else { /* non-uniform condition */
8921       /**
8922        * To maintain a logical and linear CFG without critical edges,
8923        * non-uniform conditionals are represented in the following way*) :
8924        *
8925        * The linear CFG:
8926        *                        BB_IF
8927        *                        /    \
8928        *       BB_THEN (logical)      BB_THEN (linear)
8929        *                        \    /
8930        *                        BB_INVERT (linear)
8931        *                        /    \
8932        *       BB_ELSE (logical)      BB_ELSE (linear)
8933        *                        \    /
8934        *                        BB_ENDIF
8935        *
8936        * The logical CFG:
8937        *                        BB_IF
8938        *                        /    \
8939        *       BB_THEN (logical)      BB_ELSE (logical)
8940        *                        \    /
8941        *                        BB_ENDIF
8942        *
8943        * *) Exceptions may be due to break and continue statements within loops
8944        **/
8945
8946       if_context ic;
8947
8948       begin_divergent_if_then(ctx, &ic, cond);
8949       visit_cf_list(ctx, &if_stmt->then_list);
8950
8951       begin_divergent_if_else(ctx, &ic);
8952       visit_cf_list(ctx, &if_stmt->else_list);
8953
8954       end_divergent_if(ctx, &ic);
8955
8956       return true;
8957    }
8958 }
8959
8960 static bool visit_cf_list(isel_context *ctx,
8961                           struct exec_list *list)
8962 {
8963    foreach_list_typed(nir_cf_node, node, node, list) {
8964       switch (node->type) {
8965       case nir_cf_node_block:
8966          visit_block(ctx, nir_cf_node_as_block(node));
8967          break;
8968       case nir_cf_node_if:
8969          if (!visit_if(ctx, nir_cf_node_as_if(node)))
8970             return true;
8971          break;
8972       case nir_cf_node_loop:
8973          visit_loop(ctx, nir_cf_node_as_loop(node));
8974          break;
8975       default:
8976          unreachable("unimplemented cf list type");
8977       }
8978    }
8979    return false;
8980 }
8981
8982 static void create_null_export(isel_context *ctx)
8983 {
8984    /* Some shader stages always need to have exports.
8985     * So when there is none, we need to add a null export.
8986     */
8987
8988    unsigned dest = (ctx->program->stage & hw_fs) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS;
8989    bool vm = (ctx->program->stage & hw_fs) || ctx->program->chip_class >= GFX10;
8990    Builder bld(ctx->program, ctx->block);
8991    bld.exp(aco_opcode::exp, Operand(v1), Operand(v1), Operand(v1), Operand(v1),
8992            /* enabled_mask */ 0, dest, /* compr */ false, /* done */ true, vm);
8993 }
8994
8995 static bool export_vs_varying(isel_context *ctx, int slot, bool is_pos, int *next_pos)
8996 {
8997    assert(ctx->stage == vertex_vs ||
8998           ctx->stage == tess_eval_vs ||
8999           ctx->stage == gs_copy_vs);
9000
9001    int offset = ctx->stage == tess_eval_vs
9002                 ? ctx->program->info->tes.outinfo.vs_output_param_offset[slot]
9003                 : ctx->program->info->vs.outinfo.vs_output_param_offset[slot];
9004    uint64_t mask = ctx->outputs.mask[slot];
9005    if (!is_pos && !mask)
9006       return false;
9007    if (!is_pos && offset == AC_EXP_PARAM_UNDEFINED)
9008       return false;
9009    aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
9010    exp->enabled_mask = mask;
9011    for (unsigned i = 0; i < 4; ++i) {
9012       if (mask & (1 << i))
9013          exp->operands[i] = Operand(ctx->outputs.outputs[slot][i]);
9014       else
9015          exp->operands[i] = Operand(v1);
9016    }
9017    /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9018     * Setting valid_mask=1 prevents it and has no other effect.
9019     */
9020    exp->valid_mask = ctx->options->chip_class >= GFX10 && is_pos && *next_pos == 0;
9021    exp->done = false;
9022    exp->compressed = false;
9023    if (is_pos)
9024       exp->dest = V_008DFC_SQ_EXP_POS + (*next_pos)++;
9025    else
9026       exp->dest = V_008DFC_SQ_EXP_PARAM + offset;
9027    ctx->block->instructions.emplace_back(std::move(exp));
9028
9029    return true;
9030 }
9031
9032 static void export_vs_psiz_layer_viewport(isel_context *ctx, int *next_pos)
9033 {
9034    aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
9035    exp->enabled_mask = 0;
9036    for (unsigned i = 0; i < 4; ++i)
9037       exp->operands[i] = Operand(v1);
9038    if (ctx->outputs.mask[VARYING_SLOT_PSIZ]) {
9039       exp->operands[0] = Operand(ctx->outputs.outputs[VARYING_SLOT_PSIZ][0]);
9040       exp->enabled_mask |= 0x1;
9041    }
9042    if (ctx->outputs.mask[VARYING_SLOT_LAYER]) {
9043       exp->operands[2] = Operand(ctx->outputs.outputs[VARYING_SLOT_LAYER][0]);
9044       exp->enabled_mask |= 0x4;
9045    }
9046    if (ctx->outputs.mask[VARYING_SLOT_VIEWPORT]) {
9047       if (ctx->options->chip_class < GFX9) {
9048          exp->operands[3] = Operand(ctx->outputs.outputs[VARYING_SLOT_VIEWPORT][0]);
9049          exp->enabled_mask |= 0x8;
9050       } else {
9051          Builder bld(ctx->program, ctx->block);
9052
9053          Temp out = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(16u),
9054                              Operand(ctx->outputs.outputs[VARYING_SLOT_VIEWPORT][0]));
9055          if (exp->operands[2].isTemp())
9056             out = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(out), exp->operands[2]);
9057
9058          exp->operands[2] = Operand(out);
9059          exp->enabled_mask |= 0x4;
9060       }
9061    }
9062    exp->valid_mask = ctx->options->chip_class >= GFX10 && *next_pos == 0;
9063    exp->done = false;
9064    exp->compressed = false;
9065    exp->dest = V_008DFC_SQ_EXP_POS + (*next_pos)++;
9066    ctx->block->instructions.emplace_back(std::move(exp));
9067 }
9068
9069 static void create_vs_exports(isel_context *ctx)
9070 {
9071    assert(ctx->stage == vertex_vs ||
9072           ctx->stage == tess_eval_vs ||
9073           ctx->stage == gs_copy_vs);
9074
9075    radv_vs_output_info *outinfo = ctx->stage == tess_eval_vs
9076                                   ? &ctx->program->info->tes.outinfo
9077                                   : &ctx->program->info->vs.outinfo;
9078
9079    if (outinfo->export_prim_id) {
9080       ctx->outputs.mask[VARYING_SLOT_PRIMITIVE_ID] |= 0x1;
9081       ctx->outputs.outputs[VARYING_SLOT_PRIMITIVE_ID][0] = get_arg(ctx, ctx->args->vs_prim_id);
9082    }
9083
9084    if (ctx->options->key.has_multiview_view_index) {
9085       ctx->outputs.mask[VARYING_SLOT_LAYER] |= 0x1;
9086       ctx->outputs.outputs[VARYING_SLOT_LAYER][0] = as_vgpr(ctx, get_arg(ctx, ctx->args->ac.view_index));
9087    }
9088
9089    /* the order these position exports are created is important */
9090    int next_pos = 0;
9091    bool exported_pos = export_vs_varying(ctx, VARYING_SLOT_POS, true, &next_pos);
9092    if (outinfo->writes_pointsize || outinfo->writes_layer || outinfo->writes_viewport_index) {
9093       export_vs_psiz_layer_viewport(ctx, &next_pos);
9094       exported_pos = true;
9095    }
9096    if (ctx->num_clip_distances + ctx->num_cull_distances > 0)
9097       exported_pos |= export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST0, true, &next_pos);
9098    if (ctx->num_clip_distances + ctx->num_cull_distances > 4)
9099       exported_pos |= export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST1, true, &next_pos);
9100
9101    if (ctx->export_clip_dists) {
9102       if (ctx->num_clip_distances + ctx->num_cull_distances > 0)
9103          export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST0, false, &next_pos);
9104       if (ctx->num_clip_distances + ctx->num_cull_distances > 4)
9105          export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST1, false, &next_pos);
9106    }
9107
9108    for (unsigned i = 0; i <= VARYING_SLOT_VAR31; ++i) {
9109       if (i < VARYING_SLOT_VAR0 && i != VARYING_SLOT_LAYER &&
9110           i != VARYING_SLOT_PRIMITIVE_ID)
9111          continue;
9112
9113       export_vs_varying(ctx, i, false, NULL);
9114    }
9115
9116    if (!exported_pos)
9117       create_null_export(ctx);
9118 }
9119
9120 static bool export_fs_mrt_z(isel_context *ctx)
9121 {
9122    Builder bld(ctx->program, ctx->block);
9123    unsigned enabled_channels = 0;
9124    bool compr = false;
9125    Operand values[4];
9126
9127    for (unsigned i = 0; i < 4; ++i) {
9128       values[i] = Operand(v1);
9129    }
9130
9131    /* Both stencil and sample mask only need 16-bits. */
9132    if (!ctx->program->info->ps.writes_z &&
9133        (ctx->program->info->ps.writes_stencil ||
9134         ctx->program->info->ps.writes_sample_mask)) {
9135       compr = true; /* COMPR flag */
9136
9137       if (ctx->program->info->ps.writes_stencil) {
9138          /* Stencil should be in X[23:16]. */
9139          values[0] = Operand(ctx->outputs.outputs[FRAG_RESULT_STENCIL][0]);
9140          values[0] = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(16u), values[0]);
9141          enabled_channels |= 0x3;
9142       }
9143
9144       if (ctx->program->info->ps.writes_sample_mask) {
9145          /* SampleMask should be in Y[15:0]. */
9146          values[1] = Operand(ctx->outputs.outputs[FRAG_RESULT_SAMPLE_MASK][0]);
9147          enabled_channels |= 0xc;
9148      }
9149    } else {
9150       if (ctx->program->info->ps.writes_z) {
9151          values[0] = Operand(ctx->outputs.outputs[FRAG_RESULT_DEPTH][0]);
9152          enabled_channels |= 0x1;
9153       }
9154
9155       if (ctx->program->info->ps.writes_stencil) {
9156          values[1] = Operand(ctx->outputs.outputs[FRAG_RESULT_STENCIL][0]);
9157          enabled_channels |= 0x2;
9158       }
9159
9160       if (ctx->program->info->ps.writes_sample_mask) {
9161          values[2] = Operand(ctx->outputs.outputs[FRAG_RESULT_SAMPLE_MASK][0]);
9162          enabled_channels |= 0x4;
9163       }
9164    }
9165
9166    /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9167     * writemask component.
9168     */
9169    if (ctx->options->chip_class == GFX6 &&
9170        ctx->options->family != CHIP_OLAND &&
9171        ctx->options->family != CHIP_HAINAN) {
9172             enabled_channels |= 0x1;
9173    }
9174
9175    bld.exp(aco_opcode::exp, values[0], values[1], values[2], values[3],
9176            enabled_channels, V_008DFC_SQ_EXP_MRTZ, compr);
9177
9178    return true;
9179 }
9180
9181 static bool export_fs_mrt_color(isel_context *ctx, int slot)
9182 {
9183    Builder bld(ctx->program, ctx->block);
9184    unsigned write_mask = ctx->outputs.mask[slot];
9185    Operand values[4];
9186
9187    for (unsigned i = 0; i < 4; ++i) {
9188       if (write_mask & (1 << i)) {
9189          values[i] = Operand(ctx->outputs.outputs[slot][i]);
9190       } else {
9191          values[i] = Operand(v1);
9192       }
9193    }
9194
9195    unsigned target, col_format;
9196    unsigned enabled_channels = 0;
9197    aco_opcode compr_op = (aco_opcode)0;
9198
9199    slot -= FRAG_RESULT_DATA0;
9200    target = V_008DFC_SQ_EXP_MRT + slot;
9201    col_format = (ctx->options->key.fs.col_format >> (4 * slot)) & 0xf;
9202
9203    bool is_int8 = (ctx->options->key.fs.is_int8 >> slot) & 1;
9204    bool is_int10 = (ctx->options->key.fs.is_int10 >> slot) & 1;
9205
9206    switch (col_format)
9207    {
9208    case V_028714_SPI_SHADER_ZERO:
9209       enabled_channels = 0; /* writemask */
9210       target = V_008DFC_SQ_EXP_NULL;
9211       break;
9212
9213    case V_028714_SPI_SHADER_32_R:
9214       enabled_channels = 1;
9215       break;
9216
9217    case V_028714_SPI_SHADER_32_GR:
9218       enabled_channels = 0x3;
9219       break;
9220
9221    case V_028714_SPI_SHADER_32_AR:
9222       if (ctx->options->chip_class >= GFX10) {
9223          /* Special case: on GFX10, the outputs are different for 32_AR */
9224          enabled_channels = 0x3;
9225          values[1] = values[3];
9226          values[3] = Operand(v1);
9227       } else {
9228          enabled_channels = 0x9;
9229       }
9230       break;
9231
9232    case V_028714_SPI_SHADER_FP16_ABGR:
9233       enabled_channels = 0x5;
9234       compr_op = aco_opcode::v_cvt_pkrtz_f16_f32;
9235       break;
9236
9237    case V_028714_SPI_SHADER_UNORM16_ABGR:
9238       enabled_channels = 0x5;
9239       compr_op = aco_opcode::v_cvt_pknorm_u16_f32;
9240       break;
9241
9242    case V_028714_SPI_SHADER_SNORM16_ABGR:
9243       enabled_channels = 0x5;
9244       compr_op = aco_opcode::v_cvt_pknorm_i16_f32;
9245       break;
9246
9247    case V_028714_SPI_SHADER_UINT16_ABGR: {
9248       enabled_channels = 0x5;
9249       compr_op = aco_opcode::v_cvt_pk_u16_u32;
9250       if (is_int8 || is_int10) {
9251          /* clamp */
9252          uint32_t max_rgb = is_int8 ? 255 : is_int10 ? 1023 : 0;
9253          Temp max_rgb_val = bld.copy(bld.def(s1), Operand(max_rgb));
9254
9255          for (unsigned i = 0; i < 4; i++) {
9256             if ((write_mask >> i) & 1) {
9257                values[i] = bld.vop2(aco_opcode::v_min_u32, bld.def(v1),
9258                                     i == 3 && is_int10 ? Operand(3u) : Operand(max_rgb_val),
9259                                     values[i]);
9260             }
9261          }
9262       }
9263       break;
9264    }
9265
9266    case V_028714_SPI_SHADER_SINT16_ABGR:
9267       enabled_channels = 0x5;
9268       compr_op = aco_opcode::v_cvt_pk_i16_i32;
9269       if (is_int8 || is_int10) {
9270          /* clamp */
9271          uint32_t max_rgb = is_int8 ? 127 : is_int10 ? 511 : 0;
9272          uint32_t min_rgb = is_int8 ? -128 :is_int10 ? -512 : 0;
9273          Temp max_rgb_val = bld.copy(bld.def(s1), Operand(max_rgb));
9274          Temp min_rgb_val = bld.copy(bld.def(s1), Operand(min_rgb));
9275
9276          for (unsigned i = 0; i < 4; i++) {
9277             if ((write_mask >> i) & 1) {
9278                values[i] = bld.vop2(aco_opcode::v_min_i32, bld.def(v1),
9279                                     i == 3 && is_int10 ? Operand(1u) : Operand(max_rgb_val),
9280                                     values[i]);
9281                values[i] = bld.vop2(aco_opcode::v_max_i32, bld.def(v1),
9282                                     i == 3 && is_int10 ? Operand(-2u) : Operand(min_rgb_val),
9283                                     values[i]);
9284             }
9285          }
9286       }
9287       break;
9288
9289    case V_028714_SPI_SHADER_32_ABGR:
9290       enabled_channels = 0xF;
9291       break;
9292
9293    default:
9294       break;
9295    }
9296
9297    if (target == V_008DFC_SQ_EXP_NULL)
9298       return false;
9299
9300    if ((bool) compr_op) {
9301       for (int i = 0; i < 2; i++) {
9302          /* check if at least one of the values to be compressed is enabled */
9303          unsigned enabled = (write_mask >> (i*2) | write_mask >> (i*2+1)) & 0x1;
9304          if (enabled) {
9305             enabled_channels |= enabled << (i*2);
9306             values[i] = bld.vop3(compr_op, bld.def(v1),
9307                                  values[i*2].isUndefined() ? Operand(0u) : values[i*2],
9308                                  values[i*2+1].isUndefined() ? Operand(0u): values[i*2+1]);
9309          } else {
9310             values[i] = Operand(v1);
9311          }
9312       }
9313       values[2] = Operand(v1);
9314       values[3] = Operand(v1);
9315    } else {
9316       for (int i = 0; i < 4; i++)
9317          values[i] = enabled_channels & (1 << i) ? values[i] : Operand(v1);
9318    }
9319
9320    bld.exp(aco_opcode::exp, values[0], values[1], values[2], values[3],
9321            enabled_channels, target, (bool) compr_op);
9322    return true;
9323 }
9324
9325 static void create_fs_exports(isel_context *ctx)
9326 {
9327    bool exported = false;
9328
9329    /* Export depth, stencil and sample mask. */
9330    if (ctx->outputs.mask[FRAG_RESULT_DEPTH] ||
9331        ctx->outputs.mask[FRAG_RESULT_STENCIL] ||
9332        ctx->outputs.mask[FRAG_RESULT_SAMPLE_MASK])
9333       exported |= export_fs_mrt_z(ctx);
9334
9335    /* Export all color render targets. */
9336    for (unsigned i = FRAG_RESULT_DATA0; i < FRAG_RESULT_DATA7 + 1; ++i)
9337       if (ctx->outputs.mask[i])
9338          exported |= export_fs_mrt_color(ctx, i);
9339
9340    if (!exported)
9341       create_null_export(ctx);
9342 }
9343
9344 static void write_tcs_tess_factors(isel_context *ctx)
9345 {
9346    unsigned outer_comps;
9347    unsigned inner_comps;
9348
9349    switch (ctx->args->options->key.tcs.primitive_mode) {
9350    case GL_ISOLINES:
9351       outer_comps = 2;
9352       inner_comps = 0;
9353       break;
9354    case GL_TRIANGLES:
9355       outer_comps = 3;
9356       inner_comps = 1;
9357       break;
9358    case GL_QUADS:
9359       outer_comps = 4;
9360       inner_comps = 2;
9361       break;
9362    default:
9363       return;
9364    }
9365
9366    Builder bld(ctx->program, ctx->block);
9367
9368    bld.barrier(aco_opcode::p_memory_barrier_shared);
9369    unsigned workgroup_size = ctx->tcs_num_patches * ctx->shader->info.tess.tcs_vertices_out;
9370    if (unlikely(ctx->program->chip_class != GFX6 && workgroup_size > ctx->program->wave_size))
9371       bld.sopp(aco_opcode::s_barrier);
9372
9373    Temp tcs_rel_ids = get_arg(ctx, ctx->args->ac.tcs_rel_ids);
9374    Temp invocation_id = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1), tcs_rel_ids, Operand(8u), Operand(5u));
9375
9376    Temp invocation_id_is_zero = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), invocation_id);
9377    if_context ic_invocation_id_is_zero;
9378    begin_divergent_if_then(ctx, &ic_invocation_id_is_zero, invocation_id_is_zero);
9379    bld.reset(ctx->block);
9380
9381    Temp hs_ring_tess_factor = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_HS_TESS_FACTOR * 16u));
9382
9383    std::pair<Temp, unsigned> lds_base = get_tcs_output_lds_offset(ctx);
9384    unsigned stride = inner_comps + outer_comps;
9385    unsigned lds_align = calculate_lds_alignment(ctx, lds_base.second);
9386    Temp tf_inner_vec;
9387    Temp tf_outer_vec;
9388    Temp out[6];
9389    assert(stride <= (sizeof(out) / sizeof(Temp)));
9390
9391    if (ctx->args->options->key.tcs.primitive_mode == GL_ISOLINES) {
9392       // LINES reversal
9393       tf_outer_vec = load_lds(ctx, 4, bld.tmp(v2), lds_base.first, lds_base.second + ctx->tcs_tess_lvl_out_loc, lds_align);
9394       out[1] = emit_extract_vector(ctx, tf_outer_vec, 0, v1);
9395       out[0] = emit_extract_vector(ctx, tf_outer_vec, 1, v1);
9396    } else {
9397       tf_outer_vec = load_lds(ctx, 4, bld.tmp(RegClass(RegType::vgpr, outer_comps)), lds_base.first, lds_base.second + ctx->tcs_tess_lvl_out_loc, lds_align);
9398       tf_inner_vec = load_lds(ctx, 4, bld.tmp(RegClass(RegType::vgpr, inner_comps)), lds_base.first, lds_base.second + ctx->tcs_tess_lvl_in_loc, lds_align);
9399
9400       for (unsigned i = 0; i < outer_comps; ++i)
9401          out[i] = emit_extract_vector(ctx, tf_outer_vec, i, v1);
9402       for (unsigned i = 0; i < inner_comps; ++i)
9403          out[outer_comps + i] = emit_extract_vector(ctx, tf_inner_vec, i, v1);
9404    }
9405
9406    Temp rel_patch_id = get_tess_rel_patch_id(ctx);
9407    Temp tf_base = get_arg(ctx, ctx->args->tess_factor_offset);
9408    Temp byte_offset = bld.v_mul_imm(bld.def(v1), rel_patch_id, stride * 4u);
9409    unsigned tf_const_offset = 0;
9410
9411    if (ctx->program->chip_class <= GFX8) {
9412       Temp rel_patch_id_is_zero = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), rel_patch_id);
9413       if_context ic_rel_patch_id_is_zero;
9414       begin_divergent_if_then(ctx, &ic_rel_patch_id_is_zero, rel_patch_id_is_zero);
9415       bld.reset(ctx->block);
9416
9417       /* Store the dynamic HS control word. */
9418       Temp control_word = bld.copy(bld.def(v1), Operand(0x80000000u));
9419       bld.mubuf(aco_opcode::buffer_store_dword,
9420                 /* SRSRC */ hs_ring_tess_factor, /* VADDR */ Operand(v1), /* SOFFSET */ tf_base, /* VDATA */ control_word,
9421                 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
9422                 /* disable_wqm */ false, /* glc */ true);
9423       tf_const_offset += 4;
9424
9425       begin_divergent_if_else(ctx, &ic_rel_patch_id_is_zero);
9426       end_divergent_if(ctx, &ic_rel_patch_id_is_zero);
9427       bld.reset(ctx->block);
9428    }
9429
9430    assert(stride == 2 || stride == 4 || stride == 6);
9431    Temp tf_vec = create_vec_from_array(ctx, out, stride, RegType::vgpr);
9432    store_vmem_mubuf(ctx, tf_vec, hs_ring_tess_factor, byte_offset, tf_base, tf_const_offset, 4, (1 << stride) - 1, true, false);
9433
9434    /* Store to offchip for TES to read - only if TES reads them */
9435    if (ctx->args->options->key.tcs.tes_reads_tess_factors) {
9436       Temp hs_ring_tess_offchip = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_HS_TESS_OFFCHIP * 16u));
9437       Temp oc_lds = get_arg(ctx, ctx->args->oc_lds);
9438
9439       std::pair<Temp, unsigned> vmem_offs_outer = get_tcs_per_patch_output_vmem_offset(ctx, nullptr, ctx->tcs_tess_lvl_out_loc);
9440       store_vmem_mubuf(ctx, tf_outer_vec, hs_ring_tess_offchip, vmem_offs_outer.first, oc_lds, vmem_offs_outer.second, 4, (1 << outer_comps) - 1, true, false);
9441
9442       if (likely(inner_comps)) {
9443          std::pair<Temp, unsigned> vmem_offs_inner = get_tcs_per_patch_output_vmem_offset(ctx, nullptr, ctx->tcs_tess_lvl_in_loc);
9444          store_vmem_mubuf(ctx, tf_inner_vec, hs_ring_tess_offchip, vmem_offs_inner.first, oc_lds, vmem_offs_inner.second, 4, (1 << inner_comps) - 1, true, false);
9445       }
9446    }
9447
9448    begin_divergent_if_else(ctx, &ic_invocation_id_is_zero);
9449    end_divergent_if(ctx, &ic_invocation_id_is_zero);
9450 }
9451
9452 static void emit_stream_output(isel_context *ctx,
9453                                Temp const *so_buffers,
9454                                Temp const *so_write_offset,
9455                                const struct radv_stream_output *output)
9456 {
9457    unsigned num_comps = util_bitcount(output->component_mask);
9458    unsigned writemask = (1 << num_comps) - 1;
9459    unsigned loc = output->location;
9460    unsigned buf = output->buffer;
9461
9462    assert(num_comps && num_comps <= 4);
9463    if (!num_comps || num_comps > 4)
9464       return;
9465
9466    unsigned start = ffs(output->component_mask) - 1;
9467
9468    Temp out[4];
9469    bool all_undef = true;
9470    assert(ctx->stage == vertex_vs || ctx->stage == gs_copy_vs);
9471    for (unsigned i = 0; i < num_comps; i++) {
9472       out[i] = ctx->outputs.outputs[loc][start + i];
9473       all_undef = all_undef && !out[i].id();
9474    }
9475    if (all_undef)
9476       return;
9477
9478    while (writemask) {
9479       int start, count;
9480       u_bit_scan_consecutive_range(&writemask, &start, &count);
9481       if (count == 3 && ctx->options->chip_class == GFX6) {
9482          /* GFX6 doesn't support storing vec3, split it. */
9483          writemask |= 1u << (start + 2);
9484          count = 2;
9485       }
9486
9487       unsigned offset = output->offset + start * 4;
9488
9489       Temp write_data = {ctx->program->allocateId(), RegClass(RegType::vgpr, count)};
9490       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
9491       for (int i = 0; i < count; ++i)
9492          vec->operands[i] = (ctx->outputs.mask[loc] & 1 << (start + i)) ? Operand(out[start + i]) : Operand(0u);
9493       vec->definitions[0] = Definition(write_data);
9494       ctx->block->instructions.emplace_back(std::move(vec));
9495
9496       aco_opcode opcode;
9497       switch (count) {
9498       case 1:
9499          opcode = aco_opcode::buffer_store_dword;
9500          break;
9501       case 2:
9502          opcode = aco_opcode::buffer_store_dwordx2;
9503          break;
9504       case 3:
9505          opcode = aco_opcode::buffer_store_dwordx3;
9506          break;
9507       case 4:
9508          opcode = aco_opcode::buffer_store_dwordx4;
9509          break;
9510       default:
9511          unreachable("Unsupported dword count.");
9512       }
9513
9514       aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 4, 0)};
9515       store->operands[0] = Operand(so_buffers[buf]);
9516       store->operands[1] = Operand(so_write_offset[buf]);
9517       store->operands[2] = Operand((uint32_t) 0);
9518       store->operands[3] = Operand(write_data);
9519       if (offset > 4095) {
9520          /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
9521          Builder bld(ctx->program, ctx->block);
9522          store->operands[0] = bld.vadd32(bld.def(v1), Operand(offset), Operand(so_write_offset[buf]));
9523       } else {
9524          store->offset = offset;
9525       }
9526       store->offen = true;
9527       store->glc = true;
9528       store->dlc = false;
9529       store->slc = true;
9530       store->can_reorder = true;
9531       ctx->block->instructions.emplace_back(std::move(store));
9532    }
9533 }
9534
9535 static void emit_streamout(isel_context *ctx, unsigned stream)
9536 {
9537    Builder bld(ctx->program, ctx->block);
9538
9539    Temp so_buffers[4];
9540    Temp buf_ptr = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->streamout_buffers));
9541    for (unsigned i = 0; i < 4; i++) {
9542       unsigned stride = ctx->program->info->so.strides[i];
9543       if (!stride)
9544          continue;
9545
9546       Operand off = bld.copy(bld.def(s1), Operand(i * 16u));
9547       so_buffers[i] = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), buf_ptr, off);
9548    }
9549
9550    Temp so_vtx_count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
9551                                 get_arg(ctx, ctx->args->streamout_config), Operand(0x70010u));
9552
9553    Temp tid = emit_mbcnt(ctx, bld.def(v1));
9554
9555    Temp can_emit = bld.vopc(aco_opcode::v_cmp_gt_i32, bld.def(bld.lm), so_vtx_count, tid);
9556
9557    if_context ic;
9558    begin_divergent_if_then(ctx, &ic, can_emit);
9559
9560    bld.reset(ctx->block);
9561
9562    Temp so_write_index = bld.vadd32(bld.def(v1), get_arg(ctx, ctx->args->streamout_write_idx), tid);
9563
9564    Temp so_write_offset[4];
9565
9566    for (unsigned i = 0; i < 4; i++) {
9567       unsigned stride = ctx->program->info->so.strides[i];
9568       if (!stride)
9569          continue;
9570
9571       if (stride == 1) {
9572          Temp offset = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
9573                                 get_arg(ctx, ctx->args->streamout_write_idx),
9574                                 get_arg(ctx, ctx->args->streamout_offset[i]));
9575          Temp new_offset = bld.vadd32(bld.def(v1), offset, tid);
9576
9577          so_write_offset[i] = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), new_offset);
9578       } else {
9579          Temp offset = bld.v_mul_imm(bld.def(v1), so_write_index, stride * 4u);
9580          Temp offset2 = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(4u),
9581                                  get_arg(ctx, ctx->args->streamout_offset[i]));
9582          so_write_offset[i] = bld.vadd32(bld.def(v1), offset, offset2);
9583       }
9584    }
9585
9586    for (unsigned i = 0; i < ctx->program->info->so.num_outputs; i++) {
9587       struct radv_stream_output *output =
9588          &ctx->program->info->so.outputs[i];
9589       if (stream != output->stream)
9590          continue;
9591
9592       emit_stream_output(ctx, so_buffers, so_write_offset, output);
9593    }
9594
9595    begin_divergent_if_else(ctx, &ic);
9596    end_divergent_if(ctx, &ic);
9597 }
9598
9599 } /* end namespace */
9600
9601 void fix_ls_vgpr_init_bug(isel_context *ctx, Pseudo_instruction *startpgm)
9602 {
9603    assert(ctx->shader->info.stage == MESA_SHADER_VERTEX);
9604    Builder bld(ctx->program, ctx->block);
9605    constexpr unsigned hs_idx = 1u;
9606    Builder::Result hs_thread_count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
9607                                               get_arg(ctx, ctx->args->merged_wave_info),
9608                                               Operand((8u << 16) | (hs_idx * 8u)));
9609    Temp ls_has_nonzero_hs_threads = bool_to_vector_condition(ctx, hs_thread_count.def(1).getTemp());
9610
9611    /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
9612
9613    Temp instance_id = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
9614                                get_arg(ctx, ctx->args->rel_auto_id),
9615                                get_arg(ctx, ctx->args->ac.instance_id),
9616                                ls_has_nonzero_hs_threads);
9617    Temp rel_auto_id = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
9618                                get_arg(ctx, ctx->args->ac.tcs_rel_ids),
9619                                get_arg(ctx, ctx->args->rel_auto_id),
9620                                ls_has_nonzero_hs_threads);
9621    Temp vertex_id = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
9622                              get_arg(ctx, ctx->args->ac.tcs_patch_id),
9623                              get_arg(ctx, ctx->args->ac.vertex_id),
9624                              ls_has_nonzero_hs_threads);
9625
9626    ctx->arg_temps[ctx->args->ac.instance_id.arg_index] = instance_id;
9627    ctx->arg_temps[ctx->args->rel_auto_id.arg_index] = rel_auto_id;
9628    ctx->arg_temps[ctx->args->ac.vertex_id.arg_index] = vertex_id;
9629 }
9630
9631 void split_arguments(isel_context *ctx, Pseudo_instruction *startpgm)
9632 {
9633    /* Split all arguments except for the first (ring_offsets) and the last
9634     * (exec) so that the dead channels don't stay live throughout the program.
9635     */
9636    for (int i = 1; i < startpgm->definitions.size() - 1; i++) {
9637       if (startpgm->definitions[i].regClass().size() > 1) {
9638          emit_split_vector(ctx, startpgm->definitions[i].getTemp(),
9639                            startpgm->definitions[i].regClass().size());
9640       }
9641    }
9642 }
9643
9644 void handle_bc_optimize(isel_context *ctx)
9645 {
9646    /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
9647    Builder bld(ctx->program, ctx->block);
9648    uint32_t spi_ps_input_ena = ctx->program->config->spi_ps_input_ena;
9649    bool uses_center = G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena);
9650    bool uses_centroid = G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena);
9651    ctx->persp_centroid = get_arg(ctx, ctx->args->ac.persp_centroid);
9652    ctx->linear_centroid = get_arg(ctx, ctx->args->ac.linear_centroid);
9653    if (uses_center && uses_centroid) {
9654       Temp sel = bld.vopc_e64(aco_opcode::v_cmp_lt_i32, bld.hint_vcc(bld.def(bld.lm)),
9655                               get_arg(ctx, ctx->args->ac.prim_mask), Operand(0u));
9656
9657       if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena)) {
9658          Temp new_coord[2];
9659          for (unsigned i = 0; i < 2; i++) {
9660             Temp persp_centroid = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.persp_centroid), i, v1);
9661             Temp persp_center = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.persp_center), i, v1);
9662             new_coord[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
9663                                     persp_centroid, persp_center, sel);
9664          }
9665          ctx->persp_centroid = bld.tmp(v2);
9666          bld.pseudo(aco_opcode::p_create_vector, Definition(ctx->persp_centroid),
9667                     Operand(new_coord[0]), Operand(new_coord[1]));
9668          emit_split_vector(ctx, ctx->persp_centroid, 2);
9669       }
9670
9671       if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena)) {
9672          Temp new_coord[2];
9673          for (unsigned i = 0; i < 2; i++) {
9674             Temp linear_centroid = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.linear_centroid), i, v1);
9675             Temp linear_center = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.linear_center), i, v1);
9676             new_coord[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
9677                                     linear_centroid, linear_center, sel);
9678          }
9679          ctx->linear_centroid = bld.tmp(v2);
9680          bld.pseudo(aco_opcode::p_create_vector, Definition(ctx->linear_centroid),
9681                     Operand(new_coord[0]), Operand(new_coord[1]));
9682          emit_split_vector(ctx, ctx->linear_centroid, 2);
9683       }
9684    }
9685 }
9686
9687 void setup_fp_mode(isel_context *ctx, nir_shader *shader)
9688 {
9689    Program *program = ctx->program;
9690
9691    unsigned float_controls = shader->info.float_controls_execution_mode;
9692
9693    program->next_fp_mode.preserve_signed_zero_inf_nan32 =
9694       float_controls & FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32;
9695    program->next_fp_mode.preserve_signed_zero_inf_nan16_64 =
9696       float_controls & (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16 |
9697                         FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64);
9698
9699    program->next_fp_mode.must_flush_denorms32 =
9700       float_controls & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32;
9701    program->next_fp_mode.must_flush_denorms16_64 =
9702       float_controls & (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16 |
9703                         FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64);
9704
9705    program->next_fp_mode.care_about_round32 =
9706       float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32 | FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32);
9707
9708    program->next_fp_mode.care_about_round16_64 =
9709       float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64 |
9710                         FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64);
9711
9712    /* default to preserving fp16 and fp64 denorms, since it's free */
9713    if (program->next_fp_mode.must_flush_denorms16_64)
9714       program->next_fp_mode.denorm16_64 = 0;
9715    else
9716       program->next_fp_mode.denorm16_64 = fp_denorm_keep;
9717
9718    /* preserving fp32 denorms is expensive, so only do it if asked */
9719    if (float_controls & FLOAT_CONTROLS_DENORM_PRESERVE_FP32)
9720       program->next_fp_mode.denorm32 = fp_denorm_keep;
9721    else
9722       program->next_fp_mode.denorm32 = 0;
9723
9724    if (float_controls & FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32)
9725       program->next_fp_mode.round32 = fp_round_tz;
9726    else
9727       program->next_fp_mode.round32 = fp_round_ne;
9728
9729    if (float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64))
9730       program->next_fp_mode.round16_64 = fp_round_tz;
9731    else
9732       program->next_fp_mode.round16_64 = fp_round_ne;
9733
9734    ctx->block->fp_mode = program->next_fp_mode;
9735 }
9736
9737 void cleanup_cfg(Program *program)
9738 {
9739    /* create linear_succs/logical_succs */
9740    for (Block& BB : program->blocks) {
9741       for (unsigned idx : BB.linear_preds)
9742          program->blocks[idx].linear_succs.emplace_back(BB.index);
9743       for (unsigned idx : BB.logical_preds)
9744          program->blocks[idx].logical_succs.emplace_back(BB.index);
9745    }
9746 }
9747
9748 void select_program(Program *program,
9749                     unsigned shader_count,
9750                     struct nir_shader *const *shaders,
9751                     ac_shader_config* config,
9752                     struct radv_shader_args *args)
9753 {
9754    isel_context ctx = setup_isel_context(program, shader_count, shaders, config, args, false);
9755
9756    for (unsigned i = 0; i < shader_count; i++) {
9757       nir_shader *nir = shaders[i];
9758       init_context(&ctx, nir);
9759
9760       setup_fp_mode(&ctx, nir);
9761
9762       if (!i) {
9763          /* needs to be after init_context() for FS */
9764          Pseudo_instruction *startpgm = add_startpgm(&ctx);
9765          append_logical_start(ctx.block);
9766
9767          if (unlikely(args->options->has_ls_vgpr_init_bug && ctx.stage == vertex_tess_control_hs))
9768             fix_ls_vgpr_init_bug(&ctx, startpgm);
9769
9770          split_arguments(&ctx, startpgm);
9771       }
9772
9773       /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
9774       nir_function_impl *func = nir_shader_get_entrypoint(nir);
9775       bool empty_shader = nir_cf_list_is_empty_block(&func->body) &&
9776                           ((nir->info.stage == MESA_SHADER_VERTEX &&
9777                             (ctx.stage == vertex_tess_control_hs || ctx.stage == vertex_geometry_gs)) ||
9778                            (nir->info.stage == MESA_SHADER_TESS_EVAL &&
9779                             ctx.stage == tess_eval_geometry_gs));
9780
9781       if_context ic;
9782       if (shader_count >= 2 && !empty_shader) {
9783          Builder bld(ctx.program, ctx.block);
9784          Temp count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), get_arg(&ctx, args->merged_wave_info), Operand((8u << 16) | (i * 8u)));
9785          Temp thread_id = emit_mbcnt(&ctx, bld.def(v1));
9786          Temp cond = bld.vopc(aco_opcode::v_cmp_gt_u32, bld.hint_vcc(bld.def(bld.lm)), count, thread_id);
9787
9788          begin_divergent_if_then(&ctx, &ic, cond);
9789       }
9790
9791       if (i) {
9792          Builder bld(ctx.program, ctx.block);
9793
9794          bld.barrier(aco_opcode::p_memory_barrier_shared);
9795          bld.sopp(aco_opcode::s_barrier);
9796
9797          if (ctx.stage == vertex_geometry_gs || ctx.stage == tess_eval_geometry_gs) {
9798             ctx.gs_wave_id = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1, m0), bld.def(s1, scc), get_arg(&ctx, args->merged_wave_info), Operand((8u << 16) | 16u));
9799          }
9800       } else if (ctx.stage == geometry_gs)
9801          ctx.gs_wave_id = get_arg(&ctx, args->gs_wave_id);
9802
9803       if (ctx.stage == fragment_fs)
9804          handle_bc_optimize(&ctx);
9805
9806       visit_cf_list(&ctx, &func->body);
9807
9808       if (ctx.program->info->so.num_outputs && (ctx.stage == vertex_vs || ctx.stage == tess_eval_vs))
9809          emit_streamout(&ctx, 0);
9810
9811       if (ctx.stage == vertex_vs || ctx.stage == tess_eval_vs) {
9812          create_vs_exports(&ctx);
9813       } else if (nir->info.stage == MESA_SHADER_GEOMETRY) {
9814          Builder bld(ctx.program, ctx.block);
9815          bld.barrier(aco_opcode::p_memory_barrier_gs_data);
9816          bld.sopp(aco_opcode::s_sendmsg, bld.m0(ctx.gs_wave_id), -1, sendmsg_gs_done(false, false, 0));
9817       } else if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
9818          write_tcs_tess_factors(&ctx);
9819       }
9820
9821       if (ctx.stage == fragment_fs)
9822          create_fs_exports(&ctx);
9823
9824       if (shader_count >= 2 && !empty_shader) {
9825          begin_divergent_if_else(&ctx, &ic);
9826          end_divergent_if(&ctx, &ic);
9827       }
9828
9829       ralloc_free(ctx.divergent_vals);
9830    }
9831
9832    program->config->float_mode = program->blocks[0].fp_mode.val;
9833
9834    append_logical_end(ctx.block);
9835    ctx.block->kind |= block_kind_uniform | block_kind_export_end;
9836    Builder bld(ctx.program, ctx.block);
9837    if (ctx.program->wb_smem_l1_on_end)
9838       bld.smem(aco_opcode::s_dcache_wb, false);
9839    bld.sopp(aco_opcode::s_endpgm);
9840
9841    cleanup_cfg(program);
9842 }
9843
9844 void select_gs_copy_shader(Program *program, struct nir_shader *gs_shader,
9845                            ac_shader_config* config,
9846                            struct radv_shader_args *args)
9847 {
9848    isel_context ctx = setup_isel_context(program, 1, &gs_shader, config, args, true);
9849
9850    program->next_fp_mode.preserve_signed_zero_inf_nan32 = false;
9851    program->next_fp_mode.preserve_signed_zero_inf_nan16_64 = false;
9852    program->next_fp_mode.must_flush_denorms32 = false;
9853    program->next_fp_mode.must_flush_denorms16_64 = false;
9854    program->next_fp_mode.care_about_round32 = false;
9855    program->next_fp_mode.care_about_round16_64 = false;
9856    program->next_fp_mode.denorm16_64 = fp_denorm_keep;
9857    program->next_fp_mode.denorm32 = 0;
9858    program->next_fp_mode.round32 = fp_round_ne;
9859    program->next_fp_mode.round16_64 = fp_round_ne;
9860    ctx.block->fp_mode = program->next_fp_mode;
9861
9862    add_startpgm(&ctx);
9863    append_logical_start(ctx.block);
9864
9865    Builder bld(ctx.program, ctx.block);
9866
9867    Temp gsvs_ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), program->private_segment_buffer, Operand(RING_GSVS_VS * 16u));
9868
9869    Operand stream_id(0u);
9870    if (args->shader_info->so.num_outputs)
9871       stream_id = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
9872                            get_arg(&ctx, ctx.args->streamout_config), Operand(0x20018u));
9873
9874    Temp vtx_offset = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), get_arg(&ctx, ctx.args->ac.vertex_id));
9875
9876    std::stack<Block> endif_blocks;
9877
9878    for (unsigned stream = 0; stream < 4; stream++) {
9879       if (stream_id.isConstant() && stream != stream_id.constantValue())
9880          continue;
9881
9882       unsigned num_components = args->shader_info->gs.num_stream_output_components[stream];
9883       if (stream > 0 && (!num_components || !args->shader_info->so.num_outputs))
9884          continue;
9885
9886       memset(ctx.outputs.mask, 0, sizeof(ctx.outputs.mask));
9887
9888       unsigned BB_if_idx = ctx.block->index;
9889       Block BB_endif = Block();
9890       if (!stream_id.isConstant()) {
9891          /* begin IF */
9892          Temp cond = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), stream_id, Operand(stream));
9893          append_logical_end(ctx.block);
9894          ctx.block->kind |= block_kind_uniform;
9895          bld.branch(aco_opcode::p_cbranch_z, cond);
9896
9897          BB_endif.kind |= ctx.block->kind & block_kind_top_level;
9898
9899          ctx.block = ctx.program->create_and_insert_block();
9900          add_edge(BB_if_idx, ctx.block);
9901          bld.reset(ctx.block);
9902          append_logical_start(ctx.block);
9903       }
9904
9905       unsigned offset = 0;
9906       for (unsigned i = 0; i <= VARYING_SLOT_VAR31; ++i) {
9907          if (args->shader_info->gs.output_streams[i] != stream)
9908             continue;
9909
9910          unsigned output_usage_mask = args->shader_info->gs.output_usage_mask[i];
9911          unsigned length = util_last_bit(output_usage_mask);
9912          for (unsigned j = 0; j < length; ++j) {
9913             if (!(output_usage_mask & (1 << j)))
9914                continue;
9915
9916             unsigned const_offset = offset * args->shader_info->gs.vertices_out * 16 * 4;
9917             Temp voffset = vtx_offset;
9918             if (const_offset >= 4096u) {
9919                voffset = bld.vadd32(bld.def(v1), Operand(const_offset / 4096u * 4096u), voffset);
9920                const_offset %= 4096u;
9921             }
9922
9923             aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(aco_opcode::buffer_load_dword, Format::MUBUF, 3, 1)};
9924             mubuf->definitions[0] = bld.def(v1);
9925             mubuf->operands[0] = Operand(gsvs_ring);
9926             mubuf->operands[1] = Operand(voffset);
9927             mubuf->operands[2] = Operand(0u);
9928             mubuf->offen = true;
9929             mubuf->offset = const_offset;
9930             mubuf->glc = true;
9931             mubuf->slc = true;
9932             mubuf->dlc = args->options->chip_class >= GFX10;
9933             mubuf->barrier = barrier_none;
9934             mubuf->can_reorder = true;
9935
9936             ctx.outputs.mask[i] |= 1 << j;
9937             ctx.outputs.outputs[i][j] = mubuf->definitions[0].getTemp();
9938
9939             bld.insert(std::move(mubuf));
9940
9941             offset++;
9942          }
9943       }
9944
9945       if (args->shader_info->so.num_outputs) {
9946          emit_streamout(&ctx, stream);
9947          bld.reset(ctx.block);
9948       }
9949
9950       if (stream == 0) {
9951          create_vs_exports(&ctx);
9952          ctx.block->kind |= block_kind_export_end;
9953       }
9954
9955       if (!stream_id.isConstant()) {
9956          append_logical_end(ctx.block);
9957
9958          /* branch from then block to endif block */
9959          bld.branch(aco_opcode::p_branch);
9960          add_edge(ctx.block->index, &BB_endif);
9961          ctx.block->kind |= block_kind_uniform;
9962
9963          /* emit else block */
9964          ctx.block = ctx.program->create_and_insert_block();
9965          add_edge(BB_if_idx, ctx.block);
9966          bld.reset(ctx.block);
9967          append_logical_start(ctx.block);
9968
9969          endif_blocks.push(std::move(BB_endif));
9970       }
9971    }
9972
9973    while (!endif_blocks.empty()) {
9974       Block BB_endif = std::move(endif_blocks.top());
9975       endif_blocks.pop();
9976
9977       Block *BB_else = ctx.block;
9978
9979       append_logical_end(BB_else);
9980       /* branch from else block to endif block */
9981       bld.branch(aco_opcode::p_branch);
9982       add_edge(BB_else->index, &BB_endif);
9983       BB_else->kind |= block_kind_uniform;
9984
9985       /** emit endif merge block */
9986       ctx.block = program->insert_block(std::move(BB_endif));
9987       bld.reset(ctx.block);
9988       append_logical_start(ctx.block);
9989    }
9990
9991    program->config->float_mode = program->blocks[0].fp_mode.val;
9992
9993    append_logical_end(ctx.block);
9994    ctx.block->kind |= block_kind_uniform;
9995    bld.sopp(aco_opcode::s_endpgm);
9996
9997    cleanup_cfg(program);
9998 }
9999 }