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3 * Copyright © 2018 Google
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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool then_branch_divergent
;
93 static bool visit_cf_list(struct isel_context
*ctx
,
94 struct exec_list
*list
);
96 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
98 succ
->logical_preds
.emplace_back(pred_idx
);
102 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
104 succ
->linear_preds
.emplace_back(pred_idx
);
107 static void add_edge(unsigned pred_idx
, Block
*succ
)
109 add_logical_edge(pred_idx
, succ
);
110 add_linear_edge(pred_idx
, succ
);
113 static void append_logical_start(Block
*b
)
115 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
118 static void append_logical_end(Block
*b
)
120 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
123 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
125 assert(ctx
->allocated
[def
->index
].id());
126 return ctx
->allocated
[def
->index
];
129 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
130 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
132 Builder
bld(ctx
->program
, ctx
->block
);
133 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
134 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
136 if (ctx
->program
->wave_size
== 32) {
139 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
144 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
146 Builder
bld(ctx
->program
, ctx
->block
);
149 dst
= bld
.tmp(src
.regClass());
151 assert(src
.size() == dst
.size());
153 if (ctx
->stage
!= fragment_fs
) {
157 bld
.copy(Definition(dst
), src
);
161 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
162 ctx
->program
->needs_wqm
|= program_needs_wqm
;
166 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
168 if (index
.regClass() == s1
)
169 return bld
.readlane(bld
.def(s1
), data
, index
);
171 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
173 /* Currently not implemented on GFX6-7 */
174 assert(ctx
->options
->chip_class
>= GFX8
);
176 if (ctx
->options
->chip_class
<= GFX9
|| ctx
->program
->wave_size
== 32) {
177 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
180 /* GFX10, wave64 mode:
181 * The bpermute instruction is limited to half-wave operation, which means that it can't
182 * properly support subgroup shuffle like older generations (or wave32 mode), so we
185 if (!ctx
->has_gfx10_wave64_bpermute
) {
186 ctx
->has_gfx10_wave64_bpermute
= true;
187 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
188 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
191 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
192 Temp lane_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), lane_id
);
193 Temp index_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), index
);
194 Temp cmp
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
, vcc
), lane_is_hi
, index_is_hi
);
196 return bld
.reduction(aco_opcode::p_wave64_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
),
197 bld
.vcc(cmp
), Operand(v2
.as_linear()), index_x4
, data
, gfx10_wave64_bpermute
);
200 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
202 if (val
.type() == RegType::sgpr
) {
203 Builder
bld(ctx
->program
, ctx
->block
);
204 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
206 assert(val
.type() == RegType::vgpr
);
210 //assumes a != 0xffffffff
211 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
214 Builder
bld(ctx
->program
, ctx
->block
);
216 if (util_is_power_of_two_or_zero(b
)) {
217 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
221 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
223 assert(info
.multiplier
<= 0xffffffff);
225 bool pre_shift
= info
.pre_shift
!= 0;
226 bool increment
= info
.increment
!= 0;
227 bool multiply
= true;
228 bool post_shift
= info
.post_shift
!= 0;
230 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
231 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
235 Temp pre_shift_dst
= a
;
237 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
238 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
241 Temp increment_dst
= pre_shift_dst
;
243 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
244 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
247 Temp multiply_dst
= increment_dst
;
249 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
250 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
251 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
255 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
259 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
261 Builder
bld(ctx
->program
, ctx
->block
);
262 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
266 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
268 /* no need to extract the whole vector */
269 if (src
.regClass() == dst_rc
) {
274 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
275 Builder
bld(ctx
->program
, ctx
->block
);
276 auto it
= ctx
->allocated_vec
.find(src
.id());
277 /* the size check needs to be early because elements other than 0 may be garbage */
278 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
279 if (it
->second
[idx
].regClass() == dst_rc
) {
280 return it
->second
[idx
];
282 assert(!dst_rc
.is_subdword());
283 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
284 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
288 if (dst_rc
.is_subdword())
289 src
= as_vgpr(ctx
, src
);
291 if (src
.bytes() == dst_rc
.bytes()) {
293 return bld
.copy(bld
.def(dst_rc
), src
);
295 Temp dst
= bld
.tmp(dst_rc
);
296 emit_extract_vector(ctx
, src
, idx
, dst
);
301 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
303 if (num_components
== 1)
305 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
307 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
308 split
->operands
[0] = Operand(vec_src
);
309 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
311 if (num_components
> vec_src
.size()) {
312 if (vec_src
.type() == RegType::sgpr
)
315 /* sub-dword split */
316 assert(vec_src
.type() == RegType::vgpr
);
317 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
319 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
321 for (unsigned i
= 0; i
< num_components
; i
++) {
322 elems
[i
] = {ctx
->program
->allocateId(), rc
};
323 split
->definitions
[i
] = Definition(elems
[i
]);
325 ctx
->block
->instructions
.emplace_back(std::move(split
));
326 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
329 /* This vector expansion uses a mask to determine which elements in the new vector
330 * come from the original vector. The other elements are undefined. */
331 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
333 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
338 Builder
bld(ctx
->program
, ctx
->block
);
339 if (num_components
== 1) {
340 if (dst
.type() == RegType::sgpr
)
341 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
343 bld
.copy(Definition(dst
), vec_src
);
347 unsigned component_size
= dst
.size() / num_components
;
348 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
350 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
351 vec
->definitions
[0] = Definition(dst
);
353 for (unsigned i
= 0; i
< num_components
; i
++) {
354 if (mask
& (1 << i
)) {
355 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
356 if (dst
.type() == RegType::sgpr
)
357 src
= bld
.as_uniform(src
);
358 vec
->operands
[i
] = Operand(src
);
360 vec
->operands
[i
] = Operand(0u);
362 elems
[i
] = vec
->operands
[i
].getTemp();
364 ctx
->block
->instructions
.emplace_back(std::move(vec
));
365 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
368 /* adjust misaligned small bit size loads */
369 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
371 Builder
bld(ctx
->program
, ctx
->block
);
373 Temp select
= Temp();
374 if (offset
.isConstant()) {
375 assert(offset
.constantValue() && offset
.constantValue() < 4);
376 shift
= Operand(offset
.constantValue() * 8);
378 /* bit_offset = 8 * (offset & 0x3) */
379 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
380 select
= bld
.tmp(s1
);
381 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
384 if (vec
.size() == 1) {
385 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
386 } else if (vec
.size() == 2) {
387 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
388 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
390 emit_split_vector(ctx
, dst
, 2);
392 emit_extract_vector(ctx
, tmp
, 0, dst
);
393 } else if (vec
.size() == 4) {
394 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
395 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
396 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
397 if (select
!= Temp())
398 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), select
);
399 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
400 Temp mid
= bld
.tmp(s1
);
401 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
402 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
403 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
404 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
405 emit_split_vector(ctx
, dst
, 2);
409 /* this function trims subdword vectors:
410 * if dst is vgpr - split the src and create a shrunk version according to the mask.
411 * if dst is sgpr - split the src, but move the original to sgpr. */
412 void trim_subdword_vector(isel_context
*ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
414 assert(vec_src
.type() == RegType::vgpr
);
415 emit_split_vector(ctx
, vec_src
, num_components
);
417 Builder
bld(ctx
->program
, ctx
->block
);
418 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
419 unsigned component_size
= vec_src
.bytes() / num_components
;
420 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
423 for (unsigned i
= 0; i
< num_components
; i
++) {
425 elems
[k
++] = emit_extract_vector(ctx
, vec_src
, i
, rc
);
428 if (dst
.type() == RegType::vgpr
) {
429 assert(dst
.bytes() == k
* component_size
);
430 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, k
, 1)};
431 for (unsigned i
= 0; i
< k
; i
++)
432 vec
->operands
[i
] = Operand(elems
[i
]);
433 vec
->definitions
[0] = Definition(dst
);
434 bld
.insert(std::move(vec
));
436 // TODO: alignbyte if mask doesn't start with 1?
438 assert(dst
.size() == vec_src
.size());
439 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
441 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
444 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
446 Builder
bld(ctx
->program
, ctx
->block
);
448 dst
= bld
.tmp(bld
.lm
);
450 assert(val
.regClass() == s1
);
451 assert(dst
.regClass() == bld
.lm
);
453 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
456 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
458 Builder
bld(ctx
->program
, ctx
->block
);
462 assert(val
.regClass() == bld
.lm
);
463 assert(dst
.regClass() == s1
);
465 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
466 Temp tmp
= bld
.tmp(s1
);
467 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
468 return emit_wqm(ctx
, tmp
, dst
);
471 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
473 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
474 return get_ssa_temp(ctx
, src
.src
.ssa
);
476 if (src
.src
.ssa
->num_components
== size
) {
477 bool identity_swizzle
= true;
478 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
479 if (src
.swizzle
[i
] != i
)
480 identity_swizzle
= false;
482 if (identity_swizzle
)
483 return get_ssa_temp(ctx
, src
.src
.ssa
);
486 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
487 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
488 assert(elem_size
> 0);
489 assert(vec
.bytes() % elem_size
== 0);
491 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
492 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
494 unsigned swizzle
= src
.swizzle
[0];
495 if (vec
.size() > 1) {
496 assert(src
.src
.ssa
->bit_size
== 16);
497 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
498 swizzle
= swizzle
& 1;
503 Temp dst
{ctx
->program
->allocateId(), s1
};
504 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 1)};
505 bfe
->operands
[0] = Operand(vec
);
506 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
507 bfe
->definitions
[0] = Definition(dst
);
508 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
512 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
514 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
517 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
518 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
519 for (unsigned i
= 0; i
< size
; ++i
) {
520 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
521 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
523 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
524 vec_instr
->definitions
[0] = Definition(dst
);
525 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
526 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
531 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
535 Builder
bld(ctx
->program
, ctx
->block
);
536 if (ptr
.type() == RegType::vgpr
)
537 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
538 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
539 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
542 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
544 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
545 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
546 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
547 sop2
->definitions
[0] = Definition(dst
);
549 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
550 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
553 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
554 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
556 Builder
bld(ctx
->program
, ctx
->block
);
557 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
558 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
559 if (src1
.type() == RegType::sgpr
) {
560 if (commutative
&& src0
.type() == RegType::vgpr
) {
564 } else if (src0
.type() == RegType::vgpr
&&
565 op
!= aco_opcode::v_madmk_f32
&&
566 op
!= aco_opcode::v_madak_f32
&&
567 op
!= aco_opcode::v_madmk_f16
&&
568 op
!= aco_opcode::v_madak_f16
) {
569 /* If the instruction is not commutative, we emit a VOP3A instruction */
570 bld
.vop2_e64(op
, Definition(dst
), src0
, src1
);
573 src1
= bld
.copy(bld
.def(RegType::vgpr
, src1
.size()), src1
); //TODO: as_vgpr
577 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
578 assert(dst
.size() == 1);
579 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
580 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
582 bld
.vop2(op
, Definition(dst
), src0
, src1
);
586 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
587 bool flush_denorms
= false)
589 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
590 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
591 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
593 /* ensure that the instruction has at most 1 sgpr operand
594 * The optimizer will inline constants for us */
595 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
596 src0
= as_vgpr(ctx
, src0
);
597 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
598 src1
= as_vgpr(ctx
, src1
);
599 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
600 src2
= as_vgpr(ctx
, src2
);
602 Builder
bld(ctx
->program
, ctx
->block
);
603 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
604 assert(dst
.size() == 1);
605 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
606 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
608 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
612 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
614 Builder
bld(ctx
->program
, ctx
->block
);
615 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
618 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
620 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
621 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
622 assert(src0
.size() == src1
.size());
624 aco_ptr
<Instruction
> vopc
;
625 if (src1
.type() == RegType::sgpr
) {
626 if (src0
.type() == RegType::vgpr
) {
627 /* to swap the operands, we might also have to change the opcode */
629 case aco_opcode::v_cmp_lt_f32
:
630 op
= aco_opcode::v_cmp_gt_f32
;
632 case aco_opcode::v_cmp_ge_f32
:
633 op
= aco_opcode::v_cmp_le_f32
;
635 case aco_opcode::v_cmp_lt_i32
:
636 op
= aco_opcode::v_cmp_gt_i32
;
638 case aco_opcode::v_cmp_ge_i32
:
639 op
= aco_opcode::v_cmp_le_i32
;
641 case aco_opcode::v_cmp_lt_u32
:
642 op
= aco_opcode::v_cmp_gt_u32
;
644 case aco_opcode::v_cmp_ge_u32
:
645 op
= aco_opcode::v_cmp_le_u32
;
647 case aco_opcode::v_cmp_lt_f64
:
648 op
= aco_opcode::v_cmp_gt_f64
;
650 case aco_opcode::v_cmp_ge_f64
:
651 op
= aco_opcode::v_cmp_le_f64
;
653 case aco_opcode::v_cmp_lt_i64
:
654 op
= aco_opcode::v_cmp_gt_i64
;
656 case aco_opcode::v_cmp_ge_i64
:
657 op
= aco_opcode::v_cmp_le_i64
;
659 case aco_opcode::v_cmp_lt_u64
:
660 op
= aco_opcode::v_cmp_gt_u64
;
662 case aco_opcode::v_cmp_ge_u64
:
663 op
= aco_opcode::v_cmp_le_u64
;
665 default: /* eq and ne are commutative */
672 src1
= as_vgpr(ctx
, src1
);
676 Builder
bld(ctx
->program
, ctx
->block
);
677 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
680 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
682 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
683 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
684 Builder
bld(ctx
->program
, ctx
->block
);
686 assert(dst
.regClass() == bld
.lm
);
687 assert(src0
.type() == RegType::sgpr
);
688 assert(src1
.type() == RegType::sgpr
);
689 assert(src0
.regClass() == src1
.regClass());
691 /* Emit the SALU comparison instruction */
692 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
693 /* Turn the result into a per-lane bool */
694 bool_to_vector_condition(ctx
, cmp
, dst
);
697 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
698 aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
700 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: s32_op
;
701 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: v32_op
;
702 bool divergent_vals
= ctx
->divergent_vals
[instr
->dest
.dest
.ssa
.index
];
703 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
705 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
706 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
707 aco_opcode op
= use_valu
? v_op
: s_op
;
708 assert(op
!= aco_opcode::num_opcodes
);
709 assert(dst
.regClass() == ctx
->program
->lane_mask
);
712 emit_vopc_instruction(ctx
, instr
, op
, dst
);
714 emit_sopc_instruction(ctx
, instr
, op
, dst
);
717 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
719 Builder
bld(ctx
->program
, ctx
->block
);
720 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
721 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
723 assert(dst
.regClass() == bld
.lm
);
724 assert(src0
.regClass() == bld
.lm
);
725 assert(src1
.regClass() == bld
.lm
);
727 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
730 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
732 Builder
bld(ctx
->program
, ctx
->block
);
733 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
734 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
735 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
737 assert(cond
.regClass() == bld
.lm
);
739 if (dst
.type() == RegType::vgpr
) {
740 aco_ptr
<Instruction
> bcsel
;
741 if (dst
.size() == 1) {
742 then
= as_vgpr(ctx
, then
);
743 els
= as_vgpr(ctx
, els
);
745 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
746 } else if (dst
.size() == 2) {
747 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
748 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
749 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
750 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
752 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
753 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
755 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
757 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
758 nir_print_instr(&instr
->instr
, stderr
);
759 fprintf(stderr
, "\n");
764 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
765 assert(dst
.regClass() == bld
.lm
);
766 assert(then
.regClass() == bld
.lm
);
767 assert(els
.regClass() == bld
.lm
);
770 if (!ctx
->divergent_vals
[instr
->src
[0].src
.ssa
->index
]) { /* uniform condition and values in sgpr */
771 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
772 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
773 assert(dst
.size() == then
.size());
774 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
775 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
777 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
778 nir_print_instr(&instr
->instr
, stderr
);
779 fprintf(stderr
, "\n");
784 /* divergent boolean bcsel
785 * this implements bcsel on bools: dst = s0 ? s1 : s2
786 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
787 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
789 if (cond
.id() != then
.id())
790 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
792 if (cond
.id() == els
.id())
793 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
795 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
796 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
799 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
800 aco_opcode op
, uint32_t undo
)
802 /* multiply by 16777216 to handle denormals */
803 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
804 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
805 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
806 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
807 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
809 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
811 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
814 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
816 if (ctx
->block
->fp_mode
.denorm32
== 0) {
817 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
821 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
824 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
826 if (ctx
->block
->fp_mode
.denorm32
== 0) {
827 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
831 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
834 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
836 if (ctx
->block
->fp_mode
.denorm32
== 0) {
837 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
841 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
844 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
846 if (ctx
->block
->fp_mode
.denorm32
== 0) {
847 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
851 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
854 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
856 if (ctx
->options
->chip_class
>= GFX7
)
857 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
859 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
860 /* TODO: create more efficient code! */
861 if (val
.type() == RegType::sgpr
)
862 val
= as_vgpr(ctx
, val
);
864 /* Split the input value. */
865 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
866 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
868 /* Extract the exponent and compute the unbiased value. */
869 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, bld
.def(v1
), val
);
871 /* Extract the fractional part. */
872 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
873 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
875 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
876 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
878 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
879 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
880 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
881 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
882 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
884 /* Get the sign bit. */
885 Temp sign
= bld
.vop2(aco_opcode::v_ashr_i32
, bld
.def(v1
), Operand(31u), val_hi
);
887 /* Decide the operation to apply depending on the unbiased exponent. */
888 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
889 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
890 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
891 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
892 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
893 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
895 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
898 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
900 if (ctx
->options
->chip_class
>= GFX7
)
901 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
903 /* GFX6 doesn't support V_FLOOR_F64, lower it. */
904 Temp src0
= as_vgpr(ctx
, val
);
906 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
907 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
909 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
910 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
911 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
913 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
914 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
915 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
916 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
918 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
919 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
921 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
923 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
924 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
926 return add
->definitions
[0].getTemp();
929 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
931 if (!instr
->dest
.dest
.is_ssa
) {
932 fprintf(stderr
, "nir alu dst not in ssa: ");
933 nir_print_instr(&instr
->instr
, stderr
);
934 fprintf(stderr
, "\n");
937 Builder
bld(ctx
->program
, ctx
->block
);
938 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
943 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
944 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
945 for (unsigned i
= 0; i
< num
; ++i
)
946 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
948 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
949 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
950 for (unsigned i
= 0; i
< num
; ++i
)
951 vec
->operands
[i
] = Operand
{elems
[i
]};
952 vec
->definitions
[0] = Definition(dst
);
953 ctx
->block
->instructions
.emplace_back(std::move(vec
));
954 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
956 // TODO: that is a bit suboptimal..
957 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
958 for (unsigned i
= 0; i
< num
- 1; ++i
)
959 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
960 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
961 for (unsigned i
= 0; i
< num
; ++i
) {
962 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
964 elems
[bit
/ 32] = elems
[i
];
966 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
967 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
968 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
972 bld
.copy(Definition(dst
), elems
[0]);
974 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
979 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
980 aco_ptr
<Instruction
> mov
;
981 if (dst
.type() == RegType::sgpr
) {
982 if (src
.type() == RegType::vgpr
)
983 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
984 else if (src
.regClass() == s1
)
985 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
986 else if (src
.regClass() == s2
)
987 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
989 unreachable("wrong src register class for nir_op_imov");
990 } else if (dst
.regClass() == v1
) {
991 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
992 } else if (dst
.regClass() == v2
) {
993 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
995 nir_print_instr(&instr
->instr
, stderr
);
996 unreachable("Should have been lowered to scalar.");
1001 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1002 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1003 assert(src
.regClass() == bld
.lm
);
1004 assert(dst
.regClass() == bld
.lm
);
1005 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1006 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1007 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1008 } else if (dst
.regClass() == v1
) {
1009 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1010 } else if (dst
.type() == RegType::sgpr
) {
1011 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1012 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1014 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1015 nir_print_instr(&instr
->instr
, stderr
);
1016 fprintf(stderr
, "\n");
1021 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1022 if (dst
.regClass() == v1
) {
1023 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1024 } else if (dst
.regClass() == s1
) {
1025 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1026 } else if (dst
.size() == 2) {
1027 Temp src0
= bld
.tmp(dst
.type(), 1);
1028 Temp src1
= bld
.tmp(dst
.type(), 1);
1029 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1031 if (dst
.regClass() == s2
) {
1032 Temp carry
= bld
.tmp(s1
);
1033 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1034 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1035 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1037 Temp lower
= bld
.tmp(v1
);
1038 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1039 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1040 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1043 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1044 nir_print_instr(&instr
->instr
, stderr
);
1045 fprintf(stderr
, "\n");
1050 if (dst
.regClass() == s1
) {
1051 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1052 } else if (dst
.regClass() == v1
) {
1053 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1054 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1056 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1057 nir_print_instr(&instr
->instr
, stderr
);
1058 fprintf(stderr
, "\n");
1062 case nir_op_isign
: {
1063 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1064 if (dst
.regClass() == s1
) {
1065 Temp tmp
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
1066 Temp gtz
= bld
.sopc(aco_opcode::s_cmp_gt_i32
, bld
.def(s1
, scc
), src
, Operand(0u));
1067 bld
.sop2(aco_opcode::s_add_i32
, Definition(dst
), bld
.def(s1
, scc
), gtz
, tmp
);
1068 } else if (dst
.regClass() == s2
) {
1069 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1071 if (ctx
->program
->chip_class
>= GFX8
)
1072 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1074 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1075 /* SCC gets zero-extended to 64 bit */
1076 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1077 } else if (dst
.regClass() == v1
) {
1078 Temp tmp
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
1079 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1080 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(1u), tmp
, gtz
);
1081 } else if (dst
.regClass() == v2
) {
1082 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1083 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1084 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1085 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1086 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1087 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1089 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1090 nir_print_instr(&instr
->instr
, stderr
);
1091 fprintf(stderr
, "\n");
1096 if (dst
.regClass() == v1
) {
1097 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1098 } else if (dst
.regClass() == s1
) {
1099 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1101 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1102 nir_print_instr(&instr
->instr
, stderr
);
1103 fprintf(stderr
, "\n");
1108 if (dst
.regClass() == v1
) {
1109 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1110 } else if (dst
.regClass() == s1
) {
1111 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1113 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1114 nir_print_instr(&instr
->instr
, stderr
);
1115 fprintf(stderr
, "\n");
1120 if (dst
.regClass() == v1
) {
1121 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1122 } else if (dst
.regClass() == s1
) {
1123 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1125 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1126 nir_print_instr(&instr
->instr
, stderr
);
1127 fprintf(stderr
, "\n");
1132 if (dst
.regClass() == v1
) {
1133 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1134 } else if (dst
.regClass() == s1
) {
1135 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1137 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1138 nir_print_instr(&instr
->instr
, stderr
);
1139 fprintf(stderr
, "\n");
1144 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1145 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1146 } else if (dst
.regClass() == v1
) {
1147 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1148 } else if (dst
.regClass() == s1
) {
1149 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1150 } else if (dst
.regClass() == s2
) {
1151 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1153 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1154 nir_print_instr(&instr
->instr
, stderr
);
1155 fprintf(stderr
, "\n");
1160 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1161 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1162 } else if (dst
.regClass() == v1
) {
1163 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1164 } else if (dst
.regClass() == s1
) {
1165 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1166 } else if (dst
.regClass() == s2
) {
1167 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1169 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1170 nir_print_instr(&instr
->instr
, stderr
);
1171 fprintf(stderr
, "\n");
1176 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1177 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1178 } else if (dst
.regClass() == v1
) {
1179 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1180 } else if (dst
.regClass() == s1
) {
1181 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1182 } else if (dst
.regClass() == s2
) {
1183 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1185 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1186 nir_print_instr(&instr
->instr
, stderr
);
1187 fprintf(stderr
, "\n");
1192 if (dst
.regClass() == v1
) {
1193 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1194 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1195 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1196 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1197 } else if (dst
.regClass() == v2
) {
1198 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1199 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1200 } else if (dst
.regClass() == s2
) {
1201 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1202 } else if (dst
.regClass() == s1
) {
1203 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1205 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1206 nir_print_instr(&instr
->instr
, stderr
);
1207 fprintf(stderr
, "\n");
1212 if (dst
.regClass() == v1
) {
1213 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1214 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1215 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1216 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1217 } else if (dst
.regClass() == v2
) {
1218 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1219 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1220 } else if (dst
.regClass() == s1
) {
1221 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1222 } else if (dst
.regClass() == s2
) {
1223 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1225 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1226 nir_print_instr(&instr
->instr
, stderr
);
1227 fprintf(stderr
, "\n");
1232 if (dst
.regClass() == v1
) {
1233 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1234 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1235 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1236 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1237 } else if (dst
.regClass() == v2
) {
1238 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1239 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1240 } else if (dst
.regClass() == s1
) {
1241 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1242 } else if (dst
.regClass() == s2
) {
1243 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1245 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1246 nir_print_instr(&instr
->instr
, stderr
);
1247 fprintf(stderr
, "\n");
1251 case nir_op_find_lsb
: {
1252 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1253 if (src
.regClass() == s1
) {
1254 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1255 } else if (src
.regClass() == v1
) {
1256 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1257 } else if (src
.regClass() == s2
) {
1258 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1260 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1261 nir_print_instr(&instr
->instr
, stderr
);
1262 fprintf(stderr
, "\n");
1266 case nir_op_ufind_msb
:
1267 case nir_op_ifind_msb
: {
1268 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1269 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1270 aco_opcode op
= src
.regClass() == s2
?
1271 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1272 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1273 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1275 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1276 Operand(src
.size() * 32u - 1u), msb_rev
);
1277 Temp msb
= sub
.def(0).getTemp();
1278 Temp carry
= sub
.def(1).getTemp();
1280 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1281 } else if (src
.regClass() == v1
) {
1282 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1283 Temp msb_rev
= bld
.tmp(v1
);
1284 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1285 Temp msb
= bld
.tmp(v1
);
1286 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1287 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1289 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1290 nir_print_instr(&instr
->instr
, stderr
);
1291 fprintf(stderr
, "\n");
1295 case nir_op_bitfield_reverse
: {
1296 if (dst
.regClass() == s1
) {
1297 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1298 } else if (dst
.regClass() == v1
) {
1299 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1301 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1302 nir_print_instr(&instr
->instr
, stderr
);
1303 fprintf(stderr
, "\n");
1308 if (dst
.regClass() == s1
) {
1309 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1313 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1314 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1315 if (dst
.regClass() == v1
) {
1316 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1320 assert(src0
.size() == 2 && src1
.size() == 2);
1321 Temp src00
= bld
.tmp(src0
.type(), 1);
1322 Temp src01
= bld
.tmp(dst
.type(), 1);
1323 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1324 Temp src10
= bld
.tmp(src1
.type(), 1);
1325 Temp src11
= bld
.tmp(dst
.type(), 1);
1326 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1328 if (dst
.regClass() == s2
) {
1329 Temp carry
= bld
.tmp(s1
);
1330 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1331 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1332 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1333 } else if (dst
.regClass() == v2
) {
1334 Temp dst0
= bld
.tmp(v1
);
1335 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1336 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1337 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1339 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1340 nir_print_instr(&instr
->instr
, stderr
);
1341 fprintf(stderr
, "\n");
1345 case nir_op_uadd_sat
: {
1346 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1347 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1348 if (dst
.regClass() == s1
) {
1349 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1350 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1352 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1353 } else if (dst
.regClass() == v1
) {
1354 if (ctx
->options
->chip_class
>= GFX9
) {
1355 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1356 add
->operands
[0] = Operand(src0
);
1357 add
->operands
[1] = Operand(src1
);
1358 add
->definitions
[0] = Definition(dst
);
1360 ctx
->block
->instructions
.emplace_back(std::move(add
));
1362 if (src1
.regClass() != v1
)
1363 std::swap(src0
, src1
);
1364 assert(src1
.regClass() == v1
);
1365 Temp tmp
= bld
.tmp(v1
);
1366 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1367 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1370 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1371 nir_print_instr(&instr
->instr
, stderr
);
1372 fprintf(stderr
, "\n");
1376 case nir_op_uadd_carry
: {
1377 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1378 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1379 if (dst
.regClass() == s1
) {
1380 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1383 if (dst
.regClass() == v1
) {
1384 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1385 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1389 Temp src00
= bld
.tmp(src0
.type(), 1);
1390 Temp src01
= bld
.tmp(dst
.type(), 1);
1391 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1392 Temp src10
= bld
.tmp(src1
.type(), 1);
1393 Temp src11
= bld
.tmp(dst
.type(), 1);
1394 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1395 if (dst
.regClass() == s2
) {
1396 Temp carry
= bld
.tmp(s1
);
1397 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1398 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1399 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1400 } else if (dst
.regClass() == v2
) {
1401 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1402 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1403 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1404 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1406 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1407 nir_print_instr(&instr
->instr
, stderr
);
1408 fprintf(stderr
, "\n");
1413 if (dst
.regClass() == s1
) {
1414 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1418 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1419 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1420 if (dst
.regClass() == v1
) {
1421 bld
.vsub32(Definition(dst
), src0
, src1
);
1425 Temp src00
= bld
.tmp(src0
.type(), 1);
1426 Temp src01
= bld
.tmp(dst
.type(), 1);
1427 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1428 Temp src10
= bld
.tmp(src1
.type(), 1);
1429 Temp src11
= bld
.tmp(dst
.type(), 1);
1430 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1431 if (dst
.regClass() == s2
) {
1432 Temp carry
= bld
.tmp(s1
);
1433 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1434 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1435 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1436 } else if (dst
.regClass() == v2
) {
1437 Temp lower
= bld
.tmp(v1
);
1438 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1439 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1440 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1442 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1443 nir_print_instr(&instr
->instr
, stderr
);
1444 fprintf(stderr
, "\n");
1448 case nir_op_usub_borrow
: {
1449 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1450 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1451 if (dst
.regClass() == s1
) {
1452 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1454 } else if (dst
.regClass() == v1
) {
1455 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1456 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1460 Temp src00
= bld
.tmp(src0
.type(), 1);
1461 Temp src01
= bld
.tmp(dst
.type(), 1);
1462 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1463 Temp src10
= bld
.tmp(src1
.type(), 1);
1464 Temp src11
= bld
.tmp(dst
.type(), 1);
1465 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1466 if (dst
.regClass() == s2
) {
1467 Temp borrow
= bld
.tmp(s1
);
1468 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1469 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1470 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1471 } else if (dst
.regClass() == v2
) {
1472 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1473 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1474 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1475 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1477 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1478 nir_print_instr(&instr
->instr
, stderr
);
1479 fprintf(stderr
, "\n");
1484 if (dst
.regClass() == v1
) {
1485 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1486 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1487 } else if (dst
.regClass() == s1
) {
1488 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1490 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1491 nir_print_instr(&instr
->instr
, stderr
);
1492 fprintf(stderr
, "\n");
1496 case nir_op_umul_high
: {
1497 if (dst
.regClass() == v1
) {
1498 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1499 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1500 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1501 } else if (dst
.regClass() == s1
) {
1502 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1503 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1504 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1506 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1507 nir_print_instr(&instr
->instr
, stderr
);
1508 fprintf(stderr
, "\n");
1512 case nir_op_imul_high
: {
1513 if (dst
.regClass() == v1
) {
1514 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1515 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1516 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1517 } else if (dst
.regClass() == s1
) {
1518 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1519 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1520 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1522 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1523 nir_print_instr(&instr
->instr
, stderr
);
1524 fprintf(stderr
, "\n");
1529 if (dst
.size() == 1) {
1530 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1531 } else if (dst
.size() == 2) {
1532 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]),
1533 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1535 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1536 nir_print_instr(&instr
->instr
, stderr
);
1537 fprintf(stderr
, "\n");
1542 if (dst
.size() == 1) {
1543 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1544 } else if (dst
.size() == 2) {
1545 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]),
1546 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1548 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1549 nir_print_instr(&instr
->instr
, stderr
);
1550 fprintf(stderr
, "\n");
1555 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1556 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1557 if (dst
.size() == 1) {
1558 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1559 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1561 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1562 } else if (dst
.size() == 2) {
1563 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1564 get_alu_src(ctx
, instr
->src
[0]),
1565 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1566 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1569 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1570 nir_print_instr(&instr
->instr
, stderr
);
1571 fprintf(stderr
, "\n");
1576 if (dst
.size() == 1) {
1577 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1578 } else if (dst
.size() == 2) {
1579 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1580 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
),
1581 get_alu_src(ctx
, instr
->src
[0]),
1582 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1583 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1585 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
),
1586 get_alu_src(ctx
, instr
->src
[0]),
1587 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1590 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1591 nir_print_instr(&instr
->instr
, stderr
);
1592 fprintf(stderr
, "\n");
1597 if (dst
.size() == 1) {
1598 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1599 } else if (dst
.size() == 2) {
1600 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1601 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
),
1602 get_alu_src(ctx
, instr
->src
[0]),
1603 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1604 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1606 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
),
1607 get_alu_src(ctx
, instr
->src
[0]),
1608 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1611 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1612 nir_print_instr(&instr
->instr
, stderr
);
1613 fprintf(stderr
, "\n");
1617 case nir_op_fmax3
: {
1618 if (dst
.size() == 1) {
1619 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1621 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1622 nir_print_instr(&instr
->instr
, stderr
);
1623 fprintf(stderr
, "\n");
1627 case nir_op_fmin3
: {
1628 if (dst
.size() == 1) {
1629 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1631 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1632 nir_print_instr(&instr
->instr
, stderr
);
1633 fprintf(stderr
, "\n");
1637 case nir_op_fmed3
: {
1638 if (dst
.size() == 1) {
1639 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1641 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1642 nir_print_instr(&instr
->instr
, stderr
);
1643 fprintf(stderr
, "\n");
1647 case nir_op_umax3
: {
1648 if (dst
.size() == 1) {
1649 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1651 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1652 nir_print_instr(&instr
->instr
, stderr
);
1653 fprintf(stderr
, "\n");
1657 case nir_op_umin3
: {
1658 if (dst
.size() == 1) {
1659 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1661 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1662 nir_print_instr(&instr
->instr
, stderr
);
1663 fprintf(stderr
, "\n");
1667 case nir_op_umed3
: {
1668 if (dst
.size() == 1) {
1669 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1671 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1672 nir_print_instr(&instr
->instr
, stderr
);
1673 fprintf(stderr
, "\n");
1677 case nir_op_imax3
: {
1678 if (dst
.size() == 1) {
1679 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1681 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1682 nir_print_instr(&instr
->instr
, stderr
);
1683 fprintf(stderr
, "\n");
1687 case nir_op_imin3
: {
1688 if (dst
.size() == 1) {
1689 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1691 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1692 nir_print_instr(&instr
->instr
, stderr
);
1693 fprintf(stderr
, "\n");
1697 case nir_op_imed3
: {
1698 if (dst
.size() == 1) {
1699 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1701 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1702 nir_print_instr(&instr
->instr
, stderr
);
1703 fprintf(stderr
, "\n");
1707 case nir_op_cube_face_coord
: {
1708 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1709 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1710 emit_extract_vector(ctx
, in
, 1, v1
),
1711 emit_extract_vector(ctx
, in
, 2, v1
) };
1712 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1713 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1714 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1715 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1716 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1717 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1718 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1721 case nir_op_cube_face_index
: {
1722 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1723 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1724 emit_extract_vector(ctx
, in
, 1, v1
),
1725 emit_extract_vector(ctx
, in
, 2, v1
) };
1726 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1729 case nir_op_bcsel
: {
1730 emit_bcsel(ctx
, instr
, dst
);
1734 if (dst
.size() == 1) {
1735 emit_rsq(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1736 } else if (dst
.size() == 2) {
1737 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1739 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1740 nir_print_instr(&instr
->instr
, stderr
);
1741 fprintf(stderr
, "\n");
1746 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1747 if (dst
.size() == 1) {
1748 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1749 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1750 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1751 } else if (dst
.size() == 2) {
1752 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1753 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1754 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1755 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1756 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1757 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1759 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1760 nir_print_instr(&instr
->instr
, stderr
);
1761 fprintf(stderr
, "\n");
1766 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1767 if (dst
.size() == 1) {
1768 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1769 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1770 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1771 } else if (dst
.size() == 2) {
1772 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1773 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1774 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1775 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1776 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1777 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1779 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1780 nir_print_instr(&instr
->instr
, stderr
);
1781 fprintf(stderr
, "\n");
1786 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1787 if (dst
.size() == 1) {
1788 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1789 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1790 // TODO: confirm that this holds under any circumstances
1791 } else if (dst
.size() == 2) {
1792 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1793 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1796 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1797 nir_print_instr(&instr
->instr
, stderr
);
1798 fprintf(stderr
, "\n");
1802 case nir_op_flog2
: {
1803 if (dst
.size() == 1) {
1804 emit_log2(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1806 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1807 nir_print_instr(&instr
->instr
, stderr
);
1808 fprintf(stderr
, "\n");
1813 if (dst
.size() == 1) {
1814 emit_rcp(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1815 } else if (dst
.size() == 2) {
1816 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1818 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1819 nir_print_instr(&instr
->instr
, stderr
);
1820 fprintf(stderr
, "\n");
1824 case nir_op_fexp2
: {
1825 if (dst
.size() == 1) {
1826 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1828 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1829 nir_print_instr(&instr
->instr
, stderr
);
1830 fprintf(stderr
, "\n");
1834 case nir_op_fsqrt
: {
1835 if (dst
.size() == 1) {
1836 emit_sqrt(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1837 } else if (dst
.size() == 2) {
1838 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1840 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1841 nir_print_instr(&instr
->instr
, stderr
);
1842 fprintf(stderr
, "\n");
1846 case nir_op_ffract
: {
1847 if (dst
.size() == 1) {
1848 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1849 } else if (dst
.size() == 2) {
1850 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1852 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1853 nir_print_instr(&instr
->instr
, stderr
);
1854 fprintf(stderr
, "\n");
1858 case nir_op_ffloor
: {
1859 if (dst
.size() == 1) {
1860 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
1861 } else if (dst
.size() == 2) {
1862 emit_floor_f64(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1864 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1865 nir_print_instr(&instr
->instr
, stderr
);
1866 fprintf(stderr
, "\n");
1870 case nir_op_fceil
: {
1871 if (dst
.size() == 1) {
1872 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
1873 } else if (dst
.size() == 2) {
1874 if (ctx
->options
->chip_class
>= GFX7
) {
1875 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
1877 /* GFX6 doesn't support V_CEIL_F64, lower it. */
1878 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1880 /* trunc = trunc(src0)
1881 * if (src0 > 0.0 && src0 != trunc)
1884 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
1885 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
1886 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
1887 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
1888 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
1889 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
1890 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
1893 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1894 nir_print_instr(&instr
->instr
, stderr
);
1895 fprintf(stderr
, "\n");
1899 case nir_op_ftrunc
: {
1900 if (dst
.size() == 1) {
1901 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
1902 } else if (dst
.size() == 2) {
1903 emit_trunc_f64(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1905 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1906 nir_print_instr(&instr
->instr
, stderr
);
1907 fprintf(stderr
, "\n");
1911 case nir_op_fround_even
: {
1912 if (dst
.size() == 1) {
1913 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
1914 } else if (dst
.size() == 2) {
1915 if (ctx
->options
->chip_class
>= GFX7
) {
1916 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
1918 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
1919 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1921 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
1922 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
1924 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
1925 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
1926 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
1927 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
1928 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
1929 tmp
= sub
->definitions
[0].getTemp();
1931 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
1932 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
1933 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
1934 Temp cond
= vop3
->definitions
[0].getTemp();
1936 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
1937 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
1938 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
1939 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
1941 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1944 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1945 nir_print_instr(&instr
->instr
, stderr
);
1946 fprintf(stderr
, "\n");
1952 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1953 aco_ptr
<Instruction
> norm
;
1954 if (dst
.size() == 1) {
1955 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
1956 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, as_vgpr(ctx
, src
));
1958 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
1959 if (ctx
->options
->chip_class
< GFX9
)
1960 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
1962 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
1963 bld
.vop1(opcode
, Definition(dst
), tmp
);
1965 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1966 nir_print_instr(&instr
->instr
, stderr
);
1967 fprintf(stderr
, "\n");
1971 case nir_op_ldexp
: {
1972 if (dst
.size() == 1) {
1973 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
),
1974 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0])),
1975 get_alu_src(ctx
, instr
->src
[1]));
1976 } else if (dst
.size() == 2) {
1977 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
),
1978 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0])),
1979 get_alu_src(ctx
, instr
->src
[1]));
1981 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1982 nir_print_instr(&instr
->instr
, stderr
);
1983 fprintf(stderr
, "\n");
1987 case nir_op_frexp_sig
: {
1988 if (dst
.size() == 1) {
1989 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
),
1990 get_alu_src(ctx
, instr
->src
[0]));
1991 } else if (dst
.size() == 2) {
1992 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
),
1993 get_alu_src(ctx
, instr
->src
[0]));
1995 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1996 nir_print_instr(&instr
->instr
, stderr
);
1997 fprintf(stderr
, "\n");
2001 case nir_op_frexp_exp
: {
2002 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2003 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
),
2004 get_alu_src(ctx
, instr
->src
[0]));
2005 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2006 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
),
2007 get_alu_src(ctx
, instr
->src
[0]));
2009 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2010 nir_print_instr(&instr
->instr
, stderr
);
2011 fprintf(stderr
, "\n");
2015 case nir_op_fsign
: {
2016 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2017 if (dst
.size() == 1) {
2018 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2019 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2020 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2021 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2022 } else if (dst
.size() == 2) {
2023 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2024 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2025 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2027 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2028 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2029 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2031 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2033 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2034 nir_print_instr(&instr
->instr
, stderr
);
2035 fprintf(stderr
, "\n");
2040 case nir_op_f2f16_rtne
: {
2041 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2042 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2043 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2044 src
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2045 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2048 case nir_op_f2f16_rtz
: {
2049 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2050 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2051 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2052 src
= bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, bld
.def(v1
), src
, Operand(0u));
2053 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2056 case nir_op_f2f32
: {
2057 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2058 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2059 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2060 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2062 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2063 nir_print_instr(&instr
->instr
, stderr
);
2064 fprintf(stderr
, "\n");
2068 case nir_op_f2f64
: {
2069 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2070 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2071 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2072 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2075 case nir_op_i2f32
: {
2076 assert(dst
.size() == 1);
2077 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_i32
, dst
);
2080 case nir_op_i2f64
: {
2081 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2082 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_i32
, dst
);
2083 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2084 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2085 RegClass rc
= RegClass(src
.type(), 1);
2086 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2087 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2088 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2089 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2090 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2091 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2094 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2095 nir_print_instr(&instr
->instr
, stderr
);
2096 fprintf(stderr
, "\n");
2100 case nir_op_u2f32
: {
2101 assert(dst
.size() == 1);
2102 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_u32
, dst
);
2105 case nir_op_u2f64
: {
2106 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2107 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_u32
, dst
);
2108 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2109 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2110 RegClass rc
= RegClass(src
.type(), 1);
2111 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2112 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2113 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2114 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2115 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2116 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2118 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2119 nir_print_instr(&instr
->instr
, stderr
);
2120 fprintf(stderr
, "\n");
2124 case nir_op_f2i16
: {
2125 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2126 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2127 src
= bld
.vop1(aco_opcode::v_cvt_i16_f16
, bld
.def(v1
), src
);
2128 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2129 src
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
);
2131 src
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
);
2133 if (dst
.type() == RegType::vgpr
)
2134 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2136 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2139 case nir_op_f2u16
: {
2140 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2141 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2142 src
= bld
.vop1(aco_opcode::v_cvt_u16_f16
, bld
.def(v1
), src
);
2143 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2144 src
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
);
2146 src
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
);
2148 if (dst
.type() == RegType::vgpr
)
2149 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2151 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2154 case nir_op_f2i32
: {
2155 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2156 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2157 if (dst
.type() == RegType::vgpr
)
2158 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), src
);
2160 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2161 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
));
2163 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2164 if (dst
.type() == RegType::vgpr
)
2165 bld
.vop1(aco_opcode::v_cvt_i32_f64
, Definition(dst
), src
);
2167 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2168 bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
));
2171 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2172 nir_print_instr(&instr
->instr
, stderr
);
2173 fprintf(stderr
, "\n");
2177 case nir_op_f2u32
: {
2178 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2179 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2180 if (dst
.type() == RegType::vgpr
)
2181 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), src
);
2183 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2184 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
));
2186 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2187 if (dst
.type() == RegType::vgpr
)
2188 bld
.vop1(aco_opcode::v_cvt_u32_f64
, Definition(dst
), src
);
2190 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2191 bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
));
2194 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2195 nir_print_instr(&instr
->instr
, stderr
);
2196 fprintf(stderr
, "\n");
2200 case nir_op_f2i64
: {
2201 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2202 if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::vgpr
) {
2203 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2204 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2205 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2206 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2207 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2208 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2209 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2210 Temp new_exponent
= bld
.tmp(v1
);
2211 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2212 if (ctx
->program
->chip_class
>= GFX8
)
2213 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2215 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2216 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2217 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2218 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2219 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2220 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2221 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2222 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2223 Temp new_lower
= bld
.tmp(v1
);
2224 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2225 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2226 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2228 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::sgpr
) {
2229 if (src
.type() == RegType::vgpr
)
2230 src
= bld
.as_uniform(src
);
2231 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2232 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2233 exponent
= bld
.sop2(aco_opcode::s_max_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2234 exponent
= bld
.sop2(aco_opcode::s_min_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2235 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2236 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2237 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2238 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2239 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2240 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2241 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2242 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2243 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2244 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2245 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2246 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2247 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2248 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2249 Temp borrow
= bld
.tmp(s1
);
2250 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2251 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2252 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2254 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2255 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2256 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2257 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2258 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2259 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2260 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2261 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2262 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2263 if (dst
.type() == RegType::sgpr
) {
2264 lower
= bld
.as_uniform(lower
);
2265 upper
= bld
.as_uniform(upper
);
2267 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2270 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2271 nir_print_instr(&instr
->instr
, stderr
);
2272 fprintf(stderr
, "\n");
2276 case nir_op_f2u64
: {
2277 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2278 if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::vgpr
) {
2279 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2280 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2281 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2282 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2283 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2284 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2285 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2286 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2287 Temp new_exponent
= bld
.tmp(v1
);
2288 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2289 if (ctx
->program
->chip_class
>= GFX8
)
2290 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2292 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2293 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2294 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2295 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2296 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2297 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2298 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2299 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2301 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::sgpr
) {
2302 if (src
.type() == RegType::vgpr
)
2303 src
= bld
.as_uniform(src
);
2304 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2305 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2306 exponent
= bld
.sop2(aco_opcode::s_max_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2307 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2308 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2309 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2310 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2311 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2312 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2313 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2314 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2315 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2316 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2317 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2318 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2319 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2320 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2321 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2323 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2324 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2325 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2326 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2327 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2328 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2329 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2330 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2331 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2332 if (dst
.type() == RegType::sgpr
) {
2333 lower
= bld
.as_uniform(lower
);
2334 upper
= bld
.as_uniform(upper
);
2336 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2339 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2340 nir_print_instr(&instr
->instr
, stderr
);
2341 fprintf(stderr
, "\n");
2345 case nir_op_b2f32
: {
2346 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2347 assert(src
.regClass() == bld
.lm
);
2349 if (dst
.regClass() == s1
) {
2350 src
= bool_to_scalar_condition(ctx
, src
);
2351 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2352 } else if (dst
.regClass() == v1
) {
2353 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2355 unreachable("Wrong destination register class for nir_op_b2f32.");
2359 case nir_op_b2f64
: {
2360 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2361 assert(src
.regClass() == bld
.lm
);
2363 if (dst
.regClass() == s2
) {
2364 src
= bool_to_scalar_condition(ctx
, src
);
2365 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2366 } else if (dst
.regClass() == v2
) {
2367 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2368 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2369 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2371 unreachable("Wrong destination register class for nir_op_b2f64.");
2377 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2378 /* we can actually just say dst = src */
2379 if (src
.regClass() == s1
)
2380 bld
.copy(Definition(dst
), src
);
2382 emit_extract_vector(ctx
, src
, 0, dst
);
2385 case nir_op_i2i16
: {
2386 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2387 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2388 if (dst
.regClass() == s1
) {
2389 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(dst
), Operand(src
));
2391 assert(src
.regClass() == v1b
);
2392 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2393 sdwa
->operands
[0] = Operand(src
);
2394 sdwa
->definitions
[0] = Definition(dst
);
2395 sdwa
->sel
[0] = sdwa_sbyte
;
2396 sdwa
->dst_sel
= sdwa_sword
;
2397 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2400 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2401 /* we can actually just say dst = src */
2402 if (src
.regClass() == s1
)
2403 bld
.copy(Definition(dst
), src
);
2405 emit_extract_vector(ctx
, src
, 0, dst
);
2409 case nir_op_u2u16
: {
2410 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2411 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2412 if (dst
.regClass() == s1
)
2413 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFu
), src
);
2415 assert(src
.regClass() == v1b
);
2416 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2417 sdwa
->operands
[0] = Operand(src
);
2418 sdwa
->definitions
[0] = Definition(dst
);
2419 sdwa
->sel
[0] = sdwa_ubyte
;
2420 sdwa
->dst_sel
= sdwa_uword
;
2421 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2424 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2425 /* we can actually just say dst = src */
2426 if (src
.regClass() == s1
)
2427 bld
.copy(Definition(dst
), src
);
2429 emit_extract_vector(ctx
, src
, 0, dst
);
2433 case nir_op_i2i32
: {
2434 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2435 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2436 if (dst
.regClass() == s1
) {
2437 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(dst
), Operand(src
));
2439 assert(src
.regClass() == v1b
);
2440 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2441 sdwa
->operands
[0] = Operand(src
);
2442 sdwa
->definitions
[0] = Definition(dst
);
2443 sdwa
->sel
[0] = sdwa_sbyte
;
2444 sdwa
->dst_sel
= sdwa_sdword
;
2445 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2447 } else if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2448 if (dst
.regClass() == s1
) {
2449 bld
.sop1(aco_opcode::s_sext_i32_i16
, Definition(dst
), Operand(src
));
2451 assert(src
.regClass() == v2b
);
2452 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2453 sdwa
->operands
[0] = Operand(src
);
2454 sdwa
->definitions
[0] = Definition(dst
);
2455 sdwa
->sel
[0] = sdwa_sword
;
2456 sdwa
->dst_sel
= sdwa_udword
;
2457 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2459 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2460 /* we can actually just say dst = src, as it would map the lower register */
2461 emit_extract_vector(ctx
, src
, 0, dst
);
2463 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2464 nir_print_instr(&instr
->instr
, stderr
);
2465 fprintf(stderr
, "\n");
2469 case nir_op_u2u32
: {
2470 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2471 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2472 if (dst
.regClass() == s1
)
2473 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFu
), src
);
2475 assert(src
.regClass() == v1b
);
2476 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2477 sdwa
->operands
[0] = Operand(src
);
2478 sdwa
->definitions
[0] = Definition(dst
);
2479 sdwa
->sel
[0] = sdwa_ubyte
;
2480 sdwa
->dst_sel
= sdwa_udword
;
2481 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2483 } else if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2484 if (dst
.regClass() == s1
) {
2485 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFFFu
), src
);
2487 assert(src
.regClass() == v2b
);
2488 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2489 sdwa
->operands
[0] = Operand(src
);
2490 sdwa
->definitions
[0] = Definition(dst
);
2491 sdwa
->sel
[0] = sdwa_uword
;
2492 sdwa
->dst_sel
= sdwa_udword
;
2493 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2495 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2496 /* we can actually just say dst = src, as it would map the lower register */
2497 emit_extract_vector(ctx
, src
, 0, dst
);
2499 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2500 nir_print_instr(&instr
->instr
, stderr
);
2501 fprintf(stderr
, "\n");
2505 case nir_op_i2i64
: {
2506 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2507 if (src
.regClass() == s1
) {
2508 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2509 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, high
);
2510 } else if (src
.regClass() == v1
) {
2511 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2512 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, high
);
2514 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2515 nir_print_instr(&instr
->instr
, stderr
);
2516 fprintf(stderr
, "\n");
2520 case nir_op_u2u64
: {
2521 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2522 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2523 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, Operand(0u));
2525 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2526 nir_print_instr(&instr
->instr
, stderr
);
2527 fprintf(stderr
, "\n");
2532 case nir_op_b2i32
: {
2533 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2534 assert(src
.regClass() == bld
.lm
);
2536 if (dst
.regClass() == s1
) {
2537 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2538 bool_to_scalar_condition(ctx
, src
, dst
);
2539 } else if (dst
.regClass() == v1
) {
2540 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2542 unreachable("Invalid register class for b2i32");
2548 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2549 assert(dst
.regClass() == bld
.lm
);
2551 if (src
.type() == RegType::vgpr
) {
2552 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2553 assert(dst
.regClass() == bld
.lm
);
2554 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2555 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2557 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2559 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2560 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2562 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2563 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2565 bool_to_vector_condition(ctx
, tmp
, dst
);
2569 case nir_op_pack_64_2x32_split
: {
2570 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2571 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2573 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2576 case nir_op_unpack_64_2x32_split_x
:
2577 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2579 case nir_op_unpack_64_2x32_split_y
:
2580 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2582 case nir_op_unpack_32_2x16_split_x
:
2583 if (dst
.type() == RegType::vgpr
) {
2584 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2586 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2589 case nir_op_unpack_32_2x16_split_y
:
2590 if (dst
.type() == RegType::vgpr
) {
2591 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2593 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2596 case nir_op_pack_32_2x16_split
: {
2597 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2598 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2599 if (dst
.regClass() == v1
) {
2600 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2602 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2603 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2604 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2608 case nir_op_pack_half_2x16
: {
2609 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2611 if (dst
.regClass() == v1
) {
2612 Temp src0
= bld
.tmp(v1
);
2613 Temp src1
= bld
.tmp(v1
);
2614 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2615 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2616 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2618 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2619 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2620 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2622 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2623 nir_print_instr(&instr
->instr
, stderr
);
2624 fprintf(stderr
, "\n");
2628 case nir_op_unpack_half_2x16_split_x
: {
2629 if (dst
.regClass() == v1
) {
2630 Builder
bld(ctx
->program
, ctx
->block
);
2631 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2633 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2634 nir_print_instr(&instr
->instr
, stderr
);
2635 fprintf(stderr
, "\n");
2639 case nir_op_unpack_half_2x16_split_y
: {
2640 if (dst
.regClass() == v1
) {
2641 Builder
bld(ctx
->program
, ctx
->block
);
2642 /* TODO: use SDWA here */
2643 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2644 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2646 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2647 nir_print_instr(&instr
->instr
, stderr
);
2648 fprintf(stderr
, "\n");
2652 case nir_op_fquantize2f16
: {
2653 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2654 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2657 if (ctx
->program
->chip_class
>= GFX8
) {
2658 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2659 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2660 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2662 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2663 * so compare the result and flush to 0 if it's smaller.
2665 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2666 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2667 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2668 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2669 cmp_res
= vop3
->definitions
[0].getTemp();
2672 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2673 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2674 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2676 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2681 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2682 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2684 if (dst
.regClass() == s1
) {
2685 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2686 } else if (dst
.regClass() == v1
) {
2687 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2689 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2690 nir_print_instr(&instr
->instr
, stderr
);
2691 fprintf(stderr
, "\n");
2695 case nir_op_bitfield_select
: {
2696 /* (mask & insert) | (~mask & base) */
2697 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2698 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2699 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2701 /* dst = (insert & bitmask) | (base & ~bitmask) */
2702 if (dst
.regClass() == s1
) {
2703 aco_ptr
<Instruction
> sop2
;
2704 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2705 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2707 if (const_insert
&& const_bitmask
) {
2708 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2710 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2711 lhs
= Operand(insert
);
2715 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2716 if (const_base
&& const_bitmask
) {
2717 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2719 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2720 rhs
= Operand(base
);
2723 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2725 } else if (dst
.regClass() == v1
) {
2726 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2727 base
= as_vgpr(ctx
, base
);
2728 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2729 insert
= as_vgpr(ctx
, insert
);
2731 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2734 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2735 nir_print_instr(&instr
->instr
, stderr
);
2736 fprintf(stderr
, "\n");
2742 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2743 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2744 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2746 if (dst
.type() == RegType::sgpr
) {
2748 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2749 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2750 if (const_offset
&& const_bits
) {
2751 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2752 extract
= Operand(const_extract
);
2756 width
= Operand(const_bits
->u32
<< 16);
2758 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2760 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2764 if (dst
.regClass() == s1
) {
2765 if (instr
->op
== nir_op_ubfe
)
2766 opcode
= aco_opcode::s_bfe_u32
;
2768 opcode
= aco_opcode::s_bfe_i32
;
2769 } else if (dst
.regClass() == s2
) {
2770 if (instr
->op
== nir_op_ubfe
)
2771 opcode
= aco_opcode::s_bfe_u64
;
2773 opcode
= aco_opcode::s_bfe_i64
;
2775 unreachable("Unsupported BFE bit size");
2778 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2782 if (dst
.regClass() == v1
) {
2783 if (instr
->op
== nir_op_ubfe
)
2784 opcode
= aco_opcode::v_bfe_u32
;
2786 opcode
= aco_opcode::v_bfe_i32
;
2788 unreachable("Unsupported BFE bit size");
2791 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2795 case nir_op_bit_count
: {
2796 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2797 if (src
.regClass() == s1
) {
2798 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2799 } else if (src
.regClass() == v1
) {
2800 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2801 } else if (src
.regClass() == v2
) {
2802 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2803 emit_extract_vector(ctx
, src
, 1, v1
),
2804 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2805 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2806 } else if (src
.regClass() == s2
) {
2807 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2809 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2810 nir_print_instr(&instr
->instr
, stderr
);
2811 fprintf(stderr
, "\n");
2816 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2820 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2824 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2828 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2832 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2836 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2840 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2841 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2843 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2844 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2848 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2849 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2851 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2852 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2856 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2860 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2865 case nir_op_fddx_fine
:
2866 case nir_op_fddy_fine
:
2867 case nir_op_fddx_coarse
:
2868 case nir_op_fddy_coarse
: {
2869 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2870 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2871 if (instr
->op
== nir_op_fddx_fine
) {
2872 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2873 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2874 } else if (instr
->op
== nir_op_fddy_fine
) {
2875 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2876 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2878 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2879 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2880 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2882 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2886 if (ctx
->program
->chip_class
>= GFX8
) {
2887 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2888 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2890 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
2891 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
2892 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
2894 emit_wqm(ctx
, tmp
, dst
, true);
2898 fprintf(stderr
, "Unknown NIR ALU instr: ");
2899 nir_print_instr(&instr
->instr
, stderr
);
2900 fprintf(stderr
, "\n");
2904 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
2906 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
2908 // TODO: we really want to have the resulting type as this would allow for 64bit literals
2909 // which get truncated the lsb if double and msb if int
2910 // for now, we only use s_mov_b64 with 64bit inline constants
2911 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
2912 assert(dst
.type() == RegType::sgpr
);
2914 Builder
bld(ctx
->program
, ctx
->block
);
2916 if (instr
->def
.bit_size
== 1) {
2917 assert(dst
.regClass() == bld
.lm
);
2918 int val
= instr
->value
[0].b
? -1 : 0;
2919 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
2920 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
2921 } else if (dst
.size() == 1) {
2922 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
2924 assert(dst
.size() != 1);
2925 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
2926 if (instr
->def
.bit_size
== 64)
2927 for (unsigned i
= 0; i
< dst
.size(); i
++)
2928 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
2930 for (unsigned i
= 0; i
< dst
.size(); i
++)
2931 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
2933 vec
->definitions
[0] = Definition(dst
);
2934 ctx
->block
->instructions
.emplace_back(std::move(vec
));
2938 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
2940 uint32_t new_mask
= 0;
2941 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
2942 if (mask
& (1u << i
))
2943 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
2947 Operand
load_lds_size_m0(isel_context
*ctx
)
2949 /* TODO: m0 does not need to be initialized on GFX9+ */
2950 Builder
bld(ctx
->program
, ctx
->block
);
2951 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
2954 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
2955 Temp address
, unsigned base_offset
, unsigned align
)
2957 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
2959 Builder
bld(ctx
->program
, ctx
->block
);
2961 Operand m
= load_lds_size_m0(ctx
);
2963 unsigned num_components
= dst
.size() * 4u / elem_size_bytes
;
2964 unsigned bytes_read
= 0;
2965 unsigned result_size
= 0;
2966 unsigned total_bytes
= num_components
* elem_size_bytes
;
2967 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> result
;
2968 bool large_ds_read
= ctx
->options
->chip_class
>= GFX7
;
2969 bool usable_read2
= ctx
->options
->chip_class
>= GFX7
;
2971 while (bytes_read
< total_bytes
) {
2972 unsigned todo
= total_bytes
- bytes_read
;
2973 bool aligned8
= bytes_read
% 8 == 0 && align
% 8 == 0;
2974 bool aligned16
= bytes_read
% 16 == 0 && align
% 16 == 0;
2976 aco_opcode op
= aco_opcode::last_opcode
;
2978 if (todo
>= 16 && aligned16
&& large_ds_read
) {
2979 op
= aco_opcode::ds_read_b128
;
2981 } else if (todo
>= 16 && aligned8
&& usable_read2
) {
2982 op
= aco_opcode::ds_read2_b64
;
2985 } else if (todo
>= 12 && aligned16
&& large_ds_read
) {
2986 op
= aco_opcode::ds_read_b96
;
2988 } else if (todo
>= 8 && aligned8
) {
2989 op
= aco_opcode::ds_read_b64
;
2991 } else if (todo
>= 8 && usable_read2
) {
2992 op
= aco_opcode::ds_read2_b32
;
2995 } else if (todo
>= 4) {
2996 op
= aco_opcode::ds_read_b32
;
3001 assert(todo
% elem_size_bytes
== 0);
3002 unsigned num_elements
= todo
/ elem_size_bytes
;
3003 unsigned offset
= base_offset
+ bytes_read
;
3004 unsigned max_offset
= read2
? 1019 : 65535;
3006 Temp address_offset
= address
;
3007 if (offset
> max_offset
) {
3008 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3009 offset
= bytes_read
;
3011 assert(offset
<= max_offset
); /* bytes_read shouldn't be large enough for this to happen */
3014 if (num_components
== 1 && dst
.type() == RegType::vgpr
)
3017 res
= bld
.tmp(RegClass(RegType::vgpr
, todo
/ 4));
3020 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
/ (todo
/ 2), (offset
/ (todo
/ 2)) + 1);
3022 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
);
3024 if (num_components
== 1) {
3025 assert(todo
== total_bytes
);
3026 if (dst
.type() == RegType::sgpr
)
3027 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), res
);
3031 if (dst
.type() == RegType::sgpr
) {
3032 Temp new_res
= bld
.tmp(RegType::sgpr
, res
.size());
3033 expand_vector(ctx
, res
, new_res
, res
.size(), (1 << res
.size()) - 1);
3037 if (num_elements
== 1) {
3038 result
[result_size
++] = res
;
3040 assert(res
!= dst
&& res
.size() % num_elements
== 0);
3041 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_elements
)};
3042 split
->operands
[0] = Operand(res
);
3043 for (unsigned i
= 0; i
< num_elements
; i
++)
3044 split
->definitions
[i
] = Definition(result
[result_size
++] = bld
.tmp(res
.type(), elem_size_bytes
/ 4));
3045 ctx
->block
->instructions
.emplace_back(std::move(split
));
3051 assert(result_size
== num_components
&& result_size
> 1);
3052 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, result_size
, 1)};
3053 for (unsigned i
= 0; i
< result_size
; i
++)
3054 vec
->operands
[i
] = Operand(result
[i
]);
3055 vec
->definitions
[0] = Definition(dst
);
3056 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3057 ctx
->allocated_vec
.emplace(dst
.id(), result
);
3062 Temp
extract_subvector(isel_context
*ctx
, Temp data
, unsigned start
, unsigned size
, RegType type
)
3064 if (start
== 0 && size
== data
.size())
3065 return type
== RegType::vgpr
? as_vgpr(ctx
, data
) : data
;
3067 unsigned size_hint
= 1;
3068 auto it
= ctx
->allocated_vec
.find(data
.id());
3069 if (it
!= ctx
->allocated_vec
.end())
3070 size_hint
= it
->second
[0].size();
3071 if (size
% size_hint
|| start
% size_hint
)
3078 for (unsigned i
= 0; i
< size
; i
++)
3079 elems
[i
] = emit_extract_vector(ctx
, data
, start
+ i
, RegClass(type
, size_hint
));
3082 return type
== RegType::vgpr
? as_vgpr(ctx
, elems
[0]) : elems
[0];
3084 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
3085 for (unsigned i
= 0; i
< size
; i
++)
3086 vec
->operands
[i
] = Operand(elems
[i
]);
3087 Temp res
= {ctx
->program
->allocateId(), RegClass(type
, size
* size_hint
)};
3088 vec
->definitions
[0] = Definition(res
);
3089 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3093 void ds_write_helper(isel_context
*ctx
, Operand m
, Temp address
, Temp data
, unsigned data_start
, unsigned total_size
, unsigned offset0
, unsigned offset1
, unsigned align
)
3095 Builder
bld(ctx
->program
, ctx
->block
);
3096 unsigned bytes_written
= 0;
3097 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3098 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3100 while (bytes_written
< total_size
* 4) {
3101 unsigned todo
= total_size
* 4 - bytes_written
;
3102 bool aligned8
= bytes_written
% 8 == 0 && align
% 8 == 0;
3103 bool aligned16
= bytes_written
% 16 == 0 && align
% 16 == 0;
3105 aco_opcode op
= aco_opcode::last_opcode
;
3106 bool write2
= false;
3108 if (todo
>= 16 && aligned16
&& large_ds_write
) {
3109 op
= aco_opcode::ds_write_b128
;
3111 } else if (todo
>= 16 && aligned8
&& usable_write2
) {
3112 op
= aco_opcode::ds_write2_b64
;
3115 } else if (todo
>= 12 && aligned16
&& large_ds_write
) {
3116 op
= aco_opcode::ds_write_b96
;
3118 } else if (todo
>= 8 && aligned8
) {
3119 op
= aco_opcode::ds_write_b64
;
3121 } else if (todo
>= 8 && usable_write2
) {
3122 op
= aco_opcode::ds_write2_b32
;
3125 } else if (todo
>= 4) {
3126 op
= aco_opcode::ds_write_b32
;
3132 unsigned offset
= offset0
+ offset1
+ bytes_written
;
3133 unsigned max_offset
= write2
? 1020 : 65535;
3134 Temp address_offset
= address
;
3135 if (offset
> max_offset
) {
3136 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(offset0
), address_offset
);
3137 offset
= offset1
+ bytes_written
;
3139 assert(offset
<= max_offset
); /* offset1 shouldn't be large enough for this to happen */
3142 Temp val0
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
/ 2, RegType::vgpr
);
3143 Temp val1
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2) + 1, size
/ 2, RegType::vgpr
);
3144 bld
.ds(op
, address_offset
, val0
, val1
, m
, offset
/ size
/ 2, (offset
/ size
/ 2) + 1);
3146 Temp val
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
, RegType::vgpr
);
3147 bld
.ds(op
, address_offset
, val
, m
, offset
);
3150 bytes_written
+= size
* 4;
3154 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3155 Temp address
, unsigned base_offset
, unsigned align
)
3157 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
3158 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3160 Operand m
= load_lds_size_m0(ctx
);
3162 /* we need at most two stores, assuming that the writemask is at most 4 bits wide */
3163 assert(wrmask
<= 0x0f);
3164 int start
[2], count
[2];
3165 u_bit_scan_consecutive_range(&wrmask
, &start
[0], &count
[0]);
3166 u_bit_scan_consecutive_range(&wrmask
, &start
[1], &count
[1]);
3167 assert(wrmask
== 0);
3169 /* one combined store is sufficient */
3170 if (count
[0] == count
[1] && (align
% elem_size_bytes
) == 0 && (base_offset
% elem_size_bytes
) == 0) {
3171 Builder
bld(ctx
->program
, ctx
->block
);
3173 Temp address_offset
= address
;
3174 if ((base_offset
/ elem_size_bytes
) + start
[1] > 255) {
3175 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3179 assert(count
[0] == 1);
3180 RegClass
xtract_rc(RegType::vgpr
, elem_size_bytes
/ 4);
3182 Temp val0
= emit_extract_vector(ctx
, data
, start
[0], xtract_rc
);
3183 Temp val1
= emit_extract_vector(ctx
, data
, start
[1], xtract_rc
);
3184 aco_opcode op
= elem_size_bytes
== 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3185 base_offset
= base_offset
/ elem_size_bytes
;
3186 bld
.ds(op
, address_offset
, val0
, val1
, m
,
3187 base_offset
+ start
[0], base_offset
+ start
[1]);
3191 for (unsigned i
= 0; i
< 2; i
++) {
3195 unsigned elem_size_words
= elem_size_bytes
/ 4;
3196 ds_write_helper(ctx
, m
, address
, data
, start
[i
] * elem_size_words
, count
[i
] * elem_size_words
,
3197 base_offset
, start
[i
] * elem_size_bytes
, align
);
3202 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3204 unsigned align
= 16;
3206 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3212 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3213 unsigned split_cnt
= 0u, Temp dst
= Temp())
3215 Builder
bld(ctx
->program
, ctx
->block
);
3216 unsigned dword_size
= elem_size_bytes
/ 4;
3219 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3221 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3222 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3223 instr
->definitions
[0] = Definition(dst
);
3225 for (unsigned i
= 0; i
< cnt
; ++i
) {
3227 assert(arr
[i
].size() == dword_size
);
3228 allocated_vec
[i
] = arr
[i
];
3229 instr
->operands
[i
] = Operand(arr
[i
]);
3231 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3232 allocated_vec
[i
] = zero
;
3233 instr
->operands
[i
] = Operand(zero
);
3237 bld
.insert(std::move(instr
));
3240 emit_split_vector(ctx
, dst
, split_cnt
);
3242 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3247 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3249 if (const_offset
>= 4096) {
3250 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3251 const_offset
%= 4096u;
3254 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3255 else if (unlikely(voffset
.regClass() == s1
))
3256 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3257 else if (likely(voffset
.regClass() == v1
))
3258 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3260 unreachable("Unsupported register class of voffset");
3263 return const_offset
;
3266 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3267 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3270 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3271 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3273 Builder
bld(ctx
->program
, ctx
->block
);
3274 aco_opcode op
= (aco_opcode
) ((unsigned) aco_opcode::buffer_store_dword
+ vdata
.size() - 1);
3275 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3277 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3278 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3279 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3280 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3281 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3283 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3286 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3287 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3288 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3290 Builder
bld(ctx
->program
, ctx
->block
);
3291 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3294 if (elem_size_bytes
== 8) {
3295 elem_size_bytes
= 4;
3296 write_mask
= widen_mask(write_mask
, 2);
3299 while (write_mask
) {
3302 u_bit_scan_consecutive_range(&write_mask
, &start
, &count
);
3307 unsigned sub_count
= allow_combining
? MIN2(count
, 4) : 1;
3308 unsigned const_offset
= (unsigned) start
* elem_size_bytes
+ base_const_offset
;
3310 /* GFX6 doesn't have buffer_store_dwordx3, so make sure not to emit that here either. */
3311 if (unlikely(ctx
->program
->chip_class
== GFX6
&& sub_count
== 3))
3314 Temp elem
= extract_subvector(ctx
, src
, start
, sub_count
, RegType::vgpr
);
3315 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, elem
, const_offset
, reorder
, slc
);
3325 Temp
emit_single_mubuf_load(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
,
3326 unsigned const_offset
, unsigned size_dwords
, bool allow_reorder
= true)
3328 assert(size_dwords
!= 3 || ctx
->program
->chip_class
!= GFX6
);
3329 assert(size_dwords
>= 1 && size_dwords
<= 4);
3331 Builder
bld(ctx
->program
, ctx
->block
);
3332 Temp vdata
= bld
.tmp(RegClass(RegType::vgpr
, size_dwords
));
3333 aco_opcode op
= (aco_opcode
) ((unsigned) aco_opcode::buffer_load_dword
+ size_dwords
- 1);
3334 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3336 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3337 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3338 Builder::Result r
= bld
.mubuf(op
, Definition(vdata
), Operand(descriptor
), voffset_op
, soffset_op
, const_offset
,
3339 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3340 /* disable_wqm */ false, /* glc */ true,
3341 /* dlc*/ ctx
->program
->chip_class
>= GFX10
, /* slc */ false);
3343 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3348 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3349 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3350 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3352 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3353 assert((num_components
* elem_size_bytes
/ 4) == dst
.size());
3354 assert(!!stride
!= allow_combining
);
3356 Builder
bld(ctx
->program
, ctx
->block
);
3357 unsigned split_cnt
= num_components
;
3359 if (elem_size_bytes
== 8) {
3360 elem_size_bytes
= 4;
3361 num_components
*= 2;
3365 stride
= elem_size_bytes
;
3367 unsigned load_size
= 1;
3368 if (allow_combining
) {
3369 if ((num_components
% 4) == 0)
3371 else if ((num_components
% 3) == 0 && ctx
->program
->chip_class
!= GFX6
)
3373 else if ((num_components
% 2) == 0)
3377 unsigned num_loads
= num_components
/ load_size
;
3378 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
3380 for (unsigned i
= 0; i
< num_loads
; ++i
) {
3381 unsigned const_offset
= i
* stride
* load_size
+ base_const_offset
;
3382 elems
[i
] = emit_single_mubuf_load(ctx
, descriptor
, voffset
, soffset
, const_offset
, load_size
, allow_reorder
);
3385 create_vec_from_array(ctx
, elems
.data(), num_loads
, RegType::vgpr
, load_size
* 4u, split_cnt
, dst
);
3388 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
3390 Builder
bld(ctx
->program
, ctx
->block
);
3391 Temp offset
= base_offset
.first
;
3392 unsigned const_offset
= base_offset
.second
;
3394 if (!nir_src_is_const(*off_src
)) {
3395 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
3398 /* Calculate indirect offset with stride */
3399 if (likely(indirect_offset_arg
.regClass() == v1
))
3400 with_stride
= bld
.v_mul_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
3401 else if (indirect_offset_arg
.regClass() == s1
)
3402 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
3404 unreachable("Unsupported register class of indirect offset");
3406 /* Add to the supplied base offset */
3407 if (offset
.id() == 0)
3408 offset
= with_stride
;
3409 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
3410 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
3411 else if (offset
.size() == 1 && with_stride
.size() == 1)
3412 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
3414 unreachable("Unsupported register class of indirect offset");
3416 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
3417 const_offset
+= const_offset_arg
* stride
;
3420 return std::make_pair(offset
, const_offset
);
3423 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
3425 Builder
bld(ctx
->program
, ctx
->block
);
3428 if (off1
.first
.id() && off2
.first
.id()) {
3429 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
3430 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
3431 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
3432 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
3434 unreachable("Unsupported register class of indirect offset");
3436 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
3439 return std::make_pair(offset
, off1
.second
+ off2
.second
);
3442 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
3444 Builder
bld(ctx
->program
, ctx
->block
);
3445 unsigned const_offset
= offs
.second
* multiplier
;
3447 if (!offs
.first
.id())
3448 return std::make_pair(offs
.first
, const_offset
);
3450 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
3451 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
3452 : bld
.v_mul_imm(bld
.def(v1
), offs
.first
, multiplier
);
3454 return std::make_pair(offset
, const_offset
);
3457 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
3459 Builder
bld(ctx
->program
, ctx
->block
);
3461 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
3462 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
3463 /* component is in bytes */
3464 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
3466 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
3467 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3468 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
3471 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
3473 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
3476 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
3478 Builder
bld(ctx
->program
, ctx
->block
);
3480 switch (ctx
->shader
->info
.stage
) {
3481 case MESA_SHADER_TESS_CTRL
:
3482 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
3483 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
3484 case MESA_SHADER_TESS_EVAL
:
3485 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
3487 unreachable("Unsupported stage in get_tess_rel_patch_id");
3491 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3493 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3494 Builder
bld(ctx
->program
, ctx
->block
);
3496 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
3497 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
3499 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
3501 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3502 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
3504 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3505 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
3506 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
3508 return offset_mul(ctx
, offs
, 4u);
3511 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
3513 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3514 Builder
bld(ctx
->program
, ctx
->block
);
3516 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
3517 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
3518 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
3519 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
3520 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
3521 uint32_t output_patch_stride
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
3523 std::pair
<Temp
, unsigned> offs
= instr
3524 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
3525 : std::make_pair(Temp(), 0u);
3527 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3528 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
3533 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3534 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
3536 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
3537 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
3539 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
3540 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
3546 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3548 Builder
bld(ctx
->program
, ctx
->block
);
3550 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
3551 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
3553 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
3555 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3556 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
3557 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
3559 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3560 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
3565 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
3567 Builder
bld(ctx
->program
, ctx
->block
);
3569 unsigned num_tcs_outputs
= ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
3570 ? util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
)
3571 : ctx
->args
->options
->key
.tes
.tcs_num_outputs
;
3573 unsigned output_vertex_size
= num_tcs_outputs
* 16;
3574 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
3575 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
3576 unsigned attr_stride
= ctx
->tcs_num_patches
;
3578 std::pair
<Temp
, unsigned> offs
= instr
3579 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
3580 : std::make_pair(Temp(), 0u);
3582 if (const_base_offset
)
3583 offs
.second
+= const_base_offset
* attr_stride
;
3585 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3586 Temp patch_off
= bld
.v_mul_imm(bld
.def(v1
), rel_patch_id
, 16u);
3587 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
3592 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
3594 unsigned off
= nir_intrinsic_base(instr
) * 4u;
3595 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3597 if (!nir_src_is_const(*off_src
)) {
3603 off
+= nir_src_as_uint(*off_src
) * 16u;
3606 unsigned slot
= u_bit_scan64(&mask
) + (per_vertex
? 0 : VARYING_SLOT_PATCH0
);
3607 if (off
== shader_io_get_unique_index((gl_varying_slot
) slot
) * 16u)
3614 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3616 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3617 unsigned component
= nir_intrinsic_component(instr
);
3618 unsigned idx
= nir_intrinsic_base(instr
) + component
;
3620 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
3621 if (off_instr
->type
!= nir_instr_type_load_const
)
3624 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3625 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
3627 if (instr
->src
[0].ssa
->bit_size
== 64)
3628 write_mask
= widen_mask(write_mask
, 2);
3630 for (unsigned i
= 0; i
< 8; ++i
) {
3631 if (write_mask
& (1 << i
)) {
3632 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
3633 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, v1
);
3641 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
3643 /* Only TCS per-vertex inputs are supported by this function.
3644 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
3646 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
3649 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3650 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3651 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
3652 bool can_use_temps
= nir_src_is_const(*off_src
) &&
3653 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
3654 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
3659 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
3660 Temp
*src
= &ctx
->inputs
.temps
[idx
];
3661 Temp vec
= create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u);
3662 assert(vec
.size() == dst
.size());
3664 Builder
bld(ctx
->program
, ctx
->block
);
3665 bld
.copy(Definition(dst
), vec
);
3669 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3671 Builder
bld(ctx
->program
, ctx
->block
);
3673 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
3674 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3675 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3676 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
3678 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
3679 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
3680 bool indirect_write
;
3681 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
3682 if (temp_only_input
&& !indirect_write
)
3686 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
3687 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
3688 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
3689 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
3690 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
3694 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
3695 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
3696 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
3697 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
3698 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
3699 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
3700 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
3701 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
3702 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
3703 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
3704 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
3705 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
3706 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
3708 unsigned num_tcs_inputs
= util_last_bit64(ctx
->args
->shader_info
->vs
.ls_outputs_written
);
3709 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
3710 lds_base
= bld
.v_mul_imm(bld
.def(v1
), vertex_idx
, num_tcs_inputs
* 16u);
3712 unreachable("Invalid LS or ES stage");
3715 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
3716 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
3717 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
3721 bool should_write_tcs_patch_output_to_vmem(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3723 unsigned off
= nir_intrinsic_base(instr
) * 4u;
3724 return off
!= ctx
->tcs_tess_lvl_out_loc
&&
3725 off
!= ctx
->tcs_tess_lvl_in_loc
;
3728 bool should_write_tcs_output_to_lds(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3730 /* When none of the appropriate outputs are read, we are OK to never write to LDS */
3731 if (per_vertex
? ctx
->shader
->info
.outputs_read
== 0U : ctx
->shader
->info
.patch_outputs_read
== 0u)
3734 uint64_t mask
= per_vertex
3735 ? ctx
->shader
->info
.outputs_read
3736 : ctx
->shader
->info
.patch_outputs_read
;
3737 bool indirect_write
;
3738 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
3739 return indirect_write
|| output_read
;
3742 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3744 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
3745 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3747 Builder
bld(ctx
->program
, ctx
->block
);
3749 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3750 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
3751 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3753 /* Only write to VMEM if the output is per-vertex or it's per-patch non tess factor */
3754 bool write_to_vmem
= per_vertex
|| should_write_tcs_patch_output_to_vmem(ctx
, instr
);
3755 /* Only write to LDS if the output is read by the shader, or it's per-patch tess factor */
3756 bool write_to_lds
= !write_to_vmem
|| should_write_tcs_output_to_lds(ctx
, instr
, per_vertex
);
3758 if (write_to_vmem
) {
3759 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
3760 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
3761 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
3763 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
3764 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
3765 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
3769 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
3770 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
3771 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
3775 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3777 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
3778 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3780 Builder
bld(ctx
->program
, ctx
->block
);
3782 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3783 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
3784 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
3785 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
3787 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
3790 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3792 if (ctx
->stage
== vertex_vs
||
3793 ctx
->stage
== tess_eval_vs
||
3794 ctx
->stage
== fragment_fs
||
3795 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
3796 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
3797 if (!stored_to_temps
) {
3798 fprintf(stderr
, "Unimplemented output offset instruction:\n");
3799 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
3800 fprintf(stderr
, "\n");
3803 } else if (ctx
->stage
== vertex_es
||
3804 ctx
->stage
== vertex_ls
||
3805 ctx
->stage
== tess_eval_es
||
3806 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
3807 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
3808 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
3809 visit_store_ls_or_es_output(ctx
, instr
);
3810 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
3811 visit_store_tcs_output(ctx
, instr
, false);
3813 unreachable("Shader stage not implemented");
3817 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3819 visit_load_tcs_output(ctx
, instr
, false);
3822 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
3824 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
3825 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
3827 Builder
bld(ctx
->program
, ctx
->block
);
3828 Builder::Result interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
, bld
.m0(prim_mask
), idx
, component
);
3829 if (ctx
->program
->has_16bank_lds
)
3830 interp_p1
.instr
->operands
[0].setLateKill(true);
3831 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
3834 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
3836 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
3837 for (unsigned i
= 0; i
< num_components
; i
++)
3838 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
3839 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
3840 assert(num_components
== 4);
3841 Builder
bld(ctx
->program
, ctx
->block
);
3842 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
3845 for (Operand
& op
: vec
->operands
)
3846 op
= op
.isUndefined() ? Operand(0u) : op
;
3848 vec
->definitions
[0] = Definition(dst
);
3849 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3850 emit_split_vector(ctx
, dst
, num_components
);
3854 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3856 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3857 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3858 unsigned idx
= nir_intrinsic_base(instr
);
3859 unsigned component
= nir_intrinsic_component(instr
);
3860 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
3862 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
3864 assert(offset
->u32
== 0);
3866 /* the lower 15bit of the prim_mask contain the offset into LDS
3867 * while the upper bits contain the number of prims */
3868 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
3869 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
3870 Builder
bld(ctx
->program
, ctx
->block
);
3871 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
3872 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
3873 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
3874 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
3875 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
3878 if (instr
->dest
.ssa
.num_components
== 1) {
3879 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
3881 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
3882 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
3884 Temp tmp
= {ctx
->program
->allocateId(), v1
};
3885 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
3886 vec
->operands
[i
] = Operand(tmp
);
3888 vec
->definitions
[0] = Definition(dst
);
3889 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3893 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
3894 unsigned offset
, unsigned stride
, unsigned channels
)
3896 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
3897 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
3899 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
3900 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
3903 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
3904 unsigned offset
, unsigned stride
, unsigned *channels
)
3906 if (!vtx_info
->chan_byte_size
) {
3907 *channels
= vtx_info
->num_channels
;
3908 return vtx_info
->chan_format
;
3911 unsigned num_channels
= *channels
;
3912 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
3913 unsigned new_channels
= num_channels
+ 1;
3914 /* first, assume more loads is worse and try using a larger data format */
3915 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
3917 /* don't make the attribute potentially out-of-bounds */
3918 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
3922 if (new_channels
== 5) {
3923 /* then try decreasing load size (at the cost of more loads) */
3924 new_channels
= *channels
;
3925 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
3929 if (new_channels
< *channels
)
3930 *channels
= new_channels
;
3931 num_channels
= new_channels
;
3934 switch (vtx_info
->chan_format
) {
3935 case V_008F0C_BUF_DATA_FORMAT_8
:
3936 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
3937 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
3938 case V_008F0C_BUF_DATA_FORMAT_16
:
3939 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
3940 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
3941 case V_008F0C_BUF_DATA_FORMAT_32
:
3942 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
3943 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
3945 unreachable("shouldn't reach here");
3946 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
3949 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
3950 * so we may need to fix it up. */
3951 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
3953 Builder
bld(ctx
->program
, ctx
->block
);
3955 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
3956 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
3958 /* For the integer-like cases, do a natural sign extension.
3960 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
3961 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
3964 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
3965 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
3967 /* Convert back to the right type. */
3968 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
3969 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
3970 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
3971 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
3972 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
3973 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
3979 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3981 Builder
bld(ctx
->program
, ctx
->block
);
3982 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3983 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
3985 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
3986 if (off_instr
->type
!= nir_instr_type_load_const
) {
3987 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
3988 nir_print_instr(off_instr
, stderr
);
3989 fprintf(stderr
, "\n");
3991 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
3993 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
3995 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
3996 unsigned component
= nir_intrinsic_component(instr
);
3997 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
3998 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
3999 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4000 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4002 unsigned dfmt
= attrib_format
& 0xf;
4003 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4004 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4006 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4007 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4008 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4009 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4011 num_channels
= MAX2(num_channels
, 3);
4013 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4014 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4017 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4018 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4019 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4021 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4023 Temp divided
= bld
.tmp(v1
);
4024 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4025 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4027 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4030 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4033 index
= bld
.vadd32(bld
.def(v1
),
4034 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4035 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4038 Temp channels
[num_channels
];
4039 unsigned channel_start
= 0;
4040 bool direct_fetch
= false;
4042 /* skip unused channels at the start */
4043 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4044 channel_start
= ffs(mask
) - 1;
4045 for (unsigned i
= 0; i
< channel_start
; i
++)
4046 channels
[i
] = Temp(0, s1
);
4047 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4048 num_channels
= 3 - (ffs(mask
) - 1);
4052 while (channel_start
< num_channels
) {
4053 unsigned fetch_size
= num_channels
- channel_start
;
4054 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4055 bool expanded
= false;
4057 /* use MUBUF when possible to avoid possible alignment issues */
4058 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4059 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4060 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4061 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4062 vtx_info
->chan_byte_size
== 4;
4063 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4065 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_size
);
4067 if (fetch_size
== 3 && ctx
->options
->chip_class
== GFX6
) {
4068 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4074 Temp fetch_index
= index
;
4075 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4076 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4077 fetch_offset
= fetch_offset
% attrib_stride
;
4080 Operand
soffset(0u);
4081 if (fetch_offset
>= 4096) {
4082 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4083 fetch_offset
%= 4096;
4087 switch (fetch_size
) {
4089 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4092 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4095 assert(ctx
->options
->chip_class
>= GFX7
||
4096 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4097 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4100 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4103 unreachable("Unimplemented load_input vector size");
4107 if (channel_start
== 0 && fetch_size
== dst
.size() && !post_shuffle
&&
4108 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4109 num_channels
<= 3)) {
4110 direct_fetch
= true;
4113 fetch_dst
= bld
.tmp(RegType::vgpr
, fetch_size
);
4117 Instruction
*mubuf
= bld
.mubuf(opcode
,
4118 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4119 fetch_offset
, false, true).instr
;
4120 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4122 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4123 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4124 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4125 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4128 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4130 if (fetch_size
== 1) {
4131 channels
[channel_start
] = fetch_dst
;
4133 for (unsigned i
= 0; i
< MIN2(fetch_size
, num_channels
- channel_start
); i
++)
4134 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
, v1
);
4137 channel_start
+= fetch_size
;
4140 if (!direct_fetch
) {
4141 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4142 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4144 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4145 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4146 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4148 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4149 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4150 unsigned num_temp
= 0;
4151 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4152 unsigned idx
= i
+ component
;
4153 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4154 Temp channel
= channels
[swizzle
[idx
]];
4155 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4156 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4157 vec
->operands
[i
] = Operand(channel
);
4161 } else if (is_float
&& idx
== 3) {
4162 vec
->operands
[i
] = Operand(0x3f800000u
);
4163 } else if (!is_float
&& idx
== 3) {
4164 vec
->operands
[i
] = Operand(1u);
4166 vec
->operands
[i
] = Operand(0u);
4169 vec
->definitions
[0] = Definition(dst
);
4170 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4171 emit_split_vector(ctx
, dst
, dst
.size());
4173 if (num_temp
== dst
.size())
4174 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4176 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4177 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4178 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4179 if (off_instr
->type
!= nir_instr_type_load_const
||
4180 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4181 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4182 nir_print_instr(off_instr
, stderr
);
4183 fprintf(stderr
, "\n");
4186 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4187 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4189 assert(offset
->u32
== 0);
4191 /* the lower 15bit of the prim_mask contain the offset into LDS
4192 * while the upper bits contain the number of prims */
4193 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4194 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4195 Builder
bld(ctx
->program
, ctx
->block
);
4196 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4197 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4198 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4199 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4200 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4203 unsigned idx
= nir_intrinsic_base(instr
);
4204 unsigned component
= nir_intrinsic_component(instr
);
4205 unsigned vertex_id
= 2; /* P0 */
4207 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4208 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4209 switch (src0
->u32
) {
4211 vertex_id
= 2; /* P0 */
4214 vertex_id
= 0; /* P10 */
4217 vertex_id
= 1; /* P20 */
4220 unreachable("invalid vertex index");
4224 if (dst
.size() == 1) {
4225 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4227 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4228 for (unsigned i
= 0; i
< dst
.size(); i
++)
4229 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4230 vec
->definitions
[0] = Definition(dst
);
4231 bld
.insert(std::move(vec
));
4234 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4235 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4236 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4237 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4238 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4240 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4242 unreachable("Shader stage not implemented");
4246 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4248 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4250 Builder
bld(ctx
->program
, ctx
->block
);
4251 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4254 if (!nir_src_is_const(*vertex_src
)) {
4255 /* better code could be created, but this case probably doesn't happen
4256 * much in practice */
4257 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4258 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4261 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4262 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4264 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4266 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4269 if (vertex_offset
.id()) {
4270 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4271 Operand(i
), indirect_vertex
);
4272 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4274 vertex_offset
= elem
;
4278 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4279 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4281 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4282 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4283 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4284 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4285 Operand((vertex
% 2u) * 16u), Operand(16u));
4287 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4290 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4291 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4292 return offset_mul(ctx
, offs
, 4u);
4295 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4297 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4299 Builder
bld(ctx
->program
, ctx
->block
);
4300 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4301 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4303 if (ctx
->stage
== geometry_gs
) {
4304 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4305 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4306 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4307 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4308 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4309 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4310 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4312 unreachable("Unsupported GS stage.");
4316 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4318 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4320 Builder
bld(ctx
->program
, ctx
->block
);
4321 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4323 if (load_input_from_temps(ctx
, instr
, dst
))
4326 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4327 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4328 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4330 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4333 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4335 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4337 Builder
bld(ctx
->program
, ctx
->block
);
4339 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4340 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4341 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4343 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4344 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
4346 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
4349 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4351 switch (ctx
->shader
->info
.stage
) {
4352 case MESA_SHADER_GEOMETRY
:
4353 visit_load_gs_per_vertex_input(ctx
, instr
);
4355 case MESA_SHADER_TESS_CTRL
:
4356 visit_load_tcs_per_vertex_input(ctx
, instr
);
4358 case MESA_SHADER_TESS_EVAL
:
4359 visit_load_tes_per_vertex_input(ctx
, instr
);
4362 unreachable("Unimplemented shader stage");
4366 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4368 visit_load_tcs_output(ctx
, instr
, true);
4371 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4373 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4374 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4376 visit_store_tcs_output(ctx
, instr
, true);
4379 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4381 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4383 Builder
bld(ctx
->program
, ctx
->block
);
4384 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4386 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
4387 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
4390 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
4391 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
4392 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
4393 tes_w
= Operand(tmp
);
4396 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
4397 emit_split_vector(ctx
, tess_coord
, 3);
4400 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
4402 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
4403 Builder
bld(ctx
->program
, ctx
->block
);
4404 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
4405 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
4406 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
4409 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
4413 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4415 Builder
bld(ctx
->program
, ctx
->block
);
4416 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4417 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
])
4418 index
= bld
.as_uniform(index
);
4419 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
4420 unsigned binding
= nir_intrinsic_binding(instr
);
4423 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
4424 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
4425 unsigned offset
= layout
->binding
[binding
].offset
;
4427 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
4428 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
4429 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
4430 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
4431 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
4434 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
4435 stride
= layout
->binding
[binding
].size
;
4438 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
4439 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
4441 if (nir_const_index
) {
4442 const_index
= const_index
* stride
;
4443 } else if (index
.type() == RegType::vgpr
) {
4444 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
4445 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
4447 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
4451 if (nir_const_index
) {
4452 const_index
= const_index
+ offset
;
4453 } else if (index
.type() == RegType::vgpr
) {
4454 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
4456 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
4460 if (nir_const_index
&& const_index
== 0) {
4462 } else if (index
.type() == RegType::vgpr
) {
4463 index
= bld
.vadd32(bld
.def(v1
),
4464 nir_const_index
? Operand(const_index
) : Operand(index
),
4467 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
4468 nir_const_index
? Operand(const_index
) : Operand(index
),
4472 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
4475 void load_buffer(isel_context
*ctx
, unsigned num_components
, Temp dst
,
4476 Temp rsrc
, Temp offset
, bool glc
=false, bool readonly
=true)
4478 Builder
bld(ctx
->program
, ctx
->block
);
4480 unsigned num_bytes
= dst
.size() * 4;
4481 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
4484 if (dst
.type() == RegType::vgpr
|| (ctx
->options
->chip_class
< GFX8
&& !readonly
)) {
4485 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
4486 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
4487 unsigned const_offset
= 0;
4489 Temp lower
= Temp();
4490 if (num_bytes
> 16) {
4491 assert(num_components
== 3 || num_components
== 4);
4492 op
= aco_opcode::buffer_load_dwordx4
;
4493 lower
= bld
.tmp(v4
);
4494 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
4495 mubuf
->definitions
[0] = Definition(lower
);
4496 mubuf
->operands
[0] = Operand(rsrc
);
4497 mubuf
->operands
[1] = vaddr
;
4498 mubuf
->operands
[2] = soffset
;
4499 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
4502 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4503 mubuf
->can_reorder
= readonly
;
4504 bld
.insert(std::move(mubuf
));
4505 emit_split_vector(ctx
, lower
, 2);
4508 } else if (num_bytes
== 12 && ctx
->options
->chip_class
== GFX6
) {
4509 /* GFX6 doesn't support loading vec3, expand to vec4. */
4513 switch (num_bytes
) {
4515 op
= aco_opcode::buffer_load_dword
;
4518 op
= aco_opcode::buffer_load_dwordx2
;
4521 assert(ctx
->options
->chip_class
> GFX6
);
4522 op
= aco_opcode::buffer_load_dwordx3
;
4525 op
= aco_opcode::buffer_load_dwordx4
;
4528 unreachable("Load SSBO not implemented for this size.");
4530 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
4531 mubuf
->operands
[0] = Operand(rsrc
);
4532 mubuf
->operands
[1] = vaddr
;
4533 mubuf
->operands
[2] = soffset
;
4534 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
4537 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4538 mubuf
->can_reorder
= readonly
;
4539 mubuf
->offset
= const_offset
;
4540 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
4542 if (dst
.size() > 4) {
4543 assert(lower
!= Temp());
4544 Temp upper
= bld
.tmp(RegType::vgpr
, dst
.size() - lower
.size());
4545 instr
->definitions
[0] = Definition(upper
);
4546 bld
.insert(std::move(instr
));
4547 if (dst
.size() == 8)
4548 emit_split_vector(ctx
, upper
, 2);
4549 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size() / 2, 1));
4550 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, lower
, 0, v2
));
4551 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, lower
, 1, v2
));
4552 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, upper
, 0, v2
));
4553 if (dst
.size() == 8)
4554 instr
->operands
[3] = Operand(emit_extract_vector(ctx
, upper
, 1, v2
));
4555 } else if (dst
.size() == 3 && ctx
->options
->chip_class
== GFX6
) {
4556 Temp vec
= bld
.tmp(v4
);
4557 instr
->definitions
[0] = Definition(vec
);
4558 bld
.insert(std::move(instr
));
4559 emit_split_vector(ctx
, vec
, 4);
4561 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 3, 1));
4562 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, vec
, 0, v1
));
4563 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, vec
, 1, v1
));
4564 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, vec
, 2, v1
));
4567 if (dst
.type() == RegType::sgpr
) {
4568 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
4569 instr
->definitions
[0] = Definition(vec
);
4570 bld
.insert(std::move(instr
));
4571 expand_vector(ctx
, vec
, dst
, num_components
, (1 << num_components
) - 1);
4573 instr
->definitions
[0] = Definition(dst
);
4574 bld
.insert(std::move(instr
));
4575 emit_split_vector(ctx
, dst
, num_components
);
4578 switch (num_bytes
) {
4580 op
= aco_opcode::s_buffer_load_dword
;
4583 op
= aco_opcode::s_buffer_load_dwordx2
;
4587 op
= aco_opcode::s_buffer_load_dwordx4
;
4591 op
= aco_opcode::s_buffer_load_dwordx8
;
4594 unreachable("Load SSBO not implemented for this size.");
4596 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
4597 load
->operands
[0] = Operand(rsrc
);
4598 load
->operands
[1] = Operand(bld
.as_uniform(offset
));
4599 assert(load
->operands
[1].getTemp().type() == RegType::sgpr
);
4600 load
->definitions
[0] = Definition(dst
);
4603 load
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4604 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
4605 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
4608 if (dst
.size() == 3) {
4609 Temp vec
= bld
.tmp(s4
);
4610 load
->definitions
[0] = Definition(vec
);
4611 bld
.insert(std::move(load
));
4612 emit_split_vector(ctx
, vec
, 4);
4614 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4615 emit_extract_vector(ctx
, vec
, 0, s1
),
4616 emit_extract_vector(ctx
, vec
, 1, s1
),
4617 emit_extract_vector(ctx
, vec
, 2, s1
));
4618 } else if (dst
.size() == 6) {
4619 Temp vec
= bld
.tmp(s8
);
4620 load
->definitions
[0] = Definition(vec
);
4621 bld
.insert(std::move(load
));
4622 emit_split_vector(ctx
, vec
, 4);
4624 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4625 emit_extract_vector(ctx
, vec
, 0, s2
),
4626 emit_extract_vector(ctx
, vec
, 1, s2
),
4627 emit_extract_vector(ctx
, vec
, 2, s2
));
4629 bld
.insert(std::move(load
));
4631 emit_split_vector(ctx
, dst
, num_components
);
4635 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4637 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4638 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4640 Builder
bld(ctx
->program
, ctx
->block
);
4642 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
4643 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
4644 unsigned binding
= nir_intrinsic_binding(idx_instr
);
4645 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
4647 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
4648 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
4649 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
4650 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
4651 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
4652 if (ctx
->options
->chip_class
>= GFX10
) {
4653 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
4654 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
4655 S_008F0C_RESOURCE_LEVEL(1);
4657 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
4658 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
4660 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
4661 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
4662 Operand(0xFFFFFFFFu
),
4663 Operand(desc_type
));
4664 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
4665 rsrc
, upper_dwords
);
4667 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
4668 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
4671 load_buffer(ctx
, instr
->num_components
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
4674 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4676 Builder
bld(ctx
->program
, ctx
->block
);
4677 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4679 unsigned offset
= nir_intrinsic_base(instr
);
4680 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
4681 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
4683 unsigned count
= instr
->dest
.ssa
.num_components
;
4684 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
4685 start
-= ctx
->args
->ac
.base_inline_push_consts
;
4686 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
4687 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4688 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
4689 for (unsigned i
= 0; i
< count
; ++i
) {
4690 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
4691 vec
->operands
[i
] = Operand
{elems
[i
]};
4693 vec
->definitions
[0] = Definition(dst
);
4694 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4695 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4700 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
4701 if (offset
!= 0) // TODO check if index != 0 as well
4702 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
4703 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
4708 switch (dst
.size()) {
4710 op
= aco_opcode::s_load_dword
;
4713 op
= aco_opcode::s_load_dwordx2
;
4719 op
= aco_opcode::s_load_dwordx4
;
4725 op
= aco_opcode::s_load_dwordx8
;
4728 unreachable("unimplemented or forbidden load_push_constant.");
4731 bld
.smem(op
, Definition(vec
), ptr
, index
);
4734 emit_split_vector(ctx
, vec
, 4);
4735 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
4736 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4737 emit_extract_vector(ctx
, vec
, 0, rc
),
4738 emit_extract_vector(ctx
, vec
, 1, rc
),
4739 emit_extract_vector(ctx
, vec
, 2, rc
));
4742 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
4745 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4747 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4749 Builder
bld(ctx
->program
, ctx
->block
);
4751 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
4752 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
4753 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
4754 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
4755 if (ctx
->options
->chip_class
>= GFX10
) {
4756 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
4757 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
4758 S_008F0C_RESOURCE_LEVEL(1);
4760 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
4761 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
4764 unsigned base
= nir_intrinsic_base(instr
);
4765 unsigned range
= nir_intrinsic_range(instr
);
4767 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4768 if (base
&& offset
.type() == RegType::sgpr
)
4769 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
4770 else if (base
&& offset
.type() == RegType::vgpr
)
4771 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
4773 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
4774 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
4775 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
4776 Operand(desc_type
));
4778 load_buffer(ctx
, instr
->num_components
, dst
, rsrc
, offset
);
4781 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4783 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
4784 ctx
->cf_info
.exec_potentially_empty_discard
= true;
4786 ctx
->program
->needs_exact
= true;
4788 // TODO: optimize uniform conditions
4789 Builder
bld(ctx
->program
, ctx
->block
);
4790 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4791 assert(src
.regClass() == bld
.lm
);
4792 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
4793 bld
.pseudo(aco_opcode::p_discard_if
, src
);
4794 ctx
->block
->kind
|= block_kind_uses_discard_if
;
4798 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
4800 Builder
bld(ctx
->program
, ctx
->block
);
4802 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
4803 ctx
->cf_info
.exec_potentially_empty_discard
= true;
4805 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
4806 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
4808 if (ctx
->block
->loop_nest_depth
&&
4809 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
4810 /* we handle discards the same way as jump instructions */
4811 append_logical_end(ctx
->block
);
4813 /* in loops, discard behaves like break */
4814 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
4815 ctx
->block
->kind
|= block_kind_discard
;
4818 /* uniform discard - loop ends here */
4819 assert(nir_instr_is_last(&instr
->instr
));
4820 ctx
->block
->kind
|= block_kind_uniform
;
4821 ctx
->cf_info
.has_branch
= true;
4822 bld
.branch(aco_opcode::p_branch
);
4823 add_linear_edge(ctx
->block
->index
, linear_target
);
4827 /* we add a break right behind the discard() instructions */
4828 ctx
->block
->kind
|= block_kind_break
;
4829 unsigned idx
= ctx
->block
->index
;
4831 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
4832 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
4834 /* remove critical edges from linear CFG */
4835 bld
.branch(aco_opcode::p_branch
);
4836 Block
* break_block
= ctx
->program
->create_and_insert_block();
4837 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
4838 break_block
->kind
|= block_kind_uniform
;
4839 add_linear_edge(idx
, break_block
);
4840 add_linear_edge(break_block
->index
, linear_target
);
4841 bld
.reset(break_block
);
4842 bld
.branch(aco_opcode::p_branch
);
4844 Block
* continue_block
= ctx
->program
->create_and_insert_block();
4845 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
4846 add_linear_edge(idx
, continue_block
);
4847 append_logical_start(continue_block
);
4848 ctx
->block
= continue_block
;
4853 /* it can currently happen that NIR doesn't remove the unreachable code */
4854 if (!nir_instr_is_last(&instr
->instr
)) {
4855 ctx
->program
->needs_exact
= true;
4856 /* save exec somewhere temporarily so that it doesn't get
4857 * overwritten before the discard from outer exec masks */
4858 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
4859 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
4860 ctx
->block
->kind
|= block_kind_uses_discard_if
;
4864 /* This condition is incorrect for uniformly branched discards in a loop
4865 * predicated by a divergent condition, but the above code catches that case
4866 * and the discard would end up turning into a discard_if.
4876 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
4877 /* program just ends here */
4878 ctx
->block
->kind
|= block_kind_uniform
;
4879 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
4880 0 /* enabled mask */, 9 /* dest */,
4881 false /* compressed */, true/* done */, true /* valid mask */);
4882 bld
.sopp(aco_opcode::s_endpgm
);
4883 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
4885 ctx
->block
->kind
|= block_kind_discard
;
4886 /* branch and linear edge is added by visit_if() */
4890 enum aco_descriptor_type
{
4901 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
4902 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4904 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
4905 return dim
== ac_image_cube
||
4906 dim
== ac_image_1darray
||
4907 dim
== ac_image_2darray
||
4908 dim
== ac_image_2darraymsaa
;
4911 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
4912 enum aco_descriptor_type desc_type
,
4913 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
4915 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
4916 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
4917 if (it != ctx->tex_desc.end())
4920 Temp index
= Temp();
4921 bool index_set
= false;
4922 unsigned constant_index
= 0;
4923 unsigned descriptor_set
;
4924 unsigned base_index
;
4925 Builder
bld(ctx
->program
, ctx
->block
);
4928 assert(tex_instr
&& !image
);
4930 base_index
= tex_instr
->sampler_index
;
4932 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
4933 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
4937 assert(deref_instr
->deref_type
== nir_deref_type_array
);
4938 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
4940 constant_index
+= array_size
* const_value
->u32
;
4942 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
4943 if (indirect
.type() == RegType::vgpr
)
4944 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
4946 if (array_size
!= 1)
4947 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
4953 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
4957 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
4959 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
4960 base_index
= deref_instr
->var
->data
.binding
;
4963 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
4964 list
= convert_pointer_to_64_bit(ctx
, list
);
4966 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
4967 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
4968 unsigned offset
= binding
->offset
;
4969 unsigned stride
= binding
->size
;
4973 assert(base_index
< layout
->binding_count
);
4975 switch (desc_type
) {
4976 case ACO_DESC_IMAGE
:
4978 opcode
= aco_opcode::s_load_dwordx8
;
4980 case ACO_DESC_FMASK
:
4982 opcode
= aco_opcode::s_load_dwordx8
;
4985 case ACO_DESC_SAMPLER
:
4987 opcode
= aco_opcode::s_load_dwordx4
;
4988 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
4989 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
4991 case ACO_DESC_BUFFER
:
4993 opcode
= aco_opcode::s_load_dwordx4
;
4995 case ACO_DESC_PLANE_0
:
4996 case ACO_DESC_PLANE_1
:
4998 opcode
= aco_opcode::s_load_dwordx8
;
4999 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5001 case ACO_DESC_PLANE_2
:
5003 opcode
= aco_opcode::s_load_dwordx4
;
5007 unreachable("invalid desc_type\n");
5010 offset
+= constant_index
* stride
;
5012 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5013 (!index_set
|| binding
->immutable_samplers_equal
)) {
5014 if (binding
->immutable_samplers_equal
)
5017 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5018 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5019 Operand(samplers
[constant_index
* 4 + 0]),
5020 Operand(samplers
[constant_index
* 4 + 1]),
5021 Operand(samplers
[constant_index
* 4 + 2]),
5022 Operand(samplers
[constant_index
* 4 + 3]));
5027 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5029 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5030 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5033 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5035 if (desc_type
== ACO_DESC_PLANE_2
) {
5037 for (unsigned i
= 0; i
< 8; i
++)
5038 components
[i
] = bld
.tmp(s1
);
5039 bld
.pseudo(aco_opcode::p_split_vector
,
5040 Definition(components
[0]),
5041 Definition(components
[1]),
5042 Definition(components
[2]),
5043 Definition(components
[3]),
5046 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5047 bld
.pseudo(aco_opcode::p_split_vector
,
5048 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5049 Definition(components
[4]),
5050 Definition(components
[5]),
5051 Definition(components
[6]),
5052 Definition(components
[7]),
5055 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5056 components
[0], components
[1], components
[2], components
[3],
5057 components
[4], components
[5], components
[6], components
[7]);
5063 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5066 case GLSL_SAMPLER_DIM_BUF
:
5068 case GLSL_SAMPLER_DIM_1D
:
5069 return array
? 2 : 1;
5070 case GLSL_SAMPLER_DIM_2D
:
5071 return array
? 3 : 2;
5072 case GLSL_SAMPLER_DIM_MS
:
5073 return array
? 4 : 3;
5074 case GLSL_SAMPLER_DIM_3D
:
5075 case GLSL_SAMPLER_DIM_CUBE
:
5077 case GLSL_SAMPLER_DIM_RECT
:
5078 case GLSL_SAMPLER_DIM_SUBPASS
:
5080 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5089 /* Adjust the sample index according to FMASK.
5091 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5092 * which is the identity mapping. Each nibble says which physical sample
5093 * should be fetched to get that sample.
5095 * For example, 0x11111100 means there are only 2 samples stored and
5096 * the second sample covers 3/4 of the pixel. When reading samples 0
5097 * and 1, return physical sample 0 (determined by the first two 0s
5098 * in FMASK), otherwise return physical sample 1.
5100 * The sample index should be adjusted as follows:
5101 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5103 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5105 Builder
bld(ctx
->program
, ctx
->block
);
5106 Temp fmask
= bld
.tmp(v1
);
5107 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5108 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5111 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5112 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5113 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5114 load
->operands
[0] = Operand(fmask_desc_ptr
);
5115 load
->operands
[1] = Operand(s4
); /* no sampler */
5116 load
->operands
[2] = Operand(coord
);
5117 load
->definitions
[0] = Definition(fmask
);
5124 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5125 ctx
->block
->instructions
.emplace_back(std::move(load
));
5127 Operand sample_index4
;
5128 if (sample_index
.isConstant() && sample_index
.constantValue() < 16) {
5129 sample_index4
= Operand(sample_index
.constantValue() << 2);
5130 } else if (sample_index
.regClass() == s1
) {
5131 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5133 assert(sample_index
.regClass() == v1
);
5134 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5138 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5139 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5140 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5141 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5143 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5145 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5146 * resource descriptor is 0 (invalid),
5148 Temp compare
= bld
.tmp(bld
.lm
);
5149 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5150 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5152 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5154 /* Replace the MSAA sample index. */
5155 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5158 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5161 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5162 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5163 bool is_array
= glsl_sampler_type_is_array(type
);
5164 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5165 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5166 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5167 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5168 int count
= image_type_to_components_count(dim
, is_array
);
5169 std::vector
<Temp
> coords(count
);
5170 Builder
bld(ctx
->program
, ctx
->block
);
5174 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5175 /* get sample index */
5176 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5177 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5178 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5179 std::vector
<Temp
> fmask_load_address
;
5180 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5181 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5183 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5184 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5186 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5191 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5192 coords
.resize(coords
.size() + 1);
5193 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5195 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5197 for (int i
= 0; i
< count
; i
++)
5198 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5201 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5202 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5203 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5204 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5207 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5210 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5211 for (unsigned i
= 0; i
< coords
.size(); i
++)
5212 vec
->operands
[i
] = Operand(coords
[i
]);
5213 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5214 vec
->definitions
[0] = Definition(res
);
5215 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5220 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5222 Builder
bld(ctx
->program
, ctx
->block
);
5223 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5224 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5225 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5226 bool is_array
= glsl_sampler_type_is_array(type
);
5227 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5229 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5230 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5231 unsigned num_channels
= util_last_bit(mask
);
5232 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5233 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5236 switch (num_channels
) {
5238 opcode
= aco_opcode::buffer_load_format_x
;
5241 opcode
= aco_opcode::buffer_load_format_xy
;
5244 opcode
= aco_opcode::buffer_load_format_xyz
;
5247 opcode
= aco_opcode::buffer_load_format_xyzw
;
5250 unreachable(">4 channel buffer image load");
5252 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5253 load
->operands
[0] = Operand(rsrc
);
5254 load
->operands
[1] = Operand(vindex
);
5255 load
->operands
[2] = Operand((uint32_t) 0);
5257 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5260 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5261 load
->definitions
[0] = Definition(tmp
);
5263 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5264 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5265 load
->barrier
= barrier_image
;
5266 ctx
->block
->instructions
.emplace_back(std::move(load
));
5268 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5272 Temp coords
= get_image_coords(ctx
, instr
, type
);
5273 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5275 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5276 unsigned num_components
= util_bitcount(dmask
);
5278 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5281 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5283 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5284 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5286 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5287 load
->operands
[0] = Operand(resource
);
5288 load
->operands
[1] = Operand(s4
); /* no sampler */
5289 load
->operands
[2] = Operand(coords
);
5290 load
->definitions
[0] = Definition(tmp
);
5291 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5292 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5293 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5294 load
->dmask
= dmask
;
5296 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5297 load
->barrier
= barrier_image
;
5298 ctx
->block
->instructions
.emplace_back(std::move(load
));
5300 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5304 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5306 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5307 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5308 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5309 bool is_array
= glsl_sampler_type_is_array(type
);
5310 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5312 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5314 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5315 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5316 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5318 switch (data
.size()) {
5320 opcode
= aco_opcode::buffer_store_format_x
;
5323 opcode
= aco_opcode::buffer_store_format_xy
;
5326 opcode
= aco_opcode::buffer_store_format_xyz
;
5329 opcode
= aco_opcode::buffer_store_format_xyzw
;
5332 unreachable(">4 channel buffer image store");
5334 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5335 store
->operands
[0] = Operand(rsrc
);
5336 store
->operands
[1] = Operand(vindex
);
5337 store
->operands
[2] = Operand((uint32_t) 0);
5338 store
->operands
[3] = Operand(data
);
5339 store
->idxen
= true;
5342 store
->disable_wqm
= true;
5343 store
->barrier
= barrier_image
;
5344 ctx
->program
->needs_exact
= true;
5345 ctx
->block
->instructions
.emplace_back(std::move(store
));
5349 assert(data
.type() == RegType::vgpr
);
5350 Temp coords
= get_image_coords(ctx
, instr
, type
);
5351 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5353 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5354 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5356 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5357 store
->operands
[0] = Operand(resource
);
5358 store
->operands
[1] = Operand(data
);
5359 store
->operands
[2] = Operand(coords
);
5362 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5363 store
->dmask
= (1 << data
.size()) - 1;
5365 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5366 store
->disable_wqm
= true;
5367 store
->barrier
= barrier_image
;
5368 ctx
->program
->needs_exact
= true;
5369 ctx
->block
->instructions
.emplace_back(std::move(store
));
5373 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5375 /* return the previous value if dest is ever used */
5376 bool return_previous
= false;
5377 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5378 return_previous
= true;
5381 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5382 return_previous
= true;
5386 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5387 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5388 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5389 bool is_array
= glsl_sampler_type_is_array(type
);
5390 Builder
bld(ctx
->program
, ctx
->block
);
5392 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5393 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5395 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5396 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5398 aco_opcode buf_op
, image_op
;
5399 switch (instr
->intrinsic
) {
5400 case nir_intrinsic_image_deref_atomic_add
:
5401 buf_op
= aco_opcode::buffer_atomic_add
;
5402 image_op
= aco_opcode::image_atomic_add
;
5404 case nir_intrinsic_image_deref_atomic_umin
:
5405 buf_op
= aco_opcode::buffer_atomic_umin
;
5406 image_op
= aco_opcode::image_atomic_umin
;
5408 case nir_intrinsic_image_deref_atomic_imin
:
5409 buf_op
= aco_opcode::buffer_atomic_smin
;
5410 image_op
= aco_opcode::image_atomic_smin
;
5412 case nir_intrinsic_image_deref_atomic_umax
:
5413 buf_op
= aco_opcode::buffer_atomic_umax
;
5414 image_op
= aco_opcode::image_atomic_umax
;
5416 case nir_intrinsic_image_deref_atomic_imax
:
5417 buf_op
= aco_opcode::buffer_atomic_smax
;
5418 image_op
= aco_opcode::image_atomic_smax
;
5420 case nir_intrinsic_image_deref_atomic_and
:
5421 buf_op
= aco_opcode::buffer_atomic_and
;
5422 image_op
= aco_opcode::image_atomic_and
;
5424 case nir_intrinsic_image_deref_atomic_or
:
5425 buf_op
= aco_opcode::buffer_atomic_or
;
5426 image_op
= aco_opcode::image_atomic_or
;
5428 case nir_intrinsic_image_deref_atomic_xor
:
5429 buf_op
= aco_opcode::buffer_atomic_xor
;
5430 image_op
= aco_opcode::image_atomic_xor
;
5432 case nir_intrinsic_image_deref_atomic_exchange
:
5433 buf_op
= aco_opcode::buffer_atomic_swap
;
5434 image_op
= aco_opcode::image_atomic_swap
;
5436 case nir_intrinsic_image_deref_atomic_comp_swap
:
5437 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5438 image_op
= aco_opcode::image_atomic_cmpswap
;
5441 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5444 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5446 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5447 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5448 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5449 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5450 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5451 mubuf
->operands
[0] = Operand(resource
);
5452 mubuf
->operands
[1] = Operand(vindex
);
5453 mubuf
->operands
[2] = Operand((uint32_t)0);
5454 mubuf
->operands
[3] = Operand(data
);
5455 if (return_previous
)
5456 mubuf
->definitions
[0] = Definition(dst
);
5458 mubuf
->idxen
= true;
5459 mubuf
->glc
= return_previous
;
5460 mubuf
->dlc
= false; /* Not needed for atomics */
5461 mubuf
->disable_wqm
= true;
5462 mubuf
->barrier
= barrier_image
;
5463 ctx
->program
->needs_exact
= true;
5464 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5468 Temp coords
= get_image_coords(ctx
, instr
, type
);
5469 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5470 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
5471 mimg
->operands
[0] = Operand(resource
);
5472 mimg
->operands
[1] = Operand(data
);
5473 mimg
->operands
[2] = Operand(coords
);
5474 if (return_previous
)
5475 mimg
->definitions
[0] = Definition(dst
);
5476 mimg
->glc
= return_previous
;
5477 mimg
->dlc
= false; /* Not needed for atomics */
5478 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5479 mimg
->dmask
= (1 << data
.size()) - 1;
5481 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5482 mimg
->disable_wqm
= true;
5483 mimg
->barrier
= barrier_image
;
5484 ctx
->program
->needs_exact
= true;
5485 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5489 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
5491 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
5492 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
5493 Builder
bld(ctx
->program
, ctx
->block
);
5495 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
5497 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
5498 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
5500 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
5501 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
5503 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
5504 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
5506 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
5507 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
5508 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
5509 if (dst
.type() == RegType::vgpr
)
5510 bld
.copy(Definition(dst
), shr_dst
);
5512 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
5514 emit_extract_vector(ctx
, desc
, 2, dst
);
5518 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5520 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5521 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5522 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5523 bool is_array
= glsl_sampler_type_is_array(type
);
5524 Builder
bld(ctx
->program
, ctx
->block
);
5526 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
5527 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
5528 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
5532 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
5535 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
5537 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5539 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
5540 mimg
->operands
[0] = Operand(resource
);
5541 mimg
->operands
[1] = Operand(s4
); /* no sampler */
5542 mimg
->operands
[2] = Operand(lod
);
5543 uint8_t& dmask
= mimg
->dmask
;
5544 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5545 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
5546 mimg
->da
= glsl_sampler_type_is_array(type
);
5547 mimg
->can_reorder
= true;
5548 Definition
& def
= mimg
->definitions
[0];
5549 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5551 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
5552 glsl_sampler_type_is_array(type
)) {
5554 assert(instr
->dest
.ssa
.num_components
== 3);
5555 Temp tmp
= {ctx
->program
->allocateId(), v3
};
5556 def
= Definition(tmp
);
5557 emit_split_vector(ctx
, tmp
, 3);
5559 /* divide 3rd value by 6 by multiplying with magic number */
5560 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
5561 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
5563 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5564 emit_extract_vector(ctx
, tmp
, 0, v1
),
5565 emit_extract_vector(ctx
, tmp
, 1, v1
),
5568 } else if (ctx
->options
->chip_class
== GFX9
&&
5569 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
5570 glsl_sampler_type_is_array(type
)) {
5571 assert(instr
->dest
.ssa
.num_components
== 2);
5572 def
= Definition(dst
);
5575 def
= Definition(dst
);
5578 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5581 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5583 Builder
bld(ctx
->program
, ctx
->block
);
5584 unsigned num_components
= instr
->num_components
;
5586 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5587 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5588 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5590 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5591 load_buffer(ctx
, num_components
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), glc
, false);
5594 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5596 Builder
bld(ctx
->program
, ctx
->block
);
5597 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5598 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
5599 unsigned writemask
= nir_intrinsic_write_mask(instr
);
5600 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5602 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
5603 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5605 bool smem
= !ctx
->divergent_vals
[instr
->src
[2].ssa
->index
] &&
5606 ctx
->options
->chip_class
>= GFX8
;
5608 offset
= bld
.as_uniform(offset
);
5609 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
5613 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
5614 if (count
== 3 && (smem
|| ctx
->options
->chip_class
== GFX6
)) {
5615 /* GFX6 doesn't support storing vec3, split it. */
5616 writemask
|= 1u << (start
+ 2);
5619 int num_bytes
= count
* elem_size_bytes
;
5621 if (num_bytes
> 16) {
5622 assert(elem_size_bytes
== 8);
5623 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
5628 // TODO: check alignment of sub-dword stores
5629 // TODO: split 3 bytes. there is no store instruction for that
5632 if (count
!= instr
->num_components
) {
5633 emit_split_vector(ctx
, data
, instr
->num_components
);
5634 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5635 for (int i
= 0; i
< count
; i
++) {
5636 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(data
.type(), elem_size_bytes
/ 4));
5637 vec
->operands
[i
] = Operand(smem_nonfs
? bld
.as_uniform(elem
) : elem
);
5639 write_data
= bld
.tmp(!smem
? RegType::vgpr
: smem_nonfs
? RegType::sgpr
: data
.type(), count
* elem_size_bytes
/ 4);
5640 vec
->definitions
[0] = Definition(write_data
);
5641 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5642 } else if (!smem
&& data
.type() != RegType::vgpr
) {
5643 assert(num_bytes
% 4 == 0);
5644 write_data
= bld
.copy(bld
.def(RegType::vgpr
, num_bytes
/ 4), data
);
5645 } else if (smem_nonfs
&& data
.type() == RegType::vgpr
) {
5646 assert(num_bytes
% 4 == 0);
5647 write_data
= bld
.as_uniform(data
);
5652 aco_opcode vmem_op
, smem_op
;
5653 switch (num_bytes
) {
5655 vmem_op
= aco_opcode::buffer_store_dword
;
5656 smem_op
= aco_opcode::s_buffer_store_dword
;
5659 vmem_op
= aco_opcode::buffer_store_dwordx2
;
5660 smem_op
= aco_opcode::s_buffer_store_dwordx2
;
5663 vmem_op
= aco_opcode::buffer_store_dwordx3
;
5664 smem_op
= aco_opcode::last_opcode
;
5665 assert(!smem
&& ctx
->options
->chip_class
> GFX6
);
5668 vmem_op
= aco_opcode::buffer_store_dwordx4
;
5669 smem_op
= aco_opcode::s_buffer_store_dwordx4
;
5672 unreachable("Store SSBO not implemented for this size.");
5674 if (ctx
->stage
== fragment_fs
)
5675 smem_op
= aco_opcode::p_fs_buffer_store_smem
;
5678 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(smem_op
, Format::SMEM
, 3, 0)};
5679 store
->operands
[0] = Operand(rsrc
);
5681 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5682 offset
, Operand(start
* elem_size_bytes
));
5683 store
->operands
[1] = Operand(off
);
5685 store
->operands
[1] = Operand(offset
);
5687 if (smem_op
!= aco_opcode::p_fs_buffer_store_smem
)
5688 store
->operands
[1].setFixed(m0
);
5689 store
->operands
[2] = Operand(write_data
);
5690 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
5692 store
->disable_wqm
= true;
5693 store
->barrier
= barrier_buffer
;
5694 ctx
->block
->instructions
.emplace_back(std::move(store
));
5695 ctx
->program
->wb_smem_l1_on_end
= true;
5696 if (smem_op
== aco_opcode::p_fs_buffer_store_smem
) {
5697 ctx
->block
->kind
|= block_kind_needs_lowering
;
5698 ctx
->program
->needs_exact
= true;
5701 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(vmem_op
, Format::MUBUF
, 4, 0)};
5702 store
->operands
[0] = Operand(rsrc
);
5703 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
5704 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
5705 store
->operands
[3] = Operand(write_data
);
5706 store
->offset
= start
* elem_size_bytes
;
5707 store
->offen
= (offset
.type() == RegType::vgpr
);
5708 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
5710 store
->disable_wqm
= true;
5711 store
->barrier
= barrier_buffer
;
5712 ctx
->program
->needs_exact
= true;
5713 ctx
->block
->instructions
.emplace_back(std::move(store
));
5718 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5720 /* return the previous value if dest is ever used */
5721 bool return_previous
= false;
5722 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5723 return_previous
= true;
5726 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5727 return_previous
= true;
5731 Builder
bld(ctx
->program
, ctx
->block
);
5732 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
5734 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
5735 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
5736 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
5738 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5739 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5740 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5742 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5744 aco_opcode op32
, op64
;
5745 switch (instr
->intrinsic
) {
5746 case nir_intrinsic_ssbo_atomic_add
:
5747 op32
= aco_opcode::buffer_atomic_add
;
5748 op64
= aco_opcode::buffer_atomic_add_x2
;
5750 case nir_intrinsic_ssbo_atomic_imin
:
5751 op32
= aco_opcode::buffer_atomic_smin
;
5752 op64
= aco_opcode::buffer_atomic_smin_x2
;
5754 case nir_intrinsic_ssbo_atomic_umin
:
5755 op32
= aco_opcode::buffer_atomic_umin
;
5756 op64
= aco_opcode::buffer_atomic_umin_x2
;
5758 case nir_intrinsic_ssbo_atomic_imax
:
5759 op32
= aco_opcode::buffer_atomic_smax
;
5760 op64
= aco_opcode::buffer_atomic_smax_x2
;
5762 case nir_intrinsic_ssbo_atomic_umax
:
5763 op32
= aco_opcode::buffer_atomic_umax
;
5764 op64
= aco_opcode::buffer_atomic_umax_x2
;
5766 case nir_intrinsic_ssbo_atomic_and
:
5767 op32
= aco_opcode::buffer_atomic_and
;
5768 op64
= aco_opcode::buffer_atomic_and_x2
;
5770 case nir_intrinsic_ssbo_atomic_or
:
5771 op32
= aco_opcode::buffer_atomic_or
;
5772 op64
= aco_opcode::buffer_atomic_or_x2
;
5774 case nir_intrinsic_ssbo_atomic_xor
:
5775 op32
= aco_opcode::buffer_atomic_xor
;
5776 op64
= aco_opcode::buffer_atomic_xor_x2
;
5778 case nir_intrinsic_ssbo_atomic_exchange
:
5779 op32
= aco_opcode::buffer_atomic_swap
;
5780 op64
= aco_opcode::buffer_atomic_swap_x2
;
5782 case nir_intrinsic_ssbo_atomic_comp_swap
:
5783 op32
= aco_opcode::buffer_atomic_cmpswap
;
5784 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
5787 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
5789 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
5790 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5791 mubuf
->operands
[0] = Operand(rsrc
);
5792 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
5793 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
5794 mubuf
->operands
[3] = Operand(data
);
5795 if (return_previous
)
5796 mubuf
->definitions
[0] = Definition(dst
);
5798 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
5799 mubuf
->glc
= return_previous
;
5800 mubuf
->dlc
= false; /* Not needed for atomics */
5801 mubuf
->disable_wqm
= true;
5802 mubuf
->barrier
= barrier_buffer
;
5803 ctx
->program
->needs_exact
= true;
5804 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5807 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
5809 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5810 Builder
bld(ctx
->program
, ctx
->block
);
5811 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
5812 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
5815 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
5817 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5818 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5820 if (addr
.type() == RegType::vgpr
)
5821 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
5822 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
5825 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5827 Builder
bld(ctx
->program
, ctx
->block
);
5828 unsigned num_components
= instr
->num_components
;
5829 unsigned num_bytes
= num_components
* instr
->dest
.ssa
.bit_size
/ 8;
5831 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5832 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5834 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5835 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
5837 if (dst
.type() == RegType::vgpr
|| (glc
&& ctx
->options
->chip_class
< GFX8
)) {
5838 bool global
= ctx
->options
->chip_class
>= GFX9
;
5840 if (ctx
->options
->chip_class
>= GFX7
) {
5842 switch (num_bytes
) {
5844 op
= global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
5847 op
= global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
5850 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
5853 op
= global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
5856 unreachable("load_global not implemented for this size.");
5859 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
5860 flat
->operands
[0] = Operand(addr
);
5861 flat
->operands
[1] = Operand(s1
);
5864 flat
->barrier
= barrier_buffer
;
5866 if (dst
.type() == RegType::sgpr
) {
5867 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
5868 flat
->definitions
[0] = Definition(vec
);
5869 ctx
->block
->instructions
.emplace_back(std::move(flat
));
5870 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
5872 flat
->definitions
[0] = Definition(dst
);
5873 ctx
->block
->instructions
.emplace_back(std::move(flat
));
5875 emit_split_vector(ctx
, dst
, num_components
);
5877 assert(ctx
->options
->chip_class
== GFX6
);
5879 /* GFX6 doesn't support loading vec3, expand to vec4. */
5880 num_bytes
= num_bytes
== 12 ? 16 : num_bytes
;
5883 switch (num_bytes
) {
5885 op
= aco_opcode::buffer_load_dword
;
5888 op
= aco_opcode::buffer_load_dwordx2
;
5891 op
= aco_opcode::buffer_load_dwordx4
;
5894 unreachable("load_global not implemented for this size.");
5897 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
5899 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
5900 mubuf
->operands
[0] = Operand(rsrc
);
5901 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
5902 mubuf
->operands
[2] = Operand(0u);
5906 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
5907 mubuf
->disable_wqm
= false;
5908 mubuf
->barrier
= barrier_buffer
;
5909 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
5912 if (dst
.size() == 3) {
5913 Temp vec
= bld
.tmp(v4
);
5914 instr
->definitions
[0] = Definition(vec
);
5915 bld
.insert(std::move(instr
));
5916 emit_split_vector(ctx
, vec
, 4);
5918 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 3, 1));
5919 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, vec
, 0, v1
));
5920 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, vec
, 1, v1
));
5921 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, vec
, 2, v1
));
5924 if (dst
.type() == RegType::sgpr
) {
5925 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
5926 instr
->definitions
[0] = Definition(vec
);
5927 bld
.insert(std::move(instr
));
5928 expand_vector(ctx
, vec
, dst
, num_components
, (1 << num_components
) - 1);
5929 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
5931 instr
->definitions
[0] = Definition(dst
);
5932 bld
.insert(std::move(instr
));
5933 emit_split_vector(ctx
, dst
, num_components
);
5937 switch (num_bytes
) {
5939 op
= aco_opcode::s_load_dword
;
5942 op
= aco_opcode::s_load_dwordx2
;
5946 op
= aco_opcode::s_load_dwordx4
;
5949 unreachable("load_global not implemented for this size.");
5951 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
5952 load
->operands
[0] = Operand(addr
);
5953 load
->operands
[1] = Operand(0u);
5954 load
->definitions
[0] = Definition(dst
);
5957 load
->barrier
= barrier_buffer
;
5958 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
5960 if (dst
.size() == 3) {
5962 Temp vec
= bld
.tmp(s4
);
5963 load
->definitions
[0] = Definition(vec
);
5964 ctx
->block
->instructions
.emplace_back(std::move(load
));
5965 emit_split_vector(ctx
, vec
, 4);
5967 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5968 emit_extract_vector(ctx
, vec
, 0, s1
),
5969 emit_extract_vector(ctx
, vec
, 1, s1
),
5970 emit_extract_vector(ctx
, vec
, 2, s1
));
5972 ctx
->block
->instructions
.emplace_back(std::move(load
));
5977 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5979 Builder
bld(ctx
->program
, ctx
->block
);
5980 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
5982 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5983 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5985 if (ctx
->options
->chip_class
>= GFX7
)
5986 addr
= as_vgpr(ctx
, addr
);
5988 unsigned writemask
= nir_intrinsic_write_mask(instr
);
5991 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
5992 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
5993 /* GFX6 doesn't support storing vec3, split it. */
5994 writemask
|= 1u << (start
+ 2);
5997 unsigned num_bytes
= count
* elem_size_bytes
;
5999 Temp write_data
= data
;
6000 if (count
!= instr
->num_components
) {
6001 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6002 for (int i
= 0; i
< count
; i
++)
6003 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, data
, start
+ i
, v1
));
6004 write_data
= bld
.tmp(RegType::vgpr
, count
);
6005 vec
->definitions
[0] = Definition(write_data
);
6006 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6009 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6010 unsigned offset
= start
* elem_size_bytes
;
6012 if (ctx
->options
->chip_class
>= GFX7
) {
6013 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6014 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6015 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6016 Temp carry
= bld
.tmp(bld
.lm
);
6017 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6019 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6020 Operand(offset
), addr0
);
6021 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6023 carry
).def(1).setHint(vcc
);
6025 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6030 bool global
= ctx
->options
->chip_class
>= GFX9
;
6032 switch (num_bytes
) {
6034 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6037 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6040 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6043 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6046 unreachable("store_global not implemented for this size.");
6049 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6050 flat
->operands
[0] = Operand(addr
);
6051 flat
->operands
[1] = Operand(s1
);
6052 flat
->operands
[2] = Operand(data
);
6055 flat
->offset
= offset
;
6056 flat
->disable_wqm
= true;
6057 flat
->barrier
= barrier_buffer
;
6058 ctx
->program
->needs_exact
= true;
6059 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6061 assert(ctx
->options
->chip_class
== GFX6
);
6064 switch (num_bytes
) {
6066 op
= aco_opcode::buffer_store_dword
;
6069 op
= aco_opcode::buffer_store_dwordx2
;
6072 op
= aco_opcode::buffer_store_dwordx4
;
6075 unreachable("store_global not implemented for this size.");
6078 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6080 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6081 mubuf
->operands
[0] = Operand(rsrc
);
6082 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6083 mubuf
->operands
[2] = Operand(0u);
6084 mubuf
->operands
[3] = Operand(write_data
);
6087 mubuf
->offset
= offset
;
6088 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6089 mubuf
->disable_wqm
= true;
6090 mubuf
->barrier
= barrier_buffer
;
6091 ctx
->program
->needs_exact
= true;
6092 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6097 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6099 /* return the previous value if dest is ever used */
6100 bool return_previous
= false;
6101 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6102 return_previous
= true;
6105 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6106 return_previous
= true;
6110 Builder
bld(ctx
->program
, ctx
->block
);
6111 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6112 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6114 if (ctx
->options
->chip_class
>= GFX7
)
6115 addr
= as_vgpr(ctx
, addr
);
6117 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6118 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6119 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6121 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6123 aco_opcode op32
, op64
;
6125 if (ctx
->options
->chip_class
>= GFX7
) {
6126 bool global
= ctx
->options
->chip_class
>= GFX9
;
6127 switch (instr
->intrinsic
) {
6128 case nir_intrinsic_global_atomic_add
:
6129 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6130 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6132 case nir_intrinsic_global_atomic_imin
:
6133 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6134 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6136 case nir_intrinsic_global_atomic_umin
:
6137 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6138 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6140 case nir_intrinsic_global_atomic_imax
:
6141 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6142 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6144 case nir_intrinsic_global_atomic_umax
:
6145 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6146 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6148 case nir_intrinsic_global_atomic_and
:
6149 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6150 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6152 case nir_intrinsic_global_atomic_or
:
6153 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6154 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6156 case nir_intrinsic_global_atomic_xor
:
6157 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6158 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6160 case nir_intrinsic_global_atomic_exchange
:
6161 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6162 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6164 case nir_intrinsic_global_atomic_comp_swap
:
6165 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6166 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6169 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6172 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6173 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6174 flat
->operands
[0] = Operand(addr
);
6175 flat
->operands
[1] = Operand(s1
);
6176 flat
->operands
[2] = Operand(data
);
6177 if (return_previous
)
6178 flat
->definitions
[0] = Definition(dst
);
6179 flat
->glc
= return_previous
;
6180 flat
->dlc
= false; /* Not needed for atomics */
6182 flat
->disable_wqm
= true;
6183 flat
->barrier
= barrier_buffer
;
6184 ctx
->program
->needs_exact
= true;
6185 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6187 assert(ctx
->options
->chip_class
== GFX6
);
6189 switch (instr
->intrinsic
) {
6190 case nir_intrinsic_global_atomic_add
:
6191 op32
= aco_opcode::buffer_atomic_add
;
6192 op64
= aco_opcode::buffer_atomic_add_x2
;
6194 case nir_intrinsic_global_atomic_imin
:
6195 op32
= aco_opcode::buffer_atomic_smin
;
6196 op64
= aco_opcode::buffer_atomic_smin_x2
;
6198 case nir_intrinsic_global_atomic_umin
:
6199 op32
= aco_opcode::buffer_atomic_umin
;
6200 op64
= aco_opcode::buffer_atomic_umin_x2
;
6202 case nir_intrinsic_global_atomic_imax
:
6203 op32
= aco_opcode::buffer_atomic_smax
;
6204 op64
= aco_opcode::buffer_atomic_smax_x2
;
6206 case nir_intrinsic_global_atomic_umax
:
6207 op32
= aco_opcode::buffer_atomic_umax
;
6208 op64
= aco_opcode::buffer_atomic_umax_x2
;
6210 case nir_intrinsic_global_atomic_and
:
6211 op32
= aco_opcode::buffer_atomic_and
;
6212 op64
= aco_opcode::buffer_atomic_and_x2
;
6214 case nir_intrinsic_global_atomic_or
:
6215 op32
= aco_opcode::buffer_atomic_or
;
6216 op64
= aco_opcode::buffer_atomic_or_x2
;
6218 case nir_intrinsic_global_atomic_xor
:
6219 op32
= aco_opcode::buffer_atomic_xor
;
6220 op64
= aco_opcode::buffer_atomic_xor_x2
;
6222 case nir_intrinsic_global_atomic_exchange
:
6223 op32
= aco_opcode::buffer_atomic_swap
;
6224 op64
= aco_opcode::buffer_atomic_swap_x2
;
6226 case nir_intrinsic_global_atomic_comp_swap
:
6227 op32
= aco_opcode::buffer_atomic_cmpswap
;
6228 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6231 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6234 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6236 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6238 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6239 mubuf
->operands
[0] = Operand(rsrc
);
6240 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6241 mubuf
->operands
[2] = Operand(0u);
6242 mubuf
->operands
[3] = Operand(data
);
6243 if (return_previous
)
6244 mubuf
->definitions
[0] = Definition(dst
);
6245 mubuf
->glc
= return_previous
;
6248 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6249 mubuf
->disable_wqm
= true;
6250 mubuf
->barrier
= barrier_buffer
;
6251 ctx
->program
->needs_exact
= true;
6252 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6256 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6257 Builder
bld(ctx
->program
, ctx
->block
);
6258 switch(instr
->intrinsic
) {
6259 case nir_intrinsic_group_memory_barrier
:
6260 case nir_intrinsic_memory_barrier
:
6261 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6263 case nir_intrinsic_memory_barrier_buffer
:
6264 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6266 case nir_intrinsic_memory_barrier_image
:
6267 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6269 case nir_intrinsic_memory_barrier_tcs_patch
:
6270 case nir_intrinsic_memory_barrier_shared
:
6271 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6274 unreachable("Unimplemented memory barrier intrinsic");
6279 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6281 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6282 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6283 assert(instr
->dest
.ssa
.bit_size
>= 32 && "Bitsize not supported in load_shared.");
6284 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6285 Builder
bld(ctx
->program
, ctx
->block
);
6287 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6288 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6289 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6292 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6294 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6295 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6296 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6297 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6298 assert(elem_size_bytes
>= 4 && "Only 32bit & 64bit store_shared currently supported.");
6300 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6301 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6304 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6306 unsigned offset
= nir_intrinsic_base(instr
);
6307 Operand m
= load_lds_size_m0(ctx
);
6308 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6309 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6311 unsigned num_operands
= 3;
6312 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6313 switch(instr
->intrinsic
) {
6314 case nir_intrinsic_shared_atomic_add
:
6315 op32
= aco_opcode::ds_add_u32
;
6316 op64
= aco_opcode::ds_add_u64
;
6317 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6318 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6320 case nir_intrinsic_shared_atomic_imin
:
6321 op32
= aco_opcode::ds_min_i32
;
6322 op64
= aco_opcode::ds_min_i64
;
6323 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6324 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6326 case nir_intrinsic_shared_atomic_umin
:
6327 op32
= aco_opcode::ds_min_u32
;
6328 op64
= aco_opcode::ds_min_u64
;
6329 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6330 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6332 case nir_intrinsic_shared_atomic_imax
:
6333 op32
= aco_opcode::ds_max_i32
;
6334 op64
= aco_opcode::ds_max_i64
;
6335 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6336 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6338 case nir_intrinsic_shared_atomic_umax
:
6339 op32
= aco_opcode::ds_max_u32
;
6340 op64
= aco_opcode::ds_max_u64
;
6341 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6342 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6344 case nir_intrinsic_shared_atomic_and
:
6345 op32
= aco_opcode::ds_and_b32
;
6346 op64
= aco_opcode::ds_and_b64
;
6347 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6348 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6350 case nir_intrinsic_shared_atomic_or
:
6351 op32
= aco_opcode::ds_or_b32
;
6352 op64
= aco_opcode::ds_or_b64
;
6353 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6354 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6356 case nir_intrinsic_shared_atomic_xor
:
6357 op32
= aco_opcode::ds_xor_b32
;
6358 op64
= aco_opcode::ds_xor_b64
;
6359 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6360 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6362 case nir_intrinsic_shared_atomic_exchange
:
6363 op32
= aco_opcode::ds_write_b32
;
6364 op64
= aco_opcode::ds_write_b64
;
6365 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6366 op64_rtn
= aco_opcode::ds_wrxchg2_rtn_b64
;
6368 case nir_intrinsic_shared_atomic_comp_swap
:
6369 op32
= aco_opcode::ds_cmpst_b32
;
6370 op64
= aco_opcode::ds_cmpst_b64
;
6371 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6372 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6376 unreachable("Unhandled shared atomic intrinsic");
6379 /* return the previous value if dest is ever used */
6380 bool return_previous
= false;
6381 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6382 return_previous
= true;
6385 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6386 return_previous
= true;
6391 if (data
.size() == 1) {
6392 assert(instr
->dest
.ssa
.bit_size
== 32);
6393 op
= return_previous
? op32_rtn
: op32
;
6395 assert(instr
->dest
.ssa
.bit_size
== 64);
6396 op
= return_previous
? op64_rtn
: op64
;
6399 if (offset
> 65535) {
6400 Builder
bld(ctx
->program
, ctx
->block
);
6401 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6405 aco_ptr
<DS_instruction
> ds
;
6406 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6407 ds
->operands
[0] = Operand(address
);
6408 ds
->operands
[1] = Operand(data
);
6409 if (num_operands
== 4)
6410 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6411 ds
->operands
[num_operands
- 1] = m
;
6412 ds
->offset0
= offset
;
6413 if (return_previous
)
6414 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6415 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6418 Temp
get_scratch_resource(isel_context
*ctx
)
6420 Builder
bld(ctx
->program
, ctx
->block
);
6421 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6422 if (ctx
->stage
!= compute_cs
)
6423 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6425 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6426 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6428 if (ctx
->program
->chip_class
>= GFX10
) {
6429 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6430 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6431 S_008F0C_RESOURCE_LEVEL(1);
6432 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6433 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6434 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6437 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6438 if (ctx
->program
->chip_class
<= GFX8
)
6439 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6441 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6444 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6445 assert(instr
->dest
.ssa
.bit_size
== 32 || instr
->dest
.ssa
.bit_size
== 64);
6446 Builder
bld(ctx
->program
, ctx
->block
);
6447 Temp rsrc
= get_scratch_resource(ctx
);
6448 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6449 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6452 switch (dst
.size()) {
6454 op
= aco_opcode::buffer_load_dword
;
6457 op
= aco_opcode::buffer_load_dwordx2
;
6460 op
= aco_opcode::buffer_load_dwordx3
;
6463 op
= aco_opcode::buffer_load_dwordx4
;
6467 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
6468 Temp lower
= bld
.mubuf(aco_opcode::buffer_load_dwordx4
,
6469 bld
.def(v4
), rsrc
, offset
,
6470 ctx
->program
->scratch_offset
, 0, true);
6471 Temp upper
= bld
.mubuf(dst
.size() == 6 ? aco_opcode::buffer_load_dwordx2
:
6472 aco_opcode::buffer_load_dwordx4
,
6473 dst
.size() == 6 ? bld
.def(v2
) : bld
.def(v4
),
6474 rsrc
, offset
, ctx
->program
->scratch_offset
, 16, true);
6475 emit_split_vector(ctx
, lower
, 2);
6476 elems
[0] = emit_extract_vector(ctx
, lower
, 0, v2
);
6477 elems
[1] = emit_extract_vector(ctx
, lower
, 1, v2
);
6478 if (dst
.size() == 8) {
6479 emit_split_vector(ctx
, upper
, 2);
6480 elems
[2] = emit_extract_vector(ctx
, upper
, 0, v2
);
6481 elems
[3] = emit_extract_vector(ctx
, upper
, 1, v2
);
6486 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
6487 Format::PSEUDO
, dst
.size() / 2, 1)};
6488 for (unsigned i
= 0; i
< dst
.size() / 2; i
++)
6489 vec
->operands
[i
] = Operand(elems
[i
]);
6490 vec
->definitions
[0] = Definition(dst
);
6491 bld
.insert(std::move(vec
));
6492 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
6496 unreachable("Wrong dst size for nir_intrinsic_load_scratch");
6499 bld
.mubuf(op
, Definition(dst
), rsrc
, offset
, ctx
->program
->scratch_offset
, 0, true);
6500 emit_split_vector(ctx
, dst
, instr
->num_components
);
6503 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6504 assert(instr
->src
[0].ssa
->bit_size
== 32 || instr
->src
[0].ssa
->bit_size
== 64);
6505 Builder
bld(ctx
->program
, ctx
->block
);
6506 Temp rsrc
= get_scratch_resource(ctx
);
6507 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6508 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6510 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6511 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6515 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
6516 int num_bytes
= count
* elem_size_bytes
;
6518 if (num_bytes
> 16) {
6519 assert(elem_size_bytes
== 8);
6520 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
6525 // TODO: check alignment of sub-dword stores
6526 // TODO: split 3 bytes. there is no store instruction for that
6529 if (count
!= instr
->num_components
) {
6530 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6531 for (int i
= 0; i
< count
; i
++) {
6532 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(RegType::vgpr
, elem_size_bytes
/ 4));
6533 vec
->operands
[i
] = Operand(elem
);
6535 write_data
= bld
.tmp(RegClass(RegType::vgpr
, count
* elem_size_bytes
/ 4));
6536 vec
->definitions
[0] = Definition(write_data
);
6537 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6543 switch (num_bytes
) {
6545 op
= aco_opcode::buffer_store_dword
;
6548 op
= aco_opcode::buffer_store_dwordx2
;
6551 op
= aco_opcode::buffer_store_dwordx3
;
6554 op
= aco_opcode::buffer_store_dwordx4
;
6557 unreachable("Invalid data size for nir_intrinsic_store_scratch.");
6560 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_data
, start
* elem_size_bytes
, true);
6564 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6565 uint8_t log2_ps_iter_samples
;
6566 if (ctx
->program
->info
->ps
.force_persample
) {
6567 log2_ps_iter_samples
=
6568 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6570 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6573 /* The bit pattern matches that used by fixed function fragment
6575 static const unsigned ps_iter_masks
[] = {
6576 0xffff, /* not used */
6582 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6584 Builder
bld(ctx
->program
, ctx
->block
);
6586 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6587 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6588 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6589 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6590 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6591 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6594 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6595 Builder
bld(ctx
->program
, ctx
->block
);
6597 unsigned stream
= nir_intrinsic_stream_id(instr
);
6598 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6599 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6600 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6603 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6605 unsigned num_components
=
6606 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6607 assert(num_components
);
6609 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6610 unsigned stream_offset
= 0;
6611 for (unsigned i
= 0; i
< stream
; i
++) {
6612 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6613 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6616 /* Limit on the stride field for <= GFX7. */
6617 assert(stride
< (1 << 14));
6619 Temp gsvs_dwords
[4];
6620 for (unsigned i
= 0; i
< 4; i
++)
6621 gsvs_dwords
[i
] = bld
.tmp(s1
);
6622 bld
.pseudo(aco_opcode::p_split_vector
,
6623 Definition(gsvs_dwords
[0]),
6624 Definition(gsvs_dwords
[1]),
6625 Definition(gsvs_dwords
[2]),
6626 Definition(gsvs_dwords
[3]),
6629 if (stream_offset
) {
6630 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6632 Temp carry
= bld
.tmp(s1
);
6633 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6634 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6637 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6638 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6640 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6641 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6643 unsigned offset
= 0;
6644 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6645 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6648 for (unsigned j
= 0; j
< 4; j
++) {
6649 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6652 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6653 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6654 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6655 if (const_offset
>= 4096u) {
6656 if (vaddr_offset
.isUndefined())
6657 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6659 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6660 const_offset
%= 4096u;
6663 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6664 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6665 mtbuf
->operands
[1] = vaddr_offset
;
6666 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6667 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6668 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6669 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6670 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6671 mtbuf
->offset
= const_offset
;
6674 mtbuf
->barrier
= barrier_gs_data
;
6675 mtbuf
->can_reorder
= true;
6676 bld
.insert(std::move(mtbuf
));
6679 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6682 /* outputs for the next vertex are undefined and keeping them around can
6683 * create invalid IR with control flow */
6684 ctx
->outputs
.mask
[i
] = 0;
6687 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6690 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6692 Builder
bld(ctx
->program
, ctx
->block
);
6694 if (cluster_size
== 1) {
6696 } if (op
== nir_op_iand
&& cluster_size
== 4) {
6697 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6698 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6699 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6700 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
6701 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
6702 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6703 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6704 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
6705 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
6706 //subgroupAnd(val) -> (exec & ~val) == 0
6707 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
6708 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
6709 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
6710 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
6711 //subgroupOr(val) -> (val & exec) != 0
6712 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
6713 return bool_to_vector_condition(ctx
, tmp
);
6714 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
6715 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6716 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6717 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
6718 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
6719 return bool_to_vector_condition(ctx
, tmp
);
6721 //subgroupClustered{And,Or,Xor}(val, n) ->
6722 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
6723 //cluster_offset = ~(n - 1) & lane_id
6724 //cluster_mask = ((1 << n) - 1)
6725 //subgroupClusteredAnd():
6726 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6727 //subgroupClusteredOr():
6728 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
6729 //subgroupClusteredXor():
6730 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6731 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
6732 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
6735 if (op
== nir_op_iand
)
6736 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6738 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6740 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
6742 if (ctx
->program
->chip_class
<= GFX7
)
6743 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
6744 else if (ctx
->program
->wave_size
== 64)
6745 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
6747 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
6748 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
6749 if (cluster_mask
!= 0xffffffff)
6750 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
6752 Definition cmp_def
= Definition();
6753 if (op
== nir_op_iand
) {
6754 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
6755 } else if (op
== nir_op_ior
) {
6756 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6757 } else if (op
== nir_op_ixor
) {
6758 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
6759 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
6760 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6762 cmp_def
.setHint(vcc
);
6763 return cmp_def
.getTemp();
6767 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
6769 Builder
bld(ctx
->program
, ctx
->block
);
6771 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
6772 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
6773 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
6775 if (op
== nir_op_iand
)
6776 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6778 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6780 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
6781 Temp lo
= lohi
.def(0).getTemp();
6782 Temp hi
= lohi
.def(1).getTemp();
6783 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
6785 Definition cmp_def
= Definition();
6786 if (op
== nir_op_iand
)
6787 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
6788 else if (op
== nir_op_ior
)
6789 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
6790 else if (op
== nir_op_ixor
)
6791 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
6792 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
6793 cmp_def
.setHint(vcc
);
6794 return cmp_def
.getTemp();
6797 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
6799 Builder
bld(ctx
->program
, ctx
->block
);
6801 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
6802 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
6803 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
6804 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
6805 if (op
== nir_op_iand
)
6806 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
6807 else if (op
== nir_op_ior
)
6808 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
6809 else if (op
== nir_op_ixor
)
6810 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
6816 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
6818 Builder
bld(ctx
->program
, ctx
->block
);
6819 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6820 if (src
.regClass().type() == RegType::vgpr
) {
6821 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
6822 } else if (src
.regClass() == s1
) {
6823 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
6824 } else if (src
.regClass() == s2
) {
6825 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
6827 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
6828 nir_print_instr(&instr
->instr
, stderr
);
6829 fprintf(stderr
, "\n");
6833 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
6835 Builder
bld(ctx
->program
, ctx
->block
);
6836 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
6837 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
6838 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
6840 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
6841 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
6842 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
6843 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
6846 if (ctx
->program
->chip_class
>= GFX8
) {
6847 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
6848 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
6849 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
6850 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
6851 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
6852 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
6854 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
6855 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
6856 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
6857 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
6858 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
6859 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
6860 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
6861 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
6862 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
6863 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
6866 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
6867 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
6868 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
6869 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
6870 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
6871 Temp wqm1
= bld
.tmp(v1
);
6872 emit_wqm(ctx
, tmp1
, wqm1
, true);
6873 Temp wqm2
= bld
.tmp(v1
);
6874 emit_wqm(ctx
, tmp2
, wqm2
, true);
6875 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
6879 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6881 Builder
bld(ctx
->program
, ctx
->block
);
6882 switch(instr
->intrinsic
) {
6883 case nir_intrinsic_load_barycentric_sample
:
6884 case nir_intrinsic_load_barycentric_pixel
:
6885 case nir_intrinsic_load_barycentric_centroid
: {
6886 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
6887 Temp bary
= Temp(0, s2
);
6889 case INTERP_MODE_SMOOTH
:
6890 case INTERP_MODE_NONE
:
6891 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
6892 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
6893 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
6894 bary
= ctx
->persp_centroid
;
6895 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
6896 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
6898 case INTERP_MODE_NOPERSPECTIVE
:
6899 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
6900 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
6901 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
6902 bary
= ctx
->linear_centroid
;
6903 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
6904 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
6909 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6910 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
6911 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
6912 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6913 Operand(p1
), Operand(p2
));
6914 emit_split_vector(ctx
, dst
, 2);
6917 case nir_intrinsic_load_barycentric_model
: {
6918 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
6920 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6921 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
6922 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
6923 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
6924 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6925 Operand(p1
), Operand(p2
), Operand(p3
));
6926 emit_split_vector(ctx
, dst
, 3);
6929 case nir_intrinsic_load_barycentric_at_sample
: {
6930 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
6931 switch (ctx
->options
->key
.fs
.num_samples
) {
6932 case 2: sample_pos_offset
+= 1 << 3; break;
6933 case 4: sample_pos_offset
+= 3 << 3; break;
6934 case 8: sample_pos_offset
+= 7 << 3; break;
6938 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6939 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
6940 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
6941 if (addr
.type() == RegType::sgpr
) {
6944 sample_pos_offset
+= const_addr
->u32
<< 3;
6945 offset
= Operand(sample_pos_offset
);
6946 } else if (ctx
->options
->chip_class
>= GFX9
) {
6947 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
6949 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
6950 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
6953 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
6954 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
6956 } else if (ctx
->options
->chip_class
>= GFX9
) {
6957 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
6958 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
6959 } else if (ctx
->options
->chip_class
>= GFX7
) {
6960 /* addr += private_segment_buffer + sample_pos_offset */
6961 Temp tmp0
= bld
.tmp(s1
);
6962 Temp tmp1
= bld
.tmp(s1
);
6963 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
6964 Definition scc_tmp
= bld
.def(s1
, scc
);
6965 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
6966 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
6967 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
6968 Temp pck0
= bld
.tmp(v1
);
6969 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
6970 tmp1
= as_vgpr(ctx
, tmp1
);
6971 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
6972 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
6974 /* sample_pos = flat_load_dwordx2 addr */
6975 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
6977 assert(ctx
->options
->chip_class
== GFX6
);
6979 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6980 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6981 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
6983 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
6984 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
6986 sample_pos
= bld
.tmp(v2
);
6988 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
6989 load
->definitions
[0] = Definition(sample_pos
);
6990 load
->operands
[0] = Operand(rsrc
);
6991 load
->operands
[1] = Operand(addr
);
6992 load
->operands
[2] = Operand(0u);
6993 load
->offset
= sample_pos_offset
;
6995 load
->addr64
= true;
6998 load
->disable_wqm
= false;
6999 load
->barrier
= barrier_none
;
7000 load
->can_reorder
= true;
7001 ctx
->block
->instructions
.emplace_back(std::move(load
));
7004 /* sample_pos -= 0.5 */
7005 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7006 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7007 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7008 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7009 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7011 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7014 case nir_intrinsic_load_barycentric_at_offset
: {
7015 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7016 RegClass rc
= RegClass(offset
.type(), 1);
7017 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7018 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7019 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7022 case nir_intrinsic_load_front_face
: {
7023 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7024 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7027 case nir_intrinsic_load_view_index
: {
7028 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7029 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7030 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7036 case nir_intrinsic_load_layer_id
: {
7037 unsigned idx
= nir_intrinsic_base(instr
);
7038 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7039 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7042 case nir_intrinsic_load_frag_coord
: {
7043 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7046 case nir_intrinsic_load_sample_pos
: {
7047 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7048 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7049 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7050 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7051 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7054 case nir_intrinsic_load_tess_coord
:
7055 visit_load_tess_coord(ctx
, instr
);
7057 case nir_intrinsic_load_interpolated_input
:
7058 visit_load_interpolated_input(ctx
, instr
);
7060 case nir_intrinsic_store_output
:
7061 visit_store_output(ctx
, instr
);
7063 case nir_intrinsic_load_input
:
7064 case nir_intrinsic_load_input_vertex
:
7065 visit_load_input(ctx
, instr
);
7067 case nir_intrinsic_load_output
:
7068 visit_load_output(ctx
, instr
);
7070 case nir_intrinsic_load_per_vertex_input
:
7071 visit_load_per_vertex_input(ctx
, instr
);
7073 case nir_intrinsic_load_per_vertex_output
:
7074 visit_load_per_vertex_output(ctx
, instr
);
7076 case nir_intrinsic_store_per_vertex_output
:
7077 visit_store_per_vertex_output(ctx
, instr
);
7079 case nir_intrinsic_load_ubo
:
7080 visit_load_ubo(ctx
, instr
);
7082 case nir_intrinsic_load_push_constant
:
7083 visit_load_push_constant(ctx
, instr
);
7085 case nir_intrinsic_load_constant
:
7086 visit_load_constant(ctx
, instr
);
7088 case nir_intrinsic_vulkan_resource_index
:
7089 visit_load_resource(ctx
, instr
);
7091 case nir_intrinsic_discard
:
7092 visit_discard(ctx
, instr
);
7094 case nir_intrinsic_discard_if
:
7095 visit_discard_if(ctx
, instr
);
7097 case nir_intrinsic_load_shared
:
7098 visit_load_shared(ctx
, instr
);
7100 case nir_intrinsic_store_shared
:
7101 visit_store_shared(ctx
, instr
);
7103 case nir_intrinsic_shared_atomic_add
:
7104 case nir_intrinsic_shared_atomic_imin
:
7105 case nir_intrinsic_shared_atomic_umin
:
7106 case nir_intrinsic_shared_atomic_imax
:
7107 case nir_intrinsic_shared_atomic_umax
:
7108 case nir_intrinsic_shared_atomic_and
:
7109 case nir_intrinsic_shared_atomic_or
:
7110 case nir_intrinsic_shared_atomic_xor
:
7111 case nir_intrinsic_shared_atomic_exchange
:
7112 case nir_intrinsic_shared_atomic_comp_swap
:
7113 visit_shared_atomic(ctx
, instr
);
7115 case nir_intrinsic_image_deref_load
:
7116 visit_image_load(ctx
, instr
);
7118 case nir_intrinsic_image_deref_store
:
7119 visit_image_store(ctx
, instr
);
7121 case nir_intrinsic_image_deref_atomic_add
:
7122 case nir_intrinsic_image_deref_atomic_umin
:
7123 case nir_intrinsic_image_deref_atomic_imin
:
7124 case nir_intrinsic_image_deref_atomic_umax
:
7125 case nir_intrinsic_image_deref_atomic_imax
:
7126 case nir_intrinsic_image_deref_atomic_and
:
7127 case nir_intrinsic_image_deref_atomic_or
:
7128 case nir_intrinsic_image_deref_atomic_xor
:
7129 case nir_intrinsic_image_deref_atomic_exchange
:
7130 case nir_intrinsic_image_deref_atomic_comp_swap
:
7131 visit_image_atomic(ctx
, instr
);
7133 case nir_intrinsic_image_deref_size
:
7134 visit_image_size(ctx
, instr
);
7136 case nir_intrinsic_load_ssbo
:
7137 visit_load_ssbo(ctx
, instr
);
7139 case nir_intrinsic_store_ssbo
:
7140 visit_store_ssbo(ctx
, instr
);
7142 case nir_intrinsic_load_global
:
7143 visit_load_global(ctx
, instr
);
7145 case nir_intrinsic_store_global
:
7146 visit_store_global(ctx
, instr
);
7148 case nir_intrinsic_global_atomic_add
:
7149 case nir_intrinsic_global_atomic_imin
:
7150 case nir_intrinsic_global_atomic_umin
:
7151 case nir_intrinsic_global_atomic_imax
:
7152 case nir_intrinsic_global_atomic_umax
:
7153 case nir_intrinsic_global_atomic_and
:
7154 case nir_intrinsic_global_atomic_or
:
7155 case nir_intrinsic_global_atomic_xor
:
7156 case nir_intrinsic_global_atomic_exchange
:
7157 case nir_intrinsic_global_atomic_comp_swap
:
7158 visit_global_atomic(ctx
, instr
);
7160 case nir_intrinsic_ssbo_atomic_add
:
7161 case nir_intrinsic_ssbo_atomic_imin
:
7162 case nir_intrinsic_ssbo_atomic_umin
:
7163 case nir_intrinsic_ssbo_atomic_imax
:
7164 case nir_intrinsic_ssbo_atomic_umax
:
7165 case nir_intrinsic_ssbo_atomic_and
:
7166 case nir_intrinsic_ssbo_atomic_or
:
7167 case nir_intrinsic_ssbo_atomic_xor
:
7168 case nir_intrinsic_ssbo_atomic_exchange
:
7169 case nir_intrinsic_ssbo_atomic_comp_swap
:
7170 visit_atomic_ssbo(ctx
, instr
);
7172 case nir_intrinsic_load_scratch
:
7173 visit_load_scratch(ctx
, instr
);
7175 case nir_intrinsic_store_scratch
:
7176 visit_store_scratch(ctx
, instr
);
7178 case nir_intrinsic_get_buffer_size
:
7179 visit_get_buffer_size(ctx
, instr
);
7181 case nir_intrinsic_control_barrier
: {
7182 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7183 /* GFX6 only (thanks to a hw bug workaround):
7184 * The real barrier instruction isn’t needed, because an entire patch
7185 * always fits into a single wave.
7190 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7191 bld
.sopp(aco_opcode::s_barrier
);
7195 case nir_intrinsic_memory_barrier_tcs_patch
:
7196 case nir_intrinsic_group_memory_barrier
:
7197 case nir_intrinsic_memory_barrier
:
7198 case nir_intrinsic_memory_barrier_buffer
:
7199 case nir_intrinsic_memory_barrier_image
:
7200 case nir_intrinsic_memory_barrier_shared
:
7201 emit_memory_barrier(ctx
, instr
);
7203 case nir_intrinsic_load_num_work_groups
: {
7204 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7205 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7206 emit_split_vector(ctx
, dst
, 3);
7209 case nir_intrinsic_load_local_invocation_id
: {
7210 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7211 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7212 emit_split_vector(ctx
, dst
, 3);
7215 case nir_intrinsic_load_work_group_id
: {
7216 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7217 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7218 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7219 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7220 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7221 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7222 emit_split_vector(ctx
, dst
, 3);
7225 case nir_intrinsic_load_local_invocation_index
: {
7226 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7228 /* The tg_size bits [6:11] contain the subgroup id,
7229 * we need this multiplied by the wave size, and then OR the thread id to it.
7231 if (ctx
->program
->wave_size
== 64) {
7232 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7233 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7234 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7235 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7237 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7238 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7239 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7240 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7244 case nir_intrinsic_load_subgroup_id
: {
7245 if (ctx
->stage
== compute_cs
) {
7246 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7247 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7249 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7253 case nir_intrinsic_load_subgroup_invocation
: {
7254 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7257 case nir_intrinsic_load_num_subgroups
: {
7258 if (ctx
->stage
== compute_cs
)
7259 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7260 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7262 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7265 case nir_intrinsic_ballot
: {
7266 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7267 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7268 Definition tmp
= bld
.def(dst
.regClass());
7269 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7270 if (instr
->src
[0].ssa
->bit_size
== 1) {
7271 assert(src
.regClass() == bld
.lm
);
7272 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7273 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7274 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7275 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7276 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7278 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7279 nir_print_instr(&instr
->instr
, stderr
);
7280 fprintf(stderr
, "\n");
7282 if (dst
.size() != bld
.lm
.size()) {
7283 /* Wave32 with ballot size set to 64 */
7284 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7286 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7289 case nir_intrinsic_shuffle
:
7290 case nir_intrinsic_read_invocation
: {
7291 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7292 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
]) {
7293 emit_uniform_subgroup(ctx
, instr
, src
);
7295 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7296 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !ctx
->divergent_vals
[instr
->src
[1].ssa
->index
])
7297 tid
= bld
.as_uniform(tid
);
7298 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7299 if (src
.regClass() == v1
) {
7300 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7301 } else if (src
.regClass() == v2
) {
7302 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7303 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7304 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7305 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7306 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7307 emit_split_vector(ctx
, dst
, 2);
7308 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7309 assert(src
.regClass() == bld
.lm
);
7310 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7311 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7312 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7313 assert(src
.regClass() == bld
.lm
);
7315 if (ctx
->program
->chip_class
<= GFX7
)
7316 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7317 else if (ctx
->program
->wave_size
== 64)
7318 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7320 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7321 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7322 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7323 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7325 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7326 nir_print_instr(&instr
->instr
, stderr
);
7327 fprintf(stderr
, "\n");
7332 case nir_intrinsic_load_sample_id
: {
7333 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7334 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7337 case nir_intrinsic_load_sample_mask_in
: {
7338 visit_load_sample_mask_in(ctx
, instr
);
7341 case nir_intrinsic_read_first_invocation
: {
7342 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7343 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7344 if (src
.regClass() == v1
) {
7346 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7348 } else if (src
.regClass() == v2
) {
7349 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7350 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7351 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7352 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7353 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7354 emit_split_vector(ctx
, dst
, 2);
7355 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7356 assert(src
.regClass() == bld
.lm
);
7357 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7358 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7359 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7360 } else if (src
.regClass() == s1
) {
7361 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7362 } else if (src
.regClass() == s2
) {
7363 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7365 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7366 nir_print_instr(&instr
->instr
, stderr
);
7367 fprintf(stderr
, "\n");
7371 case nir_intrinsic_vote_all
: {
7372 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7373 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7374 assert(src
.regClass() == bld
.lm
);
7375 assert(dst
.regClass() == bld
.lm
);
7377 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7378 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7379 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7382 case nir_intrinsic_vote_any
: {
7383 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7384 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7385 assert(src
.regClass() == bld
.lm
);
7386 assert(dst
.regClass() == bld
.lm
);
7388 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7389 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7392 case nir_intrinsic_reduce
:
7393 case nir_intrinsic_inclusive_scan
:
7394 case nir_intrinsic_exclusive_scan
: {
7395 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7396 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7397 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7398 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7399 nir_intrinsic_cluster_size(instr
) : 0;
7400 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7402 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
] && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7403 emit_uniform_subgroup(ctx
, instr
, src
);
7404 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7405 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7407 else if (op
== nir_op_iadd
)
7409 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7411 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7413 switch (instr
->intrinsic
) {
7414 case nir_intrinsic_reduce
:
7415 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7417 case nir_intrinsic_exclusive_scan
:
7418 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7420 case nir_intrinsic_inclusive_scan
:
7421 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7426 } else if (cluster_size
== 1) {
7427 bld
.copy(Definition(dst
), src
);
7429 src
= as_vgpr(ctx
, src
);
7433 #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
7448 unreachable("unknown reduction op");
7453 switch (instr
->intrinsic
) {
7454 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7455 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7456 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7458 unreachable("unknown reduce intrinsic");
7461 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7462 reduce
->operands
[0] = Operand(src
);
7463 // filled in by aco_reduce_assign.cpp, used internally as part of the
7465 assert(dst
.size() == 1 || dst
.size() == 2);
7466 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7467 reduce
->operands
[2] = Operand(v1
.as_linear());
7469 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7470 reduce
->definitions
[0] = Definition(tmp_dst
);
7471 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7472 reduce
->definitions
[2] = Definition();
7473 reduce
->definitions
[3] = Definition(scc
, s1
);
7474 reduce
->definitions
[4] = Definition();
7475 reduce
->reduce_op
= reduce_op
;
7476 reduce
->cluster_size
= cluster_size
;
7477 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7479 emit_wqm(ctx
, tmp_dst
, dst
);
7483 case nir_intrinsic_quad_broadcast
: {
7484 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7485 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7486 emit_uniform_subgroup(ctx
, instr
, src
);
7488 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7489 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7490 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7492 if (instr
->dest
.ssa
.bit_size
== 1) {
7493 assert(src
.regClass() == bld
.lm
);
7494 assert(dst
.regClass() == bld
.lm
);
7495 uint32_t half_mask
= 0x11111111u
<< lane
;
7496 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7497 Temp tmp
= bld
.tmp(bld
.lm
);
7498 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7499 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7500 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7501 emit_wqm(ctx
, tmp
, dst
);
7502 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7503 if (ctx
->program
->chip_class
>= GFX8
)
7504 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7506 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7507 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7508 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7509 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7510 if (ctx
->program
->chip_class
>= GFX8
) {
7511 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7512 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7514 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7515 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7517 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7518 emit_split_vector(ctx
, dst
, 2);
7520 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7521 nir_print_instr(&instr
->instr
, stderr
);
7522 fprintf(stderr
, "\n");
7527 case nir_intrinsic_quad_swap_horizontal
:
7528 case nir_intrinsic_quad_swap_vertical
:
7529 case nir_intrinsic_quad_swap_diagonal
:
7530 case nir_intrinsic_quad_swizzle_amd
: {
7531 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7532 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7533 emit_uniform_subgroup(ctx
, instr
, src
);
7536 uint16_t dpp_ctrl
= 0;
7537 switch (instr
->intrinsic
) {
7538 case nir_intrinsic_quad_swap_horizontal
:
7539 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7541 case nir_intrinsic_quad_swap_vertical
:
7542 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7544 case nir_intrinsic_quad_swap_diagonal
:
7545 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7547 case nir_intrinsic_quad_swizzle_amd
:
7548 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7553 if (ctx
->program
->chip_class
< GFX8
)
7554 dpp_ctrl
|= (1 << 15);
7556 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7557 if (instr
->dest
.ssa
.bit_size
== 1) {
7558 assert(src
.regClass() == bld
.lm
);
7559 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7560 if (ctx
->program
->chip_class
>= GFX8
)
7561 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7563 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7564 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7565 emit_wqm(ctx
, tmp
, dst
);
7566 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7568 if (ctx
->program
->chip_class
>= GFX8
)
7569 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7571 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7572 emit_wqm(ctx
, tmp
, dst
);
7573 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7574 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7575 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7576 if (ctx
->program
->chip_class
>= GFX8
) {
7577 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7578 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7580 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7581 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7583 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7584 emit_split_vector(ctx
, dst
, 2);
7586 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7587 nir_print_instr(&instr
->instr
, stderr
);
7588 fprintf(stderr
, "\n");
7592 case nir_intrinsic_masked_swizzle_amd
: {
7593 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7594 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7595 emit_uniform_subgroup(ctx
, instr
, src
);
7598 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7599 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7600 if (dst
.regClass() == v1
) {
7602 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
7604 } else if (dst
.regClass() == v2
) {
7605 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7606 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7607 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
7608 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
7609 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7610 emit_split_vector(ctx
, dst
, 2);
7612 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7613 nir_print_instr(&instr
->instr
, stderr
);
7614 fprintf(stderr
, "\n");
7618 case nir_intrinsic_write_invocation_amd
: {
7619 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7620 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7621 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7622 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7623 if (dst
.regClass() == v1
) {
7624 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7625 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7626 } else if (dst
.regClass() == v2
) {
7627 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7628 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7629 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7630 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7631 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7632 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7633 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7634 emit_split_vector(ctx
, dst
, 2);
7636 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7637 nir_print_instr(&instr
->instr
, stderr
);
7638 fprintf(stderr
, "\n");
7642 case nir_intrinsic_mbcnt_amd
: {
7643 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7644 RegClass rc
= RegClass(src
.type(), 1);
7645 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7646 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7647 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7648 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7649 emit_wqm(ctx
, wqm_tmp
, dst
);
7652 case nir_intrinsic_load_helper_invocation
: {
7653 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7654 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7655 ctx
->block
->kind
|= block_kind_needs_lowering
;
7656 ctx
->program
->needs_exact
= true;
7659 case nir_intrinsic_is_helper_invocation
: {
7660 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7661 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7662 ctx
->block
->kind
|= block_kind_needs_lowering
;
7663 ctx
->program
->needs_exact
= true;
7666 case nir_intrinsic_demote
:
7667 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7669 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7670 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7671 ctx
->block
->kind
|= block_kind_uses_demote
;
7672 ctx
->program
->needs_exact
= true;
7674 case nir_intrinsic_demote_if
: {
7675 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7676 assert(src
.regClass() == bld
.lm
);
7677 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7678 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
7680 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7681 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7682 ctx
->block
->kind
|= block_kind_uses_demote
;
7683 ctx
->program
->needs_exact
= true;
7686 case nir_intrinsic_first_invocation
: {
7687 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
7688 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7691 case nir_intrinsic_shader_clock
:
7692 bld
.smem(aco_opcode::s_memtime
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
7693 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
7695 case nir_intrinsic_load_vertex_id_zero_base
: {
7696 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7697 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
7700 case nir_intrinsic_load_first_vertex
: {
7701 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7702 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
7705 case nir_intrinsic_load_base_instance
: {
7706 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7707 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
7710 case nir_intrinsic_load_instance_id
: {
7711 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7712 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
7715 case nir_intrinsic_load_draw_id
: {
7716 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7717 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
7720 case nir_intrinsic_load_invocation_id
: {
7721 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7723 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
7724 if (ctx
->options
->chip_class
>= GFX10
)
7725 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7727 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7728 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7729 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
7730 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
7732 unreachable("Unsupported stage for load_invocation_id");
7737 case nir_intrinsic_load_primitive_id
: {
7738 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7740 switch (ctx
->shader
->info
.stage
) {
7741 case MESA_SHADER_GEOMETRY
:
7742 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
7744 case MESA_SHADER_TESS_CTRL
:
7745 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
7747 case MESA_SHADER_TESS_EVAL
:
7748 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
7751 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
7756 case nir_intrinsic_load_patch_vertices_in
: {
7757 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
7758 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
7760 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7761 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
7764 case nir_intrinsic_emit_vertex_with_counter
: {
7765 visit_emit_vertex_with_counter(ctx
, instr
);
7768 case nir_intrinsic_end_primitive_with_counter
: {
7769 unsigned stream
= nir_intrinsic_stream_id(instr
);
7770 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
7773 case nir_intrinsic_set_vertex_count
: {
7774 /* unused, the HW keeps track of this for us */
7778 fprintf(stderr
, "Unimplemented intrinsic instr: ");
7779 nir_print_instr(&instr
->instr
, stderr
);
7780 fprintf(stderr
, "\n");
7788 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
7789 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
7790 enum glsl_base_type
*stype
)
7792 nir_deref_instr
*texture_deref_instr
= NULL
;
7793 nir_deref_instr
*sampler_deref_instr
= NULL
;
7796 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
7797 switch (instr
->src
[i
].src_type
) {
7798 case nir_tex_src_texture_deref
:
7799 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
7801 case nir_tex_src_sampler_deref
:
7802 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
7804 case nir_tex_src_plane
:
7805 plane
= nir_src_as_int(instr
->src
[i
].src
);
7812 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
7814 if (!sampler_deref_instr
)
7815 sampler_deref_instr
= texture_deref_instr
;
7818 assert(instr
->op
!= nir_texop_txf_ms
&&
7819 instr
->op
!= nir_texop_samples_identical
);
7820 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
7821 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
7822 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
7823 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
7824 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
7825 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
7827 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
7830 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
7832 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
7833 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
7834 Builder
bld(ctx
->program
, ctx
->block
);
7836 /* to avoid unnecessary moves, we split and recombine sampler and image */
7837 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
7838 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
7839 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
7840 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
7841 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
7842 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
7843 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
7844 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
7846 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
7847 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
7848 img
[0], img
[1], img
[2], img
[3],
7849 img
[4], img
[5], img
[6], img
[7]);
7850 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
7851 samp
[0], samp
[1], samp
[2], samp
[3]);
7854 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
7855 instr
->op
== nir_texop_samples_identical
))
7856 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
7859 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
7860 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
7862 Builder
bld(ctx
->program
, ctx
->block
);
7864 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
7865 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
7866 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
7868 Operand
neg_one(0xbf800000u
);
7869 Operand
one(0x3f800000u
);
7870 Operand
two(0x40000000u
);
7871 Operand
four(0x40800000u
);
7873 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
7874 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
7875 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
7877 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
7878 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
7879 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
7880 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
7883 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
7884 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
7885 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
7887 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
7890 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
7891 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
7892 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
7895 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
7896 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
7898 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
7899 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
7902 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
7904 Builder
bld(ctx
->program
, ctx
->block
);
7905 Temp ma
, tc
, sc
, id
;
7908 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
7910 // see comment in ac_prepare_cube_coords()
7911 if (ctx
->options
->chip_class
<= GFX8
)
7912 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
7915 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
7917 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
7918 vop3a
->operands
[0] = Operand(ma
);
7919 vop3a
->abs
[0] = true;
7920 Temp invma
= bld
.tmp(v1
);
7921 vop3a
->definitions
[0] = Definition(invma
);
7922 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
7924 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
7926 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
7928 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
7930 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
7932 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
7935 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
7936 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
7938 for (unsigned i
= 0; i
< 2; i
++) {
7939 // see comment in ac_prepare_cube_coords()
7941 Temp deriv_sc
, deriv_tc
;
7942 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
7943 &deriv_ma
, &deriv_sc
, &deriv_tc
);
7945 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
7947 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
7948 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
7949 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
7950 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
7951 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
7952 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
7953 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
7956 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
7957 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
7961 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
7968 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
7970 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
7972 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
7973 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
7976 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
7977 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
7978 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
7982 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
7984 Builder
bld(ctx
->program
, ctx
->block
);
7985 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
7986 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false;
7987 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
7988 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp();
7989 std::vector
<Temp
> coords
;
7990 std::vector
<Temp
> derivs
;
7991 nir_const_value
*sample_index_cv
= NULL
;
7992 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
7993 enum glsl_base_type stype
;
7994 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
7996 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
7997 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
7998 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
7999 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8001 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8002 switch (instr
->src
[i
].src_type
) {
8003 case nir_tex_src_coord
: {
8004 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8005 for (unsigned i
= 0; i
< coord
.size(); i
++)
8006 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8009 case nir_tex_src_bias
:
8010 if (instr
->op
== nir_texop_txb
) {
8011 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8015 case nir_tex_src_lod
: {
8016 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8018 if (val
&& val
->f32
<= 0.0) {
8021 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8026 case nir_tex_src_comparator
:
8027 if (instr
->is_shadow
) {
8028 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8032 case nir_tex_src_offset
:
8033 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8034 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8037 case nir_tex_src_ddx
:
8038 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8041 case nir_tex_src_ddy
:
8042 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8045 case nir_tex_src_ms_index
:
8046 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8047 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8048 has_sample_index
= true;
8050 case nir_tex_src_texture_offset
:
8051 case nir_tex_src_sampler_offset
:
8057 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8058 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8060 if (instr
->op
== nir_texop_texture_samples
) {
8061 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8063 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8064 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8065 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8066 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8068 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8069 samples
, Operand(1u), bld
.scc(is_msaa
));
8073 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8074 aco_ptr
<Instruction
> tmp_instr
;
8075 Temp acc
, pack
= Temp();
8077 uint32_t pack_const
= 0;
8078 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8079 if (!const_offset
[i
])
8081 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8084 if (offset
.type() == RegType::sgpr
) {
8085 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8086 if (const_offset
[i
])
8089 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8090 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8093 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8096 if (pack
== Temp()) {
8099 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8103 if (pack_const
&& pack
!= Temp())
8104 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8106 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8107 if (const_offset
[i
])
8110 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8111 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8114 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8117 if (pack
== Temp()) {
8120 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8124 if (pack_const
&& pack
!= Temp())
8125 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8127 if (pack_const
&& pack
== Temp())
8128 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8129 else if (pack
== Temp())
8135 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8136 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8138 /* pack derivatives */
8139 if (has_ddx
|| has_ddy
) {
8140 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8141 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8142 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8143 derivs
= {ddy
, zero
, ddy
, zero
};
8145 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8146 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8147 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8148 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8153 if (instr
->coord_components
> 1 &&
8154 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8156 instr
->op
!= nir_texop_txf
)
8157 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8159 if (instr
->coord_components
> 2 &&
8160 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8161 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8162 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8163 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8165 instr
->op
!= nir_texop_txf
&&
8166 instr
->op
!= nir_texop_txf_ms
&&
8167 instr
->op
!= nir_texop_fragment_fetch
&&
8168 instr
->op
!= nir_texop_fragment_mask_fetch
)
8169 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8171 if (ctx
->options
->chip_class
== GFX9
&&
8172 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8173 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8174 assert(coords
.size() > 0 && coords
.size() < 3);
8176 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8177 Operand((uint32_t) 0) :
8178 Operand((uint32_t) 0x3f000000)));
8181 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8183 if (instr
->op
== nir_texop_samples_identical
)
8184 resource
= fmask_ptr
;
8186 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8187 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8188 instr
->op
!= nir_texop_txs
&&
8189 instr
->op
!= nir_texop_fragment_fetch
&&
8190 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8191 assert(has_sample_index
);
8192 Operand
op(sample_index
);
8193 if (sample_index_cv
)
8194 op
= Operand(sample_index_cv
->u32
);
8195 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8198 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8199 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8200 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8201 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8206 /* Build tex instruction */
8207 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8208 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8209 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8211 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8214 /* gather4 selects the component by dmask and always returns vec4 */
8215 if (instr
->op
== nir_texop_tg4
) {
8216 assert(instr
->dest
.ssa
.num_components
== 4);
8217 if (instr
->is_shadow
)
8220 dmask
= 1 << instr
->component
;
8221 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8222 tmp_dst
= bld
.tmp(v4
);
8223 } else if (instr
->op
== nir_texop_samples_identical
) {
8224 tmp_dst
= bld
.tmp(v1
);
8225 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8226 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8229 aco_ptr
<MIMG_instruction
> tex
;
8230 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8232 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8234 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8235 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8238 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8239 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8241 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8242 tex
->operands
[0] = Operand(resource
);
8243 tex
->operands
[1] = Operand(s4
); /* no sampler */
8244 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8245 if (ctx
->options
->chip_class
== GFX9
&&
8246 instr
->op
== nir_texop_txs
&&
8247 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8249 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8250 } else if (instr
->op
== nir_texop_query_levels
) {
8251 tex
->dmask
= 1 << 3;
8256 tex
->definitions
[0] = Definition(tmp_dst
);
8258 tex
->can_reorder
= true;
8259 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8262 /* divide 3rd value by 6 by multiplying with magic number */
8263 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8264 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8265 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8266 assert(instr
->dest
.ssa
.num_components
== 3);
8267 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8268 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8269 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8270 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8275 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8279 Temp tg4_compare_cube_wa64
= Temp();
8281 if (tg4_integer_workarounds
) {
8282 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8283 tex
->operands
[0] = Operand(resource
);
8284 tex
->operands
[1] = Operand(s4
); /* no sampler */
8285 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8289 Temp size
= bld
.tmp(v2
);
8290 tex
->definitions
[0] = Definition(size
);
8291 tex
->can_reorder
= true;
8292 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8293 emit_split_vector(ctx
, size
, size
.size());
8296 for (unsigned i
= 0; i
< 2; i
++) {
8297 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8298 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8299 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8300 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8303 Temp new_coords
[2] = {
8304 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8305 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8308 if (tg4_integer_cube_workaround
) {
8309 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8310 Temp desc
[resource
.size()];
8311 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8312 Format::PSEUDO
, 1, resource
.size())};
8313 split
->operands
[0] = Operand(resource
);
8314 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8315 desc
[i
] = bld
.tmp(s1
);
8316 split
->definitions
[i
] = Definition(desc
[i
]);
8318 ctx
->block
->instructions
.emplace_back(std::move(split
));
8320 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8321 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8322 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8325 if (stype
== GLSL_TYPE_UINT
) {
8326 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8327 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8328 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8329 bld
.scc(compare_cube_wa
));
8331 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8332 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8333 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8334 bld
.scc(compare_cube_wa
));
8336 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8337 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8339 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8341 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8342 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8343 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8345 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8346 Format::PSEUDO
, resource
.size(), 1)};
8347 for (unsigned i
= 0; i
< resource
.size(); i
++)
8348 vec
->operands
[i
] = Operand(desc
[i
]);
8349 resource
= bld
.tmp(resource
.regClass());
8350 vec
->definitions
[0] = Definition(resource
);
8351 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8353 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8354 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8355 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8356 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8358 coords
[0] = new_coords
[0];
8359 coords
[1] = new_coords
[1];
8362 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8363 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8365 assert(coords
.size() == 1);
8366 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8370 op
= aco_opcode::buffer_load_format_x
; break;
8372 op
= aco_opcode::buffer_load_format_xy
; break;
8374 op
= aco_opcode::buffer_load_format_xyz
; break;
8376 op
= aco_opcode::buffer_load_format_xyzw
; break;
8378 unreachable("Tex instruction loads more than 4 components.");
8381 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8382 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8385 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8387 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8388 mubuf
->operands
[0] = Operand(resource
);
8389 mubuf
->operands
[1] = Operand(coords
[0]);
8390 mubuf
->operands
[2] = Operand((uint32_t) 0);
8391 mubuf
->definitions
[0] = Definition(tmp_dst
);
8392 mubuf
->idxen
= true;
8393 mubuf
->can_reorder
= true;
8394 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8396 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8400 /* gather MIMG address components */
8401 std::vector
<Temp
> args
;
8403 args
.emplace_back(offset
);
8405 args
.emplace_back(bias
);
8407 args
.emplace_back(compare
);
8409 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8411 args
.insert(args
.end(), coords
.begin(), coords
.end());
8412 if (has_sample_index
)
8413 args
.emplace_back(sample_index
);
8415 args
.emplace_back(lod
);
8417 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8418 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8419 vec
->definitions
[0] = Definition(arg
);
8420 for (unsigned i
= 0; i
< args
.size(); i
++)
8421 vec
->operands
[i
] = Operand(args
[i
]);
8422 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8425 if (instr
->op
== nir_texop_txf
||
8426 instr
->op
== nir_texop_txf_ms
||
8427 instr
->op
== nir_texop_samples_identical
||
8428 instr
->op
== nir_texop_fragment_fetch
||
8429 instr
->op
== nir_texop_fragment_mask_fetch
) {
8430 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8431 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8432 tex
->operands
[0] = Operand(resource
);
8433 tex
->operands
[1] = Operand(s4
); /* no sampler */
8434 tex
->operands
[2] = Operand(arg
);
8439 tex
->definitions
[0] = Definition(tmp_dst
);
8440 tex
->can_reorder
= true;
8441 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8443 if (instr
->op
== nir_texop_samples_identical
) {
8444 assert(dmask
== 1 && dst
.regClass() == v1
);
8445 assert(dst
.id() != tmp_dst
.id());
8447 Temp tmp
= bld
.tmp(bld
.lm
);
8448 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8449 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8452 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8457 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8458 aco_opcode opcode
= aco_opcode::image_sample
;
8459 if (has_offset
) { /* image_sample_*_o */
8461 opcode
= aco_opcode::image_sample_c_o
;
8463 opcode
= aco_opcode::image_sample_c_d_o
;
8465 opcode
= aco_opcode::image_sample_c_b_o
;
8467 opcode
= aco_opcode::image_sample_c_lz_o
;
8469 opcode
= aco_opcode::image_sample_c_l_o
;
8471 opcode
= aco_opcode::image_sample_o
;
8473 opcode
= aco_opcode::image_sample_d_o
;
8475 opcode
= aco_opcode::image_sample_b_o
;
8477 opcode
= aco_opcode::image_sample_lz_o
;
8479 opcode
= aco_opcode::image_sample_l_o
;
8481 } else { /* no offset */
8483 opcode
= aco_opcode::image_sample_c
;
8485 opcode
= aco_opcode::image_sample_c_d
;
8487 opcode
= aco_opcode::image_sample_c_b
;
8489 opcode
= aco_opcode::image_sample_c_lz
;
8491 opcode
= aco_opcode::image_sample_c_l
;
8493 opcode
= aco_opcode::image_sample
;
8495 opcode
= aco_opcode::image_sample_d
;
8497 opcode
= aco_opcode::image_sample_b
;
8499 opcode
= aco_opcode::image_sample_lz
;
8501 opcode
= aco_opcode::image_sample_l
;
8505 if (instr
->op
== nir_texop_tg4
) {
8507 opcode
= aco_opcode::image_gather4_lz_o
;
8509 opcode
= aco_opcode::image_gather4_c_lz_o
;
8511 opcode
= aco_opcode::image_gather4_lz
;
8513 opcode
= aco_opcode::image_gather4_c_lz
;
8515 } else if (instr
->op
== nir_texop_lod
) {
8516 opcode
= aco_opcode::image_get_lod
;
8519 /* we don't need the bias, sample index, compare value or offset to be
8520 * computed in WQM but if the p_create_vector copies the coordinates, then it
8521 * needs to be in WQM */
8522 if (ctx
->stage
== fragment_fs
&&
8523 !has_derivs
&& !has_lod
&& !level_zero
&&
8524 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8525 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8526 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8528 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8529 tex
->operands
[0] = Operand(resource
);
8530 tex
->operands
[1] = Operand(sampler
);
8531 tex
->operands
[2] = Operand(arg
);
8535 tex
->definitions
[0] = Definition(tmp_dst
);
8536 tex
->can_reorder
= true;
8537 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8539 if (tg4_integer_cube_workaround
) {
8540 assert(tmp_dst
.id() != dst
.id());
8541 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8543 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8545 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8546 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8548 if (stype
== GLSL_TYPE_UINT
)
8549 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8551 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8552 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8554 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8555 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8556 val
[0], val
[1], val
[2], val
[3]);
8558 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8559 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8564 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
)
8566 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8567 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
8568 return Operand(tmp
.regClass());
8570 return Operand(tmp
);
8573 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8575 aco_ptr
<Pseudo_instruction
> phi
;
8576 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8577 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8579 bool logical
= !dst
.is_linear() || ctx
->divergent_vals
[instr
->dest
.ssa
.index
];
8580 logical
|= ctx
->block
->kind
& block_kind_merge
;
8581 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8583 /* we want a sorted list of sources, since the predecessor list is also sorted */
8584 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8585 nir_foreach_phi_src(src
, instr
)
8586 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8588 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8589 unsigned num_operands
= 0;
8590 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8591 unsigned num_defined
= 0;
8592 unsigned cur_pred_idx
= 0;
8593 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8594 if (cur_pred_idx
< preds
.size()) {
8595 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8596 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8597 unsigned skipped
= 0;
8598 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8600 if (cur_pred_idx
+ skipped
< preds
.size()) {
8601 for (unsigned i
= 0; i
< skipped
; i
++)
8602 operands
[num_operands
++] = Operand(dst
.regClass());
8603 cur_pred_idx
+= skipped
;
8608 /* Handle missing predecessors at the end. This shouldn't happen with loop
8609 * headers and we can't ignore these sources for loop header phis. */
8610 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8613 Operand op
= get_phi_operand(ctx
, src
.second
);
8614 operands
[num_operands
++] = op
;
8615 num_defined
+= !op
.isUndefined();
8617 /* handle block_kind_continue_or_break at loop exit blocks */
8618 while (cur_pred_idx
++ < preds
.size())
8619 operands
[num_operands
++] = Operand(dst
.regClass());
8621 /* If the loop ends with a break, still add a linear continue edge in case
8622 * that break is divergent or continue_or_break is used. We'll either remove
8623 * this operand later in visit_loop() if it's not necessary or replace the
8624 * undef with something correct. */
8625 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
8626 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
8627 nir_block
*last
= nir_loop_last_block(loop
);
8628 if (last
->successors
[0] != instr
->instr
.block
)
8629 operands
[num_operands
++] = Operand(RegClass());
8632 if (num_defined
== 0) {
8633 Builder
bld(ctx
->program
, ctx
->block
);
8634 if (dst
.regClass() == s1
) {
8635 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
8636 } else if (dst
.regClass() == v1
) {
8637 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
8639 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8640 for (unsigned i
= 0; i
< dst
.size(); i
++)
8641 vec
->operands
[i
] = Operand(0u);
8642 vec
->definitions
[0] = Definition(dst
);
8643 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8648 /* we can use a linear phi in some cases if one src is undef */
8649 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
8650 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
8652 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
8653 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
8654 assert(invert
->kind
& block_kind_invert
);
8656 unsigned then_block
= invert
->linear_preds
[0];
8658 Block
* insert_block
= NULL
;
8659 for (unsigned i
= 0; i
< num_operands
; i
++) {
8660 Operand op
= operands
[i
];
8661 if (op
.isUndefined())
8663 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
8664 phi
->operands
[0] = op
;
8667 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
8668 phi
->operands
[1] = Operand(dst
.regClass());
8669 phi
->definitions
[0] = Definition(dst
);
8670 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
8674 /* try to scalarize vector phis */
8675 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
8676 // TODO: scalarize linear phis on divergent ifs
8677 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
8678 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
8679 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
8680 Operand src
= operands
[i
];
8681 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
8682 can_scalarize
= false;
8684 if (can_scalarize
) {
8685 unsigned num_components
= instr
->dest
.ssa
.num_components
;
8686 assert(dst
.size() % num_components
== 0);
8687 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
8689 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
8690 for (unsigned k
= 0; k
< num_components
; k
++) {
8691 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8692 for (unsigned i
= 0; i
< num_operands
; i
++) {
8693 Operand src
= operands
[i
];
8694 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
8696 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
8697 phi
->definitions
[0] = Definition(phi_dst
);
8698 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
8699 new_vec
[k
] = phi_dst
;
8700 vec
->operands
[k
] = Operand(phi_dst
);
8702 vec
->definitions
[0] = Definition(dst
);
8703 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8704 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
8709 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8710 for (unsigned i
= 0; i
< num_operands
; i
++)
8711 phi
->operands
[i
] = operands
[i
];
8712 phi
->definitions
[0] = Definition(dst
);
8713 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
8717 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
8719 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
8721 assert(dst
.type() == RegType::sgpr
);
8723 if (dst
.size() == 1) {
8724 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
8726 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8727 for (unsigned i
= 0; i
< dst
.size(); i
++)
8728 vec
->operands
[i
] = Operand(0u);
8729 vec
->definitions
[0] = Definition(dst
);
8730 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8734 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
8736 Builder
bld(ctx
->program
, ctx
->block
);
8737 Block
*logical_target
;
8738 append_logical_end(ctx
->block
);
8739 unsigned idx
= ctx
->block
->index
;
8741 switch (instr
->type
) {
8742 case nir_jump_break
:
8743 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
8744 add_logical_edge(idx
, logical_target
);
8745 ctx
->block
->kind
|= block_kind_break
;
8747 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
8748 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
8749 /* uniform break - directly jump out of the loop */
8750 ctx
->block
->kind
|= block_kind_uniform
;
8751 ctx
->cf_info
.has_branch
= true;
8752 bld
.branch(aco_opcode::p_branch
);
8753 add_linear_edge(idx
, logical_target
);
8756 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
8757 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
8759 case nir_jump_continue
:
8760 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
8761 add_logical_edge(idx
, logical_target
);
8762 ctx
->block
->kind
|= block_kind_continue
;
8764 if (ctx
->cf_info
.parent_if
.is_divergent
) {
8765 /* for potential uniform breaks after this continue,
8766 we must ensure that they are handled correctly */
8767 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
8768 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
8769 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
8771 /* uniform continue - directly jump to the loop header */
8772 ctx
->block
->kind
|= block_kind_uniform
;
8773 ctx
->cf_info
.has_branch
= true;
8774 bld
.branch(aco_opcode::p_branch
);
8775 add_linear_edge(idx
, logical_target
);
8780 fprintf(stderr
, "Unknown NIR jump instr: ");
8781 nir_print_instr(&instr
->instr
, stderr
);
8782 fprintf(stderr
, "\n");
8786 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
8787 ctx
->cf_info
.exec_potentially_empty_break
= true;
8788 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
8791 /* remove critical edges from linear CFG */
8792 bld
.branch(aco_opcode::p_branch
);
8793 Block
* break_block
= ctx
->program
->create_and_insert_block();
8794 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
8795 break_block
->kind
|= block_kind_uniform
;
8796 add_linear_edge(idx
, break_block
);
8797 /* the loop_header pointer might be invalidated by this point */
8798 if (instr
->type
== nir_jump_continue
)
8799 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
8800 add_linear_edge(break_block
->index
, logical_target
);
8801 bld
.reset(break_block
);
8802 bld
.branch(aco_opcode::p_branch
);
8804 Block
* continue_block
= ctx
->program
->create_and_insert_block();
8805 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
8806 add_linear_edge(idx
, continue_block
);
8807 append_logical_start(continue_block
);
8808 ctx
->block
= continue_block
;
8812 void visit_block(isel_context
*ctx
, nir_block
*block
)
8814 nir_foreach_instr(instr
, block
) {
8815 switch (instr
->type
) {
8816 case nir_instr_type_alu
:
8817 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
8819 case nir_instr_type_load_const
:
8820 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
8822 case nir_instr_type_intrinsic
:
8823 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
8825 case nir_instr_type_tex
:
8826 visit_tex(ctx
, nir_instr_as_tex(instr
));
8828 case nir_instr_type_phi
:
8829 visit_phi(ctx
, nir_instr_as_phi(instr
));
8831 case nir_instr_type_ssa_undef
:
8832 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
8834 case nir_instr_type_deref
:
8836 case nir_instr_type_jump
:
8837 visit_jump(ctx
, nir_instr_as_jump(instr
));
8840 fprintf(stderr
, "Unknown NIR instr type: ");
8841 nir_print_instr(instr
, stderr
);
8842 fprintf(stderr
, "\n");
8847 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
8848 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
8853 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
8854 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
8856 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
8857 RegClass rc
= vals
[0].regClass();
8859 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
8861 unsigned next_pred
= 1;
8863 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
8864 Block
& block
= ctx
->program
->blocks
[idx
];
8865 if (block
.loop_nest_depth
!= loop_nest_depth
) {
8866 vals
[idx
- first
] = vals
[idx
- 1 - first
];
8870 if (block
.kind
& block_kind_continue
) {
8871 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
8876 bool all_same
= true;
8877 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
8878 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
8882 val
= vals
[block
.linear_preds
[0] - first
];
8884 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
8885 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
8886 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
8887 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
8888 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
8889 phi
->definitions
[0] = Definition(val
.getTemp());
8890 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
8892 vals
[idx
- first
] = val
;
8895 return vals
[last
- first
];
8898 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
8900 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
8901 append_logical_end(ctx
->block
);
8902 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
8903 Builder
bld(ctx
->program
, ctx
->block
);
8904 bld
.branch(aco_opcode::p_branch
);
8905 unsigned loop_preheader_idx
= ctx
->block
->index
;
8907 Block loop_exit
= Block();
8908 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
8909 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
8911 Block
* loop_header
= ctx
->program
->create_and_insert_block();
8912 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
8913 loop_header
->kind
|= block_kind_loop_header
;
8914 add_edge(loop_preheader_idx
, loop_header
);
8915 ctx
->block
= loop_header
;
8917 /* emit loop body */
8918 unsigned loop_header_idx
= loop_header
->index
;
8919 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
8920 append_logical_start(ctx
->block
);
8921 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
8923 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
8924 if (!ctx
->cf_info
.has_branch
) {
8925 append_logical_end(ctx
->block
);
8926 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
8927 /* Discards can result in code running with an empty exec mask.
8928 * This would result in divergent breaks not ever being taken. As a
8929 * workaround, break the loop when the loop mask is empty instead of
8930 * always continuing. */
8931 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
8932 unsigned block_idx
= ctx
->block
->index
;
8934 /* create helper blocks to avoid critical edges */
8935 Block
*break_block
= ctx
->program
->create_and_insert_block();
8936 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
8937 break_block
->kind
= block_kind_uniform
;
8938 bld
.reset(break_block
);
8939 bld
.branch(aco_opcode::p_branch
);
8940 add_linear_edge(block_idx
, break_block
);
8941 add_linear_edge(break_block
->index
, &loop_exit
);
8943 Block
*continue_block
= ctx
->program
->create_and_insert_block();
8944 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
8945 continue_block
->kind
= block_kind_uniform
;
8946 bld
.reset(continue_block
);
8947 bld
.branch(aco_opcode::p_branch
);
8948 add_linear_edge(block_idx
, continue_block
);
8949 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
8951 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
8952 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
8953 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
8955 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
8956 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
8957 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
8959 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
8962 bld
.reset(ctx
->block
);
8963 bld
.branch(aco_opcode::p_branch
);
8966 /* Fixup phis in loop header from unreachable blocks.
8967 * has_branch/has_divergent_branch also indicates if the loop ends with a
8968 * break/continue instruction, but we don't emit those if unreachable=true */
8970 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
8971 bool linear
= ctx
->cf_info
.has_branch
;
8972 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
8973 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
8974 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
8975 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
8976 /* the last operand should be the one that needs to be removed */
8977 instr
->operands
.pop_back();
8978 } else if (!is_phi(instr
)) {
8984 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
8985 * and the previous one shouldn't both happen at once because a break in the
8986 * merge block would get CSE'd */
8987 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
8988 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
8989 Operand vals
[num_vals
];
8990 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
8991 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
8992 if (ctx
->cf_info
.has_branch
)
8993 instr
->operands
.pop_back();
8995 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
8996 } else if (!is_phi(instr
)) {
9002 ctx
->cf_info
.has_branch
= false;
9004 // TODO: if the loop has not a single exit, we must add one °°
9005 /* emit loop successor block */
9006 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9007 append_logical_start(ctx
->block
);
9010 // TODO: check if it is beneficial to not branch on continues
9011 /* trim linear phis in loop header */
9012 for (auto&& instr
: loop_entry
->instructions
) {
9013 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9014 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9015 new_phi
->definitions
[0] = instr
->definitions
[0];
9016 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9017 new_phi
->operands
[i
] = instr
->operands
[i
];
9018 /* check that the remaining operands are all the same */
9019 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9020 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9021 instr
.swap(new_phi
);
9022 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9031 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9035 append_logical_end(ctx
->block
);
9036 ctx
->block
->kind
|= block_kind_branch
;
9038 /* branch to linear then block */
9039 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9040 aco_ptr
<Pseudo_branch_instruction
> branch
;
9041 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9042 branch
->operands
[0] = Operand(cond
);
9043 ctx
->block
->instructions
.push_back(std::move(branch
));
9045 ic
->BB_if_idx
= ctx
->block
->index
;
9046 ic
->BB_invert
= Block();
9047 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9048 /* Invert blocks are intentionally not marked as top level because they
9049 * are not part of the logical cfg. */
9050 ic
->BB_invert
.kind
|= block_kind_invert
;
9051 ic
->BB_endif
= Block();
9052 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9053 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9055 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9056 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9057 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9058 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9059 ctx
->cf_info
.parent_if
.is_divergent
= true;
9061 /* divergent branches use cbranch_execz */
9062 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9063 ctx
->cf_info
.exec_potentially_empty_break
= false;
9064 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9066 /** emit logical then block */
9067 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9068 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9069 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9070 ctx
->block
= BB_then_logical
;
9071 append_logical_start(BB_then_logical
);
9074 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9076 Block
*BB_then_logical
= ctx
->block
;
9077 append_logical_end(BB_then_logical
);
9078 /* branch from logical then block to invert block */
9079 aco_ptr
<Pseudo_branch_instruction
> branch
;
9080 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9081 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9082 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9083 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9084 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9085 BB_then_logical
->kind
|= block_kind_uniform
;
9086 assert(!ctx
->cf_info
.has_branch
);
9087 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9088 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9090 /** emit linear then block */
9091 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9092 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9093 BB_then_linear
->kind
|= block_kind_uniform
;
9094 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9095 /* branch from linear then block to invert block */
9096 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9097 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9098 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9100 /** emit invert merge block */
9101 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9102 ic
->invert_idx
= ctx
->block
->index
;
9104 /* branch to linear else block (skip else) */
9105 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9106 branch
->operands
[0] = Operand(ic
->cond
);
9107 ctx
->block
->instructions
.push_back(std::move(branch
));
9109 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9110 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9111 ic
->exec_potentially_empty_break_depth_old
=
9112 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9113 /* divergent branches use cbranch_execz */
9114 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9115 ctx
->cf_info
.exec_potentially_empty_break
= false;
9116 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9118 /** emit logical else block */
9119 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9120 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9121 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9122 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9123 ctx
->block
= BB_else_logical
;
9124 append_logical_start(BB_else_logical
);
9127 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9129 Block
*BB_else_logical
= ctx
->block
;
9130 append_logical_end(BB_else_logical
);
9132 /* branch from logical else block to endif block */
9133 aco_ptr
<Pseudo_branch_instruction
> branch
;
9134 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9135 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9136 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9137 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9138 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9139 BB_else_logical
->kind
|= block_kind_uniform
;
9141 assert(!ctx
->cf_info
.has_branch
);
9142 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9145 /** emit linear else block */
9146 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9147 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9148 BB_else_linear
->kind
|= block_kind_uniform
;
9149 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9151 /* branch from linear else block to endif block */
9152 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9153 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9154 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9157 /** emit endif merge block */
9158 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9159 append_logical_start(ctx
->block
);
9162 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9163 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9164 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9165 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9166 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9167 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9168 !ctx
->cf_info
.parent_if
.is_divergent
) {
9169 ctx
->cf_info
.exec_potentially_empty_break
= false;
9170 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9172 /* uniform control flow never has an empty exec-mask */
9173 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9174 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9175 ctx
->cf_info
.exec_potentially_empty_break
= false;
9176 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9180 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9182 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9183 Builder
bld(ctx
->program
, ctx
->block
);
9184 aco_ptr
<Pseudo_branch_instruction
> branch
;
9186 if (!ctx
->divergent_vals
[if_stmt
->condition
.ssa
->index
]) { /* uniform condition */
9188 * Uniform conditionals are represented in the following way*) :
9190 * The linear and logical CFG:
9193 * BB_THEN (logical) BB_ELSE (logical)
9197 * *) Exceptions may be due to break and continue statements within loops
9198 * If a break/continue happens within uniform control flow, it branches
9199 * to the loop exit/entry block. Otherwise, it branches to the next
9202 append_logical_end(ctx
->block
);
9203 ctx
->block
->kind
|= block_kind_uniform
;
9206 assert(cond
.regClass() == bld
.lm
);
9207 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9208 cond
= bool_to_scalar_condition(ctx
, cond
);
9210 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9211 branch
->operands
[0] = Operand(cond
);
9212 branch
->operands
[0].setFixed(scc
);
9213 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9215 unsigned BB_if_idx
= ctx
->block
->index
;
9216 Block BB_endif
= Block();
9217 BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9218 BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9220 /** emit then block */
9221 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9222 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9223 add_edge(BB_if_idx
, BB_then
);
9224 append_logical_start(BB_then
);
9225 ctx
->block
= BB_then
;
9226 visit_cf_list(ctx
, &if_stmt
->then_list
);
9227 BB_then
= ctx
->block
;
9228 bool then_branch
= ctx
->cf_info
.has_branch
;
9229 bool then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9232 append_logical_end(BB_then
);
9233 /* branch from then block to endif block */
9234 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9235 BB_then
->instructions
.emplace_back(std::move(branch
));
9236 add_linear_edge(BB_then
->index
, &BB_endif
);
9237 if (!then_branch_divergent
)
9238 add_logical_edge(BB_then
->index
, &BB_endif
);
9239 BB_then
->kind
|= block_kind_uniform
;
9242 ctx
->cf_info
.has_branch
= false;
9243 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9245 /** emit else block */
9246 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9247 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9248 add_edge(BB_if_idx
, BB_else
);
9249 append_logical_start(BB_else
);
9250 ctx
->block
= BB_else
;
9251 visit_cf_list(ctx
, &if_stmt
->else_list
);
9252 BB_else
= ctx
->block
;
9254 if (!ctx
->cf_info
.has_branch
) {
9255 append_logical_end(BB_else
);
9256 /* branch from then block to endif block */
9257 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9258 BB_else
->instructions
.emplace_back(std::move(branch
));
9259 add_linear_edge(BB_else
->index
, &BB_endif
);
9260 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9261 add_logical_edge(BB_else
->index
, &BB_endif
);
9262 BB_else
->kind
|= block_kind_uniform
;
9265 ctx
->cf_info
.has_branch
&= then_branch
;
9266 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= then_branch_divergent
;
9268 /** emit endif merge block */
9269 if (!ctx
->cf_info
.has_branch
) {
9270 ctx
->block
= ctx
->program
->insert_block(std::move(BB_endif
));
9271 append_logical_start(ctx
->block
);
9273 return !ctx
->cf_info
.has_branch
;
9274 } else { /* non-uniform condition */
9276 * To maintain a logical and linear CFG without critical edges,
9277 * non-uniform conditionals are represented in the following way*) :
9282 * BB_THEN (logical) BB_THEN (linear)
9284 * BB_INVERT (linear)
9286 * BB_ELSE (logical) BB_ELSE (linear)
9293 * BB_THEN (logical) BB_ELSE (logical)
9297 * *) Exceptions may be due to break and continue statements within loops
9302 begin_divergent_if_then(ctx
, &ic
, cond
);
9303 visit_cf_list(ctx
, &if_stmt
->then_list
);
9305 begin_divergent_if_else(ctx
, &ic
);
9306 visit_cf_list(ctx
, &if_stmt
->else_list
);
9308 end_divergent_if(ctx
, &ic
);
9314 static bool visit_cf_list(isel_context
*ctx
,
9315 struct exec_list
*list
)
9317 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9318 switch (node
->type
) {
9319 case nir_cf_node_block
:
9320 visit_block(ctx
, nir_cf_node_as_block(node
));
9322 case nir_cf_node_if
:
9323 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9326 case nir_cf_node_loop
:
9327 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9330 unreachable("unimplemented cf list type");
9336 static void create_null_export(isel_context
*ctx
)
9338 /* Some shader stages always need to have exports.
9339 * So when there is none, we need to add a null export.
9342 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9343 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9344 Builder
bld(ctx
->program
, ctx
->block
);
9345 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9346 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9349 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9351 assert(ctx
->stage
== vertex_vs
||
9352 ctx
->stage
== tess_eval_vs
||
9353 ctx
->stage
== gs_copy_vs
);
9355 int offset
= ctx
->stage
== tess_eval_vs
9356 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9357 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9358 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9359 if (!is_pos
&& !mask
)
9361 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9363 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9364 exp
->enabled_mask
= mask
;
9365 for (unsigned i
= 0; i
< 4; ++i
) {
9366 if (mask
& (1 << i
))
9367 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9369 exp
->operands
[i
] = Operand(v1
);
9371 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9372 * Setting valid_mask=1 prevents it and has no other effect.
9374 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9376 exp
->compressed
= false;
9378 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9380 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9381 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9386 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9388 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9389 exp
->enabled_mask
= 0;
9390 for (unsigned i
= 0; i
< 4; ++i
)
9391 exp
->operands
[i
] = Operand(v1
);
9392 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9393 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9394 exp
->enabled_mask
|= 0x1;
9396 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9397 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9398 exp
->enabled_mask
|= 0x4;
9400 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9401 if (ctx
->options
->chip_class
< GFX9
) {
9402 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9403 exp
->enabled_mask
|= 0x8;
9405 Builder
bld(ctx
->program
, ctx
->block
);
9407 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9408 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9409 if (exp
->operands
[2].isTemp())
9410 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9412 exp
->operands
[2] = Operand(out
);
9413 exp
->enabled_mask
|= 0x4;
9416 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9418 exp
->compressed
= false;
9419 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9420 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9423 static void create_vs_exports(isel_context
*ctx
)
9425 assert(ctx
->stage
== vertex_vs
||
9426 ctx
->stage
== tess_eval_vs
||
9427 ctx
->stage
== gs_copy_vs
);
9429 radv_vs_output_info
*outinfo
= ctx
->stage
== tess_eval_vs
9430 ? &ctx
->program
->info
->tes
.outinfo
9431 : &ctx
->program
->info
->vs
.outinfo
;
9433 if (outinfo
->export_prim_id
) {
9434 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9435 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9438 if (ctx
->options
->key
.has_multiview_view_index
) {
9439 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9440 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9443 /* the order these position exports are created is important */
9445 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9446 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9447 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9448 exported_pos
= true;
9450 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9451 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9452 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9453 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9455 if (ctx
->export_clip_dists
) {
9456 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9457 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9458 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9459 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9462 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9463 if (i
< VARYING_SLOT_VAR0
&& i
!= VARYING_SLOT_LAYER
&&
9464 i
!= VARYING_SLOT_PRIMITIVE_ID
)
9467 export_vs_varying(ctx
, i
, false, NULL
);
9471 create_null_export(ctx
);
9474 static bool export_fs_mrt_z(isel_context
*ctx
)
9476 Builder
bld(ctx
->program
, ctx
->block
);
9477 unsigned enabled_channels
= 0;
9481 for (unsigned i
= 0; i
< 4; ++i
) {
9482 values
[i
] = Operand(v1
);
9485 /* Both stencil and sample mask only need 16-bits. */
9486 if (!ctx
->program
->info
->ps
.writes_z
&&
9487 (ctx
->program
->info
->ps
.writes_stencil
||
9488 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9489 compr
= true; /* COMPR flag */
9491 if (ctx
->program
->info
->ps
.writes_stencil
) {
9492 /* Stencil should be in X[23:16]. */
9493 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9494 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9495 enabled_channels
|= 0x3;
9498 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9499 /* SampleMask should be in Y[15:0]. */
9500 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9501 enabled_channels
|= 0xc;
9504 if (ctx
->program
->info
->ps
.writes_z
) {
9505 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9506 enabled_channels
|= 0x1;
9509 if (ctx
->program
->info
->ps
.writes_stencil
) {
9510 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9511 enabled_channels
|= 0x2;
9514 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9515 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9516 enabled_channels
|= 0x4;
9520 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9521 * writemask component.
9523 if (ctx
->options
->chip_class
== GFX6
&&
9524 ctx
->options
->family
!= CHIP_OLAND
&&
9525 ctx
->options
->family
!= CHIP_HAINAN
) {
9526 enabled_channels
|= 0x1;
9529 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9530 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9535 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9537 Builder
bld(ctx
->program
, ctx
->block
);
9538 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9541 for (unsigned i
= 0; i
< 4; ++i
) {
9542 if (write_mask
& (1 << i
)) {
9543 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9545 values
[i
] = Operand(v1
);
9549 unsigned target
, col_format
;
9550 unsigned enabled_channels
= 0;
9551 aco_opcode compr_op
= (aco_opcode
)0;
9553 slot
-= FRAG_RESULT_DATA0
;
9554 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9555 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9557 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9558 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
9562 case V_028714_SPI_SHADER_ZERO
:
9563 enabled_channels
= 0; /* writemask */
9564 target
= V_008DFC_SQ_EXP_NULL
;
9567 case V_028714_SPI_SHADER_32_R
:
9568 enabled_channels
= 1;
9571 case V_028714_SPI_SHADER_32_GR
:
9572 enabled_channels
= 0x3;
9575 case V_028714_SPI_SHADER_32_AR
:
9576 if (ctx
->options
->chip_class
>= GFX10
) {
9577 /* Special case: on GFX10, the outputs are different for 32_AR */
9578 enabled_channels
= 0x3;
9579 values
[1] = values
[3];
9580 values
[3] = Operand(v1
);
9582 enabled_channels
= 0x9;
9586 case V_028714_SPI_SHADER_FP16_ABGR
:
9587 enabled_channels
= 0x5;
9588 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
9591 case V_028714_SPI_SHADER_UNORM16_ABGR
:
9592 enabled_channels
= 0x5;
9593 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
9596 case V_028714_SPI_SHADER_SNORM16_ABGR
:
9597 enabled_channels
= 0x5;
9598 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
9601 case V_028714_SPI_SHADER_UINT16_ABGR
: {
9602 enabled_channels
= 0x5;
9603 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
9604 if (is_int8
|| is_int10
) {
9606 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
9607 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9609 for (unsigned i
= 0; i
< 4; i
++) {
9610 if ((write_mask
>> i
) & 1) {
9611 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
9612 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
9620 case V_028714_SPI_SHADER_SINT16_ABGR
:
9621 enabled_channels
= 0x5;
9622 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
9623 if (is_int8
|| is_int10
) {
9625 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
9626 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
9627 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9628 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
9630 for (unsigned i
= 0; i
< 4; i
++) {
9631 if ((write_mask
>> i
) & 1) {
9632 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
9633 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
9635 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
9636 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
9643 case V_028714_SPI_SHADER_32_ABGR
:
9644 enabled_channels
= 0xF;
9651 if (target
== V_008DFC_SQ_EXP_NULL
)
9654 if ((bool) compr_op
) {
9655 for (int i
= 0; i
< 2; i
++) {
9656 /* check if at least one of the values to be compressed is enabled */
9657 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
9659 enabled_channels
|= enabled
<< (i
*2);
9660 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
9661 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
9662 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
9664 values
[i
] = Operand(v1
);
9667 values
[2] = Operand(v1
);
9668 values
[3] = Operand(v1
);
9670 for (int i
= 0; i
< 4; i
++)
9671 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
9674 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9675 enabled_channels
, target
, (bool) compr_op
);
9679 static void create_fs_exports(isel_context
*ctx
)
9681 bool exported
= false;
9683 /* Export depth, stencil and sample mask. */
9684 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
9685 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
9686 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
9687 exported
|= export_fs_mrt_z(ctx
);
9689 /* Export all color render targets. */
9690 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
9691 if (ctx
->outputs
.mask
[i
])
9692 exported
|= export_fs_mrt_color(ctx
, i
);
9695 create_null_export(ctx
);
9698 static void write_tcs_tess_factors(isel_context
*ctx
)
9700 unsigned outer_comps
;
9701 unsigned inner_comps
;
9703 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
9720 Builder
bld(ctx
->program
, ctx
->block
);
9722 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
9723 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
9724 bld
.sopp(aco_opcode::s_barrier
);
9726 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
9727 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
9729 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
9730 if_context ic_invocation_id_is_zero
;
9731 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
9732 bld
.reset(ctx
->block
);
9734 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
9736 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
9737 unsigned stride
= inner_comps
+ outer_comps
;
9738 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
9742 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
9744 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
9746 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
9747 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
9748 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
9750 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
9751 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
9753 for (unsigned i
= 0; i
< outer_comps
; ++i
)
9754 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
9755 for (unsigned i
= 0; i
< inner_comps
; ++i
)
9756 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
9759 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
9760 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
9761 Temp byte_offset
= bld
.v_mul_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
9762 unsigned tf_const_offset
= 0;
9764 if (ctx
->program
->chip_class
<= GFX8
) {
9765 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
9766 if_context ic_rel_patch_id_is_zero
;
9767 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
9768 bld
.reset(ctx
->block
);
9770 /* Store the dynamic HS control word. */
9771 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
9772 bld
.mubuf(aco_opcode::buffer_store_dword
,
9773 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
9774 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
9775 /* disable_wqm */ false, /* glc */ true);
9776 tf_const_offset
+= 4;
9778 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
9779 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
9780 bld
.reset(ctx
->block
);
9783 assert(stride
== 2 || stride
== 4 || stride
== 6);
9784 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
9785 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
9787 /* Store to offchip for TES to read - only if TES reads them */
9788 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
9789 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
9790 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
9792 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
9793 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
9795 if (likely(inner_comps
)) {
9796 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
9797 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
9801 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
9802 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
9805 static void emit_stream_output(isel_context
*ctx
,
9806 Temp
const *so_buffers
,
9807 Temp
const *so_write_offset
,
9808 const struct radv_stream_output
*output
)
9810 unsigned num_comps
= util_bitcount(output
->component_mask
);
9811 unsigned writemask
= (1 << num_comps
) - 1;
9812 unsigned loc
= output
->location
;
9813 unsigned buf
= output
->buffer
;
9815 assert(num_comps
&& num_comps
<= 4);
9816 if (!num_comps
|| num_comps
> 4)
9819 unsigned start
= ffs(output
->component_mask
) - 1;
9822 bool all_undef
= true;
9823 assert(ctx
->stage
== vertex_vs
|| ctx
->stage
== gs_copy_vs
);
9824 for (unsigned i
= 0; i
< num_comps
; i
++) {
9825 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
9826 all_undef
= all_undef
&& !out
[i
].id();
9833 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
9834 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
9835 /* GFX6 doesn't support storing vec3, split it. */
9836 writemask
|= 1u << (start
+ 2);
9840 unsigned offset
= output
->offset
+ start
* 4;
9842 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
9843 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
9844 for (int i
= 0; i
< count
; ++i
)
9845 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
9846 vec
->definitions
[0] = Definition(write_data
);
9847 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9852 opcode
= aco_opcode::buffer_store_dword
;
9855 opcode
= aco_opcode::buffer_store_dwordx2
;
9858 opcode
= aco_opcode::buffer_store_dwordx3
;
9861 opcode
= aco_opcode::buffer_store_dwordx4
;
9864 unreachable("Unsupported dword count.");
9867 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
9868 store
->operands
[0] = Operand(so_buffers
[buf
]);
9869 store
->operands
[1] = Operand(so_write_offset
[buf
]);
9870 store
->operands
[2] = Operand((uint32_t) 0);
9871 store
->operands
[3] = Operand(write_data
);
9872 if (offset
> 4095) {
9873 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
9874 Builder
bld(ctx
->program
, ctx
->block
);
9875 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
9877 store
->offset
= offset
;
9879 store
->offen
= true;
9883 store
->can_reorder
= true;
9884 ctx
->block
->instructions
.emplace_back(std::move(store
));
9888 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
9890 Builder
bld(ctx
->program
, ctx
->block
);
9893 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
9894 for (unsigned i
= 0; i
< 4; i
++) {
9895 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
9899 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
9900 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
9903 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
9904 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
9906 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
9908 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
9911 begin_divergent_if_then(ctx
, &ic
, can_emit
);
9913 bld
.reset(ctx
->block
);
9915 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
9917 Temp so_write_offset
[4];
9919 for (unsigned i
= 0; i
< 4; i
++) {
9920 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
9925 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
9926 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
9927 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
9928 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
9930 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
9932 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
9933 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
9934 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
9935 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
9939 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
9940 struct radv_stream_output
*output
=
9941 &ctx
->program
->info
->so
.outputs
[i
];
9942 if (stream
!= output
->stream
)
9945 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
9948 begin_divergent_if_else(ctx
, &ic
);
9949 end_divergent_if(ctx
, &ic
);
9952 } /* end namespace */
9954 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
9956 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
9957 Builder
bld(ctx
->program
, ctx
->block
);
9958 constexpr unsigned hs_idx
= 1u;
9959 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
9960 get_arg(ctx
, ctx
->args
->merged_wave_info
),
9961 Operand((8u << 16) | (hs_idx
* 8u)));
9962 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
9964 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
9966 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
9967 get_arg(ctx
, ctx
->args
->rel_auto_id
),
9968 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
9969 ls_has_nonzero_hs_threads
);
9970 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
9971 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
9972 get_arg(ctx
, ctx
->args
->rel_auto_id
),
9973 ls_has_nonzero_hs_threads
);
9974 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
9975 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
9976 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
9977 ls_has_nonzero_hs_threads
);
9979 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
9980 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
9981 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
9984 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
9986 /* Split all arguments except for the first (ring_offsets) and the last
9987 * (exec) so that the dead channels don't stay live throughout the program.
9989 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
9990 if (startpgm
->definitions
[i
].regClass().size() > 1) {
9991 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
9992 startpgm
->definitions
[i
].regClass().size());
9997 void handle_bc_optimize(isel_context
*ctx
)
9999 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10000 Builder
bld(ctx
->program
, ctx
->block
);
10001 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10002 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10003 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10004 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10005 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10006 if (uses_center
&& uses_centroid
) {
10007 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10008 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10010 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10012 for (unsigned i
= 0; i
< 2; i
++) {
10013 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10014 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10015 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10016 persp_centroid
, persp_center
, sel
);
10018 ctx
->persp_centroid
= bld
.tmp(v2
);
10019 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10020 Operand(new_coord
[0]), Operand(new_coord
[1]));
10021 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10024 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10026 for (unsigned i
= 0; i
< 2; i
++) {
10027 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10028 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10029 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10030 linear_centroid
, linear_center
, sel
);
10032 ctx
->linear_centroid
= bld
.tmp(v2
);
10033 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10034 Operand(new_coord
[0]), Operand(new_coord
[1]));
10035 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10040 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10042 Program
*program
= ctx
->program
;
10044 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10046 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10047 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10048 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10049 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10050 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10052 program
->next_fp_mode
.must_flush_denorms32
=
10053 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10054 program
->next_fp_mode
.must_flush_denorms16_64
=
10055 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10056 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10058 program
->next_fp_mode
.care_about_round32
=
10059 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10061 program
->next_fp_mode
.care_about_round16_64
=
10062 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10063 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10065 /* default to preserving fp16 and fp64 denorms, since it's free */
10066 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10067 program
->next_fp_mode
.denorm16_64
= 0;
10069 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10071 /* preserving fp32 denorms is expensive, so only do it if asked */
10072 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10073 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10075 program
->next_fp_mode
.denorm32
= 0;
10077 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10078 program
->next_fp_mode
.round32
= fp_round_tz
;
10080 program
->next_fp_mode
.round32
= fp_round_ne
;
10082 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10083 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10085 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10087 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10090 void cleanup_cfg(Program
*program
)
10092 /* create linear_succs/logical_succs */
10093 for (Block
& BB
: program
->blocks
) {
10094 for (unsigned idx
: BB
.linear_preds
)
10095 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10096 for (unsigned idx
: BB
.logical_preds
)
10097 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10101 void select_program(Program
*program
,
10102 unsigned shader_count
,
10103 struct nir_shader
*const *shaders
,
10104 ac_shader_config
* config
,
10105 struct radv_shader_args
*args
)
10107 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10108 if_context ic_merged_wave_info
;
10110 for (unsigned i
= 0; i
< shader_count
; i
++) {
10111 nir_shader
*nir
= shaders
[i
];
10112 init_context(&ctx
, nir
);
10114 setup_fp_mode(&ctx
, nir
);
10117 /* needs to be after init_context() for FS */
10118 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10119 append_logical_start(ctx
.block
);
10121 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10122 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10124 split_arguments(&ctx
, startpgm
);
10127 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10128 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10129 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10130 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10131 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10132 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10133 ctx
.stage
== tess_eval_geometry_gs
));
10135 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : (shader_count
>= 2 && !empty_shader
);
10136 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10137 if (check_merged_wave_info
) {
10138 Builder
bld(ctx
.program
, ctx
.block
);
10140 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10141 Temp count
= i
== 0 ? get_arg(&ctx
, args
->merged_wave_info
)
10142 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10143 get_arg(&ctx
, args
->merged_wave_info
), Operand(i
* 8u));
10145 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10148 if (ctx
.program
->wave_size
== 64) {
10149 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10150 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10151 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10153 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10154 cond
= emit_extract_vector(&ctx
, mask
, 0, bld
.lm
);
10157 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10161 Builder
bld(ctx
.program
, ctx
.block
);
10163 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10164 bld
.sopp(aco_opcode::s_barrier
);
10166 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10167 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10169 } else if (ctx
.stage
== geometry_gs
)
10170 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10172 if (ctx
.stage
== fragment_fs
)
10173 handle_bc_optimize(&ctx
);
10175 visit_cf_list(&ctx
, &func
->body
);
10177 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
== vertex_vs
|| ctx
.stage
== tess_eval_vs
))
10178 emit_streamout(&ctx
, 0);
10180 if (ctx
.stage
== vertex_vs
|| ctx
.stage
== tess_eval_vs
) {
10181 create_vs_exports(&ctx
);
10182 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10183 Builder
bld(ctx
.program
, ctx
.block
);
10184 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10185 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10186 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10187 write_tcs_tess_factors(&ctx
);
10190 if (ctx
.stage
== fragment_fs
)
10191 create_fs_exports(&ctx
);
10193 if (endif_merged_wave_info
) {
10194 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10195 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10198 ralloc_free(ctx
.divergent_vals
);
10200 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10201 /* Outputs of the previous stage are inputs to the next stage */
10202 ctx
.inputs
= ctx
.outputs
;
10203 ctx
.outputs
= shader_io_state();
10207 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10209 append_logical_end(ctx
.block
);
10210 ctx
.block
->kind
|= block_kind_uniform
| block_kind_export_end
;
10211 Builder
bld(ctx
.program
, ctx
.block
);
10212 if (ctx
.program
->wb_smem_l1_on_end
)
10213 bld
.smem(aco_opcode::s_dcache_wb
, false);
10214 bld
.sopp(aco_opcode::s_endpgm
);
10216 cleanup_cfg(program
);
10219 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10220 ac_shader_config
* config
,
10221 struct radv_shader_args
*args
)
10223 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10225 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
10226 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
10227 program
->next_fp_mode
.must_flush_denorms32
= false;
10228 program
->next_fp_mode
.must_flush_denorms16_64
= false;
10229 program
->next_fp_mode
.care_about_round32
= false;
10230 program
->next_fp_mode
.care_about_round16_64
= false;
10231 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10232 program
->next_fp_mode
.denorm32
= 0;
10233 program
->next_fp_mode
.round32
= fp_round_ne
;
10234 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10235 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10237 add_startpgm(&ctx
);
10238 append_logical_start(ctx
.block
);
10240 Builder
bld(ctx
.program
, ctx
.block
);
10242 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10244 Operand
stream_id(0u);
10245 if (args
->shader_info
->so
.num_outputs
)
10246 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10247 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10249 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10251 std::stack
<Block
> endif_blocks
;
10253 for (unsigned stream
= 0; stream
< 4; stream
++) {
10254 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10257 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10258 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10261 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10263 unsigned BB_if_idx
= ctx
.block
->index
;
10264 Block BB_endif
= Block();
10265 if (!stream_id
.isConstant()) {
10267 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10268 append_logical_end(ctx
.block
);
10269 ctx
.block
->kind
|= block_kind_uniform
;
10270 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
10272 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10274 ctx
.block
= ctx
.program
->create_and_insert_block();
10275 add_edge(BB_if_idx
, ctx
.block
);
10276 bld
.reset(ctx
.block
);
10277 append_logical_start(ctx
.block
);
10280 unsigned offset
= 0;
10281 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10282 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10285 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10286 unsigned length
= util_last_bit(output_usage_mask
);
10287 for (unsigned j
= 0; j
< length
; ++j
) {
10288 if (!(output_usage_mask
& (1 << j
)))
10291 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10292 Temp voffset
= vtx_offset
;
10293 if (const_offset
>= 4096u) {
10294 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10295 const_offset
%= 4096u;
10298 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10299 mubuf
->definitions
[0] = bld
.def(v1
);
10300 mubuf
->operands
[0] = Operand(gsvs_ring
);
10301 mubuf
->operands
[1] = Operand(voffset
);
10302 mubuf
->operands
[2] = Operand(0u);
10303 mubuf
->offen
= true;
10304 mubuf
->offset
= const_offset
;
10307 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
10308 mubuf
->barrier
= barrier_none
;
10309 mubuf
->can_reorder
= true;
10311 ctx
.outputs
.mask
[i
] |= 1 << j
;
10312 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
10314 bld
.insert(std::move(mubuf
));
10320 if (args
->shader_info
->so
.num_outputs
) {
10321 emit_streamout(&ctx
, stream
);
10322 bld
.reset(ctx
.block
);
10326 create_vs_exports(&ctx
);
10327 ctx
.block
->kind
|= block_kind_export_end
;
10330 if (!stream_id
.isConstant()) {
10331 append_logical_end(ctx
.block
);
10333 /* branch from then block to endif block */
10334 bld
.branch(aco_opcode::p_branch
);
10335 add_edge(ctx
.block
->index
, &BB_endif
);
10336 ctx
.block
->kind
|= block_kind_uniform
;
10338 /* emit else block */
10339 ctx
.block
= ctx
.program
->create_and_insert_block();
10340 add_edge(BB_if_idx
, ctx
.block
);
10341 bld
.reset(ctx
.block
);
10342 append_logical_start(ctx
.block
);
10344 endif_blocks
.push(std::move(BB_endif
));
10348 while (!endif_blocks
.empty()) {
10349 Block BB_endif
= std::move(endif_blocks
.top());
10350 endif_blocks
.pop();
10352 Block
*BB_else
= ctx
.block
;
10354 append_logical_end(BB_else
);
10355 /* branch from else block to endif block */
10356 bld
.branch(aco_opcode::p_branch
);
10357 add_edge(BB_else
->index
, &BB_endif
);
10358 BB_else
->kind
|= block_kind_uniform
;
10360 /** emit endif merge block */
10361 ctx
.block
= program
->insert_block(std::move(BB_endif
));
10362 bld
.reset(ctx
.block
);
10363 append_logical_start(ctx
.block
);
10366 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10368 append_logical_end(ctx
.block
);
10369 ctx
.block
->kind
|= block_kind_uniform
;
10370 bld
.sopp(aco_opcode::s_endpgm
);
10372 cleanup_cfg(program
);