src/amd/compiler/aco_instruction_selection.cpp

   1 /*
   2  * Copyright © 2018 Valve Corporation
   3  * Copyright © 2018 Google
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <algorithm>
  27 #include <array>
  28 #include <stack>
  29 #include <map>
  30
  31 #include "ac_shader_util.h"
  32 #include "aco_ir.h"
  33 #include "aco_builder.h"
  34 #include "aco_interface.h"
  35 #include "aco_instruction_selection_setup.cpp"
  36 #include "util/fast_idiv_by_const.h"
  37
  38 namespace aco {
  39 namespace {
  40
  41 class loop_info_RAII {
  42    isel_context* ctx;
  43    unsigned header_idx_old;
  44    Block* exit_old;
  45    bool divergent_cont_old;
  46    bool divergent_branch_old;
  47    bool divergent_if_old;
  48
  49 public:
  50    loop_info_RAII(isel_context* ctx, unsigned loop_header_idx, Block* loop_exit)
  51       : ctx(ctx),
  52         header_idx_old(ctx->cf_info.parent_loop.header_idx), exit_old(ctx->cf_info.parent_loop.exit),
  53         divergent_cont_old(ctx->cf_info.parent_loop.has_divergent_continue),
  54         divergent_branch_old(ctx->cf_info.parent_loop.has_divergent_branch),
  55         divergent_if_old(ctx->cf_info.parent_if.is_divergent)
  56    {
  57       ctx->cf_info.parent_loop.header_idx = loop_header_idx;
  58       ctx->cf_info.parent_loop.exit = loop_exit;
  59       ctx->cf_info.parent_loop.has_divergent_continue = false;
  60       ctx->cf_info.parent_loop.has_divergent_branch = false;
  61       ctx->cf_info.parent_if.is_divergent = false;
  62       ctx->cf_info.loop_nest_depth = ctx->cf_info.loop_nest_depth + 1;
  63    }
  64
  65    ~loop_info_RAII()
  66    {
  67       ctx->cf_info.parent_loop.header_idx = header_idx_old;
  68       ctx->cf_info.parent_loop.exit = exit_old;
  69       ctx->cf_info.parent_loop.has_divergent_continue = divergent_cont_old;
  70       ctx->cf_info.parent_loop.has_divergent_branch = divergent_branch_old;
  71       ctx->cf_info.parent_if.is_divergent = divergent_if_old;
  72       ctx->cf_info.loop_nest_depth = ctx->cf_info.loop_nest_depth - 1;
  73       if (!ctx->cf_info.loop_nest_depth && !ctx->cf_info.parent_if.is_divergent)
  74          ctx->cf_info.exec_potentially_empty_discard = false;
  75    }
  76 };
  77
  78 struct if_context {
  79    Temp cond;
  80
  81    bool divergent_old;
  82    bool exec_potentially_empty_discard_old;
  83    bool exec_potentially_empty_break_old;
  84    uint16_t exec_potentially_empty_break_depth_old;
  85
  86    unsigned BB_if_idx;
  87    unsigned invert_idx;
  88    bool then_branch_divergent;
  89    Block BB_invert;
  90    Block BB_endif;
  91 };
  92
  93 static void visit_cf_list(struct isel_context *ctx,
  94                           struct exec_list *list);
  95
  96 static void add_logical_edge(unsigned pred_idx, Block *succ)
  97 {
  98    succ->logical_preds.emplace_back(pred_idx);
  99 }
 100
 101
 102 static void add_linear_edge(unsigned pred_idx, Block *succ)
 103 {
 104    succ->linear_preds.emplace_back(pred_idx);
 105 }
 106
 107 static void add_edge(unsigned pred_idx, Block *succ)
 108 {
 109    add_logical_edge(pred_idx, succ);
 110    add_linear_edge(pred_idx, succ);
 111 }
 112
 113 static void append_logical_start(Block *b)
 114 {
 115    Builder(NULL, b).pseudo(aco_opcode::p_logical_start);
 116 }
 117
 118 static void append_logical_end(Block *b)
 119 {
 120    Builder(NULL, b).pseudo(aco_opcode::p_logical_end);
 121 }
 122
 123 Temp get_ssa_temp(struct isel_context *ctx, nir_ssa_def *def)
 124 {
 125    assert(ctx->allocated[def->index].id());
 126    return ctx->allocated[def->index];
 127 }
 128
 129 Temp emit_mbcnt(isel_context *ctx, Definition dst,
 130                 Operand mask_lo = Operand((uint32_t) -1), Operand mask_hi = Operand((uint32_t) -1))
 131 {
 132    Builder bld(ctx->program, ctx->block);
 133    Definition lo_def = ctx->program->wave_size == 32 ? dst : bld.def(v1);
 134    Temp thread_id_lo = bld.vop3(aco_opcode::v_mbcnt_lo_u32_b32, lo_def, mask_lo, Operand(0u));
 135
 136    if (ctx->program->wave_size == 32) {
 137       return thread_id_lo;
 138    } else {
 139       Temp thread_id_hi = bld.vop3(aco_opcode::v_mbcnt_hi_u32_b32, dst, mask_hi, thread_id_lo);
 140       return thread_id_hi;
 141    }
 142 }
 143
 144 Temp emit_wqm(isel_context *ctx, Temp src, Temp dst=Temp(0, s1), bool program_needs_wqm = false)
 145 {
 146    Builder bld(ctx->program, ctx->block);
 147
 148    if (!dst.id())
 149       dst = bld.tmp(src.regClass());
 150
 151    assert(src.size() == dst.size());
 152
 153    if (ctx->stage != fragment_fs) {
 154       if (!dst.id())
 155          return src;
 156
 157       bld.copy(Definition(dst), src);
 158       return dst;
 159    }
 160
 161    bld.pseudo(aco_opcode::p_wqm, Definition(dst), src);
 162    ctx->program->needs_wqm |= program_needs_wqm;
 163    return dst;
 164 }
 165
 166 static Temp emit_bpermute(isel_context *ctx, Builder &bld, Temp index, Temp data)
 167 {
 168    if (index.regClass() == s1)
 169       return bld.readlane(bld.def(s1), data, index);
 170
 171    Temp index_x4 = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), index);
 172
 173    /* Currently not implemented on GFX6-7 */
 174    assert(ctx->options->chip_class >= GFX8);
 175
 176    if (ctx->options->chip_class <= GFX9 || ctx->program->wave_size == 32) {
 177       return bld.ds(aco_opcode::ds_bpermute_b32, bld.def(v1), index_x4, data);
 178    }
 179
 180    /* GFX10, wave64 mode:
 181     * The bpermute instruction is limited to half-wave operation, which means that it can't
 182     * properly support subgroup shuffle like older generations (or wave32 mode), so we
 183     * emulate it here.
 184     */
 185    if (!ctx->has_gfx10_wave64_bpermute) {
 186       ctx->has_gfx10_wave64_bpermute = true;
 187       ctx->program->config->num_shared_vgprs = 8; /* Shared VGPRs are allocated in groups of 8 */
 188       ctx->program->vgpr_limit -= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
 189    }
 190
 191    Temp lane_id = emit_mbcnt(ctx, bld.def(v1));
 192    Temp lane_is_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x20u), lane_id);
 193    Temp index_is_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x20u), index);
 194    Temp cmp = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm, vcc), lane_is_hi, index_is_hi);
 195
 196    return bld.reduction(aco_opcode::p_wave64_bpermute, bld.def(v1), bld.def(s2), bld.def(s1, scc),
 197                         bld.vcc(cmp), Operand(v2.as_linear()), index_x4, data, gfx10_wave64_bpermute);
 198 }
 199
 200 Temp as_vgpr(isel_context *ctx, Temp val)
 201 {
 202    if (val.type() == RegType::sgpr) {
 203       Builder bld(ctx->program, ctx->block);
 204       return bld.copy(bld.def(RegType::vgpr, val.size()), val);
 205    }
 206    assert(val.type() == RegType::vgpr);
 207    return val;
 208 }
 209
 210 //assumes a != 0xffffffff
 211 void emit_v_div_u32(isel_context *ctx, Temp dst, Temp a, uint32_t b)
 212 {
 213    assert(b != 0);
 214    Builder bld(ctx->program, ctx->block);
 215
 216    if (util_is_power_of_two_or_zero(b)) {
 217       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(dst), Operand((uint32_t)util_logbase2(b)), a);
 218       return;
 219    }
 220
 221    util_fast_udiv_info info = util_compute_fast_udiv_info(b, 32, 32);
 222
 223    assert(info.multiplier <= 0xffffffff);
 224
 225    bool pre_shift = info.pre_shift != 0;
 226    bool increment = info.increment != 0;
 227    bool multiply = true;
 228    bool post_shift = info.post_shift != 0;
 229
 230    if (!pre_shift && !increment && !multiply && !post_shift) {
 231       bld.vop1(aco_opcode::v_mov_b32, Definition(dst), a);
 232       return;
 233    }
 234
 235    Temp pre_shift_dst = a;
 236    if (pre_shift) {
 237       pre_shift_dst = (increment || multiply || post_shift) ? bld.tmp(v1) : dst;
 238       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(pre_shift_dst), Operand((uint32_t)info.pre_shift), a);
 239    }
 240
 241    Temp increment_dst = pre_shift_dst;
 242    if (increment) {
 243       increment_dst = (post_shift || multiply) ? bld.tmp(v1) : dst;
 244       bld.vadd32(Definition(increment_dst), Operand((uint32_t) info.increment), pre_shift_dst);
 245    }
 246
 247    Temp multiply_dst = increment_dst;
 248    if (multiply) {
 249       multiply_dst = post_shift ? bld.tmp(v1) : dst;
 250       bld.vop3(aco_opcode::v_mul_hi_u32, Definition(multiply_dst), increment_dst,
 251                bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand((uint32_t)info.multiplier)));
 252    }
 253
 254    if (post_shift) {
 255       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(dst), Operand((uint32_t)info.post_shift), multiply_dst);
 256    }
 257 }
 258
 259 void emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, Temp dst)
 260 {
 261    Builder bld(ctx->program, ctx->block);
 262    bld.pseudo(aco_opcode::p_extract_vector, Definition(dst), src, Operand(idx));
 263 }
 264
 265
 266 Temp emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, RegClass dst_rc)
 267 {
 268    /* no need to extract the whole vector */
 269    if (src.regClass() == dst_rc) {
 270       assert(idx == 0);
 271       return src;
 272    }
 273    assert(src.size() > idx);
 274    Builder bld(ctx->program, ctx->block);
 275    auto it = ctx->allocated_vec.find(src.id());
 276    /* the size check needs to be early because elements other than 0 may be garbage */
 277    if (it != ctx->allocated_vec.end() && it->second[0].size() == dst_rc.size()) {
 278       if (it->second[idx].regClass() == dst_rc) {
 279          return it->second[idx];
 280       } else {
 281          assert(dst_rc.size() == it->second[idx].regClass().size());
 282          assert(dst_rc.type() == RegType::vgpr && it->second[idx].type() == RegType::sgpr);
 283          return bld.copy(bld.def(dst_rc), it->second[idx]);
 284       }
 285    }
 286
 287    if (src.size() == dst_rc.size()) {
 288       assert(idx == 0);
 289       return bld.copy(bld.def(dst_rc), src);
 290    } else {
 291       Temp dst = bld.tmp(dst_rc);
 292       emit_extract_vector(ctx, src, idx, dst);
 293       return dst;
 294    }
 295 }
 296
 297 void emit_split_vector(isel_context* ctx, Temp vec_src, unsigned num_components)
 298 {
 299    if (num_components == 1)
 300       return;
 301    if (ctx->allocated_vec.find(vec_src.id()) != ctx->allocated_vec.end())
 302       return;
 303    aco_ptr<Pseudo_instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector, Format::PSEUDO, 1, num_components)};
 304    split->operands[0] = Operand(vec_src);
 305    std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 306    for (unsigned i = 0; i < num_components; i++) {
 307       elems[i] = {ctx->program->allocateId(), RegClass(vec_src.type(), vec_src.size() / num_components)};
 308       split->definitions[i] = Definition(elems[i]);
 309    }
 310    ctx->block->instructions.emplace_back(std::move(split));
 311    ctx->allocated_vec.emplace(vec_src.id(), elems);
 312 }
 313
 314 /* This vector expansion uses a mask to determine which elements in the new vector
 315  * come from the original vector. The other elements are undefined. */
 316 void expand_vector(isel_context* ctx, Temp vec_src, Temp dst, unsigned num_components, unsigned mask)
 317 {
 318    emit_split_vector(ctx, vec_src, util_bitcount(mask));
 319
 320    if (vec_src == dst)
 321       return;
 322
 323    Builder bld(ctx->program, ctx->block);
 324    if (num_components == 1) {
 325       if (dst.type() == RegType::sgpr)
 326          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec_src);
 327       else
 328          bld.copy(Definition(dst), vec_src);
 329       return;
 330    }
 331
 332    unsigned component_size = dst.size() / num_components;
 333    std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 334
 335    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1)};
 336    vec->definitions[0] = Definition(dst);
 337    unsigned k = 0;
 338    for (unsigned i = 0; i < num_components; i++) {
 339       if (mask & (1 << i)) {
 340          Temp src = emit_extract_vector(ctx, vec_src, k++, RegClass(vec_src.type(), component_size));
 341          if (dst.type() == RegType::sgpr)
 342             src = bld.as_uniform(src);
 343          vec->operands[i] = Operand(src);
 344       } else {
 345          vec->operands[i] = Operand(0u);
 346       }
 347       elems[i] = vec->operands[i].getTemp();
 348    }
 349    ctx->block->instructions.emplace_back(std::move(vec));
 350    ctx->allocated_vec.emplace(dst.id(), elems);
 351 }
 352
 353 Temp bool_to_vector_condition(isel_context *ctx, Temp val, Temp dst = Temp(0, s2))
 354 {
 355    Builder bld(ctx->program, ctx->block);
 356    if (!dst.id())
 357       dst = bld.tmp(bld.lm);
 358
 359    assert(val.regClass() == s1);
 360    assert(dst.regClass() == bld.lm);
 361
 362    return bld.sop2(Builder::s_cselect, Definition(dst), Operand((uint32_t) -1), Operand(0u), bld.scc(val));
 363 }
 364
 365 Temp bool_to_scalar_condition(isel_context *ctx, Temp val, Temp dst = Temp(0, s1))
 366 {
 367    Builder bld(ctx->program, ctx->block);
 368    if (!dst.id())
 369       dst = bld.tmp(s1);
 370
 371    assert(val.regClass() == bld.lm);
 372    assert(dst.regClass() == s1);
 373
 374    /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
 375    Temp tmp = bld.tmp(s1);
 376    bld.sop2(Builder::s_and, bld.def(bld.lm), bld.scc(Definition(tmp)), val, Operand(exec, bld.lm));
 377    return emit_wqm(ctx, tmp, dst);
 378 }
 379
 380 Temp get_alu_src(struct isel_context *ctx, nir_alu_src src, unsigned size=1)
 381 {
 382    if (src.src.ssa->num_components == 1 && src.swizzle[0] == 0 && size == 1)
 383       return get_ssa_temp(ctx, src.src.ssa);
 384
 385    if (src.src.ssa->num_components == size) {
 386       bool identity_swizzle = true;
 387       for (unsigned i = 0; identity_swizzle && i < size; i++) {
 388          if (src.swizzle[i] != i)
 389             identity_swizzle = false;
 390       }
 391       if (identity_swizzle)
 392          return get_ssa_temp(ctx, src.src.ssa);
 393    }
 394
 395    Temp vec = get_ssa_temp(ctx, src.src.ssa);
 396    unsigned elem_size = vec.size() / src.src.ssa->num_components;
 397    assert(elem_size > 0); /* TODO: 8 and 16-bit vectors not supported */
 398    assert(vec.size() % elem_size == 0);
 399
 400    RegClass elem_rc = RegClass(vec.type(), elem_size);
 401    if (size == 1) {
 402       return emit_extract_vector(ctx, vec, src.swizzle[0], elem_rc);
 403    } else {
 404       assert(size <= 4);
 405       std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 406       aco_ptr<Pseudo_instruction> vec_instr{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, size, 1)};
 407       for (unsigned i = 0; i < size; ++i) {
 408          elems[i] = emit_extract_vector(ctx, vec, src.swizzle[i], elem_rc);
 409          vec_instr->operands[i] = Operand{elems[i]};
 410       }
 411       Temp dst{ctx->program->allocateId(), RegClass(vec.type(), elem_size * size)};
 412       vec_instr->definitions[0] = Definition(dst);
 413       ctx->block->instructions.emplace_back(std::move(vec_instr));
 414       ctx->allocated_vec.emplace(dst.id(), elems);
 415       return dst;
 416    }
 417 }
 418
 419 Temp convert_pointer_to_64_bit(isel_context *ctx, Temp ptr)
 420 {
 421    if (ptr.size() == 2)
 422       return ptr;
 423    Builder bld(ctx->program, ctx->block);
 424    if (ptr.type() == RegType::vgpr)
 425       ptr = bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), ptr);
 426    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s2),
 427                      ptr, Operand((unsigned)ctx->options->address32_hi));
 428 }
 429
 430 void emit_sop2_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst, bool writes_scc)
 431 {
 432    aco_ptr<SOP2_instruction> sop2{create_instruction<SOP2_instruction>(op, Format::SOP2, 2, writes_scc ? 2 : 1)};
 433    sop2->operands[0] = Operand(get_alu_src(ctx, instr->src[0]));
 434    sop2->operands[1] = Operand(get_alu_src(ctx, instr->src[1]));
 435    sop2->definitions[0] = Definition(dst);
 436    if (writes_scc)
 437       sop2->definitions[1] = Definition(ctx->program->allocateId(), scc, s1);
 438    ctx->block->instructions.emplace_back(std::move(sop2));
 439 }
 440
 441 void emit_vop2_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst,
 442                            bool commutative, bool swap_srcs=false, bool flush_denorms = false)
 443 {
 444    Builder bld(ctx->program, ctx->block);
 445    Temp src0 = get_alu_src(ctx, instr->src[swap_srcs ? 1 : 0]);
 446    Temp src1 = get_alu_src(ctx, instr->src[swap_srcs ? 0 : 1]);
 447    if (src1.type() == RegType::sgpr) {
 448       if (commutative && src0.type() == RegType::vgpr) {
 449          Temp t = src0;
 450          src0 = src1;
 451          src1 = t;
 452       } else if (src0.type() == RegType::vgpr &&
 453                  op != aco_opcode::v_madmk_f32 &&
 454                  op != aco_opcode::v_madak_f32 &&
 455                  op != aco_opcode::v_madmk_f16 &&
 456                  op != aco_opcode::v_madak_f16) {
 457          /* If the instruction is not commutative, we emit a VOP3A instruction */
 458          bld.vop2_e64(op, Definition(dst), src0, src1);
 459          return;
 460       } else {
 461          src1 = bld.copy(bld.def(RegType::vgpr, src1.size()), src1); //TODO: as_vgpr
 462       }
 463    }
 464
 465    if (flush_denorms && ctx->program->chip_class < GFX9) {
 466       assert(dst.size() == 1);
 467       Temp tmp = bld.vop2(op, bld.def(v1), src0, src1);
 468       bld.vop2(aco_opcode::v_mul_f32, Definition(dst), Operand(0x3f800000u), tmp);
 469    } else {
 470       bld.vop2(op, Definition(dst), src0, src1);
 471    }
 472 }
 473
 474 void emit_vop3a_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst,
 475                             bool flush_denorms = false)
 476 {
 477    Temp src0 = get_alu_src(ctx, instr->src[0]);
 478    Temp src1 = get_alu_src(ctx, instr->src[1]);
 479    Temp src2 = get_alu_src(ctx, instr->src[2]);
 480
 481    /* ensure that the instruction has at most 1 sgpr operand
 482     * The optimizer will inline constants for us */
 483    if (src0.type() == RegType::sgpr && src1.type() == RegType::sgpr)
 484       src0 = as_vgpr(ctx, src0);
 485    if (src1.type() == RegType::sgpr && src2.type() == RegType::sgpr)
 486       src1 = as_vgpr(ctx, src1);
 487    if (src2.type() == RegType::sgpr && src0.type() == RegType::sgpr)
 488       src2 = as_vgpr(ctx, src2);
 489
 490    Builder bld(ctx->program, ctx->block);
 491    if (flush_denorms && ctx->program->chip_class < GFX9) {
 492       assert(dst.size() == 1);
 493       Temp tmp = bld.vop3(op, Definition(dst), src0, src1, src2);
 494       bld.vop2(aco_opcode::v_mul_f32, Definition(dst), Operand(0x3f800000u), tmp);
 495    } else {
 496       bld.vop3(op, Definition(dst), src0, src1, src2);
 497    }
 498 }
 499
 500 void emit_vop1_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 501 {
 502    Builder bld(ctx->program, ctx->block);
 503    bld.vop1(op, Definition(dst), get_alu_src(ctx, instr->src[0]));
 504 }
 505
 506 void emit_vopc_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 507 {
 508    Temp src0 = get_alu_src(ctx, instr->src[0]);
 509    Temp src1 = get_alu_src(ctx, instr->src[1]);
 510    assert(src0.size() == src1.size());
 511
 512    aco_ptr<Instruction> vopc;
 513    if (src1.type() == RegType::sgpr) {
 514       if (src0.type() == RegType::vgpr) {
 515          /* to swap the operands, we might also have to change the opcode */
 516          switch (op) {
 517             case aco_opcode::v_cmp_lt_f32:
 518                op = aco_opcode::v_cmp_gt_f32;
 519                break;
 520             case aco_opcode::v_cmp_ge_f32:
 521                op = aco_opcode::v_cmp_le_f32;
 522                break;
 523             case aco_opcode::v_cmp_lt_i32:
 524                op = aco_opcode::v_cmp_gt_i32;
 525                break;
 526             case aco_opcode::v_cmp_ge_i32:
 527                op = aco_opcode::v_cmp_le_i32;
 528                break;
 529             case aco_opcode::v_cmp_lt_u32:
 530                op = aco_opcode::v_cmp_gt_u32;
 531                break;
 532             case aco_opcode::v_cmp_ge_u32:
 533                op = aco_opcode::v_cmp_le_u32;
 534                break;
 535             case aco_opcode::v_cmp_lt_f64:
 536                op = aco_opcode::v_cmp_gt_f64;
 537                break;
 538             case aco_opcode::v_cmp_ge_f64:
 539                op = aco_opcode::v_cmp_le_f64;
 540                break;
 541             case aco_opcode::v_cmp_lt_i64:
 542                op = aco_opcode::v_cmp_gt_i64;
 543                break;
 544             case aco_opcode::v_cmp_ge_i64:
 545                op = aco_opcode::v_cmp_le_i64;
 546                break;
 547             case aco_opcode::v_cmp_lt_u64:
 548                op = aco_opcode::v_cmp_gt_u64;
 549                break;
 550             case aco_opcode::v_cmp_ge_u64:
 551                op = aco_opcode::v_cmp_le_u64;
 552                break;
 553             default: /* eq and ne are commutative */
 554                break;
 555          }
 556          Temp t = src0;
 557          src0 = src1;
 558          src1 = t;
 559       } else {
 560          src1 = as_vgpr(ctx, src1);
 561       }
 562    }
 563
 564    Builder bld(ctx->program, ctx->block);
 565    bld.vopc(op, bld.hint_vcc(Definition(dst)), src0, src1);
 566 }
 567
 568 void emit_sopc_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 569 {
 570    Temp src0 = get_alu_src(ctx, instr->src[0]);
 571    Temp src1 = get_alu_src(ctx, instr->src[1]);
 572    Builder bld(ctx->program, ctx->block);
 573
 574    assert(dst.regClass() == bld.lm);
 575    assert(src0.type() == RegType::sgpr);
 576    assert(src1.type() == RegType::sgpr);
 577    assert(src0.regClass() == src1.regClass());
 578
 579    /* Emit the SALU comparison instruction */
 580    Temp cmp = bld.sopc(op, bld.scc(bld.def(s1)), src0, src1);
 581    /* Turn the result into a per-lane bool */
 582    bool_to_vector_condition(ctx, cmp, dst);
 583 }
 584
 585 void emit_comparison(isel_context *ctx, nir_alu_instr *instr, Temp dst,
 586                      aco_opcode v32_op, aco_opcode v64_op, aco_opcode s32_op = aco_opcode::num_opcodes, aco_opcode s64_op = aco_opcode::num_opcodes)
 587 {
 588    aco_opcode s_op = instr->src[0].src.ssa->bit_size == 64 ? s64_op : s32_op;
 589    aco_opcode v_op = instr->src[0].src.ssa->bit_size == 64 ? v64_op : v32_op;
 590    bool divergent_vals = ctx->divergent_vals[instr->dest.dest.ssa.index];
 591    bool use_valu = s_op == aco_opcode::num_opcodes ||
 592                    divergent_vals ||
 593                    ctx->allocated[instr->src[0].src.ssa->index].type() == RegType::vgpr ||
 594                    ctx->allocated[instr->src[1].src.ssa->index].type() == RegType::vgpr;
 595    aco_opcode op = use_valu ? v_op : s_op;
 596    assert(op != aco_opcode::num_opcodes);
 597    assert(dst.regClass() == ctx->program->lane_mask);
 598
 599    if (use_valu)
 600       emit_vopc_instruction(ctx, instr, op, dst);
 601    else
 602       emit_sopc_instruction(ctx, instr, op, dst);
 603 }
 604
 605 void emit_boolean_logic(isel_context *ctx, nir_alu_instr *instr, Builder::WaveSpecificOpcode op, Temp dst)
 606 {
 607    Builder bld(ctx->program, ctx->block);
 608    Temp src0 = get_alu_src(ctx, instr->src[0]);
 609    Temp src1 = get_alu_src(ctx, instr->src[1]);
 610
 611    assert(dst.regClass() == bld.lm);
 612    assert(src0.regClass() == bld.lm);
 613    assert(src1.regClass() == bld.lm);
 614
 615    bld.sop2(op, Definition(dst), bld.def(s1, scc), src0, src1);
 616 }
 617
 618 void emit_bcsel(isel_context *ctx, nir_alu_instr *instr, Temp dst)
 619 {
 620    Builder bld(ctx->program, ctx->block);
 621    Temp cond = get_alu_src(ctx, instr->src[0]);
 622    Temp then = get_alu_src(ctx, instr->src[1]);
 623    Temp els = get_alu_src(ctx, instr->src[2]);
 624
 625    assert(cond.regClass() == bld.lm);
 626
 627    if (dst.type() == RegType::vgpr) {
 628       aco_ptr<Instruction> bcsel;
 629       if (dst.size() == 1) {
 630          then = as_vgpr(ctx, then);
 631          els = as_vgpr(ctx, els);
 632
 633          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), els, then, cond);
 634       } else if (dst.size() == 2) {
 635          Temp then_lo = bld.tmp(v1), then_hi = bld.tmp(v1);
 636          bld.pseudo(aco_opcode::p_split_vector, Definition(then_lo), Definition(then_hi), then);
 637          Temp else_lo = bld.tmp(v1), else_hi = bld.tmp(v1);
 638          bld.pseudo(aco_opcode::p_split_vector, Definition(else_lo), Definition(else_hi), els);
 639
 640          Temp dst0 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_lo, then_lo, cond);
 641          Temp dst1 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_hi, then_hi, cond);
 642
 643          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
 644       } else {
 645          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 646          nir_print_instr(&instr->instr, stderr);
 647          fprintf(stderr, "\n");
 648       }
 649       return;
 650    }
 651
 652    if (instr->dest.dest.ssa.bit_size == 1) {
 653       assert(dst.regClass() == bld.lm);
 654       assert(then.regClass() == bld.lm);
 655       assert(els.regClass() == bld.lm);
 656    }
 657
 658    if (!ctx->divergent_vals[instr->src[0].src.ssa->index]) { /* uniform condition and values in sgpr */
 659       if (dst.regClass() == s1 || dst.regClass() == s2) {
 660          assert((then.regClass() == s1 || then.regClass() == s2) && els.regClass() == then.regClass());
 661          assert(dst.size() == then.size());
 662          aco_opcode op = dst.regClass() == s1 ? aco_opcode::s_cselect_b32 : aco_opcode::s_cselect_b64;
 663          bld.sop2(op, Definition(dst), then, els, bld.scc(bool_to_scalar_condition(ctx, cond)));
 664       } else {
 665          fprintf(stderr, "Unimplemented uniform bcsel bit size: ");
 666          nir_print_instr(&instr->instr, stderr);
 667          fprintf(stderr, "\n");
 668       }
 669       return;
 670    }
 671
 672    /* divergent boolean bcsel
 673     * this implements bcsel on bools: dst = s0 ? s1 : s2
 674     * are going to be: dst = (s0 & s1) | (~s0 & s2) */
 675    assert(instr->dest.dest.ssa.bit_size == 1);
 676
 677    if (cond.id() != then.id())
 678       then = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), cond, then);
 679
 680    if (cond.id() == els.id())
 681       bld.sop1(Builder::s_mov, Definition(dst), then);
 682    else
 683       bld.sop2(Builder::s_or, Definition(dst), bld.def(s1, scc), then,
 684                bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), els, cond));
 685 }
 686
 687 void emit_scaled_op(isel_context *ctx, Builder& bld, Definition dst, Temp val,
 688                     aco_opcode op, uint32_t undo)
 689 {
 690    /* multiply by 16777216 to handle denormals */
 691    Temp is_denormal = bld.vopc(aco_opcode::v_cmp_class_f32, bld.hint_vcc(bld.def(bld.lm)),
 692                                as_vgpr(ctx, val), bld.copy(bld.def(v1), Operand((1u << 7) | (1u << 4))));
 693    Temp scaled = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x4b800000u), val);
 694    scaled = bld.vop1(op, bld.def(v1), scaled);
 695    scaled = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(undo), scaled);
 696
 697    Temp not_scaled = bld.vop1(op, bld.def(v1), val);
 698
 699    bld.vop2(aco_opcode::v_cndmask_b32, dst, not_scaled, scaled, is_denormal);
 700 }
 701
 702 void emit_rcp(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 703 {
 704    if (ctx->block->fp_mode.denorm32 == 0) {
 705       bld.vop1(aco_opcode::v_rcp_f32, dst, val);
 706       return;
 707    }
 708
 709    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_rcp_f32, 0x4b800000u);
 710 }
 711
 712 void emit_rsq(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 713 {
 714    if (ctx->block->fp_mode.denorm32 == 0) {
 715       bld.vop1(aco_opcode::v_rsq_f32, dst, val);
 716       return;
 717    }
 718
 719    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_rsq_f32, 0x45800000u);
 720 }
 721
 722 void emit_sqrt(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 723 {
 724    if (ctx->block->fp_mode.denorm32 == 0) {
 725       bld.vop1(aco_opcode::v_sqrt_f32, dst, val);
 726       return;
 727    }
 728
 729    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_sqrt_f32, 0x39800000u);
 730 }
 731
 732 void emit_log2(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 733 {
 734    if (ctx->block->fp_mode.denorm32 == 0) {
 735       bld.vop1(aco_opcode::v_log_f32, dst, val);
 736       return;
 737    }
 738
 739    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_log_f32, 0xc1c00000u);
 740 }
 741
 742 Temp emit_trunc_f64(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 743 {
 744    if (ctx->options->chip_class >= GFX7)
 745       return bld.vop1(aco_opcode::v_trunc_f64, Definition(dst), val);
 746
 747    /* GFX6 doesn't support V_TRUNC_F64, lower it. */
 748    /* TODO: create more efficient code! */
 749    if (val.type() == RegType::sgpr)
 750       val = as_vgpr(ctx, val);
 751
 752    /* Split the input value. */
 753    Temp val_lo = bld.tmp(v1), val_hi = bld.tmp(v1);
 754    bld.pseudo(aco_opcode::p_split_vector, Definition(val_lo), Definition(val_hi), val);
 755
 756    /* Extract the exponent and compute the unbiased value. */
 757    Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f64, bld.def(v1), val);
 758
 759    /* Extract the fractional part. */
 760    Temp fract_mask = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(-1u), Operand(0x000fffffu));
 761    fract_mask = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), fract_mask, exponent);
 762
 763    Temp fract_mask_lo = bld.tmp(v1), fract_mask_hi = bld.tmp(v1);
 764    bld.pseudo(aco_opcode::p_split_vector, Definition(fract_mask_lo), Definition(fract_mask_hi), fract_mask);
 765
 766    Temp fract_lo = bld.tmp(v1), fract_hi = bld.tmp(v1);
 767    Temp tmp = bld.vop1(aco_opcode::v_not_b32, bld.def(v1), fract_mask_lo);
 768    fract_lo = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), val_lo, tmp);
 769    tmp = bld.vop1(aco_opcode::v_not_b32, bld.def(v1), fract_mask_hi);
 770    fract_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), val_hi, tmp);
 771
 772    /* Get the sign bit. */
 773    Temp sign = bld.vop2(aco_opcode::v_ashr_i32, bld.def(v1), Operand(31u), val_hi);
 774
 775    /* Decide the operation to apply depending on the unbiased exponent. */
 776    Temp exp_lt0 = bld.vopc_e64(aco_opcode::v_cmp_lt_i32, bld.hint_vcc(bld.def(bld.lm)), exponent, Operand(0u));
 777    Temp dst_lo = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), fract_lo, bld.copy(bld.def(v1), Operand(0u)), exp_lt0);
 778    Temp dst_hi = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), fract_hi, sign, exp_lt0);
 779    Temp exp_gt51 = bld.vopc_e64(aco_opcode::v_cmp_gt_i32, bld.def(s2), exponent, Operand(51u));
 780    dst_lo = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), dst_lo, val_lo, exp_gt51);
 781    dst_hi = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), dst_hi, val_hi, exp_gt51);
 782
 783    return bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst_lo, dst_hi);
 784 }
 785
 786 Temp emit_floor_f64(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 787 {
 788    if (ctx->options->chip_class >= GFX7)
 789       return bld.vop1(aco_opcode::v_floor_f64, Definition(dst), val);
 790
 791    /* GFX6 doesn't support V_FLOOR_F64, lower it. */
 792    Temp src0 = as_vgpr(ctx, val);
 793
 794    Temp mask = bld.copy(bld.def(s1), Operand(3u)); /* isnan */
 795    Temp min_val = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(-1u), Operand(0x3fefffffu));
 796
 797    Temp isnan = bld.vopc_e64(aco_opcode::v_cmp_class_f64, bld.hint_vcc(bld.def(bld.lm)), src0, mask);
 798    Temp fract = bld.vop1(aco_opcode::v_fract_f64, bld.def(v2), src0);
 799    Temp min = bld.vop3(aco_opcode::v_min_f64, bld.def(v2), fract, min_val);
 800
 801    Temp then_lo = bld.tmp(v1), then_hi = bld.tmp(v1);
 802    bld.pseudo(aco_opcode::p_split_vector, Definition(then_lo), Definition(then_hi), src0);
 803    Temp else_lo = bld.tmp(v1), else_hi = bld.tmp(v1);
 804    bld.pseudo(aco_opcode::p_split_vector, Definition(else_lo), Definition(else_hi), min);
 805
 806    Temp dst0 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_lo, then_lo, isnan);
 807    Temp dst1 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_hi, then_hi, isnan);
 808
 809    Temp v = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), dst0, dst1);
 810
 811    Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst), src0, v);
 812    static_cast<VOP3A_instruction*>(add)->neg[1] = true;
 813
 814    return add->definitions[0].getTemp();
 815 }
 816
 817 void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
 818 {
 819    if (!instr->dest.dest.is_ssa) {
 820       fprintf(stderr, "nir alu dst not in ssa: ");
 821       nir_print_instr(&instr->instr, stderr);
 822       fprintf(stderr, "\n");
 823       abort();
 824    }
 825    Builder bld(ctx->program, ctx->block);
 826    Temp dst = get_ssa_temp(ctx, &instr->dest.dest.ssa);
 827    switch(instr->op) {
 828    case nir_op_vec2:
 829    case nir_op_vec3:
 830    case nir_op_vec4: {
 831       std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 832       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.dest.ssa.num_components, 1)};
 833       for (unsigned i = 0; i < instr->dest.dest.ssa.num_components; ++i) {
 834          elems[i] = get_alu_src(ctx, instr->src[i]);
 835          vec->operands[i] = Operand{elems[i]};
 836       }
 837       vec->definitions[0] = Definition(dst);
 838       ctx->block->instructions.emplace_back(std::move(vec));
 839       ctx->allocated_vec.emplace(dst.id(), elems);
 840       break;
 841    }
 842    case nir_op_mov: {
 843       Temp src = get_alu_src(ctx, instr->src[0]);
 844       aco_ptr<Instruction> mov;
 845       if (dst.type() == RegType::sgpr) {
 846          if (src.type() == RegType::vgpr)
 847             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), src);
 848          else if (src.regClass() == s1)
 849             bld.sop1(aco_opcode::s_mov_b32, Definition(dst), src);
 850          else if (src.regClass() == s2)
 851             bld.sop1(aco_opcode::s_mov_b64, Definition(dst), src);
 852          else
 853             unreachable("wrong src register class for nir_op_imov");
 854       } else if (dst.regClass() == v1) {
 855          bld.vop1(aco_opcode::v_mov_b32, Definition(dst), src);
 856       } else if (dst.regClass() == v2) {
 857          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src);
 858       } else {
 859          nir_print_instr(&instr->instr, stderr);
 860          unreachable("Should have been lowered to scalar.");
 861       }
 862       break;
 863    }
 864    case nir_op_inot: {
 865       Temp src = get_alu_src(ctx, instr->src[0]);
 866       if (instr->dest.dest.ssa.bit_size == 1) {
 867          assert(src.regClass() == bld.lm);
 868          assert(dst.regClass() == bld.lm);
 869          /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
 870          Temp tmp = bld.sop1(Builder::s_not, bld.def(bld.lm), bld.def(s1, scc), src);
 871          bld.sop2(Builder::s_and, Definition(dst), bld.def(s1, scc), tmp, Operand(exec, bld.lm));
 872       } else if (dst.regClass() == v1) {
 873          emit_vop1_instruction(ctx, instr, aco_opcode::v_not_b32, dst);
 874       } else if (dst.type() == RegType::sgpr) {
 875          aco_opcode opcode = dst.size() == 1 ? aco_opcode::s_not_b32 : aco_opcode::s_not_b64;
 876          bld.sop1(opcode, Definition(dst), bld.def(s1, scc), src);
 877       } else {
 878          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 879          nir_print_instr(&instr->instr, stderr);
 880          fprintf(stderr, "\n");
 881       }
 882       break;
 883    }
 884    case nir_op_ineg: {
 885       Temp src = get_alu_src(ctx, instr->src[0]);
 886       if (dst.regClass() == v1) {
 887          bld.vsub32(Definition(dst), Operand(0u), Operand(src));
 888       } else if (dst.regClass() == s1) {
 889          bld.sop2(aco_opcode::s_mul_i32, Definition(dst), Operand((uint32_t) -1), src);
 890       } else if (dst.size() == 2) {
 891          Temp src0 = bld.tmp(dst.type(), 1);
 892          Temp src1 = bld.tmp(dst.type(), 1);
 893          bld.pseudo(aco_opcode::p_split_vector, Definition(src0), Definition(src1), src);
 894
 895          if (dst.regClass() == s2) {
 896             Temp carry = bld.tmp(s1);
 897             Temp dst0 = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(carry)), Operand(0u), src0);
 898             Temp dst1 = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), src1, carry);
 899             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
 900          } else {
 901             Temp lower = bld.tmp(v1);
 902             Temp borrow = bld.vsub32(Definition(lower), Operand(0u), src0, true).def(1).getTemp();
 903             Temp upper = bld.vsub32(bld.def(v1), Operand(0u), src1, false, borrow);
 904             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
 905          }
 906       } else {
 907          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 908          nir_print_instr(&instr->instr, stderr);
 909          fprintf(stderr, "\n");
 910       }
 911       break;
 912    }
 913    case nir_op_iabs: {
 914       if (dst.regClass() == s1) {
 915          bld.sop1(aco_opcode::s_abs_i32, Definition(dst), bld.def(s1, scc), get_alu_src(ctx, instr->src[0]));
 916       } else if (dst.regClass() == v1) {
 917          Temp src = get_alu_src(ctx, instr->src[0]);
 918          bld.vop2(aco_opcode::v_max_i32, Definition(dst), src, bld.vsub32(bld.def(v1), Operand(0u), src));
 919       } else {
 920          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 921          nir_print_instr(&instr->instr, stderr);
 922          fprintf(stderr, "\n");
 923       }
 924       break;
 925    }
 926    case nir_op_isign: {
 927       Temp src = get_alu_src(ctx, instr->src[0]);
 928       if (dst.regClass() == s1) {
 929          Temp tmp = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
 930          Temp gtz = bld.sopc(aco_opcode::s_cmp_gt_i32, bld.def(s1, scc), src, Operand(0u));
 931          bld.sop2(aco_opcode::s_add_i32, Definition(dst), bld.def(s1, scc), gtz, tmp);
 932       } else if (dst.regClass() == s2) {
 933          Temp neg = bld.sop2(aco_opcode::s_ashr_i64, bld.def(s2), bld.def(s1, scc), src, Operand(63u));
 934          Temp neqz;
 935          if (ctx->program->chip_class >= GFX8)
 936             neqz = bld.sopc(aco_opcode::s_cmp_lg_u64, bld.def(s1, scc), src, Operand(0u));
 937          else
 938             neqz = bld.sop2(aco_opcode::s_or_b64, bld.def(s2), bld.def(s1, scc), src, Operand(0u)).def(1).getTemp();
 939          /* SCC gets zero-extended to 64 bit */
 940          bld.sop2(aco_opcode::s_or_b64, Definition(dst), bld.def(s1, scc), neg, bld.scc(neqz));
 941       } else if (dst.regClass() == v1) {
 942          Temp tmp = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
 943          Temp gtz = bld.vopc(aco_opcode::v_cmp_ge_i32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
 944          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(1u), tmp, gtz);
 945       } else if (dst.regClass() == v2) {
 946          Temp upper = emit_extract_vector(ctx, src, 1, v1);
 947          Temp neg = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), upper);
 948          Temp gtz = bld.vopc(aco_opcode::v_cmp_ge_i64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
 949          Temp lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(1u), neg, gtz);
 950          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), neg, gtz);
 951          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
 952       } else {
 953          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 954          nir_print_instr(&instr->instr, stderr);
 955          fprintf(stderr, "\n");
 956       }
 957       break;
 958    }
 959    case nir_op_imax: {
 960       if (dst.regClass() == v1) {
 961          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_i32, dst, true);
 962       } else if (dst.regClass() == s1) {
 963          emit_sop2_instruction(ctx, instr, aco_opcode::s_max_i32, dst, true);
 964       } else {
 965          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 966          nir_print_instr(&instr->instr, stderr);
 967          fprintf(stderr, "\n");
 968       }
 969       break;
 970    }
 971    case nir_op_umax: {
 972       if (dst.regClass() == v1) {
 973          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_u32, dst, true);
 974       } else if (dst.regClass() == s1) {
 975          emit_sop2_instruction(ctx, instr, aco_opcode::s_max_u32, dst, true);
 976       } else {
 977          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 978          nir_print_instr(&instr->instr, stderr);
 979          fprintf(stderr, "\n");
 980       }
 981       break;
 982    }
 983    case nir_op_imin: {
 984       if (dst.regClass() == v1) {
 985          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_i32, dst, true);
 986       } else if (dst.regClass() == s1) {
 987          emit_sop2_instruction(ctx, instr, aco_opcode::s_min_i32, dst, true);
 988       } else {
 989          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 990          nir_print_instr(&instr->instr, stderr);
 991          fprintf(stderr, "\n");
 992       }
 993       break;
 994    }
 995    case nir_op_umin: {
 996       if (dst.regClass() == v1) {
 997          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_u32, dst, true);
 998       } else if (dst.regClass() == s1) {
 999          emit_sop2_instruction(ctx, instr, aco_opcode::s_min_u32, dst, true);
1000       } else {
1001          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1002          nir_print_instr(&instr->instr, stderr);
1003          fprintf(stderr, "\n");
1004       }
1005       break;
1006    }
1007    case nir_op_ior: {
1008       if (instr->dest.dest.ssa.bit_size == 1) {
1009          emit_boolean_logic(ctx, instr, Builder::s_or, dst);
1010       } else if (dst.regClass() == v1) {
1011          emit_vop2_instruction(ctx, instr, aco_opcode::v_or_b32, dst, true);
1012       } else if (dst.regClass() == s1) {
1013          emit_sop2_instruction(ctx, instr, aco_opcode::s_or_b32, dst, true);
1014       } else if (dst.regClass() == s2) {
1015          emit_sop2_instruction(ctx, instr, aco_opcode::s_or_b64, dst, true);
1016       } else {
1017          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1018          nir_print_instr(&instr->instr, stderr);
1019          fprintf(stderr, "\n");
1020       }
1021       break;
1022    }
1023    case nir_op_iand: {
1024       if (instr->dest.dest.ssa.bit_size == 1) {
1025          emit_boolean_logic(ctx, instr, Builder::s_and, dst);
1026       } else if (dst.regClass() == v1) {
1027          emit_vop2_instruction(ctx, instr, aco_opcode::v_and_b32, dst, true);
1028       } else if (dst.regClass() == s1) {
1029          emit_sop2_instruction(ctx, instr, aco_opcode::s_and_b32, dst, true);
1030       } else if (dst.regClass() == s2) {
1031          emit_sop2_instruction(ctx, instr, aco_opcode::s_and_b64, dst, true);
1032       } else {
1033          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1034          nir_print_instr(&instr->instr, stderr);
1035          fprintf(stderr, "\n");
1036       }
1037       break;
1038    }
1039    case nir_op_ixor: {
1040       if (instr->dest.dest.ssa.bit_size == 1) {
1041          emit_boolean_logic(ctx, instr, Builder::s_xor, dst);
1042       } else if (dst.regClass() == v1) {
1043          emit_vop2_instruction(ctx, instr, aco_opcode::v_xor_b32, dst, true);
1044       } else if (dst.regClass() == s1) {
1045          emit_sop2_instruction(ctx, instr, aco_opcode::s_xor_b32, dst, true);
1046       } else if (dst.regClass() == s2) {
1047          emit_sop2_instruction(ctx, instr, aco_opcode::s_xor_b64, dst, true);
1048       } else {
1049          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1050          nir_print_instr(&instr->instr, stderr);
1051          fprintf(stderr, "\n");
1052       }
1053       break;
1054    }
1055    case nir_op_ushr: {
1056       if (dst.regClass() == v1) {
1057          emit_vop2_instruction(ctx, instr, aco_opcode::v_lshrrev_b32, dst, false, true);
1058       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
1059          bld.vop3(aco_opcode::v_lshrrev_b64, Definition(dst),
1060                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
1061       } else if (dst.regClass() == v2) {
1062          bld.vop3(aco_opcode::v_lshr_b64, Definition(dst),
1063                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1064       } else if (dst.regClass() == s2) {
1065          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshr_b64, dst, true);
1066       } else if (dst.regClass() == s1) {
1067          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshr_b32, dst, true);
1068       } else {
1069          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1070          nir_print_instr(&instr->instr, stderr);
1071          fprintf(stderr, "\n");
1072       }
1073       break;
1074    }
1075    case nir_op_ishl: {
1076       if (dst.regClass() == v1) {
1077          emit_vop2_instruction(ctx, instr, aco_opcode::v_lshlrev_b32, dst, false, true);
1078       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
1079          bld.vop3(aco_opcode::v_lshlrev_b64, Definition(dst),
1080                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
1081       } else if (dst.regClass() == v2) {
1082          bld.vop3(aco_opcode::v_lshl_b64, Definition(dst),
1083                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1084       } else if (dst.regClass() == s1) {
1085          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshl_b32, dst, true);
1086       } else if (dst.regClass() == s2) {
1087          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshl_b64, dst, true);
1088       } else {
1089          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1090          nir_print_instr(&instr->instr, stderr);
1091          fprintf(stderr, "\n");
1092       }
1093       break;
1094    }
1095    case nir_op_ishr: {
1096       if (dst.regClass() == v1) {
1097          emit_vop2_instruction(ctx, instr, aco_opcode::v_ashrrev_i32, dst, false, true);
1098       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
1099          bld.vop3(aco_opcode::v_ashrrev_i64, Definition(dst),
1100                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
1101       } else if (dst.regClass() == v2) {
1102          bld.vop3(aco_opcode::v_ashr_i64, Definition(dst),
1103                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1104       } else if (dst.regClass() == s1) {
1105          emit_sop2_instruction(ctx, instr, aco_opcode::s_ashr_i32, dst, true);
1106       } else if (dst.regClass() == s2) {
1107          emit_sop2_instruction(ctx, instr, aco_opcode::s_ashr_i64, dst, true);
1108       } else {
1109          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1110          nir_print_instr(&instr->instr, stderr);
1111          fprintf(stderr, "\n");
1112       }
1113       break;
1114    }
1115    case nir_op_find_lsb: {
1116       Temp src = get_alu_src(ctx, instr->src[0]);
1117       if (src.regClass() == s1) {
1118          bld.sop1(aco_opcode::s_ff1_i32_b32, Definition(dst), src);
1119       } else if (src.regClass() == v1) {
1120          emit_vop1_instruction(ctx, instr, aco_opcode::v_ffbl_b32, dst);
1121       } else if (src.regClass() == s2) {
1122          bld.sop1(aco_opcode::s_ff1_i32_b64, Definition(dst), src);
1123       } else {
1124          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1125          nir_print_instr(&instr->instr, stderr);
1126          fprintf(stderr, "\n");
1127       }
1128       break;
1129    }
1130    case nir_op_ufind_msb:
1131    case nir_op_ifind_msb: {
1132       Temp src = get_alu_src(ctx, instr->src[0]);
1133       if (src.regClass() == s1 || src.regClass() == s2) {
1134          aco_opcode op = src.regClass() == s2 ?
1135                          (instr->op == nir_op_ufind_msb ? aco_opcode::s_flbit_i32_b64 : aco_opcode::s_flbit_i32_i64) :
1136                          (instr->op == nir_op_ufind_msb ? aco_opcode::s_flbit_i32_b32 : aco_opcode::s_flbit_i32);
1137          Temp msb_rev = bld.sop1(op, bld.def(s1), src);
1138
1139          Builder::Result sub = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc),
1140                                         Operand(src.size() * 32u - 1u), msb_rev);
1141          Temp msb = sub.def(0).getTemp();
1142          Temp carry = sub.def(1).getTemp();
1143
1144          bld.sop2(aco_opcode::s_cselect_b32, Definition(dst), Operand((uint32_t)-1), msb, bld.scc(carry));
1145       } else if (src.regClass() == v1) {
1146          aco_opcode op = instr->op == nir_op_ufind_msb ? aco_opcode::v_ffbh_u32 : aco_opcode::v_ffbh_i32;
1147          Temp msb_rev = bld.tmp(v1);
1148          emit_vop1_instruction(ctx, instr, op, msb_rev);
1149          Temp msb = bld.tmp(v1);
1150          Temp carry = bld.vsub32(Definition(msb), Operand(31u), Operand(msb_rev), true).def(1).getTemp();
1151          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), msb, Operand((uint32_t)-1), carry);
1152       } else {
1153          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1154          nir_print_instr(&instr->instr, stderr);
1155          fprintf(stderr, "\n");
1156       }
1157       break;
1158    }
1159    case nir_op_bitfield_reverse: {
1160       if (dst.regClass() == s1) {
1161          bld.sop1(aco_opcode::s_brev_b32, Definition(dst), get_alu_src(ctx, instr->src[0]));
1162       } else if (dst.regClass() == v1) {
1163          bld.vop1(aco_opcode::v_bfrev_b32, Definition(dst), get_alu_src(ctx, instr->src[0]));
1164       } else {
1165          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1166          nir_print_instr(&instr->instr, stderr);
1167          fprintf(stderr, "\n");
1168       }
1169       break;
1170    }
1171    case nir_op_iadd: {
1172       if (dst.regClass() == s1) {
1173          emit_sop2_instruction(ctx, instr, aco_opcode::s_add_u32, dst, true);
1174          break;
1175       }
1176
1177       Temp src0 = get_alu_src(ctx, instr->src[0]);
1178       Temp src1 = get_alu_src(ctx, instr->src[1]);
1179       if (dst.regClass() == v1) {
1180          bld.vadd32(Definition(dst), Operand(src0), Operand(src1));
1181          break;
1182       }
1183
1184       assert(src0.size() == 2 && src1.size() == 2);
1185       Temp src00 = bld.tmp(src0.type(), 1);
1186       Temp src01 = bld.tmp(dst.type(), 1);
1187       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1188       Temp src10 = bld.tmp(src1.type(), 1);
1189       Temp src11 = bld.tmp(dst.type(), 1);
1190       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1191
1192       if (dst.regClass() == s2) {
1193          Temp carry = bld.tmp(s1);
1194          Temp dst0 = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1195          Temp dst1 = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), src01, src11, bld.scc(carry));
1196          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1197       } else if (dst.regClass() == v2) {
1198          Temp dst0 = bld.tmp(v1);
1199          Temp carry = bld.vadd32(Definition(dst0), src00, src10, true).def(1).getTemp();
1200          Temp dst1 = bld.vadd32(bld.def(v1), src01, src11, false, carry);
1201          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1202       } else {
1203          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1204          nir_print_instr(&instr->instr, stderr);
1205          fprintf(stderr, "\n");
1206       }
1207       break;
1208    }
1209    case nir_op_uadd_sat: {
1210       Temp src0 = get_alu_src(ctx, instr->src[0]);
1211       Temp src1 = get_alu_src(ctx, instr->src[1]);
1212       if (dst.regClass() == s1) {
1213          Temp tmp = bld.tmp(s1), carry = bld.tmp(s1);
1214          bld.sop2(aco_opcode::s_add_u32, Definition(tmp), bld.scc(Definition(carry)),
1215                   src0, src1);
1216          bld.sop2(aco_opcode::s_cselect_b32, Definition(dst), Operand((uint32_t) -1), tmp, bld.scc(carry));
1217       } else if (dst.regClass() == v1) {
1218          if (ctx->options->chip_class >= GFX9) {
1219             aco_ptr<VOP3A_instruction> add{create_instruction<VOP3A_instruction>(aco_opcode::v_add_u32, asVOP3(Format::VOP2), 2, 1)};
1220             add->operands[0] = Operand(src0);
1221             add->operands[1] = Operand(src1);
1222             add->definitions[0] = Definition(dst);
1223             add->clamp = 1;
1224             ctx->block->instructions.emplace_back(std::move(add));
1225          } else {
1226             if (src1.regClass() != v1)
1227                std::swap(src0, src1);
1228             assert(src1.regClass() == v1);
1229             Temp tmp = bld.tmp(v1);
1230             Temp carry = bld.vadd32(Definition(tmp), src0, src1, true).def(1).getTemp();
1231             bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), tmp, Operand((uint32_t) -1), carry);
1232          }
1233       } else {
1234          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1235          nir_print_instr(&instr->instr, stderr);
1236          fprintf(stderr, "\n");
1237       }
1238       break;
1239    }
1240    case nir_op_uadd_carry: {
1241       Temp src0 = get_alu_src(ctx, instr->src[0]);
1242       Temp src1 = get_alu_src(ctx, instr->src[1]);
1243       if (dst.regClass() == s1) {
1244          bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(dst)), src0, src1);
1245          break;
1246       }
1247       if (dst.regClass() == v1) {
1248          Temp carry = bld.vadd32(bld.def(v1), src0, src1, true).def(1).getTemp();
1249          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), carry);
1250          break;
1251       }
1252
1253       Temp src00 = bld.tmp(src0.type(), 1);
1254       Temp src01 = bld.tmp(dst.type(), 1);
1255       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1256       Temp src10 = bld.tmp(src1.type(), 1);
1257       Temp src11 = bld.tmp(dst.type(), 1);
1258       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1259       if (dst.regClass() == s2) {
1260          Temp carry = bld.tmp(s1);
1261          bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1262          carry = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.scc(bld.def(s1)), src01, src11, bld.scc(carry)).def(1).getTemp();
1263          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), carry, Operand(0u));
1264       } else if (dst.regClass() == v2) {
1265          Temp carry = bld.vadd32(bld.def(v1), src00, src10, true).def(1).getTemp();
1266          carry = bld.vadd32(bld.def(v1), src01, src11, true, carry).def(1).getTemp();
1267          carry = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand(1u), carry);
1268          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), carry, Operand(0u));
1269       } else {
1270          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1271          nir_print_instr(&instr->instr, stderr);
1272          fprintf(stderr, "\n");
1273       }
1274       break;
1275    }
1276    case nir_op_isub: {
1277       if (dst.regClass() == s1) {
1278          emit_sop2_instruction(ctx, instr, aco_opcode::s_sub_i32, dst, true);
1279          break;
1280       }
1281
1282       Temp src0 = get_alu_src(ctx, instr->src[0]);
1283       Temp src1 = get_alu_src(ctx, instr->src[1]);
1284       if (dst.regClass() == v1) {
1285          bld.vsub32(Definition(dst), src0, src1);
1286          break;
1287       }
1288
1289       Temp src00 = bld.tmp(src0.type(), 1);
1290       Temp src01 = bld.tmp(dst.type(), 1);
1291       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1292       Temp src10 = bld.tmp(src1.type(), 1);
1293       Temp src11 = bld.tmp(dst.type(), 1);
1294       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1295       if (dst.regClass() == s2) {
1296          Temp carry = bld.tmp(s1);
1297          Temp dst0 = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1298          Temp dst1 = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), src01, src11, carry);
1299          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1300       } else if (dst.regClass() == v2) {
1301          Temp lower = bld.tmp(v1);
1302          Temp borrow = bld.vsub32(Definition(lower), src00, src10, true).def(1).getTemp();
1303          Temp upper = bld.vsub32(bld.def(v1), src01, src11, false, borrow);
1304          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1305       } else {
1306          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1307          nir_print_instr(&instr->instr, stderr);
1308          fprintf(stderr, "\n");
1309       }
1310       break;
1311    }
1312    case nir_op_usub_borrow: {
1313       Temp src0 = get_alu_src(ctx, instr->src[0]);
1314       Temp src1 = get_alu_src(ctx, instr->src[1]);
1315       if (dst.regClass() == s1) {
1316          bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(dst)), src0, src1);
1317          break;
1318       } else if (dst.regClass() == v1) {
1319          Temp borrow = bld.vsub32(bld.def(v1), src0, src1, true).def(1).getTemp();
1320          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), borrow);
1321          break;
1322       }
1323
1324       Temp src00 = bld.tmp(src0.type(), 1);
1325       Temp src01 = bld.tmp(dst.type(), 1);
1326       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1327       Temp src10 = bld.tmp(src1.type(), 1);
1328       Temp src11 = bld.tmp(dst.type(), 1);
1329       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1330       if (dst.regClass() == s2) {
1331          Temp borrow = bld.tmp(s1);
1332          bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(borrow)), src00, src10);
1333          borrow = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.scc(bld.def(s1)), src01, src11, bld.scc(borrow)).def(1).getTemp();
1334          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), borrow, Operand(0u));
1335       } else if (dst.regClass() == v2) {
1336          Temp borrow = bld.vsub32(bld.def(v1), src00, src10, true).def(1).getTemp();
1337          borrow = bld.vsub32(bld.def(v1), src01, src11, true, Operand(borrow)).def(1).getTemp();
1338          borrow = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand(1u), borrow);
1339          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), borrow, Operand(0u));
1340       } else {
1341          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1342          nir_print_instr(&instr->instr, stderr);
1343          fprintf(stderr, "\n");
1344       }
1345       break;
1346    }
1347    case nir_op_imul: {
1348       if (dst.regClass() == v1) {
1349          bld.vop3(aco_opcode::v_mul_lo_u32, Definition(dst),
1350                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1351       } else if (dst.regClass() == s1) {
1352          emit_sop2_instruction(ctx, instr, aco_opcode::s_mul_i32, dst, false);
1353       } else {
1354          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1355          nir_print_instr(&instr->instr, stderr);
1356          fprintf(stderr, "\n");
1357       }
1358       break;
1359    }
1360    case nir_op_umul_high: {
1361       if (dst.regClass() == v1) {
1362          bld.vop3(aco_opcode::v_mul_hi_u32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1363       } else if (dst.regClass() == s1 && ctx->options->chip_class >= GFX9) {
1364          bld.sop2(aco_opcode::s_mul_hi_u32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1365       } else if (dst.regClass() == s1) {
1366          Temp tmp = bld.vop3(aco_opcode::v_mul_hi_u32, bld.def(v1), get_alu_src(ctx, instr->src[0]),
1367                              as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1368          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), tmp);
1369       } else {
1370          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1371          nir_print_instr(&instr->instr, stderr);
1372          fprintf(stderr, "\n");
1373       }
1374       break;
1375    }
1376    case nir_op_imul_high: {
1377       if (dst.regClass() == v1) {
1378          bld.vop3(aco_opcode::v_mul_hi_i32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1379       } else if (dst.regClass() == s1 && ctx->options->chip_class >= GFX9) {
1380          bld.sop2(aco_opcode::s_mul_hi_i32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1381       } else if (dst.regClass() == s1) {
1382          Temp tmp = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), get_alu_src(ctx, instr->src[0]),
1383                              as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1384          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), tmp);
1385       } else {
1386          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1387          nir_print_instr(&instr->instr, stderr);
1388          fprintf(stderr, "\n");
1389       }
1390       break;
1391    }
1392    case nir_op_fmul: {
1393       if (dst.size() == 1) {
1394          emit_vop2_instruction(ctx, instr, aco_opcode::v_mul_f32, dst, true);
1395       } else if (dst.size() == 2) {
1396          bld.vop3(aco_opcode::v_mul_f64, Definition(dst), get_alu_src(ctx, instr->src[0]),
1397                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1398       } else {
1399          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1400          nir_print_instr(&instr->instr, stderr);
1401          fprintf(stderr, "\n");
1402       }
1403       break;
1404    }
1405    case nir_op_fadd: {
1406       if (dst.size() == 1) {
1407          emit_vop2_instruction(ctx, instr, aco_opcode::v_add_f32, dst, true);
1408       } else if (dst.size() == 2) {
1409          bld.vop3(aco_opcode::v_add_f64, Definition(dst), get_alu_src(ctx, instr->src[0]),
1410                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1411       } else {
1412          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1413          nir_print_instr(&instr->instr, stderr);
1414          fprintf(stderr, "\n");
1415       }
1416       break;
1417    }
1418    case nir_op_fsub: {
1419       Temp src0 = get_alu_src(ctx, instr->src[0]);
1420       Temp src1 = get_alu_src(ctx, instr->src[1]);
1421       if (dst.size() == 1) {
1422          if (src1.type() == RegType::vgpr || src0.type() != RegType::vgpr)
1423             emit_vop2_instruction(ctx, instr, aco_opcode::v_sub_f32, dst, false);
1424          else
1425             emit_vop2_instruction(ctx, instr, aco_opcode::v_subrev_f32, dst, true);
1426       } else if (dst.size() == 2) {
1427          Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst),
1428                                      get_alu_src(ctx, instr->src[0]),
1429                                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1430          VOP3A_instruction* sub = static_cast<VOP3A_instruction*>(add);
1431          sub->neg[1] = true;
1432       } else {
1433          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1434          nir_print_instr(&instr->instr, stderr);
1435          fprintf(stderr, "\n");
1436       }
1437       break;
1438    }
1439    case nir_op_fmax: {
1440       if (dst.size() == 1) {
1441          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_f32, dst, true, false, ctx->block->fp_mode.must_flush_denorms32);
1442       } else if (dst.size() == 2) {
1443          if (ctx->block->fp_mode.must_flush_denorms16_64 && ctx->program->chip_class < GFX9) {
1444             Temp tmp = bld.vop3(aco_opcode::v_max_f64, bld.def(v2),
1445                                 get_alu_src(ctx, instr->src[0]),
1446                                 as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1447             bld.vop3(aco_opcode::v_mul_f64, Definition(dst), Operand(0x3FF0000000000000lu), tmp);
1448          } else {
1449             bld.vop3(aco_opcode::v_max_f64, Definition(dst),
1450                      get_alu_src(ctx, instr->src[0]),
1451                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1452          }
1453       } else {
1454          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1455          nir_print_instr(&instr->instr, stderr);
1456          fprintf(stderr, "\n");
1457       }
1458       break;
1459    }
1460    case nir_op_fmin: {
1461       if (dst.size() == 1) {
1462          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_f32, dst, true, false, ctx->block->fp_mode.must_flush_denorms32);
1463       } else if (dst.size() == 2) {
1464          if (ctx->block->fp_mode.must_flush_denorms16_64 && ctx->program->chip_class < GFX9) {
1465             Temp tmp = bld.vop3(aco_opcode::v_min_f64, bld.def(v2),
1466                                 get_alu_src(ctx, instr->src[0]),
1467                                 as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1468             bld.vop3(aco_opcode::v_mul_f64, Definition(dst), Operand(0x3FF0000000000000lu), tmp);
1469          } else {
1470             bld.vop3(aco_opcode::v_min_f64, Definition(dst),
1471                      get_alu_src(ctx, instr->src[0]),
1472                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1473          }
1474       } else {
1475          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1476          nir_print_instr(&instr->instr, stderr);
1477          fprintf(stderr, "\n");
1478       }
1479       break;
1480    }
1481    case nir_op_fmax3: {
1482       if (dst.size() == 1) {
1483          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_f32, dst, ctx->block->fp_mode.must_flush_denorms32);
1484       } else {
1485          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1486          nir_print_instr(&instr->instr, stderr);
1487          fprintf(stderr, "\n");
1488       }
1489       break;
1490    }
1491    case nir_op_fmin3: {
1492       if (dst.size() == 1) {
1493          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_f32, dst, ctx->block->fp_mode.must_flush_denorms32);
1494       } else {
1495          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1496          nir_print_instr(&instr->instr, stderr);
1497          fprintf(stderr, "\n");
1498       }
1499       break;
1500    }
1501    case nir_op_fmed3: {
1502       if (dst.size() == 1) {
1503          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_f32, dst, ctx->block->fp_mode.must_flush_denorms32);
1504       } else {
1505          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1506          nir_print_instr(&instr->instr, stderr);
1507          fprintf(stderr, "\n");
1508       }
1509       break;
1510    }
1511    case nir_op_umax3: {
1512       if (dst.size() == 1) {
1513          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_u32, dst);
1514       } else {
1515          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1516          nir_print_instr(&instr->instr, stderr);
1517          fprintf(stderr, "\n");
1518       }
1519       break;
1520    }
1521    case nir_op_umin3: {
1522       if (dst.size() == 1) {
1523          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_u32, dst);
1524       } else {
1525          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1526          nir_print_instr(&instr->instr, stderr);
1527          fprintf(stderr, "\n");
1528       }
1529       break;
1530    }
1531    case nir_op_umed3: {
1532       if (dst.size() == 1) {
1533          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_u32, dst);
1534       } else {
1535          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1536          nir_print_instr(&instr->instr, stderr);
1537          fprintf(stderr, "\n");
1538       }
1539       break;
1540    }
1541    case nir_op_imax3: {
1542       if (dst.size() == 1) {
1543          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_i32, dst);
1544       } else {
1545          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1546          nir_print_instr(&instr->instr, stderr);
1547          fprintf(stderr, "\n");
1548       }
1549       break;
1550    }
1551    case nir_op_imin3: {
1552       if (dst.size() == 1) {
1553          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_i32, dst);
1554       } else {
1555          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1556          nir_print_instr(&instr->instr, stderr);
1557          fprintf(stderr, "\n");
1558       }
1559       break;
1560    }
1561    case nir_op_imed3: {
1562       if (dst.size() == 1) {
1563          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_i32, dst);
1564       } else {
1565          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1566          nir_print_instr(&instr->instr, stderr);
1567          fprintf(stderr, "\n");
1568       }
1569       break;
1570    }
1571    case nir_op_cube_face_coord: {
1572       Temp in = get_alu_src(ctx, instr->src[0], 3);
1573       Temp src[3] = { emit_extract_vector(ctx, in, 0, v1),
1574                       emit_extract_vector(ctx, in, 1, v1),
1575                       emit_extract_vector(ctx, in, 2, v1) };
1576       Temp ma = bld.vop3(aco_opcode::v_cubema_f32, bld.def(v1), src[0], src[1], src[2]);
1577       ma = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), ma);
1578       Temp sc = bld.vop3(aco_opcode::v_cubesc_f32, bld.def(v1), src[0], src[1], src[2]);
1579       Temp tc = bld.vop3(aco_opcode::v_cubetc_f32, bld.def(v1), src[0], src[1], src[2]);
1580       sc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), sc, ma, Operand(0x3f000000u/*0.5*/));
1581       tc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), tc, ma, Operand(0x3f000000u/*0.5*/));
1582       bld.pseudo(aco_opcode::p_create_vector, Definition(dst), sc, tc);
1583       break;
1584    }
1585    case nir_op_cube_face_index: {
1586       Temp in = get_alu_src(ctx, instr->src[0], 3);
1587       Temp src[3] = { emit_extract_vector(ctx, in, 0, v1),
1588                       emit_extract_vector(ctx, in, 1, v1),
1589                       emit_extract_vector(ctx, in, 2, v1) };
1590       bld.vop3(aco_opcode::v_cubeid_f32, Definition(dst), src[0], src[1], src[2]);
1591       break;
1592    }
1593    case nir_op_bcsel: {
1594       emit_bcsel(ctx, instr, dst);
1595       break;
1596    }
1597    case nir_op_frsq: {
1598       if (dst.size() == 1) {
1599          emit_rsq(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1600       } else if (dst.size() == 2) {
1601          emit_vop1_instruction(ctx, instr, aco_opcode::v_rsq_f64, dst);
1602       } else {
1603          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1604          nir_print_instr(&instr->instr, stderr);
1605          fprintf(stderr, "\n");
1606       }
1607       break;
1608    }
1609    case nir_op_fneg: {
1610       Temp src = get_alu_src(ctx, instr->src[0]);
1611       if (dst.size() == 1) {
1612          if (ctx->block->fp_mode.must_flush_denorms32)
1613             src = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x3f800000u), as_vgpr(ctx, src));
1614          bld.vop2(aco_opcode::v_xor_b32, Definition(dst), Operand(0x80000000u), as_vgpr(ctx, src));
1615       } else if (dst.size() == 2) {
1616          if (ctx->block->fp_mode.must_flush_denorms16_64)
1617             src = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), Operand(0x3FF0000000000000lu), as_vgpr(ctx, src));
1618          Temp upper = bld.tmp(v1), lower = bld.tmp(v1);
1619          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1620          upper = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), Operand(0x80000000u), upper);
1621          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1622       } else {
1623          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1624          nir_print_instr(&instr->instr, stderr);
1625          fprintf(stderr, "\n");
1626       }
1627       break;
1628    }
1629    case nir_op_fabs: {
1630       Temp src = get_alu_src(ctx, instr->src[0]);
1631       if (dst.size() == 1) {
1632          if (ctx->block->fp_mode.must_flush_denorms32)
1633             src = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x3f800000u), as_vgpr(ctx, src));
1634          bld.vop2(aco_opcode::v_and_b32, Definition(dst), Operand(0x7FFFFFFFu), as_vgpr(ctx, src));
1635       } else if (dst.size() == 2) {
1636          if (ctx->block->fp_mode.must_flush_denorms16_64)
1637             src = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), Operand(0x3FF0000000000000lu), as_vgpr(ctx, src));
1638          Temp upper = bld.tmp(v1), lower = bld.tmp(v1);
1639          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1640          upper = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7FFFFFFFu), upper);
1641          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1642       } else {
1643          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1644          nir_print_instr(&instr->instr, stderr);
1645          fprintf(stderr, "\n");
1646       }
1647       break;
1648    }
1649    case nir_op_fsat: {
1650       Temp src = get_alu_src(ctx, instr->src[0]);
1651       if (dst.size() == 1) {
1652          bld.vop3(aco_opcode::v_med3_f32, Definition(dst), Operand(0u), Operand(0x3f800000u), src);
1653          /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1654          // TODO: confirm that this holds under any circumstances
1655       } else if (dst.size() == 2) {
1656          Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst), src, Operand(0u));
1657          VOP3A_instruction* vop3 = static_cast<VOP3A_instruction*>(add);
1658          vop3->clamp = true;
1659       } else {
1660          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1661          nir_print_instr(&instr->instr, stderr);
1662          fprintf(stderr, "\n");
1663       }
1664       break;
1665    }
1666    case nir_op_flog2: {
1667       if (dst.size() == 1) {
1668          emit_log2(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1669       } else {
1670          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1671          nir_print_instr(&instr->instr, stderr);
1672          fprintf(stderr, "\n");
1673       }
1674       break;
1675    }
1676    case nir_op_frcp: {
1677       if (dst.size() == 1) {
1678          emit_rcp(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1679       } else if (dst.size() == 2) {
1680          emit_vop1_instruction(ctx, instr, aco_opcode::v_rcp_f64, dst);
1681       } else {
1682          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1683          nir_print_instr(&instr->instr, stderr);
1684          fprintf(stderr, "\n");
1685       }
1686       break;
1687    }
1688    case nir_op_fexp2: {
1689       if (dst.size() == 1) {
1690          emit_vop1_instruction(ctx, instr, aco_opcode::v_exp_f32, dst);
1691       } else {
1692          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1693          nir_print_instr(&instr->instr, stderr);
1694          fprintf(stderr, "\n");
1695       }
1696       break;
1697    }
1698    case nir_op_fsqrt: {
1699       if (dst.size() == 1) {
1700          emit_sqrt(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1701       } else if (dst.size() == 2) {
1702          emit_vop1_instruction(ctx, instr, aco_opcode::v_sqrt_f64, dst);
1703       } else {
1704          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1705          nir_print_instr(&instr->instr, stderr);
1706          fprintf(stderr, "\n");
1707       }
1708       break;
1709    }
1710    case nir_op_ffract: {
1711       if (dst.size() == 1) {
1712          emit_vop1_instruction(ctx, instr, aco_opcode::v_fract_f32, dst);
1713       } else if (dst.size() == 2) {
1714          emit_vop1_instruction(ctx, instr, aco_opcode::v_fract_f64, dst);
1715       } else {
1716          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1717          nir_print_instr(&instr->instr, stderr);
1718          fprintf(stderr, "\n");
1719       }
1720       break;
1721    }
1722    case nir_op_ffloor: {
1723       if (dst.size() == 1) {
1724          emit_vop1_instruction(ctx, instr, aco_opcode::v_floor_f32, dst);
1725       } else if (dst.size() == 2) {
1726          emit_floor_f64(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1727       } else {
1728          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1729          nir_print_instr(&instr->instr, stderr);
1730          fprintf(stderr, "\n");
1731       }
1732       break;
1733    }
1734    case nir_op_fceil: {
1735       if (dst.size() == 1) {
1736          emit_vop1_instruction(ctx, instr, aco_opcode::v_ceil_f32, dst);
1737       } else if (dst.size() == 2) {
1738          if (ctx->options->chip_class >= GFX7) {
1739             emit_vop1_instruction(ctx, instr, aco_opcode::v_ceil_f64, dst);
1740          } else {
1741             /* GFX6 doesn't support V_CEIL_F64, lower it. */
1742             Temp src0 = get_alu_src(ctx, instr->src[0]);
1743
1744             /* trunc = trunc(src0)
1745              * if (src0 > 0.0 && src0 != trunc)
1746              *    trunc += 1.0
1747              */
1748             Temp trunc = emit_trunc_f64(ctx, bld, bld.def(v2), src0);
1749             Temp tmp0 = bld.vopc_e64(aco_opcode::v_cmp_gt_f64, bld.def(bld.lm), src0, Operand(0u));
1750             Temp tmp1 = bld.vopc(aco_opcode::v_cmp_lg_f64, bld.hint_vcc(bld.def(bld.lm)), src0, trunc);
1751             Temp cond = bld.sop2(aco_opcode::s_and_b64, bld.hint_vcc(bld.def(s2)), bld.def(s1, scc), tmp0, tmp1);
1752             Temp add = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), bld.copy(bld.def(v1), Operand(0u)), bld.copy(bld.def(v1), Operand(0x3ff00000u)), cond);
1753             add = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), bld.copy(bld.def(v1), Operand(0u)), add);
1754             bld.vop3(aco_opcode::v_add_f64, Definition(dst), trunc, add);
1755          }
1756       } else {
1757          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1758          nir_print_instr(&instr->instr, stderr);
1759          fprintf(stderr, "\n");
1760       }
1761       break;
1762    }
1763    case nir_op_ftrunc: {
1764       if (dst.size() == 1) {
1765          emit_vop1_instruction(ctx, instr, aco_opcode::v_trunc_f32, dst);
1766       } else if (dst.size() == 2) {
1767          emit_trunc_f64(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1768       } else {
1769          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1770          nir_print_instr(&instr->instr, stderr);
1771          fprintf(stderr, "\n");
1772       }
1773       break;
1774    }
1775    case nir_op_fround_even: {
1776       if (dst.size() == 1) {
1777          emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f32, dst);
1778       } else if (dst.size() == 2) {
1779          if (ctx->options->chip_class >= GFX7) {
1780             emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f64, dst);
1781          } else {
1782             /* GFX6 doesn't support V_RNDNE_F64, lower it. */
1783             Temp src0 = get_alu_src(ctx, instr->src[0]);
1784
1785             Temp src0_lo = bld.tmp(v1), src0_hi = bld.tmp(v1);
1786             bld.pseudo(aco_opcode::p_split_vector, Definition(src0_lo), Definition(src0_hi), src0);
1787
1788             Temp bitmask = bld.sop1(aco_opcode::s_brev_b32, bld.def(s1), bld.copy(bld.def(s1), Operand(-2u)));
1789             Temp bfi = bld.vop3(aco_opcode::v_bfi_b32, bld.def(v1), bitmask, bld.copy(bld.def(v1), Operand(0x43300000u)), as_vgpr(ctx, src0_hi));
1790             Temp tmp = bld.vop3(aco_opcode::v_add_f64, bld.def(v2), src0, bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), bfi));
1791             Instruction *sub = bld.vop3(aco_opcode::v_add_f64, bld.def(v2), tmp, bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), bfi));
1792             static_cast<VOP3A_instruction*>(sub)->neg[1] = true;
1793             tmp = sub->definitions[0].getTemp();
1794
1795             Temp v = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(-1u), Operand(0x432fffffu));
1796             Instruction* vop3 = bld.vopc_e64(aco_opcode::v_cmp_gt_f64, bld.hint_vcc(bld.def(bld.lm)), src0, v);
1797             static_cast<VOP3A_instruction*>(vop3)->abs[0] = true;
1798             Temp cond = vop3->definitions[0].getTemp();
1799
1800             Temp tmp_lo = bld.tmp(v1), tmp_hi = bld.tmp(v1);
1801             bld.pseudo(aco_opcode::p_split_vector, Definition(tmp_lo), Definition(tmp_hi), tmp);
1802             Temp dst0 = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), tmp_lo, as_vgpr(ctx, src0_lo), cond);
1803             Temp dst1 = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), tmp_hi, as_vgpr(ctx, src0_hi), cond);
1804
1805             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1806          }
1807       } else {
1808          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1809          nir_print_instr(&instr->instr, stderr);
1810          fprintf(stderr, "\n");
1811       }
1812       break;
1813    }
1814    case nir_op_fsin:
1815    case nir_op_fcos: {
1816       Temp src = get_alu_src(ctx, instr->src[0]);
1817       aco_ptr<Instruction> norm;
1818       if (dst.size() == 1) {
1819          Temp half_pi = bld.copy(bld.def(s1), Operand(0x3e22f983u));
1820          Temp tmp = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), half_pi, as_vgpr(ctx, src));
1821
1822          /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
1823          if (ctx->options->chip_class < GFX9)
1824             tmp = bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), tmp);
1825
1826          aco_opcode opcode = instr->op == nir_op_fsin ? aco_opcode::v_sin_f32 : aco_opcode::v_cos_f32;
1827          bld.vop1(opcode, Definition(dst), tmp);
1828       } else {
1829          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1830          nir_print_instr(&instr->instr, stderr);
1831          fprintf(stderr, "\n");
1832       }
1833       break;
1834    }
1835    case nir_op_ldexp: {
1836       if (dst.size() == 1) {
1837          bld.vop3(aco_opcode::v_ldexp_f32, Definition(dst),
1838                   as_vgpr(ctx, get_alu_src(ctx, instr->src[0])),
1839                   get_alu_src(ctx, instr->src[1]));
1840       } else if (dst.size() == 2) {
1841          bld.vop3(aco_opcode::v_ldexp_f64, Definition(dst),
1842                   as_vgpr(ctx, get_alu_src(ctx, instr->src[0])),
1843                   get_alu_src(ctx, instr->src[1]));
1844       } else {
1845          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1846          nir_print_instr(&instr->instr, stderr);
1847          fprintf(stderr, "\n");
1848       }
1849       break;
1850    }
1851    case nir_op_frexp_sig: {
1852       if (dst.size() == 1) {
1853          bld.vop1(aco_opcode::v_frexp_mant_f32, Definition(dst),
1854                   get_alu_src(ctx, instr->src[0]));
1855       } else if (dst.size() == 2) {
1856          bld.vop1(aco_opcode::v_frexp_mant_f64, Definition(dst),
1857                   get_alu_src(ctx, instr->src[0]));
1858       } else {
1859          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1860          nir_print_instr(&instr->instr, stderr);
1861          fprintf(stderr, "\n");
1862       }
1863       break;
1864    }
1865    case nir_op_frexp_exp: {
1866       if (instr->src[0].src.ssa->bit_size == 32) {
1867          bld.vop1(aco_opcode::v_frexp_exp_i32_f32, Definition(dst),
1868                   get_alu_src(ctx, instr->src[0]));
1869       } else if (instr->src[0].src.ssa->bit_size == 64) {
1870          bld.vop1(aco_opcode::v_frexp_exp_i32_f64, Definition(dst),
1871                   get_alu_src(ctx, instr->src[0]));
1872       } else {
1873          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1874          nir_print_instr(&instr->instr, stderr);
1875          fprintf(stderr, "\n");
1876       }
1877       break;
1878    }
1879    case nir_op_fsign: {
1880       Temp src = as_vgpr(ctx, get_alu_src(ctx, instr->src[0]));
1881       if (dst.size() == 1) {
1882          Temp cond = bld.vopc(aco_opcode::v_cmp_nlt_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1883          src = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0x3f800000u), src, cond);
1884          cond = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1885          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0xbf800000u), src, cond);
1886       } else if (dst.size() == 2) {
1887          Temp cond = bld.vopc(aco_opcode::v_cmp_nlt_f64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1888          Temp tmp = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0x3FF00000u));
1889          Temp upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), tmp, emit_extract_vector(ctx, src, 1, v1), cond);
1890
1891          cond = bld.vopc(aco_opcode::v_cmp_le_f64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1892          tmp = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0xBFF00000u));
1893          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), tmp, upper, cond);
1894
1895          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), Operand(0u), upper);
1896       } else {
1897          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1898          nir_print_instr(&instr->instr, stderr);
1899          fprintf(stderr, "\n");
1900       }
1901       break;
1902    }
1903    case nir_op_f2f32: {
1904       if (instr->src[0].src.ssa->bit_size == 64) {
1905          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_f64, dst);
1906       } else {
1907          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1908          nir_print_instr(&instr->instr, stderr);
1909          fprintf(stderr, "\n");
1910       }
1911       break;
1912    }
1913    case nir_op_f2f64: {
1914       if (instr->src[0].src.ssa->bit_size == 32) {
1915          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_f32, dst);
1916       } else {
1917          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1918          nir_print_instr(&instr->instr, stderr);
1919          fprintf(stderr, "\n");
1920       }
1921       break;
1922    }
1923    case nir_op_i2f32: {
1924       assert(dst.size() == 1);
1925       emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_i32, dst);
1926       break;
1927    }
1928    case nir_op_i2f64: {
1929       if (instr->src[0].src.ssa->bit_size == 32) {
1930          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_i32, dst);
1931       } else if (instr->src[0].src.ssa->bit_size == 64) {
1932          Temp src = get_alu_src(ctx, instr->src[0]);
1933          RegClass rc = RegClass(src.type(), 1);
1934          Temp lower = bld.tmp(rc), upper = bld.tmp(rc);
1935          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1936          lower = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), lower);
1937          upper = bld.vop1(aco_opcode::v_cvt_f64_i32, bld.def(v2), upper);
1938          upper = bld.vop3(aco_opcode::v_ldexp_f64, bld.def(v2), upper, Operand(32u));
1939          bld.vop3(aco_opcode::v_add_f64, Definition(dst), lower, upper);
1940
1941       } else {
1942          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1943          nir_print_instr(&instr->instr, stderr);
1944          fprintf(stderr, "\n");
1945       }
1946       break;
1947    }
1948    case nir_op_u2f32: {
1949       assert(dst.size() == 1);
1950       emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_u32, dst);
1951       break;
1952    }
1953    case nir_op_u2f64: {
1954       if (instr->src[0].src.ssa->bit_size == 32) {
1955          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_u32, dst);
1956       } else if (instr->src[0].src.ssa->bit_size == 64) {
1957          Temp src = get_alu_src(ctx, instr->src[0]);
1958          RegClass rc = RegClass(src.type(), 1);
1959          Temp lower = bld.tmp(rc), upper = bld.tmp(rc);
1960          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1961          lower = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), lower);
1962          upper = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), upper);
1963          upper = bld.vop3(aco_opcode::v_ldexp_f64, bld.def(v2), upper, Operand(32u));
1964          bld.vop3(aco_opcode::v_add_f64, Definition(dst), lower, upper);
1965       } else {
1966          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1967          nir_print_instr(&instr->instr, stderr);
1968          fprintf(stderr, "\n");
1969       }
1970       break;
1971    }
1972    case nir_op_f2i32: {
1973       Temp src = get_alu_src(ctx, instr->src[0]);
1974       if (instr->src[0].src.ssa->bit_size == 32) {
1975          if (dst.type() == RegType::vgpr)
1976             bld.vop1(aco_opcode::v_cvt_i32_f32, Definition(dst), src);
1977          else
1978             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1979                        bld.vop1(aco_opcode::v_cvt_i32_f32, bld.def(v1), src));
1980
1981       } else if (instr->src[0].src.ssa->bit_size == 64) {
1982          if (dst.type() == RegType::vgpr)
1983             bld.vop1(aco_opcode::v_cvt_i32_f64, Definition(dst), src);
1984          else
1985             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1986                        bld.vop1(aco_opcode::v_cvt_i32_f64, bld.def(v1), src));
1987
1988       } else {
1989          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1990          nir_print_instr(&instr->instr, stderr);
1991          fprintf(stderr, "\n");
1992       }
1993       break;
1994    }
1995    case nir_op_f2u32: {
1996       Temp src = get_alu_src(ctx, instr->src[0]);
1997       if (instr->src[0].src.ssa->bit_size == 32) {
1998          if (dst.type() == RegType::vgpr)
1999             bld.vop1(aco_opcode::v_cvt_u32_f32, Definition(dst), src);
2000          else
2001             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
2002                        bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), src));
2003
2004       } else if (instr->src[0].src.ssa->bit_size == 64) {
2005          if (dst.type() == RegType::vgpr)
2006             bld.vop1(aco_opcode::v_cvt_u32_f64, Definition(dst), src);
2007          else
2008             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
2009                        bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), src));
2010
2011       } else {
2012          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2013          nir_print_instr(&instr->instr, stderr);
2014          fprintf(stderr, "\n");
2015       }
2016       break;
2017    }
2018    case nir_op_f2i64: {
2019       Temp src = get_alu_src(ctx, instr->src[0]);
2020       if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::vgpr) {
2021          Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f32, bld.def(v1), src);
2022          exponent = bld.vop3(aco_opcode::v_med3_i32, bld.def(v1), Operand(0x0u), exponent, Operand(64u));
2023          Temp mantissa = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffu), src);
2024          Temp sign = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
2025          mantissa = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(0x800000u), mantissa);
2026          mantissa = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(7u), mantissa);
2027          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), mantissa);
2028          Temp new_exponent = bld.tmp(v1);
2029          Temp borrow = bld.vsub32(Definition(new_exponent), Operand(63u), exponent, true).def(1).getTemp();
2030          if (ctx->program->chip_class >= GFX8)
2031             mantissa = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), new_exponent, mantissa);
2032          else
2033             mantissa = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), mantissa, new_exponent);
2034          Temp saturate = bld.vop1(aco_opcode::v_bfrev_b32, bld.def(v1), Operand(0xfffffffeu));
2035          Temp lower = bld.tmp(v1), upper = bld.tmp(v1);
2036          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2037          lower = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), lower, Operand(0xffffffffu), borrow);
2038          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), upper, saturate, borrow);
2039          lower = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), sign, lower);
2040          upper = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), sign, upper);
2041          Temp new_lower = bld.tmp(v1);
2042          borrow = bld.vsub32(Definition(new_lower), lower, sign, true).def(1).getTemp();
2043          Temp new_upper = bld.vsub32(bld.def(v1), upper, sign, false, borrow);
2044          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), new_lower, new_upper);
2045
2046       } else if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::sgpr) {
2047          if (src.type() == RegType::vgpr)
2048             src = bld.as_uniform(src);
2049          Temp exponent = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), src, Operand(0x80017u));
2050          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(126u));
2051          exponent = bld.sop2(aco_opcode::s_max_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), exponent);
2052          exponent = bld.sop2(aco_opcode::s_min_u32, bld.def(s1), bld.def(s1, scc), Operand(64u), exponent);
2053          Temp mantissa = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0x7fffffu), src);
2054          Temp sign = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
2055          mantissa = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(0x800000u), mantissa);
2056          mantissa = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), mantissa, Operand(7u));
2057          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), mantissa);
2058          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), Operand(63u), exponent);
2059          mantissa = bld.sop2(aco_opcode::s_lshr_b64, bld.def(s2), bld.def(s1, scc), mantissa, exponent);
2060          Temp cond = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), exponent, Operand(0xffffffffu)); // exp >= 64
2061          Temp saturate = bld.sop1(aco_opcode::s_brev_b64, bld.def(s2), Operand(0xfffffffeu));
2062          mantissa = bld.sop2(aco_opcode::s_cselect_b64, bld.def(s2), saturate, mantissa, cond);
2063          Temp lower = bld.tmp(s1), upper = bld.tmp(s1);
2064          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2065          lower = bld.sop2(aco_opcode::s_xor_b32, bld.def(s1), bld.def(s1, scc), sign, lower);
2066          upper = bld.sop2(aco_opcode::s_xor_b32, bld.def(s1), bld.def(s1, scc), sign, upper);
2067          Temp borrow = bld.tmp(s1);
2068          lower = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(borrow)), lower, sign);
2069          upper = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), upper, sign, borrow);
2070          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2071
2072       } else if (instr->src[0].src.ssa->bit_size == 64) {
2073          Temp vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0x3df00000u));
2074          Temp trunc = emit_trunc_f64(ctx, bld, bld.def(v2), src);
2075          Temp mul = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), trunc, vec);
2076          vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0xc1f00000u));
2077          Temp floor = emit_floor_f64(ctx, bld, bld.def(v2), mul);
2078          Temp fma = bld.vop3(aco_opcode::v_fma_f64, bld.def(v2), floor, vec, trunc);
2079          Temp lower = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), fma);
2080          Temp upper = bld.vop1(aco_opcode::v_cvt_i32_f64, bld.def(v1), floor);
2081          if (dst.type() == RegType::sgpr) {
2082             lower = bld.as_uniform(lower);
2083             upper = bld.as_uniform(upper);
2084          }
2085          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2086
2087       } else {
2088          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2089          nir_print_instr(&instr->instr, stderr);
2090          fprintf(stderr, "\n");
2091       }
2092       break;
2093    }
2094    case nir_op_f2u64: {
2095       Temp src = get_alu_src(ctx, instr->src[0]);
2096       if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::vgpr) {
2097          Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f32, bld.def(v1), src);
2098          Temp exponent_in_range = bld.vopc(aco_opcode::v_cmp_ge_i32, bld.hint_vcc(bld.def(bld.lm)), Operand(64u), exponent);
2099          exponent = bld.vop2(aco_opcode::v_max_i32, bld.def(v1), Operand(0x0u), exponent);
2100          Temp mantissa = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffu), src);
2101          mantissa = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(0x800000u), mantissa);
2102          Temp exponent_small = bld.vsub32(bld.def(v1), Operand(24u), exponent);
2103          Temp small = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), exponent_small, mantissa);
2104          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), mantissa);
2105          Temp new_exponent = bld.tmp(v1);
2106          Temp cond_small = bld.vsub32(Definition(new_exponent), exponent, Operand(24u), true).def(1).getTemp();
2107          if (ctx->program->chip_class >= GFX8)
2108             mantissa = bld.vop3(aco_opcode::v_lshlrev_b64, bld.def(v2), new_exponent, mantissa);
2109          else
2110             mantissa = bld.vop3(aco_opcode::v_lshl_b64, bld.def(v2), mantissa, new_exponent);
2111          Temp lower = bld.tmp(v1), upper = bld.tmp(v1);
2112          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2113          lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), lower, small, cond_small);
2114          upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), upper, Operand(0u), cond_small);
2115          lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xffffffffu), lower, exponent_in_range);
2116          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xffffffffu), upper, exponent_in_range);
2117          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2118
2119       } else if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::sgpr) {
2120          if (src.type() == RegType::vgpr)
2121             src = bld.as_uniform(src);
2122          Temp exponent = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), src, Operand(0x80017u));
2123          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(126u));
2124          exponent = bld.sop2(aco_opcode::s_max_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), exponent);
2125          Temp mantissa = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0x7fffffu), src);
2126          mantissa = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(0x800000u), mantissa);
2127          Temp exponent_small = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), Operand(24u), exponent);
2128          Temp small = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), mantissa, exponent_small);
2129          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), mantissa);
2130          Temp exponent_large = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(24u));
2131          mantissa = bld.sop2(aco_opcode::s_lshl_b64, bld.def(s2), bld.def(s1, scc), mantissa, exponent_large);
2132          Temp cond = bld.sopc(aco_opcode::s_cmp_ge_i32, bld.def(s1, scc), Operand(64u), exponent);
2133          mantissa = bld.sop2(aco_opcode::s_cselect_b64, bld.def(s2), mantissa, Operand(0xffffffffu), cond);
2134          Temp lower = bld.tmp(s1), upper = bld.tmp(s1);
2135          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2136          Temp cond_small = bld.sopc(aco_opcode::s_cmp_le_i32, bld.def(s1, scc), exponent, Operand(24u));
2137          lower = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), small, lower, cond_small);
2138          upper = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), Operand(0u), upper, cond_small);
2139          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2140
2141       } else if (instr->src[0].src.ssa->bit_size == 64) {
2142          Temp vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0x3df00000u));
2143          Temp trunc = emit_trunc_f64(ctx, bld, bld.def(v2), src);
2144          Temp mul = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), trunc, vec);
2145          vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0xc1f00000u));
2146          Temp floor = emit_floor_f64(ctx, bld, bld.def(v2), mul);
2147          Temp fma = bld.vop3(aco_opcode::v_fma_f64, bld.def(v2), floor, vec, trunc);
2148          Temp lower = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), fma);
2149          Temp upper = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), floor);
2150          if (dst.type() == RegType::sgpr) {
2151             lower = bld.as_uniform(lower);
2152             upper = bld.as_uniform(upper);
2153          }
2154          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2155
2156       } else {
2157          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2158          nir_print_instr(&instr->instr, stderr);
2159          fprintf(stderr, "\n");
2160       }
2161       break;
2162    }
2163    case nir_op_b2f32: {
2164       Temp src = get_alu_src(ctx, instr->src[0]);
2165       assert(src.regClass() == bld.lm);
2166
2167       if (dst.regClass() == s1) {
2168          src = bool_to_scalar_condition(ctx, src);
2169          bld.sop2(aco_opcode::s_mul_i32, Definition(dst), Operand(0x3f800000u), src);
2170       } else if (dst.regClass() == v1) {
2171          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(0x3f800000u), src);
2172       } else {
2173          unreachable("Wrong destination register class for nir_op_b2f32.");
2174       }
2175       break;
2176    }
2177    case nir_op_b2f64: {
2178       Temp src = get_alu_src(ctx, instr->src[0]);
2179       assert(src.regClass() == bld.lm);
2180
2181       if (dst.regClass() == s2) {
2182          src = bool_to_scalar_condition(ctx, src);
2183          bld.sop2(aco_opcode::s_cselect_b64, Definition(dst), Operand(0x3f800000u), Operand(0u), bld.scc(src));
2184       } else if (dst.regClass() == v2) {
2185          Temp one = bld.vop1(aco_opcode::v_mov_b32, bld.def(v2), Operand(0x3FF00000u));
2186          Temp upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), one, src);
2187          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), Operand(0u), upper);
2188       } else {
2189          unreachable("Wrong destination register class for nir_op_b2f64.");
2190       }
2191       break;
2192    }
2193    case nir_op_i2i32: {
2194       Temp src = get_alu_src(ctx, instr->src[0]);
2195       if (instr->src[0].src.ssa->bit_size == 64) {
2196          /* we can actually just say dst = src, as it would map the lower register */
2197          emit_extract_vector(ctx, src, 0, dst);
2198       } else {
2199          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2200          nir_print_instr(&instr->instr, stderr);
2201          fprintf(stderr, "\n");
2202       }
2203       break;
2204    }
2205    case nir_op_u2u32: {
2206       Temp src = get_alu_src(ctx, instr->src[0]);
2207       if (instr->src[0].src.ssa->bit_size == 16) {
2208          if (dst.regClass() == s1) {
2209             bld.sop2(aco_opcode::s_and_b32, Definition(dst), bld.def(s1, scc), Operand(0xFFFFu), src);
2210          } else {
2211             // TODO: do better with SDWA
2212             bld.vop2(aco_opcode::v_and_b32, Definition(dst), Operand(0xFFFFu), src);
2213          }
2214       } else if (instr->src[0].src.ssa->bit_size == 64) {
2215          /* we can actually just say dst = src, as it would map the lower register */
2216          emit_extract_vector(ctx, src, 0, dst);
2217       } else {
2218          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2219          nir_print_instr(&instr->instr, stderr);
2220          fprintf(stderr, "\n");
2221       }
2222       break;
2223    }
2224    case nir_op_i2i64: {
2225       Temp src = get_alu_src(ctx, instr->src[0]);
2226       if (src.regClass() == s1) {
2227          Temp high = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
2228          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, high);
2229       } else if (src.regClass() == v1) {
2230          Temp high = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
2231          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, high);
2232       } else {
2233          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2234          nir_print_instr(&instr->instr, stderr);
2235          fprintf(stderr, "\n");
2236       }
2237       break;
2238    }
2239    case nir_op_u2u64: {
2240       Temp src = get_alu_src(ctx, instr->src[0]);
2241       if (instr->src[0].src.ssa->bit_size == 32) {
2242          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, Operand(0u));
2243       } else {
2244          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2245          nir_print_instr(&instr->instr, stderr);
2246          fprintf(stderr, "\n");
2247       }
2248       break;
2249    }
2250    case nir_op_b2i32: {
2251       Temp src = get_alu_src(ctx, instr->src[0]);
2252       assert(src.regClass() == bld.lm);
2253
2254       if (dst.regClass() == s1) {
2255          // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2256          bool_to_scalar_condition(ctx, src, dst);
2257       } else if (dst.regClass() == v1) {
2258          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), src);
2259       } else {
2260          unreachable("Invalid register class for b2i32");
2261       }
2262       break;
2263    }
2264    case nir_op_i2b1: {
2265       Temp src = get_alu_src(ctx, instr->src[0]);
2266       assert(dst.regClass() == bld.lm);
2267
2268       if (src.type() == RegType::vgpr) {
2269          assert(src.regClass() == v1 || src.regClass() == v2);
2270          assert(dst.regClass() == bld.lm);
2271          bld.vopc(src.size() == 2 ? aco_opcode::v_cmp_lg_u64 : aco_opcode::v_cmp_lg_u32,
2272                   Definition(dst), Operand(0u), src).def(0).setHint(vcc);
2273       } else {
2274          assert(src.regClass() == s1 || src.regClass() == s2);
2275          Temp tmp;
2276          if (src.regClass() == s2 && ctx->program->chip_class <= GFX7) {
2277             tmp = bld.sop2(aco_opcode::s_or_b64, bld.def(s2), bld.def(s1, scc), Operand(0u), src).def(1).getTemp();
2278          } else {
2279             tmp = bld.sopc(src.size() == 2 ? aco_opcode::s_cmp_lg_u64 : aco_opcode::s_cmp_lg_u32,
2280                            bld.scc(bld.def(s1)), Operand(0u), src);
2281          }
2282          bool_to_vector_condition(ctx, tmp, dst);
2283       }
2284       break;
2285    }
2286    case nir_op_pack_64_2x32_split: {
2287       Temp src0 = get_alu_src(ctx, instr->src[0]);
2288       Temp src1 = get_alu_src(ctx, instr->src[1]);
2289
2290       bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src0, src1);
2291       break;
2292    }
2293    case nir_op_unpack_64_2x32_split_x:
2294       bld.pseudo(aco_opcode::p_split_vector, Definition(dst), bld.def(dst.regClass()), get_alu_src(ctx, instr->src[0]));
2295       break;
2296    case nir_op_unpack_64_2x32_split_y:
2297       bld.pseudo(aco_opcode::p_split_vector, bld.def(dst.regClass()), Definition(dst), get_alu_src(ctx, instr->src[0]));
2298       break;
2299    case nir_op_pack_half_2x16: {
2300       Temp src = get_alu_src(ctx, instr->src[0], 2);
2301
2302       if (dst.regClass() == v1) {
2303          Temp src0 = bld.tmp(v1);
2304          Temp src1 = bld.tmp(v1);
2305          bld.pseudo(aco_opcode::p_split_vector, Definition(src0), Definition(src1), src);
2306          if (!ctx->block->fp_mode.care_about_round32 || ctx->block->fp_mode.round32 == fp_round_tz)
2307             bld.vop3(aco_opcode::v_cvt_pkrtz_f16_f32, Definition(dst), src0, src1);
2308          else
2309             bld.vop3(aco_opcode::v_cvt_pk_u16_u32, Definition(dst),
2310                      bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src0),
2311                      bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src1));
2312       } else {
2313          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2314          nir_print_instr(&instr->instr, stderr);
2315          fprintf(stderr, "\n");
2316       }
2317       break;
2318    }
2319    case nir_op_unpack_half_2x16_split_x: {
2320       if (dst.regClass() == v1) {
2321          Builder bld(ctx->program, ctx->block);
2322          bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst), get_alu_src(ctx, instr->src[0]));
2323       } else {
2324          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2325          nir_print_instr(&instr->instr, stderr);
2326          fprintf(stderr, "\n");
2327       }
2328       break;
2329    }
2330    case nir_op_unpack_half_2x16_split_y: {
2331       if (dst.regClass() == v1) {
2332          Builder bld(ctx->program, ctx->block);
2333          /* TODO: use SDWA here */
2334          bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst),
2335                   bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(16u), as_vgpr(ctx, get_alu_src(ctx, instr->src[0]))));
2336       } else {
2337          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2338          nir_print_instr(&instr->instr, stderr);
2339          fprintf(stderr, "\n");
2340       }
2341       break;
2342    }
2343    case nir_op_fquantize2f16: {
2344       Temp src = get_alu_src(ctx, instr->src[0]);
2345       Temp f16 = bld.vop1(aco_opcode::v_cvt_f16_f32, bld.def(v1), src);
2346       Temp f32, cmp_res;
2347
2348       if (ctx->program->chip_class >= GFX8) {
2349          Temp mask = bld.copy(bld.def(s1), Operand(0x36Fu)); /* value is NOT negative/positive denormal value */
2350          cmp_res = bld.vopc_e64(aco_opcode::v_cmp_class_f16, bld.hint_vcc(bld.def(bld.lm)), f16, mask);
2351          f32 = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), f16);
2352       } else {
2353          /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2354           * so compare the result and flush to 0 if it's smaller.
2355           */
2356          f32 = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), f16);
2357          Temp smallest = bld.copy(bld.def(s1), Operand(0x38800000u));
2358          Instruction* vop3 = bld.vopc_e64(aco_opcode::v_cmp_nlt_f32, bld.hint_vcc(bld.def(bld.lm)), f32, smallest);
2359          static_cast<VOP3A_instruction*>(vop3)->abs[0] = true;
2360          cmp_res = vop3->definitions[0].getTemp();
2361       }
2362
2363       if (ctx->block->fp_mode.preserve_signed_zero_inf_nan32 || ctx->program->chip_class < GFX8) {
2364          Temp copysign_0 = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0u), as_vgpr(ctx, src));
2365          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), copysign_0, f32, cmp_res);
2366       } else {
2367          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), f32, cmp_res);
2368       }
2369       break;
2370    }
2371    case nir_op_bfm: {
2372       Temp bits = get_alu_src(ctx, instr->src[0]);
2373       Temp offset = get_alu_src(ctx, instr->src[1]);
2374
2375       if (dst.regClass() == s1) {
2376          bld.sop2(aco_opcode::s_bfm_b32, Definition(dst), bits, offset);
2377       } else if (dst.regClass() == v1) {
2378          bld.vop3(aco_opcode::v_bfm_b32, Definition(dst), bits, offset);
2379       } else {
2380          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2381          nir_print_instr(&instr->instr, stderr);
2382          fprintf(stderr, "\n");
2383       }
2384       break;
2385    }
2386    case nir_op_bitfield_select: {
2387       /* (mask & insert) | (~mask & base) */
2388       Temp bitmask = get_alu_src(ctx, instr->src[0]);
2389       Temp insert = get_alu_src(ctx, instr->src[1]);
2390       Temp base = get_alu_src(ctx, instr->src[2]);
2391
2392       /* dst = (insert & bitmask) | (base & ~bitmask) */
2393       if (dst.regClass() == s1) {
2394          aco_ptr<Instruction> sop2;
2395          nir_const_value* const_bitmask = nir_src_as_const_value(instr->src[0].src);
2396          nir_const_value* const_insert = nir_src_as_const_value(instr->src[1].src);
2397          Operand lhs;
2398          if (const_insert && const_bitmask) {
2399             lhs = Operand(const_insert->u32 & const_bitmask->u32);
2400          } else {
2401             insert = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), insert, bitmask);
2402             lhs = Operand(insert);
2403          }
2404
2405          Operand rhs;
2406          nir_const_value* const_base = nir_src_as_const_value(instr->src[2].src);
2407          if (const_base && const_bitmask) {
2408             rhs = Operand(const_base->u32 & ~const_bitmask->u32);
2409          } else {
2410             base = bld.sop2(aco_opcode::s_andn2_b32, bld.def(s1), bld.def(s1, scc), base, bitmask);
2411             rhs = Operand(base);
2412          }
2413
2414          bld.sop2(aco_opcode::s_or_b32, Definition(dst), bld.def(s1, scc), rhs, lhs);
2415
2416       } else if (dst.regClass() == v1) {
2417          if (base.type() == RegType::sgpr && (bitmask.type() == RegType::sgpr || (insert.type() == RegType::sgpr)))
2418             base = as_vgpr(ctx, base);
2419          if (insert.type() == RegType::sgpr && bitmask.type() == RegType::sgpr)
2420             insert = as_vgpr(ctx, insert);
2421
2422          bld.vop3(aco_opcode::v_bfi_b32, Definition(dst), bitmask, insert, base);
2423
2424       } else {
2425          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2426          nir_print_instr(&instr->instr, stderr);
2427          fprintf(stderr, "\n");
2428       }
2429       break;
2430    }
2431    case nir_op_ubfe:
2432    case nir_op_ibfe: {
2433       Temp base = get_alu_src(ctx, instr->src[0]);
2434       Temp offset = get_alu_src(ctx, instr->src[1]);
2435       Temp bits = get_alu_src(ctx, instr->src[2]);
2436
2437       if (dst.type() == RegType::sgpr) {
2438          Operand extract;
2439          nir_const_value* const_offset = nir_src_as_const_value(instr->src[1].src);
2440          nir_const_value* const_bits = nir_src_as_const_value(instr->src[2].src);
2441          if (const_offset && const_bits) {
2442             uint32_t const_extract = (const_bits->u32 << 16) | const_offset->u32;
2443             extract = Operand(const_extract);
2444          } else {
2445             Operand width;
2446             if (const_bits) {
2447                width = Operand(const_bits->u32 << 16);
2448             } else {
2449                width = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), bits, Operand(16u));
2450             }
2451             extract = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), offset, width);
2452          }
2453
2454          aco_opcode opcode;
2455          if (dst.regClass() == s1) {
2456             if (instr->op == nir_op_ubfe)
2457                opcode = aco_opcode::s_bfe_u32;
2458             else
2459                opcode = aco_opcode::s_bfe_i32;
2460          } else if (dst.regClass() == s2) {
2461             if (instr->op == nir_op_ubfe)
2462                opcode = aco_opcode::s_bfe_u64;
2463             else
2464                opcode = aco_opcode::s_bfe_i64;
2465          } else {
2466             unreachable("Unsupported BFE bit size");
2467          }
2468
2469          bld.sop2(opcode, Definition(dst), bld.def(s1, scc), base, extract);
2470
2471       } else {
2472          aco_opcode opcode;
2473          if (dst.regClass() == v1) {
2474             if (instr->op == nir_op_ubfe)
2475                opcode = aco_opcode::v_bfe_u32;
2476             else
2477                opcode = aco_opcode::v_bfe_i32;
2478          } else {
2479             unreachable("Unsupported BFE bit size");
2480          }
2481
2482          emit_vop3a_instruction(ctx, instr, opcode, dst);
2483       }
2484       break;
2485    }
2486    case nir_op_bit_count: {
2487       Temp src = get_alu_src(ctx, instr->src[0]);
2488       if (src.regClass() == s1) {
2489          bld.sop1(aco_opcode::s_bcnt1_i32_b32, Definition(dst), bld.def(s1, scc), src);
2490       } else if (src.regClass() == v1) {
2491          bld.vop3(aco_opcode::v_bcnt_u32_b32, Definition(dst), src, Operand(0u));
2492       } else if (src.regClass() == v2) {
2493          bld.vop3(aco_opcode::v_bcnt_u32_b32, Definition(dst),
2494                   emit_extract_vector(ctx, src, 1, v1),
2495                   bld.vop3(aco_opcode::v_bcnt_u32_b32, bld.def(v1),
2496                            emit_extract_vector(ctx, src, 0, v1), Operand(0u)));
2497       } else if (src.regClass() == s2) {
2498          bld.sop1(aco_opcode::s_bcnt1_i32_b64, Definition(dst), bld.def(s1, scc), src);
2499       } else {
2500          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2501          nir_print_instr(&instr->instr, stderr);
2502          fprintf(stderr, "\n");
2503       }
2504       break;
2505    }
2506    case nir_op_flt: {
2507       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_f32, aco_opcode::v_cmp_lt_f64);
2508       break;
2509    }
2510    case nir_op_fge: {
2511       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_f32, aco_opcode::v_cmp_ge_f64);
2512       break;
2513    }
2514    case nir_op_feq: {
2515       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_eq_f32, aco_opcode::v_cmp_eq_f64);
2516       break;
2517    }
2518    case nir_op_fne: {
2519       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_neq_f32, aco_opcode::v_cmp_neq_f64);
2520       break;
2521    }
2522    case nir_op_ilt: {
2523       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_i32, aco_opcode::v_cmp_lt_i64, aco_opcode::s_cmp_lt_i32);
2524       break;
2525    }
2526    case nir_op_ige: {
2527       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_i32, aco_opcode::v_cmp_ge_i64, aco_opcode::s_cmp_ge_i32);
2528       break;
2529    }
2530    case nir_op_ieq: {
2531       if (instr->src[0].src.ssa->bit_size == 1)
2532          emit_boolean_logic(ctx, instr, Builder::s_xnor, dst);
2533       else
2534          emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_eq_i32, aco_opcode::v_cmp_eq_i64, aco_opcode::s_cmp_eq_i32,
2535                          ctx->program->chip_class >= GFX8 ? aco_opcode::s_cmp_eq_u64 : aco_opcode::num_opcodes);
2536       break;
2537    }
2538    case nir_op_ine: {
2539       if (instr->src[0].src.ssa->bit_size == 1)
2540          emit_boolean_logic(ctx, instr, Builder::s_xor, dst);
2541       else
2542          emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lg_i32, aco_opcode::v_cmp_lg_i64, aco_opcode::s_cmp_lg_i32,
2543                          ctx->program->chip_class >= GFX8 ? aco_opcode::s_cmp_lg_u64 : aco_opcode::num_opcodes);
2544       break;
2545    }
2546    case nir_op_ult: {
2547       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_u32, aco_opcode::v_cmp_lt_u64, aco_opcode::s_cmp_lt_u32);
2548       break;
2549    }
2550    case nir_op_uge: {
2551       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_u32, aco_opcode::v_cmp_ge_u64, aco_opcode::s_cmp_ge_u32);
2552       break;
2553    }
2554    case nir_op_fddx:
2555    case nir_op_fddy:
2556    case nir_op_fddx_fine:
2557    case nir_op_fddy_fine:
2558    case nir_op_fddx_coarse:
2559    case nir_op_fddy_coarse: {
2560       Temp src = get_alu_src(ctx, instr->src[0]);
2561       uint16_t dpp_ctrl1, dpp_ctrl2;
2562       if (instr->op == nir_op_fddx_fine) {
2563          dpp_ctrl1 = dpp_quad_perm(0, 0, 2, 2);
2564          dpp_ctrl2 = dpp_quad_perm(1, 1, 3, 3);
2565       } else if (instr->op == nir_op_fddy_fine) {
2566          dpp_ctrl1 = dpp_quad_perm(0, 1, 0, 1);
2567          dpp_ctrl2 = dpp_quad_perm(2, 3, 2, 3);
2568       } else {
2569          dpp_ctrl1 = dpp_quad_perm(0, 0, 0, 0);
2570          if (instr->op == nir_op_fddx || instr->op == nir_op_fddx_coarse)
2571             dpp_ctrl2 = dpp_quad_perm(1, 1, 1, 1);
2572          else
2573             dpp_ctrl2 = dpp_quad_perm(2, 2, 2, 2);
2574       }
2575
2576       Temp tmp;
2577       if (ctx->program->chip_class >= GFX8) {
2578          Temp tl = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl1);
2579          tmp = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), src, tl, dpp_ctrl2);
2580       } else {
2581          Temp tl = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl1);
2582          Temp tr = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl2);
2583          tmp = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), tr, tl);
2584       }
2585       emit_wqm(ctx, tmp, dst, true);
2586       break;
2587    }
2588    default:
2589       fprintf(stderr, "Unknown NIR ALU instr: ");
2590       nir_print_instr(&instr->instr, stderr);
2591       fprintf(stderr, "\n");
2592    }
2593 }
2594
2595 void visit_load_const(isel_context *ctx, nir_load_const_instr *instr)
2596 {
2597    Temp dst = get_ssa_temp(ctx, &instr->def);
2598
2599    // TODO: we really want to have the resulting type as this would allow for 64bit literals
2600    // which get truncated the lsb if double and msb if int
2601    // for now, we only use s_mov_b64 with 64bit inline constants
2602    assert(instr->def.num_components == 1 && "Vector load_const should be lowered to scalar.");
2603    assert(dst.type() == RegType::sgpr);
2604
2605    Builder bld(ctx->program, ctx->block);
2606
2607    if (instr->def.bit_size == 1) {
2608       assert(dst.regClass() == bld.lm);
2609       int val = instr->value[0].b ? -1 : 0;
2610       Operand op = bld.lm.size() == 1 ? Operand((uint32_t) val) : Operand((uint64_t) val);
2611       bld.sop1(Builder::s_mov, Definition(dst), op);
2612    } else if (dst.size() == 1) {
2613       bld.copy(Definition(dst), Operand(instr->value[0].u32));
2614    } else {
2615       assert(dst.size() != 1);
2616       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
2617       if (instr->def.bit_size == 64)
2618          for (unsigned i = 0; i < dst.size(); i++)
2619             vec->operands[i] = Operand{(uint32_t)(instr->value[0].u64 >> i * 32)};
2620       else {
2621          for (unsigned i = 0; i < dst.size(); i++)
2622             vec->operands[i] = Operand{instr->value[i].u32};
2623       }
2624       vec->definitions[0] = Definition(dst);
2625       ctx->block->instructions.emplace_back(std::move(vec));
2626    }
2627 }
2628
2629 uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2630 {
2631    uint32_t new_mask = 0;
2632    for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2633       if (mask & (1u << i))
2634          new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2635    return new_mask;
2636 }
2637
2638 Operand load_lds_size_m0(isel_context *ctx)
2639 {
2640    /* TODO: m0 does not need to be initialized on GFX9+ */
2641    Builder bld(ctx->program, ctx->block);
2642    return bld.m0((Temp)bld.sopk(aco_opcode::s_movk_i32, bld.def(s1, m0), 0xffff));
2643 }
2644
2645 Temp load_lds(isel_context *ctx, unsigned elem_size_bytes, Temp dst,
2646               Temp address, unsigned base_offset, unsigned align)
2647 {
2648    assert(util_is_power_of_two_nonzero(align) && align >= 4);
2649
2650    Builder bld(ctx->program, ctx->block);
2651
2652    Operand m = load_lds_size_m0(ctx);
2653
2654    unsigned num_components = dst.size() * 4u / elem_size_bytes;
2655    unsigned bytes_read = 0;
2656    unsigned result_size = 0;
2657    unsigned total_bytes = num_components * elem_size_bytes;
2658    std::array<Temp, NIR_MAX_VEC_COMPONENTS> result;
2659    bool large_ds_read = ctx->options->chip_class >= GFX7;
2660    bool usable_read2 = ctx->options->chip_class >= GFX7;
2661
2662    while (bytes_read < total_bytes) {
2663       unsigned todo = total_bytes - bytes_read;
2664       bool aligned8 = bytes_read % 8 == 0 && align % 8 == 0;
2665       bool aligned16 = bytes_read % 16 == 0 && align % 16 == 0;
2666
2667       aco_opcode op = aco_opcode::last_opcode;
2668       bool read2 = false;
2669       if (todo >= 16 && aligned16 && large_ds_read) {
2670          op = aco_opcode::ds_read_b128;
2671          todo = 16;
2672       } else if (todo >= 16 && aligned8 && usable_read2) {
2673          op = aco_opcode::ds_read2_b64;
2674          read2 = true;
2675          todo = 16;
2676       } else if (todo >= 12 && aligned16 && large_ds_read) {
2677          op = aco_opcode::ds_read_b96;
2678          todo = 12;
2679       } else if (todo >= 8 && aligned8) {
2680          op = aco_opcode::ds_read_b64;
2681          todo = 8;
2682       } else if (todo >= 8 && usable_read2) {
2683          op = aco_opcode::ds_read2_b32;
2684          read2 = true;
2685          todo = 8;
2686       } else if (todo >= 4) {
2687          op = aco_opcode::ds_read_b32;
2688          todo = 4;
2689       } else {
2690          assert(false);
2691       }
2692       assert(todo % elem_size_bytes == 0);
2693       unsigned num_elements = todo / elem_size_bytes;
2694       unsigned offset = base_offset + bytes_read;
2695       unsigned max_offset = read2 ? 1019 : 65535;
2696
2697       Temp address_offset = address;
2698       if (offset > max_offset) {
2699          address_offset = bld.vadd32(bld.def(v1), Operand(base_offset), address_offset);
2700          offset = bytes_read;
2701       }
2702       assert(offset <= max_offset); /* bytes_read shouldn't be large enough for this to happen */
2703
2704       Temp res;
2705       if (num_components == 1 && dst.type() == RegType::vgpr)
2706          res = dst;
2707       else
2708          res = bld.tmp(RegClass(RegType::vgpr, todo / 4));
2709
2710       if (read2)
2711          res = bld.ds(op, Definition(res), address_offset, m, offset / (todo / 2), (offset / (todo / 2)) + 1);
2712       else
2713          res = bld.ds(op, Definition(res), address_offset, m, offset);
2714
2715       if (num_components == 1) {
2716          assert(todo == total_bytes);
2717          if (dst.type() == RegType::sgpr)
2718             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), res);
2719          return dst;
2720       }
2721
2722       if (dst.type() == RegType::sgpr) {
2723          Temp new_res = bld.tmp(RegType::sgpr, res.size());
2724          expand_vector(ctx, res, new_res, res.size(), (1 << res.size()) - 1);
2725          res = new_res;
2726       }
2727
2728       if (num_elements == 1) {
2729          result[result_size++] = res;
2730       } else {
2731          assert(res != dst && res.size() % num_elements == 0);
2732          aco_ptr<Pseudo_instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector, Format::PSEUDO, 1, num_elements)};
2733          split->operands[0] = Operand(res);
2734          for (unsigned i = 0; i < num_elements; i++)
2735             split->definitions[i] = Definition(result[result_size++] = bld.tmp(res.type(), elem_size_bytes / 4));
2736          ctx->block->instructions.emplace_back(std::move(split));
2737       }
2738
2739       bytes_read += todo;
2740    }
2741
2742    assert(result_size == num_components && result_size > 1);
2743    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, result_size, 1)};
2744    for (unsigned i = 0; i < result_size; i++)
2745       vec->operands[i] = Operand(result[i]);
2746    vec->definitions[0] = Definition(dst);
2747    ctx->block->instructions.emplace_back(std::move(vec));
2748    ctx->allocated_vec.emplace(dst.id(), result);
2749
2750    return dst;
2751 }
2752
2753 Temp extract_subvector(isel_context *ctx, Temp data, unsigned start, unsigned size, RegType type)
2754 {
2755    if (start == 0 && size == data.size())
2756       return type == RegType::vgpr ? as_vgpr(ctx, data) : data;
2757
2758    unsigned size_hint = 1;
2759    auto it = ctx->allocated_vec.find(data.id());
2760    if (it != ctx->allocated_vec.end())
2761       size_hint = it->second[0].size();
2762    if (size % size_hint || start % size_hint)
2763       size_hint = 1;
2764
2765    start /= size_hint;
2766    size /= size_hint;
2767
2768    Temp elems[size];
2769    for (unsigned i = 0; i < size; i++)
2770       elems[i] = emit_extract_vector(ctx, data, start + i, RegClass(type, size_hint));
2771
2772    if (size == 1)
2773       return type == RegType::vgpr ? as_vgpr(ctx, elems[0]) : elems[0];
2774
2775    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, size, 1)};
2776    for (unsigned i = 0; i < size; i++)
2777       vec->operands[i] = Operand(elems[i]);
2778    Temp res = {ctx->program->allocateId(), RegClass(type, size * size_hint)};
2779    vec->definitions[0] = Definition(res);
2780    ctx->block->instructions.emplace_back(std::move(vec));
2781    return res;
2782 }
2783
2784 void ds_write_helper(isel_context *ctx, Operand m, Temp address, Temp data, unsigned data_start, unsigned total_size, unsigned offset0, unsigned offset1, unsigned align)
2785 {
2786    Builder bld(ctx->program, ctx->block);
2787    unsigned bytes_written = 0;
2788    bool large_ds_write = ctx->options->chip_class >= GFX7;
2789    bool usable_write2 = ctx->options->chip_class >= GFX7;
2790
2791    while (bytes_written < total_size * 4) {
2792       unsigned todo = total_size * 4 - bytes_written;
2793       bool aligned8 = bytes_written % 8 == 0 && align % 8 == 0;
2794       bool aligned16 = bytes_written % 16 == 0 && align % 16 == 0;
2795
2796       aco_opcode op = aco_opcode::last_opcode;
2797       bool write2 = false;
2798       unsigned size = 0;
2799       if (todo >= 16 && aligned16 && large_ds_write) {
2800          op = aco_opcode::ds_write_b128;
2801          size = 4;
2802       } else if (todo >= 16 && aligned8 && usable_write2) {
2803          op = aco_opcode::ds_write2_b64;
2804          write2 = true;
2805          size = 4;
2806       } else if (todo >= 12 && aligned16 && large_ds_write) {
2807          op = aco_opcode::ds_write_b96;
2808          size = 3;
2809       } else if (todo >= 8 && aligned8) {
2810          op = aco_opcode::ds_write_b64;
2811          size = 2;
2812       } else if (todo >= 8 && usable_write2) {
2813          op = aco_opcode::ds_write2_b32;
2814          write2 = true;
2815          size = 2;
2816       } else if (todo >= 4) {
2817          op = aco_opcode::ds_write_b32;
2818          size = 1;
2819       } else {
2820          assert(false);
2821       }
2822
2823       unsigned offset = offset0 + offset1 + bytes_written;
2824       unsigned max_offset = write2 ? 1020 : 65535;
2825       Temp address_offset = address;
2826       if (offset > max_offset) {
2827          address_offset = bld.vadd32(bld.def(v1), Operand(offset0), address_offset);
2828          offset = offset1 + bytes_written;
2829       }
2830       assert(offset <= max_offset); /* offset1 shouldn't be large enough for this to happen */
2831
2832       if (write2) {
2833          Temp val0 = extract_subvector(ctx, data, data_start + (bytes_written >> 2), size / 2, RegType::vgpr);
2834          Temp val1 = extract_subvector(ctx, data, data_start + (bytes_written >> 2) + 1, size / 2, RegType::vgpr);
2835          bld.ds(op, address_offset, val0, val1, m, offset / size / 2, (offset / size / 2) + 1);
2836       } else {
2837          Temp val = extract_subvector(ctx, data, data_start + (bytes_written >> 2), size, RegType::vgpr);
2838          bld.ds(op, address_offset, val, m, offset);
2839       }
2840
2841       bytes_written += size * 4;
2842    }
2843 }
2844
2845 void store_lds(isel_context *ctx, unsigned elem_size_bytes, Temp data, uint32_t wrmask,
2846                Temp address, unsigned base_offset, unsigned align)
2847 {
2848    assert(util_is_power_of_two_nonzero(align) && align >= 4);
2849    assert(elem_size_bytes == 4 || elem_size_bytes == 8);
2850
2851    Operand m = load_lds_size_m0(ctx);
2852
2853    /* we need at most two stores, assuming that the writemask is at most 4 bits wide */
2854    assert(wrmask <= 0x0f);
2855    int start[2], count[2];
2856    u_bit_scan_consecutive_range(&wrmask, &start[0], &count[0]);
2857    u_bit_scan_consecutive_range(&wrmask, &start[1], &count[1]);
2858    assert(wrmask == 0);
2859
2860    /* one combined store is sufficient */
2861    if (count[0] == count[1] && (align % elem_size_bytes) == 0 && (base_offset % elem_size_bytes) == 0) {
2862       Builder bld(ctx->program, ctx->block);
2863
2864       Temp address_offset = address;
2865       if ((base_offset / elem_size_bytes) + start[1] > 255) {
2866          address_offset = bld.vadd32(bld.def(v1), Operand(base_offset), address_offset);
2867          base_offset = 0;
2868       }
2869
2870       assert(count[0] == 1);
2871       RegClass xtract_rc(RegType::vgpr, elem_size_bytes / 4);
2872
2873       Temp val0 = emit_extract_vector(ctx, data, start[0], xtract_rc);
2874       Temp val1 = emit_extract_vector(ctx, data, start[1], xtract_rc);
2875       aco_opcode op = elem_size_bytes == 4 ? aco_opcode::ds_write2_b32 : aco_opcode::ds_write2_b64;
2876       base_offset = base_offset / elem_size_bytes;
2877       bld.ds(op, address_offset, val0, val1, m,
2878              base_offset + start[0], base_offset + start[1]);
2879       return;
2880    }
2881
2882    for (unsigned i = 0; i < 2; i++) {
2883       if (count[i] == 0)
2884          continue;
2885
2886       unsigned elem_size_words = elem_size_bytes / 4;
2887       ds_write_helper(ctx, m, address, data, start[i] * elem_size_words, count[i] * elem_size_words,
2888                       base_offset, start[i] * elem_size_bytes, align);
2889    }
2890    return;
2891 }
2892
2893 unsigned calculate_lds_alignment(isel_context *ctx, unsigned const_offset)
2894 {
2895    unsigned align = 16;
2896    if (const_offset)
2897       align = std::min(align, 1u << (ffs(const_offset) - 1));
2898
2899    return align;
2900 }
2901
2902
2903 Temp create_vec_from_array(isel_context *ctx, Temp arr[], unsigned cnt, RegType reg_type, unsigned split_cnt = 0u, Temp dst = Temp())
2904 {
2905    Builder bld(ctx->program, ctx->block);
2906
2907    if (!dst.id())
2908       dst = bld.tmp(RegClass(reg_type, cnt * arr[0].size()));
2909
2910    std::array<Temp, NIR_MAX_VEC_COMPONENTS> allocated_vec;
2911    aco_ptr<Pseudo_instruction> instr {create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, cnt, 1)};
2912    instr->definitions[0] = Definition(dst);
2913
2914    for (unsigned i = 0; i < cnt; ++i) {
2915       assert(arr[i].size() == arr[0].size());
2916       allocated_vec[i] = arr[i];
2917       instr->operands[i] = Operand(arr[i]);
2918    }
2919
2920    bld.insert(std::move(instr));
2921
2922    if (split_cnt)
2923       emit_split_vector(ctx, dst, split_cnt);
2924    else
2925       ctx->allocated_vec.emplace(dst.id(), allocated_vec); /* emit_split_vector already does this */
2926
2927    return dst;
2928 }
2929
2930 inline unsigned resolve_excess_vmem_const_offset(Builder &bld, Temp &voffset, unsigned const_offset)
2931 {
2932    if (const_offset >= 4096) {
2933       unsigned excess_const_offset = const_offset / 4096u * 4096u;
2934       const_offset %= 4096u;
2935
2936       if (!voffset.id())
2937          voffset = bld.copy(bld.def(v1), Operand(excess_const_offset));
2938       else if (unlikely(voffset.regClass() == s1))
2939          voffset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), Operand(excess_const_offset), Operand(voffset));
2940       else if (likely(voffset.regClass() == v1))
2941          voffset = bld.vadd32(bld.def(v1), Operand(voffset), Operand(excess_const_offset));
2942       else
2943          unreachable("Unsupported register class of voffset");
2944    }
2945
2946    return const_offset;
2947 }
2948
2949 void emit_single_mubuf_store(isel_context *ctx, Temp descriptor, Temp voffset, Temp soffset, Temp vdata,
2950                              unsigned const_offset = 0u, bool allow_reorder = true, bool slc = false)
2951 {
2952    assert(vdata.id());
2953    assert(vdata.size() != 3 || ctx->program->chip_class != GFX6);
2954    assert(vdata.size() >= 1 && vdata.size() <= 4);
2955
2956    Builder bld(ctx->program, ctx->block);
2957    aco_opcode op = (aco_opcode) ((unsigned) aco_opcode::buffer_store_dword + vdata.size() - 1);
2958    const_offset = resolve_excess_vmem_const_offset(bld, voffset, const_offset);
2959
2960    Operand voffset_op = voffset.id() ? Operand(as_vgpr(ctx, voffset)) : Operand(v1);
2961    Operand soffset_op = soffset.id() ? Operand(soffset) : Operand(0u);
2962    Builder::Result r = bld.mubuf(op, Operand(descriptor), voffset_op, soffset_op, Operand(vdata), const_offset,
2963                                  /* offen */ !voffset_op.isUndefined(), /* idxen*/ false, /* addr64 */ false,
2964                                  /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc);
2965
2966    static_cast<MUBUF_instruction *>(r.instr)->can_reorder = allow_reorder;
2967 }
2968
2969 void store_vmem_mubuf(isel_context *ctx, Temp src, Temp descriptor, Temp voffset, Temp soffset,
2970                                    unsigned base_const_offset, unsigned elem_size_bytes, unsigned write_mask,
2971                                    bool allow_combining = true, bool reorder = true, bool slc = false)
2972 {
2973    Builder bld(ctx->program, ctx->block);
2974    assert(elem_size_bytes == 4 || elem_size_bytes == 8);
2975    assert(write_mask);
2976
2977    if (elem_size_bytes == 8) {
2978       elem_size_bytes = 4;
2979       write_mask = widen_mask(write_mask, 2);
2980    }
2981
2982    while (write_mask) {
2983       int start = 0;
2984       int count = 0;
2985       u_bit_scan_consecutive_range(&write_mask, &start, &count);
2986       assert(count > 0);
2987       assert(start >= 0);
2988
2989       while (count > 0) {
2990          unsigned sub_count = allow_combining ? MIN2(count, 4) : 1;
2991          unsigned const_offset = (unsigned) start * elem_size_bytes + base_const_offset;
2992
2993          /* GFX6 doesn't have buffer_store_dwordx3, so make sure not to emit that here either. */
2994          if (unlikely(ctx->program->chip_class == GFX6 && sub_count == 3))
2995             sub_count = 2;
2996
2997          Temp elem = extract_subvector(ctx, src, start, sub_count, RegType::vgpr);
2998          emit_single_mubuf_store(ctx, descriptor, voffset, soffset, elem, const_offset, reorder, slc);
2999
3000          count -= sub_count;
3001          start += sub_count;
3002       }
3003
3004       assert(count == 0);
3005    }
3006 }
3007
3008 Temp emit_single_mubuf_load(isel_context *ctx, Temp descriptor, Temp voffset, Temp soffset,
3009                             unsigned const_offset, unsigned size_dwords, bool allow_reorder = true)
3010 {
3011    assert(size_dwords != 3 || ctx->program->chip_class != GFX6);
3012    assert(size_dwords >= 1 && size_dwords <= 4);
3013
3014    Builder bld(ctx->program, ctx->block);
3015    Temp vdata = bld.tmp(RegClass(RegType::vgpr, size_dwords));
3016    aco_opcode op = (aco_opcode) ((unsigned) aco_opcode::buffer_load_dword + size_dwords - 1);
3017    const_offset = resolve_excess_vmem_const_offset(bld, voffset, const_offset);
3018
3019    Operand voffset_op = voffset.id() ? Operand(as_vgpr(ctx, voffset)) : Operand(v1);
3020    Operand soffset_op = soffset.id() ? Operand(soffset) : Operand(0u);
3021    Builder::Result r = bld.mubuf(op, Definition(vdata), Operand(descriptor), voffset_op, soffset_op, const_offset,
3022                                  /* offen */ !voffset_op.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3023                                  /* disable_wqm */ false, /* glc */ true,
3024                                  /* dlc*/ ctx->program->chip_class >= GFX10, /* slc */ false);
3025
3026    static_cast<MUBUF_instruction *>(r.instr)->can_reorder = allow_reorder;
3027
3028    return vdata;
3029 }
3030
3031 void load_vmem_mubuf(isel_context *ctx, Temp dst, Temp descriptor, Temp voffset, Temp soffset,
3032                      unsigned base_const_offset, unsigned elem_size_bytes, unsigned num_components,
3033                      unsigned stride = 0u, bool allow_combining = true, bool allow_reorder = true)
3034 {
3035    assert(elem_size_bytes == 4 || elem_size_bytes == 8);
3036    assert((num_components * elem_size_bytes / 4) == dst.size());
3037    assert(!!stride != allow_combining);
3038
3039    Builder bld(ctx->program, ctx->block);
3040    unsigned split_cnt = num_components;
3041
3042    if (elem_size_bytes == 8) {
3043       elem_size_bytes = 4;
3044       num_components *= 2;
3045    }
3046
3047    if (!stride)
3048       stride = elem_size_bytes;
3049
3050    unsigned load_size = 1;
3051    if (allow_combining) {
3052       if ((num_components % 4) == 0)
3053          load_size = 4;
3054       else if ((num_components % 3) == 0 && ctx->program->chip_class != GFX6)
3055          load_size = 3;
3056       else if ((num_components % 2) == 0)
3057          load_size = 2;
3058    }
3059
3060    unsigned num_loads = num_components / load_size;
3061    std::array<Temp, NIR_MAX_VEC_COMPONENTS> elems;
3062
3063    for (unsigned i = 0; i < num_loads; ++i) {
3064       unsigned const_offset = i * stride * load_size + base_const_offset;
3065       elems[i] = emit_single_mubuf_load(ctx, descriptor, voffset, soffset, const_offset, load_size, allow_reorder);
3066    }
3067
3068    create_vec_from_array(ctx, elems.data(), num_loads, RegType::vgpr, split_cnt, dst);
3069 }
3070
3071 std::pair<Temp, unsigned> offset_add_from_nir(isel_context *ctx, const std::pair<Temp, unsigned> &base_offset, nir_src *off_src, unsigned stride = 1u)
3072 {
3073    Builder bld(ctx->program, ctx->block);
3074    Temp offset = base_offset.first;
3075    unsigned const_offset = base_offset.second;
3076
3077    if (!nir_src_is_const(*off_src)) {
3078       Temp indirect_offset_arg = get_ssa_temp(ctx, off_src->ssa);
3079       Temp with_stride;
3080
3081       /* Calculate indirect offset with stride */
3082       if (likely(indirect_offset_arg.regClass() == v1))
3083          with_stride = bld.v_mul_imm(bld.def(v1), indirect_offset_arg, stride);
3084       else if (indirect_offset_arg.regClass() == s1)
3085          with_stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), indirect_offset_arg);
3086       else
3087          unreachable("Unsupported register class of indirect offset");
3088
3089       /* Add to the supplied base offset */
3090       if (offset.id() == 0)
3091          offset = with_stride;
3092       else if (unlikely(offset.regClass() == s1 && with_stride.regClass() == s1))
3093          offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), with_stride, offset);
3094       else if (offset.size() == 1 && with_stride.size() == 1)
3095          offset = bld.vadd32(bld.def(v1), with_stride, offset);
3096       else
3097          unreachable("Unsupported register class of indirect offset");
3098    } else {
3099       unsigned const_offset_arg = nir_src_as_uint(*off_src);
3100       const_offset += const_offset_arg * stride;
3101    }
3102
3103    return std::make_pair(offset, const_offset);
3104 }
3105
3106 std::pair<Temp, unsigned> offset_add(isel_context *ctx, const std::pair<Temp, unsigned> &off1, const std::pair<Temp, unsigned> &off2)
3107 {
3108    Builder bld(ctx->program, ctx->block);
3109    Temp offset;
3110
3111    if (off1.first.id() && off2.first.id()) {
3112       if (unlikely(off1.first.regClass() == s1 && off2.first.regClass() == s1))
3113          offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), off1.first, off2.first);
3114       else if (off1.first.size() == 1 && off2.first.size() == 1)
3115          offset = bld.vadd32(bld.def(v1), off1.first, off2.first);
3116       else
3117          unreachable("Unsupported register class of indirect offset");
3118    } else {
3119       offset = off1.first.id() ? off1.first : off2.first;
3120    }
3121
3122    return std::make_pair(offset, off1.second + off2.second);
3123 }
3124
3125 std::pair<Temp, unsigned> offset_mul(isel_context *ctx, const std::pair<Temp, unsigned> &offs, unsigned multiplier)
3126 {
3127    Builder bld(ctx->program, ctx->block);
3128    unsigned const_offset = offs.second * multiplier;
3129
3130    if (!offs.first.id())
3131       return std::make_pair(offs.first, const_offset);
3132
3133    Temp offset = unlikely(offs.first.regClass() == s1)
3134                  ? bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(multiplier), offs.first)
3135                  : bld.v_mul_imm(bld.def(v1), offs.first, multiplier);
3136
3137    return std::make_pair(offset, const_offset);
3138 }
3139
3140 std::pair<Temp, unsigned> get_intrinsic_io_basic_offset(isel_context *ctx, nir_intrinsic_instr *instr, unsigned base_stride, unsigned component_stride)
3141 {
3142    Builder bld(ctx->program, ctx->block);
3143
3144    /* base is the driver_location, which is already multiplied by 4, so is in dwords */
3145    unsigned const_offset = nir_intrinsic_base(instr) * base_stride;
3146    /* component is in bytes */
3147    const_offset += nir_intrinsic_component(instr) * component_stride;
3148
3149    /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
3150    nir_src *off_src = nir_get_io_offset_src(instr);
3151    return offset_add_from_nir(ctx, std::make_pair(Temp(), const_offset), off_src, 4u * base_stride);
3152 }
3153
3154 std::pair<Temp, unsigned> get_intrinsic_io_basic_offset(isel_context *ctx, nir_intrinsic_instr *instr, unsigned stride = 1u)
3155 {
3156    return get_intrinsic_io_basic_offset(ctx, instr, stride, stride);
3157 }
3158
3159 Temp get_tess_rel_patch_id(isel_context *ctx)
3160 {
3161    Builder bld(ctx->program, ctx->block);
3162
3163    switch (ctx->shader->info.stage) {
3164    case MESA_SHADER_TESS_CTRL:
3165       return bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0xffu),
3166                       get_arg(ctx, ctx->args->ac.tcs_rel_ids));
3167    case MESA_SHADER_TESS_EVAL:
3168       return get_arg(ctx, ctx->args->tes_rel_patch_id);
3169    default:
3170       unreachable("Unsupported stage in get_tess_rel_patch_id");
3171    }
3172 }
3173
3174 std::pair<Temp, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context *ctx, nir_intrinsic_instr *instr)
3175 {
3176    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
3177    Builder bld(ctx->program, ctx->block);
3178
3179    uint32_t tcs_in_patch_stride = ctx->args->options->key.tcs.input_vertices * ctx->tcs_num_inputs * 4;
3180    uint32_t tcs_in_vertex_stride = ctx->tcs_num_inputs * 4;
3181
3182    std::pair<Temp, unsigned> offs = get_intrinsic_io_basic_offset(ctx, instr);
3183
3184    nir_src *vertex_index_src = nir_get_io_vertex_index_src(instr);
3185    offs = offset_add_from_nir(ctx, offs, vertex_index_src, tcs_in_vertex_stride);
3186
3187    Temp rel_patch_id = get_tess_rel_patch_id(ctx);
3188    Temp tcs_in_current_patch_offset = bld.v_mul24_imm(bld.def(v1), rel_patch_id, tcs_in_patch_stride);
3189    offs = offset_add(ctx, offs, std::make_pair(tcs_in_current_patch_offset, 0));
3190
3191    return offset_mul(ctx, offs, 4u);
3192 }
3193
3194 std::pair<Temp, unsigned> get_tcs_output_lds_offset(isel_context *ctx, nir_intrinsic_instr *instr = nullptr, bool per_vertex = false)
3195 {
3196    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
3197    Builder bld(ctx->program, ctx->block);
3198
3199    uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * ctx->tcs_num_inputs * 16;
3200    uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
3201    uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->args->shader_info->tcs.patch_outputs_written);
3202    uint32_t output_vertex_size = num_tcs_outputs * 16;
3203    uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
3204    uint32_t output_patch_stride = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
3205
3206    std::pair<Temp, unsigned> offs = instr
3207                                     ? get_intrinsic_io_basic_offset(ctx, instr, 4u)
3208                                     : std::make_pair(Temp(), 0u);
3209
3210    Temp rel_patch_id = get_tess_rel_patch_id(ctx);
3211    Temp patch_off = bld.v_mul24_imm(bld.def(v1), rel_patch_id, output_patch_stride);
3212
3213    if (per_vertex) {
3214       assert(instr);
3215
3216       nir_src *vertex_index_src = nir_get_io_vertex_index_src(instr);
3217       offs = offset_add_from_nir(ctx, offs, vertex_index_src, output_vertex_size);
3218
3219       uint32_t output_patch0_offset = (input_patch_size * ctx->tcs_num_patches);
3220       offs = offset_add(ctx, offs, std::make_pair(patch_off, output_patch0_offset));
3221    } else {
3222       uint32_t output_patch0_patch_data_offset = (input_patch_size * ctx->tcs_num_patches + pervertex_output_patch_size);
3223       offs = offset_add(ctx, offs, std::make_pair(patch_off, output_patch0_patch_data_offset));
3224    }
3225
3226    return offs;
3227 }
3228
3229 std::pair<Temp, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context *ctx, nir_intrinsic_instr *instr)
3230 {
3231    Builder bld(ctx->program, ctx->block);
3232
3233    unsigned vertices_per_patch = ctx->shader->info.tess.tcs_vertices_out;
3234    unsigned attr_stride = vertices_per_patch * ctx->tcs_num_patches;
3235
3236    std::pair<Temp, unsigned> offs = get_intrinsic_io_basic_offset(ctx, instr, attr_stride * 4u, 4u);
3237
3238    Temp rel_patch_id = get_tess_rel_patch_id(ctx);
3239    Temp patch_off = bld.v_mul24_imm(bld.def(v1), rel_patch_id, vertices_per_patch * 16u);
3240    offs = offset_add(ctx, offs, std::make_pair(patch_off, 0u));
3241
3242    nir_src *vertex_index_src = nir_get_io_vertex_index_src(instr);
3243    offs = offset_add_from_nir(ctx, offs, vertex_index_src, 16u);
3244
3245    return offs;
3246 }
3247
3248 std::pair<Temp, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context *ctx, nir_intrinsic_instr *instr = nullptr, unsigned const_base_offset = 0u)
3249 {
3250    Builder bld(ctx->program, ctx->block);
3251
3252    unsigned num_tcs_outputs = ctx->shader->info.stage == MESA_SHADER_TESS_CTRL
3253                               ? util_last_bit64(ctx->args->shader_info->tcs.outputs_written)
3254                               : ctx->args->options->key.tes.tcs_num_outputs;
3255
3256    unsigned output_vertex_size = num_tcs_outputs * 16;
3257    unsigned per_vertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
3258    unsigned per_patch_data_offset = per_vertex_output_patch_size * ctx->tcs_num_patches;
3259    unsigned attr_stride = ctx->tcs_num_patches;
3260
3261    std::pair<Temp, unsigned> offs = instr
3262                                     ? get_intrinsic_io_basic_offset(ctx, instr, attr_stride * 4u, 4u)
3263                                     : std::make_pair(Temp(), 0u);
3264
3265    if (const_base_offset)
3266       offs.second += const_base_offset * attr_stride;
3267
3268    Temp rel_patch_id = get_tess_rel_patch_id(ctx);
3269    Temp patch_off = bld.v_mul_imm(bld.def(v1), rel_patch_id, 16u);
3270    offs = offset_add(ctx, offs, std::make_pair(patch_off, per_patch_data_offset));
3271
3272    return offs;
3273 }
3274
3275 void visit_store_ls_or_es_output(isel_context *ctx, nir_intrinsic_instr *instr)
3276 {
3277    Builder bld(ctx->program, ctx->block);
3278
3279    std::pair<Temp, unsigned> offs = get_intrinsic_io_basic_offset(ctx, instr, 4u);
3280    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
3281    unsigned write_mask = nir_intrinsic_write_mask(instr);
3282    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8u;
3283
3284    if (ctx->stage == vertex_es || ctx->stage == tess_eval_es) {
3285       /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
3286       Temp esgs_ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_ESGS_VS * 16u));
3287       Temp es2gs_offset = get_arg(ctx, ctx->args->es2gs_offset);
3288       store_vmem_mubuf(ctx, src, esgs_ring, offs.first, es2gs_offset, offs.second, elem_size_bytes, write_mask, false, true, true);
3289    } else {
3290       Temp lds_base;
3291
3292       if (ctx->stage == vertex_geometry_gs || ctx->stage == tess_eval_geometry_gs) {
3293          /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
3294          unsigned itemsize = ctx->stage == vertex_geometry_gs
3295                              ? ctx->program->info->vs.es_info.esgs_itemsize
3296                              : ctx->program->info->tes.es_info.esgs_itemsize;
3297          Temp thread_id = emit_mbcnt(ctx, bld.def(v1));
3298          Temp wave_idx = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), get_arg(ctx, ctx->args->merged_wave_info), Operand(4u << 16 | 24));
3299          Temp vertex_idx = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), thread_id,
3300                                bld.v_mul24_imm(bld.def(v1), as_vgpr(ctx, wave_idx), ctx->program->wave_size));
3301          lds_base = bld.v_mul24_imm(bld.def(v1), vertex_idx, itemsize);
3302       } else if (ctx->stage == vertex_ls || ctx->stage == vertex_tess_control_hs) {
3303          /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
3304           * GFX9+: LS is merged into HS, but still uses the same LDS layout.
3305           */
3306          unsigned num_tcs_inputs = util_last_bit64(ctx->args->shader_info->vs.ls_outputs_written);
3307          Temp vertex_idx = get_arg(ctx, ctx->args->rel_auto_id);
3308          lds_base = bld.v_mul_imm(bld.def(v1), vertex_idx, num_tcs_inputs * 16u);
3309       } else {
3310          unreachable("Invalid LS or ES stage");
3311       }
3312
3313       offs = offset_add(ctx, offs, std::make_pair(lds_base, 0u));
3314       unsigned lds_align = calculate_lds_alignment(ctx, offs.second);
3315       store_lds(ctx, elem_size_bytes, src, write_mask, offs.first, offs.second, lds_align);
3316    }
3317 }
3318
3319 bool should_write_tcs_patch_output_to_vmem(isel_context *ctx, nir_intrinsic_instr *instr)
3320 {
3321    unsigned off = nir_intrinsic_base(instr) * 4u;
3322    nir_src *off_src = nir_get_io_offset_src(instr);
3323
3324    /* Indirect offset, we can't be sure if this is a tess factor, always write to VMEM */
3325    if (!nir_src_is_const(*off_src))
3326       return true;
3327
3328    off += nir_src_as_uint(*off_src) * 16u;
3329
3330    const unsigned tess_index_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
3331    const unsigned tess_index_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
3332
3333    return (off != (tess_index_inner * 16u)) &&
3334           (off != (tess_index_outer * 16u));
3335 }
3336
3337 bool should_write_tcs_patch_output_to_lds(isel_context *ctx, nir_intrinsic_instr *instr, bool per_vertex)
3338 {
3339    unsigned off = nir_intrinsic_base(instr) * 4u;
3340    nir_src *off_src = nir_get_io_offset_src(instr);
3341
3342    /* When none of the appropriate outputs are read, we are OK to never write to LDS */
3343    if (per_vertex ? ctx->shader->info.outputs_read == 0U : ctx->shader->info.patch_outputs_read == 0u)
3344       return false;
3345
3346    /* Indirect offset, we can't be sure if this is read or not, always write to LDS */
3347    if (!nir_src_is_const(*off_src))
3348       return true;
3349
3350    off += nir_src_as_uint(*off_src) * 16u;
3351
3352    uint64_t out_rd = per_vertex
3353                      ? ctx->shader->info.outputs_read
3354                      : ctx->shader->info.patch_outputs_read;
3355    while (out_rd) {
3356       unsigned slot = u_bit_scan64(&out_rd) + (per_vertex ? 0 : VARYING_SLOT_PATCH0);
3357       if (off == shader_io_get_unique_index((gl_varying_slot) slot) * 16u)
3358          return true;
3359    }
3360
3361    return false;
3362 }
3363
3364 void visit_store_tcs_output(isel_context *ctx, nir_intrinsic_instr *instr, bool per_vertex)
3365 {
3366    assert(ctx->stage == tess_control_hs || ctx->stage == vertex_tess_control_hs);
3367    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
3368
3369    Builder bld(ctx->program, ctx->block);
3370
3371    Temp store_val = get_ssa_temp(ctx, instr->src[0].ssa);
3372    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
3373    unsigned write_mask = nir_intrinsic_write_mask(instr);
3374
3375    /* Only write to VMEM if the output is per-vertex or it's per-patch non tess factor */
3376    bool write_to_vmem = per_vertex || should_write_tcs_patch_output_to_vmem(ctx, instr);
3377    /* Only write to LDS if the output is read by the shader, or it's per-patch tess factor */
3378    bool write_to_lds = !write_to_vmem || should_write_tcs_patch_output_to_lds(ctx, instr, per_vertex);
3379
3380    if (write_to_vmem) {
3381       std::pair<Temp, unsigned> vmem_offs = per_vertex
3382                                             ? get_tcs_per_vertex_output_vmem_offset(ctx, instr)
3383                                             : get_tcs_per_patch_output_vmem_offset(ctx, instr);
3384
3385       Temp hs_ring_tess_offchip = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_HS_TESS_OFFCHIP * 16u));
3386       Temp oc_lds = get_arg(ctx, ctx->args->oc_lds);
3387       store_vmem_mubuf(ctx, store_val, hs_ring_tess_offchip, vmem_offs.first, oc_lds, vmem_offs.second, elem_size_bytes, write_mask, false, false);
3388    }
3389
3390    if (write_to_lds) {
3391       std::pair<Temp, unsigned> lds_offs = get_tcs_output_lds_offset(ctx, instr, per_vertex);
3392       unsigned lds_align = calculate_lds_alignment(ctx, lds_offs.second);
3393       store_lds(ctx, elem_size_bytes, store_val, write_mask, lds_offs.first, lds_offs.second, lds_align);
3394    }
3395 }
3396
3397 void visit_load_tcs_output(isel_context *ctx, nir_intrinsic_instr *instr, bool per_vertex)
3398 {
3399    assert(ctx->stage == tess_control_hs || ctx->stage == vertex_tess_control_hs);
3400    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
3401
3402    Builder bld(ctx->program, ctx->block);
3403
3404    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3405    std::pair<Temp, unsigned> lds_offs = get_tcs_output_lds_offset(ctx, instr, per_vertex);
3406    unsigned lds_align = calculate_lds_alignment(ctx, lds_offs.second);
3407    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
3408
3409    load_lds(ctx, elem_size_bytes, dst, lds_offs.first, lds_offs.second, lds_align);
3410 }
3411
3412 void visit_store_output(isel_context *ctx, nir_intrinsic_instr *instr)
3413 {
3414    if (ctx->stage == vertex_vs ||
3415        ctx->stage == tess_eval_vs ||
3416        ctx->stage == fragment_fs ||
3417        ctx->shader->info.stage == MESA_SHADER_GEOMETRY) {
3418       unsigned write_mask = nir_intrinsic_write_mask(instr);
3419       unsigned component = nir_intrinsic_component(instr);
3420       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
3421       unsigned idx = nir_intrinsic_base(instr) + component;
3422
3423       nir_instr *off_instr = instr->src[1].ssa->parent_instr;
3424       if (off_instr->type != nir_instr_type_load_const) {
3425          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
3426          nir_print_instr(off_instr, stderr);
3427          fprintf(stderr, "\n");
3428       }
3429       idx += nir_instr_as_load_const(off_instr)->value[0].u32 * 4u;
3430
3431       if (instr->src[0].ssa->bit_size == 64)
3432          write_mask = widen_mask(write_mask, 2);
3433
3434       for (unsigned i = 0; i < 8; ++i) {
3435          if (write_mask & (1 << i)) {
3436             ctx->outputs.mask[idx / 4u] |= 1 << (idx % 4u);
3437             ctx->outputs.outputs[idx / 4u][idx % 4u] = emit_extract_vector(ctx, src, i, v1);
3438          }
3439          idx++;
3440       }
3441    } else if (ctx->stage == vertex_es ||
3442               ctx->stage == vertex_ls ||
3443               ctx->stage == tess_eval_es ||
3444               (ctx->stage == vertex_tess_control_hs && ctx->shader->info.stage == MESA_SHADER_VERTEX) ||
3445               (ctx->stage == vertex_geometry_gs && ctx->shader->info.stage == MESA_SHADER_VERTEX) ||
3446               (ctx->stage == tess_eval_geometry_gs && ctx->shader->info.stage == MESA_SHADER_TESS_EVAL)) {
3447       visit_store_ls_or_es_output(ctx, instr);
3448    } else if (ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) {
3449       visit_store_tcs_output(ctx, instr, false);
3450    } else {
3451       unreachable("Shader stage not implemented");
3452    }
3453 }
3454
3455 void visit_load_output(isel_context *ctx, nir_intrinsic_instr *instr)
3456 {
3457    visit_load_tcs_output(ctx, instr, false);
3458 }
3459
3460 void emit_interp_instr(isel_context *ctx, unsigned idx, unsigned component, Temp src, Temp dst, Temp prim_mask)
3461 {
3462    Temp coord1 = emit_extract_vector(ctx, src, 0, v1);
3463    Temp coord2 = emit_extract_vector(ctx, src, 1, v1);
3464
3465    Builder bld(ctx->program, ctx->block);
3466    Temp tmp = bld.vintrp(aco_opcode::v_interp_p1_f32, bld.def(v1), coord1, bld.m0(prim_mask), idx, component);
3467    bld.vintrp(aco_opcode::v_interp_p2_f32, Definition(dst), coord2, bld.m0(prim_mask), tmp, idx, component);
3468 }
3469
3470 void emit_load_frag_coord(isel_context *ctx, Temp dst, unsigned num_components)
3471 {
3472    aco_ptr<Pseudo_instruction> vec(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1));
3473    for (unsigned i = 0; i < num_components; i++)
3474       vec->operands[i] = Operand(get_arg(ctx, ctx->args->ac.frag_pos[i]));
3475    if (G_0286CC_POS_W_FLOAT_ENA(ctx->program->config->spi_ps_input_ena)) {
3476       assert(num_components == 4);
3477       Builder bld(ctx->program, ctx->block);
3478       vec->operands[3] = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), get_arg(ctx, ctx->args->ac.frag_pos[3]));
3479    }
3480
3481    for (Operand& op : vec->operands)
3482       op = op.isUndefined() ? Operand(0u) : op;
3483
3484    vec->definitions[0] = Definition(dst);
3485    ctx->block->instructions.emplace_back(std::move(vec));
3486    emit_split_vector(ctx, dst, num_components);
3487    return;
3488 }
3489
3490 void visit_load_interpolated_input(isel_context *ctx, nir_intrinsic_instr *instr)
3491 {
3492    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3493    Temp coords = get_ssa_temp(ctx, instr->src[0].ssa);
3494    unsigned idx = nir_intrinsic_base(instr);
3495    unsigned component = nir_intrinsic_component(instr);
3496    Temp prim_mask = get_arg(ctx, ctx->args->ac.prim_mask);
3497
3498    nir_const_value* offset = nir_src_as_const_value(instr->src[1]);
3499    if (offset) {
3500       assert(offset->u32 == 0);
3501    } else {
3502       /* the lower 15bit of the prim_mask contain the offset into LDS
3503        * while the upper bits contain the number of prims */
3504       Temp offset_src = get_ssa_temp(ctx, instr->src[1].ssa);
3505       assert(offset_src.regClass() == s1 && "TODO: divergent offsets...");
3506       Builder bld(ctx->program, ctx->block);
3507       Temp stride = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), prim_mask, Operand(16u));
3508       stride = bld.sop1(aco_opcode::s_bcnt1_i32_b32, bld.def(s1), bld.def(s1, scc), stride);
3509       stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, Operand(48u));
3510       offset_src = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, offset_src);
3511       prim_mask = bld.sop2(aco_opcode::s_add_i32, bld.def(s1, m0), bld.def(s1, scc), offset_src, prim_mask);
3512    }
3513
3514    if (instr->dest.ssa.num_components == 1) {
3515       emit_interp_instr(ctx, idx, component, coords, dst, prim_mask);
3516    } else {
3517       aco_ptr<Pseudo_instruction> vec(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.ssa.num_components, 1));
3518       for (unsigned i = 0; i < instr->dest.ssa.num_components; i++)
3519       {
3520          Temp tmp = {ctx->program->allocateId(), v1};
3521          emit_interp_instr(ctx, idx, component+i, coords, tmp, prim_mask);
3522          vec->operands[i] = Operand(tmp);
3523       }
3524       vec->definitions[0] = Definition(dst);
3525       ctx->block->instructions.emplace_back(std::move(vec));
3526    }
3527 }
3528
3529 bool check_vertex_fetch_size(isel_context *ctx, const ac_data_format_info *vtx_info,
3530                              unsigned offset, unsigned stride, unsigned channels)
3531 {
3532    unsigned vertex_byte_size = vtx_info->chan_byte_size * channels;
3533    if (vtx_info->chan_byte_size != 4 && channels == 3)
3534       return false;
3535    return (ctx->options->chip_class != GFX6 && ctx->options->chip_class != GFX10) ||
3536           (offset % vertex_byte_size == 0 && stride % vertex_byte_size == 0);
3537 }
3538
3539 uint8_t get_fetch_data_format(isel_context *ctx, const ac_data_format_info *vtx_info,
3540                               unsigned offset, unsigned stride, unsigned *channels)
3541 {
3542    if (!vtx_info->chan_byte_size) {
3543       *channels = vtx_info->num_channels;
3544       return vtx_info->chan_format;
3545    }
3546
3547    unsigned num_channels = *channels;
3548    if (!check_vertex_fetch_size(ctx, vtx_info, offset, stride, *channels)) {
3549       unsigned new_channels = num_channels + 1;
3550       /* first, assume more loads is worse and try using a larger data format */
3551       while (new_channels <= 4 && !check_vertex_fetch_size(ctx, vtx_info, offset, stride, new_channels)) {
3552          new_channels++;
3553          /* don't make the attribute potentially out-of-bounds */
3554          if (offset + new_channels * vtx_info->chan_byte_size > stride)
3555             new_channels = 5;
3556       }
3557
3558       if (new_channels == 5) {
3559          /* then try decreasing load size (at the cost of more loads) */
3560          new_channels = *channels;
3561          while (new_channels > 1 && !check_vertex_fetch_size(ctx, vtx_info, offset, stride, new_channels))
3562             new_channels--;
3563       }
3564
3565       if (new_channels < *channels)
3566          *channels = new_channels;
3567       num_channels = new_channels;
3568    }
3569
3570    switch (vtx_info->chan_format) {
3571    case V_008F0C_BUF_DATA_FORMAT_8:
3572       return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8, V_008F0C_BUF_DATA_FORMAT_8_8,
3573                          V_008F0C_BUF_DATA_FORMAT_INVALID, V_008F0C_BUF_DATA_FORMAT_8_8_8_8}[num_channels - 1];
3574    case V_008F0C_BUF_DATA_FORMAT_16:
3575       return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16, V_008F0C_BUF_DATA_FORMAT_16_16,
3576                          V_008F0C_BUF_DATA_FORMAT_INVALID, V_008F0C_BUF_DATA_FORMAT_16_16_16_16}[num_channels - 1];
3577    case V_008F0C_BUF_DATA_FORMAT_32:
3578       return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32, V_008F0C_BUF_DATA_FORMAT_32_32,
3579                          V_008F0C_BUF_DATA_FORMAT_32_32_32, V_008F0C_BUF_DATA_FORMAT_32_32_32_32}[num_channels - 1];
3580    }
3581    unreachable("shouldn't reach here");
3582    return V_008F0C_BUF_DATA_FORMAT_INVALID;
3583 }
3584
3585 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
3586  * so we may need to fix it up. */
3587 Temp adjust_vertex_fetch_alpha(isel_context *ctx, unsigned adjustment, Temp alpha)
3588 {
3589    Builder bld(ctx->program, ctx->block);
3590
3591    if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
3592       alpha = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), alpha);
3593
3594    /* For the integer-like cases, do a natural sign extension.
3595     *
3596     * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
3597     * and happen to contain 0, 1, 2, 3 as the two LSBs of the
3598     * exponent.
3599     */
3600    alpha = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(adjustment == RADV_ALPHA_ADJUST_SNORM ? 7u : 30u), alpha);
3601    alpha = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(30u), alpha);
3602
3603    /* Convert back to the right type. */
3604    if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
3605       alpha = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), alpha);
3606       Temp clamp = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0xbf800000u), alpha);
3607       alpha = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xbf800000u), alpha, clamp);
3608    } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
3609       alpha = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), alpha);
3610    }
3611
3612    return alpha;
3613 }
3614
3615 void visit_load_input(isel_context *ctx, nir_intrinsic_instr *instr)
3616 {
3617    Builder bld(ctx->program, ctx->block);
3618    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3619    if (ctx->shader->info.stage == MESA_SHADER_VERTEX) {
3620
3621       nir_instr *off_instr = instr->src[0].ssa->parent_instr;
3622       if (off_instr->type != nir_instr_type_load_const) {
3623          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
3624          nir_print_instr(off_instr, stderr);
3625          fprintf(stderr, "\n");
3626       }
3627       uint32_t offset = nir_instr_as_load_const(off_instr)->value[0].u32;
3628
3629       Temp vertex_buffers = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->vertex_buffers));
3630
3631       unsigned location = nir_intrinsic_base(instr) / 4 - VERT_ATTRIB_GENERIC0 + offset;
3632       unsigned component = nir_intrinsic_component(instr);
3633       unsigned attrib_binding = ctx->options->key.vs.vertex_attribute_bindings[location];
3634       uint32_t attrib_offset = ctx->options->key.vs.vertex_attribute_offsets[location];
3635       uint32_t attrib_stride = ctx->options->key.vs.vertex_attribute_strides[location];
3636       unsigned attrib_format = ctx->options->key.vs.vertex_attribute_formats[location];
3637
3638       unsigned dfmt = attrib_format & 0xf;
3639       unsigned nfmt = (attrib_format >> 4) & 0x7;
3640       const struct ac_data_format_info *vtx_info = ac_get_data_format_info(dfmt);
3641
3642       unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa) << component;
3643       unsigned num_channels = MIN2(util_last_bit(mask), vtx_info->num_channels);
3644       unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> (location * 2)) & 3;
3645       bool post_shuffle = ctx->options->key.vs.post_shuffle & (1 << location);
3646       if (post_shuffle)
3647          num_channels = MAX2(num_channels, 3);
3648
3649       Operand off = bld.copy(bld.def(s1), Operand(attrib_binding * 16u));
3650       Temp list = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), vertex_buffers, off);
3651
3652       Temp index;
3653       if (ctx->options->key.vs.instance_rate_inputs & (1u << location)) {
3654          uint32_t divisor = ctx->options->key.vs.instance_rate_divisors[location];
3655          Temp start_instance = get_arg(ctx, ctx->args->ac.start_instance);
3656          if (divisor) {
3657             Temp instance_id = get_arg(ctx, ctx->args->ac.instance_id);
3658             if (divisor != 1) {
3659                Temp divided = bld.tmp(v1);
3660                emit_v_div_u32(ctx, divided, as_vgpr(ctx, instance_id), divisor);
3661                index = bld.vadd32(bld.def(v1), start_instance, divided);
3662             } else {
3663                index = bld.vadd32(bld.def(v1), start_instance, instance_id);
3664             }
3665          } else {
3666             index = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), start_instance);
3667          }
3668       } else {
3669          index = bld.vadd32(bld.def(v1),
3670                             get_arg(ctx, ctx->args->ac.base_vertex),
3671                             get_arg(ctx, ctx->args->ac.vertex_id));
3672       }
3673
3674       Temp channels[num_channels];
3675       unsigned channel_start = 0;
3676       bool direct_fetch = false;
3677
3678       /* skip unused channels at the start */
3679       if (vtx_info->chan_byte_size && !post_shuffle) {
3680          channel_start = ffs(mask) - 1;
3681          for (unsigned i = 0; i < channel_start; i++)
3682             channels[i] = Temp(0, s1);
3683       } else if (vtx_info->chan_byte_size && post_shuffle && !(mask & 0x8)) {
3684          num_channels = 3 - (ffs(mask) - 1);
3685       }
3686
3687       /* load channels */
3688       while (channel_start < num_channels) {
3689          unsigned fetch_size = num_channels - channel_start;
3690          unsigned fetch_offset = attrib_offset + channel_start * vtx_info->chan_byte_size;
3691          bool expanded = false;
3692
3693          /* use MUBUF when possible to avoid possible alignment issues */
3694          /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
3695          bool use_mubuf = (nfmt == V_008F0C_BUF_NUM_FORMAT_FLOAT ||
3696                            nfmt == V_008F0C_BUF_NUM_FORMAT_UINT ||
3697                            nfmt == V_008F0C_BUF_NUM_FORMAT_SINT) &&
3698                           vtx_info->chan_byte_size == 4;
3699          unsigned fetch_dfmt = V_008F0C_BUF_DATA_FORMAT_INVALID;
3700          if (!use_mubuf) {
3701             fetch_dfmt = get_fetch_data_format(ctx, vtx_info, fetch_offset, attrib_stride, &fetch_size);
3702          } else {
3703             if (fetch_size == 3 && ctx->options->chip_class == GFX6) {
3704                /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
3705                fetch_size = 4;
3706                expanded = true;
3707             }
3708          }
3709
3710          Temp fetch_index = index;
3711          if (attrib_stride != 0 && fetch_offset > attrib_stride) {
3712             fetch_index = bld.vadd32(bld.def(v1), Operand(fetch_offset / attrib_stride), fetch_index);
3713             fetch_offset = fetch_offset % attrib_stride;
3714          }
3715
3716          Operand soffset(0u);
3717          if (fetch_offset >= 4096) {
3718             soffset = bld.copy(bld.def(s1), Operand(fetch_offset / 4096 * 4096));
3719             fetch_offset %= 4096;
3720          }
3721
3722          aco_opcode opcode;
3723          switch (fetch_size) {
3724          case 1:
3725             opcode = use_mubuf ? aco_opcode::buffer_load_dword : aco_opcode::tbuffer_load_format_x;
3726             break;
3727          case 2:
3728             opcode = use_mubuf ? aco_opcode::buffer_load_dwordx2 : aco_opcode::tbuffer_load_format_xy;
3729             break;
3730          case 3:
3731             assert(ctx->options->chip_class >= GFX7 ||
3732                    (!use_mubuf && ctx->options->chip_class == GFX6));
3733             opcode = use_mubuf ? aco_opcode::buffer_load_dwordx3 : aco_opcode::tbuffer_load_format_xyz;
3734             break;
3735          case 4:
3736             opcode = use_mubuf ? aco_opcode::buffer_load_dwordx4 : aco_opcode::tbuffer_load_format_xyzw;
3737             break;
3738          default:
3739             unreachable("Unimplemented load_input vector size");
3740          }
3741
3742          Temp fetch_dst;
3743          if (channel_start == 0 && fetch_size == dst.size() && !post_shuffle &&
3744              !expanded && (alpha_adjust == RADV_ALPHA_ADJUST_NONE ||
3745                            num_channels <= 3)) {
3746             direct_fetch = true;
3747             fetch_dst = dst;
3748          } else {
3749             fetch_dst = bld.tmp(RegType::vgpr, fetch_size);
3750          }
3751
3752          if (use_mubuf) {
3753             Instruction *mubuf = bld.mubuf(opcode,
3754                                            Definition(fetch_dst), list, fetch_index, soffset,
3755                                            fetch_offset, false, true).instr;
3756             static_cast<MUBUF_instruction*>(mubuf)->can_reorder = true;
3757          } else {
3758             Instruction *mtbuf = bld.mtbuf(opcode,
3759                                            Definition(fetch_dst), list, fetch_index, soffset,
3760                                            fetch_dfmt, nfmt, fetch_offset, false, true).instr;
3761             static_cast<MTBUF_instruction*>(mtbuf)->can_reorder = true;
3762          }
3763
3764          emit_split_vector(ctx, fetch_dst, fetch_dst.size());
3765
3766          if (fetch_size == 1) {
3767             channels[channel_start] = fetch_dst;
3768          } else {
3769             for (unsigned i = 0; i < MIN2(fetch_size, num_channels - channel_start); i++)
3770                channels[channel_start + i] = emit_extract_vector(ctx, fetch_dst, i, v1);
3771          }
3772
3773          channel_start += fetch_size;
3774       }
3775
3776       if (!direct_fetch) {
3777          bool is_float = nfmt != V_008F0C_BUF_NUM_FORMAT_UINT &&
3778                          nfmt != V_008F0C_BUF_NUM_FORMAT_SINT;
3779
3780          static const unsigned swizzle_normal[4] = {0, 1, 2, 3};
3781          static const unsigned swizzle_post_shuffle[4] = {2, 1, 0, 3};
3782          const unsigned *swizzle = post_shuffle ? swizzle_post_shuffle : swizzle_normal;
3783
3784          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
3785          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
3786          unsigned num_temp = 0;
3787          for (unsigned i = 0; i < dst.size(); i++) {
3788             unsigned idx = i + component;
3789             if (swizzle[idx] < num_channels && channels[swizzle[idx]].id()) {
3790                Temp channel = channels[swizzle[idx]];
3791                if (idx == 3 && alpha_adjust != RADV_ALPHA_ADJUST_NONE)
3792                   channel = adjust_vertex_fetch_alpha(ctx, alpha_adjust, channel);
3793                vec->operands[i] = Operand(channel);
3794
3795                num_temp++;
3796                elems[i] = channel;
3797             } else if (is_float && idx == 3) {
3798                vec->operands[i] = Operand(0x3f800000u);
3799             } else if (!is_float && idx == 3) {
3800                vec->operands[i] = Operand(1u);
3801             } else {
3802                vec->operands[i] = Operand(0u);
3803             }
3804          }
3805          vec->definitions[0] = Definition(dst);
3806          ctx->block->instructions.emplace_back(std::move(vec));
3807          emit_split_vector(ctx, dst, dst.size());
3808
3809          if (num_temp == dst.size())
3810             ctx->allocated_vec.emplace(dst.id(), elems);
3811       }
3812    } else if (ctx->shader->info.stage == MESA_SHADER_FRAGMENT) {
3813       unsigned offset_idx = instr->intrinsic == nir_intrinsic_load_input ? 0 : 1;
3814       nir_instr *off_instr = instr->src[offset_idx].ssa->parent_instr;
3815       if (off_instr->type != nir_instr_type_load_const ||
3816           nir_instr_as_load_const(off_instr)->value[0].u32 != 0) {
3817          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
3818          nir_print_instr(off_instr, stderr);
3819          fprintf(stderr, "\n");
3820       }
3821
3822       Temp prim_mask = get_arg(ctx, ctx->args->ac.prim_mask);
3823       nir_const_value* offset = nir_src_as_const_value(instr->src[offset_idx]);
3824       if (offset) {
3825          assert(offset->u32 == 0);
3826       } else {
3827          /* the lower 15bit of the prim_mask contain the offset into LDS
3828           * while the upper bits contain the number of prims */
3829          Temp offset_src = get_ssa_temp(ctx, instr->src[offset_idx].ssa);
3830          assert(offset_src.regClass() == s1 && "TODO: divergent offsets...");
3831          Builder bld(ctx->program, ctx->block);
3832          Temp stride = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), prim_mask, Operand(16u));
3833          stride = bld.sop1(aco_opcode::s_bcnt1_i32_b32, bld.def(s1), bld.def(s1, scc), stride);
3834          stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, Operand(48u));
3835          offset_src = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, offset_src);
3836          prim_mask = bld.sop2(aco_opcode::s_add_i32, bld.def(s1, m0), bld.def(s1, scc), offset_src, prim_mask);
3837       }
3838
3839       unsigned idx = nir_intrinsic_base(instr);
3840       unsigned component = nir_intrinsic_component(instr);
3841       unsigned vertex_id = 2; /* P0 */
3842
3843       if (instr->intrinsic == nir_intrinsic_load_input_vertex) {
3844          nir_const_value* src0 = nir_src_as_const_value(instr->src[0]);
3845          switch (src0->u32) {
3846          case 0:
3847             vertex_id = 2; /* P0 */
3848             break;
3849          case 1:
3850             vertex_id = 0; /* P10 */
3851             break;
3852          case 2:
3853             vertex_id = 1; /* P20 */
3854             break;
3855          default:
3856             unreachable("invalid vertex index");
3857          }
3858       }
3859
3860       if (dst.size() == 1) {
3861          bld.vintrp(aco_opcode::v_interp_mov_f32, Definition(dst), Operand(vertex_id), bld.m0(prim_mask), idx, component);
3862       } else {
3863          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
3864          for (unsigned i = 0; i < dst.size(); i++)
3865             vec->operands[i] = bld.vintrp(aco_opcode::v_interp_mov_f32, bld.def(v1), Operand(vertex_id), bld.m0(prim_mask), idx, component + i);
3866          vec->definitions[0] = Definition(dst);
3867          bld.insert(std::move(vec));
3868       }
3869
3870    } else if (ctx->shader->info.stage == MESA_SHADER_TESS_EVAL) {
3871       Temp ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_HS_TESS_OFFCHIP * 16u));
3872       Temp soffset = get_arg(ctx, ctx->args->oc_lds);
3873       std::pair<Temp, unsigned> offs = get_tcs_per_patch_output_vmem_offset(ctx, instr);
3874       unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8u;
3875
3876       load_vmem_mubuf(ctx, dst, ring, offs.first, soffset, offs.second, elem_size_bytes, instr->dest.ssa.num_components);
3877    } else {
3878       unreachable("Shader stage not implemented");
3879    }
3880 }
3881
3882 std::pair<Temp, unsigned> get_gs_per_vertex_input_offset(isel_context *ctx, nir_intrinsic_instr *instr, unsigned base_stride = 1u)
3883 {
3884    assert(ctx->shader->info.stage == MESA_SHADER_GEOMETRY);
3885
3886    Builder bld(ctx->program, ctx->block);
3887    nir_src *vertex_src = nir_get_io_vertex_index_src(instr);
3888    Temp vertex_offset;
3889
3890    if (!nir_src_is_const(*vertex_src)) {
3891       /* better code could be created, but this case probably doesn't happen
3892        * much in practice */
3893       Temp indirect_vertex = as_vgpr(ctx, get_ssa_temp(ctx, vertex_src->ssa));
3894       for (unsigned i = 0; i < ctx->shader->info.gs.vertices_in; i++) {
3895          Temp elem;
3896
3897          if (ctx->stage == vertex_geometry_gs || ctx->stage == tess_eval_geometry_gs) {
3898             elem = get_arg(ctx, ctx->args->gs_vtx_offset[i / 2u * 2u]);
3899             if (i % 2u)
3900                elem = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(16u), elem);
3901          } else {
3902             elem = get_arg(ctx, ctx->args->gs_vtx_offset[i]);
3903          }
3904
3905          if (vertex_offset.id()) {
3906             Temp cond = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.hint_vcc(bld.def(bld.lm)),
3907                                  Operand(i), indirect_vertex);
3908             vertex_offset = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), vertex_offset, elem, cond);
3909          } else {
3910             vertex_offset = elem;
3911          }
3912       }
3913
3914       if (ctx->stage == vertex_geometry_gs || ctx->stage == tess_eval_geometry_gs)
3915          vertex_offset = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0xffffu), vertex_offset);
3916    } else {
3917       unsigned vertex = nir_src_as_uint(*vertex_src);
3918       if (ctx->stage == vertex_geometry_gs || ctx->stage == tess_eval_geometry_gs)
3919          vertex_offset = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1),
3920                                   get_arg(ctx, ctx->args->gs_vtx_offset[vertex / 2u * 2u]),
3921                                   Operand((vertex % 2u) * 16u), Operand(16u));
3922       else
3923          vertex_offset = get_arg(ctx, ctx->args->gs_vtx_offset[vertex]);
3924    }
3925
3926    std::pair<Temp, unsigned> offs = get_intrinsic_io_basic_offset(ctx, instr, base_stride);
3927    offs = offset_add(ctx, offs, std::make_pair(vertex_offset, 0u));
3928    return offset_mul(ctx, offs, 4u);
3929 }
3930
3931 void visit_load_gs_per_vertex_input(isel_context *ctx, nir_intrinsic_instr *instr)
3932 {
3933    assert(ctx->shader->info.stage == MESA_SHADER_GEOMETRY);
3934
3935    Builder bld(ctx->program, ctx->block);
3936    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3937    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
3938
3939    if (ctx->stage == geometry_gs) {
3940       std::pair<Temp, unsigned> offs = get_gs_per_vertex_input_offset(ctx, instr, ctx->program->wave_size);
3941       Temp ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_ESGS_GS * 16u));
3942       load_vmem_mubuf(ctx, dst, ring, offs.first, Temp(), offs.second, elem_size_bytes, instr->dest.ssa.num_components, 4u * ctx->program->wave_size, false, true);
3943    } else if (ctx->stage == vertex_geometry_gs || ctx->stage == tess_eval_geometry_gs) {
3944       std::pair<Temp, unsigned> offs = get_gs_per_vertex_input_offset(ctx, instr);
3945       unsigned lds_align = calculate_lds_alignment(ctx, offs.second);
3946       load_lds(ctx, elem_size_bytes, dst, offs.first, offs.second, lds_align);
3947    } else {
3948       unreachable("Unsupported GS stage.");
3949    }
3950 }
3951
3952 void visit_load_tcs_per_vertex_input(isel_context *ctx, nir_intrinsic_instr *instr)
3953 {
3954    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
3955
3956    Builder bld(ctx->program, ctx->block);
3957    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3958    std::pair<Temp, unsigned> offs = get_tcs_per_vertex_input_lds_offset(ctx, instr);
3959    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
3960    unsigned lds_align = calculate_lds_alignment(ctx, offs.second);
3961
3962    load_lds(ctx, elem_size_bytes, dst, offs.first, offs.second, lds_align);
3963 }
3964
3965 void visit_load_tes_per_vertex_input(isel_context *ctx, nir_intrinsic_instr *instr)
3966 {
3967    assert(ctx->shader->info.stage == MESA_SHADER_TESS_EVAL);
3968
3969    Builder bld(ctx->program, ctx->block);
3970
3971    Temp ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_HS_TESS_OFFCHIP * 16u));
3972    Temp oc_lds = get_arg(ctx, ctx->args->oc_lds);
3973    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3974
3975    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
3976    std::pair<Temp, unsigned> offs = get_tcs_per_vertex_output_vmem_offset(ctx, instr);
3977
3978    load_vmem_mubuf(ctx, dst, ring, offs.first, oc_lds, offs.second, elem_size_bytes, instr->dest.ssa.num_components, 0u, true, true);
3979 }
3980
3981 void visit_load_per_vertex_input(isel_context *ctx, nir_intrinsic_instr *instr)
3982 {
3983    switch (ctx->shader->info.stage) {
3984    case MESA_SHADER_GEOMETRY:
3985       visit_load_gs_per_vertex_input(ctx, instr);
3986       break;
3987    case MESA_SHADER_TESS_CTRL:
3988       visit_load_tcs_per_vertex_input(ctx, instr);
3989       break;
3990    case MESA_SHADER_TESS_EVAL:
3991       visit_load_tes_per_vertex_input(ctx, instr);
3992       break;
3993    default:
3994       unreachable("Unimplemented shader stage");
3995    }
3996 }
3997
3998 void visit_load_per_vertex_output(isel_context *ctx, nir_intrinsic_instr *instr)
3999 {
4000    visit_load_tcs_output(ctx, instr, true);
4001 }
4002
4003 void visit_store_per_vertex_output(isel_context *ctx, nir_intrinsic_instr *instr)
4004 {
4005    assert(ctx->stage == tess_control_hs || ctx->stage == vertex_tess_control_hs);
4006    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
4007
4008    visit_store_tcs_output(ctx, instr, true);
4009 }
4010
4011 void visit_load_tess_coord(isel_context *ctx, nir_intrinsic_instr *instr)
4012 {
4013    assert(ctx->shader->info.stage == MESA_SHADER_TESS_EVAL);
4014
4015    Builder bld(ctx->program, ctx->block);
4016    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4017
4018    Operand tes_u(get_arg(ctx, ctx->args->tes_u));
4019    Operand tes_v(get_arg(ctx, ctx->args->tes_v));
4020    Operand tes_w(0u);
4021
4022    if (ctx->shader->info.tess.primitive_mode == GL_TRIANGLES) {
4023       Temp tmp = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), tes_u, tes_v);
4024       tmp = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), Operand(0x3f800000u /* 1.0f */), tmp);
4025       tes_w = Operand(tmp);
4026    }
4027
4028    Temp tess_coord = bld.pseudo(aco_opcode::p_create_vector, Definition(dst), tes_u, tes_v, tes_w);
4029    emit_split_vector(ctx, tess_coord, 3);
4030 }
4031
4032 Temp load_desc_ptr(isel_context *ctx, unsigned desc_set)
4033 {
4034    if (ctx->program->info->need_indirect_descriptor_sets) {
4035       Builder bld(ctx->program, ctx->block);
4036       Temp ptr64 = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->descriptor_sets[0]));
4037       Operand off = bld.copy(bld.def(s1), Operand(desc_set << 2));
4038       return bld.smem(aco_opcode::s_load_dword, bld.def(s1), ptr64, off);//, false, false, false);
4039    }
4040
4041    return get_arg(ctx, ctx->args->descriptor_sets[desc_set]);
4042 }
4043
4044
4045 void visit_load_resource(isel_context *ctx, nir_intrinsic_instr *instr)
4046 {
4047    Builder bld(ctx->program, ctx->block);
4048    Temp index = get_ssa_temp(ctx, instr->src[0].ssa);
4049    if (!ctx->divergent_vals[instr->dest.ssa.index])
4050       index = bld.as_uniform(index);
4051    unsigned desc_set = nir_intrinsic_desc_set(instr);
4052    unsigned binding = nir_intrinsic_binding(instr);
4053
4054    Temp desc_ptr;
4055    radv_pipeline_layout *pipeline_layout = ctx->options->layout;
4056    radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
4057    unsigned offset = layout->binding[binding].offset;
4058    unsigned stride;
4059    if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
4060        layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
4061       unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start + layout->binding[binding].dynamic_offset_offset;
4062       desc_ptr = get_arg(ctx, ctx->args->ac.push_constants);
4063       offset = pipeline_layout->push_constant_size + 16 * idx;
4064       stride = 16;
4065    } else {
4066       desc_ptr = load_desc_ptr(ctx, desc_set);
4067       stride = layout->binding[binding].size;
4068    }
4069
4070    nir_const_value* nir_const_index = nir_src_as_const_value(instr->src[0]);
4071    unsigned const_index = nir_const_index ? nir_const_index->u32 : 0;
4072    if (stride != 1) {
4073       if (nir_const_index) {
4074          const_index = const_index * stride;
4075       } else if (index.type() == RegType::vgpr) {
4076          bool index24bit = layout->binding[binding].array_size <= 0x1000000;
4077          index = bld.v_mul_imm(bld.def(v1), index, stride, index24bit);
4078       } else {
4079          index = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), Operand(index));
4080       }
4081    }
4082    if (offset) {
4083       if (nir_const_index) {
4084          const_index = const_index + offset;
4085       } else if (index.type() == RegType::vgpr) {
4086          index = bld.vadd32(bld.def(v1), Operand(offset), index);
4087       } else {
4088          index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset), Operand(index));
4089       }
4090    }
4091
4092    if (nir_const_index && const_index == 0) {
4093       index = desc_ptr;
4094    } else if (index.type() == RegType::vgpr) {
4095       index = bld.vadd32(bld.def(v1),
4096                          nir_const_index ? Operand(const_index) : Operand(index),
4097                          Operand(desc_ptr));
4098    } else {
4099       index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
4100                        nir_const_index ? Operand(const_index) : Operand(index),
4101                        Operand(desc_ptr));
4102    }
4103
4104    bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), index);
4105 }
4106
4107 void load_buffer(isel_context *ctx, unsigned num_components, Temp dst,
4108                  Temp rsrc, Temp offset, bool glc=false, bool readonly=true)
4109 {
4110    Builder bld(ctx->program, ctx->block);
4111
4112    unsigned num_bytes = dst.size() * 4;
4113    bool dlc = glc && ctx->options->chip_class >= GFX10;
4114
4115    aco_opcode op;
4116    if (dst.type() == RegType::vgpr || (ctx->options->chip_class < GFX8 && !readonly)) {
4117       Operand vaddr = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
4118       Operand soffset = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
4119       unsigned const_offset = 0;
4120
4121       Temp lower = Temp();
4122       if (num_bytes > 16) {
4123          assert(num_components == 3 || num_components == 4);
4124          op = aco_opcode::buffer_load_dwordx4;
4125          lower = bld.tmp(v4);
4126          aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
4127          mubuf->definitions[0] = Definition(lower);
4128          mubuf->operands[0] = Operand(rsrc);
4129          mubuf->operands[1] = vaddr;
4130          mubuf->operands[2] = soffset;
4131          mubuf->offen = (offset.type() == RegType::vgpr);
4132          mubuf->glc = glc;
4133          mubuf->dlc = dlc;
4134          mubuf->barrier = readonly ? barrier_none : barrier_buffer;
4135          mubuf->can_reorder = readonly;
4136          bld.insert(std::move(mubuf));
4137          emit_split_vector(ctx, lower, 2);
4138          num_bytes -= 16;
4139          const_offset = 16;
4140       } else if (num_bytes == 12 && ctx->options->chip_class == GFX6) {
4141          /* GFX6 doesn't support loading vec3, expand to vec4. */
4142          num_bytes = 16;
4143       }
4144
4145       switch (num_bytes) {
4146          case 4:
4147             op = aco_opcode::buffer_load_dword;
4148             break;
4149          case 8:
4150             op = aco_opcode::buffer_load_dwordx2;
4151             break;
4152          case 12:
4153             assert(ctx->options->chip_class > GFX6);
4154             op = aco_opcode::buffer_load_dwordx3;
4155             break;
4156          case 16:
4157             op = aco_opcode::buffer_load_dwordx4;
4158             break;
4159          default:
4160             unreachable("Load SSBO not implemented for this size.");
4161       }
4162       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
4163       mubuf->operands[0] = Operand(rsrc);
4164       mubuf->operands[1] = vaddr;
4165       mubuf->operands[2] = soffset;
4166       mubuf->offen = (offset.type() == RegType::vgpr);
4167       mubuf->glc = glc;
4168       mubuf->dlc = dlc;
4169       mubuf->barrier = readonly ? barrier_none : barrier_buffer;
4170       mubuf->can_reorder = readonly;
4171       mubuf->offset = const_offset;
4172       aco_ptr<Instruction> instr = std::move(mubuf);
4173
4174       if (dst.size() > 4) {
4175          assert(lower != Temp());
4176          Temp upper = bld.tmp(RegType::vgpr, dst.size() - lower.size());
4177          instr->definitions[0] = Definition(upper);
4178          bld.insert(std::move(instr));
4179          if (dst.size() == 8)
4180             emit_split_vector(ctx, upper, 2);
4181          instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size() / 2, 1));
4182          instr->operands[0] = Operand(emit_extract_vector(ctx, lower, 0, v2));
4183          instr->operands[1] = Operand(emit_extract_vector(ctx, lower, 1, v2));
4184          instr->operands[2] = Operand(emit_extract_vector(ctx, upper, 0, v2));
4185          if (dst.size() == 8)
4186             instr->operands[3] = Operand(emit_extract_vector(ctx, upper, 1, v2));
4187       } else if (dst.size() == 3 && ctx->options->chip_class == GFX6) {
4188          Temp vec = bld.tmp(v4);
4189          instr->definitions[0] = Definition(vec);
4190          bld.insert(std::move(instr));
4191          emit_split_vector(ctx, vec, 4);
4192
4193          instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, 3, 1));
4194          instr->operands[0] = Operand(emit_extract_vector(ctx, vec, 0, v1));
4195          instr->operands[1] = Operand(emit_extract_vector(ctx, vec, 1, v1));
4196          instr->operands[2] = Operand(emit_extract_vector(ctx, vec, 2, v1));
4197       }
4198
4199       if (dst.type() == RegType::sgpr) {
4200          Temp vec = bld.tmp(RegType::vgpr, dst.size());
4201          instr->definitions[0] = Definition(vec);
4202          bld.insert(std::move(instr));
4203          expand_vector(ctx, vec, dst, num_components, (1 << num_components) - 1);
4204       } else {
4205          instr->definitions[0] = Definition(dst);
4206          bld.insert(std::move(instr));
4207          emit_split_vector(ctx, dst, num_components);
4208       }
4209    } else {
4210       switch (num_bytes) {
4211          case 4:
4212             op = aco_opcode::s_buffer_load_dword;
4213             break;
4214          case 8:
4215             op = aco_opcode::s_buffer_load_dwordx2;
4216             break;
4217          case 12:
4218          case 16:
4219             op = aco_opcode::s_buffer_load_dwordx4;
4220             break;
4221          case 24:
4222          case 32:
4223             op = aco_opcode::s_buffer_load_dwordx8;
4224             break;
4225          default:
4226             unreachable("Load SSBO not implemented for this size.");
4227       }
4228       aco_ptr<SMEM_instruction> load{create_instruction<SMEM_instruction>(op, Format::SMEM, 2, 1)};
4229       load->operands[0] = Operand(rsrc);
4230       load->operands[1] = Operand(bld.as_uniform(offset));
4231       assert(load->operands[1].getTemp().type() == RegType::sgpr);
4232       load->definitions[0] = Definition(dst);
4233       load->glc = glc;
4234       load->dlc = dlc;
4235       load->barrier = readonly ? barrier_none : barrier_buffer;
4236       load->can_reorder = false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
4237       assert(ctx->options->chip_class >= GFX8 || !glc);
4238
4239       /* trim vector */
4240       if (dst.size() == 3) {
4241          Temp vec = bld.tmp(s4);
4242          load->definitions[0] = Definition(vec);
4243          bld.insert(std::move(load));
4244          emit_split_vector(ctx, vec, 4);
4245
4246          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4247                     emit_extract_vector(ctx, vec, 0, s1),
4248                     emit_extract_vector(ctx, vec, 1, s1),
4249                     emit_extract_vector(ctx, vec, 2, s1));
4250       } else if (dst.size() == 6) {
4251          Temp vec = bld.tmp(s8);
4252          load->definitions[0] = Definition(vec);
4253          bld.insert(std::move(load));
4254          emit_split_vector(ctx, vec, 4);
4255
4256          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4257                     emit_extract_vector(ctx, vec, 0, s2),
4258                     emit_extract_vector(ctx, vec, 1, s2),
4259                     emit_extract_vector(ctx, vec, 2, s2));
4260       } else {
4261          bld.insert(std::move(load));
4262       }
4263       emit_split_vector(ctx, dst, num_components);
4264    }
4265 }
4266
4267 void visit_load_ubo(isel_context *ctx, nir_intrinsic_instr *instr)
4268 {
4269    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4270    Temp rsrc = get_ssa_temp(ctx, instr->src[0].ssa);
4271
4272    Builder bld(ctx->program, ctx->block);
4273
4274    nir_intrinsic_instr* idx_instr = nir_instr_as_intrinsic(instr->src[0].ssa->parent_instr);
4275    unsigned desc_set = nir_intrinsic_desc_set(idx_instr);
4276    unsigned binding = nir_intrinsic_binding(idx_instr);
4277    radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
4278
4279    if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
4280       uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
4281                            S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
4282                            S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
4283                            S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
4284       if (ctx->options->chip_class >= GFX10) {
4285          desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
4286                       S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
4287                       S_008F0C_RESOURCE_LEVEL(1);
4288       } else {
4289          desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
4290                       S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
4291       }
4292       Temp upper_dwords = bld.pseudo(aco_opcode::p_create_vector, bld.def(s3),
4293                                      Operand(S_008F04_BASE_ADDRESS_HI(ctx->options->address32_hi)),
4294                                      Operand(0xFFFFFFFFu),
4295                                      Operand(desc_type));
4296       rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
4297                         rsrc, upper_dwords);
4298    } else {
4299       rsrc = convert_pointer_to_64_bit(ctx, rsrc);
4300       rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
4301    }
4302
4303    load_buffer(ctx, instr->num_components, dst, rsrc, get_ssa_temp(ctx, instr->src[1].ssa));
4304 }
4305
4306 void visit_load_push_constant(isel_context *ctx, nir_intrinsic_instr *instr)
4307 {
4308    Builder bld(ctx->program, ctx->block);
4309    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4310
4311    unsigned offset = nir_intrinsic_base(instr);
4312    nir_const_value *index_cv = nir_src_as_const_value(instr->src[0]);
4313    if (index_cv && instr->dest.ssa.bit_size == 32) {
4314
4315       unsigned count = instr->dest.ssa.num_components;
4316       unsigned start = (offset + index_cv->u32) / 4u;
4317       start -= ctx->args->ac.base_inline_push_consts;
4318       if (start + count <= ctx->args->ac.num_inline_push_consts) {
4319          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
4320          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
4321          for (unsigned i = 0; i < count; ++i) {
4322             elems[i] = get_arg(ctx, ctx->args->ac.inline_push_consts[start + i]);
4323             vec->operands[i] = Operand{elems[i]};
4324          }
4325          vec->definitions[0] = Definition(dst);
4326          ctx->block->instructions.emplace_back(std::move(vec));
4327          ctx->allocated_vec.emplace(dst.id(), elems);
4328          return;
4329       }
4330    }
4331
4332    Temp index = bld.as_uniform(get_ssa_temp(ctx, instr->src[0].ssa));
4333    if (offset != 0) // TODO check if index != 0 as well
4334       index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset), index);
4335    Temp ptr = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->ac.push_constants));
4336    Temp vec = dst;
4337    bool trim = false;
4338    aco_opcode op;
4339
4340    switch (dst.size()) {
4341    case 1:
4342       op = aco_opcode::s_load_dword;
4343       break;
4344    case 2:
4345       op = aco_opcode::s_load_dwordx2;
4346       break;
4347    case 3:
4348       vec = bld.tmp(s4);
4349       trim = true;
4350    case 4:
4351       op = aco_opcode::s_load_dwordx4;
4352       break;
4353    case 6:
4354       vec = bld.tmp(s8);
4355       trim = true;
4356    case 8:
4357       op = aco_opcode::s_load_dwordx8;
4358       break;
4359    default:
4360       unreachable("unimplemented or forbidden load_push_constant.");
4361    }
4362
4363    bld.smem(op, Definition(vec), ptr, index);
4364
4365    if (trim) {
4366       emit_split_vector(ctx, vec, 4);
4367       RegClass rc = dst.size() == 3 ? s1 : s2;
4368       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4369                  emit_extract_vector(ctx, vec, 0, rc),
4370                  emit_extract_vector(ctx, vec, 1, rc),
4371                  emit_extract_vector(ctx, vec, 2, rc));
4372
4373    }
4374    emit_split_vector(ctx, dst, instr->dest.ssa.num_components);
4375 }
4376
4377 void visit_load_constant(isel_context *ctx, nir_intrinsic_instr *instr)
4378 {
4379    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4380
4381    Builder bld(ctx->program, ctx->block);
4382
4383    uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
4384                         S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
4385                         S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
4386                         S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
4387    if (ctx->options->chip_class >= GFX10) {
4388       desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
4389                    S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
4390                    S_008F0C_RESOURCE_LEVEL(1);
4391    } else {
4392       desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
4393                    S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
4394    }
4395
4396    unsigned base = nir_intrinsic_base(instr);
4397    unsigned range = nir_intrinsic_range(instr);
4398
4399    Temp offset = get_ssa_temp(ctx, instr->src[0].ssa);
4400    if (base && offset.type() == RegType::sgpr)
4401       offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), offset, Operand(base));
4402    else if (base && offset.type() == RegType::vgpr)
4403       offset = bld.vadd32(bld.def(v1), Operand(base), offset);
4404
4405    Temp rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
4406                           bld.sop1(aco_opcode::p_constaddr, bld.def(s2), bld.def(s1, scc), Operand(ctx->constant_data_offset)),
4407                           Operand(MIN2(base + range, ctx->shader->constant_data_size)),
4408                           Operand(desc_type));
4409
4410    load_buffer(ctx, instr->num_components, dst, rsrc, offset);
4411 }
4412
4413 void visit_discard_if(isel_context *ctx, nir_intrinsic_instr *instr)
4414 {
4415    if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
4416       ctx->cf_info.exec_potentially_empty_discard = true;
4417
4418    ctx->program->needs_exact = true;
4419
4420    // TODO: optimize uniform conditions
4421    Builder bld(ctx->program, ctx->block);
4422    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
4423    assert(src.regClass() == bld.lm);
4424    src = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
4425    bld.pseudo(aco_opcode::p_discard_if, src);
4426    ctx->block->kind |= block_kind_uses_discard_if;
4427    return;
4428 }
4429
4430 void visit_discard(isel_context* ctx, nir_intrinsic_instr *instr)
4431 {
4432    Builder bld(ctx->program, ctx->block);
4433
4434    if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
4435       ctx->cf_info.exec_potentially_empty_discard = true;
4436
4437    bool divergent = ctx->cf_info.parent_if.is_divergent ||
4438                     ctx->cf_info.parent_loop.has_divergent_continue;
4439
4440    if (ctx->block->loop_nest_depth &&
4441        ((nir_instr_is_last(&instr->instr) && !divergent) || divergent)) {
4442       /* we handle discards the same way as jump instructions */
4443       append_logical_end(ctx->block);
4444
4445       /* in loops, discard behaves like break */
4446       Block *linear_target = ctx->cf_info.parent_loop.exit;
4447       ctx->block->kind |= block_kind_discard;
4448
4449       if (!divergent) {
4450          /* uniform discard - loop ends here */
4451          assert(nir_instr_is_last(&instr->instr));
4452          ctx->block->kind |= block_kind_uniform;
4453          ctx->cf_info.has_branch = true;
4454          bld.branch(aco_opcode::p_branch);
4455          add_linear_edge(ctx->block->index, linear_target);
4456          return;
4457       }
4458
4459       /* we add a break right behind the discard() instructions */
4460       ctx->block->kind |= block_kind_break;
4461       unsigned idx = ctx->block->index;
4462
4463       /* remove critical edges from linear CFG */
4464       bld.branch(aco_opcode::p_branch);
4465       Block* break_block = ctx->program->create_and_insert_block();
4466       break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
4467       break_block->kind |= block_kind_uniform;
4468       add_linear_edge(idx, break_block);
4469       add_linear_edge(break_block->index, linear_target);
4470       bld.reset(break_block);
4471       bld.branch(aco_opcode::p_branch);
4472
4473       Block* continue_block = ctx->program->create_and_insert_block();
4474       continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
4475       add_linear_edge(idx, continue_block);
4476       append_logical_start(continue_block);
4477       ctx->block = continue_block;
4478
4479       return;
4480    }
4481
4482    /* it can currently happen that NIR doesn't remove the unreachable code */
4483    if (!nir_instr_is_last(&instr->instr)) {
4484       ctx->program->needs_exact = true;
4485       /* save exec somewhere temporarily so that it doesn't get
4486        * overwritten before the discard from outer exec masks */
4487       Temp cond = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), Operand(0xFFFFFFFF), Operand(exec, bld.lm));
4488       bld.pseudo(aco_opcode::p_discard_if, cond);
4489       ctx->block->kind |= block_kind_uses_discard_if;
4490       return;
4491    }
4492
4493    /* This condition is incorrect for uniformly branched discards in a loop
4494     * predicated by a divergent condition, but the above code catches that case
4495     * and the discard would end up turning into a discard_if.
4496     * For example:
4497     * if (divergent) {
4498     *    while (...) {
4499     *       if (uniform) {
4500     *          discard;
4501     *       }
4502     *    }
4503     * }
4504     */
4505    if (!ctx->cf_info.parent_if.is_divergent) {
4506       /* program just ends here */
4507       ctx->block->kind |= block_kind_uniform;
4508       bld.exp(aco_opcode::exp, Operand(v1), Operand(v1), Operand(v1), Operand(v1),
4509               0 /* enabled mask */, 9 /* dest */,
4510               false /* compressed */, true/* done */, true /* valid mask */);
4511       bld.sopp(aco_opcode::s_endpgm);
4512       // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
4513    } else {
4514       ctx->block->kind |= block_kind_discard;
4515       /* branch and linear edge is added by visit_if() */
4516    }
4517 }
4518
4519 enum aco_descriptor_type {
4520    ACO_DESC_IMAGE,
4521    ACO_DESC_FMASK,
4522    ACO_DESC_SAMPLER,
4523    ACO_DESC_BUFFER,
4524    ACO_DESC_PLANE_0,
4525    ACO_DESC_PLANE_1,
4526    ACO_DESC_PLANE_2,
4527 };
4528
4529 static bool
4530 should_declare_array(isel_context *ctx, enum glsl_sampler_dim sampler_dim, bool is_array) {
4531    if (sampler_dim == GLSL_SAMPLER_DIM_BUF)
4532       return false;
4533    ac_image_dim dim = ac_get_sampler_dim(ctx->options->chip_class, sampler_dim, is_array);
4534    return dim == ac_image_cube ||
4535           dim == ac_image_1darray ||
4536           dim == ac_image_2darray ||
4537           dim == ac_image_2darraymsaa;
4538 }
4539
4540 Temp get_sampler_desc(isel_context *ctx, nir_deref_instr *deref_instr,
4541                       enum aco_descriptor_type desc_type,
4542                       const nir_tex_instr *tex_instr, bool image, bool write)
4543 {
4544 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
4545    std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
4546    if (it != ctx->tex_desc.end())
4547       return it->second;
4548 */
4549    Temp index = Temp();
4550    bool index_set = false;
4551    unsigned constant_index = 0;
4552    unsigned descriptor_set;
4553    unsigned base_index;
4554    Builder bld(ctx->program, ctx->block);
4555
4556    if (!deref_instr) {
4557       assert(tex_instr && !image);
4558       descriptor_set = 0;
4559       base_index = tex_instr->sampler_index;
4560    } else {
4561       while(deref_instr->deref_type != nir_deref_type_var) {
4562          unsigned array_size = glsl_get_aoa_size(deref_instr->type);
4563          if (!array_size)
4564             array_size = 1;
4565
4566          assert(deref_instr->deref_type == nir_deref_type_array);
4567          nir_const_value *const_value = nir_src_as_const_value(deref_instr->arr.index);
4568          if (const_value) {
4569             constant_index += array_size * const_value->u32;
4570          } else {
4571             Temp indirect = get_ssa_temp(ctx, deref_instr->arr.index.ssa);
4572             if (indirect.type() == RegType::vgpr)
4573                indirect = bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), indirect);
4574
4575             if (array_size != 1)
4576                indirect = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(array_size), indirect);
4577
4578             if (!index_set) {
4579                index = indirect;
4580                index_set = true;
4581             } else {
4582                index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), index, indirect);
4583             }
4584          }
4585
4586          deref_instr = nir_src_as_deref(deref_instr->parent);
4587       }
4588       descriptor_set = deref_instr->var->data.descriptor_set;
4589       base_index = deref_instr->var->data.binding;
4590    }
4591
4592    Temp list = load_desc_ptr(ctx, descriptor_set);
4593    list = convert_pointer_to_64_bit(ctx, list);
4594
4595    struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4596    struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4597    unsigned offset = binding->offset;
4598    unsigned stride = binding->size;
4599    aco_opcode opcode;
4600    RegClass type;
4601
4602    assert(base_index < layout->binding_count);
4603
4604    switch (desc_type) {
4605    case ACO_DESC_IMAGE:
4606       type = s8;
4607       opcode = aco_opcode::s_load_dwordx8;
4608       break;
4609    case ACO_DESC_FMASK:
4610       type = s8;
4611       opcode = aco_opcode::s_load_dwordx8;
4612       offset += 32;
4613       break;
4614    case ACO_DESC_SAMPLER:
4615       type = s4;
4616       opcode = aco_opcode::s_load_dwordx4;
4617       if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4618          offset += radv_combined_image_descriptor_sampler_offset(binding);
4619       break;
4620    case ACO_DESC_BUFFER:
4621       type = s4;
4622       opcode = aco_opcode::s_load_dwordx4;
4623       break;
4624    case ACO_DESC_PLANE_0:
4625    case ACO_DESC_PLANE_1:
4626       type = s8;
4627       opcode = aco_opcode::s_load_dwordx8;
4628       offset += 32 * (desc_type - ACO_DESC_PLANE_0);
4629       break;
4630    case ACO_DESC_PLANE_2:
4631       type = s4;
4632       opcode = aco_opcode::s_load_dwordx4;
4633       offset += 64;
4634       break;
4635    default:
4636       unreachable("invalid desc_type\n");
4637    }
4638
4639    offset += constant_index * stride;
4640
4641    if (desc_type == ACO_DESC_SAMPLER && binding->immutable_samplers_offset &&
4642       (!index_set || binding->immutable_samplers_equal)) {
4643       if (binding->immutable_samplers_equal)
4644          constant_index = 0;
4645
4646       const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4647       return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
4648                         Operand(samplers[constant_index * 4 + 0]),
4649                         Operand(samplers[constant_index * 4 + 1]),
4650                         Operand(samplers[constant_index * 4 + 2]),
4651                         Operand(samplers[constant_index * 4 + 3]));
4652    }
4653
4654    Operand off;
4655    if (!index_set) {
4656       off = bld.copy(bld.def(s1), Operand(offset));
4657    } else {
4658       off = Operand((Temp)bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset),
4659                                    bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), index)));
4660    }
4661
4662    Temp res = bld.smem(opcode, bld.def(type), list, off);
4663
4664    if (desc_type == ACO_DESC_PLANE_2) {
4665       Temp components[8];
4666       for (unsigned i = 0; i < 8; i++)
4667          components[i] = bld.tmp(s1);
4668       bld.pseudo(aco_opcode::p_split_vector,
4669                  Definition(components[0]),
4670                  Definition(components[1]),
4671                  Definition(components[2]),
4672                  Definition(components[3]),
4673                  res);
4674
4675       Temp desc2 = get_sampler_desc(ctx, deref_instr, ACO_DESC_PLANE_1, tex_instr, image, write);
4676       bld.pseudo(aco_opcode::p_split_vector,
4677                  bld.def(s1), bld.def(s1), bld.def(s1), bld.def(s1),
4678                  Definition(components[4]),
4679                  Definition(components[5]),
4680                  Definition(components[6]),
4681                  Definition(components[7]),
4682                  desc2);
4683
4684       res = bld.pseudo(aco_opcode::p_create_vector, bld.def(s8),
4685                        components[0], components[1], components[2], components[3],
4686                        components[4], components[5], components[6], components[7]);
4687    }
4688
4689    return res;
4690 }
4691
4692 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
4693 {
4694    switch (dim) {
4695    case GLSL_SAMPLER_DIM_BUF:
4696       return 1;
4697    case GLSL_SAMPLER_DIM_1D:
4698       return array ? 2 : 1;
4699    case GLSL_SAMPLER_DIM_2D:
4700       return array ? 3 : 2;
4701    case GLSL_SAMPLER_DIM_MS:
4702       return array ? 4 : 3;
4703    case GLSL_SAMPLER_DIM_3D:
4704    case GLSL_SAMPLER_DIM_CUBE:
4705       return 3;
4706    case GLSL_SAMPLER_DIM_RECT:
4707    case GLSL_SAMPLER_DIM_SUBPASS:
4708       return 2;
4709    case GLSL_SAMPLER_DIM_SUBPASS_MS:
4710       return 3;
4711    default:
4712       break;
4713    }
4714    return 0;
4715 }
4716
4717
4718 /* Adjust the sample index according to FMASK.
4719  *
4720  * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4721  * which is the identity mapping. Each nibble says which physical sample
4722  * should be fetched to get that sample.
4723  *
4724  * For example, 0x11111100 means there are only 2 samples stored and
4725  * the second sample covers 3/4 of the pixel. When reading samples 0
4726  * and 1, return physical sample 0 (determined by the first two 0s
4727  * in FMASK), otherwise return physical sample 1.
4728  *
4729  * The sample index should be adjusted as follows:
4730  *   sample_index = (fmask >> (sample_index * 4)) & 0xF;
4731  */
4732 static Temp adjust_sample_index_using_fmask(isel_context *ctx, bool da, std::vector<Temp>& coords, Operand sample_index, Temp fmask_desc_ptr)
4733 {
4734    Builder bld(ctx->program, ctx->block);
4735    Temp fmask = bld.tmp(v1);
4736    unsigned dim = ctx->options->chip_class >= GFX10
4737                   ? ac_get_sampler_dim(ctx->options->chip_class, GLSL_SAMPLER_DIM_2D, da)
4738                   : 0;
4739
4740    Temp coord = da ? bld.pseudo(aco_opcode::p_create_vector, bld.def(v3), coords[0], coords[1], coords[2]) :
4741                      bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), coords[0], coords[1]);
4742    aco_ptr<MIMG_instruction> load{create_instruction<MIMG_instruction>(aco_opcode::image_load, Format::MIMG, 3, 1)};
4743    load->operands[0] = Operand(fmask_desc_ptr);
4744    load->operands[1] = Operand(s4); /* no sampler */
4745    load->operands[2] = Operand(coord);
4746    load->definitions[0] = Definition(fmask);
4747    load->glc = false;
4748    load->dlc = false;
4749    load->dmask = 0x1;
4750    load->unrm = true;
4751    load->da = da;
4752    load->dim = dim;
4753    load->can_reorder = true; /* fmask images shouldn't be modified */
4754    ctx->block->instructions.emplace_back(std::move(load));
4755
4756    Operand sample_index4;
4757    if (sample_index.isConstant() && sample_index.constantValue() < 16) {
4758       sample_index4 = Operand(sample_index.constantValue() << 2);
4759    } else if (sample_index.regClass() == s1) {
4760       sample_index4 = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), sample_index, Operand(2u));
4761    } else {
4762       assert(sample_index.regClass() == v1);
4763       sample_index4 = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), sample_index);
4764    }
4765
4766    Temp final_sample;
4767    if (sample_index4.isConstant() && sample_index4.constantValue() == 0)
4768       final_sample = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(15u), fmask);
4769    else if (sample_index4.isConstant() && sample_index4.constantValue() == 28)
4770       final_sample = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(28u), fmask);
4771    else
4772       final_sample = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1), fmask, sample_index4, Operand(4u));
4773
4774    /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4775     * resource descriptor is 0 (invalid),
4776     */
4777    Temp compare = bld.tmp(bld.lm);
4778    bld.vopc_e64(aco_opcode::v_cmp_lg_u32, Definition(compare),
4779                 Operand(0u), emit_extract_vector(ctx, fmask_desc_ptr, 1, s1)).def(0).setHint(vcc);
4780
4781    Temp sample_index_v = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), sample_index);
4782
4783    /* Replace the MSAA sample index. */
4784    return bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), sample_index_v, final_sample, compare);
4785 }
4786
4787 static Temp get_image_coords(isel_context *ctx, const nir_intrinsic_instr *instr, const struct glsl_type *type)
4788 {
4789
4790    Temp src0 = get_ssa_temp(ctx, instr->src[1].ssa);
4791    enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4792    bool is_array = glsl_sampler_type_is_array(type);
4793    ASSERTED bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS || dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
4794    assert(!add_frag_pos && "Input attachments should be lowered.");
4795    bool is_ms = (dim == GLSL_SAMPLER_DIM_MS || dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
4796    bool gfx9_1d = ctx->options->chip_class == GFX9 && dim == GLSL_SAMPLER_DIM_1D;
4797    int count = image_type_to_components_count(dim, is_array);
4798    std::vector<Temp> coords(count);
4799    Builder bld(ctx->program, ctx->block);
4800
4801    if (is_ms) {
4802       count--;
4803       Temp src2 = get_ssa_temp(ctx, instr->src[2].ssa);
4804       /* get sample index */
4805       if (instr->intrinsic == nir_intrinsic_image_deref_load) {
4806          nir_const_value *sample_cv = nir_src_as_const_value(instr->src[2]);
4807          Operand sample_index = sample_cv ? Operand(sample_cv->u32) : Operand(emit_extract_vector(ctx, src2, 0, v1));
4808          std::vector<Temp> fmask_load_address;
4809          for (unsigned i = 0; i < (is_array ? 3 : 2); i++)
4810             fmask_load_address.emplace_back(emit_extract_vector(ctx, src0, i, v1));
4811
4812          Temp fmask_desc_ptr = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_FMASK, nullptr, false, false);
4813          coords[count] = adjust_sample_index_using_fmask(ctx, is_array, fmask_load_address, sample_index, fmask_desc_ptr);
4814       } else {
4815          coords[count] = emit_extract_vector(ctx, src2, 0, v1);
4816       }
4817    }
4818
4819    if (gfx9_1d) {
4820       coords[0] = emit_extract_vector(ctx, src0, 0, v1);
4821       coords.resize(coords.size() + 1);
4822       coords[1] = bld.copy(bld.def(v1), Operand(0u));
4823       if (is_array)
4824          coords[2] = emit_extract_vector(ctx, src0, 1, v1);
4825    } else {
4826       for (int i = 0; i < count; i++)
4827          coords[i] = emit_extract_vector(ctx, src0, i, v1);
4828    }
4829
4830    if (instr->intrinsic == nir_intrinsic_image_deref_load ||
4831        instr->intrinsic == nir_intrinsic_image_deref_store) {
4832       int lod_index = instr->intrinsic == nir_intrinsic_image_deref_load ? 3 : 4;
4833       bool level_zero = nir_src_is_const(instr->src[lod_index]) && nir_src_as_uint(instr->src[lod_index]) == 0;
4834
4835       if (!level_zero)
4836          coords.emplace_back(get_ssa_temp(ctx, instr->src[lod_index].ssa));
4837    }
4838
4839    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, coords.size(), 1)};
4840    for (unsigned i = 0; i < coords.size(); i++)
4841       vec->operands[i] = Operand(coords[i]);
4842    Temp res = {ctx->program->allocateId(), RegClass(RegType::vgpr, coords.size())};
4843    vec->definitions[0] = Definition(res);
4844    ctx->block->instructions.emplace_back(std::move(vec));
4845    return res;
4846 }
4847
4848
4849 void visit_image_load(isel_context *ctx, nir_intrinsic_instr *instr)
4850 {
4851    Builder bld(ctx->program, ctx->block);
4852    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4853    const struct glsl_type *type = glsl_without_array(var->type);
4854    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4855    bool is_array = glsl_sampler_type_is_array(type);
4856    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4857
4858    if (dim == GLSL_SAMPLER_DIM_BUF) {
4859       unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
4860       unsigned num_channels = util_last_bit(mask);
4861       Temp rsrc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4862       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4863
4864       aco_opcode opcode;
4865       switch (num_channels) {
4866       case 1:
4867          opcode = aco_opcode::buffer_load_format_x;
4868          break;
4869       case 2:
4870          opcode = aco_opcode::buffer_load_format_xy;
4871          break;
4872       case 3:
4873          opcode = aco_opcode::buffer_load_format_xyz;
4874          break;
4875       case 4:
4876          opcode = aco_opcode::buffer_load_format_xyzw;
4877          break;
4878       default:
4879          unreachable(">4 channel buffer image load");
4880       }
4881       aco_ptr<MUBUF_instruction> load{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 3, 1)};
4882       load->operands[0] = Operand(rsrc);
4883       load->operands[1] = Operand(vindex);
4884       load->operands[2] = Operand((uint32_t) 0);
4885       Temp tmp;
4886       if (num_channels == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
4887          tmp = dst;
4888       else
4889          tmp = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_channels)};
4890       load->definitions[0] = Definition(tmp);
4891       load->idxen = true;
4892       load->glc = var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT);
4893       load->dlc = load->glc && ctx->options->chip_class >= GFX10;
4894       load->barrier = barrier_image;
4895       ctx->block->instructions.emplace_back(std::move(load));
4896
4897       expand_vector(ctx, tmp, dst, instr->dest.ssa.num_components, (1 << num_channels) - 1);
4898       return;
4899    }
4900
4901    Temp coords = get_image_coords(ctx, instr, type);
4902    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
4903
4904    unsigned dmask = nir_ssa_def_components_read(&instr->dest.ssa);
4905    unsigned num_components = util_bitcount(dmask);
4906    Temp tmp;
4907    if (num_components == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
4908       tmp = dst;
4909    else
4910       tmp = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_components)};
4911
4912    bool level_zero = nir_src_is_const(instr->src[3]) && nir_src_as_uint(instr->src[3]) == 0;
4913    aco_opcode opcode = level_zero ? aco_opcode::image_load : aco_opcode::image_load_mip;
4914
4915    aco_ptr<MIMG_instruction> load{create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 1)};
4916    load->operands[0] = Operand(resource);
4917    load->operands[1] = Operand(s4); /* no sampler */
4918    load->operands[2] = Operand(coords);
4919    load->definitions[0] = Definition(tmp);
4920    load->glc = var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT) ? 1 : 0;
4921    load->dlc = load->glc && ctx->options->chip_class >= GFX10;
4922    load->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4923    load->dmask = dmask;
4924    load->unrm = true;
4925    load->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
4926    load->barrier = barrier_image;
4927    ctx->block->instructions.emplace_back(std::move(load));
4928
4929    expand_vector(ctx, tmp, dst, instr->dest.ssa.num_components, dmask);
4930    return;
4931 }
4932
4933 void visit_image_store(isel_context *ctx, nir_intrinsic_instr *instr)
4934 {
4935    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4936    const struct glsl_type *type = glsl_without_array(var->type);
4937    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4938    bool is_array = glsl_sampler_type_is_array(type);
4939    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[3].ssa));
4940
4941    bool glc = ctx->options->chip_class == GFX6 || var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE) ? 1 : 0;
4942
4943    if (dim == GLSL_SAMPLER_DIM_BUF) {
4944       Temp rsrc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4945       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4946       aco_opcode opcode;
4947       switch (data.size()) {
4948       case 1:
4949          opcode = aco_opcode::buffer_store_format_x;
4950          break;
4951       case 2:
4952          opcode = aco_opcode::buffer_store_format_xy;
4953          break;
4954       case 3:
4955          opcode = aco_opcode::buffer_store_format_xyz;
4956          break;
4957       case 4:
4958          opcode = aco_opcode::buffer_store_format_xyzw;
4959          break;
4960       default:
4961          unreachable(">4 channel buffer image store");
4962       }
4963       aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 4, 0)};
4964       store->operands[0] = Operand(rsrc);
4965       store->operands[1] = Operand(vindex);
4966       store->operands[2] = Operand((uint32_t) 0);
4967       store->operands[3] = Operand(data);
4968       store->idxen = true;
4969       store->glc = glc;
4970       store->dlc = false;
4971       store->disable_wqm = true;
4972       store->barrier = barrier_image;
4973       ctx->program->needs_exact = true;
4974       ctx->block->instructions.emplace_back(std::move(store));
4975       return;
4976    }
4977
4978    assert(data.type() == RegType::vgpr);
4979    Temp coords = get_image_coords(ctx, instr, type);
4980    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
4981
4982    bool level_zero = nir_src_is_const(instr->src[4]) && nir_src_as_uint(instr->src[4]) == 0;
4983    aco_opcode opcode = level_zero ? aco_opcode::image_store : aco_opcode::image_store_mip;
4984
4985    aco_ptr<MIMG_instruction> store{create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 0)};
4986    store->operands[0] = Operand(resource);
4987    store->operands[1] = Operand(data);
4988    store->operands[2] = Operand(coords);
4989    store->glc = glc;
4990    store->dlc = false;
4991    store->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4992    store->dmask = (1 << data.size()) - 1;
4993    store->unrm = true;
4994    store->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
4995    store->disable_wqm = true;
4996    store->barrier = barrier_image;
4997    ctx->program->needs_exact = true;
4998    ctx->block->instructions.emplace_back(std::move(store));
4999    return;
5000 }
5001
5002 void visit_image_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
5003 {
5004    /* return the previous value if dest is ever used */
5005    bool return_previous = false;
5006    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
5007       return_previous = true;
5008       break;
5009    }
5010    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
5011       return_previous = true;
5012       break;
5013    }
5014
5015    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
5016    const struct glsl_type *type = glsl_without_array(var->type);
5017    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
5018    bool is_array = glsl_sampler_type_is_array(type);
5019    Builder bld(ctx->program, ctx->block);
5020
5021    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[3].ssa));
5022    assert(data.size() == 1 && "64bit ssbo atomics not yet implemented.");
5023
5024    if (instr->intrinsic == nir_intrinsic_image_deref_atomic_comp_swap)
5025       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), get_ssa_temp(ctx, instr->src[4].ssa), data);
5026
5027    aco_opcode buf_op, image_op;
5028    switch (instr->intrinsic) {
5029       case nir_intrinsic_image_deref_atomic_add:
5030          buf_op = aco_opcode::buffer_atomic_add;
5031          image_op = aco_opcode::image_atomic_add;
5032          break;
5033       case nir_intrinsic_image_deref_atomic_umin:
5034          buf_op = aco_opcode::buffer_atomic_umin;
5035          image_op = aco_opcode::image_atomic_umin;
5036          break;
5037       case nir_intrinsic_image_deref_atomic_imin:
5038          buf_op = aco_opcode::buffer_atomic_smin;
5039          image_op = aco_opcode::image_atomic_smin;
5040          break;
5041       case nir_intrinsic_image_deref_atomic_umax:
5042          buf_op = aco_opcode::buffer_atomic_umax;
5043          image_op = aco_opcode::image_atomic_umax;
5044          break;
5045       case nir_intrinsic_image_deref_atomic_imax:
5046          buf_op = aco_opcode::buffer_atomic_smax;
5047          image_op = aco_opcode::image_atomic_smax;
5048          break;
5049       case nir_intrinsic_image_deref_atomic_and:
5050          buf_op = aco_opcode::buffer_atomic_and;
5051          image_op = aco_opcode::image_atomic_and;
5052          break;
5053       case nir_intrinsic_image_deref_atomic_or:
5054          buf_op = aco_opcode::buffer_atomic_or;
5055          image_op = aco_opcode::image_atomic_or;
5056          break;
5057       case nir_intrinsic_image_deref_atomic_xor:
5058          buf_op = aco_opcode::buffer_atomic_xor;
5059          image_op = aco_opcode::image_atomic_xor;
5060          break;
5061       case nir_intrinsic_image_deref_atomic_exchange:
5062          buf_op = aco_opcode::buffer_atomic_swap;
5063          image_op = aco_opcode::image_atomic_swap;
5064          break;
5065       case nir_intrinsic_image_deref_atomic_comp_swap:
5066          buf_op = aco_opcode::buffer_atomic_cmpswap;
5067          image_op = aco_opcode::image_atomic_cmpswap;
5068          break;
5069       default:
5070          unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5071    }
5072
5073    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5074
5075    if (dim == GLSL_SAMPLER_DIM_BUF) {
5076       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
5077       Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
5078       //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5079       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(buf_op, Format::MUBUF, 4, return_previous ? 1 : 0)};
5080       mubuf->operands[0] = Operand(resource);
5081       mubuf->operands[1] = Operand(vindex);
5082       mubuf->operands[2] = Operand((uint32_t)0);
5083       mubuf->operands[3] = Operand(data);
5084       if (return_previous)
5085          mubuf->definitions[0] = Definition(dst);
5086       mubuf->offset = 0;
5087       mubuf->idxen = true;
5088       mubuf->glc = return_previous;
5089       mubuf->dlc = false; /* Not needed for atomics */
5090       mubuf->disable_wqm = true;
5091       mubuf->barrier = barrier_image;
5092       ctx->program->needs_exact = true;
5093       ctx->block->instructions.emplace_back(std::move(mubuf));
5094       return;
5095    }
5096
5097    Temp coords = get_image_coords(ctx, instr, type);
5098    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
5099    aco_ptr<MIMG_instruction> mimg{create_instruction<MIMG_instruction>(image_op, Format::MIMG, 3, return_previous ? 1 : 0)};
5100    mimg->operands[0] = Operand(resource);
5101    mimg->operands[1] = Operand(data);
5102    mimg->operands[2] = Operand(coords);
5103    if (return_previous)
5104       mimg->definitions[0] = Definition(dst);
5105    mimg->glc = return_previous;
5106    mimg->dlc = false; /* Not needed for atomics */
5107    mimg->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
5108    mimg->dmask = (1 << data.size()) - 1;
5109    mimg->unrm = true;
5110    mimg->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
5111    mimg->disable_wqm = true;
5112    mimg->barrier = barrier_image;
5113    ctx->program->needs_exact = true;
5114    ctx->block->instructions.emplace_back(std::move(mimg));
5115    return;
5116 }
5117
5118 void get_buffer_size(isel_context *ctx, Temp desc, Temp dst, bool in_elements)
5119 {
5120    if (in_elements && ctx->options->chip_class == GFX8) {
5121       /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
5122       Builder bld(ctx->program, ctx->block);
5123
5124       Temp size = emit_extract_vector(ctx, desc, 2, s1);
5125
5126       Temp size_div3 = bld.vop3(aco_opcode::v_mul_hi_u32, bld.def(v1), bld.copy(bld.def(v1), Operand(0xaaaaaaabu)), size);
5127       size_div3 = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.as_uniform(size_div3), Operand(1u));
5128
5129       Temp stride = emit_extract_vector(ctx, desc, 1, s1);
5130       stride = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), stride, Operand((5u << 16) | 16u));
5131
5132       Temp is12 = bld.sopc(aco_opcode::s_cmp_eq_i32, bld.def(s1, scc), stride, Operand(12u));
5133       size = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), size_div3, size, bld.scc(is12));
5134
5135       Temp shr_dst = dst.type() == RegType::vgpr ? bld.tmp(s1) : dst;
5136       bld.sop2(aco_opcode::s_lshr_b32, Definition(shr_dst), bld.def(s1, scc),
5137                size, bld.sop1(aco_opcode::s_ff1_i32_b32, bld.def(s1), stride));
5138       if (dst.type() == RegType::vgpr)
5139          bld.copy(Definition(dst), shr_dst);
5140
5141       /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
5142    } else {
5143       emit_extract_vector(ctx, desc, 2, dst);
5144    }
5145 }
5146
5147 void visit_image_size(isel_context *ctx, nir_intrinsic_instr *instr)
5148 {
5149    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
5150    const struct glsl_type *type = glsl_without_array(var->type);
5151    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
5152    bool is_array = glsl_sampler_type_is_array(type);
5153    Builder bld(ctx->program, ctx->block);
5154
5155    if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
5156       Temp desc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, NULL, true, false);
5157       return get_buffer_size(ctx, desc, get_ssa_temp(ctx, &instr->dest.ssa), true);
5158    }
5159
5160    /* LOD */
5161    Temp lod = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
5162
5163    /* Resource */
5164    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, NULL, true, false);
5165
5166    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5167
5168    aco_ptr<MIMG_instruction> mimg{create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 3, 1)};
5169    mimg->operands[0] = Operand(resource);
5170    mimg->operands[1] = Operand(s4); /* no sampler */
5171    mimg->operands[2] = Operand(lod);
5172    uint8_t& dmask = mimg->dmask;
5173    mimg->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
5174    mimg->dmask = (1 << instr->dest.ssa.num_components) - 1;
5175    mimg->da = glsl_sampler_type_is_array(type);
5176    mimg->can_reorder = true;
5177    Definition& def = mimg->definitions[0];
5178    ctx->block->instructions.emplace_back(std::move(mimg));
5179
5180    if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
5181        glsl_sampler_type_is_array(type)) {
5182
5183       assert(instr->dest.ssa.num_components == 3);
5184       Temp tmp = {ctx->program->allocateId(), v3};
5185       def = Definition(tmp);
5186       emit_split_vector(ctx, tmp, 3);
5187
5188       /* divide 3rd value by 6 by multiplying with magic number */
5189       Temp c = bld.copy(bld.def(s1), Operand((uint32_t) 0x2AAAAAAB));
5190       Temp by_6 = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), emit_extract_vector(ctx, tmp, 2, v1), c);
5191
5192       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
5193                  emit_extract_vector(ctx, tmp, 0, v1),
5194                  emit_extract_vector(ctx, tmp, 1, v1),
5195                  by_6);
5196
5197    } else if (ctx->options->chip_class == GFX9 &&
5198               glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
5199               glsl_sampler_type_is_array(type)) {
5200       assert(instr->dest.ssa.num_components == 2);
5201       def = Definition(dst);
5202       dmask = 0x5;
5203    } else {
5204       def = Definition(dst);
5205    }
5206
5207    emit_split_vector(ctx, dst, instr->dest.ssa.num_components);
5208 }
5209
5210 void visit_load_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
5211 {
5212    Builder bld(ctx->program, ctx->block);
5213    unsigned num_components = instr->num_components;
5214
5215    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5216    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5217    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
5218
5219    bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT);
5220    load_buffer(ctx, num_components, dst, rsrc, get_ssa_temp(ctx, instr->src[1].ssa), glc, false);
5221 }
5222
5223 void visit_store_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
5224 {
5225    Builder bld(ctx->program, ctx->block);
5226    Temp data = get_ssa_temp(ctx, instr->src[0].ssa);
5227    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
5228    unsigned writemask = nir_intrinsic_write_mask(instr);
5229    Temp offset = get_ssa_temp(ctx, instr->src[2].ssa);
5230
5231    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5232    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
5233
5234    bool smem = !ctx->divergent_vals[instr->src[2].ssa->index] &&
5235                ctx->options->chip_class >= GFX8;
5236    if (smem)
5237       offset = bld.as_uniform(offset);
5238    bool smem_nonfs = smem && ctx->stage != fragment_fs;
5239
5240    while (writemask) {
5241       int start, count;
5242       u_bit_scan_consecutive_range(&writemask, &start, &count);
5243       if (count == 3 && (smem || ctx->options->chip_class == GFX6)) {
5244          /* GFX6 doesn't support storing vec3, split it. */
5245          writemask |= 1u << (start + 2);
5246          count = 2;
5247       }
5248       int num_bytes = count * elem_size_bytes;
5249
5250       if (num_bytes > 16) {
5251          assert(elem_size_bytes == 8);
5252          writemask |= (((count - 2) << 1) - 1) << (start + 2);
5253          count = 2;
5254          num_bytes = 16;
5255       }
5256
5257       // TODO: check alignment of sub-dword stores
5258       // TODO: split 3 bytes. there is no store instruction for that
5259
5260       Temp write_data;
5261       if (count != instr->num_components) {
5262          emit_split_vector(ctx, data, instr->num_components);
5263          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
5264          for (int i = 0; i < count; i++) {
5265             Temp elem = emit_extract_vector(ctx, data, start + i, RegClass(data.type(), elem_size_bytes / 4));
5266             vec->operands[i] = Operand(smem_nonfs ? bld.as_uniform(elem) : elem);
5267          }
5268          write_data = bld.tmp(!smem ? RegType::vgpr : smem_nonfs ? RegType::sgpr : data.type(), count * elem_size_bytes / 4);
5269          vec->definitions[0] = Definition(write_data);
5270          ctx->block->instructions.emplace_back(std::move(vec));
5271       } else if (!smem && data.type() != RegType::vgpr) {
5272          assert(num_bytes % 4 == 0);
5273          write_data = bld.copy(bld.def(RegType::vgpr, num_bytes / 4), data);
5274       } else if (smem_nonfs && data.type() == RegType::vgpr) {
5275          assert(num_bytes % 4 == 0);
5276          write_data = bld.as_uniform(data);
5277       } else {
5278          write_data = data;
5279       }
5280
5281       aco_opcode vmem_op, smem_op;
5282       switch (num_bytes) {
5283          case 4:
5284             vmem_op = aco_opcode::buffer_store_dword;
5285             smem_op = aco_opcode::s_buffer_store_dword;
5286             break;
5287          case 8:
5288             vmem_op = aco_opcode::buffer_store_dwordx2;
5289             smem_op = aco_opcode::s_buffer_store_dwordx2;
5290             break;
5291          case 12:
5292             vmem_op = aco_opcode::buffer_store_dwordx3;
5293             smem_op = aco_opcode::last_opcode;
5294             assert(!smem && ctx->options->chip_class > GFX6);
5295             break;
5296          case 16:
5297             vmem_op = aco_opcode::buffer_store_dwordx4;
5298             smem_op = aco_opcode::s_buffer_store_dwordx4;
5299             break;
5300          default:
5301             unreachable("Store SSBO not implemented for this size.");
5302       }
5303       if (ctx->stage == fragment_fs)
5304          smem_op = aco_opcode::p_fs_buffer_store_smem;
5305
5306       if (smem) {
5307          aco_ptr<SMEM_instruction> store{create_instruction<SMEM_instruction>(smem_op, Format::SMEM, 3, 0)};
5308          store->operands[0] = Operand(rsrc);
5309          if (start) {
5310             Temp off = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
5311                                 offset, Operand(start * elem_size_bytes));
5312             store->operands[1] = Operand(off);
5313          } else {
5314             store->operands[1] = Operand(offset);
5315          }
5316          if (smem_op != aco_opcode::p_fs_buffer_store_smem)
5317             store->operands[1].setFixed(m0);
5318          store->operands[2] = Operand(write_data);
5319          store->glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
5320          store->dlc = false;
5321          store->disable_wqm = true;
5322          store->barrier = barrier_buffer;
5323          ctx->block->instructions.emplace_back(std::move(store));
5324          ctx->program->wb_smem_l1_on_end = true;
5325          if (smem_op == aco_opcode::p_fs_buffer_store_smem) {
5326             ctx->block->kind |= block_kind_needs_lowering;
5327             ctx->program->needs_exact = true;
5328          }
5329       } else {
5330          aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(vmem_op, Format::MUBUF, 4, 0)};
5331          store->operands[0] = Operand(rsrc);
5332          store->operands[1] = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
5333          store->operands[2] = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
5334          store->operands[3] = Operand(write_data);
5335          store->offset = start * elem_size_bytes;
5336          store->offen = (offset.type() == RegType::vgpr);
5337          store->glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
5338          store->dlc = false;
5339          store->disable_wqm = true;
5340          store->barrier = barrier_buffer;
5341          ctx->program->needs_exact = true;
5342          ctx->block->instructions.emplace_back(std::move(store));
5343       }
5344    }
5345 }
5346
5347 void visit_atomic_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
5348 {
5349    /* return the previous value if dest is ever used */
5350    bool return_previous = false;
5351    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
5352       return_previous = true;
5353       break;
5354    }
5355    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
5356       return_previous = true;
5357       break;
5358    }
5359
5360    Builder bld(ctx->program, ctx->block);
5361    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[2].ssa));
5362
5363    if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap)
5364       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(RegType::vgpr, data.size() * 2),
5365                         get_ssa_temp(ctx, instr->src[3].ssa), data);
5366
5367    Temp offset = get_ssa_temp(ctx, instr->src[1].ssa);
5368    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5369    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
5370
5371    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5372
5373    aco_opcode op32, op64;
5374    switch (instr->intrinsic) {
5375       case nir_intrinsic_ssbo_atomic_add:
5376          op32 = aco_opcode::buffer_atomic_add;
5377          op64 = aco_opcode::buffer_atomic_add_x2;
5378          break;
5379       case nir_intrinsic_ssbo_atomic_imin:
5380          op32 = aco_opcode::buffer_atomic_smin;
5381          op64 = aco_opcode::buffer_atomic_smin_x2;
5382          break;
5383       case nir_intrinsic_ssbo_atomic_umin:
5384          op32 = aco_opcode::buffer_atomic_umin;
5385          op64 = aco_opcode::buffer_atomic_umin_x2;
5386          break;
5387       case nir_intrinsic_ssbo_atomic_imax:
5388          op32 = aco_opcode::buffer_atomic_smax;
5389          op64 = aco_opcode::buffer_atomic_smax_x2;
5390          break;
5391       case nir_intrinsic_ssbo_atomic_umax:
5392          op32 = aco_opcode::buffer_atomic_umax;
5393          op64 = aco_opcode::buffer_atomic_umax_x2;
5394          break;
5395       case nir_intrinsic_ssbo_atomic_and:
5396          op32 = aco_opcode::buffer_atomic_and;
5397          op64 = aco_opcode::buffer_atomic_and_x2;
5398          break;
5399       case nir_intrinsic_ssbo_atomic_or:
5400          op32 = aco_opcode::buffer_atomic_or;
5401          op64 = aco_opcode::buffer_atomic_or_x2;
5402          break;
5403       case nir_intrinsic_ssbo_atomic_xor:
5404          op32 = aco_opcode::buffer_atomic_xor;
5405          op64 = aco_opcode::buffer_atomic_xor_x2;
5406          break;
5407       case nir_intrinsic_ssbo_atomic_exchange:
5408          op32 = aco_opcode::buffer_atomic_swap;
5409          op64 = aco_opcode::buffer_atomic_swap_x2;
5410          break;
5411       case nir_intrinsic_ssbo_atomic_comp_swap:
5412          op32 = aco_opcode::buffer_atomic_cmpswap;
5413          op64 = aco_opcode::buffer_atomic_cmpswap_x2;
5414          break;
5415       default:
5416          unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
5417    }
5418    aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
5419    aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, return_previous ? 1 : 0)};
5420    mubuf->operands[0] = Operand(rsrc);
5421    mubuf->operands[1] = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
5422    mubuf->operands[2] = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
5423    mubuf->operands[3] = Operand(data);
5424    if (return_previous)
5425       mubuf->definitions[0] = Definition(dst);
5426    mubuf->offset = 0;
5427    mubuf->offen = (offset.type() == RegType::vgpr);
5428    mubuf->glc = return_previous;
5429    mubuf->dlc = false; /* Not needed for atomics */
5430    mubuf->disable_wqm = true;
5431    mubuf->barrier = barrier_buffer;
5432    ctx->program->needs_exact = true;
5433    ctx->block->instructions.emplace_back(std::move(mubuf));
5434 }
5435
5436 void visit_get_buffer_size(isel_context *ctx, nir_intrinsic_instr *instr) {
5437
5438    Temp index = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5439    Builder bld(ctx->program, ctx->block);
5440    Temp desc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), index, Operand(0u));
5441    get_buffer_size(ctx, desc, get_ssa_temp(ctx, &instr->dest.ssa), false);
5442 }
5443
5444 Temp get_gfx6_global_rsrc(Builder& bld, Temp addr)
5445 {
5446    uint32_t rsrc_conf = S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5447                         S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
5448
5449    if (addr.type() == RegType::vgpr)
5450       return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf));
5451    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), addr, Operand(-1u), Operand(rsrc_conf));
5452 }
5453
5454 void visit_load_global(isel_context *ctx, nir_intrinsic_instr *instr)
5455 {
5456    Builder bld(ctx->program, ctx->block);
5457    unsigned num_components = instr->num_components;
5458    unsigned num_bytes = num_components * instr->dest.ssa.bit_size / 8;
5459
5460    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5461    Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
5462
5463    bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT);
5464    bool dlc = glc && ctx->options->chip_class >= GFX10;
5465    aco_opcode op;
5466    if (dst.type() == RegType::vgpr || (glc && ctx->options->chip_class < GFX8)) {
5467       bool global = ctx->options->chip_class >= GFX9;
5468
5469       if (ctx->options->chip_class >= GFX7) {
5470          aco_opcode op;
5471          switch (num_bytes) {
5472          case 4:
5473             op = global ? aco_opcode::global_load_dword : aco_opcode::flat_load_dword;
5474             break;
5475          case 8:
5476             op = global ? aco_opcode::global_load_dwordx2 : aco_opcode::flat_load_dwordx2;
5477             break;
5478          case 12:
5479             op = global ? aco_opcode::global_load_dwordx3 : aco_opcode::flat_load_dwordx3;
5480             break;
5481          case 16:
5482             op = global ? aco_opcode::global_load_dwordx4 : aco_opcode::flat_load_dwordx4;
5483             break;
5484          default:
5485             unreachable("load_global not implemented for this size.");
5486          }
5487
5488          aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 2, 1)};
5489          flat->operands[0] = Operand(addr);
5490          flat->operands[1] = Operand(s1);
5491          flat->glc = glc;
5492          flat->dlc = dlc;
5493          flat->barrier = barrier_buffer;
5494
5495          if (dst.type() == RegType::sgpr) {
5496             Temp vec = bld.tmp(RegType::vgpr, dst.size());
5497             flat->definitions[0] = Definition(vec);
5498             ctx->block->instructions.emplace_back(std::move(flat));
5499             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec);
5500          } else {
5501             flat->definitions[0] = Definition(dst);
5502             ctx->block->instructions.emplace_back(std::move(flat));
5503          }
5504          emit_split_vector(ctx, dst, num_components);
5505       } else {
5506          assert(ctx->options->chip_class == GFX6);
5507
5508          /* GFX6 doesn't support loading vec3, expand to vec4. */
5509          num_bytes = num_bytes == 12 ? 16 : num_bytes;
5510
5511          aco_opcode op;
5512          switch (num_bytes) {
5513          case 4:
5514             op = aco_opcode::buffer_load_dword;
5515             break;
5516          case 8:
5517             op = aco_opcode::buffer_load_dwordx2;
5518             break;
5519          case 16:
5520             op = aco_opcode::buffer_load_dwordx4;
5521             break;
5522          default:
5523             unreachable("load_global not implemented for this size.");
5524          }
5525
5526          Temp rsrc = get_gfx6_global_rsrc(bld, addr);
5527
5528          aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
5529          mubuf->operands[0] = Operand(rsrc);
5530          mubuf->operands[1] = addr.type() == RegType::vgpr ? Operand(addr) : Operand(v1);
5531          mubuf->operands[2] = Operand(0u);
5532          mubuf->glc = glc;
5533          mubuf->dlc = false;
5534          mubuf->offset = 0;
5535          mubuf->addr64 = addr.type() == RegType::vgpr;
5536          mubuf->disable_wqm = false;
5537          mubuf->barrier = barrier_buffer;
5538          aco_ptr<Instruction> instr = std::move(mubuf);
5539
5540          /* expand vector */
5541          if (dst.size() == 3) {
5542             Temp vec = bld.tmp(v4);
5543             instr->definitions[0] = Definition(vec);
5544             bld.insert(std::move(instr));
5545             emit_split_vector(ctx, vec, 4);
5546
5547             instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, 3, 1));
5548             instr->operands[0] = Operand(emit_extract_vector(ctx, vec, 0, v1));
5549             instr->operands[1] = Operand(emit_extract_vector(ctx, vec, 1, v1));
5550             instr->operands[2] = Operand(emit_extract_vector(ctx, vec, 2, v1));
5551          }
5552
5553          if (dst.type() == RegType::sgpr) {
5554             Temp vec = bld.tmp(RegType::vgpr, dst.size());
5555             instr->definitions[0] = Definition(vec);
5556             bld.insert(std::move(instr));
5557             expand_vector(ctx, vec, dst, num_components, (1 << num_components) - 1);
5558             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec);
5559          } else {
5560             instr->definitions[0] = Definition(dst);
5561             bld.insert(std::move(instr));
5562             emit_split_vector(ctx, dst, num_components);
5563          }
5564       }
5565    } else {
5566       switch (num_bytes) {
5567          case 4:
5568             op = aco_opcode::s_load_dword;
5569             break;
5570          case 8:
5571             op = aco_opcode::s_load_dwordx2;
5572             break;
5573          case 12:
5574          case 16:
5575             op = aco_opcode::s_load_dwordx4;
5576             break;
5577          default:
5578             unreachable("load_global not implemented for this size.");
5579       }
5580       aco_ptr<SMEM_instruction> load{create_instruction<SMEM_instruction>(op, Format::SMEM, 2, 1)};
5581       load->operands[0] = Operand(addr);
5582       load->operands[1] = Operand(0u);
5583       load->definitions[0] = Definition(dst);
5584       load->glc = glc;
5585       load->dlc = dlc;
5586       load->barrier = barrier_buffer;
5587       assert(ctx->options->chip_class >= GFX8 || !glc);
5588
5589       if (dst.size() == 3) {
5590          /* trim vector */
5591          Temp vec = bld.tmp(s4);
5592          load->definitions[0] = Definition(vec);
5593          ctx->block->instructions.emplace_back(std::move(load));
5594          emit_split_vector(ctx, vec, 4);
5595
5596          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
5597                     emit_extract_vector(ctx, vec, 0, s1),
5598                     emit_extract_vector(ctx, vec, 1, s1),
5599                     emit_extract_vector(ctx, vec, 2, s1));
5600       } else {
5601          ctx->block->instructions.emplace_back(std::move(load));
5602       }
5603    }
5604 }
5605
5606 void visit_store_global(isel_context *ctx, nir_intrinsic_instr *instr)
5607 {
5608    Builder bld(ctx->program, ctx->block);
5609    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
5610
5611    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5612    Temp addr = get_ssa_temp(ctx, instr->src[1].ssa);
5613
5614    if (ctx->options->chip_class >= GFX7)
5615       addr = as_vgpr(ctx, addr);
5616
5617    unsigned writemask = nir_intrinsic_write_mask(instr);
5618    while (writemask) {
5619       int start, count;
5620       u_bit_scan_consecutive_range(&writemask, &start, &count);
5621       if (count == 3 && ctx->options->chip_class == GFX6) {
5622          /* GFX6 doesn't support storing vec3, split it. */
5623          writemask |= 1u << (start + 2);
5624          count = 2;
5625       }
5626       unsigned num_bytes = count * elem_size_bytes;
5627
5628       Temp write_data = data;
5629       if (count != instr->num_components) {
5630          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
5631          for (int i = 0; i < count; i++)
5632             vec->operands[i] = Operand(emit_extract_vector(ctx, data, start + i, v1));
5633          write_data = bld.tmp(RegType::vgpr, count);
5634          vec->definitions[0] = Definition(write_data);
5635          ctx->block->instructions.emplace_back(std::move(vec));
5636       }
5637
5638       bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
5639       unsigned offset = start * elem_size_bytes;
5640
5641       if (ctx->options->chip_class >= GFX7) {
5642          if (offset > 0 && ctx->options->chip_class < GFX9) {
5643             Temp addr0 = bld.tmp(v1), addr1 = bld.tmp(v1);
5644             Temp new_addr0 = bld.tmp(v1), new_addr1 = bld.tmp(v1);
5645             Temp carry = bld.tmp(bld.lm);
5646             bld.pseudo(aco_opcode::p_split_vector, Definition(addr0), Definition(addr1), addr);
5647
5648             bld.vop2(aco_opcode::v_add_co_u32, Definition(new_addr0), bld.hint_vcc(Definition(carry)),
5649                      Operand(offset), addr0);
5650             bld.vop2(aco_opcode::v_addc_co_u32, Definition(new_addr1), bld.def(bld.lm),
5651                      Operand(0u), addr1,
5652                      carry).def(1).setHint(vcc);
5653
5654             addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), new_addr0, new_addr1);
5655
5656             offset = 0;
5657          }
5658
5659          bool global = ctx->options->chip_class >= GFX9;
5660          aco_opcode op;
5661          switch (num_bytes) {
5662          case 4:
5663             op = global ? aco_opcode::global_store_dword : aco_opcode::flat_store_dword;
5664             break;
5665          case 8:
5666             op = global ? aco_opcode::global_store_dwordx2 : aco_opcode::flat_store_dwordx2;
5667             break;
5668          case 12:
5669             op = global ? aco_opcode::global_store_dwordx3 : aco_opcode::flat_store_dwordx3;
5670             break;
5671          case 16:
5672             op = global ? aco_opcode::global_store_dwordx4 : aco_opcode::flat_store_dwordx4;
5673             break;
5674          default:
5675             unreachable("store_global not implemented for this size.");
5676          }
5677
5678          aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 3, 0)};
5679          flat->operands[0] = Operand(addr);
5680          flat->operands[1] = Operand(s1);
5681          flat->operands[2] = Operand(data);
5682          flat->glc = glc;
5683          flat->dlc = false;
5684          flat->offset = offset;
5685          flat->disable_wqm = true;
5686          flat->barrier = barrier_buffer;
5687          ctx->program->needs_exact = true;
5688          ctx->block->instructions.emplace_back(std::move(flat));
5689       } else {
5690          assert(ctx->options->chip_class == GFX6);
5691
5692          aco_opcode op;
5693          switch (num_bytes) {
5694          case 4:
5695             op = aco_opcode::buffer_store_dword;
5696             break;
5697          case 8:
5698             op = aco_opcode::buffer_store_dwordx2;
5699             break;
5700          case 16:
5701             op = aco_opcode::buffer_store_dwordx4;
5702             break;
5703          default:
5704             unreachable("store_global not implemented for this size.");
5705          }
5706
5707          Temp rsrc = get_gfx6_global_rsrc(bld, addr);
5708
5709          aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, 0)};
5710          mubuf->operands[0] = Operand(rsrc);
5711          mubuf->operands[1] = addr.type() == RegType::vgpr ? Operand(addr) : Operand(v1);
5712          mubuf->operands[2] = Operand(0u);
5713          mubuf->operands[3] = Operand(write_data);
5714          mubuf->glc = glc;
5715          mubuf->dlc = false;
5716          mubuf->offset = offset;
5717          mubuf->addr64 = addr.type() == RegType::vgpr;
5718          mubuf->disable_wqm = true;
5719          mubuf->barrier = barrier_buffer;
5720          ctx->program->needs_exact = true;
5721          ctx->block->instructions.emplace_back(std::move(mubuf));
5722       }
5723    }
5724 }
5725
5726 void visit_global_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
5727 {
5728    /* return the previous value if dest is ever used */
5729    bool return_previous = false;
5730    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
5731       return_previous = true;
5732       break;
5733    }
5734    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
5735       return_previous = true;
5736       break;
5737    }
5738
5739    Builder bld(ctx->program, ctx->block);
5740    Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
5741    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5742
5743    if (ctx->options->chip_class >= GFX7)
5744       addr = as_vgpr(ctx, addr);
5745
5746    if (instr->intrinsic == nir_intrinsic_global_atomic_comp_swap)
5747       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(RegType::vgpr, data.size() * 2),
5748                         get_ssa_temp(ctx, instr->src[2].ssa), data);
5749
5750    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5751
5752    aco_opcode op32, op64;
5753
5754    if (ctx->options->chip_class >= GFX7) {
5755       bool global = ctx->options->chip_class >= GFX9;
5756       switch (instr->intrinsic) {
5757          case nir_intrinsic_global_atomic_add:
5758             op32 = global ? aco_opcode::global_atomic_add : aco_opcode::flat_atomic_add;
5759             op64 = global ? aco_opcode::global_atomic_add_x2 : aco_opcode::flat_atomic_add_x2;
5760             break;
5761          case nir_intrinsic_global_atomic_imin:
5762             op32 = global ? aco_opcode::global_atomic_smin : aco_opcode::flat_atomic_smin;
5763             op64 = global ? aco_opcode::global_atomic_smin_x2 : aco_opcode::flat_atomic_smin_x2;
5764             break;
5765          case nir_intrinsic_global_atomic_umin:
5766             op32 = global ? aco_opcode::global_atomic_umin : aco_opcode::flat_atomic_umin;
5767             op64 = global ? aco_opcode::global_atomic_umin_x2 : aco_opcode::flat_atomic_umin_x2;
5768             break;
5769          case nir_intrinsic_global_atomic_imax:
5770             op32 = global ? aco_opcode::global_atomic_smax : aco_opcode::flat_atomic_smax;
5771             op64 = global ? aco_opcode::global_atomic_smax_x2 : aco_opcode::flat_atomic_smax_x2;
5772             break;
5773          case nir_intrinsic_global_atomic_umax:
5774             op32 = global ? aco_opcode::global_atomic_umax : aco_opcode::flat_atomic_umax;
5775             op64 = global ? aco_opcode::global_atomic_umax_x2 : aco_opcode::flat_atomic_umax_x2;
5776             break;
5777          case nir_intrinsic_global_atomic_and:
5778             op32 = global ? aco_opcode::global_atomic_and : aco_opcode::flat_atomic_and;
5779             op64 = global ? aco_opcode::global_atomic_and_x2 : aco_opcode::flat_atomic_and_x2;
5780             break;
5781          case nir_intrinsic_global_atomic_or:
5782             op32 = global ? aco_opcode::global_atomic_or : aco_opcode::flat_atomic_or;
5783             op64 = global ? aco_opcode::global_atomic_or_x2 : aco_opcode::flat_atomic_or_x2;
5784             break;
5785          case nir_intrinsic_global_atomic_xor:
5786             op32 = global ? aco_opcode::global_atomic_xor : aco_opcode::flat_atomic_xor;
5787             op64 = global ? aco_opcode::global_atomic_xor_x2 : aco_opcode::flat_atomic_xor_x2;
5788             break;
5789          case nir_intrinsic_global_atomic_exchange:
5790             op32 = global ? aco_opcode::global_atomic_swap : aco_opcode::flat_atomic_swap;
5791             op64 = global ? aco_opcode::global_atomic_swap_x2 : aco_opcode::flat_atomic_swap_x2;
5792             break;
5793          case nir_intrinsic_global_atomic_comp_swap:
5794             op32 = global ? aco_opcode::global_atomic_cmpswap : aco_opcode::flat_atomic_cmpswap;
5795             op64 = global ? aco_opcode::global_atomic_cmpswap_x2 : aco_opcode::flat_atomic_cmpswap_x2;
5796             break;
5797          default:
5798             unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
5799       }
5800
5801       aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
5802       aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 3, return_previous ? 1 : 0)};
5803       flat->operands[0] = Operand(addr);
5804       flat->operands[1] = Operand(s1);
5805       flat->operands[2] = Operand(data);
5806       if (return_previous)
5807          flat->definitions[0] = Definition(dst);
5808       flat->glc = return_previous;
5809       flat->dlc = false; /* Not needed for atomics */
5810       flat->offset = 0;
5811       flat->disable_wqm = true;
5812       flat->barrier = barrier_buffer;
5813       ctx->program->needs_exact = true;
5814       ctx->block->instructions.emplace_back(std::move(flat));
5815    } else {
5816       assert(ctx->options->chip_class == GFX6);
5817
5818       switch (instr->intrinsic) {
5819          case nir_intrinsic_global_atomic_add:
5820             op32 = aco_opcode::buffer_atomic_add;
5821             op64 = aco_opcode::buffer_atomic_add_x2;
5822             break;
5823          case nir_intrinsic_global_atomic_imin:
5824             op32 = aco_opcode::buffer_atomic_smin;
5825             op64 = aco_opcode::buffer_atomic_smin_x2;
5826             break;
5827          case nir_intrinsic_global_atomic_umin:
5828             op32 = aco_opcode::buffer_atomic_umin;
5829             op64 = aco_opcode::buffer_atomic_umin_x2;
5830             break;
5831          case nir_intrinsic_global_atomic_imax:
5832             op32 = aco_opcode::buffer_atomic_smax;
5833             op64 = aco_opcode::buffer_atomic_smax_x2;
5834             break;
5835          case nir_intrinsic_global_atomic_umax:
5836             op32 = aco_opcode::buffer_atomic_umax;
5837             op64 = aco_opcode::buffer_atomic_umax_x2;
5838             break;
5839          case nir_intrinsic_global_atomic_and:
5840             op32 = aco_opcode::buffer_atomic_and;
5841             op64 = aco_opcode::buffer_atomic_and_x2;
5842             break;
5843          case nir_intrinsic_global_atomic_or:
5844             op32 = aco_opcode::buffer_atomic_or;
5845             op64 = aco_opcode::buffer_atomic_or_x2;
5846             break;
5847          case nir_intrinsic_global_atomic_xor:
5848             op32 = aco_opcode::buffer_atomic_xor;
5849             op64 = aco_opcode::buffer_atomic_xor_x2;
5850             break;
5851          case nir_intrinsic_global_atomic_exchange:
5852             op32 = aco_opcode::buffer_atomic_swap;
5853             op64 = aco_opcode::buffer_atomic_swap_x2;
5854             break;
5855          case nir_intrinsic_global_atomic_comp_swap:
5856             op32 = aco_opcode::buffer_atomic_cmpswap;
5857             op64 = aco_opcode::buffer_atomic_cmpswap_x2;
5858             break;
5859          default:
5860             unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
5861       }
5862
5863       Temp rsrc = get_gfx6_global_rsrc(bld, addr);
5864
5865       aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
5866
5867       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, return_previous ? 1 : 0)};
5868       mubuf->operands[0] = Operand(rsrc);
5869       mubuf->operands[1] = addr.type() == RegType::vgpr ? Operand(addr) : Operand(v1);
5870       mubuf->operands[2] = Operand(0u);
5871       mubuf->operands[3] = Operand(data);
5872       if (return_previous)
5873          mubuf->definitions[0] = Definition(dst);
5874       mubuf->glc = return_previous;
5875       mubuf->dlc = false;
5876       mubuf->offset = 0;
5877       mubuf->addr64 = addr.type() == RegType::vgpr;
5878       mubuf->disable_wqm = true;
5879       mubuf->barrier = barrier_buffer;
5880       ctx->program->needs_exact = true;
5881       ctx->block->instructions.emplace_back(std::move(mubuf));
5882    }
5883 }
5884
5885 void emit_memory_barrier(isel_context *ctx, nir_intrinsic_instr *instr) {
5886    Builder bld(ctx->program, ctx->block);
5887    switch(instr->intrinsic) {
5888       case nir_intrinsic_group_memory_barrier:
5889       case nir_intrinsic_memory_barrier:
5890          bld.barrier(aco_opcode::p_memory_barrier_common);
5891          break;
5892       case nir_intrinsic_memory_barrier_buffer:
5893          bld.barrier(aco_opcode::p_memory_barrier_buffer);
5894          break;
5895       case nir_intrinsic_memory_barrier_image:
5896          bld.barrier(aco_opcode::p_memory_barrier_image);
5897          break;
5898       case nir_intrinsic_memory_barrier_tcs_patch:
5899       case nir_intrinsic_memory_barrier_shared:
5900          bld.barrier(aco_opcode::p_memory_barrier_shared);
5901          break;
5902       default:
5903          unreachable("Unimplemented memory barrier intrinsic");
5904          break;
5905    }
5906 }
5907
5908 void visit_load_shared(isel_context *ctx, nir_intrinsic_instr *instr)
5909 {
5910    // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
5911    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5912    assert(instr->dest.ssa.bit_size >= 32 && "Bitsize not supported in load_shared.");
5913    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5914    Builder bld(ctx->program, ctx->block);
5915
5916    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
5917    unsigned align = nir_intrinsic_align_mul(instr) ? nir_intrinsic_align(instr) : elem_size_bytes;
5918    load_lds(ctx, elem_size_bytes, dst, address, nir_intrinsic_base(instr), align);
5919 }
5920
5921 void visit_store_shared(isel_context *ctx, nir_intrinsic_instr *instr)
5922 {
5923    unsigned writemask = nir_intrinsic_write_mask(instr);
5924    Temp data = get_ssa_temp(ctx, instr->src[0].ssa);
5925    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5926    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
5927    assert(elem_size_bytes >= 4 && "Only 32bit & 64bit store_shared currently supported.");
5928
5929    unsigned align = nir_intrinsic_align_mul(instr) ? nir_intrinsic_align(instr) : elem_size_bytes;
5930    store_lds(ctx, elem_size_bytes, data, writemask, address, nir_intrinsic_base(instr), align);
5931 }
5932
5933 void visit_shared_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
5934 {
5935    unsigned offset = nir_intrinsic_base(instr);
5936    Operand m = load_lds_size_m0(ctx);
5937    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5938    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5939
5940    unsigned num_operands = 3;
5941    aco_opcode op32, op64, op32_rtn, op64_rtn;
5942    switch(instr->intrinsic) {
5943       case nir_intrinsic_shared_atomic_add:
5944          op32 = aco_opcode::ds_add_u32;
5945          op64 = aco_opcode::ds_add_u64;
5946          op32_rtn = aco_opcode::ds_add_rtn_u32;
5947          op64_rtn = aco_opcode::ds_add_rtn_u64;
5948          break;
5949       case nir_intrinsic_shared_atomic_imin:
5950          op32 = aco_opcode::ds_min_i32;
5951          op64 = aco_opcode::ds_min_i64;
5952          op32_rtn = aco_opcode::ds_min_rtn_i32;
5953          op64_rtn = aco_opcode::ds_min_rtn_i64;
5954          break;
5955       case nir_intrinsic_shared_atomic_umin:
5956          op32 = aco_opcode::ds_min_u32;
5957          op64 = aco_opcode::ds_min_u64;
5958          op32_rtn = aco_opcode::ds_min_rtn_u32;
5959          op64_rtn = aco_opcode::ds_min_rtn_u64;
5960          break;
5961       case nir_intrinsic_shared_atomic_imax:
5962          op32 = aco_opcode::ds_max_i32;
5963          op64 = aco_opcode::ds_max_i64;
5964          op32_rtn = aco_opcode::ds_max_rtn_i32;
5965          op64_rtn = aco_opcode::ds_max_rtn_i64;
5966          break;
5967       case nir_intrinsic_shared_atomic_umax:
5968          op32 = aco_opcode::ds_max_u32;
5969          op64 = aco_opcode::ds_max_u64;
5970          op32_rtn = aco_opcode::ds_max_rtn_u32;
5971          op64_rtn = aco_opcode::ds_max_rtn_u64;
5972          break;
5973       case nir_intrinsic_shared_atomic_and:
5974          op32 = aco_opcode::ds_and_b32;
5975          op64 = aco_opcode::ds_and_b64;
5976          op32_rtn = aco_opcode::ds_and_rtn_b32;
5977          op64_rtn = aco_opcode::ds_and_rtn_b64;
5978          break;
5979       case nir_intrinsic_shared_atomic_or:
5980          op32 = aco_opcode::ds_or_b32;
5981          op64 = aco_opcode::ds_or_b64;
5982          op32_rtn = aco_opcode::ds_or_rtn_b32;
5983          op64_rtn = aco_opcode::ds_or_rtn_b64;
5984          break;
5985       case nir_intrinsic_shared_atomic_xor:
5986          op32 = aco_opcode::ds_xor_b32;
5987          op64 = aco_opcode::ds_xor_b64;
5988          op32_rtn = aco_opcode::ds_xor_rtn_b32;
5989          op64_rtn = aco_opcode::ds_xor_rtn_b64;
5990          break;
5991       case nir_intrinsic_shared_atomic_exchange:
5992          op32 = aco_opcode::ds_write_b32;
5993          op64 = aco_opcode::ds_write_b64;
5994          op32_rtn = aco_opcode::ds_wrxchg_rtn_b32;
5995          op64_rtn = aco_opcode::ds_wrxchg2_rtn_b64;
5996          break;
5997       case nir_intrinsic_shared_atomic_comp_swap:
5998          op32 = aco_opcode::ds_cmpst_b32;
5999          op64 = aco_opcode::ds_cmpst_b64;
6000          op32_rtn = aco_opcode::ds_cmpst_rtn_b32;
6001          op64_rtn = aco_opcode::ds_cmpst_rtn_b64;
6002          num_operands = 4;
6003          break;
6004       default:
6005          unreachable("Unhandled shared atomic intrinsic");
6006    }
6007
6008    /* return the previous value if dest is ever used */
6009    bool return_previous = false;
6010    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
6011       return_previous = true;
6012       break;
6013    }
6014    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
6015       return_previous = true;
6016       break;
6017    }
6018
6019    aco_opcode op;
6020    if (data.size() == 1) {
6021       assert(instr->dest.ssa.bit_size == 32);
6022       op = return_previous ? op32_rtn : op32;
6023    } else {
6024       assert(instr->dest.ssa.bit_size == 64);
6025       op = return_previous ? op64_rtn : op64;
6026    }
6027
6028    if (offset > 65535) {
6029       Builder bld(ctx->program, ctx->block);
6030       address = bld.vadd32(bld.def(v1), Operand(offset), address);
6031       offset = 0;
6032    }
6033
6034    aco_ptr<DS_instruction> ds;
6035    ds.reset(create_instruction<DS_instruction>(op, Format::DS, num_operands, return_previous ? 1 : 0));
6036    ds->operands[0] = Operand(address);
6037    ds->operands[1] = Operand(data);
6038    if (num_operands == 4)
6039       ds->operands[2] = Operand(get_ssa_temp(ctx, instr->src[2].ssa));
6040    ds->operands[num_operands - 1] = m;
6041    ds->offset0 = offset;
6042    if (return_previous)
6043       ds->definitions[0] = Definition(get_ssa_temp(ctx, &instr->dest.ssa));
6044    ctx->block->instructions.emplace_back(std::move(ds));
6045 }
6046
6047 Temp get_scratch_resource(isel_context *ctx)
6048 {
6049    Builder bld(ctx->program, ctx->block);
6050    Temp scratch_addr = ctx->program->private_segment_buffer;
6051    if (ctx->stage != compute_cs)
6052       scratch_addr = bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), scratch_addr, Operand(0u));
6053
6054    uint32_t rsrc_conf = S_008F0C_ADD_TID_ENABLE(1) |
6055                         S_008F0C_INDEX_STRIDE(ctx->program->wave_size == 64 ? 3 : 2);;
6056
6057    if (ctx->program->chip_class >= GFX10) {
6058       rsrc_conf |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
6059                    S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
6060                    S_008F0C_RESOURCE_LEVEL(1);
6061    } else if (ctx->program->chip_class <= GFX7) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6062       rsrc_conf |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
6063                    S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
6064    }
6065
6066    /* older generations need element size = 16 bytes. element size removed in GFX9 */
6067    if (ctx->program->chip_class <= GFX8)
6068       rsrc_conf |= S_008F0C_ELEMENT_SIZE(3);
6069
6070    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), scratch_addr, Operand(-1u), Operand(rsrc_conf));
6071 }
6072
6073 void visit_load_scratch(isel_context *ctx, nir_intrinsic_instr *instr) {
6074    assert(instr->dest.ssa.bit_size == 32 || instr->dest.ssa.bit_size == 64);
6075    Builder bld(ctx->program, ctx->block);
6076    Temp rsrc = get_scratch_resource(ctx);
6077    Temp offset = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
6078    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6079
6080    aco_opcode op;
6081    switch (dst.size()) {
6082       case 1:
6083          op = aco_opcode::buffer_load_dword;
6084          break;
6085       case 2:
6086          op = aco_opcode::buffer_load_dwordx2;
6087          break;
6088       case 3:
6089          op = aco_opcode::buffer_load_dwordx3;
6090          break;
6091       case 4:
6092          op = aco_opcode::buffer_load_dwordx4;
6093          break;
6094       case 6:
6095       case 8: {
6096          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
6097          Temp lower = bld.mubuf(aco_opcode::buffer_load_dwordx4,
6098                                 bld.def(v4), rsrc, offset,
6099                                 ctx->program->scratch_offset, 0, true);
6100          Temp upper = bld.mubuf(dst.size() == 6 ? aco_opcode::buffer_load_dwordx2 :
6101                                                   aco_opcode::buffer_load_dwordx4,
6102                                 dst.size() == 6 ? bld.def(v2) : bld.def(v4),
6103                                 rsrc, offset, ctx->program->scratch_offset, 16, true);
6104          emit_split_vector(ctx, lower, 2);
6105          elems[0] = emit_extract_vector(ctx, lower, 0, v2);
6106          elems[1] = emit_extract_vector(ctx, lower, 1, v2);
6107          if (dst.size() == 8) {
6108             emit_split_vector(ctx, upper, 2);
6109             elems[2] = emit_extract_vector(ctx, upper, 0, v2);
6110             elems[3] = emit_extract_vector(ctx, upper, 1, v2);
6111          } else {
6112             elems[2] = upper;
6113          }
6114
6115          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector,
6116                                                                          Format::PSEUDO, dst.size() / 2, 1)};
6117          for (unsigned i = 0; i < dst.size() / 2; i++)
6118             vec->operands[i] = Operand(elems[i]);
6119          vec->definitions[0] = Definition(dst);
6120          bld.insert(std::move(vec));
6121          ctx->allocated_vec.emplace(dst.id(), elems);
6122          return;
6123       }
6124       default:
6125          unreachable("Wrong dst size for nir_intrinsic_load_scratch");
6126    }
6127
6128    bld.mubuf(op, Definition(dst), rsrc, offset, ctx->program->scratch_offset, 0, true);
6129    emit_split_vector(ctx, dst, instr->num_components);
6130 }
6131
6132 void visit_store_scratch(isel_context *ctx, nir_intrinsic_instr *instr) {
6133    assert(instr->src[0].ssa->bit_size == 32 || instr->src[0].ssa->bit_size == 64);
6134    Builder bld(ctx->program, ctx->block);
6135    Temp rsrc = get_scratch_resource(ctx);
6136    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
6137    Temp offset = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
6138
6139    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
6140    unsigned writemask = nir_intrinsic_write_mask(instr);
6141
6142    while (writemask) {
6143       int start, count;
6144       u_bit_scan_consecutive_range(&writemask, &start, &count);
6145       int num_bytes = count * elem_size_bytes;
6146
6147       if (num_bytes > 16) {
6148          assert(elem_size_bytes == 8);
6149          writemask |= (((count - 2) << 1) - 1) << (start + 2);
6150          count = 2;
6151          num_bytes = 16;
6152       }
6153
6154       // TODO: check alignment of sub-dword stores
6155       // TODO: split 3 bytes. there is no store instruction for that
6156
6157       Temp write_data;
6158       if (count != instr->num_components) {
6159          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
6160          for (int i = 0; i < count; i++) {
6161             Temp elem = emit_extract_vector(ctx, data, start + i, RegClass(RegType::vgpr, elem_size_bytes / 4));
6162             vec->operands[i] = Operand(elem);
6163          }
6164          write_data = bld.tmp(RegClass(RegType::vgpr, count * elem_size_bytes / 4));
6165          vec->definitions[0] = Definition(write_data);
6166          ctx->block->instructions.emplace_back(std::move(vec));
6167       } else {
6168          write_data = data;
6169       }
6170
6171       aco_opcode op;
6172       switch (num_bytes) {
6173          case 4:
6174             op = aco_opcode::buffer_store_dword;
6175             break;
6176          case 8:
6177             op = aco_opcode::buffer_store_dwordx2;
6178             break;
6179          case 12:
6180             op = aco_opcode::buffer_store_dwordx3;
6181             break;
6182          case 16:
6183             op = aco_opcode::buffer_store_dwordx4;
6184             break;
6185          default:
6186             unreachable("Invalid data size for nir_intrinsic_store_scratch.");
6187       }
6188
6189       bld.mubuf(op, rsrc, offset, ctx->program->scratch_offset, write_data, start * elem_size_bytes, true);
6190    }
6191 }
6192
6193 void visit_load_sample_mask_in(isel_context *ctx, nir_intrinsic_instr *instr) {
6194    uint8_t log2_ps_iter_samples;
6195    if (ctx->program->info->ps.force_persample) {
6196       log2_ps_iter_samples =
6197          util_logbase2(ctx->options->key.fs.num_samples);
6198    } else {
6199       log2_ps_iter_samples = ctx->options->key.fs.log2_ps_iter_samples;
6200    }
6201
6202    /* The bit pattern matches that used by fixed function fragment
6203     * processing. */
6204    static const unsigned ps_iter_masks[] = {
6205       0xffff, /* not used */
6206       0x5555,
6207       0x1111,
6208       0x0101,
6209       0x0001,
6210    };
6211    assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
6212
6213    Builder bld(ctx->program, ctx->block);
6214
6215    Temp sample_id = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1),
6216                              get_arg(ctx, ctx->args->ac.ancillary), Operand(8u), Operand(4u));
6217    Temp ps_iter_mask = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(ps_iter_masks[log2_ps_iter_samples]));
6218    Temp mask = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), sample_id, ps_iter_mask);
6219    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6220    bld.vop2(aco_opcode::v_and_b32, Definition(dst), mask, get_arg(ctx, ctx->args->ac.sample_coverage));
6221 }
6222
6223 void visit_emit_vertex_with_counter(isel_context *ctx, nir_intrinsic_instr *instr) {
6224    Builder bld(ctx->program, ctx->block);
6225
6226    unsigned stream = nir_intrinsic_stream_id(instr);
6227    Temp next_vertex = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
6228    next_vertex = bld.v_mul_imm(bld.def(v1), next_vertex, 4u);
6229    nir_const_value *next_vertex_cv = nir_src_as_const_value(instr->src[0]);
6230
6231    /* get GSVS ring */
6232    Temp gsvs_ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_GSVS_GS * 16u));
6233
6234    unsigned num_components =
6235       ctx->program->info->gs.num_stream_output_components[stream];
6236    assert(num_components);
6237
6238    unsigned stride = 4u * num_components * ctx->shader->info.gs.vertices_out;
6239    unsigned stream_offset = 0;
6240    for (unsigned i = 0; i < stream; i++) {
6241       unsigned prev_stride = 4u * ctx->program->info->gs.num_stream_output_components[i] * ctx->shader->info.gs.vertices_out;
6242       stream_offset += prev_stride * ctx->program->wave_size;
6243    }
6244
6245    /* Limit on the stride field for <= GFX7. */
6246    assert(stride < (1 << 14));
6247
6248    Temp gsvs_dwords[4];
6249    for (unsigned i = 0; i < 4; i++)
6250       gsvs_dwords[i] = bld.tmp(s1);
6251    bld.pseudo(aco_opcode::p_split_vector,
6252               Definition(gsvs_dwords[0]),
6253               Definition(gsvs_dwords[1]),
6254               Definition(gsvs_dwords[2]),
6255               Definition(gsvs_dwords[3]),
6256               gsvs_ring);
6257
6258    if (stream_offset) {
6259       Temp stream_offset_tmp = bld.copy(bld.def(s1), Operand(stream_offset));
6260
6261       Temp carry = bld.tmp(s1);
6262       gsvs_dwords[0] = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), gsvs_dwords[0], stream_offset_tmp);
6263       gsvs_dwords[1] = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), gsvs_dwords[1], Operand(0u), bld.scc(carry));
6264    }
6265
6266    gsvs_dwords[1] = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), gsvs_dwords[1], Operand(S_008F04_STRIDE(stride)));
6267    gsvs_dwords[2] = bld.copy(bld.def(s1), Operand((uint32_t)ctx->program->wave_size));
6268
6269    gsvs_ring = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
6270                           gsvs_dwords[0], gsvs_dwords[1], gsvs_dwords[2], gsvs_dwords[3]);
6271
6272    unsigned offset = 0;
6273    for (unsigned i = 0; i <= VARYING_SLOT_VAR31; i++) {
6274       if (ctx->program->info->gs.output_streams[i] != stream)
6275          continue;
6276
6277       for (unsigned j = 0; j < 4; j++) {
6278          if (!(ctx->program->info->gs.output_usage_mask[i] & (1 << j)))
6279             continue;
6280
6281          if (ctx->outputs.mask[i] & (1 << j)) {
6282             Operand vaddr_offset = next_vertex_cv ? Operand(v1) : Operand(next_vertex);
6283             unsigned const_offset = (offset + (next_vertex_cv ? next_vertex_cv->u32 : 0u)) * 4u;
6284             if (const_offset >= 4096u) {
6285                if (vaddr_offset.isUndefined())
6286                   vaddr_offset = bld.copy(bld.def(v1), Operand(const_offset / 4096u * 4096u));
6287                else
6288                   vaddr_offset = bld.vadd32(bld.def(v1), Operand(const_offset / 4096u * 4096u), vaddr_offset);
6289                const_offset %= 4096u;
6290             }
6291
6292             aco_ptr<MTBUF_instruction> mtbuf{create_instruction<MTBUF_instruction>(aco_opcode::tbuffer_store_format_x, Format::MTBUF, 4, 0)};
6293             mtbuf->operands[0] = Operand(gsvs_ring);
6294             mtbuf->operands[1] = vaddr_offset;
6295             mtbuf->operands[2] = Operand(get_arg(ctx, ctx->args->gs2vs_offset));
6296             mtbuf->operands[3] = Operand(ctx->outputs.outputs[i][j]);
6297             mtbuf->offen = !vaddr_offset.isUndefined();
6298             mtbuf->dfmt = V_008F0C_BUF_DATA_FORMAT_32;
6299             mtbuf->nfmt = V_008F0C_BUF_NUM_FORMAT_UINT;
6300             mtbuf->offset = const_offset;
6301             mtbuf->glc = true;
6302             mtbuf->slc = true;
6303             mtbuf->barrier = barrier_gs_data;
6304             mtbuf->can_reorder = true;
6305             bld.insert(std::move(mtbuf));
6306          }
6307
6308          offset += ctx->shader->info.gs.vertices_out;
6309       }
6310
6311       /* outputs for the next vertex are undefined and keeping them around can
6312        * create invalid IR with control flow */
6313       ctx->outputs.mask[i] = 0;
6314    }
6315
6316    bld.sopp(aco_opcode::s_sendmsg, bld.m0(ctx->gs_wave_id), -1, sendmsg_gs(false, true, stream));
6317 }
6318
6319 Temp emit_boolean_reduce(isel_context *ctx, nir_op op, unsigned cluster_size, Temp src)
6320 {
6321    Builder bld(ctx->program, ctx->block);
6322
6323    if (cluster_size == 1) {
6324       return src;
6325    } if (op == nir_op_iand && cluster_size == 4) {
6326       //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6327       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src);
6328       return bld.sop1(Builder::s_not, bld.def(bld.lm), bld.def(s1, scc),
6329                       bld.sop1(Builder::s_wqm, bld.def(bld.lm), bld.def(s1, scc), tmp));
6330    } else if (op == nir_op_ior && cluster_size == 4) {
6331       //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6332       return bld.sop1(Builder::s_wqm, bld.def(bld.lm), bld.def(s1, scc),
6333                       bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm)));
6334    } else if (op == nir_op_iand && cluster_size == ctx->program->wave_size) {
6335       //subgroupAnd(val) -> (exec & ~val) == 0
6336       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src).def(1).getTemp();
6337       Temp cond = bool_to_vector_condition(ctx, emit_wqm(ctx, tmp));
6338       return bld.sop1(Builder::s_not, bld.def(bld.lm), bld.def(s1, scc), cond);
6339    } else if (op == nir_op_ior && cluster_size == ctx->program->wave_size) {
6340       //subgroupOr(val) -> (val & exec) != 0
6341       Temp tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm)).def(1).getTemp();
6342       return bool_to_vector_condition(ctx, tmp);
6343    } else if (op == nir_op_ixor && cluster_size == ctx->program->wave_size) {
6344       //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6345       Temp tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
6346       tmp = bld.sop1(Builder::s_bcnt1_i32, bld.def(s1), bld.def(s1, scc), tmp);
6347       tmp = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), tmp, Operand(1u)).def(1).getTemp();
6348       return bool_to_vector_condition(ctx, tmp);
6349    } else {
6350       //subgroupClustered{And,Or,Xor}(val, n) ->
6351       //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ;  just v_mbcnt_lo_u32_b32 on wave32
6352       //cluster_offset = ~(n - 1) & lane_id
6353       //cluster_mask = ((1 << n) - 1)
6354       //subgroupClusteredAnd():
6355       //   return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6356       //subgroupClusteredOr():
6357       //   return ((val & exec) >> cluster_offset) & cluster_mask != 0
6358       //subgroupClusteredXor():
6359       //   return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6360       Temp lane_id = emit_mbcnt(ctx, bld.def(v1));
6361       Temp cluster_offset = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(~uint32_t(cluster_size - 1)), lane_id);
6362
6363       Temp tmp;
6364       if (op == nir_op_iand)
6365          tmp = bld.sop2(Builder::s_orn2, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
6366       else
6367          tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
6368
6369       uint32_t cluster_mask = cluster_size == 32 ? -1 : (1u << cluster_size) - 1u;
6370
6371       if (ctx->program->chip_class <= GFX7)
6372          tmp = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), tmp, cluster_offset);
6373       else if (ctx->program->wave_size == 64)
6374          tmp = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), cluster_offset, tmp);
6375       else
6376          tmp = bld.vop2_e64(aco_opcode::v_lshrrev_b32, bld.def(v1), cluster_offset, tmp);
6377       tmp = emit_extract_vector(ctx, tmp, 0, v1);
6378       if (cluster_mask != 0xffffffff)
6379          tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(cluster_mask), tmp);
6380
6381       Definition cmp_def = Definition();
6382       if (op == nir_op_iand) {
6383          cmp_def = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm), Operand(cluster_mask), tmp).def(0);
6384       } else if (op == nir_op_ior) {
6385          cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp).def(0);
6386       } else if (op == nir_op_ixor) {
6387          tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u),
6388                         bld.vop3(aco_opcode::v_bcnt_u32_b32, bld.def(v1), tmp, Operand(0u)));
6389          cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp).def(0);
6390       }
6391       cmp_def.setHint(vcc);
6392       return cmp_def.getTemp();
6393    }
6394 }
6395
6396 Temp emit_boolean_exclusive_scan(isel_context *ctx, nir_op op, Temp src)
6397 {
6398    Builder bld(ctx->program, ctx->block);
6399
6400    //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
6401    //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
6402    //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
6403    Temp tmp;
6404    if (op == nir_op_iand)
6405       tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src);
6406    else
6407       tmp = bld.sop2(Builder::s_and, bld.def(s2), bld.def(s1, scc), src, Operand(exec, bld.lm));
6408
6409    Builder::Result lohi = bld.pseudo(aco_opcode::p_split_vector, bld.def(s1), bld.def(s1), tmp);
6410    Temp lo = lohi.def(0).getTemp();
6411    Temp hi = lohi.def(1).getTemp();
6412    Temp mbcnt = emit_mbcnt(ctx, bld.def(v1), Operand(lo), Operand(hi));
6413
6414    Definition cmp_def = Definition();
6415    if (op == nir_op_iand)
6416       cmp_def = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm), Operand(0u), mbcnt).def(0);
6417    else if (op == nir_op_ior)
6418       cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), mbcnt).def(0);
6419    else if (op == nir_op_ixor)
6420       cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u),
6421                          bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u), mbcnt)).def(0);
6422    cmp_def.setHint(vcc);
6423    return cmp_def.getTemp();
6424 }
6425
6426 Temp emit_boolean_inclusive_scan(isel_context *ctx, nir_op op, Temp src)
6427 {
6428    Builder bld(ctx->program, ctx->block);
6429
6430    //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
6431    //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
6432    //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
6433    Temp tmp = emit_boolean_exclusive_scan(ctx, op, src);
6434    if (op == nir_op_iand)
6435       return bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
6436    else if (op == nir_op_ior)
6437       return bld.sop2(Builder::s_or, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
6438    else if (op == nir_op_ixor)
6439       return bld.sop2(Builder::s_xor, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
6440
6441    assert(false);
6442    return Temp();
6443 }
6444
6445 void emit_uniform_subgroup(isel_context *ctx, nir_intrinsic_instr *instr, Temp src)
6446 {
6447    Builder bld(ctx->program, ctx->block);
6448    Definition dst(get_ssa_temp(ctx, &instr->dest.ssa));
6449    if (src.regClass().type() == RegType::vgpr) {
6450       bld.pseudo(aco_opcode::p_as_uniform, dst, src);
6451    } else if (src.regClass() == s1) {
6452       bld.sop1(aco_opcode::s_mov_b32, dst, src);
6453    } else if (src.regClass() == s2) {
6454       bld.sop1(aco_opcode::s_mov_b64, dst, src);
6455    } else {
6456       fprintf(stderr, "Unimplemented NIR instr bit size: ");
6457       nir_print_instr(&instr->instr, stderr);
6458       fprintf(stderr, "\n");
6459    }
6460 }
6461
6462 void emit_interp_center(isel_context *ctx, Temp dst, Temp pos1, Temp pos2)
6463 {
6464    Builder bld(ctx->program, ctx->block);
6465    Temp persp_center = get_arg(ctx, ctx->args->ac.persp_center);
6466    Temp p1 = emit_extract_vector(ctx, persp_center, 0, v1);
6467    Temp p2 = emit_extract_vector(ctx, persp_center, 1, v1);
6468
6469    Temp ddx_1, ddx_2, ddy_1, ddy_2;
6470    uint32_t dpp_ctrl0 = dpp_quad_perm(0, 0, 0, 0);
6471    uint32_t dpp_ctrl1 = dpp_quad_perm(1, 1, 1, 1);
6472    uint32_t dpp_ctrl2 = dpp_quad_perm(2, 2, 2, 2);
6473
6474    /* Build DD X/Y */
6475    if (ctx->program->chip_class >= GFX8) {
6476       Temp tl_1 = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), p1, dpp_ctrl0);
6477       ddx_1 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p1, tl_1, dpp_ctrl1);
6478       ddy_1 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p1, tl_1, dpp_ctrl2);
6479       Temp tl_2 = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), p2, dpp_ctrl0);
6480       ddx_2 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p2, tl_2, dpp_ctrl1);
6481       ddy_2 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p2, tl_2, dpp_ctrl2);
6482    } else {
6483       Temp tl_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl0);
6484       ddx_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl1);
6485       ddx_1 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddx_1, tl_1);
6486       ddx_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl2);
6487       ddx_2 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddx_2, tl_1);
6488       Temp tl_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl0);
6489       ddy_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl1);
6490       ddy_1 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddy_1, tl_2);
6491       ddy_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl2);
6492       ddy_2 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddy_2, tl_2);
6493    }
6494
6495    /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
6496    Temp tmp1 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddx_1, pos1, p1);
6497    Temp tmp2 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddx_2, pos1, p2);
6498    tmp1 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddy_1, pos2, tmp1);
6499    tmp2 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddy_2, pos2, tmp2);
6500    Temp wqm1 = bld.tmp(v1);
6501    emit_wqm(ctx, tmp1, wqm1, true);
6502    Temp wqm2 = bld.tmp(v1);
6503    emit_wqm(ctx, tmp2, wqm2, true);
6504    bld.pseudo(aco_opcode::p_create_vector, Definition(dst), wqm1, wqm2);
6505    return;
6506 }
6507
6508 void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr)
6509 {
6510    Builder bld(ctx->program, ctx->block);
6511    switch(instr->intrinsic) {
6512    case nir_intrinsic_load_barycentric_sample:
6513    case nir_intrinsic_load_barycentric_pixel:
6514    case nir_intrinsic_load_barycentric_centroid: {
6515       glsl_interp_mode mode = (glsl_interp_mode)nir_intrinsic_interp_mode(instr);
6516       Temp bary = Temp(0, s2);
6517       switch (mode) {
6518       case INTERP_MODE_SMOOTH:
6519       case INTERP_MODE_NONE:
6520          if (instr->intrinsic == nir_intrinsic_load_barycentric_pixel)
6521             bary = get_arg(ctx, ctx->args->ac.persp_center);
6522          else if (instr->intrinsic == nir_intrinsic_load_barycentric_centroid)
6523             bary = ctx->persp_centroid;
6524          else if (instr->intrinsic == nir_intrinsic_load_barycentric_sample)
6525             bary = get_arg(ctx, ctx->args->ac.persp_sample);
6526          break;
6527       case INTERP_MODE_NOPERSPECTIVE:
6528          if (instr->intrinsic == nir_intrinsic_load_barycentric_pixel)
6529             bary = get_arg(ctx, ctx->args->ac.linear_center);
6530          else if (instr->intrinsic == nir_intrinsic_load_barycentric_centroid)
6531             bary = ctx->linear_centroid;
6532          else if (instr->intrinsic == nir_intrinsic_load_barycentric_sample)
6533             bary = get_arg(ctx, ctx->args->ac.linear_sample);
6534          break;
6535       default:
6536          break;
6537       }
6538       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6539       Temp p1 = emit_extract_vector(ctx, bary, 0, v1);
6540       Temp p2 = emit_extract_vector(ctx, bary, 1, v1);
6541       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
6542                  Operand(p1), Operand(p2));
6543       emit_split_vector(ctx, dst, 2);
6544       break;
6545    }
6546    case nir_intrinsic_load_barycentric_model: {
6547       Temp model = get_arg(ctx, ctx->args->ac.pull_model);
6548
6549       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6550       Temp p1 = emit_extract_vector(ctx, model, 0, v1);
6551       Temp p2 = emit_extract_vector(ctx, model, 1, v1);
6552       Temp p3 = emit_extract_vector(ctx, model, 2, v1);
6553       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
6554                  Operand(p1), Operand(p2), Operand(p3));
6555       emit_split_vector(ctx, dst, 3);
6556       break;
6557    }
6558    case nir_intrinsic_load_barycentric_at_sample: {
6559       uint32_t sample_pos_offset = RING_PS_SAMPLE_POSITIONS * 16;
6560       switch (ctx->options->key.fs.num_samples) {
6561          case 2: sample_pos_offset += 1 << 3; break;
6562          case 4: sample_pos_offset += 3 << 3; break;
6563          case 8: sample_pos_offset += 7 << 3; break;
6564          default: break;
6565       }
6566       Temp sample_pos;
6567       Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
6568       nir_const_value* const_addr = nir_src_as_const_value(instr->src[0]);
6569       Temp private_segment_buffer = ctx->program->private_segment_buffer;
6570       if (addr.type() == RegType::sgpr) {
6571          Operand offset;
6572          if (const_addr) {
6573             sample_pos_offset += const_addr->u32 << 3;
6574             offset = Operand(sample_pos_offset);
6575          } else if (ctx->options->chip_class >= GFX9) {
6576             offset = bld.sop2(aco_opcode::s_lshl3_add_u32, bld.def(s1), bld.def(s1, scc), addr, Operand(sample_pos_offset));
6577          } else {
6578             offset = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), addr, Operand(3u));
6579             offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), addr, Operand(sample_pos_offset));
6580          }
6581
6582          Operand off = bld.copy(bld.def(s1), Operand(offset));
6583          sample_pos = bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), private_segment_buffer, off);
6584
6585       } else if (ctx->options->chip_class >= GFX9) {
6586          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
6587          sample_pos = bld.global(aco_opcode::global_load_dwordx2, bld.def(v2), addr, private_segment_buffer, sample_pos_offset);
6588       } else if (ctx->options->chip_class >= GFX7) {
6589          /* addr += private_segment_buffer + sample_pos_offset */
6590          Temp tmp0 = bld.tmp(s1);
6591          Temp tmp1 = bld.tmp(s1);
6592          bld.pseudo(aco_opcode::p_split_vector, Definition(tmp0), Definition(tmp1), private_segment_buffer);
6593          Definition scc_tmp = bld.def(s1, scc);
6594          tmp0 = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), scc_tmp, tmp0, Operand(sample_pos_offset));
6595          tmp1 = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), tmp1, Operand(0u), bld.scc(scc_tmp.getTemp()));
6596          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
6597          Temp pck0 = bld.tmp(v1);
6598          Temp carry = bld.vadd32(Definition(pck0), tmp0, addr, true).def(1).getTemp();
6599          tmp1 = as_vgpr(ctx, tmp1);
6600          Temp pck1 = bld.vop2_e64(aco_opcode::v_addc_co_u32, bld.def(v1), bld.hint_vcc(bld.def(bld.lm)), tmp1, Operand(0u), carry);
6601          addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), pck0, pck1);
6602
6603          /* sample_pos = flat_load_dwordx2 addr */
6604          sample_pos = bld.flat(aco_opcode::flat_load_dwordx2, bld.def(v2), addr, Operand(s1));
6605       } else {
6606          assert(ctx->options->chip_class == GFX6);
6607
6608          uint32_t rsrc_conf = S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
6609                               S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
6610          Temp rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), private_segment_buffer, Operand(0u), Operand(rsrc_conf));
6611
6612          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
6613          addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), addr, Operand(0u));
6614
6615          sample_pos = bld.tmp(v2);
6616
6617          aco_ptr<MUBUF_instruction> load{create_instruction<MUBUF_instruction>(aco_opcode::buffer_load_dwordx2, Format::MUBUF, 3, 1)};
6618          load->definitions[0] = Definition(sample_pos);
6619          load->operands[0] = Operand(rsrc);
6620          load->operands[1] = Operand(addr);
6621          load->operands[2] = Operand(0u);
6622          load->offset = sample_pos_offset;
6623          load->offen = 0;
6624          load->addr64 = true;
6625          load->glc = false;
6626          load->dlc = false;
6627          load->disable_wqm = false;
6628          load->barrier = barrier_none;
6629          load->can_reorder = true;
6630          ctx->block->instructions.emplace_back(std::move(load));
6631       }
6632
6633       /* sample_pos -= 0.5 */
6634       Temp pos1 = bld.tmp(RegClass(sample_pos.type(), 1));
6635       Temp pos2 = bld.tmp(RegClass(sample_pos.type(), 1));
6636       bld.pseudo(aco_opcode::p_split_vector, Definition(pos1), Definition(pos2), sample_pos);
6637       pos1 = bld.vop2_e64(aco_opcode::v_sub_f32, bld.def(v1), pos1, Operand(0x3f000000u));
6638       pos2 = bld.vop2_e64(aco_opcode::v_sub_f32, bld.def(v1), pos2, Operand(0x3f000000u));
6639
6640       emit_interp_center(ctx, get_ssa_temp(ctx, &instr->dest.ssa), pos1, pos2);
6641       break;
6642    }
6643    case nir_intrinsic_load_barycentric_at_offset: {
6644       Temp offset = get_ssa_temp(ctx, instr->src[0].ssa);
6645       RegClass rc = RegClass(offset.type(), 1);
6646       Temp pos1 = bld.tmp(rc), pos2 = bld.tmp(rc);
6647       bld.pseudo(aco_opcode::p_split_vector, Definition(pos1), Definition(pos2), offset);
6648       emit_interp_center(ctx, get_ssa_temp(ctx, &instr->dest.ssa), pos1, pos2);
6649       break;
6650    }
6651    case nir_intrinsic_load_front_face: {
6652       bld.vopc(aco_opcode::v_cmp_lg_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6653                Operand(0u), get_arg(ctx, ctx->args->ac.front_face)).def(0).setHint(vcc);
6654       break;
6655    }
6656    case nir_intrinsic_load_view_index: {
6657       if (ctx->stage & (sw_vs | sw_gs | sw_tcs | sw_tes)) {
6658          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6659          bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.view_index)));
6660          break;
6661       }
6662
6663       /* fallthrough */
6664    }
6665    case nir_intrinsic_load_layer_id: {
6666       unsigned idx = nir_intrinsic_base(instr);
6667       bld.vintrp(aco_opcode::v_interp_mov_f32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6668                  Operand(2u), bld.m0(get_arg(ctx, ctx->args->ac.prim_mask)), idx, 0);
6669       break;
6670    }
6671    case nir_intrinsic_load_frag_coord: {
6672       emit_load_frag_coord(ctx, get_ssa_temp(ctx, &instr->dest.ssa), 4);
6673       break;
6674    }
6675    case nir_intrinsic_load_sample_pos: {
6676       Temp posx = get_arg(ctx, ctx->args->ac.frag_pos[0]);
6677       Temp posy = get_arg(ctx, ctx->args->ac.frag_pos[1]);
6678       bld.pseudo(aco_opcode::p_create_vector, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6679                  posx.id() ? bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), posx) : Operand(0u),
6680                  posy.id() ? bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), posy) : Operand(0u));
6681       break;
6682    }
6683    case nir_intrinsic_load_tess_coord:
6684       visit_load_tess_coord(ctx, instr);
6685       break;
6686    case nir_intrinsic_load_interpolated_input:
6687       visit_load_interpolated_input(ctx, instr);
6688       break;
6689    case nir_intrinsic_store_output:
6690       visit_store_output(ctx, instr);
6691       break;
6692    case nir_intrinsic_load_input:
6693    case nir_intrinsic_load_input_vertex:
6694       visit_load_input(ctx, instr);
6695       break;
6696    case nir_intrinsic_load_output:
6697       visit_load_output(ctx, instr);
6698       break;
6699    case nir_intrinsic_load_per_vertex_input:
6700       visit_load_per_vertex_input(ctx, instr);
6701       break;
6702    case nir_intrinsic_load_per_vertex_output:
6703       visit_load_per_vertex_output(ctx, instr);
6704       break;
6705    case nir_intrinsic_store_per_vertex_output:
6706       visit_store_per_vertex_output(ctx, instr);
6707       break;
6708    case nir_intrinsic_load_ubo:
6709       visit_load_ubo(ctx, instr);
6710       break;
6711    case nir_intrinsic_load_push_constant:
6712       visit_load_push_constant(ctx, instr);
6713       break;
6714    case nir_intrinsic_load_constant:
6715       visit_load_constant(ctx, instr);
6716       break;
6717    case nir_intrinsic_vulkan_resource_index:
6718       visit_load_resource(ctx, instr);
6719       break;
6720    case nir_intrinsic_discard:
6721       visit_discard(ctx, instr);
6722       break;
6723    case nir_intrinsic_discard_if:
6724       visit_discard_if(ctx, instr);
6725       break;
6726    case nir_intrinsic_load_shared:
6727       visit_load_shared(ctx, instr);
6728       break;
6729    case nir_intrinsic_store_shared:
6730       visit_store_shared(ctx, instr);
6731       break;
6732    case nir_intrinsic_shared_atomic_add:
6733    case nir_intrinsic_shared_atomic_imin:
6734    case nir_intrinsic_shared_atomic_umin:
6735    case nir_intrinsic_shared_atomic_imax:
6736    case nir_intrinsic_shared_atomic_umax:
6737    case nir_intrinsic_shared_atomic_and:
6738    case nir_intrinsic_shared_atomic_or:
6739    case nir_intrinsic_shared_atomic_xor:
6740    case nir_intrinsic_shared_atomic_exchange:
6741    case nir_intrinsic_shared_atomic_comp_swap:
6742       visit_shared_atomic(ctx, instr);
6743       break;
6744    case nir_intrinsic_image_deref_load:
6745       visit_image_load(ctx, instr);
6746       break;
6747    case nir_intrinsic_image_deref_store:
6748       visit_image_store(ctx, instr);
6749       break;
6750    case nir_intrinsic_image_deref_atomic_add:
6751    case nir_intrinsic_image_deref_atomic_umin:
6752    case nir_intrinsic_image_deref_atomic_imin:
6753    case nir_intrinsic_image_deref_atomic_umax:
6754    case nir_intrinsic_image_deref_atomic_imax:
6755    case nir_intrinsic_image_deref_atomic_and:
6756    case nir_intrinsic_image_deref_atomic_or:
6757    case nir_intrinsic_image_deref_atomic_xor:
6758    case nir_intrinsic_image_deref_atomic_exchange:
6759    case nir_intrinsic_image_deref_atomic_comp_swap:
6760       visit_image_atomic(ctx, instr);
6761       break;
6762    case nir_intrinsic_image_deref_size:
6763       visit_image_size(ctx, instr);
6764       break;
6765    case nir_intrinsic_load_ssbo:
6766       visit_load_ssbo(ctx, instr);
6767       break;
6768    case nir_intrinsic_store_ssbo:
6769       visit_store_ssbo(ctx, instr);
6770       break;
6771    case nir_intrinsic_load_global:
6772       visit_load_global(ctx, instr);
6773       break;
6774    case nir_intrinsic_store_global:
6775       visit_store_global(ctx, instr);
6776       break;
6777    case nir_intrinsic_global_atomic_add:
6778    case nir_intrinsic_global_atomic_imin:
6779    case nir_intrinsic_global_atomic_umin:
6780    case nir_intrinsic_global_atomic_imax:
6781    case nir_intrinsic_global_atomic_umax:
6782    case nir_intrinsic_global_atomic_and:
6783    case nir_intrinsic_global_atomic_or:
6784    case nir_intrinsic_global_atomic_xor:
6785    case nir_intrinsic_global_atomic_exchange:
6786    case nir_intrinsic_global_atomic_comp_swap:
6787       visit_global_atomic(ctx, instr);
6788       break;
6789    case nir_intrinsic_ssbo_atomic_add:
6790    case nir_intrinsic_ssbo_atomic_imin:
6791    case nir_intrinsic_ssbo_atomic_umin:
6792    case nir_intrinsic_ssbo_atomic_imax:
6793    case nir_intrinsic_ssbo_atomic_umax:
6794    case nir_intrinsic_ssbo_atomic_and:
6795    case nir_intrinsic_ssbo_atomic_or:
6796    case nir_intrinsic_ssbo_atomic_xor:
6797    case nir_intrinsic_ssbo_atomic_exchange:
6798    case nir_intrinsic_ssbo_atomic_comp_swap:
6799       visit_atomic_ssbo(ctx, instr);
6800       break;
6801    case nir_intrinsic_load_scratch:
6802       visit_load_scratch(ctx, instr);
6803       break;
6804    case nir_intrinsic_store_scratch:
6805       visit_store_scratch(ctx, instr);
6806       break;
6807    case nir_intrinsic_get_buffer_size:
6808       visit_get_buffer_size(ctx, instr);
6809       break;
6810    case nir_intrinsic_control_barrier: {
6811       if (ctx->program->chip_class == GFX6 && ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) {
6812          /* GFX6 only (thanks to a hw bug workaround):
6813           * The real barrier instruction isn’t needed, because an entire patch
6814           * always fits into a single wave.
6815           */
6816          break;
6817       }
6818
6819       if (ctx->shader->info.stage == MESA_SHADER_COMPUTE) {
6820          unsigned* bsize = ctx->program->info->cs.block_size;
6821          unsigned workgroup_size = bsize[0] * bsize[1] * bsize[2];
6822          if (workgroup_size > ctx->program->wave_size)
6823             bld.sopp(aco_opcode::s_barrier);
6824       } else if (ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) {
6825          /* For each patch provided during rendering, n TCS shader invocations will be processed,
6826           * where n is the number of vertices in the output patch.
6827           */
6828          unsigned workgroup_size = ctx->tcs_num_patches * ctx->shader->info.tess.tcs_vertices_out;
6829          if (workgroup_size > ctx->program->wave_size)
6830             bld.sopp(aco_opcode::s_barrier);
6831       } else {
6832          /* We don't know the workgroup size, so always emit the s_barrier. */
6833          bld.sopp(aco_opcode::s_barrier);
6834       }
6835
6836       break;
6837    }
6838    case nir_intrinsic_memory_barrier_tcs_patch:
6839    case nir_intrinsic_group_memory_barrier:
6840    case nir_intrinsic_memory_barrier:
6841    case nir_intrinsic_memory_barrier_buffer:
6842    case nir_intrinsic_memory_barrier_image:
6843    case nir_intrinsic_memory_barrier_shared:
6844       emit_memory_barrier(ctx, instr);
6845       break;
6846    case nir_intrinsic_load_num_work_groups: {
6847       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6848       bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.num_work_groups)));
6849       emit_split_vector(ctx, dst, 3);
6850       break;
6851    }
6852    case nir_intrinsic_load_local_invocation_id: {
6853       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6854       bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.local_invocation_ids)));
6855       emit_split_vector(ctx, dst, 3);
6856       break;
6857    }
6858    case nir_intrinsic_load_work_group_id: {
6859       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6860       struct ac_arg *args = ctx->args->ac.workgroup_ids;
6861       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
6862                  args[0].used ? Operand(get_arg(ctx, args[0])) : Operand(0u),
6863                  args[1].used ? Operand(get_arg(ctx, args[1])) : Operand(0u),
6864                  args[2].used ? Operand(get_arg(ctx, args[2])) : Operand(0u));
6865       emit_split_vector(ctx, dst, 3);
6866       break;
6867    }
6868    case nir_intrinsic_load_local_invocation_index: {
6869       Temp id = emit_mbcnt(ctx, bld.def(v1));
6870
6871       /* The tg_size bits [6:11] contain the subgroup id,
6872        * we need this multiplied by the wave size, and then OR the thread id to it.
6873        */
6874       if (ctx->program->wave_size == 64) {
6875          /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
6876          Temp tg_num = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0xfc0u),
6877                                 get_arg(ctx, ctx->args->ac.tg_size));
6878          bld.vop2(aco_opcode::v_or_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), tg_num, id);
6879       } else {
6880          /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR  */
6881          Temp tg_num = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
6882                                 get_arg(ctx, ctx->args->ac.tg_size), Operand(0x6u | (0x6u << 16)));
6883          bld.vop3(aco_opcode::v_lshl_or_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), tg_num, Operand(0x5u), id);
6884       }
6885       break;
6886    }
6887    case nir_intrinsic_load_subgroup_id: {
6888       if (ctx->stage == compute_cs) {
6889          bld.sop2(aco_opcode::s_bfe_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), bld.def(s1, scc),
6890                   get_arg(ctx, ctx->args->ac.tg_size), Operand(0x6u | (0x6u << 16)));
6891       } else {
6892          bld.sop1(aco_opcode::s_mov_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand(0x0u));
6893       }
6894       break;
6895    }
6896    case nir_intrinsic_load_subgroup_invocation: {
6897       emit_mbcnt(ctx, Definition(get_ssa_temp(ctx, &instr->dest.ssa)));
6898       break;
6899    }
6900    case nir_intrinsic_load_num_subgroups: {
6901       if (ctx->stage == compute_cs)
6902          bld.sop2(aco_opcode::s_and_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), bld.def(s1, scc), Operand(0x3fu),
6903                   get_arg(ctx, ctx->args->ac.tg_size));
6904       else
6905          bld.sop1(aco_opcode::s_mov_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand(0x1u));
6906       break;
6907    }
6908    case nir_intrinsic_ballot: {
6909       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6910       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6911       Definition tmp = bld.def(dst.regClass());
6912       Definition lanemask_tmp = dst.size() == bld.lm.size() ? tmp : bld.def(src.regClass());
6913       if (instr->src[0].ssa->bit_size == 1) {
6914          assert(src.regClass() == bld.lm);
6915          bld.sop2(Builder::s_and, lanemask_tmp, bld.def(s1, scc), Operand(exec, bld.lm), src);
6916       } else if (instr->src[0].ssa->bit_size == 32 && src.regClass() == v1) {
6917          bld.vopc(aco_opcode::v_cmp_lg_u32, lanemask_tmp, Operand(0u), src);
6918       } else if (instr->src[0].ssa->bit_size == 64 && src.regClass() == v2) {
6919          bld.vopc(aco_opcode::v_cmp_lg_u64, lanemask_tmp, Operand(0u), src);
6920       } else {
6921          fprintf(stderr, "Unimplemented NIR instr bit size: ");
6922          nir_print_instr(&instr->instr, stderr);
6923          fprintf(stderr, "\n");
6924       }
6925       if (dst.size() != bld.lm.size()) {
6926          /* Wave32 with ballot size set to 64 */
6927          bld.pseudo(aco_opcode::p_create_vector, Definition(tmp), lanemask_tmp.getTemp(), Operand(0u));
6928       }
6929       emit_wqm(ctx, tmp.getTemp(), dst);
6930       break;
6931    }
6932    case nir_intrinsic_shuffle:
6933    case nir_intrinsic_read_invocation: {
6934       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6935       if (!ctx->divergent_vals[instr->src[0].ssa->index]) {
6936          emit_uniform_subgroup(ctx, instr, src);
6937       } else {
6938          Temp tid = get_ssa_temp(ctx, instr->src[1].ssa);
6939          if (instr->intrinsic == nir_intrinsic_read_invocation || !ctx->divergent_vals[instr->src[1].ssa->index])
6940             tid = bld.as_uniform(tid);
6941          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6942          if (src.regClass() == v1) {
6943             emit_wqm(ctx, emit_bpermute(ctx, bld, tid, src), dst);
6944          } else if (src.regClass() == v2) {
6945             Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6946             bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6947             lo = emit_wqm(ctx, emit_bpermute(ctx, bld, tid, lo));
6948             hi = emit_wqm(ctx, emit_bpermute(ctx, bld, tid, hi));
6949             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6950             emit_split_vector(ctx, dst, 2);
6951          } else if (instr->dest.ssa.bit_size == 1 && tid.regClass() == s1) {
6952             assert(src.regClass() == bld.lm);
6953             Temp tmp = bld.sopc(Builder::s_bitcmp1, bld.def(s1, scc), src, tid);
6954             bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
6955          } else if (instr->dest.ssa.bit_size == 1 && tid.regClass() == v1) {
6956             assert(src.regClass() == bld.lm);
6957             Temp tmp;
6958             if (ctx->program->chip_class <= GFX7)
6959                tmp = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), src, tid);
6960             else if (ctx->program->wave_size == 64)
6961                tmp = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), tid, src);
6962             else
6963                tmp = bld.vop2_e64(aco_opcode::v_lshrrev_b32, bld.def(v1), tid, src);
6964             tmp = emit_extract_vector(ctx, tmp, 0, v1);
6965             tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u), tmp);
6966             emit_wqm(ctx, bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp), dst);
6967          } else {
6968             fprintf(stderr, "Unimplemented NIR instr bit size: ");
6969             nir_print_instr(&instr->instr, stderr);
6970             fprintf(stderr, "\n");
6971          }
6972       }
6973       break;
6974    }
6975    case nir_intrinsic_load_sample_id: {
6976       bld.vop3(aco_opcode::v_bfe_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6977                get_arg(ctx, ctx->args->ac.ancillary), Operand(8u), Operand(4u));
6978       break;
6979    }
6980    case nir_intrinsic_load_sample_mask_in: {
6981       visit_load_sample_mask_in(ctx, instr);
6982       break;
6983    }
6984    case nir_intrinsic_read_first_invocation: {
6985       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6986       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6987       if (src.regClass() == v1) {
6988          emit_wqm(ctx,
6989                   bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), src),
6990                   dst);
6991       } else if (src.regClass() == v2) {
6992          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6993          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6994          lo = emit_wqm(ctx, bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), lo));
6995          hi = emit_wqm(ctx, bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), hi));
6996          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6997          emit_split_vector(ctx, dst, 2);
6998       } else if (instr->dest.ssa.bit_size == 1) {
6999          assert(src.regClass() == bld.lm);
7000          Temp tmp = bld.sopc(Builder::s_bitcmp1, bld.def(s1, scc), src,
7001                              bld.sop1(Builder::s_ff1_i32, bld.def(s1), Operand(exec, bld.lm)));
7002          bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
7003       } else if (src.regClass() == s1) {
7004          bld.sop1(aco_opcode::s_mov_b32, Definition(dst), src);
7005       } else if (src.regClass() == s2) {
7006          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src);
7007       } else {
7008          fprintf(stderr, "Unimplemented NIR instr bit size: ");
7009          nir_print_instr(&instr->instr, stderr);
7010          fprintf(stderr, "\n");
7011       }
7012       break;
7013    }
7014    case nir_intrinsic_vote_all: {
7015       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7016       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7017       assert(src.regClass() == bld.lm);
7018       assert(dst.regClass() == bld.lm);
7019
7020       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src).def(1).getTemp();
7021       Temp cond = bool_to_vector_condition(ctx, emit_wqm(ctx, tmp));
7022       bld.sop1(Builder::s_not, Definition(dst), bld.def(s1, scc), cond);
7023       break;
7024    }
7025    case nir_intrinsic_vote_any: {
7026       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7027       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7028       assert(src.regClass() == bld.lm);
7029       assert(dst.regClass() == bld.lm);
7030
7031       Temp tmp = bool_to_scalar_condition(ctx, src);
7032       bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
7033       break;
7034    }
7035    case nir_intrinsic_reduce:
7036    case nir_intrinsic_inclusive_scan:
7037    case nir_intrinsic_exclusive_scan: {
7038       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7039       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7040       nir_op op = (nir_op) nir_intrinsic_reduction_op(instr);
7041       unsigned cluster_size = instr->intrinsic == nir_intrinsic_reduce ?
7042          nir_intrinsic_cluster_size(instr) : 0;
7043       cluster_size = util_next_power_of_two(MIN2(cluster_size ? cluster_size : ctx->program->wave_size, ctx->program->wave_size));
7044
7045       if (!ctx->divergent_vals[instr->src[0].ssa->index] && (op == nir_op_ior || op == nir_op_iand)) {
7046          emit_uniform_subgroup(ctx, instr, src);
7047       } else if (instr->dest.ssa.bit_size == 1) {
7048          if (op == nir_op_imul || op == nir_op_umin || op == nir_op_imin)
7049             op = nir_op_iand;
7050          else if (op == nir_op_iadd)
7051             op = nir_op_ixor;
7052          else if (op == nir_op_umax || op == nir_op_imax)
7053             op = nir_op_ior;
7054          assert(op == nir_op_iand || op == nir_op_ior || op == nir_op_ixor);
7055
7056          switch (instr->intrinsic) {
7057          case nir_intrinsic_reduce:
7058             emit_wqm(ctx, emit_boolean_reduce(ctx, op, cluster_size, src), dst);
7059             break;
7060          case nir_intrinsic_exclusive_scan:
7061             emit_wqm(ctx, emit_boolean_exclusive_scan(ctx, op, src), dst);
7062             break;
7063          case nir_intrinsic_inclusive_scan:
7064             emit_wqm(ctx, emit_boolean_inclusive_scan(ctx, op, src), dst);
7065             break;
7066          default:
7067             assert(false);
7068          }
7069       } else if (cluster_size == 1) {
7070          bld.copy(Definition(dst), src);
7071       } else {
7072          src = as_vgpr(ctx, src);
7073
7074          ReduceOp reduce_op;
7075          switch (op) {
7076          #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
7077             CASE(iadd)
7078             CASE(imul)
7079             CASE(fadd)
7080             CASE(fmul)
7081             CASE(imin)
7082             CASE(umin)
7083             CASE(fmin)
7084             CASE(imax)
7085             CASE(umax)
7086             CASE(fmax)
7087             CASE(iand)
7088             CASE(ior)
7089             CASE(ixor)
7090             default:
7091                unreachable("unknown reduction op");
7092          #undef CASE
7093          }
7094
7095          aco_opcode aco_op;
7096          switch (instr->intrinsic) {
7097             case nir_intrinsic_reduce: aco_op = aco_opcode::p_reduce; break;
7098             case nir_intrinsic_inclusive_scan: aco_op = aco_opcode::p_inclusive_scan; break;
7099             case nir_intrinsic_exclusive_scan: aco_op = aco_opcode::p_exclusive_scan; break;
7100             default:
7101                unreachable("unknown reduce intrinsic");
7102          }
7103
7104          aco_ptr<Pseudo_reduction_instruction> reduce{create_instruction<Pseudo_reduction_instruction>(aco_op, Format::PSEUDO_REDUCTION, 3, 5)};
7105          reduce->operands[0] = Operand(src);
7106          // filled in by aco_reduce_assign.cpp, used internally as part of the
7107          // reduce sequence
7108          assert(dst.size() == 1 || dst.size() == 2);
7109          reduce->operands[1] = Operand(RegClass(RegType::vgpr, dst.size()).as_linear());
7110          reduce->operands[2] = Operand(v1.as_linear());
7111
7112          Temp tmp_dst = bld.tmp(dst.regClass());
7113          reduce->definitions[0] = Definition(tmp_dst);
7114          reduce->definitions[1] = bld.def(ctx->program->lane_mask); // used internally
7115          reduce->definitions[2] = Definition();
7116          reduce->definitions[3] = Definition(scc, s1);
7117          reduce->definitions[4] = Definition();
7118          reduce->reduce_op = reduce_op;
7119          reduce->cluster_size = cluster_size;
7120          ctx->block->instructions.emplace_back(std::move(reduce));
7121
7122          emit_wqm(ctx, tmp_dst, dst);
7123       }
7124       break;
7125    }
7126    case nir_intrinsic_quad_broadcast: {
7127       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7128       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
7129          emit_uniform_subgroup(ctx, instr, src);
7130       } else {
7131          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7132          unsigned lane = nir_src_as_const_value(instr->src[1])->u32;
7133          uint32_t dpp_ctrl = dpp_quad_perm(lane, lane, lane, lane);
7134
7135          if (instr->dest.ssa.bit_size == 1) {
7136             assert(src.regClass() == bld.lm);
7137             assert(dst.regClass() == bld.lm);
7138             uint32_t half_mask = 0x11111111u << lane;
7139             Temp mask_tmp = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(half_mask), Operand(half_mask));
7140             Temp tmp = bld.tmp(bld.lm);
7141             bld.sop1(Builder::s_wqm, Definition(tmp),
7142                      bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), mask_tmp,
7143                               bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm))));
7144             emit_wqm(ctx, tmp, dst);
7145          } else if (instr->dest.ssa.bit_size == 32) {
7146             if (ctx->program->chip_class >= GFX8)
7147                emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl), dst);
7148             else
7149                emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl), dst);
7150          } else if (instr->dest.ssa.bit_size == 64) {
7151             Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
7152             bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
7153             if (ctx->program->chip_class >= GFX8) {
7154                lo = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), lo, dpp_ctrl));
7155                hi = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), hi, dpp_ctrl));
7156             } else {
7157                lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, (1 << 15) | dpp_ctrl));
7158                hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, (1 << 15) | dpp_ctrl));
7159             }
7160             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
7161             emit_split_vector(ctx, dst, 2);
7162          } else {
7163             fprintf(stderr, "Unimplemented NIR instr bit size: ");
7164             nir_print_instr(&instr->instr, stderr);
7165             fprintf(stderr, "\n");
7166          }
7167       }
7168       break;
7169    }
7170    case nir_intrinsic_quad_swap_horizontal:
7171    case nir_intrinsic_quad_swap_vertical:
7172    case nir_intrinsic_quad_swap_diagonal:
7173    case nir_intrinsic_quad_swizzle_amd: {
7174       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7175       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
7176          emit_uniform_subgroup(ctx, instr, src);
7177          break;
7178       }
7179       uint16_t dpp_ctrl = 0;
7180       switch (instr->intrinsic) {
7181       case nir_intrinsic_quad_swap_horizontal:
7182          dpp_ctrl = dpp_quad_perm(1, 0, 3, 2);
7183          break;
7184       case nir_intrinsic_quad_swap_vertical:
7185          dpp_ctrl = dpp_quad_perm(2, 3, 0, 1);
7186          break;
7187       case nir_intrinsic_quad_swap_diagonal:
7188          dpp_ctrl = dpp_quad_perm(3, 2, 1, 0);
7189          break;
7190       case nir_intrinsic_quad_swizzle_amd:
7191          dpp_ctrl = nir_intrinsic_swizzle_mask(instr);
7192          break;
7193       default:
7194          break;
7195       }
7196       if (ctx->program->chip_class < GFX8)
7197          dpp_ctrl |= (1 << 15);
7198
7199       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7200       if (instr->dest.ssa.bit_size == 1) {
7201          assert(src.regClass() == bld.lm);
7202          src = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand((uint32_t)-1), src);
7203          if (ctx->program->chip_class >= GFX8)
7204             src = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl);
7205          else
7206             src = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, dpp_ctrl);
7207          Temp tmp = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), src);
7208          emit_wqm(ctx, tmp, dst);
7209       } else if (instr->dest.ssa.bit_size == 32) {
7210          Temp tmp;
7211          if (ctx->program->chip_class >= GFX8)
7212             tmp = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl);
7213          else
7214             tmp = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, dpp_ctrl);
7215          emit_wqm(ctx, tmp, dst);
7216       } else if (instr->dest.ssa.bit_size == 64) {
7217          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
7218          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
7219          if (ctx->program->chip_class >= GFX8) {
7220             lo = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), lo, dpp_ctrl));
7221             hi = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), hi, dpp_ctrl));
7222          } else {
7223             lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, dpp_ctrl));
7224             hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, dpp_ctrl));
7225          }
7226          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
7227          emit_split_vector(ctx, dst, 2);
7228       } else {
7229          fprintf(stderr, "Unimplemented NIR instr bit size: ");
7230          nir_print_instr(&instr->instr, stderr);
7231          fprintf(stderr, "\n");
7232       }
7233       break;
7234    }
7235    case nir_intrinsic_masked_swizzle_amd: {
7236       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7237       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
7238          emit_uniform_subgroup(ctx, instr, src);
7239          break;
7240       }
7241       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7242       uint32_t mask = nir_intrinsic_swizzle_mask(instr);
7243       if (dst.regClass() == v1) {
7244          emit_wqm(ctx,
7245                   bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, mask, 0, false),
7246                   dst);
7247       } else if (dst.regClass() == v2) {
7248          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
7249          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
7250          lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, mask, 0, false));
7251          hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, mask, 0, false));
7252          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
7253          emit_split_vector(ctx, dst, 2);
7254       } else {
7255          fprintf(stderr, "Unimplemented NIR instr bit size: ");
7256          nir_print_instr(&instr->instr, stderr);
7257          fprintf(stderr, "\n");
7258       }
7259       break;
7260    }
7261    case nir_intrinsic_write_invocation_amd: {
7262       Temp src = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
7263       Temp val = bld.as_uniform(get_ssa_temp(ctx, instr->src[1].ssa));
7264       Temp lane = bld.as_uniform(get_ssa_temp(ctx, instr->src[2].ssa));
7265       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7266       if (dst.regClass() == v1) {
7267          /* src2 is ignored for writelane. RA assigns the same reg for dst */
7268          emit_wqm(ctx, bld.writelane(bld.def(v1), val, lane, src), dst);
7269       } else if (dst.regClass() == v2) {
7270          Temp src_lo = bld.tmp(v1), src_hi = bld.tmp(v1);
7271          Temp val_lo = bld.tmp(s1), val_hi = bld.tmp(s1);
7272          bld.pseudo(aco_opcode::p_split_vector, Definition(src_lo), Definition(src_hi), src);
7273          bld.pseudo(aco_opcode::p_split_vector, Definition(val_lo), Definition(val_hi), val);
7274          Temp lo = emit_wqm(ctx, bld.writelane(bld.def(v1), val_lo, lane, src_hi));
7275          Temp hi = emit_wqm(ctx, bld.writelane(bld.def(v1), val_hi, lane, src_hi));
7276          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
7277          emit_split_vector(ctx, dst, 2);
7278       } else {
7279          fprintf(stderr, "Unimplemented NIR instr bit size: ");
7280          nir_print_instr(&instr->instr, stderr);
7281          fprintf(stderr, "\n");
7282       }
7283       break;
7284    }
7285    case nir_intrinsic_mbcnt_amd: {
7286       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7287       RegClass rc = RegClass(src.type(), 1);
7288       Temp mask_lo = bld.tmp(rc), mask_hi = bld.tmp(rc);
7289       bld.pseudo(aco_opcode::p_split_vector, Definition(mask_lo), Definition(mask_hi), src);
7290       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7291       Temp wqm_tmp = emit_mbcnt(ctx, bld.def(v1), Operand(mask_lo), Operand(mask_hi));
7292       emit_wqm(ctx, wqm_tmp, dst);
7293       break;
7294    }
7295    case nir_intrinsic_load_helper_invocation: {
7296       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7297       bld.pseudo(aco_opcode::p_load_helper, Definition(dst));
7298       ctx->block->kind |= block_kind_needs_lowering;
7299       ctx->program->needs_exact = true;
7300       break;
7301    }
7302    case nir_intrinsic_is_helper_invocation: {
7303       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7304       bld.pseudo(aco_opcode::p_is_helper, Definition(dst));
7305       ctx->block->kind |= block_kind_needs_lowering;
7306       ctx->program->needs_exact = true;
7307       break;
7308    }
7309    case nir_intrinsic_demote:
7310       bld.pseudo(aco_opcode::p_demote_to_helper, Operand(-1u));
7311
7312       if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
7313          ctx->cf_info.exec_potentially_empty_discard = true;
7314       ctx->block->kind |= block_kind_uses_demote;
7315       ctx->program->needs_exact = true;
7316       break;
7317    case nir_intrinsic_demote_if: {
7318       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7319       assert(src.regClass() == bld.lm);
7320       Temp cond = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
7321       bld.pseudo(aco_opcode::p_demote_to_helper, cond);
7322
7323       if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
7324          ctx->cf_info.exec_potentially_empty_discard = true;
7325       ctx->block->kind |= block_kind_uses_demote;
7326       ctx->program->needs_exact = true;
7327       break;
7328    }
7329    case nir_intrinsic_first_invocation: {
7330       emit_wqm(ctx, bld.sop1(Builder::s_ff1_i32, bld.def(s1), Operand(exec, bld.lm)),
7331                get_ssa_temp(ctx, &instr->dest.ssa));
7332       break;
7333    }
7334    case nir_intrinsic_shader_clock:
7335       bld.smem(aco_opcode::s_memtime, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), false);
7336       emit_split_vector(ctx, get_ssa_temp(ctx, &instr->dest.ssa), 2);
7337       break;
7338    case nir_intrinsic_load_vertex_id_zero_base: {
7339       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7340       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.vertex_id));
7341       break;
7342    }
7343    case nir_intrinsic_load_first_vertex: {
7344       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7345       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.base_vertex));
7346       break;
7347    }
7348    case nir_intrinsic_load_base_instance: {
7349       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7350       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.start_instance));
7351       break;
7352    }
7353    case nir_intrinsic_load_instance_id: {
7354       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7355       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.instance_id));
7356       break;
7357    }
7358    case nir_intrinsic_load_draw_id: {
7359       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7360       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.draw_id));
7361       break;
7362    }
7363    case nir_intrinsic_load_invocation_id: {
7364       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7365
7366       if (ctx->shader->info.stage == MESA_SHADER_GEOMETRY) {
7367          if (ctx->options->chip_class >= GFX10)
7368             bld.vop2_e64(aco_opcode::v_and_b32, Definition(dst), Operand(127u), get_arg(ctx, ctx->args->ac.gs_invocation_id));
7369          else
7370             bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.gs_invocation_id));
7371       } else if (ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) {
7372          bld.vop3(aco_opcode::v_bfe_u32, Definition(dst),
7373                   get_arg(ctx, ctx->args->ac.tcs_rel_ids), Operand(8u), Operand(5u));
7374       } else {
7375          unreachable("Unsupported stage for load_invocation_id");
7376       }
7377
7378       break;
7379    }
7380    case nir_intrinsic_load_primitive_id: {
7381       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7382
7383       switch (ctx->shader->info.stage) {
7384       case MESA_SHADER_GEOMETRY:
7385          bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.gs_prim_id));
7386          break;
7387       case MESA_SHADER_TESS_CTRL:
7388          bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.tcs_patch_id));
7389          break;
7390       case MESA_SHADER_TESS_EVAL:
7391          bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.tes_patch_id));
7392          break;
7393       default:
7394          unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
7395       }
7396
7397       break;
7398    }
7399    case nir_intrinsic_load_patch_vertices_in: {
7400       assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL ||
7401              ctx->shader->info.stage == MESA_SHADER_TESS_EVAL);
7402
7403       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7404       bld.copy(Definition(dst), Operand(ctx->args->options->key.tcs.input_vertices));
7405       break;
7406    }
7407    case nir_intrinsic_emit_vertex_with_counter: {
7408       visit_emit_vertex_with_counter(ctx, instr);
7409       break;
7410    }
7411    case nir_intrinsic_end_primitive_with_counter: {
7412       unsigned stream = nir_intrinsic_stream_id(instr);
7413       bld.sopp(aco_opcode::s_sendmsg, bld.m0(ctx->gs_wave_id), -1, sendmsg_gs(true, false, stream));
7414       break;
7415    }
7416    case nir_intrinsic_set_vertex_count: {
7417       /* unused, the HW keeps track of this for us */
7418       break;
7419    }
7420    default:
7421       fprintf(stderr, "Unimplemented intrinsic instr: ");
7422       nir_print_instr(&instr->instr, stderr);
7423       fprintf(stderr, "\n");
7424       abort();
7425
7426       break;
7427    }
7428 }
7429
7430
7431 void tex_fetch_ptrs(isel_context *ctx, nir_tex_instr *instr,
7432                     Temp *res_ptr, Temp *samp_ptr, Temp *fmask_ptr,
7433                     enum glsl_base_type *stype)
7434 {
7435    nir_deref_instr *texture_deref_instr = NULL;
7436    nir_deref_instr *sampler_deref_instr = NULL;
7437    int plane = -1;
7438
7439    for (unsigned i = 0; i < instr->num_srcs; i++) {
7440       switch (instr->src[i].src_type) {
7441       case nir_tex_src_texture_deref:
7442          texture_deref_instr = nir_src_as_deref(instr->src[i].src);
7443          break;
7444       case nir_tex_src_sampler_deref:
7445          sampler_deref_instr = nir_src_as_deref(instr->src[i].src);
7446          break;
7447       case nir_tex_src_plane:
7448          plane = nir_src_as_int(instr->src[i].src);
7449          break;
7450       default:
7451          break;
7452       }
7453    }
7454
7455    *stype = glsl_get_sampler_result_type(texture_deref_instr->type);
7456
7457    if (!sampler_deref_instr)
7458       sampler_deref_instr = texture_deref_instr;
7459
7460    if (plane >= 0) {
7461       assert(instr->op != nir_texop_txf_ms &&
7462              instr->op != nir_texop_samples_identical);
7463       assert(instr->sampler_dim  != GLSL_SAMPLER_DIM_BUF);
7464       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, (aco_descriptor_type)(ACO_DESC_PLANE_0 + plane), instr, false, false);
7465    } else if (instr->sampler_dim  == GLSL_SAMPLER_DIM_BUF) {
7466       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_BUFFER, instr, false, false);
7467    } else if (instr->op == nir_texop_fragment_mask_fetch) {
7468       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_FMASK, instr, false, false);
7469    } else {
7470       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_IMAGE, instr, false, false);
7471    }
7472    if (samp_ptr) {
7473       *samp_ptr = get_sampler_desc(ctx, sampler_deref_instr, ACO_DESC_SAMPLER, instr, false, false);
7474
7475       if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT && ctx->options->chip_class < GFX8) {
7476          /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
7477          Builder bld(ctx->program, ctx->block);
7478
7479          /* to avoid unnecessary moves, we split and recombine sampler and image */
7480          Temp img[8] = {bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1),
7481                         bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1)};
7482          Temp samp[4] = {bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1)};
7483          bld.pseudo(aco_opcode::p_split_vector, Definition(img[0]), Definition(img[1]),
7484                     Definition(img[2]), Definition(img[3]), Definition(img[4]),
7485                     Definition(img[5]), Definition(img[6]), Definition(img[7]), *res_ptr);
7486          bld.pseudo(aco_opcode::p_split_vector, Definition(samp[0]), Definition(samp[1]),
7487                     Definition(samp[2]), Definition(samp[3]), *samp_ptr);
7488
7489          samp[0] = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), samp[0], img[7]);
7490          *res_ptr = bld.pseudo(aco_opcode::p_create_vector, bld.def(s8),
7491                                img[0], img[1], img[2], img[3],
7492                                img[4], img[5], img[6], img[7]);
7493          *samp_ptr = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
7494                                 samp[0], samp[1], samp[2], samp[3]);
7495       }
7496    }
7497    if (fmask_ptr && (instr->op == nir_texop_txf_ms ||
7498                      instr->op == nir_texop_samples_identical))
7499       *fmask_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_FMASK, instr, false, false);
7500 }
7501
7502 void build_cube_select(isel_context *ctx, Temp ma, Temp id, Temp deriv,
7503                        Temp *out_ma, Temp *out_sc, Temp *out_tc)
7504 {
7505    Builder bld(ctx->program, ctx->block);
7506
7507    Temp deriv_x = emit_extract_vector(ctx, deriv, 0, v1);
7508    Temp deriv_y = emit_extract_vector(ctx, deriv, 1, v1);
7509    Temp deriv_z = emit_extract_vector(ctx, deriv, 2, v1);
7510
7511    Operand neg_one(0xbf800000u);
7512    Operand one(0x3f800000u);
7513    Operand two(0x40000000u);
7514    Operand four(0x40800000u);
7515
7516    Temp is_ma_positive = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), ma);
7517    Temp sgn_ma = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), neg_one, one, is_ma_positive);
7518    Temp neg_sgn_ma = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), Operand(0u), sgn_ma);
7519
7520    Temp is_ma_z = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), four, id);
7521    Temp is_ma_y = bld.vopc(aco_opcode::v_cmp_le_f32, bld.def(bld.lm), two, id);
7522    is_ma_y = bld.sop2(Builder::s_andn2, bld.hint_vcc(bld.def(bld.lm)), is_ma_y, is_ma_z);
7523    Temp is_not_ma_x = bld.sop2(aco_opcode::s_or_b64, bld.hint_vcc(bld.def(bld.lm)), bld.def(s1, scc), is_ma_z, is_ma_y);
7524
7525    // select sc
7526    Temp tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_z, deriv_x, is_not_ma_x);
7527    Temp sgn = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1),
7528                        bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), neg_sgn_ma, sgn_ma, is_ma_z),
7529                        one, is_ma_y);
7530    *out_sc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tmp, sgn);
7531
7532    // select tc
7533    tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_y, deriv_z, is_ma_y);
7534    sgn = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), neg_one, sgn_ma, is_ma_y);
7535    *out_tc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tmp, sgn);
7536
7537    // select ma
7538    tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
7539                   bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_x, deriv_y, is_ma_y),
7540                   deriv_z, is_ma_z);
7541    tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffffu), tmp);
7542    *out_ma = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), two, tmp);
7543 }
7544
7545 void prepare_cube_coords(isel_context *ctx, std::vector<Temp>& coords, Temp* ddx, Temp* ddy, bool is_deriv, bool is_array)
7546 {
7547    Builder bld(ctx->program, ctx->block);
7548    Temp ma, tc, sc, id;
7549
7550    if (is_array) {
7551       coords[3] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coords[3]);
7552
7553       // see comment in ac_prepare_cube_coords()
7554       if (ctx->options->chip_class <= GFX8)
7555          coords[3] = bld.vop2(aco_opcode::v_max_f32, bld.def(v1), Operand(0u), coords[3]);
7556    }
7557
7558    ma = bld.vop3(aco_opcode::v_cubema_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7559
7560    aco_ptr<VOP3A_instruction> vop3a{create_instruction<VOP3A_instruction>(aco_opcode::v_rcp_f32, asVOP3(Format::VOP1), 1, 1)};
7561    vop3a->operands[0] = Operand(ma);
7562    vop3a->abs[0] = true;
7563    Temp invma = bld.tmp(v1);
7564    vop3a->definitions[0] = Definition(invma);
7565    ctx->block->instructions.emplace_back(std::move(vop3a));
7566
7567    sc = bld.vop3(aco_opcode::v_cubesc_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7568    if (!is_deriv)
7569       sc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), sc, invma, Operand(0x3fc00000u/*1.5*/));
7570
7571    tc = bld.vop3(aco_opcode::v_cubetc_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7572    if (!is_deriv)
7573       tc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), tc, invma, Operand(0x3fc00000u/*1.5*/));
7574
7575    id = bld.vop3(aco_opcode::v_cubeid_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7576
7577    if (is_deriv) {
7578       sc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), sc, invma);
7579       tc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tc, invma);
7580
7581       for (unsigned i = 0; i < 2; i++) {
7582          // see comment in ac_prepare_cube_coords()
7583          Temp deriv_ma;
7584          Temp deriv_sc, deriv_tc;
7585          build_cube_select(ctx, ma, id, i ? *ddy : *ddx,
7586                            &deriv_ma, &deriv_sc, &deriv_tc);
7587
7588          deriv_ma = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, invma);
7589
7590          Temp x = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1),
7591                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_sc, invma),
7592                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, sc));
7593          Temp y = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1),
7594                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_tc, invma),
7595                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, tc));
7596          *(i ? ddy : ddx) = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), x, y);
7597       }
7598
7599       sc = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), Operand(0x3fc00000u/*1.5*/), sc);
7600       tc = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), Operand(0x3fc00000u/*1.5*/), tc);
7601    }
7602
7603    if (is_array)
7604       id = bld.vop2(aco_opcode::v_madmk_f32, bld.def(v1), coords[3], id, Operand(0x41000000u/*8.0*/));
7605    coords.resize(3);
7606    coords[0] = sc;
7607    coords[1] = tc;
7608    coords[2] = id;
7609 }
7610
7611 void get_const_vec(nir_ssa_def *vec, nir_const_value *cv[4])
7612 {
7613    if (vec->parent_instr->type != nir_instr_type_alu)
7614       return;
7615    nir_alu_instr *vec_instr = nir_instr_as_alu(vec->parent_instr);
7616    if (vec_instr->op != nir_op_vec(vec->num_components))
7617       return;
7618
7619    for (unsigned i = 0; i < vec->num_components; i++) {
7620       cv[i] = vec_instr->src[i].swizzle[0] == 0 ?
7621               nir_src_as_const_value(vec_instr->src[i].src) : NULL;
7622    }
7623 }
7624
7625 void visit_tex(isel_context *ctx, nir_tex_instr *instr)
7626 {
7627    Builder bld(ctx->program, ctx->block);
7628    bool has_bias = false, has_lod = false, level_zero = false, has_compare = false,
7629         has_offset = false, has_ddx = false, has_ddy = false, has_derivs = false, has_sample_index = false;
7630    Temp resource, sampler, fmask_ptr, bias = Temp(), compare = Temp(), sample_index = Temp(),
7631         lod = Temp(), offset = Temp(), ddx = Temp(), ddy = Temp();
7632    std::vector<Temp> coords;
7633    std::vector<Temp> derivs;
7634    nir_const_value *sample_index_cv = NULL;
7635    nir_const_value *const_offset[4] = {NULL, NULL, NULL, NULL};
7636    enum glsl_base_type stype;
7637    tex_fetch_ptrs(ctx, instr, &resource, &sampler, &fmask_ptr, &stype);
7638
7639    bool tg4_integer_workarounds = ctx->options->chip_class <= GFX8 && instr->op == nir_texop_tg4 &&
7640                                   (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT);
7641    bool tg4_integer_cube_workaround = tg4_integer_workarounds &&
7642                                       instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
7643
7644    for (unsigned i = 0; i < instr->num_srcs; i++) {
7645       switch (instr->src[i].src_type) {
7646       case nir_tex_src_coord: {
7647          Temp coord = get_ssa_temp(ctx, instr->src[i].src.ssa);
7648          for (unsigned i = 0; i < coord.size(); i++)
7649             coords.emplace_back(emit_extract_vector(ctx, coord, i, v1));
7650          break;
7651       }
7652       case nir_tex_src_bias:
7653          if (instr->op == nir_texop_txb) {
7654             bias = get_ssa_temp(ctx, instr->src[i].src.ssa);
7655             has_bias = true;
7656          }
7657          break;
7658       case nir_tex_src_lod: {
7659          nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
7660
7661          if (val && val->f32 <= 0.0) {
7662             level_zero = true;
7663          } else {
7664             lod = get_ssa_temp(ctx, instr->src[i].src.ssa);
7665             has_lod = true;
7666          }
7667          break;
7668       }
7669       case nir_tex_src_comparator:
7670          if (instr->is_shadow) {
7671             compare = get_ssa_temp(ctx, instr->src[i].src.ssa);
7672             has_compare = true;
7673          }
7674          break;
7675       case nir_tex_src_offset:
7676          offset = get_ssa_temp(ctx, instr->src[i].src.ssa);
7677          get_const_vec(instr->src[i].src.ssa, const_offset);
7678          has_offset = true;
7679          break;
7680       case nir_tex_src_ddx:
7681          ddx = get_ssa_temp(ctx, instr->src[i].src.ssa);
7682          has_ddx = true;
7683          break;
7684       case nir_tex_src_ddy:
7685          ddy = get_ssa_temp(ctx, instr->src[i].src.ssa);
7686          has_ddy = true;
7687          break;
7688       case nir_tex_src_ms_index:
7689          sample_index = get_ssa_temp(ctx, instr->src[i].src.ssa);
7690          sample_index_cv = nir_src_as_const_value(instr->src[i].src);
7691          has_sample_index = true;
7692          break;
7693       case nir_tex_src_texture_offset:
7694       case nir_tex_src_sampler_offset:
7695       default:
7696          break;
7697       }
7698    }
7699
7700    if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
7701       return get_buffer_size(ctx, resource, get_ssa_temp(ctx, &instr->dest.ssa), true);
7702
7703    if (instr->op == nir_texop_texture_samples) {
7704       Temp dword3 = emit_extract_vector(ctx, resource, 3, s1);
7705
7706       Temp samples_log2 = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), dword3, Operand(16u | 4u<<16));
7707       Temp samples = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), Operand(1u), samples_log2);
7708       Temp type = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), dword3, Operand(28u | 4u<<16 /* offset=28, width=4 */));
7709       Temp is_msaa = bld.sopc(aco_opcode::s_cmp_ge_u32, bld.def(s1, scc), type, Operand(14u));
7710
7711       bld.sop2(aco_opcode::s_cselect_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
7712                samples, Operand(1u), bld.scc(is_msaa));
7713       return;
7714    }
7715
7716    if (has_offset && instr->op != nir_texop_txf && instr->op != nir_texop_txf_ms) {
7717       aco_ptr<Instruction> tmp_instr;
7718       Temp acc, pack = Temp();
7719
7720       uint32_t pack_const = 0;
7721       for (unsigned i = 0; i < offset.size(); i++) {
7722          if (!const_offset[i])
7723             continue;
7724          pack_const |= (const_offset[i]->u32 & 0x3Fu) << (8u * i);
7725       }
7726
7727       if (offset.type() == RegType::sgpr) {
7728          for (unsigned i = 0; i < offset.size(); i++) {
7729             if (const_offset[i])
7730                continue;
7731
7732             acc = emit_extract_vector(ctx, offset, i, s1);
7733             acc = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), acc, Operand(0x3Fu));
7734
7735             if (i) {
7736                acc = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), acc, Operand(8u * i));
7737             }
7738
7739             if (pack == Temp()) {
7740                pack = acc;
7741             } else {
7742                pack = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), pack, acc);
7743             }
7744          }
7745
7746          if (pack_const && pack != Temp())
7747             pack = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(pack_const), pack);
7748       } else {
7749          for (unsigned i = 0; i < offset.size(); i++) {
7750             if (const_offset[i])
7751                continue;
7752
7753             acc = emit_extract_vector(ctx, offset, i, v1);
7754             acc = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x3Fu), acc);
7755
7756             if (i) {
7757                acc = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(8u * i), acc);
7758             }
7759
7760             if (pack == Temp()) {
7761                pack = acc;
7762             } else {
7763                pack = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), pack, acc);
7764             }
7765          }
7766
7767          if (pack_const && pack != Temp())
7768             pack = bld.sop2(aco_opcode::v_or_b32, bld.def(v1), Operand(pack_const), pack);
7769       }
7770       if (pack_const && pack == Temp())
7771          offset = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(pack_const));
7772       else if (pack == Temp())
7773          has_offset = false;
7774       else
7775          offset = pack;
7776    }
7777
7778    if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && instr->coord_components)
7779       prepare_cube_coords(ctx, coords, &ddx, &ddy, instr->op == nir_texop_txd, instr->is_array && instr->op != nir_texop_lod);
7780
7781    /* pack derivatives */
7782    if (has_ddx || has_ddy) {
7783       if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && ctx->options->chip_class == GFX9) {
7784          assert(has_ddx && has_ddy && ddx.size() == 1 && ddy.size() == 1);
7785          Temp zero = bld.copy(bld.def(v1), Operand(0u));
7786          derivs = {ddy, zero, ddy, zero};
7787       } else {
7788          for (unsigned i = 0; has_ddx && i < ddx.size(); i++)
7789             derivs.emplace_back(emit_extract_vector(ctx, ddx, i, v1));
7790          for (unsigned i = 0; has_ddy && i < ddy.size(); i++)
7791             derivs.emplace_back(emit_extract_vector(ctx, ddy, i, v1));
7792       }
7793       has_derivs = true;
7794    }
7795
7796    if (instr->coord_components > 1 &&
7797        instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
7798        instr->is_array &&
7799        instr->op != nir_texop_txf)
7800       coords[1] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coords[1]);
7801
7802    if (instr->coord_components > 2 &&
7803       (instr->sampler_dim == GLSL_SAMPLER_DIM_2D ||
7804        instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
7805        instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS ||
7806        instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
7807        instr->is_array &&
7808        instr->op != nir_texop_txf &&
7809        instr->op != nir_texop_txf_ms &&
7810        instr->op != nir_texop_fragment_fetch &&
7811        instr->op != nir_texop_fragment_mask_fetch)
7812       coords[2] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coords[2]);
7813
7814    if (ctx->options->chip_class == GFX9 &&
7815        instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
7816        instr->op != nir_texop_lod && instr->coord_components) {
7817       assert(coords.size() > 0 && coords.size() < 3);
7818
7819       coords.insert(std::next(coords.begin()), bld.copy(bld.def(v1), instr->op == nir_texop_txf ?
7820                                                                      Operand((uint32_t) 0) :
7821                                                                      Operand((uint32_t) 0x3f000000)));
7822    }
7823
7824    bool da = should_declare_array(ctx, instr->sampler_dim, instr->is_array);
7825
7826    if (instr->op == nir_texop_samples_identical)
7827       resource = fmask_ptr;
7828
7829    else if ((instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
7830              instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
7831             instr->op != nir_texop_txs &&
7832             instr->op != nir_texop_fragment_fetch &&
7833             instr->op != nir_texop_fragment_mask_fetch) {
7834       assert(has_sample_index);
7835       Operand op(sample_index);
7836       if (sample_index_cv)
7837          op = Operand(sample_index_cv->u32);
7838       sample_index = adjust_sample_index_using_fmask(ctx, da, coords, op, fmask_ptr);
7839    }
7840
7841    if (has_offset && (instr->op == nir_texop_txf || instr->op == nir_texop_txf_ms)) {
7842       for (unsigned i = 0; i < std::min(offset.size(), instr->coord_components); i++) {
7843          Temp off = emit_extract_vector(ctx, offset, i, v1);
7844          coords[i] = bld.vadd32(bld.def(v1), coords[i], off);
7845       }
7846       has_offset = false;
7847    }
7848
7849    /* Build tex instruction */
7850    unsigned dmask = nir_ssa_def_components_read(&instr->dest.ssa);
7851    unsigned dim = ctx->options->chip_class >= GFX10 && instr->sampler_dim != GLSL_SAMPLER_DIM_BUF
7852                   ? ac_get_sampler_dim(ctx->options->chip_class, instr->sampler_dim, instr->is_array)
7853                   : 0;
7854    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7855    Temp tmp_dst = dst;
7856
7857    /* gather4 selects the component by dmask and always returns vec4 */
7858    if (instr->op == nir_texop_tg4) {
7859       assert(instr->dest.ssa.num_components == 4);
7860       if (instr->is_shadow)
7861          dmask = 1;
7862       else
7863          dmask = 1 << instr->component;
7864       if (tg4_integer_cube_workaround || dst.type() == RegType::sgpr)
7865          tmp_dst = bld.tmp(v4);
7866    } else if (instr->op == nir_texop_samples_identical) {
7867       tmp_dst = bld.tmp(v1);
7868    } else if (util_bitcount(dmask) != instr->dest.ssa.num_components || dst.type() == RegType::sgpr) {
7869       tmp_dst = bld.tmp(RegClass(RegType::vgpr, util_bitcount(dmask)));
7870    }
7871
7872    aco_ptr<MIMG_instruction> tex;
7873    if (instr->op == nir_texop_txs || instr->op == nir_texop_query_levels) {
7874       if (!has_lod)
7875          lod = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
7876
7877       bool div_by_6 = instr->op == nir_texop_txs &&
7878                       instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
7879                       instr->is_array &&
7880                       (dmask & (1 << 2));
7881       if (tmp_dst.id() == dst.id() && div_by_6)
7882          tmp_dst = bld.tmp(tmp_dst.regClass());
7883
7884       tex.reset(create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 3, 1));
7885       tex->operands[0] = Operand(resource);
7886       tex->operands[1] = Operand(s4); /* no sampler */
7887       tex->operands[2] = Operand(as_vgpr(ctx,lod));
7888       if (ctx->options->chip_class == GFX9 &&
7889           instr->op == nir_texop_txs &&
7890           instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
7891           instr->is_array) {
7892          tex->dmask = (dmask & 0x1) | ((dmask & 0x2) << 1);
7893       } else if (instr->op == nir_texop_query_levels) {
7894          tex->dmask = 1 << 3;
7895       } else {
7896          tex->dmask = dmask;
7897       }
7898       tex->da = da;
7899       tex->definitions[0] = Definition(tmp_dst);
7900       tex->dim = dim;
7901       tex->can_reorder = true;
7902       ctx->block->instructions.emplace_back(std::move(tex));
7903
7904       if (div_by_6) {
7905          /* divide 3rd value by 6 by multiplying with magic number */
7906          emit_split_vector(ctx, tmp_dst, tmp_dst.size());
7907          Temp c = bld.copy(bld.def(s1), Operand((uint32_t) 0x2AAAAAAB));
7908          Temp by_6 = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), emit_extract_vector(ctx, tmp_dst, 2, v1), c);
7909          assert(instr->dest.ssa.num_components == 3);
7910          Temp tmp = dst.type() == RegType::vgpr ? dst : bld.tmp(v3);
7911          tmp_dst = bld.pseudo(aco_opcode::p_create_vector, Definition(tmp),
7912                               emit_extract_vector(ctx, tmp_dst, 0, v1),
7913                               emit_extract_vector(ctx, tmp_dst, 1, v1),
7914                               by_6);
7915
7916       }
7917
7918       expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, dmask);
7919       return;
7920    }
7921
7922    Temp tg4_compare_cube_wa64 = Temp();
7923
7924    if (tg4_integer_workarounds) {
7925       tex.reset(create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 3, 1));
7926       tex->operands[0] = Operand(resource);
7927       tex->operands[1] = Operand(s4); /* no sampler */
7928       tex->operands[2] = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
7929       tex->dim = dim;
7930       tex->dmask = 0x3;
7931       tex->da = da;
7932       Temp size = bld.tmp(v2);
7933       tex->definitions[0] = Definition(size);
7934       tex->can_reorder = true;
7935       ctx->block->instructions.emplace_back(std::move(tex));
7936       emit_split_vector(ctx, size, size.size());
7937
7938       Temp half_texel[2];
7939       for (unsigned i = 0; i < 2; i++) {
7940          half_texel[i] = emit_extract_vector(ctx, size, i, v1);
7941          half_texel[i] = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), half_texel[i]);
7942          half_texel[i] = bld.vop1(aco_opcode::v_rcp_iflag_f32, bld.def(v1), half_texel[i]);
7943          half_texel[i] = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0xbf000000/*-0.5*/), half_texel[i]);
7944       }
7945
7946       Temp new_coords[2] = {
7947          bld.vop2(aco_opcode::v_add_f32, bld.def(v1), coords[0], half_texel[0]),
7948          bld.vop2(aco_opcode::v_add_f32, bld.def(v1), coords[1], half_texel[1])
7949       };
7950
7951       if (tg4_integer_cube_workaround) {
7952          // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
7953          Temp desc[resource.size()];
7954          aco_ptr<Instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector,
7955                                                                            Format::PSEUDO, 1, resource.size())};
7956          split->operands[0] = Operand(resource);
7957          for (unsigned i = 0; i < resource.size(); i++) {
7958             desc[i] = bld.tmp(s1);
7959             split->definitions[i] = Definition(desc[i]);
7960          }
7961          ctx->block->instructions.emplace_back(std::move(split));
7962
7963          Temp dfmt = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), desc[1], Operand(20u | (6u << 16)));
7964          Temp compare_cube_wa = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), dfmt,
7965                                          Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8));
7966
7967          Temp nfmt;
7968          if (stype == GLSL_TYPE_UINT) {
7969             nfmt = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1),
7970                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED),
7971                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT),
7972                             bld.scc(compare_cube_wa));
7973          } else {
7974             nfmt = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1),
7975                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED),
7976                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT),
7977                             bld.scc(compare_cube_wa));
7978          }
7979          tg4_compare_cube_wa64 = bld.tmp(bld.lm);
7980          bool_to_vector_condition(ctx, compare_cube_wa, tg4_compare_cube_wa64);
7981
7982          nfmt = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), nfmt, Operand(26u));
7983
7984          desc[1] = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), desc[1],
7985                             Operand((uint32_t)C_008F14_NUM_FORMAT));
7986          desc[1] = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), desc[1], nfmt);
7987
7988          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector,
7989                                                                          Format::PSEUDO, resource.size(), 1)};
7990          for (unsigned i = 0; i < resource.size(); i++)
7991             vec->operands[i] = Operand(desc[i]);
7992          resource = bld.tmp(resource.regClass());
7993          vec->definitions[0] = Definition(resource);
7994          ctx->block->instructions.emplace_back(std::move(vec));
7995
7996          new_coords[0] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
7997                                   new_coords[0], coords[0], tg4_compare_cube_wa64);
7998          new_coords[1] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
7999                                   new_coords[1], coords[1], tg4_compare_cube_wa64);
8000       }
8001       coords[0] = new_coords[0];
8002       coords[1] = new_coords[1];
8003    }
8004
8005    if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
8006       //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8007
8008       assert(coords.size() == 1);
8009       unsigned last_bit = util_last_bit(nir_ssa_def_components_read(&instr->dest.ssa));
8010       aco_opcode op;
8011       switch (last_bit) {
8012       case 1:
8013          op = aco_opcode::buffer_load_format_x; break;
8014       case 2:
8015          op = aco_opcode::buffer_load_format_xy; break;
8016       case 3:
8017          op = aco_opcode::buffer_load_format_xyz; break;
8018       case 4:
8019          op = aco_opcode::buffer_load_format_xyzw; break;
8020       default:
8021          unreachable("Tex instruction loads more than 4 components.");
8022       }
8023
8024       /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8025       if (last_bit == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
8026          tmp_dst = dst;
8027       else
8028          tmp_dst = bld.tmp(RegType::vgpr, last_bit);
8029
8030       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
8031       mubuf->operands[0] = Operand(resource);
8032       mubuf->operands[1] = Operand(coords[0]);
8033       mubuf->operands[2] = Operand((uint32_t) 0);
8034       mubuf->definitions[0] = Definition(tmp_dst);
8035       mubuf->idxen = true;
8036       mubuf->can_reorder = true;
8037       ctx->block->instructions.emplace_back(std::move(mubuf));
8038
8039       expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, (1 << last_bit) - 1);
8040       return;
8041    }
8042
8043    /* gather MIMG address components */
8044    std::vector<Temp> args;
8045    if (has_offset)
8046       args.emplace_back(offset);
8047    if (has_bias)
8048       args.emplace_back(bias);
8049    if (has_compare)
8050       args.emplace_back(compare);
8051    if (has_derivs)
8052       args.insert(args.end(), derivs.begin(), derivs.end());
8053
8054    args.insert(args.end(), coords.begin(), coords.end());
8055    if (has_sample_index)
8056       args.emplace_back(sample_index);
8057    if (has_lod)
8058       args.emplace_back(lod);
8059
8060    Temp arg = bld.tmp(RegClass(RegType::vgpr, args.size()));
8061    aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, args.size(), 1)};
8062    vec->definitions[0] = Definition(arg);
8063    for (unsigned i = 0; i < args.size(); i++)
8064       vec->operands[i] = Operand(args[i]);
8065    ctx->block->instructions.emplace_back(std::move(vec));
8066
8067
8068    if (instr->op == nir_texop_txf ||
8069        instr->op == nir_texop_txf_ms ||
8070        instr->op == nir_texop_samples_identical ||
8071        instr->op == nir_texop_fragment_fetch ||
8072        instr->op == nir_texop_fragment_mask_fetch) {
8073       aco_opcode op = level_zero || instr->sampler_dim == GLSL_SAMPLER_DIM_MS || instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS ? aco_opcode::image_load : aco_opcode::image_load_mip;
8074       tex.reset(create_instruction<MIMG_instruction>(op, Format::MIMG, 3, 1));
8075       tex->operands[0] = Operand(resource);
8076       tex->operands[1] = Operand(s4); /* no sampler */
8077       tex->operands[2] = Operand(arg);
8078       tex->dim = dim;
8079       tex->dmask = dmask;
8080       tex->unrm = true;
8081       tex->da = da;
8082       tex->definitions[0] = Definition(tmp_dst);
8083       tex->can_reorder = true;
8084       ctx->block->instructions.emplace_back(std::move(tex));
8085
8086       if (instr->op == nir_texop_samples_identical) {
8087          assert(dmask == 1 && dst.regClass() == v1);
8088          assert(dst.id() != tmp_dst.id());
8089
8090          Temp tmp = bld.tmp(bld.lm);
8091          bld.vopc(aco_opcode::v_cmp_eq_u32, Definition(tmp), Operand(0u), tmp_dst).def(0).setHint(vcc);
8092          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand((uint32_t)-1), tmp);
8093
8094       } else {
8095          expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, dmask);
8096       }
8097       return;
8098    }
8099
8100    // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8101    aco_opcode opcode = aco_opcode::image_sample;
8102    if (has_offset) { /* image_sample_*_o */
8103       if (has_compare) {
8104          opcode = aco_opcode::image_sample_c_o;
8105          if (has_derivs)
8106             opcode = aco_opcode::image_sample_c_d_o;
8107          if (has_bias)
8108             opcode = aco_opcode::image_sample_c_b_o;
8109          if (level_zero)
8110             opcode = aco_opcode::image_sample_c_lz_o;
8111          if (has_lod)
8112             opcode = aco_opcode::image_sample_c_l_o;
8113       } else {
8114          opcode = aco_opcode::image_sample_o;
8115          if (has_derivs)
8116             opcode = aco_opcode::image_sample_d_o;
8117          if (has_bias)
8118             opcode = aco_opcode::image_sample_b_o;
8119          if (level_zero)
8120             opcode = aco_opcode::image_sample_lz_o;
8121          if (has_lod)
8122             opcode = aco_opcode::image_sample_l_o;
8123       }
8124    } else { /* no offset */
8125       if (has_compare) {
8126          opcode = aco_opcode::image_sample_c;
8127          if (has_derivs)
8128             opcode = aco_opcode::image_sample_c_d;
8129          if (has_bias)
8130             opcode = aco_opcode::image_sample_c_b;
8131          if (level_zero)
8132             opcode = aco_opcode::image_sample_c_lz;
8133          if (has_lod)
8134             opcode = aco_opcode::image_sample_c_l;
8135       } else {
8136          opcode = aco_opcode::image_sample;
8137          if (has_derivs)
8138             opcode = aco_opcode::image_sample_d;
8139          if (has_bias)
8140             opcode = aco_opcode::image_sample_b;
8141          if (level_zero)
8142             opcode = aco_opcode::image_sample_lz;
8143          if (has_lod)
8144             opcode = aco_opcode::image_sample_l;
8145       }
8146    }
8147
8148    if (instr->op == nir_texop_tg4) {
8149       if (has_offset) {
8150          opcode = aco_opcode::image_gather4_lz_o;
8151          if (has_compare)
8152             opcode = aco_opcode::image_gather4_c_lz_o;
8153       } else {
8154          opcode = aco_opcode::image_gather4_lz;
8155          if (has_compare)
8156             opcode = aco_opcode::image_gather4_c_lz;
8157       }
8158    } else if (instr->op == nir_texop_lod) {
8159       opcode = aco_opcode::image_get_lod;
8160    }
8161
8162    /* we don't need the bias, sample index, compare value or offset to be
8163     * computed in WQM but if the p_create_vector copies the coordinates, then it
8164     * needs to be in WQM */
8165    if (ctx->stage == fragment_fs &&
8166        !has_derivs && !has_lod && !level_zero &&
8167        instr->sampler_dim != GLSL_SAMPLER_DIM_MS &&
8168        instr->sampler_dim != GLSL_SAMPLER_DIM_SUBPASS_MS)
8169       arg = emit_wqm(ctx, arg, bld.tmp(arg.regClass()), true);
8170
8171    tex.reset(create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 1));
8172    tex->operands[0] = Operand(resource);
8173    tex->operands[1] = Operand(sampler);
8174    tex->operands[2] = Operand(arg);
8175    tex->dim = dim;
8176    tex->dmask = dmask;
8177    tex->da = da;
8178    tex->definitions[0] = Definition(tmp_dst);
8179    tex->can_reorder = true;
8180    ctx->block->instructions.emplace_back(std::move(tex));
8181
8182    if (tg4_integer_cube_workaround) {
8183       assert(tmp_dst.id() != dst.id());
8184       assert(tmp_dst.size() == dst.size() && dst.size() == 4);
8185
8186       emit_split_vector(ctx, tmp_dst, tmp_dst.size());
8187       Temp val[4];
8188       for (unsigned i = 0; i < dst.size(); i++) {
8189          val[i] = emit_extract_vector(ctx, tmp_dst, i, v1);
8190          Temp cvt_val;
8191          if (stype == GLSL_TYPE_UINT)
8192             cvt_val = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), val[i]);
8193          else
8194             cvt_val = bld.vop1(aco_opcode::v_cvt_i32_f32, bld.def(v1), val[i]);
8195          val[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), val[i], cvt_val, tg4_compare_cube_wa64);
8196       }
8197       Temp tmp = dst.regClass() == v4 ? dst : bld.tmp(v4);
8198       tmp_dst = bld.pseudo(aco_opcode::p_create_vector, Definition(tmp),
8199                            val[0], val[1], val[2], val[3]);
8200    }
8201    unsigned mask = instr->op == nir_texop_tg4 ? 0xF : dmask;
8202    expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, mask);
8203
8204 }
8205
8206
8207 Operand get_phi_operand(isel_context *ctx, nir_ssa_def *ssa)
8208 {
8209    Temp tmp = get_ssa_temp(ctx, ssa);
8210    if (ssa->parent_instr->type == nir_instr_type_ssa_undef)
8211       return Operand(tmp.regClass());
8212    else
8213       return Operand(tmp);
8214 }
8215
8216 void visit_phi(isel_context *ctx, nir_phi_instr *instr)
8217 {
8218    aco_ptr<Pseudo_instruction> phi;
8219    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
8220    assert(instr->dest.ssa.bit_size != 1 || dst.regClass() == ctx->program->lane_mask);
8221
8222    bool logical = !dst.is_linear() || ctx->divergent_vals[instr->dest.ssa.index];
8223    logical |= ctx->block->kind & block_kind_merge;
8224    aco_opcode opcode = logical ? aco_opcode::p_phi : aco_opcode::p_linear_phi;
8225
8226    /* we want a sorted list of sources, since the predecessor list is also sorted */
8227    std::map<unsigned, nir_ssa_def*> phi_src;
8228    nir_foreach_phi_src(src, instr)
8229       phi_src[src->pred->index] = src->src.ssa;
8230
8231    std::vector<unsigned>& preds = logical ? ctx->block->logical_preds : ctx->block->linear_preds;
8232    unsigned num_operands = 0;
8233    Operand operands[std::max(exec_list_length(&instr->srcs), (unsigned)preds.size())];
8234    unsigned num_defined = 0;
8235    unsigned cur_pred_idx = 0;
8236    for (std::pair<unsigned, nir_ssa_def *> src : phi_src) {
8237       if (cur_pred_idx < preds.size()) {
8238          /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8239          unsigned block = ctx->cf_info.nir_to_aco[src.first];
8240          unsigned skipped = 0;
8241          while (cur_pred_idx + skipped < preds.size() && preds[cur_pred_idx + skipped] != block)
8242             skipped++;
8243          if (cur_pred_idx + skipped < preds.size()) {
8244             for (unsigned i = 0; i < skipped; i++)
8245                operands[num_operands++] = Operand(dst.regClass());
8246             cur_pred_idx += skipped;
8247          } else {
8248             continue;
8249          }
8250       }
8251       cur_pred_idx++;
8252       Operand op = get_phi_operand(ctx, src.second);
8253       operands[num_operands++] = op;
8254       num_defined += !op.isUndefined();
8255    }
8256    /* handle block_kind_continue_or_break at loop exit blocks */
8257    while (cur_pred_idx++ < preds.size())
8258       operands[num_operands++] = Operand(dst.regClass());
8259
8260    if (num_defined == 0) {
8261       Builder bld(ctx->program, ctx->block);
8262       if (dst.regClass() == s1) {
8263          bld.sop1(aco_opcode::s_mov_b32, Definition(dst), Operand(0u));
8264       } else if (dst.regClass() == v1) {
8265          bld.vop1(aco_opcode::v_mov_b32, Definition(dst), Operand(0u));
8266       } else {
8267          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
8268          for (unsigned i = 0; i < dst.size(); i++)
8269             vec->operands[i] = Operand(0u);
8270          vec->definitions[0] = Definition(dst);
8271          ctx->block->instructions.emplace_back(std::move(vec));
8272       }
8273       return;
8274    }
8275
8276    /* we can use a linear phi in some cases if one src is undef */
8277    if (dst.is_linear() && ctx->block->kind & block_kind_merge && num_defined == 1) {
8278       phi.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_linear_phi, Format::PSEUDO, num_operands, 1));
8279
8280       Block *linear_else = &ctx->program->blocks[ctx->block->linear_preds[1]];
8281       Block *invert = &ctx->program->blocks[linear_else->linear_preds[0]];
8282       assert(invert->kind & block_kind_invert);
8283
8284       unsigned then_block = invert->linear_preds[0];
8285
8286       Block* insert_block = NULL;
8287       for (unsigned i = 0; i < num_operands; i++) {
8288          Operand op = operands[i];
8289          if (op.isUndefined())
8290             continue;
8291          insert_block = ctx->block->logical_preds[i] == then_block ? invert : ctx->block;
8292          phi->operands[0] = op;
8293          break;
8294       }
8295       assert(insert_block); /* should be handled by the "num_defined == 0" case above */
8296       phi->operands[1] = Operand(dst.regClass());
8297       phi->definitions[0] = Definition(dst);
8298       insert_block->instructions.emplace(insert_block->instructions.begin(), std::move(phi));
8299       return;
8300    }
8301
8302    /* try to scalarize vector phis */
8303    if (instr->dest.ssa.bit_size != 1 && dst.size() > 1) {
8304       // TODO: scalarize linear phis on divergent ifs
8305       bool can_scalarize = (opcode == aco_opcode::p_phi || !(ctx->block->kind & block_kind_merge));
8306       std::array<Temp, NIR_MAX_VEC_COMPONENTS> new_vec;
8307       for (unsigned i = 0; can_scalarize && (i < num_operands); i++) {
8308          Operand src = operands[i];
8309          if (src.isTemp() && ctx->allocated_vec.find(src.tempId()) == ctx->allocated_vec.end())
8310             can_scalarize = false;
8311       }
8312       if (can_scalarize) {
8313          unsigned num_components = instr->dest.ssa.num_components;
8314          assert(dst.size() % num_components == 0);
8315          RegClass rc = RegClass(dst.type(), dst.size() / num_components);
8316
8317          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1)};
8318          for (unsigned k = 0; k < num_components; k++) {
8319             phi.reset(create_instruction<Pseudo_instruction>(opcode, Format::PSEUDO, num_operands, 1));
8320             for (unsigned i = 0; i < num_operands; i++) {
8321                Operand src = operands[i];
8322                phi->operands[i] = src.isTemp() ? Operand(ctx->allocated_vec[src.tempId()][k]) : Operand(rc);
8323             }
8324             Temp phi_dst = {ctx->program->allocateId(), rc};
8325             phi->definitions[0] = Definition(phi_dst);
8326             ctx->block->instructions.emplace(ctx->block->instructions.begin(), std::move(phi));
8327             new_vec[k] = phi_dst;
8328             vec->operands[k] = Operand(phi_dst);
8329          }
8330          vec->definitions[0] = Definition(dst);
8331          ctx->block->instructions.emplace_back(std::move(vec));
8332          ctx->allocated_vec.emplace(dst.id(), new_vec);
8333          return;
8334       }
8335    }
8336
8337    phi.reset(create_instruction<Pseudo_instruction>(opcode, Format::PSEUDO, num_operands, 1));
8338    for (unsigned i = 0; i < num_operands; i++)
8339       phi->operands[i] = operands[i];
8340    phi->definitions[0] = Definition(dst);
8341    ctx->block->instructions.emplace(ctx->block->instructions.begin(), std::move(phi));
8342 }
8343
8344
8345 void visit_undef(isel_context *ctx, nir_ssa_undef_instr *instr)
8346 {
8347    Temp dst = get_ssa_temp(ctx, &instr->def);
8348
8349    assert(dst.type() == RegType::sgpr);
8350
8351    if (dst.size() == 1) {
8352       Builder(ctx->program, ctx->block).copy(Definition(dst), Operand(0u));
8353    } else {
8354       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
8355       for (unsigned i = 0; i < dst.size(); i++)
8356          vec->operands[i] = Operand(0u);
8357       vec->definitions[0] = Definition(dst);
8358       ctx->block->instructions.emplace_back(std::move(vec));
8359    }
8360 }
8361
8362 void visit_jump(isel_context *ctx, nir_jump_instr *instr)
8363 {
8364    Builder bld(ctx->program, ctx->block);
8365    Block *logical_target;
8366    append_logical_end(ctx->block);
8367    unsigned idx = ctx->block->index;
8368
8369    switch (instr->type) {
8370    case nir_jump_break:
8371       logical_target = ctx->cf_info.parent_loop.exit;
8372       add_logical_edge(idx, logical_target);
8373       ctx->block->kind |= block_kind_break;
8374
8375       if (!ctx->cf_info.parent_if.is_divergent &&
8376           !ctx->cf_info.parent_loop.has_divergent_continue) {
8377          /* uniform break - directly jump out of the loop */
8378          ctx->block->kind |= block_kind_uniform;
8379          ctx->cf_info.has_branch = true;
8380          bld.branch(aco_opcode::p_branch);
8381          add_linear_edge(idx, logical_target);
8382          return;
8383       }
8384       ctx->cf_info.parent_loop.has_divergent_branch = true;
8385       ctx->cf_info.nir_to_aco[instr->instr.block->index] = ctx->block->index;
8386       break;
8387    case nir_jump_continue:
8388       logical_target = &ctx->program->blocks[ctx->cf_info.parent_loop.header_idx];
8389       add_logical_edge(idx, logical_target);
8390       ctx->block->kind |= block_kind_continue;
8391
8392       if (ctx->cf_info.parent_if.is_divergent) {
8393          /* for potential uniform breaks after this continue,
8394             we must ensure that they are handled correctly */
8395          ctx->cf_info.parent_loop.has_divergent_continue = true;
8396          ctx->cf_info.parent_loop.has_divergent_branch = true;
8397          ctx->cf_info.nir_to_aco[instr->instr.block->index] = ctx->block->index;
8398       } else {
8399          /* uniform continue - directly jump to the loop header */
8400          ctx->block->kind |= block_kind_uniform;
8401          ctx->cf_info.has_branch = true;
8402          bld.branch(aco_opcode::p_branch);
8403          add_linear_edge(idx, logical_target);
8404          return;
8405       }
8406       break;
8407    default:
8408       fprintf(stderr, "Unknown NIR jump instr: ");
8409       nir_print_instr(&instr->instr, stderr);
8410       fprintf(stderr, "\n");
8411       abort();
8412    }
8413
8414    if (ctx->cf_info.parent_if.is_divergent && !ctx->cf_info.exec_potentially_empty_break) {
8415       ctx->cf_info.exec_potentially_empty_break = true;
8416       ctx->cf_info.exec_potentially_empty_break_depth = ctx->cf_info.loop_nest_depth;
8417    }
8418
8419    /* remove critical edges from linear CFG */
8420    bld.branch(aco_opcode::p_branch);
8421    Block* break_block = ctx->program->create_and_insert_block();
8422    break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8423    break_block->kind |= block_kind_uniform;
8424    add_linear_edge(idx, break_block);
8425    /* the loop_header pointer might be invalidated by this point */
8426    if (instr->type == nir_jump_continue)
8427       logical_target = &ctx->program->blocks[ctx->cf_info.parent_loop.header_idx];
8428    add_linear_edge(break_block->index, logical_target);
8429    bld.reset(break_block);
8430    bld.branch(aco_opcode::p_branch);
8431
8432    Block* continue_block = ctx->program->create_and_insert_block();
8433    continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8434    add_linear_edge(idx, continue_block);
8435    append_logical_start(continue_block);
8436    ctx->block = continue_block;
8437    return;
8438 }
8439
8440 void visit_block(isel_context *ctx, nir_block *block)
8441 {
8442    nir_foreach_instr(instr, block) {
8443       switch (instr->type) {
8444       case nir_instr_type_alu:
8445          visit_alu_instr(ctx, nir_instr_as_alu(instr));
8446          break;
8447       case nir_instr_type_load_const:
8448          visit_load_const(ctx, nir_instr_as_load_const(instr));
8449          break;
8450       case nir_instr_type_intrinsic:
8451          visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
8452          break;
8453       case nir_instr_type_tex:
8454          visit_tex(ctx, nir_instr_as_tex(instr));
8455          break;
8456       case nir_instr_type_phi:
8457          visit_phi(ctx, nir_instr_as_phi(instr));
8458          break;
8459       case nir_instr_type_ssa_undef:
8460          visit_undef(ctx, nir_instr_as_ssa_undef(instr));
8461          break;
8462       case nir_instr_type_deref:
8463          break;
8464       case nir_instr_type_jump:
8465          visit_jump(ctx, nir_instr_as_jump(instr));
8466          break;
8467       default:
8468          fprintf(stderr, "Unknown NIR instr type: ");
8469          nir_print_instr(instr, stderr);
8470          fprintf(stderr, "\n");
8471          //abort();
8472       }
8473    }
8474
8475    if (!ctx->cf_info.parent_loop.has_divergent_branch)
8476       ctx->cf_info.nir_to_aco[block->index] = ctx->block->index;
8477 }
8478
8479
8480
8481 static void visit_loop(isel_context *ctx, nir_loop *loop)
8482 {
8483    //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
8484    append_logical_end(ctx->block);
8485    ctx->block->kind |= block_kind_loop_preheader | block_kind_uniform;
8486    Builder bld(ctx->program, ctx->block);
8487    bld.branch(aco_opcode::p_branch);
8488    unsigned loop_preheader_idx = ctx->block->index;
8489
8490    Block loop_exit = Block();
8491    loop_exit.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8492    loop_exit.kind |= (block_kind_loop_exit | (ctx->block->kind & block_kind_top_level));
8493
8494    Block* loop_header = ctx->program->create_and_insert_block();
8495    loop_header->loop_nest_depth = ctx->cf_info.loop_nest_depth + 1;
8496    loop_header->kind |= block_kind_loop_header;
8497    add_edge(loop_preheader_idx, loop_header);
8498    ctx->block = loop_header;
8499
8500    /* emit loop body */
8501    unsigned loop_header_idx = loop_header->index;
8502    loop_info_RAII loop_raii(ctx, loop_header_idx, &loop_exit);
8503    append_logical_start(ctx->block);
8504    visit_cf_list(ctx, &loop->body);
8505
8506    //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
8507    if (!ctx->cf_info.has_branch) {
8508       append_logical_end(ctx->block);
8509       if (ctx->cf_info.exec_potentially_empty_discard || ctx->cf_info.exec_potentially_empty_break) {
8510          /* Discards can result in code running with an empty exec mask.
8511           * This would result in divergent breaks not ever being taken. As a
8512           * workaround, break the loop when the loop mask is empty instead of
8513           * always continuing. */
8514          ctx->block->kind |= (block_kind_continue_or_break | block_kind_uniform);
8515          unsigned block_idx = ctx->block->index;
8516
8517          /* create helper blocks to avoid critical edges */
8518          Block *break_block = ctx->program->create_and_insert_block();
8519          break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8520          break_block->kind = block_kind_uniform;
8521          bld.reset(break_block);
8522          bld.branch(aco_opcode::p_branch);
8523          add_linear_edge(block_idx, break_block);
8524          add_linear_edge(break_block->index, &loop_exit);
8525
8526          Block *continue_block = ctx->program->create_and_insert_block();
8527          continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8528          continue_block->kind = block_kind_uniform;
8529          bld.reset(continue_block);
8530          bld.branch(aco_opcode::p_branch);
8531          add_linear_edge(block_idx, continue_block);
8532          add_linear_edge(continue_block->index, &ctx->program->blocks[loop_header_idx]);
8533
8534          if (!ctx->cf_info.parent_loop.has_divergent_branch)
8535             add_logical_edge(block_idx, &ctx->program->blocks[loop_header_idx]);
8536          ctx->block = &ctx->program->blocks[block_idx];
8537       } else {
8538          ctx->block->kind |= (block_kind_continue | block_kind_uniform);
8539          if (!ctx->cf_info.parent_loop.has_divergent_branch)
8540             add_edge(ctx->block->index, &ctx->program->blocks[loop_header_idx]);
8541          else
8542             add_linear_edge(ctx->block->index, &ctx->program->blocks[loop_header_idx]);
8543       }
8544
8545       bld.reset(ctx->block);
8546       bld.branch(aco_opcode::p_branch);
8547    }
8548
8549    /* fixup phis in loop header from unreachable blocks */
8550    if (ctx->cf_info.has_branch || ctx->cf_info.parent_loop.has_divergent_branch) {
8551       bool linear = ctx->cf_info.has_branch;
8552       bool logical = ctx->cf_info.has_branch || ctx->cf_info.parent_loop.has_divergent_branch;
8553       for (aco_ptr<Instruction>& instr : ctx->program->blocks[loop_header_idx].instructions) {
8554          if ((logical && instr->opcode == aco_opcode::p_phi) ||
8555              (linear && instr->opcode == aco_opcode::p_linear_phi)) {
8556             /* the last operand should be the one that needs to be removed */
8557             instr->operands.pop_back();
8558          } else if (!is_phi(instr)) {
8559             break;
8560          }
8561       }
8562    }
8563
8564    ctx->cf_info.has_branch = false;
8565
8566    // TODO: if the loop has not a single exit, we must add one °°
8567    /* emit loop successor block */
8568    ctx->block = ctx->program->insert_block(std::move(loop_exit));
8569    append_logical_start(ctx->block);
8570
8571    #if 0
8572    // TODO: check if it is beneficial to not branch on continues
8573    /* trim linear phis in loop header */
8574    for (auto&& instr : loop_entry->instructions) {
8575       if (instr->opcode == aco_opcode::p_linear_phi) {
8576          aco_ptr<Pseudo_instruction> new_phi{create_instruction<Pseudo_instruction>(aco_opcode::p_linear_phi, Format::PSEUDO, loop_entry->linear_predecessors.size(), 1)};
8577          new_phi->definitions[0] = instr->definitions[0];
8578          for (unsigned i = 0; i < new_phi->operands.size(); i++)
8579             new_phi->operands[i] = instr->operands[i];
8580          /* check that the remaining operands are all the same */
8581          for (unsigned i = new_phi->operands.size(); i < instr->operands.size(); i++)
8582             assert(instr->operands[i].tempId() == instr->operands.back().tempId());
8583          instr.swap(new_phi);
8584       } else if (instr->opcode == aco_opcode::p_phi) {
8585          continue;
8586       } else {
8587          break;
8588       }
8589    }
8590    #endif
8591 }
8592
8593 static void begin_divergent_if_then(isel_context *ctx, if_context *ic, Temp cond)
8594 {
8595    ic->cond = cond;
8596
8597    append_logical_end(ctx->block);
8598    ctx->block->kind |= block_kind_branch;
8599
8600    /* branch to linear then block */
8601    assert(cond.regClass() == ctx->program->lane_mask);
8602    aco_ptr<Pseudo_branch_instruction> branch;
8603    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_z, Format::PSEUDO_BRANCH, 1, 0));
8604    branch->operands[0] = Operand(cond);
8605    ctx->block->instructions.push_back(std::move(branch));
8606
8607    ic->BB_if_idx = ctx->block->index;
8608    ic->BB_invert = Block();
8609    ic->BB_invert.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8610    /* Invert blocks are intentionally not marked as top level because they
8611     * are not part of the logical cfg. */
8612    ic->BB_invert.kind |= block_kind_invert;
8613    ic->BB_endif = Block();
8614    ic->BB_endif.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8615    ic->BB_endif.kind |= (block_kind_merge | (ctx->block->kind & block_kind_top_level));
8616
8617    ic->exec_potentially_empty_discard_old = ctx->cf_info.exec_potentially_empty_discard;
8618    ic->exec_potentially_empty_break_old = ctx->cf_info.exec_potentially_empty_break;
8619    ic->exec_potentially_empty_break_depth_old = ctx->cf_info.exec_potentially_empty_break_depth;
8620    ic->divergent_old = ctx->cf_info.parent_if.is_divergent;
8621    ctx->cf_info.parent_if.is_divergent = true;
8622
8623    /* divergent branches use cbranch_execz */
8624    ctx->cf_info.exec_potentially_empty_discard = false;
8625    ctx->cf_info.exec_potentially_empty_break = false;
8626    ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8627
8628    /** emit logical then block */
8629    Block* BB_then_logical = ctx->program->create_and_insert_block();
8630    BB_then_logical->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8631    add_edge(ic->BB_if_idx, BB_then_logical);
8632    ctx->block = BB_then_logical;
8633    append_logical_start(BB_then_logical);
8634 }
8635
8636 static void begin_divergent_if_else(isel_context *ctx, if_context *ic)
8637 {
8638    Block *BB_then_logical = ctx->block;
8639    append_logical_end(BB_then_logical);
8640     /* branch from logical then block to invert block */
8641    aco_ptr<Pseudo_branch_instruction> branch;
8642    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8643    BB_then_logical->instructions.emplace_back(std::move(branch));
8644    add_linear_edge(BB_then_logical->index, &ic->BB_invert);
8645    if (!ctx->cf_info.parent_loop.has_divergent_branch)
8646       add_logical_edge(BB_then_logical->index, &ic->BB_endif);
8647    BB_then_logical->kind |= block_kind_uniform;
8648    assert(!ctx->cf_info.has_branch);
8649    ic->then_branch_divergent = ctx->cf_info.parent_loop.has_divergent_branch;
8650    ctx->cf_info.parent_loop.has_divergent_branch = false;
8651
8652    /** emit linear then block */
8653    Block* BB_then_linear = ctx->program->create_and_insert_block();
8654    BB_then_linear->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8655    BB_then_linear->kind |= block_kind_uniform;
8656    add_linear_edge(ic->BB_if_idx, BB_then_linear);
8657    /* branch from linear then block to invert block */
8658    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8659    BB_then_linear->instructions.emplace_back(std::move(branch));
8660    add_linear_edge(BB_then_linear->index, &ic->BB_invert);
8661
8662    /** emit invert merge block */
8663    ctx->block = ctx->program->insert_block(std::move(ic->BB_invert));
8664    ic->invert_idx = ctx->block->index;
8665
8666    /* branch to linear else block (skip else) */
8667    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_nz, Format::PSEUDO_BRANCH, 1, 0));
8668    branch->operands[0] = Operand(ic->cond);
8669    ctx->block->instructions.push_back(std::move(branch));
8670
8671    ic->exec_potentially_empty_discard_old |= ctx->cf_info.exec_potentially_empty_discard;
8672    ic->exec_potentially_empty_break_old |= ctx->cf_info.exec_potentially_empty_break;
8673    ic->exec_potentially_empty_break_depth_old =
8674       std::min(ic->exec_potentially_empty_break_depth_old, ctx->cf_info.exec_potentially_empty_break_depth);
8675    /* divergent branches use cbranch_execz */
8676    ctx->cf_info.exec_potentially_empty_discard = false;
8677    ctx->cf_info.exec_potentially_empty_break = false;
8678    ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8679
8680    /** emit logical else block */
8681    Block* BB_else_logical = ctx->program->create_and_insert_block();
8682    BB_else_logical->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8683    add_logical_edge(ic->BB_if_idx, BB_else_logical);
8684    add_linear_edge(ic->invert_idx, BB_else_logical);
8685    ctx->block = BB_else_logical;
8686    append_logical_start(BB_else_logical);
8687 }
8688
8689 static void end_divergent_if(isel_context *ctx, if_context *ic)
8690 {
8691    Block *BB_else_logical = ctx->block;
8692    append_logical_end(BB_else_logical);
8693
8694    /* branch from logical else block to endif block */
8695    aco_ptr<Pseudo_branch_instruction> branch;
8696    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8697    BB_else_logical->instructions.emplace_back(std::move(branch));
8698    add_linear_edge(BB_else_logical->index, &ic->BB_endif);
8699    if (!ctx->cf_info.parent_loop.has_divergent_branch)
8700       add_logical_edge(BB_else_logical->index, &ic->BB_endif);
8701    BB_else_logical->kind |= block_kind_uniform;
8702
8703    assert(!ctx->cf_info.has_branch);
8704    ctx->cf_info.parent_loop.has_divergent_branch &= ic->then_branch_divergent;
8705
8706
8707    /** emit linear else block */
8708    Block* BB_else_linear = ctx->program->create_and_insert_block();
8709    BB_else_linear->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8710    BB_else_linear->kind |= block_kind_uniform;
8711    add_linear_edge(ic->invert_idx, BB_else_linear);
8712
8713    /* branch from linear else block to endif block */
8714    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8715    BB_else_linear->instructions.emplace_back(std::move(branch));
8716    add_linear_edge(BB_else_linear->index, &ic->BB_endif);
8717
8718
8719    /** emit endif merge block */
8720    ctx->block = ctx->program->insert_block(std::move(ic->BB_endif));
8721    append_logical_start(ctx->block);
8722
8723
8724    ctx->cf_info.parent_if.is_divergent = ic->divergent_old;
8725    ctx->cf_info.exec_potentially_empty_discard |= ic->exec_potentially_empty_discard_old;
8726    ctx->cf_info.exec_potentially_empty_break |= ic->exec_potentially_empty_break_old;
8727    ctx->cf_info.exec_potentially_empty_break_depth =
8728       std::min(ic->exec_potentially_empty_break_depth_old, ctx->cf_info.exec_potentially_empty_break_depth);
8729    if (ctx->cf_info.loop_nest_depth == ctx->cf_info.exec_potentially_empty_break_depth &&
8730        !ctx->cf_info.parent_if.is_divergent) {
8731       ctx->cf_info.exec_potentially_empty_break = false;
8732       ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8733    }
8734    /* uniform control flow never has an empty exec-mask */
8735    if (!ctx->cf_info.loop_nest_depth && !ctx->cf_info.parent_if.is_divergent) {
8736       ctx->cf_info.exec_potentially_empty_discard = false;
8737       ctx->cf_info.exec_potentially_empty_break = false;
8738       ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8739    }
8740 }
8741
8742 static void visit_if(isel_context *ctx, nir_if *if_stmt)
8743 {
8744    Temp cond = get_ssa_temp(ctx, if_stmt->condition.ssa);
8745    Builder bld(ctx->program, ctx->block);
8746    aco_ptr<Pseudo_branch_instruction> branch;
8747
8748    if (!ctx->divergent_vals[if_stmt->condition.ssa->index]) { /* uniform condition */
8749       /**
8750        * Uniform conditionals are represented in the following way*) :
8751        *
8752        * The linear and logical CFG:
8753        *                        BB_IF
8754        *                        /    \
8755        *       BB_THEN (logical)      BB_ELSE (logical)
8756        *                        \    /
8757        *                        BB_ENDIF
8758        *
8759        * *) Exceptions may be due to break and continue statements within loops
8760        *    If a break/continue happens within uniform control flow, it branches
8761        *    to the loop exit/entry block. Otherwise, it branches to the next
8762        *    merge block.
8763        **/
8764       append_logical_end(ctx->block);
8765       ctx->block->kind |= block_kind_uniform;
8766
8767       /* emit branch */
8768       assert(cond.regClass() == bld.lm);
8769       // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
8770       cond = bool_to_scalar_condition(ctx, cond);
8771
8772       branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_z, Format::PSEUDO_BRANCH, 1, 0));
8773       branch->operands[0] = Operand(cond);
8774       branch->operands[0].setFixed(scc);
8775       ctx->block->instructions.emplace_back(std::move(branch));
8776
8777       unsigned BB_if_idx = ctx->block->index;
8778       Block BB_endif = Block();
8779       BB_endif.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8780       BB_endif.kind |= ctx->block->kind & block_kind_top_level;
8781
8782       /** emit then block */
8783       Block* BB_then = ctx->program->create_and_insert_block();
8784       BB_then->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8785       add_edge(BB_if_idx, BB_then);
8786       append_logical_start(BB_then);
8787       ctx->block = BB_then;
8788       visit_cf_list(ctx, &if_stmt->then_list);
8789       BB_then = ctx->block;
8790       bool then_branch = ctx->cf_info.has_branch;
8791       bool then_branch_divergent = ctx->cf_info.parent_loop.has_divergent_branch;
8792
8793       if (!then_branch) {
8794          append_logical_end(BB_then);
8795          /* branch from then block to endif block */
8796          branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8797          BB_then->instructions.emplace_back(std::move(branch));
8798          add_linear_edge(BB_then->index, &BB_endif);
8799          if (!then_branch_divergent)
8800             add_logical_edge(BB_then->index, &BB_endif);
8801          BB_then->kind |= block_kind_uniform;
8802       }
8803
8804       ctx->cf_info.has_branch = false;
8805       ctx->cf_info.parent_loop.has_divergent_branch = false;
8806
8807       /** emit else block */
8808       Block* BB_else = ctx->program->create_and_insert_block();
8809       BB_else->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8810       add_edge(BB_if_idx, BB_else);
8811       append_logical_start(BB_else);
8812       ctx->block = BB_else;
8813       visit_cf_list(ctx, &if_stmt->else_list);
8814       BB_else = ctx->block;
8815
8816       if (!ctx->cf_info.has_branch) {
8817          append_logical_end(BB_else);
8818          /* branch from then block to endif block */
8819          branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8820          BB_else->instructions.emplace_back(std::move(branch));
8821          add_linear_edge(BB_else->index, &BB_endif);
8822          if (!ctx->cf_info.parent_loop.has_divergent_branch)
8823             add_logical_edge(BB_else->index, &BB_endif);
8824          BB_else->kind |= block_kind_uniform;
8825       }
8826
8827       ctx->cf_info.has_branch &= then_branch;
8828       ctx->cf_info.parent_loop.has_divergent_branch &= then_branch_divergent;
8829
8830       /** emit endif merge block */
8831       if (!ctx->cf_info.has_branch) {
8832          ctx->block = ctx->program->insert_block(std::move(BB_endif));
8833          append_logical_start(ctx->block);
8834       }
8835    } else { /* non-uniform condition */
8836       /**
8837        * To maintain a logical and linear CFG without critical edges,
8838        * non-uniform conditionals are represented in the following way*) :
8839        *
8840        * The linear CFG:
8841        *                        BB_IF
8842        *                        /    \
8843        *       BB_THEN (logical)      BB_THEN (linear)
8844        *                        \    /
8845        *                        BB_INVERT (linear)
8846        *                        /    \
8847        *       BB_ELSE (logical)      BB_ELSE (linear)
8848        *                        \    /
8849        *                        BB_ENDIF
8850        *
8851        * The logical CFG:
8852        *                        BB_IF
8853        *                        /    \
8854        *       BB_THEN (logical)      BB_ELSE (logical)
8855        *                        \    /
8856        *                        BB_ENDIF
8857        *
8858        * *) Exceptions may be due to break and continue statements within loops
8859        **/
8860
8861       if_context ic;
8862
8863       begin_divergent_if_then(ctx, &ic, cond);
8864       visit_cf_list(ctx, &if_stmt->then_list);
8865
8866       begin_divergent_if_else(ctx, &ic);
8867       visit_cf_list(ctx, &if_stmt->else_list);
8868
8869       end_divergent_if(ctx, &ic);
8870    }
8871 }
8872
8873 static void visit_cf_list(isel_context *ctx,
8874                           struct exec_list *list)
8875 {
8876    foreach_list_typed(nir_cf_node, node, node, list) {
8877       switch (node->type) {
8878       case nir_cf_node_block:
8879          visit_block(ctx, nir_cf_node_as_block(node));
8880          break;
8881       case nir_cf_node_if:
8882          visit_if(ctx, nir_cf_node_as_if(node));
8883          break;
8884       case nir_cf_node_loop:
8885          visit_loop(ctx, nir_cf_node_as_loop(node));
8886          break;
8887       default:
8888          unreachable("unimplemented cf list type");
8889       }
8890    }
8891 }
8892
8893 static void export_vs_varying(isel_context *ctx, int slot, bool is_pos, int *next_pos)
8894 {
8895    assert(ctx->stage == vertex_vs ||
8896           ctx->stage == tess_eval_vs ||
8897           ctx->stage == gs_copy_vs);
8898
8899    int offset = ctx->stage == tess_eval_vs
8900                 ? ctx->program->info->tes.outinfo.vs_output_param_offset[slot]
8901                 : ctx->program->info->vs.outinfo.vs_output_param_offset[slot];
8902    uint64_t mask = ctx->outputs.mask[slot];
8903    if (!is_pos && !mask)
8904       return;
8905    if (!is_pos && offset == AC_EXP_PARAM_UNDEFINED)
8906       return;
8907    aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
8908    exp->enabled_mask = mask;
8909    for (unsigned i = 0; i < 4; ++i) {
8910       if (mask & (1 << i))
8911          exp->operands[i] = Operand(ctx->outputs.outputs[slot][i]);
8912       else
8913          exp->operands[i] = Operand(v1);
8914    }
8915    /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
8916     * Setting valid_mask=1 prevents it and has no other effect.
8917     */
8918    exp->valid_mask = ctx->options->chip_class >= GFX10 && is_pos && *next_pos == 0;
8919    exp->done = false;
8920    exp->compressed = false;
8921    if (is_pos)
8922       exp->dest = V_008DFC_SQ_EXP_POS + (*next_pos)++;
8923    else
8924       exp->dest = V_008DFC_SQ_EXP_PARAM + offset;
8925    ctx->block->instructions.emplace_back(std::move(exp));
8926 }
8927
8928 static void export_vs_psiz_layer_viewport(isel_context *ctx, int *next_pos)
8929 {
8930    aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
8931    exp->enabled_mask = 0;
8932    for (unsigned i = 0; i < 4; ++i)
8933       exp->operands[i] = Operand(v1);
8934    if (ctx->outputs.mask[VARYING_SLOT_PSIZ]) {
8935       exp->operands[0] = Operand(ctx->outputs.outputs[VARYING_SLOT_PSIZ][0]);
8936       exp->enabled_mask |= 0x1;
8937    }
8938    if (ctx->outputs.mask[VARYING_SLOT_LAYER]) {
8939       exp->operands[2] = Operand(ctx->outputs.outputs[VARYING_SLOT_LAYER][0]);
8940       exp->enabled_mask |= 0x4;
8941    }
8942    if (ctx->outputs.mask[VARYING_SLOT_VIEWPORT]) {
8943       if (ctx->options->chip_class < GFX9) {
8944          exp->operands[3] = Operand(ctx->outputs.outputs[VARYING_SLOT_VIEWPORT][0]);
8945          exp->enabled_mask |= 0x8;
8946       } else {
8947          Builder bld(ctx->program, ctx->block);
8948
8949          Temp out = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(16u),
8950                              Operand(ctx->outputs.outputs[VARYING_SLOT_VIEWPORT][0]));
8951          if (exp->operands[2].isTemp())
8952             out = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(out), exp->operands[2]);
8953
8954          exp->operands[2] = Operand(out);
8955          exp->enabled_mask |= 0x4;
8956       }
8957    }
8958    exp->valid_mask = ctx->options->chip_class >= GFX10 && *next_pos == 0;
8959    exp->done = false;
8960    exp->compressed = false;
8961    exp->dest = V_008DFC_SQ_EXP_POS + (*next_pos)++;
8962    ctx->block->instructions.emplace_back(std::move(exp));
8963 }
8964
8965 static void create_vs_exports(isel_context *ctx)
8966 {
8967    assert(ctx->stage == vertex_vs ||
8968           ctx->stage == tess_eval_vs ||
8969           ctx->stage == gs_copy_vs);
8970
8971    radv_vs_output_info *outinfo = ctx->stage == tess_eval_vs
8972                                   ? &ctx->program->info->tes.outinfo
8973                                   : &ctx->program->info->vs.outinfo;
8974
8975    if (outinfo->export_prim_id) {
8976       ctx->outputs.mask[VARYING_SLOT_PRIMITIVE_ID] |= 0x1;
8977       ctx->outputs.outputs[VARYING_SLOT_PRIMITIVE_ID][0] = get_arg(ctx, ctx->args->vs_prim_id);
8978    }
8979
8980    if (ctx->options->key.has_multiview_view_index) {
8981       ctx->outputs.mask[VARYING_SLOT_LAYER] |= 0x1;
8982       ctx->outputs.outputs[VARYING_SLOT_LAYER][0] = as_vgpr(ctx, get_arg(ctx, ctx->args->ac.view_index));
8983    }
8984
8985    /* the order these position exports are created is important */
8986    int next_pos = 0;
8987    export_vs_varying(ctx, VARYING_SLOT_POS, true, &next_pos);
8988    if (outinfo->writes_pointsize || outinfo->writes_layer || outinfo->writes_viewport_index) {
8989       export_vs_psiz_layer_viewport(ctx, &next_pos);
8990    }
8991    if (ctx->num_clip_distances + ctx->num_cull_distances > 0)
8992       export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST0, true, &next_pos);
8993    if (ctx->num_clip_distances + ctx->num_cull_distances > 4)
8994       export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST1, true, &next_pos);
8995
8996    if (ctx->export_clip_dists) {
8997       if (ctx->num_clip_distances + ctx->num_cull_distances > 0)
8998          export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST0, false, &next_pos);
8999       if (ctx->num_clip_distances + ctx->num_cull_distances > 4)
9000          export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST1, false, &next_pos);
9001    }
9002
9003    for (unsigned i = 0; i <= VARYING_SLOT_VAR31; ++i) {
9004       if (i < VARYING_SLOT_VAR0 && i != VARYING_SLOT_LAYER &&
9005           i != VARYING_SLOT_PRIMITIVE_ID)
9006          continue;
9007
9008       export_vs_varying(ctx, i, false, NULL);
9009    }
9010 }
9011
9012 static void export_fs_mrt_z(isel_context *ctx)
9013 {
9014    Builder bld(ctx->program, ctx->block);
9015    unsigned enabled_channels = 0;
9016    bool compr = false;
9017    Operand values[4];
9018
9019    for (unsigned i = 0; i < 4; ++i) {
9020       values[i] = Operand(v1);
9021    }
9022
9023    /* Both stencil and sample mask only need 16-bits. */
9024    if (!ctx->program->info->ps.writes_z &&
9025        (ctx->program->info->ps.writes_stencil ||
9026         ctx->program->info->ps.writes_sample_mask)) {
9027       compr = true; /* COMPR flag */
9028
9029       if (ctx->program->info->ps.writes_stencil) {
9030          /* Stencil should be in X[23:16]. */
9031          values[0] = Operand(ctx->outputs.outputs[FRAG_RESULT_STENCIL][0]);
9032          values[0] = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(16u), values[0]);
9033          enabled_channels |= 0x3;
9034       }
9035
9036       if (ctx->program->info->ps.writes_sample_mask) {
9037          /* SampleMask should be in Y[15:0]. */
9038          values[1] = Operand(ctx->outputs.outputs[FRAG_RESULT_SAMPLE_MASK][0]);
9039          enabled_channels |= 0xc;
9040      }
9041    } else {
9042       if (ctx->program->info->ps.writes_z) {
9043          values[0] = Operand(ctx->outputs.outputs[FRAG_RESULT_DEPTH][0]);
9044          enabled_channels |= 0x1;
9045       }
9046
9047       if (ctx->program->info->ps.writes_stencil) {
9048          values[1] = Operand(ctx->outputs.outputs[FRAG_RESULT_STENCIL][0]);
9049          enabled_channels |= 0x2;
9050       }
9051
9052       if (ctx->program->info->ps.writes_sample_mask) {
9053          values[2] = Operand(ctx->outputs.outputs[FRAG_RESULT_SAMPLE_MASK][0]);
9054          enabled_channels |= 0x4;
9055       }
9056    }
9057
9058    /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9059     * writemask component.
9060     */
9061    if (ctx->options->chip_class == GFX6 &&
9062        ctx->options->family != CHIP_OLAND &&
9063        ctx->options->family != CHIP_HAINAN) {
9064             enabled_channels |= 0x1;
9065    }
9066
9067    bld.exp(aco_opcode::exp, values[0], values[1], values[2], values[3],
9068            enabled_channels, V_008DFC_SQ_EXP_MRTZ, compr);
9069 }
9070
9071 static void export_fs_mrt_color(isel_context *ctx, int slot)
9072 {
9073    Builder bld(ctx->program, ctx->block);
9074    unsigned write_mask = ctx->outputs.mask[slot];
9075    Operand values[4];
9076
9077    for (unsigned i = 0; i < 4; ++i) {
9078       if (write_mask & (1 << i)) {
9079          values[i] = Operand(ctx->outputs.outputs[slot][i]);
9080       } else {
9081          values[i] = Operand(v1);
9082       }
9083    }
9084
9085    unsigned target, col_format;
9086    unsigned enabled_channels = 0;
9087    aco_opcode compr_op = (aco_opcode)0;
9088
9089    slot -= FRAG_RESULT_DATA0;
9090    target = V_008DFC_SQ_EXP_MRT + slot;
9091    col_format = (ctx->options->key.fs.col_format >> (4 * slot)) & 0xf;
9092
9093    bool is_int8 = (ctx->options->key.fs.is_int8 >> slot) & 1;
9094    bool is_int10 = (ctx->options->key.fs.is_int10 >> slot) & 1;
9095
9096    switch (col_format)
9097    {
9098    case V_028714_SPI_SHADER_ZERO:
9099       enabled_channels = 0; /* writemask */
9100       target = V_008DFC_SQ_EXP_NULL;
9101       break;
9102
9103    case V_028714_SPI_SHADER_32_R:
9104       enabled_channels = 1;
9105       break;
9106
9107    case V_028714_SPI_SHADER_32_GR:
9108       enabled_channels = 0x3;
9109       break;
9110
9111    case V_028714_SPI_SHADER_32_AR:
9112       if (ctx->options->chip_class >= GFX10) {
9113          /* Special case: on GFX10, the outputs are different for 32_AR */
9114          enabled_channels = 0x3;
9115          values[1] = values[3];
9116          values[3] = Operand(v1);
9117       } else {
9118          enabled_channels = 0x9;
9119       }
9120       break;
9121
9122    case V_028714_SPI_SHADER_FP16_ABGR:
9123       enabled_channels = 0x5;
9124       compr_op = aco_opcode::v_cvt_pkrtz_f16_f32;
9125       break;
9126
9127    case V_028714_SPI_SHADER_UNORM16_ABGR:
9128       enabled_channels = 0x5;
9129       compr_op = aco_opcode::v_cvt_pknorm_u16_f32;
9130       break;
9131
9132    case V_028714_SPI_SHADER_SNORM16_ABGR:
9133       enabled_channels = 0x5;
9134       compr_op = aco_opcode::v_cvt_pknorm_i16_f32;
9135       break;
9136
9137    case V_028714_SPI_SHADER_UINT16_ABGR: {
9138       enabled_channels = 0x5;
9139       compr_op = aco_opcode::v_cvt_pk_u16_u32;
9140       if (is_int8 || is_int10) {
9141          /* clamp */
9142          uint32_t max_rgb = is_int8 ? 255 : is_int10 ? 1023 : 0;
9143          Temp max_rgb_val = bld.copy(bld.def(s1), Operand(max_rgb));
9144
9145          for (unsigned i = 0; i < 4; i++) {
9146             if ((write_mask >> i) & 1) {
9147                values[i] = bld.vop2(aco_opcode::v_min_u32, bld.def(v1),
9148                                     i == 3 && is_int10 ? Operand(3u) : Operand(max_rgb_val),
9149                                     values[i]);
9150             }
9151          }
9152       }
9153       break;
9154    }
9155
9156    case V_028714_SPI_SHADER_SINT16_ABGR:
9157       enabled_channels = 0x5;
9158       compr_op = aco_opcode::v_cvt_pk_i16_i32;
9159       if (is_int8 || is_int10) {
9160          /* clamp */
9161          uint32_t max_rgb = is_int8 ? 127 : is_int10 ? 511 : 0;
9162          uint32_t min_rgb = is_int8 ? -128 :is_int10 ? -512 : 0;
9163          Temp max_rgb_val = bld.copy(bld.def(s1), Operand(max_rgb));
9164          Temp min_rgb_val = bld.copy(bld.def(s1), Operand(min_rgb));
9165
9166          for (unsigned i = 0; i < 4; i++) {
9167             if ((write_mask >> i) & 1) {
9168                values[i] = bld.vop2(aco_opcode::v_min_i32, bld.def(v1),
9169                                     i == 3 && is_int10 ? Operand(1u) : Operand(max_rgb_val),
9170                                     values[i]);
9171                values[i] = bld.vop2(aco_opcode::v_max_i32, bld.def(v1),
9172                                     i == 3 && is_int10 ? Operand(-2u) : Operand(min_rgb_val),
9173                                     values[i]);
9174             }
9175          }
9176       }
9177       break;
9178
9179    case V_028714_SPI_SHADER_32_ABGR:
9180       enabled_channels = 0xF;
9181       break;
9182
9183    default:
9184       break;
9185    }
9186
9187    if (target == V_008DFC_SQ_EXP_NULL)
9188       return;
9189
9190    if ((bool) compr_op) {
9191       for (int i = 0; i < 2; i++) {
9192          /* check if at least one of the values to be compressed is enabled */
9193          unsigned enabled = (write_mask >> (i*2) | write_mask >> (i*2+1)) & 0x1;
9194          if (enabled) {
9195             enabled_channels |= enabled << (i*2);
9196             values[i] = bld.vop3(compr_op, bld.def(v1),
9197                                  values[i*2].isUndefined() ? Operand(0u) : values[i*2],
9198                                  values[i*2+1].isUndefined() ? Operand(0u): values[i*2+1]);
9199          } else {
9200             values[i] = Operand(v1);
9201          }
9202       }
9203       values[2] = Operand(v1);
9204       values[3] = Operand(v1);
9205    } else {
9206       for (int i = 0; i < 4; i++)
9207          values[i] = enabled_channels & (1 << i) ? values[i] : Operand(v1);
9208    }
9209
9210    bld.exp(aco_opcode::exp, values[0], values[1], values[2], values[3],
9211            enabled_channels, target, (bool) compr_op);
9212 }
9213
9214 static void create_fs_exports(isel_context *ctx)
9215 {
9216    /* Export depth, stencil and sample mask. */
9217    if (ctx->outputs.mask[FRAG_RESULT_DEPTH] ||
9218        ctx->outputs.mask[FRAG_RESULT_STENCIL] ||
9219        ctx->outputs.mask[FRAG_RESULT_SAMPLE_MASK]) {
9220       export_fs_mrt_z(ctx);
9221    }
9222
9223    /* Export all color render targets. */
9224    for (unsigned i = FRAG_RESULT_DATA0; i < FRAG_RESULT_DATA7 + 1; ++i) {
9225       if (ctx->outputs.mask[i])
9226          export_fs_mrt_color(ctx, i);
9227    }
9228 }
9229
9230 static void write_tcs_tess_factors(isel_context *ctx)
9231 {
9232    unsigned outer_comps;
9233    unsigned inner_comps;
9234
9235    switch (ctx->args->options->key.tcs.primitive_mode) {
9236    case GL_ISOLINES:
9237       outer_comps = 2;
9238       inner_comps = 0;
9239       break;
9240    case GL_TRIANGLES:
9241       outer_comps = 3;
9242       inner_comps = 1;
9243       break;
9244    case GL_QUADS:
9245       outer_comps = 4;
9246       inner_comps = 2;
9247       break;
9248    default:
9249       return;
9250    }
9251
9252    const unsigned tess_index_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
9253    const unsigned tess_index_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
9254
9255    Builder bld(ctx->program, ctx->block);
9256
9257    bld.barrier(aco_opcode::p_memory_barrier_shared);
9258    unsigned workgroup_size = ctx->tcs_num_patches * ctx->shader->info.tess.tcs_vertices_out;
9259    if (unlikely(ctx->program->chip_class != GFX6 && workgroup_size > ctx->program->wave_size))
9260       bld.sopp(aco_opcode::s_barrier);
9261
9262    Temp tcs_rel_ids = get_arg(ctx, ctx->args->ac.tcs_rel_ids);
9263    Temp invocation_id = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1), tcs_rel_ids, Operand(8u), Operand(5u));
9264
9265    Temp invocation_id_is_zero = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), invocation_id);
9266    if_context ic_invocation_id_is_zero;
9267    begin_divergent_if_then(ctx, &ic_invocation_id_is_zero, invocation_id_is_zero);
9268    bld.reset(ctx->block);
9269
9270    Temp hs_ring_tess_factor = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_HS_TESS_FACTOR * 16u));
9271
9272    std::pair<Temp, unsigned> lds_base = get_tcs_output_lds_offset(ctx);
9273    unsigned stride = inner_comps + outer_comps;
9274    Temp inner[4];
9275    Temp outer[4];
9276    Temp out[6];
9277    assert(inner_comps <= (sizeof(inner) / sizeof(Temp)));
9278    assert(outer_comps <= (sizeof(outer) / sizeof(Temp)));
9279    assert(stride <= (sizeof(out) / sizeof(Temp)));
9280
9281    if (ctx->args->options->key.tcs.primitive_mode == GL_ISOLINES) {
9282       // LINES reversal
9283       outer[0] = out[1] = load_lds(ctx, 4, bld.tmp(v1), lds_base.first, lds_base.second + tess_index_outer * 16 + 0 * 4, 4);
9284       outer[1] = out[0] = load_lds(ctx, 4, bld.tmp(v1), lds_base.first, lds_base.second + tess_index_outer * 16 + 1 * 4, 4);
9285    } else {
9286       for (unsigned i = 0; i < outer_comps; ++i)
9287          outer[i] = out[i] = load_lds(ctx, 4, bld.tmp(v1), lds_base.first, lds_base.second + tess_index_outer * 16 + i * 4, 4);
9288
9289       for (unsigned i = 0; i < inner_comps; ++i)
9290          inner[i] = out[outer_comps + i] = load_lds(ctx, 4, bld.tmp(v1), lds_base.first, lds_base.second + tess_index_inner * 16 + i * 4, 4);
9291    }
9292
9293    Temp rel_patch_id = get_tess_rel_patch_id(ctx);
9294    Temp tf_base = get_arg(ctx, ctx->args->tess_factor_offset);
9295    Temp byte_offset = bld.v_mul_imm(bld.def(v1), rel_patch_id, stride * 4u);
9296    unsigned tf_const_offset = 0;
9297
9298    if (ctx->program->chip_class <= GFX8) {
9299       Temp rel_patch_id_is_zero = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), rel_patch_id);
9300       if_context ic_rel_patch_id_is_zero;
9301       begin_divergent_if_then(ctx, &ic_rel_patch_id_is_zero, rel_patch_id_is_zero);
9302       bld.reset(ctx->block);
9303
9304       /* Store the dynamic HS control word. */
9305       Temp control_word = bld.copy(bld.def(v1), Operand(0x80000000u));
9306       bld.mubuf(aco_opcode::buffer_store_dword,
9307                 /* SRSRC */ hs_ring_tess_factor, /* VADDR */ Operand(v1), /* SOFFSET */ tf_base, /* VDATA */ control_word,
9308                 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
9309                 /* disable_wqm */ false, /* glc */ true);
9310       tf_const_offset += 4;
9311
9312       begin_divergent_if_else(ctx, &ic_rel_patch_id_is_zero);
9313       end_divergent_if(ctx, &ic_rel_patch_id_is_zero);
9314       bld.reset(ctx->block);
9315    }
9316
9317    assert(stride == 2 || stride == 4 || stride == 6);
9318    Temp tf_vec = create_vec_from_array(ctx, out, stride, RegType::vgpr);
9319    store_vmem_mubuf(ctx, tf_vec, hs_ring_tess_factor, byte_offset, tf_base, tf_const_offset, 4, (1 << stride) - 1, true, false);
9320
9321    /* Store to offchip for TES to read - only if TES reads them */
9322    if (ctx->args->options->key.tcs.tes_reads_tess_factors) {
9323       Temp hs_ring_tess_offchip = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_HS_TESS_OFFCHIP * 16u));
9324       Temp oc_lds = get_arg(ctx, ctx->args->oc_lds);
9325
9326       std::pair<Temp, unsigned> vmem_offs_outer = get_tcs_per_patch_output_vmem_offset(ctx, nullptr, tess_index_outer * 16);
9327       Temp outer_vec = create_vec_from_array(ctx, outer, outer_comps, RegType::vgpr);
9328       store_vmem_mubuf(ctx, outer_vec, hs_ring_tess_offchip, vmem_offs_outer.first, oc_lds, vmem_offs_outer.second, 4, (1 << outer_comps) - 1, true, false);
9329
9330       if (likely(inner_comps)) {
9331          std::pair<Temp, unsigned> vmem_offs_inner = get_tcs_per_patch_output_vmem_offset(ctx, nullptr, tess_index_inner * 16);
9332          Temp inner_vec = create_vec_from_array(ctx, inner, inner_comps, RegType::vgpr);
9333          store_vmem_mubuf(ctx, inner_vec, hs_ring_tess_offchip, vmem_offs_inner.first, oc_lds, vmem_offs_inner.second, 4, (1 << inner_comps) - 1, true, false);
9334       }
9335    }
9336
9337    begin_divergent_if_else(ctx, &ic_invocation_id_is_zero);
9338    end_divergent_if(ctx, &ic_invocation_id_is_zero);
9339 }
9340
9341 static void emit_stream_output(isel_context *ctx,
9342                                Temp const *so_buffers,
9343                                Temp const *so_write_offset,
9344                                const struct radv_stream_output *output)
9345 {
9346    unsigned num_comps = util_bitcount(output->component_mask);
9347    unsigned writemask = (1 << num_comps) - 1;
9348    unsigned loc = output->location;
9349    unsigned buf = output->buffer;
9350
9351    assert(num_comps && num_comps <= 4);
9352    if (!num_comps || num_comps > 4)
9353       return;
9354
9355    unsigned start = ffs(output->component_mask) - 1;
9356
9357    Temp out[4];
9358    bool all_undef = true;
9359    assert(ctx->stage == vertex_vs || ctx->stage == gs_copy_vs);
9360    for (unsigned i = 0; i < num_comps; i++) {
9361       out[i] = ctx->outputs.outputs[loc][start + i];
9362       all_undef = all_undef && !out[i].id();
9363    }
9364    if (all_undef)
9365       return;
9366
9367    while (writemask) {
9368       int start, count;
9369       u_bit_scan_consecutive_range(&writemask, &start, &count);
9370       if (count == 3 && ctx->options->chip_class == GFX6) {
9371          /* GFX6 doesn't support storing vec3, split it. */
9372          writemask |= 1u << (start + 2);
9373          count = 2;
9374       }
9375
9376       unsigned offset = output->offset + start * 4;
9377
9378       Temp write_data = {ctx->program->allocateId(), RegClass(RegType::vgpr, count)};
9379       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
9380       for (int i = 0; i < count; ++i)
9381          vec->operands[i] = (ctx->outputs.mask[loc] & 1 << (start + i)) ? Operand(out[start + i]) : Operand(0u);
9382       vec->definitions[0] = Definition(write_data);
9383       ctx->block->instructions.emplace_back(std::move(vec));
9384
9385       aco_opcode opcode;
9386       switch (count) {
9387       case 1:
9388          opcode = aco_opcode::buffer_store_dword;
9389          break;
9390       case 2:
9391          opcode = aco_opcode::buffer_store_dwordx2;
9392          break;
9393       case 3:
9394          opcode = aco_opcode::buffer_store_dwordx3;
9395          break;
9396       case 4:
9397          opcode = aco_opcode::buffer_store_dwordx4;
9398          break;
9399       default:
9400          unreachable("Unsupported dword count.");
9401       }
9402
9403       aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 4, 0)};
9404       store->operands[0] = Operand(so_buffers[buf]);
9405       store->operands[1] = Operand(so_write_offset[buf]);
9406       store->operands[2] = Operand((uint32_t) 0);
9407       store->operands[3] = Operand(write_data);
9408       if (offset > 4095) {
9409          /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
9410          Builder bld(ctx->program, ctx->block);
9411          store->operands[0] = bld.vadd32(bld.def(v1), Operand(offset), Operand(so_write_offset[buf]));
9412       } else {
9413          store->offset = offset;
9414       }
9415       store->offen = true;
9416       store->glc = true;
9417       store->dlc = false;
9418       store->slc = true;
9419       store->can_reorder = true;
9420       ctx->block->instructions.emplace_back(std::move(store));
9421    }
9422 }
9423
9424 static void emit_streamout(isel_context *ctx, unsigned stream)
9425 {
9426    Builder bld(ctx->program, ctx->block);
9427
9428    Temp so_buffers[4];
9429    Temp buf_ptr = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->streamout_buffers));
9430    for (unsigned i = 0; i < 4; i++) {
9431       unsigned stride = ctx->program->info->so.strides[i];
9432       if (!stride)
9433          continue;
9434
9435       Operand off = bld.copy(bld.def(s1), Operand(i * 16u));
9436       so_buffers[i] = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), buf_ptr, off);
9437    }
9438
9439    Temp so_vtx_count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
9440                                 get_arg(ctx, ctx->args->streamout_config), Operand(0x70010u));
9441
9442    Temp tid = emit_mbcnt(ctx, bld.def(v1));
9443
9444    Temp can_emit = bld.vopc(aco_opcode::v_cmp_gt_i32, bld.def(bld.lm), so_vtx_count, tid);
9445
9446    if_context ic;
9447    begin_divergent_if_then(ctx, &ic, can_emit);
9448
9449    bld.reset(ctx->block);
9450
9451    Temp so_write_index = bld.vadd32(bld.def(v1), get_arg(ctx, ctx->args->streamout_write_idx), tid);
9452
9453    Temp so_write_offset[4];
9454
9455    for (unsigned i = 0; i < 4; i++) {
9456       unsigned stride = ctx->program->info->so.strides[i];
9457       if (!stride)
9458          continue;
9459
9460       if (stride == 1) {
9461          Temp offset = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
9462                                 get_arg(ctx, ctx->args->streamout_write_idx),
9463                                 get_arg(ctx, ctx->args->streamout_offset[i]));
9464          Temp new_offset = bld.vadd32(bld.def(v1), offset, tid);
9465
9466          so_write_offset[i] = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), new_offset);
9467       } else {
9468          Temp offset = bld.v_mul_imm(bld.def(v1), so_write_index, stride * 4u);
9469          Temp offset2 = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(4u),
9470                                  get_arg(ctx, ctx->args->streamout_offset[i]));
9471          so_write_offset[i] = bld.vadd32(bld.def(v1), offset, offset2);
9472       }
9473    }
9474
9475    for (unsigned i = 0; i < ctx->program->info->so.num_outputs; i++) {
9476       struct radv_stream_output *output =
9477          &ctx->program->info->so.outputs[i];
9478       if (stream != output->stream)
9479          continue;
9480
9481       emit_stream_output(ctx, so_buffers, so_write_offset, output);
9482    }
9483
9484    begin_divergent_if_else(ctx, &ic);
9485    end_divergent_if(ctx, &ic);
9486 }
9487
9488 } /* end namespace */
9489
9490 void fix_ls_vgpr_init_bug(isel_context *ctx, Pseudo_instruction *startpgm)
9491 {
9492    assert(ctx->shader->info.stage == MESA_SHADER_VERTEX);
9493    Builder bld(ctx->program, ctx->block);
9494    constexpr unsigned hs_idx = 1u;
9495    Builder::Result hs_thread_count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
9496                                               get_arg(ctx, ctx->args->merged_wave_info),
9497                                               Operand((8u << 16) | (hs_idx * 8u)));
9498    Temp ls_has_nonzero_hs_threads = bool_to_vector_condition(ctx, hs_thread_count.def(1).getTemp());
9499
9500    /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
9501
9502    Temp instance_id = bld.sop2(aco_opcode::v_cndmask_b32, bld.def(v1),
9503                                get_arg(ctx, ctx->args->ac.instance_id),
9504                                get_arg(ctx, ctx->args->rel_auto_id),
9505                                ls_has_nonzero_hs_threads);
9506    Temp rel_auto_id = bld.sop2(aco_opcode::v_cndmask_b32, bld.def(v1),
9507                                get_arg(ctx, ctx->args->rel_auto_id),
9508                                get_arg(ctx, ctx->args->ac.tcs_rel_ids),
9509                                ls_has_nonzero_hs_threads);
9510    Temp vertex_id = bld.sop2(aco_opcode::v_cndmask_b32, bld.def(v1),
9511                              get_arg(ctx, ctx->args->ac.vertex_id),
9512                              get_arg(ctx, ctx->args->ac.tcs_patch_id),
9513                              ls_has_nonzero_hs_threads);
9514
9515    ctx->arg_temps[ctx->args->ac.instance_id.arg_index] = instance_id;
9516    ctx->arg_temps[ctx->args->rel_auto_id.arg_index] = rel_auto_id;
9517    ctx->arg_temps[ctx->args->ac.vertex_id.arg_index] = vertex_id;
9518 }
9519
9520 void split_arguments(isel_context *ctx, Pseudo_instruction *startpgm)
9521 {
9522    /* Split all arguments except for the first (ring_offsets) and the last
9523     * (exec) so that the dead channels don't stay live throughout the program.
9524     */
9525    for (int i = 1; i < startpgm->definitions.size() - 1; i++) {
9526       if (startpgm->definitions[i].regClass().size() > 1) {
9527          emit_split_vector(ctx, startpgm->definitions[i].getTemp(),
9528                            startpgm->definitions[i].regClass().size());
9529       }
9530    }
9531 }
9532
9533 void handle_bc_optimize(isel_context *ctx)
9534 {
9535    /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
9536    Builder bld(ctx->program, ctx->block);
9537    uint32_t spi_ps_input_ena = ctx->program->config->spi_ps_input_ena;
9538    bool uses_center = G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena);
9539    bool uses_centroid = G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena);
9540    ctx->persp_centroid = get_arg(ctx, ctx->args->ac.persp_centroid);
9541    ctx->linear_centroid = get_arg(ctx, ctx->args->ac.linear_centroid);
9542    if (uses_center && uses_centroid) {
9543       Temp sel = bld.vopc_e64(aco_opcode::v_cmp_lt_i32, bld.hint_vcc(bld.def(bld.lm)),
9544                               get_arg(ctx, ctx->args->ac.prim_mask), Operand(0u));
9545
9546       if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena)) {
9547          Temp new_coord[2];
9548          for (unsigned i = 0; i < 2; i++) {
9549             Temp persp_centroid = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.persp_centroid), i, v1);
9550             Temp persp_center = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.persp_center), i, v1);
9551             new_coord[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
9552                                     persp_centroid, persp_center, sel);
9553          }
9554          ctx->persp_centroid = bld.tmp(v2);
9555          bld.pseudo(aco_opcode::p_create_vector, Definition(ctx->persp_centroid),
9556                     Operand(new_coord[0]), Operand(new_coord[1]));
9557          emit_split_vector(ctx, ctx->persp_centroid, 2);
9558       }
9559
9560       if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena)) {
9561          Temp new_coord[2];
9562          for (unsigned i = 0; i < 2; i++) {
9563             Temp linear_centroid = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.linear_centroid), i, v1);
9564             Temp linear_center = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.linear_center), i, v1);
9565             new_coord[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
9566                                     linear_centroid, linear_center, sel);
9567          }
9568          ctx->linear_centroid = bld.tmp(v2);
9569          bld.pseudo(aco_opcode::p_create_vector, Definition(ctx->linear_centroid),
9570                     Operand(new_coord[0]), Operand(new_coord[1]));
9571          emit_split_vector(ctx, ctx->linear_centroid, 2);
9572       }
9573    }
9574 }
9575
9576 void setup_fp_mode(isel_context *ctx, nir_shader *shader)
9577 {
9578    Program *program = ctx->program;
9579
9580    unsigned float_controls = shader->info.float_controls_execution_mode;
9581
9582    program->next_fp_mode.preserve_signed_zero_inf_nan32 =
9583       float_controls & FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32;
9584    program->next_fp_mode.preserve_signed_zero_inf_nan16_64 =
9585       float_controls & (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16 |
9586                         FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64);
9587
9588    program->next_fp_mode.must_flush_denorms32 =
9589       float_controls & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32;
9590    program->next_fp_mode.must_flush_denorms16_64 =
9591       float_controls & (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16 |
9592                         FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64);
9593
9594    program->next_fp_mode.care_about_round32 =
9595       float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32 | FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32);
9596
9597    program->next_fp_mode.care_about_round16_64 =
9598       float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64 |
9599                         FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64);
9600
9601    /* default to preserving fp16 and fp64 denorms, since it's free */
9602    if (program->next_fp_mode.must_flush_denorms16_64)
9603       program->next_fp_mode.denorm16_64 = 0;
9604    else
9605       program->next_fp_mode.denorm16_64 = fp_denorm_keep;
9606
9607    /* preserving fp32 denorms is expensive, so only do it if asked */
9608    if (float_controls & FLOAT_CONTROLS_DENORM_PRESERVE_FP32)
9609       program->next_fp_mode.denorm32 = fp_denorm_keep;
9610    else
9611       program->next_fp_mode.denorm32 = 0;
9612
9613    if (float_controls & FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32)
9614       program->next_fp_mode.round32 = fp_round_tz;
9615    else
9616       program->next_fp_mode.round32 = fp_round_ne;
9617
9618    if (float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64))
9619       program->next_fp_mode.round16_64 = fp_round_tz;
9620    else
9621       program->next_fp_mode.round16_64 = fp_round_ne;
9622
9623    ctx->block->fp_mode = program->next_fp_mode;
9624 }
9625
9626 void cleanup_cfg(Program *program)
9627 {
9628    /* create linear_succs/logical_succs */
9629    for (Block& BB : program->blocks) {
9630       for (unsigned idx : BB.linear_preds)
9631          program->blocks[idx].linear_succs.emplace_back(BB.index);
9632       for (unsigned idx : BB.logical_preds)
9633          program->blocks[idx].logical_succs.emplace_back(BB.index);
9634    }
9635 }
9636
9637 void select_program(Program *program,
9638                     unsigned shader_count,
9639                     struct nir_shader *const *shaders,
9640                     ac_shader_config* config,
9641                     struct radv_shader_args *args)
9642 {
9643    isel_context ctx = setup_isel_context(program, shader_count, shaders, config, args, false);
9644
9645    for (unsigned i = 0; i < shader_count; i++) {
9646       nir_shader *nir = shaders[i];
9647       init_context(&ctx, nir);
9648
9649       setup_fp_mode(&ctx, nir);
9650
9651       if (!i) {
9652          /* needs to be after init_context() for FS */
9653          Pseudo_instruction *startpgm = add_startpgm(&ctx);
9654          append_logical_start(ctx.block);
9655
9656          if (unlikely(args->options->has_ls_vgpr_init_bug && ctx.stage == vertex_tess_control_hs))
9657             fix_ls_vgpr_init_bug(&ctx, startpgm);
9658
9659          split_arguments(&ctx, startpgm);
9660       }
9661
9662       /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
9663       nir_function_impl *func = nir_shader_get_entrypoint(nir);
9664       bool empty_shader = nir_cf_list_is_empty_block(&func->body) &&
9665                           ((nir->info.stage == MESA_SHADER_VERTEX &&
9666                             (ctx.stage == vertex_tess_control_hs || ctx.stage == vertex_geometry_gs)) ||
9667                            (nir->info.stage == MESA_SHADER_TESS_EVAL &&
9668                             ctx.stage == tess_eval_geometry_gs));
9669
9670       if_context ic;
9671       if (shader_count >= 2 && !empty_shader) {
9672          Builder bld(ctx.program, ctx.block);
9673          Temp count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), get_arg(&ctx, args->merged_wave_info), Operand((8u << 16) | (i * 8u)));
9674          Temp thread_id = emit_mbcnt(&ctx, bld.def(v1));
9675          Temp cond = bld.vopc(aco_opcode::v_cmp_gt_u32, bld.hint_vcc(bld.def(bld.lm)), count, thread_id);
9676
9677          begin_divergent_if_then(&ctx, &ic, cond);
9678       }
9679
9680       if (i) {
9681          Builder bld(ctx.program, ctx.block);
9682
9683          bld.barrier(aco_opcode::p_memory_barrier_shared);
9684          bld.sopp(aco_opcode::s_barrier);
9685
9686          if (ctx.stage == vertex_geometry_gs || ctx.stage == tess_eval_geometry_gs) {
9687             ctx.gs_wave_id = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1, m0), bld.def(s1, scc), get_arg(&ctx, args->merged_wave_info), Operand((8u << 16) | 16u));
9688          }
9689       } else if (ctx.stage == geometry_gs)
9690          ctx.gs_wave_id = get_arg(&ctx, args->gs_wave_id);
9691
9692       if (ctx.stage == fragment_fs)
9693          handle_bc_optimize(&ctx);
9694
9695       visit_cf_list(&ctx, &func->body);
9696
9697       if (ctx.program->info->so.num_outputs && (ctx.stage == vertex_vs || ctx.stage == tess_eval_vs))
9698          emit_streamout(&ctx, 0);
9699
9700       if (ctx.stage == vertex_vs || ctx.stage == tess_eval_vs) {
9701          create_vs_exports(&ctx);
9702       } else if (nir->info.stage == MESA_SHADER_GEOMETRY) {
9703          Builder bld(ctx.program, ctx.block);
9704          bld.barrier(aco_opcode::p_memory_barrier_gs_data);
9705          bld.sopp(aco_opcode::s_sendmsg, bld.m0(ctx.gs_wave_id), -1, sendmsg_gs_done(false, false, 0));
9706       } else if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
9707          write_tcs_tess_factors(&ctx);
9708       }
9709
9710       if (ctx.stage == fragment_fs)
9711          create_fs_exports(&ctx);
9712
9713       if (shader_count >= 2 && !empty_shader) {
9714          begin_divergent_if_else(&ctx, &ic);
9715          end_divergent_if(&ctx, &ic);
9716       }
9717
9718       ralloc_free(ctx.divergent_vals);
9719    }
9720
9721    program->config->float_mode = program->blocks[0].fp_mode.val;
9722
9723    append_logical_end(ctx.block);
9724    ctx.block->kind |= block_kind_uniform | block_kind_export_end;
9725    Builder bld(ctx.program, ctx.block);
9726    if (ctx.program->wb_smem_l1_on_end)
9727       bld.smem(aco_opcode::s_dcache_wb, false);
9728    bld.sopp(aco_opcode::s_endpgm);
9729
9730    cleanup_cfg(program);
9731 }
9732
9733 void select_gs_copy_shader(Program *program, struct nir_shader *gs_shader,
9734                            ac_shader_config* config,
9735                            struct radv_shader_args *args)
9736 {
9737    isel_context ctx = setup_isel_context(program, 1, &gs_shader, config, args, true);
9738
9739    program->next_fp_mode.preserve_signed_zero_inf_nan32 = false;
9740    program->next_fp_mode.preserve_signed_zero_inf_nan16_64 = false;
9741    program->next_fp_mode.must_flush_denorms32 = false;
9742    program->next_fp_mode.must_flush_denorms16_64 = false;
9743    program->next_fp_mode.care_about_round32 = false;
9744    program->next_fp_mode.care_about_round16_64 = false;
9745    program->next_fp_mode.denorm16_64 = fp_denorm_keep;
9746    program->next_fp_mode.denorm32 = 0;
9747    program->next_fp_mode.round32 = fp_round_ne;
9748    program->next_fp_mode.round16_64 = fp_round_ne;
9749    ctx.block->fp_mode = program->next_fp_mode;
9750
9751    add_startpgm(&ctx);
9752    append_logical_start(ctx.block);
9753
9754    Builder bld(ctx.program, ctx.block);
9755
9756    Temp gsvs_ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), program->private_segment_buffer, Operand(RING_GSVS_VS * 16u));
9757
9758    Operand stream_id(0u);
9759    if (args->shader_info->so.num_outputs)
9760       stream_id = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
9761                            get_arg(&ctx, ctx.args->streamout_config), Operand(0x20018u));
9762
9763    Temp vtx_offset = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), get_arg(&ctx, ctx.args->ac.vertex_id));
9764
9765    std::stack<Block> endif_blocks;
9766
9767    for (unsigned stream = 0; stream < 4; stream++) {
9768       if (stream_id.isConstant() && stream != stream_id.constantValue())
9769          continue;
9770
9771       unsigned num_components = args->shader_info->gs.num_stream_output_components[stream];
9772       if (stream > 0 && (!num_components || !args->shader_info->so.num_outputs))
9773          continue;
9774
9775       memset(ctx.outputs.mask, 0, sizeof(ctx.outputs.mask));
9776
9777       unsigned BB_if_idx = ctx.block->index;
9778       Block BB_endif = Block();
9779       if (!stream_id.isConstant()) {
9780          /* begin IF */
9781          Temp cond = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), stream_id, Operand(stream));
9782          append_logical_end(ctx.block);
9783          ctx.block->kind |= block_kind_uniform;
9784          bld.branch(aco_opcode::p_cbranch_z, cond);
9785
9786          BB_endif.kind |= ctx.block->kind & block_kind_top_level;
9787
9788          ctx.block = ctx.program->create_and_insert_block();
9789          add_edge(BB_if_idx, ctx.block);
9790          bld.reset(ctx.block);
9791          append_logical_start(ctx.block);
9792       }
9793
9794       unsigned offset = 0;
9795       for (unsigned i = 0; i <= VARYING_SLOT_VAR31; ++i) {
9796          if (args->shader_info->gs.output_streams[i] != stream)
9797             continue;
9798
9799          unsigned output_usage_mask = args->shader_info->gs.output_usage_mask[i];
9800          unsigned length = util_last_bit(output_usage_mask);
9801          for (unsigned j = 0; j < length; ++j) {
9802             if (!(output_usage_mask & (1 << j)))
9803                continue;
9804
9805             unsigned const_offset = offset * args->shader_info->gs.vertices_out * 16 * 4;
9806             Temp voffset = vtx_offset;
9807             if (const_offset >= 4096u) {
9808                voffset = bld.vadd32(bld.def(v1), Operand(const_offset / 4096u * 4096u), voffset);
9809                const_offset %= 4096u;
9810             }
9811
9812             aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(aco_opcode::buffer_load_dword, Format::MUBUF, 3, 1)};
9813             mubuf->definitions[0] = bld.def(v1);
9814             mubuf->operands[0] = Operand(gsvs_ring);
9815             mubuf->operands[1] = Operand(voffset);
9816             mubuf->operands[2] = Operand(0u);
9817             mubuf->offen = true;
9818             mubuf->offset = const_offset;
9819             mubuf->glc = true;
9820             mubuf->slc = true;
9821             mubuf->dlc = args->options->chip_class >= GFX10;
9822             mubuf->barrier = barrier_none;
9823             mubuf->can_reorder = true;
9824
9825             ctx.outputs.mask[i] |= 1 << j;
9826             ctx.outputs.outputs[i][j] = mubuf->definitions[0].getTemp();
9827
9828             bld.insert(std::move(mubuf));
9829
9830             offset++;
9831          }
9832       }
9833
9834       if (args->shader_info->so.num_outputs) {
9835          emit_streamout(&ctx, stream);
9836          bld.reset(ctx.block);
9837       }
9838
9839       if (stream == 0) {
9840          create_vs_exports(&ctx);
9841          ctx.block->kind |= block_kind_export_end;
9842       }
9843
9844       if (!stream_id.isConstant()) {
9845          append_logical_end(ctx.block);
9846
9847          /* branch from then block to endif block */
9848          bld.branch(aco_opcode::p_branch);
9849          add_edge(ctx.block->index, &BB_endif);
9850          ctx.block->kind |= block_kind_uniform;
9851
9852          /* emit else block */
9853          ctx.block = ctx.program->create_and_insert_block();
9854          add_edge(BB_if_idx, ctx.block);
9855          bld.reset(ctx.block);
9856          append_logical_start(ctx.block);
9857
9858          endif_blocks.push(std::move(BB_endif));
9859       }
9860    }
9861
9862    while (!endif_blocks.empty()) {
9863       Block BB_endif = std::move(endif_blocks.top());
9864       endif_blocks.pop();
9865
9866       Block *BB_else = ctx.block;
9867
9868       append_logical_end(BB_else);
9869       /* branch from else block to endif block */
9870       bld.branch(aco_opcode::p_branch);
9871       add_edge(BB_else->index, &BB_endif);
9872       BB_else->kind |= block_kind_uniform;
9873
9874       /** emit endif merge block */
9875       ctx.block = program->insert_block(std::move(BB_endif));
9876       bld.reset(ctx.block);
9877       append_logical_start(ctx.block);
9878    }
9879
9880    program->config->float_mode = program->blocks[0].fp_mode.val;
9881
9882    append_logical_end(ctx.block);
9883    ctx.block->kind |= block_kind_uniform;
9884    bld.sopp(aco_opcode::s_endpgm);
9885
9886    cleanup_cfg(program);
9887 }
9888 }