src/amd/compiler/aco_instruction_selection.cpp

   1 /*
   2  * Copyright © 2018 Valve Corporation
   3  * Copyright © 2018 Google
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <algorithm>
  27 #include <array>
  28 #include <stack>
  29 #include <map>
  30
  31 #include "ac_shader_util.h"
  32 #include "aco_ir.h"
  33 #include "aco_builder.h"
  34 #include "aco_interface.h"
  35 #include "aco_instruction_selection_setup.cpp"
  36 #include "util/fast_idiv_by_const.h"
  37
  38 namespace aco {
  39 namespace {
  40
  41 class loop_info_RAII {
  42    isel_context* ctx;
  43    unsigned header_idx_old;
  44    Block* exit_old;
  45    bool divergent_cont_old;
  46    bool divergent_branch_old;
  47    bool divergent_if_old;
  48
  49 public:
  50    loop_info_RAII(isel_context* ctx, unsigned loop_header_idx, Block* loop_exit)
  51       : ctx(ctx),
  52         header_idx_old(ctx->cf_info.parent_loop.header_idx), exit_old(ctx->cf_info.parent_loop.exit),
  53         divergent_cont_old(ctx->cf_info.parent_loop.has_divergent_continue),
  54         divergent_branch_old(ctx->cf_info.parent_loop.has_divergent_branch),
  55         divergent_if_old(ctx->cf_info.parent_if.is_divergent)
  56    {
  57       ctx->cf_info.parent_loop.header_idx = loop_header_idx;
  58       ctx->cf_info.parent_loop.exit = loop_exit;
  59       ctx->cf_info.parent_loop.has_divergent_continue = false;
  60       ctx->cf_info.parent_loop.has_divergent_branch = false;
  61       ctx->cf_info.parent_if.is_divergent = false;
  62       ctx->cf_info.loop_nest_depth = ctx->cf_info.loop_nest_depth + 1;
  63    }
  64
  65    ~loop_info_RAII()
  66    {
  67       ctx->cf_info.parent_loop.header_idx = header_idx_old;
  68       ctx->cf_info.parent_loop.exit = exit_old;
  69       ctx->cf_info.parent_loop.has_divergent_continue = divergent_cont_old;
  70       ctx->cf_info.parent_loop.has_divergent_branch = divergent_branch_old;
  71       ctx->cf_info.parent_if.is_divergent = divergent_if_old;
  72       ctx->cf_info.loop_nest_depth = ctx->cf_info.loop_nest_depth - 1;
  73       if (!ctx->cf_info.loop_nest_depth && !ctx->cf_info.parent_if.is_divergent)
  74          ctx->cf_info.exec_potentially_empty_discard = false;
  75    }
  76 };
  77
  78 struct if_context {
  79    Temp cond;
  80
  81    bool divergent_old;
  82    bool exec_potentially_empty_discard_old;
  83    bool exec_potentially_empty_break_old;
  84    uint16_t exec_potentially_empty_break_depth_old;
  85
  86    unsigned BB_if_idx;
  87    unsigned invert_idx;
  88    bool then_branch_divergent;
  89    Block BB_invert;
  90    Block BB_endif;
  91 };
  92
  93 static void visit_cf_list(struct isel_context *ctx,
  94                           struct exec_list *list);
  95
  96 static void add_logical_edge(unsigned pred_idx, Block *succ)
  97 {
  98    succ->logical_preds.emplace_back(pred_idx);
  99 }
 100
 101
 102 static void add_linear_edge(unsigned pred_idx, Block *succ)
 103 {
 104    succ->linear_preds.emplace_back(pred_idx);
 105 }
 106
 107 static void add_edge(unsigned pred_idx, Block *succ)
 108 {
 109    add_logical_edge(pred_idx, succ);
 110    add_linear_edge(pred_idx, succ);
 111 }
 112
 113 static void append_logical_start(Block *b)
 114 {
 115    Builder(NULL, b).pseudo(aco_opcode::p_logical_start);
 116 }
 117
 118 static void append_logical_end(Block *b)
 119 {
 120    Builder(NULL, b).pseudo(aco_opcode::p_logical_end);
 121 }
 122
 123 Temp get_ssa_temp(struct isel_context *ctx, nir_ssa_def *def)
 124 {
 125    assert(ctx->allocated[def->index].id());
 126    return ctx->allocated[def->index];
 127 }
 128
 129 Temp emit_mbcnt(isel_context *ctx, Definition dst,
 130                 Operand mask_lo = Operand((uint32_t) -1), Operand mask_hi = Operand((uint32_t) -1))
 131 {
 132    Builder bld(ctx->program, ctx->block);
 133    Definition lo_def = ctx->program->wave_size == 32 ? dst : bld.def(v1);
 134    Temp thread_id_lo = bld.vop3(aco_opcode::v_mbcnt_lo_u32_b32, lo_def, mask_lo, Operand(0u));
 135
 136    if (ctx->program->wave_size == 32) {
 137       return thread_id_lo;
 138    } else {
 139       Temp thread_id_hi = bld.vop3(aco_opcode::v_mbcnt_hi_u32_b32, dst, mask_hi, thread_id_lo);
 140       return thread_id_hi;
 141    }
 142 }
 143
 144 Temp emit_wqm(isel_context *ctx, Temp src, Temp dst=Temp(0, s1), bool program_needs_wqm = false)
 145 {
 146    Builder bld(ctx->program, ctx->block);
 147
 148    if (!dst.id())
 149       dst = bld.tmp(src.regClass());
 150
 151    assert(src.size() == dst.size());
 152
 153    if (ctx->stage != fragment_fs) {
 154       if (!dst.id())
 155          return src;
 156
 157       bld.copy(Definition(dst), src);
 158       return dst;
 159    }
 160
 161    bld.pseudo(aco_opcode::p_wqm, Definition(dst), src);
 162    ctx->program->needs_wqm |= program_needs_wqm;
 163    return dst;
 164 }
 165
 166 static Temp emit_bpermute(isel_context *ctx, Builder &bld, Temp index, Temp data)
 167 {
 168    if (index.regClass() == s1)
 169       return bld.readlane(bld.def(s1), data, index);
 170
 171    Temp index_x4 = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), index);
 172
 173    /* Currently not implemented on GFX6-7 */
 174    assert(ctx->options->chip_class >= GFX8);
 175
 176    if (ctx->options->chip_class <= GFX9 || ctx->program->wave_size == 32) {
 177       return bld.ds(aco_opcode::ds_bpermute_b32, bld.def(v1), index_x4, data);
 178    }
 179
 180    /* GFX10, wave64 mode:
 181     * The bpermute instruction is limited to half-wave operation, which means that it can't
 182     * properly support subgroup shuffle like older generations (or wave32 mode), so we
 183     * emulate it here.
 184     */
 185    if (!ctx->has_gfx10_wave64_bpermute) {
 186       ctx->has_gfx10_wave64_bpermute = true;
 187       ctx->program->config->num_shared_vgprs = 8; /* Shared VGPRs are allocated in groups of 8 */
 188       ctx->program->vgpr_limit -= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
 189    }
 190
 191    Temp lane_id = emit_mbcnt(ctx, bld.def(v1));
 192    Temp lane_is_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x20u), lane_id);
 193    Temp index_is_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x20u), index);
 194    Temp cmp = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm, vcc), lane_is_hi, index_is_hi);
 195
 196    return bld.reduction(aco_opcode::p_wave64_bpermute, bld.def(v1), bld.def(s2), bld.def(s1, scc),
 197                         bld.vcc(cmp), Operand(v2.as_linear()), index_x4, data, gfx10_wave64_bpermute);
 198 }
 199
 200 Temp as_vgpr(isel_context *ctx, Temp val)
 201 {
 202    if (val.type() == RegType::sgpr) {
 203       Builder bld(ctx->program, ctx->block);
 204       return bld.copy(bld.def(RegType::vgpr, val.size()), val);
 205    }
 206    assert(val.type() == RegType::vgpr);
 207    return val;
 208 }
 209
 210 //assumes a != 0xffffffff
 211 void emit_v_div_u32(isel_context *ctx, Temp dst, Temp a, uint32_t b)
 212 {
 213    assert(b != 0);
 214    Builder bld(ctx->program, ctx->block);
 215
 216    if (util_is_power_of_two_or_zero(b)) {
 217       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(dst), Operand((uint32_t)util_logbase2(b)), a);
 218       return;
 219    }
 220
 221    util_fast_udiv_info info = util_compute_fast_udiv_info(b, 32, 32);
 222
 223    assert(info.multiplier <= 0xffffffff);
 224
 225    bool pre_shift = info.pre_shift != 0;
 226    bool increment = info.increment != 0;
 227    bool multiply = true;
 228    bool post_shift = info.post_shift != 0;
 229
 230    if (!pre_shift && !increment && !multiply && !post_shift) {
 231       bld.vop1(aco_opcode::v_mov_b32, Definition(dst), a);
 232       return;
 233    }
 234
 235    Temp pre_shift_dst = a;
 236    if (pre_shift) {
 237       pre_shift_dst = (increment || multiply || post_shift) ? bld.tmp(v1) : dst;
 238       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(pre_shift_dst), Operand((uint32_t)info.pre_shift), a);
 239    }
 240
 241    Temp increment_dst = pre_shift_dst;
 242    if (increment) {
 243       increment_dst = (post_shift || multiply) ? bld.tmp(v1) : dst;
 244       bld.vadd32(Definition(increment_dst), Operand((uint32_t) info.increment), pre_shift_dst);
 245    }
 246
 247    Temp multiply_dst = increment_dst;
 248    if (multiply) {
 249       multiply_dst = post_shift ? bld.tmp(v1) : dst;
 250       bld.vop3(aco_opcode::v_mul_hi_u32, Definition(multiply_dst), increment_dst,
 251                bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand((uint32_t)info.multiplier)));
 252    }
 253
 254    if (post_shift) {
 255       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(dst), Operand((uint32_t)info.post_shift), multiply_dst);
 256    }
 257 }
 258
 259 void emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, Temp dst)
 260 {
 261    Builder bld(ctx->program, ctx->block);
 262    bld.pseudo(aco_opcode::p_extract_vector, Definition(dst), src, Operand(idx));
 263 }
 264
 265
 266 Temp emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, RegClass dst_rc)
 267 {
 268    /* no need to extract the whole vector */
 269    if (src.regClass() == dst_rc) {
 270       assert(idx == 0);
 271       return src;
 272    }
 273    assert(src.size() > idx);
 274    Builder bld(ctx->program, ctx->block);
 275    auto it = ctx->allocated_vec.find(src.id());
 276    /* the size check needs to be early because elements other than 0 may be garbage */
 277    if (it != ctx->allocated_vec.end() && it->second[0].size() == dst_rc.size()) {
 278       if (it->second[idx].regClass() == dst_rc) {
 279          return it->second[idx];
 280       } else {
 281          assert(dst_rc.size() == it->second[idx].regClass().size());
 282          assert(dst_rc.type() == RegType::vgpr && it->second[idx].type() == RegType::sgpr);
 283          return bld.copy(bld.def(dst_rc), it->second[idx]);
 284       }
 285    }
 286
 287    if (src.size() == dst_rc.size()) {
 288       assert(idx == 0);
 289       return bld.copy(bld.def(dst_rc), src);
 290    } else {
 291       Temp dst = bld.tmp(dst_rc);
 292       emit_extract_vector(ctx, src, idx, dst);
 293       return dst;
 294    }
 295 }
 296
 297 void emit_split_vector(isel_context* ctx, Temp vec_src, unsigned num_components)
 298 {
 299    if (num_components == 1)
 300       return;
 301    if (ctx->allocated_vec.find(vec_src.id()) != ctx->allocated_vec.end())
 302       return;
 303    aco_ptr<Pseudo_instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector, Format::PSEUDO, 1, num_components)};
 304    split->operands[0] = Operand(vec_src);
 305    std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 306    for (unsigned i = 0; i < num_components; i++) {
 307       elems[i] = {ctx->program->allocateId(), RegClass(vec_src.type(), vec_src.size() / num_components)};
 308       split->definitions[i] = Definition(elems[i]);
 309    }
 310    ctx->block->instructions.emplace_back(std::move(split));
 311    ctx->allocated_vec.emplace(vec_src.id(), elems);
 312 }
 313
 314 /* This vector expansion uses a mask to determine which elements in the new vector
 315  * come from the original vector. The other elements are undefined. */
 316 void expand_vector(isel_context* ctx, Temp vec_src, Temp dst, unsigned num_components, unsigned mask)
 317 {
 318    emit_split_vector(ctx, vec_src, util_bitcount(mask));
 319
 320    if (vec_src == dst)
 321       return;
 322
 323    Builder bld(ctx->program, ctx->block);
 324    if (num_components == 1) {
 325       if (dst.type() == RegType::sgpr)
 326          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec_src);
 327       else
 328          bld.copy(Definition(dst), vec_src);
 329       return;
 330    }
 331
 332    unsigned component_size = dst.size() / num_components;
 333    std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 334
 335    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1)};
 336    vec->definitions[0] = Definition(dst);
 337    unsigned k = 0;
 338    for (unsigned i = 0; i < num_components; i++) {
 339       if (mask & (1 << i)) {
 340          Temp src = emit_extract_vector(ctx, vec_src, k++, RegClass(vec_src.type(), component_size));
 341          if (dst.type() == RegType::sgpr)
 342             src = bld.as_uniform(src);
 343          vec->operands[i] = Operand(src);
 344       } else {
 345          vec->operands[i] = Operand(0u);
 346       }
 347       elems[i] = vec->operands[i].getTemp();
 348    }
 349    ctx->block->instructions.emplace_back(std::move(vec));
 350    ctx->allocated_vec.emplace(dst.id(), elems);
 351 }
 352
 353 Temp bool_to_vector_condition(isel_context *ctx, Temp val, Temp dst = Temp(0, s2))
 354 {
 355    Builder bld(ctx->program, ctx->block);
 356    if (!dst.id())
 357       dst = bld.tmp(bld.lm);
 358
 359    assert(val.regClass() == s1);
 360    assert(dst.regClass() == bld.lm);
 361
 362    return bld.sop2(Builder::s_cselect, Definition(dst), Operand((uint32_t) -1), Operand(0u), bld.scc(val));
 363 }
 364
 365 Temp bool_to_scalar_condition(isel_context *ctx, Temp val, Temp dst = Temp(0, s1))
 366 {
 367    Builder bld(ctx->program, ctx->block);
 368    if (!dst.id())
 369       dst = bld.tmp(s1);
 370
 371    assert(val.regClass() == bld.lm);
 372    assert(dst.regClass() == s1);
 373
 374    /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
 375    Temp tmp = bld.tmp(s1);
 376    bld.sop2(Builder::s_and, bld.def(bld.lm), bld.scc(Definition(tmp)), val, Operand(exec, bld.lm));
 377    return emit_wqm(ctx, tmp, dst);
 378 }
 379
 380 Temp get_alu_src(struct isel_context *ctx, nir_alu_src src, unsigned size=1)
 381 {
 382    if (src.src.ssa->num_components == 1 && src.swizzle[0] == 0 && size == 1)
 383       return get_ssa_temp(ctx, src.src.ssa);
 384
 385    if (src.src.ssa->num_components == size) {
 386       bool identity_swizzle = true;
 387       for (unsigned i = 0; identity_swizzle && i < size; i++) {
 388          if (src.swizzle[i] != i)
 389             identity_swizzle = false;
 390       }
 391       if (identity_swizzle)
 392          return get_ssa_temp(ctx, src.src.ssa);
 393    }
 394
 395    Temp vec = get_ssa_temp(ctx, src.src.ssa);
 396    unsigned elem_size = vec.size() / src.src.ssa->num_components;
 397    assert(elem_size > 0); /* TODO: 8 and 16-bit vectors not supported */
 398    assert(vec.size() % elem_size == 0);
 399
 400    RegClass elem_rc = RegClass(vec.type(), elem_size);
 401    if (size == 1) {
 402       return emit_extract_vector(ctx, vec, src.swizzle[0], elem_rc);
 403    } else {
 404       assert(size <= 4);
 405       std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 406       aco_ptr<Pseudo_instruction> vec_instr{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, size, 1)};
 407       for (unsigned i = 0; i < size; ++i) {
 408          elems[i] = emit_extract_vector(ctx, vec, src.swizzle[i], elem_rc);
 409          vec_instr->operands[i] = Operand{elems[i]};
 410       }
 411       Temp dst{ctx->program->allocateId(), RegClass(vec.type(), elem_size * size)};
 412       vec_instr->definitions[0] = Definition(dst);
 413       ctx->block->instructions.emplace_back(std::move(vec_instr));
 414       ctx->allocated_vec.emplace(dst.id(), elems);
 415       return dst;
 416    }
 417 }
 418
 419 Temp convert_pointer_to_64_bit(isel_context *ctx, Temp ptr)
 420 {
 421    if (ptr.size() == 2)
 422       return ptr;
 423    Builder bld(ctx->program, ctx->block);
 424    if (ptr.type() == RegType::vgpr)
 425       ptr = bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), ptr);
 426    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s2),
 427                      ptr, Operand((unsigned)ctx->options->address32_hi));
 428 }
 429
 430 void emit_sop2_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst, bool writes_scc)
 431 {
 432    aco_ptr<SOP2_instruction> sop2{create_instruction<SOP2_instruction>(op, Format::SOP2, 2, writes_scc ? 2 : 1)};
 433    sop2->operands[0] = Operand(get_alu_src(ctx, instr->src[0]));
 434    sop2->operands[1] = Operand(get_alu_src(ctx, instr->src[1]));
 435    sop2->definitions[0] = Definition(dst);
 436    if (writes_scc)
 437       sop2->definitions[1] = Definition(ctx->program->allocateId(), scc, s1);
 438    ctx->block->instructions.emplace_back(std::move(sop2));
 439 }
 440
 441 void emit_vop2_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst,
 442                            bool commutative, bool swap_srcs=false, bool flush_denorms = false)
 443 {
 444    Builder bld(ctx->program, ctx->block);
 445    Temp src0 = get_alu_src(ctx, instr->src[swap_srcs ? 1 : 0]);
 446    Temp src1 = get_alu_src(ctx, instr->src[swap_srcs ? 0 : 1]);
 447    if (src1.type() == RegType::sgpr) {
 448       if (commutative && src0.type() == RegType::vgpr) {
 449          Temp t = src0;
 450          src0 = src1;
 451          src1 = t;
 452       } else if (src0.type() == RegType::vgpr &&
 453                  op != aco_opcode::v_madmk_f32 &&
 454                  op != aco_opcode::v_madak_f32 &&
 455                  op != aco_opcode::v_madmk_f16 &&
 456                  op != aco_opcode::v_madak_f16) {
 457          /* If the instruction is not commutative, we emit a VOP3A instruction */
 458          bld.vop2_e64(op, Definition(dst), src0, src1);
 459          return;
 460       } else {
 461          src1 = bld.copy(bld.def(RegType::vgpr, src1.size()), src1); //TODO: as_vgpr
 462       }
 463    }
 464
 465    if (flush_denorms && ctx->program->chip_class < GFX9) {
 466       assert(dst.size() == 1);
 467       Temp tmp = bld.vop2(op, bld.def(v1), src0, src1);
 468       bld.vop2(aco_opcode::v_mul_f32, Definition(dst), Operand(0x3f800000u), tmp);
 469    } else {
 470       bld.vop2(op, Definition(dst), src0, src1);
 471    }
 472 }
 473
 474 void emit_vop3a_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst,
 475                             bool flush_denorms = false)
 476 {
 477    Temp src0 = get_alu_src(ctx, instr->src[0]);
 478    Temp src1 = get_alu_src(ctx, instr->src[1]);
 479    Temp src2 = get_alu_src(ctx, instr->src[2]);
 480
 481    /* ensure that the instruction has at most 1 sgpr operand
 482     * The optimizer will inline constants for us */
 483    if (src0.type() == RegType::sgpr && src1.type() == RegType::sgpr)
 484       src0 = as_vgpr(ctx, src0);
 485    if (src1.type() == RegType::sgpr && src2.type() == RegType::sgpr)
 486       src1 = as_vgpr(ctx, src1);
 487    if (src2.type() == RegType::sgpr && src0.type() == RegType::sgpr)
 488       src2 = as_vgpr(ctx, src2);
 489
 490    Builder bld(ctx->program, ctx->block);
 491    if (flush_denorms && ctx->program->chip_class < GFX9) {
 492       assert(dst.size() == 1);
 493       Temp tmp = bld.vop3(op, Definition(dst), src0, src1, src2);
 494       bld.vop2(aco_opcode::v_mul_f32, Definition(dst), Operand(0x3f800000u), tmp);
 495    } else {
 496       bld.vop3(op, Definition(dst), src0, src1, src2);
 497    }
 498 }
 499
 500 void emit_vop1_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 501 {
 502    Builder bld(ctx->program, ctx->block);
 503    bld.vop1(op, Definition(dst), get_alu_src(ctx, instr->src[0]));
 504 }
 505
 506 void emit_vopc_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 507 {
 508    Temp src0 = get_alu_src(ctx, instr->src[0]);
 509    Temp src1 = get_alu_src(ctx, instr->src[1]);
 510    assert(src0.size() == src1.size());
 511
 512    aco_ptr<Instruction> vopc;
 513    if (src1.type() == RegType::sgpr) {
 514       if (src0.type() == RegType::vgpr) {
 515          /* to swap the operands, we might also have to change the opcode */
 516          switch (op) {
 517             case aco_opcode::v_cmp_lt_f32:
 518                op = aco_opcode::v_cmp_gt_f32;
 519                break;
 520             case aco_opcode::v_cmp_ge_f32:
 521                op = aco_opcode::v_cmp_le_f32;
 522                break;
 523             case aco_opcode::v_cmp_lt_i32:
 524                op = aco_opcode::v_cmp_gt_i32;
 525                break;
 526             case aco_opcode::v_cmp_ge_i32:
 527                op = aco_opcode::v_cmp_le_i32;
 528                break;
 529             case aco_opcode::v_cmp_lt_u32:
 530                op = aco_opcode::v_cmp_gt_u32;
 531                break;
 532             case aco_opcode::v_cmp_ge_u32:
 533                op = aco_opcode::v_cmp_le_u32;
 534                break;
 535             case aco_opcode::v_cmp_lt_f64:
 536                op = aco_opcode::v_cmp_gt_f64;
 537                break;
 538             case aco_opcode::v_cmp_ge_f64:
 539                op = aco_opcode::v_cmp_le_f64;
 540                break;
 541             case aco_opcode::v_cmp_lt_i64:
 542                op = aco_opcode::v_cmp_gt_i64;
 543                break;
 544             case aco_opcode::v_cmp_ge_i64:
 545                op = aco_opcode::v_cmp_le_i64;
 546                break;
 547             case aco_opcode::v_cmp_lt_u64:
 548                op = aco_opcode::v_cmp_gt_u64;
 549                break;
 550             case aco_opcode::v_cmp_ge_u64:
 551                op = aco_opcode::v_cmp_le_u64;
 552                break;
 553             default: /* eq and ne are commutative */
 554                break;
 555          }
 556          Temp t = src0;
 557          src0 = src1;
 558          src1 = t;
 559       } else {
 560          src1 = as_vgpr(ctx, src1);
 561       }
 562    }
 563
 564    Builder bld(ctx->program, ctx->block);
 565    bld.vopc(op, bld.hint_vcc(Definition(dst)), src0, src1);
 566 }
 567
 568 void emit_sopc_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 569 {
 570    Temp src0 = get_alu_src(ctx, instr->src[0]);
 571    Temp src1 = get_alu_src(ctx, instr->src[1]);
 572    Builder bld(ctx->program, ctx->block);
 573
 574    assert(dst.regClass() == bld.lm);
 575    assert(src0.type() == RegType::sgpr);
 576    assert(src1.type() == RegType::sgpr);
 577    assert(src0.regClass() == src1.regClass());
 578
 579    /* Emit the SALU comparison instruction */
 580    Temp cmp = bld.sopc(op, bld.scc(bld.def(s1)), src0, src1);
 581    /* Turn the result into a per-lane bool */
 582    bool_to_vector_condition(ctx, cmp, dst);
 583 }
 584
 585 void emit_comparison(isel_context *ctx, nir_alu_instr *instr, Temp dst,
 586                      aco_opcode v32_op, aco_opcode v64_op, aco_opcode s32_op = aco_opcode::num_opcodes, aco_opcode s64_op = aco_opcode::num_opcodes)
 587 {
 588    aco_opcode s_op = instr->src[0].src.ssa->bit_size == 64 ? s64_op : s32_op;
 589    aco_opcode v_op = instr->src[0].src.ssa->bit_size == 64 ? v64_op : v32_op;
 590    bool divergent_vals = ctx->divergent_vals[instr->dest.dest.ssa.index];
 591    bool use_valu = s_op == aco_opcode::num_opcodes ||
 592                    divergent_vals ||
 593                    ctx->allocated[instr->src[0].src.ssa->index].type() == RegType::vgpr ||
 594                    ctx->allocated[instr->src[1].src.ssa->index].type() == RegType::vgpr;
 595    aco_opcode op = use_valu ? v_op : s_op;
 596    assert(op != aco_opcode::num_opcodes);
 597    assert(dst.regClass() == ctx->program->lane_mask);
 598
 599    if (use_valu)
 600       emit_vopc_instruction(ctx, instr, op, dst);
 601    else
 602       emit_sopc_instruction(ctx, instr, op, dst);
 603 }
 604
 605 void emit_boolean_logic(isel_context *ctx, nir_alu_instr *instr, Builder::WaveSpecificOpcode op, Temp dst)
 606 {
 607    Builder bld(ctx->program, ctx->block);
 608    Temp src0 = get_alu_src(ctx, instr->src[0]);
 609    Temp src1 = get_alu_src(ctx, instr->src[1]);
 610
 611    assert(dst.regClass() == bld.lm);
 612    assert(src0.regClass() == bld.lm);
 613    assert(src1.regClass() == bld.lm);
 614
 615    bld.sop2(op, Definition(dst), bld.def(s1, scc), src0, src1);
 616 }
 617
 618 void emit_bcsel(isel_context *ctx, nir_alu_instr *instr, Temp dst)
 619 {
 620    Builder bld(ctx->program, ctx->block);
 621    Temp cond = get_alu_src(ctx, instr->src[0]);
 622    Temp then = get_alu_src(ctx, instr->src[1]);
 623    Temp els = get_alu_src(ctx, instr->src[2]);
 624
 625    assert(cond.regClass() == bld.lm);
 626
 627    if (dst.type() == RegType::vgpr) {
 628       aco_ptr<Instruction> bcsel;
 629       if (dst.size() == 1) {
 630          then = as_vgpr(ctx, then);
 631          els = as_vgpr(ctx, els);
 632
 633          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), els, then, cond);
 634       } else if (dst.size() == 2) {
 635          Temp then_lo = bld.tmp(v1), then_hi = bld.tmp(v1);
 636          bld.pseudo(aco_opcode::p_split_vector, Definition(then_lo), Definition(then_hi), then);
 637          Temp else_lo = bld.tmp(v1), else_hi = bld.tmp(v1);
 638          bld.pseudo(aco_opcode::p_split_vector, Definition(else_lo), Definition(else_hi), els);
 639
 640          Temp dst0 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_lo, then_lo, cond);
 641          Temp dst1 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_hi, then_hi, cond);
 642
 643          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
 644       } else {
 645          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 646          nir_print_instr(&instr->instr, stderr);
 647          fprintf(stderr, "\n");
 648       }
 649       return;
 650    }
 651
 652    if (instr->dest.dest.ssa.bit_size == 1) {
 653       assert(dst.regClass() == bld.lm);
 654       assert(then.regClass() == bld.lm);
 655       assert(els.regClass() == bld.lm);
 656    }
 657
 658    if (!ctx->divergent_vals[instr->src[0].src.ssa->index]) { /* uniform condition and values in sgpr */
 659       if (dst.regClass() == s1 || dst.regClass() == s2) {
 660          assert((then.regClass() == s1 || then.regClass() == s2) && els.regClass() == then.regClass());
 661          assert(dst.size() == then.size());
 662          aco_opcode op = dst.regClass() == s1 ? aco_opcode::s_cselect_b32 : aco_opcode::s_cselect_b64;
 663          bld.sop2(op, Definition(dst), then, els, bld.scc(bool_to_scalar_condition(ctx, cond)));
 664       } else {
 665          fprintf(stderr, "Unimplemented uniform bcsel bit size: ");
 666          nir_print_instr(&instr->instr, stderr);
 667          fprintf(stderr, "\n");
 668       }
 669       return;
 670    }
 671
 672    /* divergent boolean bcsel
 673     * this implements bcsel on bools: dst = s0 ? s1 : s2
 674     * are going to be: dst = (s0 & s1) | (~s0 & s2) */
 675    assert(instr->dest.dest.ssa.bit_size == 1);
 676
 677    if (cond.id() != then.id())
 678       then = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), cond, then);
 679
 680    if (cond.id() == els.id())
 681       bld.sop1(Builder::s_mov, Definition(dst), then);
 682    else
 683       bld.sop2(Builder::s_or, Definition(dst), bld.def(s1, scc), then,
 684                bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), els, cond));
 685 }
 686
 687 void emit_scaled_op(isel_context *ctx, Builder& bld, Definition dst, Temp val,
 688                     aco_opcode op, uint32_t undo)
 689 {
 690    /* multiply by 16777216 to handle denormals */
 691    Temp is_denormal = bld.vopc(aco_opcode::v_cmp_class_f32, bld.hint_vcc(bld.def(bld.lm)),
 692                                as_vgpr(ctx, val), bld.copy(bld.def(v1), Operand((1u << 7) | (1u << 4))));
 693    Temp scaled = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x4b800000u), val);
 694    scaled = bld.vop1(op, bld.def(v1), scaled);
 695    scaled = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(undo), scaled);
 696
 697    Temp not_scaled = bld.vop1(op, bld.def(v1), val);
 698
 699    bld.vop2(aco_opcode::v_cndmask_b32, dst, not_scaled, scaled, is_denormal);
 700 }
 701
 702 void emit_rcp(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 703 {
 704    if (ctx->block->fp_mode.denorm32 == 0) {
 705       bld.vop1(aco_opcode::v_rcp_f32, dst, val);
 706       return;
 707    }
 708
 709    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_rcp_f32, 0x4b800000u);
 710 }
 711
 712 void emit_rsq(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 713 {
 714    if (ctx->block->fp_mode.denorm32 == 0) {
 715       bld.vop1(aco_opcode::v_rsq_f32, dst, val);
 716       return;
 717    }
 718
 719    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_rsq_f32, 0x45800000u);
 720 }
 721
 722 void emit_sqrt(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 723 {
 724    if (ctx->block->fp_mode.denorm32 == 0) {
 725       bld.vop1(aco_opcode::v_sqrt_f32, dst, val);
 726       return;
 727    }
 728
 729    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_sqrt_f32, 0x39800000u);
 730 }
 731
 732 void emit_log2(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 733 {
 734    if (ctx->block->fp_mode.denorm32 == 0) {
 735       bld.vop1(aco_opcode::v_log_f32, dst, val);
 736       return;
 737    }
 738
 739    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_log_f32, 0xc1c00000u);
 740 }
 741
 742 Temp emit_trunc_f64(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 743 {
 744    if (ctx->options->chip_class >= GFX7)
 745       return bld.vop1(aco_opcode::v_trunc_f64, Definition(dst), val);
 746
 747    /* GFX6 doesn't support V_TRUNC_F64, lower it. */
 748    /* TODO: create more efficient code! */
 749    if (val.type() == RegType::sgpr)
 750       val = as_vgpr(ctx, val);
 751
 752    /* Split the input value. */
 753    Temp val_lo = bld.tmp(v1), val_hi = bld.tmp(v1);
 754    bld.pseudo(aco_opcode::p_split_vector, Definition(val_lo), Definition(val_hi), val);
 755
 756    /* Extract the exponent and compute the unbiased value. */
 757    Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f64, bld.def(v1), val);
 758
 759    /* Extract the fractional part. */
 760    Temp fract_mask = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(-1u), Operand(0x000fffffu));
 761    fract_mask = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), fract_mask, exponent);
 762
 763    Temp fract_mask_lo = bld.tmp(v1), fract_mask_hi = bld.tmp(v1);
 764    bld.pseudo(aco_opcode::p_split_vector, Definition(fract_mask_lo), Definition(fract_mask_hi), fract_mask);
 765
 766    Temp fract_lo = bld.tmp(v1), fract_hi = bld.tmp(v1);
 767    Temp tmp = bld.vop1(aco_opcode::v_not_b32, bld.def(v1), fract_mask_lo);
 768    fract_lo = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), val_lo, tmp);
 769    tmp = bld.vop1(aco_opcode::v_not_b32, bld.def(v1), fract_mask_hi);
 770    fract_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), val_hi, tmp);
 771
 772    /* Get the sign bit. */
 773    Temp sign = bld.vop2(aco_opcode::v_ashr_i32, bld.def(v1), Operand(31u), val_hi);
 774
 775    /* Decide the operation to apply depending on the unbiased exponent. */
 776    Temp exp_lt0 = bld.vopc_e64(aco_opcode::v_cmp_lt_i32, bld.hint_vcc(bld.def(bld.lm)), exponent, Operand(0u));
 777    Temp dst_lo = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), fract_lo, bld.copy(bld.def(v1), Operand(0u)), exp_lt0);
 778    Temp dst_hi = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), fract_hi, sign, exp_lt0);
 779    Temp exp_gt51 = bld.vopc_e64(aco_opcode::v_cmp_gt_i32, bld.def(s2), exponent, Operand(51u));
 780    dst_lo = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), dst_lo, val_lo, exp_gt51);
 781    dst_hi = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), dst_hi, val_hi, exp_gt51);
 782
 783    return bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst_lo, dst_hi);
 784 }
 785
 786 Temp emit_floor_f64(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 787 {
 788    if (ctx->options->chip_class >= GFX7)
 789       return bld.vop1(aco_opcode::v_floor_f64, Definition(dst), val);
 790
 791    /* GFX6 doesn't support V_FLOOR_F64, lower it. */
 792    Temp src0 = as_vgpr(ctx, val);
 793
 794    Temp mask = bld.copy(bld.def(s1), Operand(3u)); /* isnan */
 795    Temp min_val = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(-1u), Operand(0x3fefffffu));
 796
 797    Temp isnan = bld.vopc_e64(aco_opcode::v_cmp_class_f64, bld.hint_vcc(bld.def(bld.lm)), src0, mask);
 798    Temp fract = bld.vop1(aco_opcode::v_fract_f64, bld.def(v2), src0);
 799    Temp min = bld.vop3(aco_opcode::v_min_f64, bld.def(v2), fract, min_val);
 800
 801    Temp then_lo = bld.tmp(v1), then_hi = bld.tmp(v1);
 802    bld.pseudo(aco_opcode::p_split_vector, Definition(then_lo), Definition(then_hi), src0);
 803    Temp else_lo = bld.tmp(v1), else_hi = bld.tmp(v1);
 804    bld.pseudo(aco_opcode::p_split_vector, Definition(else_lo), Definition(else_hi), min);
 805
 806    Temp dst0 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_lo, then_lo, isnan);
 807    Temp dst1 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_hi, then_hi, isnan);
 808
 809    Temp v = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), dst0, dst1);
 810
 811    Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst), src0, v);
 812    static_cast<VOP3A_instruction*>(add)->neg[1] = true;
 813
 814    return add->definitions[0].getTemp();
 815 }
 816
 817 void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
 818 {
 819    if (!instr->dest.dest.is_ssa) {
 820       fprintf(stderr, "nir alu dst not in ssa: ");
 821       nir_print_instr(&instr->instr, stderr);
 822       fprintf(stderr, "\n");
 823       abort();
 824    }
 825    Builder bld(ctx->program, ctx->block);
 826    Temp dst = get_ssa_temp(ctx, &instr->dest.dest.ssa);
 827    switch(instr->op) {
 828    case nir_op_vec2:
 829    case nir_op_vec3:
 830    case nir_op_vec4: {
 831       std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 832       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.dest.ssa.num_components, 1)};
 833       for (unsigned i = 0; i < instr->dest.dest.ssa.num_components; ++i) {
 834          elems[i] = get_alu_src(ctx, instr->src[i]);
 835          vec->operands[i] = Operand{elems[i]};
 836       }
 837       vec->definitions[0] = Definition(dst);
 838       ctx->block->instructions.emplace_back(std::move(vec));
 839       ctx->allocated_vec.emplace(dst.id(), elems);
 840       break;
 841    }
 842    case nir_op_mov: {
 843       Temp src = get_alu_src(ctx, instr->src[0]);
 844       aco_ptr<Instruction> mov;
 845       if (dst.type() == RegType::sgpr) {
 846          if (src.type() == RegType::vgpr)
 847             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), src);
 848          else if (src.regClass() == s1)
 849             bld.sop1(aco_opcode::s_mov_b32, Definition(dst), src);
 850          else if (src.regClass() == s2)
 851             bld.sop1(aco_opcode::s_mov_b64, Definition(dst), src);
 852          else
 853             unreachable("wrong src register class for nir_op_imov");
 854       } else if (dst.regClass() == v1) {
 855          bld.vop1(aco_opcode::v_mov_b32, Definition(dst), src);
 856       } else if (dst.regClass() == v2) {
 857          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src);
 858       } else {
 859          nir_print_instr(&instr->instr, stderr);
 860          unreachable("Should have been lowered to scalar.");
 861       }
 862       break;
 863    }
 864    case nir_op_inot: {
 865       Temp src = get_alu_src(ctx, instr->src[0]);
 866       if (instr->dest.dest.ssa.bit_size == 1) {
 867          assert(src.regClass() == bld.lm);
 868          assert(dst.regClass() == bld.lm);
 869          /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
 870          Temp tmp = bld.sop1(Builder::s_not, bld.def(bld.lm), bld.def(s1, scc), src);
 871          bld.sop2(Builder::s_and, Definition(dst), bld.def(s1, scc), tmp, Operand(exec, bld.lm));
 872       } else if (dst.regClass() == v1) {
 873          emit_vop1_instruction(ctx, instr, aco_opcode::v_not_b32, dst);
 874       } else if (dst.type() == RegType::sgpr) {
 875          aco_opcode opcode = dst.size() == 1 ? aco_opcode::s_not_b32 : aco_opcode::s_not_b64;
 876          bld.sop1(opcode, Definition(dst), bld.def(s1, scc), src);
 877       } else {
 878          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 879          nir_print_instr(&instr->instr, stderr);
 880          fprintf(stderr, "\n");
 881       }
 882       break;
 883    }
 884    case nir_op_ineg: {
 885       Temp src = get_alu_src(ctx, instr->src[0]);
 886       if (dst.regClass() == v1) {
 887          bld.vsub32(Definition(dst), Operand(0u), Operand(src));
 888       } else if (dst.regClass() == s1) {
 889          bld.sop2(aco_opcode::s_mul_i32, Definition(dst), Operand((uint32_t) -1), src);
 890       } else if (dst.size() == 2) {
 891          Temp src0 = bld.tmp(dst.type(), 1);
 892          Temp src1 = bld.tmp(dst.type(), 1);
 893          bld.pseudo(aco_opcode::p_split_vector, Definition(src0), Definition(src1), src);
 894
 895          if (dst.regClass() == s2) {
 896             Temp carry = bld.tmp(s1);
 897             Temp dst0 = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(carry)), Operand(0u), src0);
 898             Temp dst1 = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), src1, carry);
 899             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
 900          } else {
 901             Temp lower = bld.tmp(v1);
 902             Temp borrow = bld.vsub32(Definition(lower), Operand(0u), src0, true).def(1).getTemp();
 903             Temp upper = bld.vsub32(bld.def(v1), Operand(0u), src1, false, borrow);
 904             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
 905          }
 906       } else {
 907          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 908          nir_print_instr(&instr->instr, stderr);
 909          fprintf(stderr, "\n");
 910       }
 911       break;
 912    }
 913    case nir_op_iabs: {
 914       if (dst.regClass() == s1) {
 915          bld.sop1(aco_opcode::s_abs_i32, Definition(dst), bld.def(s1, scc), get_alu_src(ctx, instr->src[0]));
 916       } else if (dst.regClass() == v1) {
 917          Temp src = get_alu_src(ctx, instr->src[0]);
 918          bld.vop2(aco_opcode::v_max_i32, Definition(dst), src, bld.vsub32(bld.def(v1), Operand(0u), src));
 919       } else {
 920          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 921          nir_print_instr(&instr->instr, stderr);
 922          fprintf(stderr, "\n");
 923       }
 924       break;
 925    }
 926    case nir_op_isign: {
 927       Temp src = get_alu_src(ctx, instr->src[0]);
 928       if (dst.regClass() == s1) {
 929          Temp tmp = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
 930          Temp gtz = bld.sopc(aco_opcode::s_cmp_gt_i32, bld.def(s1, scc), src, Operand(0u));
 931          bld.sop2(aco_opcode::s_add_i32, Definition(dst), bld.def(s1, scc), gtz, tmp);
 932       } else if (dst.regClass() == s2) {
 933          Temp neg = bld.sop2(aco_opcode::s_ashr_i64, bld.def(s2), bld.def(s1, scc), src, Operand(63u));
 934          Temp neqz;
 935          if (ctx->program->chip_class >= GFX8)
 936             neqz = bld.sopc(aco_opcode::s_cmp_lg_u64, bld.def(s1, scc), src, Operand(0u));
 937          else
 938             neqz = bld.sop2(aco_opcode::s_or_b64, bld.def(s2), bld.def(s1, scc), src, Operand(0u)).def(1).getTemp();
 939          /* SCC gets zero-extended to 64 bit */
 940          bld.sop2(aco_opcode::s_or_b64, Definition(dst), bld.def(s1, scc), neg, bld.scc(neqz));
 941       } else if (dst.regClass() == v1) {
 942          Temp tmp = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
 943          Temp gtz = bld.vopc(aco_opcode::v_cmp_ge_i32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
 944          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(1u), tmp, gtz);
 945       } else if (dst.regClass() == v2) {
 946          Temp upper = emit_extract_vector(ctx, src, 1, v1);
 947          Temp neg = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), upper);
 948          Temp gtz = bld.vopc(aco_opcode::v_cmp_ge_i64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
 949          Temp lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(1u), neg, gtz);
 950          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), neg, gtz);
 951          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
 952       } else {
 953          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 954          nir_print_instr(&instr->instr, stderr);
 955          fprintf(stderr, "\n");
 956       }
 957       break;
 958    }
 959    case nir_op_imax: {
 960       if (dst.regClass() == v1) {
 961          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_i32, dst, true);
 962       } else if (dst.regClass() == s1) {
 963          emit_sop2_instruction(ctx, instr, aco_opcode::s_max_i32, dst, true);
 964       } else {
 965          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 966          nir_print_instr(&instr->instr, stderr);
 967          fprintf(stderr, "\n");
 968       }
 969       break;
 970    }
 971    case nir_op_umax: {
 972       if (dst.regClass() == v1) {
 973          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_u32, dst, true);
 974       } else if (dst.regClass() == s1) {
 975          emit_sop2_instruction(ctx, instr, aco_opcode::s_max_u32, dst, true);
 976       } else {
 977          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 978          nir_print_instr(&instr->instr, stderr);
 979          fprintf(stderr, "\n");
 980       }
 981       break;
 982    }
 983    case nir_op_imin: {
 984       if (dst.regClass() == v1) {
 985          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_i32, dst, true);
 986       } else if (dst.regClass() == s1) {
 987          emit_sop2_instruction(ctx, instr, aco_opcode::s_min_i32, dst, true);
 988       } else {
 989          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 990          nir_print_instr(&instr->instr, stderr);
 991          fprintf(stderr, "\n");
 992       }
 993       break;
 994    }
 995    case nir_op_umin: {
 996       if (dst.regClass() == v1) {
 997          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_u32, dst, true);
 998       } else if (dst.regClass() == s1) {
 999          emit_sop2_instruction(ctx, instr, aco_opcode::s_min_u32, dst, true);
1000       } else {
1001          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1002          nir_print_instr(&instr->instr, stderr);
1003          fprintf(stderr, "\n");
1004       }
1005       break;
1006    }
1007    case nir_op_ior: {
1008       if (instr->dest.dest.ssa.bit_size == 1) {
1009          emit_boolean_logic(ctx, instr, Builder::s_or, dst);
1010       } else if (dst.regClass() == v1) {
1011          emit_vop2_instruction(ctx, instr, aco_opcode::v_or_b32, dst, true);
1012       } else if (dst.regClass() == s1) {
1013          emit_sop2_instruction(ctx, instr, aco_opcode::s_or_b32, dst, true);
1014       } else if (dst.regClass() == s2) {
1015          emit_sop2_instruction(ctx, instr, aco_opcode::s_or_b64, dst, true);
1016       } else {
1017          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1018          nir_print_instr(&instr->instr, stderr);
1019          fprintf(stderr, "\n");
1020       }
1021       break;
1022    }
1023    case nir_op_iand: {
1024       if (instr->dest.dest.ssa.bit_size == 1) {
1025          emit_boolean_logic(ctx, instr, Builder::s_and, dst);
1026       } else if (dst.regClass() == v1) {
1027          emit_vop2_instruction(ctx, instr, aco_opcode::v_and_b32, dst, true);
1028       } else if (dst.regClass() == s1) {
1029          emit_sop2_instruction(ctx, instr, aco_opcode::s_and_b32, dst, true);
1030       } else if (dst.regClass() == s2) {
1031          emit_sop2_instruction(ctx, instr, aco_opcode::s_and_b64, dst, true);
1032       } else {
1033          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1034          nir_print_instr(&instr->instr, stderr);
1035          fprintf(stderr, "\n");
1036       }
1037       break;
1038    }
1039    case nir_op_ixor: {
1040       if (instr->dest.dest.ssa.bit_size == 1) {
1041          emit_boolean_logic(ctx, instr, Builder::s_xor, dst);
1042       } else if (dst.regClass() == v1) {
1043          emit_vop2_instruction(ctx, instr, aco_opcode::v_xor_b32, dst, true);
1044       } else if (dst.regClass() == s1) {
1045          emit_sop2_instruction(ctx, instr, aco_opcode::s_xor_b32, dst, true);
1046       } else if (dst.regClass() == s2) {
1047          emit_sop2_instruction(ctx, instr, aco_opcode::s_xor_b64, dst, true);
1048       } else {
1049          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1050          nir_print_instr(&instr->instr, stderr);
1051          fprintf(stderr, "\n");
1052       }
1053       break;
1054    }
1055    case nir_op_ushr: {
1056       if (dst.regClass() == v1) {
1057          emit_vop2_instruction(ctx, instr, aco_opcode::v_lshrrev_b32, dst, false, true);
1058       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
1059          bld.vop3(aco_opcode::v_lshrrev_b64, Definition(dst),
1060                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
1061       } else if (dst.regClass() == v2) {
1062          bld.vop3(aco_opcode::v_lshr_b64, Definition(dst),
1063                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1064       } else if (dst.regClass() == s2) {
1065          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshr_b64, dst, true);
1066       } else if (dst.regClass() == s1) {
1067          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshr_b32, dst, true);
1068       } else {
1069          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1070          nir_print_instr(&instr->instr, stderr);
1071          fprintf(stderr, "\n");
1072       }
1073       break;
1074    }
1075    case nir_op_ishl: {
1076       if (dst.regClass() == v1) {
1077          emit_vop2_instruction(ctx, instr, aco_opcode::v_lshlrev_b32, dst, false, true);
1078       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
1079          bld.vop3(aco_opcode::v_lshlrev_b64, Definition(dst),
1080                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
1081       } else if (dst.regClass() == v2) {
1082          bld.vop3(aco_opcode::v_lshl_b64, Definition(dst),
1083                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1084       } else if (dst.regClass() == s1) {
1085          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshl_b32, dst, true);
1086       } else if (dst.regClass() == s2) {
1087          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshl_b64, dst, true);
1088       } else {
1089          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1090          nir_print_instr(&instr->instr, stderr);
1091          fprintf(stderr, "\n");
1092       }
1093       break;
1094    }
1095    case nir_op_ishr: {
1096       if (dst.regClass() == v1) {
1097          emit_vop2_instruction(ctx, instr, aco_opcode::v_ashrrev_i32, dst, false, true);
1098       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
1099          bld.vop3(aco_opcode::v_ashrrev_i64, Definition(dst),
1100                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
1101       } else if (dst.regClass() == v2) {
1102          bld.vop3(aco_opcode::v_ashr_i64, Definition(dst),
1103                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1104       } else if (dst.regClass() == s1) {
1105          emit_sop2_instruction(ctx, instr, aco_opcode::s_ashr_i32, dst, true);
1106       } else if (dst.regClass() == s2) {
1107          emit_sop2_instruction(ctx, instr, aco_opcode::s_ashr_i64, dst, true);
1108       } else {
1109          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1110          nir_print_instr(&instr->instr, stderr);
1111          fprintf(stderr, "\n");
1112       }
1113       break;
1114    }
1115    case nir_op_find_lsb: {
1116       Temp src = get_alu_src(ctx, instr->src[0]);
1117       if (src.regClass() == s1) {
1118          bld.sop1(aco_opcode::s_ff1_i32_b32, Definition(dst), src);
1119       } else if (src.regClass() == v1) {
1120          emit_vop1_instruction(ctx, instr, aco_opcode::v_ffbl_b32, dst);
1121       } else if (src.regClass() == s2) {
1122          bld.sop1(aco_opcode::s_ff1_i32_b64, Definition(dst), src);
1123       } else {
1124          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1125          nir_print_instr(&instr->instr, stderr);
1126          fprintf(stderr, "\n");
1127       }
1128       break;
1129    }
1130    case nir_op_ufind_msb:
1131    case nir_op_ifind_msb: {
1132       Temp src = get_alu_src(ctx, instr->src[0]);
1133       if (src.regClass() == s1 || src.regClass() == s2) {
1134          aco_opcode op = src.regClass() == s2 ?
1135                          (instr->op == nir_op_ufind_msb ? aco_opcode::s_flbit_i32_b64 : aco_opcode::s_flbit_i32_i64) :
1136                          (instr->op == nir_op_ufind_msb ? aco_opcode::s_flbit_i32_b32 : aco_opcode::s_flbit_i32);
1137          Temp msb_rev = bld.sop1(op, bld.def(s1), src);
1138
1139          Builder::Result sub = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc),
1140                                         Operand(src.size() * 32u - 1u), msb_rev);
1141          Temp msb = sub.def(0).getTemp();
1142          Temp carry = sub.def(1).getTemp();
1143
1144          bld.sop2(aco_opcode::s_cselect_b32, Definition(dst), Operand((uint32_t)-1), msb, bld.scc(carry));
1145       } else if (src.regClass() == v1) {
1146          aco_opcode op = instr->op == nir_op_ufind_msb ? aco_opcode::v_ffbh_u32 : aco_opcode::v_ffbh_i32;
1147          Temp msb_rev = bld.tmp(v1);
1148          emit_vop1_instruction(ctx, instr, op, msb_rev);
1149          Temp msb = bld.tmp(v1);
1150          Temp carry = bld.vsub32(Definition(msb), Operand(31u), Operand(msb_rev), true).def(1).getTemp();
1151          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), msb, Operand((uint32_t)-1), carry);
1152       } else {
1153          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1154          nir_print_instr(&instr->instr, stderr);
1155          fprintf(stderr, "\n");
1156       }
1157       break;
1158    }
1159    case nir_op_bitfield_reverse: {
1160       if (dst.regClass() == s1) {
1161          bld.sop1(aco_opcode::s_brev_b32, Definition(dst), get_alu_src(ctx, instr->src[0]));
1162       } else if (dst.regClass() == v1) {
1163          bld.vop1(aco_opcode::v_bfrev_b32, Definition(dst), get_alu_src(ctx, instr->src[0]));
1164       } else {
1165          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1166          nir_print_instr(&instr->instr, stderr);
1167          fprintf(stderr, "\n");
1168       }
1169       break;
1170    }
1171    case nir_op_iadd: {
1172       if (dst.regClass() == s1) {
1173          emit_sop2_instruction(ctx, instr, aco_opcode::s_add_u32, dst, true);
1174          break;
1175       }
1176
1177       Temp src0 = get_alu_src(ctx, instr->src[0]);
1178       Temp src1 = get_alu_src(ctx, instr->src[1]);
1179       if (dst.regClass() == v1) {
1180          bld.vadd32(Definition(dst), Operand(src0), Operand(src1));
1181          break;
1182       }
1183
1184       assert(src0.size() == 2 && src1.size() == 2);
1185       Temp src00 = bld.tmp(src0.type(), 1);
1186       Temp src01 = bld.tmp(dst.type(), 1);
1187       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1188       Temp src10 = bld.tmp(src1.type(), 1);
1189       Temp src11 = bld.tmp(dst.type(), 1);
1190       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1191
1192       if (dst.regClass() == s2) {
1193          Temp carry = bld.tmp(s1);
1194          Temp dst0 = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1195          Temp dst1 = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), src01, src11, bld.scc(carry));
1196          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1197       } else if (dst.regClass() == v2) {
1198          Temp dst0 = bld.tmp(v1);
1199          Temp carry = bld.vadd32(Definition(dst0), src00, src10, true).def(1).getTemp();
1200          Temp dst1 = bld.vadd32(bld.def(v1), src01, src11, false, carry);
1201          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1202       } else {
1203          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1204          nir_print_instr(&instr->instr, stderr);
1205          fprintf(stderr, "\n");
1206       }
1207       break;
1208    }
1209    case nir_op_uadd_sat: {
1210       Temp src0 = get_alu_src(ctx, instr->src[0]);
1211       Temp src1 = get_alu_src(ctx, instr->src[1]);
1212       if (dst.regClass() == s1) {
1213          Temp tmp = bld.tmp(s1), carry = bld.tmp(s1);
1214          bld.sop2(aco_opcode::s_add_u32, Definition(tmp), bld.scc(Definition(carry)),
1215                   src0, src1);
1216          bld.sop2(aco_opcode::s_cselect_b32, Definition(dst), Operand((uint32_t) -1), tmp, bld.scc(carry));
1217       } else if (dst.regClass() == v1) {
1218          if (ctx->options->chip_class >= GFX9) {
1219             aco_ptr<VOP3A_instruction> add{create_instruction<VOP3A_instruction>(aco_opcode::v_add_u32, asVOP3(Format::VOP2), 2, 1)};
1220             add->operands[0] = Operand(src0);
1221             add->operands[1] = Operand(src1);
1222             add->definitions[0] = Definition(dst);
1223             add->clamp = 1;
1224             ctx->block->instructions.emplace_back(std::move(add));
1225          } else {
1226             if (src1.regClass() != v1)
1227                std::swap(src0, src1);
1228             assert(src1.regClass() == v1);
1229             Temp tmp = bld.tmp(v1);
1230             Temp carry = bld.vadd32(Definition(tmp), src0, src1, true).def(1).getTemp();
1231             bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), tmp, Operand((uint32_t) -1), carry);
1232          }
1233       } else {
1234          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1235          nir_print_instr(&instr->instr, stderr);
1236          fprintf(stderr, "\n");
1237       }
1238       break;
1239    }
1240    case nir_op_uadd_carry: {
1241       Temp src0 = get_alu_src(ctx, instr->src[0]);
1242       Temp src1 = get_alu_src(ctx, instr->src[1]);
1243       if (dst.regClass() == s1) {
1244          bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(dst)), src0, src1);
1245          break;
1246       }
1247       if (dst.regClass() == v1) {
1248          Temp carry = bld.vadd32(bld.def(v1), src0, src1, true).def(1).getTemp();
1249          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), carry);
1250          break;
1251       }
1252
1253       Temp src00 = bld.tmp(src0.type(), 1);
1254       Temp src01 = bld.tmp(dst.type(), 1);
1255       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1256       Temp src10 = bld.tmp(src1.type(), 1);
1257       Temp src11 = bld.tmp(dst.type(), 1);
1258       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1259       if (dst.regClass() == s2) {
1260          Temp carry = bld.tmp(s1);
1261          bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1262          carry = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.scc(bld.def(s1)), src01, src11, bld.scc(carry)).def(1).getTemp();
1263          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), carry, Operand(0u));
1264       } else if (dst.regClass() == v2) {
1265          Temp carry = bld.vadd32(bld.def(v1), src00, src10, true).def(1).getTemp();
1266          carry = bld.vadd32(bld.def(v1), src01, src11, true, carry).def(1).getTemp();
1267          carry = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand(1u), carry);
1268          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), carry, Operand(0u));
1269       } else {
1270          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1271          nir_print_instr(&instr->instr, stderr);
1272          fprintf(stderr, "\n");
1273       }
1274       break;
1275    }
1276    case nir_op_isub: {
1277       if (dst.regClass() == s1) {
1278          emit_sop2_instruction(ctx, instr, aco_opcode::s_sub_i32, dst, true);
1279          break;
1280       }
1281
1282       Temp src0 = get_alu_src(ctx, instr->src[0]);
1283       Temp src1 = get_alu_src(ctx, instr->src[1]);
1284       if (dst.regClass() == v1) {
1285          bld.vsub32(Definition(dst), src0, src1);
1286          break;
1287       }
1288
1289       Temp src00 = bld.tmp(src0.type(), 1);
1290       Temp src01 = bld.tmp(dst.type(), 1);
1291       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1292       Temp src10 = bld.tmp(src1.type(), 1);
1293       Temp src11 = bld.tmp(dst.type(), 1);
1294       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1295       if (dst.regClass() == s2) {
1296          Temp carry = bld.tmp(s1);
1297          Temp dst0 = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1298          Temp dst1 = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), src01, src11, carry);
1299          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1300       } else if (dst.regClass() == v2) {
1301          Temp lower = bld.tmp(v1);
1302          Temp borrow = bld.vsub32(Definition(lower), src00, src10, true).def(1).getTemp();
1303          Temp upper = bld.vsub32(bld.def(v1), src01, src11, false, borrow);
1304          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1305       } else {
1306          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1307          nir_print_instr(&instr->instr, stderr);
1308          fprintf(stderr, "\n");
1309       }
1310       break;
1311    }
1312    case nir_op_usub_borrow: {
1313       Temp src0 = get_alu_src(ctx, instr->src[0]);
1314       Temp src1 = get_alu_src(ctx, instr->src[1]);
1315       if (dst.regClass() == s1) {
1316          bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(dst)), src0, src1);
1317          break;
1318       } else if (dst.regClass() == v1) {
1319          Temp borrow = bld.vsub32(bld.def(v1), src0, src1, true).def(1).getTemp();
1320          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), borrow);
1321          break;
1322       }
1323
1324       Temp src00 = bld.tmp(src0.type(), 1);
1325       Temp src01 = bld.tmp(dst.type(), 1);
1326       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1327       Temp src10 = bld.tmp(src1.type(), 1);
1328       Temp src11 = bld.tmp(dst.type(), 1);
1329       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1330       if (dst.regClass() == s2) {
1331          Temp borrow = bld.tmp(s1);
1332          bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(borrow)), src00, src10);
1333          borrow = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.scc(bld.def(s1)), src01, src11, bld.scc(borrow)).def(1).getTemp();
1334          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), borrow, Operand(0u));
1335       } else if (dst.regClass() == v2) {
1336          Temp borrow = bld.vsub32(bld.def(v1), src00, src10, true).def(1).getTemp();
1337          borrow = bld.vsub32(bld.def(v1), src01, src11, true, Operand(borrow)).def(1).getTemp();
1338          borrow = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand(1u), borrow);
1339          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), borrow, Operand(0u));
1340       } else {
1341          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1342          nir_print_instr(&instr->instr, stderr);
1343          fprintf(stderr, "\n");
1344       }
1345       break;
1346    }
1347    case nir_op_imul: {
1348       if (dst.regClass() == v1) {
1349          bld.vop3(aco_opcode::v_mul_lo_u32, Definition(dst),
1350                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1351       } else if (dst.regClass() == s1) {
1352          emit_sop2_instruction(ctx, instr, aco_opcode::s_mul_i32, dst, false);
1353       } else {
1354          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1355          nir_print_instr(&instr->instr, stderr);
1356          fprintf(stderr, "\n");
1357       }
1358       break;
1359    }
1360    case nir_op_umul_high: {
1361       if (dst.regClass() == v1) {
1362          bld.vop3(aco_opcode::v_mul_hi_u32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1363       } else if (dst.regClass() == s1 && ctx->options->chip_class >= GFX9) {
1364          bld.sop2(aco_opcode::s_mul_hi_u32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1365       } else if (dst.regClass() == s1) {
1366          Temp tmp = bld.vop3(aco_opcode::v_mul_hi_u32, bld.def(v1), get_alu_src(ctx, instr->src[0]),
1367                              as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1368          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), tmp);
1369       } else {
1370          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1371          nir_print_instr(&instr->instr, stderr);
1372          fprintf(stderr, "\n");
1373       }
1374       break;
1375    }
1376    case nir_op_imul_high: {
1377       if (dst.regClass() == v1) {
1378          bld.vop3(aco_opcode::v_mul_hi_i32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1379       } else if (dst.regClass() == s1 && ctx->options->chip_class >= GFX9) {
1380          bld.sop2(aco_opcode::s_mul_hi_i32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1381       } else if (dst.regClass() == s1) {
1382          Temp tmp = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), get_alu_src(ctx, instr->src[0]),
1383                              as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1384          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), tmp);
1385       } else {
1386          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1387          nir_print_instr(&instr->instr, stderr);
1388          fprintf(stderr, "\n");
1389       }
1390       break;
1391    }
1392    case nir_op_fmul: {
1393       if (dst.size() == 1) {
1394          emit_vop2_instruction(ctx, instr, aco_opcode::v_mul_f32, dst, true);
1395       } else if (dst.size() == 2) {
1396          bld.vop3(aco_opcode::v_mul_f64, Definition(dst), get_alu_src(ctx, instr->src[0]),
1397                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1398       } else {
1399          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1400          nir_print_instr(&instr->instr, stderr);
1401          fprintf(stderr, "\n");
1402       }
1403       break;
1404    }
1405    case nir_op_fadd: {
1406       if (dst.size() == 1) {
1407          emit_vop2_instruction(ctx, instr, aco_opcode::v_add_f32, dst, true);
1408       } else if (dst.size() == 2) {
1409          bld.vop3(aco_opcode::v_add_f64, Definition(dst), get_alu_src(ctx, instr->src[0]),
1410                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1411       } else {
1412          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1413          nir_print_instr(&instr->instr, stderr);
1414          fprintf(stderr, "\n");
1415       }
1416       break;
1417    }
1418    case nir_op_fsub: {
1419       Temp src0 = get_alu_src(ctx, instr->src[0]);
1420       Temp src1 = get_alu_src(ctx, instr->src[1]);
1421       if (dst.size() == 1) {
1422          if (src1.type() == RegType::vgpr || src0.type() != RegType::vgpr)
1423             emit_vop2_instruction(ctx, instr, aco_opcode::v_sub_f32, dst, false);
1424          else
1425             emit_vop2_instruction(ctx, instr, aco_opcode::v_subrev_f32, dst, true);
1426       } else if (dst.size() == 2) {
1427          Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst),
1428                                      get_alu_src(ctx, instr->src[0]),
1429                                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1430          VOP3A_instruction* sub = static_cast<VOP3A_instruction*>(add);
1431          sub->neg[1] = true;
1432       } else {
1433          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1434          nir_print_instr(&instr->instr, stderr);
1435          fprintf(stderr, "\n");
1436       }
1437       break;
1438    }
1439    case nir_op_fmax: {
1440       if (dst.size() == 1) {
1441          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_f32, dst, true, false, ctx->block->fp_mode.must_flush_denorms32);
1442       } else if (dst.size() == 2) {
1443          if (ctx->block->fp_mode.must_flush_denorms16_64 && ctx->program->chip_class < GFX9) {
1444             Temp tmp = bld.vop3(aco_opcode::v_max_f64, bld.def(v2),
1445                                 get_alu_src(ctx, instr->src[0]),
1446                                 as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1447             bld.vop3(aco_opcode::v_mul_f64, Definition(dst), Operand(0x3FF0000000000000lu), tmp);
1448          } else {
1449             bld.vop3(aco_opcode::v_max_f64, Definition(dst),
1450                      get_alu_src(ctx, instr->src[0]),
1451                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1452          }
1453       } else {
1454          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1455          nir_print_instr(&instr->instr, stderr);
1456          fprintf(stderr, "\n");
1457       }
1458       break;
1459    }
1460    case nir_op_fmin: {
1461       if (dst.size() == 1) {
1462          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_f32, dst, true, false, ctx->block->fp_mode.must_flush_denorms32);
1463       } else if (dst.size() == 2) {
1464          if (ctx->block->fp_mode.must_flush_denorms16_64 && ctx->program->chip_class < GFX9) {
1465             Temp tmp = bld.vop3(aco_opcode::v_min_f64, bld.def(v2),
1466                                 get_alu_src(ctx, instr->src[0]),
1467                                 as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1468             bld.vop3(aco_opcode::v_mul_f64, Definition(dst), Operand(0x3FF0000000000000lu), tmp);
1469          } else {
1470             bld.vop3(aco_opcode::v_min_f64, Definition(dst),
1471                      get_alu_src(ctx, instr->src[0]),
1472                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1473          }
1474       } else {
1475          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1476          nir_print_instr(&instr->instr, stderr);
1477          fprintf(stderr, "\n");
1478       }
1479       break;
1480    }
1481    case nir_op_fmax3: {
1482       if (dst.size() == 1) {
1483          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_f32, dst, ctx->block->fp_mode.must_flush_denorms32);
1484       } else {
1485          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1486          nir_print_instr(&instr->instr, stderr);
1487          fprintf(stderr, "\n");
1488       }
1489       break;
1490    }
1491    case nir_op_fmin3: {
1492       if (dst.size() == 1) {
1493          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_f32, dst, ctx->block->fp_mode.must_flush_denorms32);
1494       } else {
1495          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1496          nir_print_instr(&instr->instr, stderr);
1497          fprintf(stderr, "\n");
1498       }
1499       break;
1500    }
1501    case nir_op_fmed3: {
1502       if (dst.size() == 1) {
1503          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_f32, dst, ctx->block->fp_mode.must_flush_denorms32);
1504       } else {
1505          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1506          nir_print_instr(&instr->instr, stderr);
1507          fprintf(stderr, "\n");
1508       }
1509       break;
1510    }
1511    case nir_op_umax3: {
1512       if (dst.size() == 1) {
1513          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_u32, dst);
1514       } else {
1515          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1516          nir_print_instr(&instr->instr, stderr);
1517          fprintf(stderr, "\n");
1518       }
1519       break;
1520    }
1521    case nir_op_umin3: {
1522       if (dst.size() == 1) {
1523          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_u32, dst);
1524       } else {
1525          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1526          nir_print_instr(&instr->instr, stderr);
1527          fprintf(stderr, "\n");
1528       }
1529       break;
1530    }
1531    case nir_op_umed3: {
1532       if (dst.size() == 1) {
1533          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_u32, dst);
1534       } else {
1535          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1536          nir_print_instr(&instr->instr, stderr);
1537          fprintf(stderr, "\n");
1538       }
1539       break;
1540    }
1541    case nir_op_imax3: {
1542       if (dst.size() == 1) {
1543          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_i32, dst);
1544       } else {
1545          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1546          nir_print_instr(&instr->instr, stderr);
1547          fprintf(stderr, "\n");
1548       }
1549       break;
1550    }
1551    case nir_op_imin3: {
1552       if (dst.size() == 1) {
1553          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_i32, dst);
1554       } else {
1555          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1556          nir_print_instr(&instr->instr, stderr);
1557          fprintf(stderr, "\n");
1558       }
1559       break;
1560    }
1561    case nir_op_imed3: {
1562       if (dst.size() == 1) {
1563          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_i32, dst);
1564       } else {
1565          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1566          nir_print_instr(&instr->instr, stderr);
1567          fprintf(stderr, "\n");
1568       }
1569       break;
1570    }
1571    case nir_op_cube_face_coord: {
1572       Temp in = get_alu_src(ctx, instr->src[0], 3);
1573       Temp src[3] = { emit_extract_vector(ctx, in, 0, v1),
1574                       emit_extract_vector(ctx, in, 1, v1),
1575                       emit_extract_vector(ctx, in, 2, v1) };
1576       Temp ma = bld.vop3(aco_opcode::v_cubema_f32, bld.def(v1), src[0], src[1], src[2]);
1577       ma = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), ma);
1578       Temp sc = bld.vop3(aco_opcode::v_cubesc_f32, bld.def(v1), src[0], src[1], src[2]);
1579       Temp tc = bld.vop3(aco_opcode::v_cubetc_f32, bld.def(v1), src[0], src[1], src[2]);
1580       sc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), sc, ma, Operand(0x3f000000u/*0.5*/));
1581       tc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), tc, ma, Operand(0x3f000000u/*0.5*/));
1582       bld.pseudo(aco_opcode::p_create_vector, Definition(dst), sc, tc);
1583       break;
1584    }
1585    case nir_op_cube_face_index: {
1586       Temp in = get_alu_src(ctx, instr->src[0], 3);
1587       Temp src[3] = { emit_extract_vector(ctx, in, 0, v1),
1588                       emit_extract_vector(ctx, in, 1, v1),
1589                       emit_extract_vector(ctx, in, 2, v1) };
1590       bld.vop3(aco_opcode::v_cubeid_f32, Definition(dst), src[0], src[1], src[2]);
1591       break;
1592    }
1593    case nir_op_bcsel: {
1594       emit_bcsel(ctx, instr, dst);
1595       break;
1596    }
1597    case nir_op_frsq: {
1598       if (dst.size() == 1) {
1599          emit_rsq(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1600       } else if (dst.size() == 2) {
1601          emit_vop1_instruction(ctx, instr, aco_opcode::v_rsq_f64, dst);
1602       } else {
1603          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1604          nir_print_instr(&instr->instr, stderr);
1605          fprintf(stderr, "\n");
1606       }
1607       break;
1608    }
1609    case nir_op_fneg: {
1610       Temp src = get_alu_src(ctx, instr->src[0]);
1611       if (dst.size() == 1) {
1612          if (ctx->block->fp_mode.must_flush_denorms32)
1613             src = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x3f800000u), as_vgpr(ctx, src));
1614          bld.vop2(aco_opcode::v_xor_b32, Definition(dst), Operand(0x80000000u), as_vgpr(ctx, src));
1615       } else if (dst.size() == 2) {
1616          if (ctx->block->fp_mode.must_flush_denorms16_64)
1617             src = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), Operand(0x3FF0000000000000lu), as_vgpr(ctx, src));
1618          Temp upper = bld.tmp(v1), lower = bld.tmp(v1);
1619          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1620          upper = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), Operand(0x80000000u), upper);
1621          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1622       } else {
1623          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1624          nir_print_instr(&instr->instr, stderr);
1625          fprintf(stderr, "\n");
1626       }
1627       break;
1628    }
1629    case nir_op_fabs: {
1630       Temp src = get_alu_src(ctx, instr->src[0]);
1631       if (dst.size() == 1) {
1632          if (ctx->block->fp_mode.must_flush_denorms32)
1633             src = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x3f800000u), as_vgpr(ctx, src));
1634          bld.vop2(aco_opcode::v_and_b32, Definition(dst), Operand(0x7FFFFFFFu), as_vgpr(ctx, src));
1635       } else if (dst.size() == 2) {
1636          if (ctx->block->fp_mode.must_flush_denorms16_64)
1637             src = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), Operand(0x3FF0000000000000lu), as_vgpr(ctx, src));
1638          Temp upper = bld.tmp(v1), lower = bld.tmp(v1);
1639          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1640          upper = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7FFFFFFFu), upper);
1641          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1642       } else {
1643          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1644          nir_print_instr(&instr->instr, stderr);
1645          fprintf(stderr, "\n");
1646       }
1647       break;
1648    }
1649    case nir_op_fsat: {
1650       Temp src = get_alu_src(ctx, instr->src[0]);
1651       if (dst.size() == 1) {
1652          bld.vop3(aco_opcode::v_med3_f32, Definition(dst), Operand(0u), Operand(0x3f800000u), src);
1653          /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1654          // TODO: confirm that this holds under any circumstances
1655       } else if (dst.size() == 2) {
1656          Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst), src, Operand(0u));
1657          VOP3A_instruction* vop3 = static_cast<VOP3A_instruction*>(add);
1658          vop3->clamp = true;
1659       } else {
1660          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1661          nir_print_instr(&instr->instr, stderr);
1662          fprintf(stderr, "\n");
1663       }
1664       break;
1665    }
1666    case nir_op_flog2: {
1667       if (dst.size() == 1) {
1668          emit_log2(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1669       } else {
1670          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1671          nir_print_instr(&instr->instr, stderr);
1672          fprintf(stderr, "\n");
1673       }
1674       break;
1675    }
1676    case nir_op_frcp: {
1677       if (dst.size() == 1) {
1678          emit_rcp(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1679       } else if (dst.size() == 2) {
1680          emit_vop1_instruction(ctx, instr, aco_opcode::v_rcp_f64, dst);
1681       } else {
1682          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1683          nir_print_instr(&instr->instr, stderr);
1684          fprintf(stderr, "\n");
1685       }
1686       break;
1687    }
1688    case nir_op_fexp2: {
1689       if (dst.size() == 1) {
1690          emit_vop1_instruction(ctx, instr, aco_opcode::v_exp_f32, dst);
1691       } else {
1692          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1693          nir_print_instr(&instr->instr, stderr);
1694          fprintf(stderr, "\n");
1695       }
1696       break;
1697    }
1698    case nir_op_fsqrt: {
1699       if (dst.size() == 1) {
1700          emit_sqrt(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1701       } else if (dst.size() == 2) {
1702          emit_vop1_instruction(ctx, instr, aco_opcode::v_sqrt_f64, dst);
1703       } else {
1704          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1705          nir_print_instr(&instr->instr, stderr);
1706          fprintf(stderr, "\n");
1707       }
1708       break;
1709    }
1710    case nir_op_ffract: {
1711       if (dst.size() == 1) {
1712          emit_vop1_instruction(ctx, instr, aco_opcode::v_fract_f32, dst);
1713       } else if (dst.size() == 2) {
1714          emit_vop1_instruction(ctx, instr, aco_opcode::v_fract_f64, dst);
1715       } else {
1716          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1717          nir_print_instr(&instr->instr, stderr);
1718          fprintf(stderr, "\n");
1719       }
1720       break;
1721    }
1722    case nir_op_ffloor: {
1723       if (dst.size() == 1) {
1724          emit_vop1_instruction(ctx, instr, aco_opcode::v_floor_f32, dst);
1725       } else if (dst.size() == 2) {
1726          emit_floor_f64(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1727       } else {
1728          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1729          nir_print_instr(&instr->instr, stderr);
1730          fprintf(stderr, "\n");
1731       }
1732       break;
1733    }
1734    case nir_op_fceil: {
1735       if (dst.size() == 1) {
1736          emit_vop1_instruction(ctx, instr, aco_opcode::v_ceil_f32, dst);
1737       } else if (dst.size() == 2) {
1738          if (ctx->options->chip_class >= GFX7) {
1739             emit_vop1_instruction(ctx, instr, aco_opcode::v_ceil_f64, dst);
1740          } else {
1741             /* GFX6 doesn't support V_CEIL_F64, lower it. */
1742             Temp src0 = get_alu_src(ctx, instr->src[0]);
1743
1744             /* trunc = trunc(src0)
1745              * if (src0 > 0.0 && src0 != trunc)
1746              *    trunc += 1.0
1747              */
1748             Temp trunc = emit_trunc_f64(ctx, bld, bld.def(v2), src0);
1749             Temp tmp0 = bld.vopc_e64(aco_opcode::v_cmp_gt_f64, bld.def(bld.lm), src0, Operand(0u));
1750             Temp tmp1 = bld.vopc(aco_opcode::v_cmp_lg_f64, bld.hint_vcc(bld.def(bld.lm)), src0, trunc);
1751             Temp cond = bld.sop2(aco_opcode::s_and_b64, bld.hint_vcc(bld.def(s2)), bld.def(s1, scc), tmp0, tmp1);
1752             Temp add = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), bld.copy(bld.def(v1), Operand(0u)), bld.copy(bld.def(v1), Operand(0x3ff00000u)), cond);
1753             add = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), bld.copy(bld.def(v1), Operand(0u)), add);
1754             bld.vop3(aco_opcode::v_add_f64, Definition(dst), trunc, add);
1755          }
1756       } else {
1757          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1758          nir_print_instr(&instr->instr, stderr);
1759          fprintf(stderr, "\n");
1760       }
1761       break;
1762    }
1763    case nir_op_ftrunc: {
1764       if (dst.size() == 1) {
1765          emit_vop1_instruction(ctx, instr, aco_opcode::v_trunc_f32, dst);
1766       } else if (dst.size() == 2) {
1767          emit_trunc_f64(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1768       } else {
1769          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1770          nir_print_instr(&instr->instr, stderr);
1771          fprintf(stderr, "\n");
1772       }
1773       break;
1774    }
1775    case nir_op_fround_even: {
1776       if (dst.size() == 1) {
1777          emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f32, dst);
1778       } else if (dst.size() == 2) {
1779          if (ctx->options->chip_class >= GFX7) {
1780             emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f64, dst);
1781          } else {
1782             /* GFX6 doesn't support V_RNDNE_F64, lower it. */
1783             Temp src0 = get_alu_src(ctx, instr->src[0]);
1784
1785             Temp src0_lo = bld.tmp(v1), src0_hi = bld.tmp(v1);
1786             bld.pseudo(aco_opcode::p_split_vector, Definition(src0_lo), Definition(src0_hi), src0);
1787
1788             Temp bitmask = bld.sop1(aco_opcode::s_brev_b32, bld.def(s1), bld.copy(bld.def(s1), Operand(-2u)));
1789             Temp bfi = bld.vop3(aco_opcode::v_bfi_b32, bld.def(v1), bitmask, bld.copy(bld.def(v1), Operand(0x43300000u)), as_vgpr(ctx, src0_hi));
1790             Temp tmp = bld.vop3(aco_opcode::v_add_f64, bld.def(v2), src0, bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), bfi));
1791             Instruction *sub = bld.vop3(aco_opcode::v_add_f64, bld.def(v2), tmp, bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), bfi));
1792             static_cast<VOP3A_instruction*>(sub)->neg[1] = true;
1793             tmp = sub->definitions[0].getTemp();
1794
1795             Temp v = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(-1u), Operand(0x432fffffu));
1796             Instruction* vop3 = bld.vopc_e64(aco_opcode::v_cmp_gt_f64, bld.hint_vcc(bld.def(bld.lm)), src0, v);
1797             static_cast<VOP3A_instruction*>(vop3)->abs[0] = true;
1798             Temp cond = vop3->definitions[0].getTemp();
1799
1800             Temp tmp_lo = bld.tmp(v1), tmp_hi = bld.tmp(v1);
1801             bld.pseudo(aco_opcode::p_split_vector, Definition(tmp_lo), Definition(tmp_hi), tmp);
1802             Temp dst0 = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), tmp_lo, as_vgpr(ctx, src0_lo), cond);
1803             Temp dst1 = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), tmp_hi, as_vgpr(ctx, src0_hi), cond);
1804
1805             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1806          }
1807       } else {
1808          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1809          nir_print_instr(&instr->instr, stderr);
1810          fprintf(stderr, "\n");
1811       }
1812       break;
1813    }
1814    case nir_op_fsin:
1815    case nir_op_fcos: {
1816       Temp src = get_alu_src(ctx, instr->src[0]);
1817       aco_ptr<Instruction> norm;
1818       if (dst.size() == 1) {
1819          Temp half_pi = bld.copy(bld.def(s1), Operand(0x3e22f983u));
1820          Temp tmp = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), half_pi, as_vgpr(ctx, src));
1821
1822          /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
1823          if (ctx->options->chip_class < GFX9)
1824             tmp = bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), tmp);
1825
1826          aco_opcode opcode = instr->op == nir_op_fsin ? aco_opcode::v_sin_f32 : aco_opcode::v_cos_f32;
1827          bld.vop1(opcode, Definition(dst), tmp);
1828       } else {
1829          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1830          nir_print_instr(&instr->instr, stderr);
1831          fprintf(stderr, "\n");
1832       }
1833       break;
1834    }
1835    case nir_op_ldexp: {
1836       if (dst.size() == 1) {
1837          bld.vop3(aco_opcode::v_ldexp_f32, Definition(dst),
1838                   as_vgpr(ctx, get_alu_src(ctx, instr->src[0])),
1839                   get_alu_src(ctx, instr->src[1]));
1840       } else if (dst.size() == 2) {
1841          bld.vop3(aco_opcode::v_ldexp_f64, Definition(dst),
1842                   as_vgpr(ctx, get_alu_src(ctx, instr->src[0])),
1843                   get_alu_src(ctx, instr->src[1]));
1844       } else {
1845          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1846          nir_print_instr(&instr->instr, stderr);
1847          fprintf(stderr, "\n");
1848       }
1849       break;
1850    }
1851    case nir_op_frexp_sig: {
1852       if (dst.size() == 1) {
1853          bld.vop1(aco_opcode::v_frexp_mant_f32, Definition(dst),
1854                   get_alu_src(ctx, instr->src[0]));
1855       } else if (dst.size() == 2) {
1856          bld.vop1(aco_opcode::v_frexp_mant_f64, Definition(dst),
1857                   get_alu_src(ctx, instr->src[0]));
1858       } else {
1859          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1860          nir_print_instr(&instr->instr, stderr);
1861          fprintf(stderr, "\n");
1862       }
1863       break;
1864    }
1865    case nir_op_frexp_exp: {
1866       if (instr->src[0].src.ssa->bit_size == 32) {
1867          bld.vop1(aco_opcode::v_frexp_exp_i32_f32, Definition(dst),
1868                   get_alu_src(ctx, instr->src[0]));
1869       } else if (instr->src[0].src.ssa->bit_size == 64) {
1870          bld.vop1(aco_opcode::v_frexp_exp_i32_f64, Definition(dst),
1871                   get_alu_src(ctx, instr->src[0]));
1872       } else {
1873          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1874          nir_print_instr(&instr->instr, stderr);
1875          fprintf(stderr, "\n");
1876       }
1877       break;
1878    }
1879    case nir_op_fsign: {
1880       Temp src = as_vgpr(ctx, get_alu_src(ctx, instr->src[0]));
1881       if (dst.size() == 1) {
1882          Temp cond = bld.vopc(aco_opcode::v_cmp_nlt_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1883          src = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0x3f800000u), src, cond);
1884          cond = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1885          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0xbf800000u), src, cond);
1886       } else if (dst.size() == 2) {
1887          Temp cond = bld.vopc(aco_opcode::v_cmp_nlt_f64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1888          Temp tmp = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0x3FF00000u));
1889          Temp upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), tmp, emit_extract_vector(ctx, src, 1, v1), cond);
1890
1891          cond = bld.vopc(aco_opcode::v_cmp_le_f64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1892          tmp = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0xBFF00000u));
1893          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), tmp, upper, cond);
1894
1895          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), Operand(0u), upper);
1896       } else {
1897          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1898          nir_print_instr(&instr->instr, stderr);
1899          fprintf(stderr, "\n");
1900       }
1901       break;
1902    }
1903    case nir_op_f2f32: {
1904       if (instr->src[0].src.ssa->bit_size == 64) {
1905          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_f64, dst);
1906       } else {
1907          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1908          nir_print_instr(&instr->instr, stderr);
1909          fprintf(stderr, "\n");
1910       }
1911       break;
1912    }
1913    case nir_op_f2f64: {
1914       if (instr->src[0].src.ssa->bit_size == 32) {
1915          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_f32, dst);
1916       } else {
1917          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1918          nir_print_instr(&instr->instr, stderr);
1919          fprintf(stderr, "\n");
1920       }
1921       break;
1922    }
1923    case nir_op_i2f32: {
1924       assert(dst.size() == 1);
1925       emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_i32, dst);
1926       break;
1927    }
1928    case nir_op_i2f64: {
1929       if (instr->src[0].src.ssa->bit_size == 32) {
1930          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_i32, dst);
1931       } else if (instr->src[0].src.ssa->bit_size == 64) {
1932          Temp src = get_alu_src(ctx, instr->src[0]);
1933          RegClass rc = RegClass(src.type(), 1);
1934          Temp lower = bld.tmp(rc), upper = bld.tmp(rc);
1935          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1936          lower = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), lower);
1937          upper = bld.vop1(aco_opcode::v_cvt_f64_i32, bld.def(v2), upper);
1938          upper = bld.vop3(aco_opcode::v_ldexp_f64, bld.def(v2), upper, Operand(32u));
1939          bld.vop3(aco_opcode::v_add_f64, Definition(dst), lower, upper);
1940
1941       } else {
1942          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1943          nir_print_instr(&instr->instr, stderr);
1944          fprintf(stderr, "\n");
1945       }
1946       break;
1947    }
1948    case nir_op_u2f32: {
1949       assert(dst.size() == 1);
1950       emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_u32, dst);
1951       break;
1952    }
1953    case nir_op_u2f64: {
1954       if (instr->src[0].src.ssa->bit_size == 32) {
1955          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_u32, dst);
1956       } else if (instr->src[0].src.ssa->bit_size == 64) {
1957          Temp src = get_alu_src(ctx, instr->src[0]);
1958          RegClass rc = RegClass(src.type(), 1);
1959          Temp lower = bld.tmp(rc), upper = bld.tmp(rc);
1960          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1961          lower = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), lower);
1962          upper = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), upper);
1963          upper = bld.vop3(aco_opcode::v_ldexp_f64, bld.def(v2), upper, Operand(32u));
1964          bld.vop3(aco_opcode::v_add_f64, Definition(dst), lower, upper);
1965       } else {
1966          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1967          nir_print_instr(&instr->instr, stderr);
1968          fprintf(stderr, "\n");
1969       }
1970       break;
1971    }
1972    case nir_op_f2i32: {
1973       Temp src = get_alu_src(ctx, instr->src[0]);
1974       if (instr->src[0].src.ssa->bit_size == 32) {
1975          if (dst.type() == RegType::vgpr)
1976             bld.vop1(aco_opcode::v_cvt_i32_f32, Definition(dst), src);
1977          else
1978             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1979                        bld.vop1(aco_opcode::v_cvt_i32_f32, bld.def(v1), src));
1980
1981       } else if (instr->src[0].src.ssa->bit_size == 64) {
1982          if (dst.type() == RegType::vgpr)
1983             bld.vop1(aco_opcode::v_cvt_i32_f64, Definition(dst), src);
1984          else
1985             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1986                        bld.vop1(aco_opcode::v_cvt_i32_f64, bld.def(v1), src));
1987
1988       } else {
1989          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1990          nir_print_instr(&instr->instr, stderr);
1991          fprintf(stderr, "\n");
1992       }
1993       break;
1994    }
1995    case nir_op_f2u32: {
1996       Temp src = get_alu_src(ctx, instr->src[0]);
1997       if (instr->src[0].src.ssa->bit_size == 32) {
1998          if (dst.type() == RegType::vgpr)
1999             bld.vop1(aco_opcode::v_cvt_u32_f32, Definition(dst), src);
2000          else
2001             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
2002                        bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), src));
2003
2004       } else if (instr->src[0].src.ssa->bit_size == 64) {
2005          if (dst.type() == RegType::vgpr)
2006             bld.vop1(aco_opcode::v_cvt_u32_f64, Definition(dst), src);
2007          else
2008             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
2009                        bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), src));
2010
2011       } else {
2012          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2013          nir_print_instr(&instr->instr, stderr);
2014          fprintf(stderr, "\n");
2015       }
2016       break;
2017    }
2018    case nir_op_f2i64: {
2019       Temp src = get_alu_src(ctx, instr->src[0]);
2020       if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::vgpr) {
2021          Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f32, bld.def(v1), src);
2022          exponent = bld.vop3(aco_opcode::v_med3_i32, bld.def(v1), Operand(0x0u), exponent, Operand(64u));
2023          Temp mantissa = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffu), src);
2024          Temp sign = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
2025          mantissa = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(0x800000u), mantissa);
2026          mantissa = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(7u), mantissa);
2027          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), mantissa);
2028          Temp new_exponent = bld.tmp(v1);
2029          Temp borrow = bld.vsub32(Definition(new_exponent), Operand(63u), exponent, true).def(1).getTemp();
2030          if (ctx->program->chip_class >= GFX8)
2031             mantissa = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), new_exponent, mantissa);
2032          else
2033             mantissa = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), mantissa, new_exponent);
2034          Temp saturate = bld.vop1(aco_opcode::v_bfrev_b32, bld.def(v1), Operand(0xfffffffeu));
2035          Temp lower = bld.tmp(v1), upper = bld.tmp(v1);
2036          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2037          lower = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), lower, Operand(0xffffffffu), borrow);
2038          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), upper, saturate, borrow);
2039          lower = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), sign, lower);
2040          upper = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), sign, upper);
2041          Temp new_lower = bld.tmp(v1);
2042          borrow = bld.vsub32(Definition(new_lower), lower, sign, true).def(1).getTemp();
2043          Temp new_upper = bld.vsub32(bld.def(v1), upper, sign, false, borrow);
2044          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), new_lower, new_upper);
2045
2046       } else if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::sgpr) {
2047          if (src.type() == RegType::vgpr)
2048             src = bld.as_uniform(src);
2049          Temp exponent = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), src, Operand(0x80017u));
2050          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(126u));
2051          exponent = bld.sop2(aco_opcode::s_max_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), exponent);
2052          exponent = bld.sop2(aco_opcode::s_min_u32, bld.def(s1), bld.def(s1, scc), Operand(64u), exponent);
2053          Temp mantissa = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0x7fffffu), src);
2054          Temp sign = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
2055          mantissa = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(0x800000u), mantissa);
2056          mantissa = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), mantissa, Operand(7u));
2057          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), mantissa);
2058          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), Operand(63u), exponent);
2059          mantissa = bld.sop2(aco_opcode::s_lshr_b64, bld.def(s2), bld.def(s1, scc), mantissa, exponent);
2060          Temp cond = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), exponent, Operand(0xffffffffu)); // exp >= 64
2061          Temp saturate = bld.sop1(aco_opcode::s_brev_b64, bld.def(s2), Operand(0xfffffffeu));
2062          mantissa = bld.sop2(aco_opcode::s_cselect_b64, bld.def(s2), saturate, mantissa, cond);
2063          Temp lower = bld.tmp(s1), upper = bld.tmp(s1);
2064          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2065          lower = bld.sop2(aco_opcode::s_xor_b32, bld.def(s1), bld.def(s1, scc), sign, lower);
2066          upper = bld.sop2(aco_opcode::s_xor_b32, bld.def(s1), bld.def(s1, scc), sign, upper);
2067          Temp borrow = bld.tmp(s1);
2068          lower = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(borrow)), lower, sign);
2069          upper = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), upper, sign, borrow);
2070          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2071
2072       } else if (instr->src[0].src.ssa->bit_size == 64) {
2073          Temp vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0x3df00000u));
2074          Temp trunc = emit_trunc_f64(ctx, bld, bld.def(v2), src);
2075          Temp mul = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), trunc, vec);
2076          vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0xc1f00000u));
2077          Temp floor = emit_floor_f64(ctx, bld, bld.def(v2), mul);
2078          Temp fma = bld.vop3(aco_opcode::v_fma_f64, bld.def(v2), floor, vec, trunc);
2079          Temp lower = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), fma);
2080          Temp upper = bld.vop1(aco_opcode::v_cvt_i32_f64, bld.def(v1), floor);
2081          if (dst.type() == RegType::sgpr) {
2082             lower = bld.as_uniform(lower);
2083             upper = bld.as_uniform(upper);
2084          }
2085          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2086
2087       } else {
2088          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2089          nir_print_instr(&instr->instr, stderr);
2090          fprintf(stderr, "\n");
2091       }
2092       break;
2093    }
2094    case nir_op_f2u64: {
2095       Temp src = get_alu_src(ctx, instr->src[0]);
2096       if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::vgpr) {
2097          Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f32, bld.def(v1), src);
2098          Temp exponent_in_range = bld.vopc(aco_opcode::v_cmp_ge_i32, bld.hint_vcc(bld.def(bld.lm)), Operand(64u), exponent);
2099          exponent = bld.vop2(aco_opcode::v_max_i32, bld.def(v1), Operand(0x0u), exponent);
2100          Temp mantissa = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffu), src);
2101          mantissa = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(0x800000u), mantissa);
2102          Temp exponent_small = bld.vsub32(bld.def(v1), Operand(24u), exponent);
2103          Temp small = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), exponent_small, mantissa);
2104          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), mantissa);
2105          Temp new_exponent = bld.tmp(v1);
2106          Temp cond_small = bld.vsub32(Definition(new_exponent), exponent, Operand(24u), true).def(1).getTemp();
2107          if (ctx->program->chip_class >= GFX8)
2108             mantissa = bld.vop3(aco_opcode::v_lshlrev_b64, bld.def(v2), new_exponent, mantissa);
2109          else
2110             mantissa = bld.vop3(aco_opcode::v_lshl_b64, bld.def(v2), mantissa, new_exponent);
2111          Temp lower = bld.tmp(v1), upper = bld.tmp(v1);
2112          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2113          lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), lower, small, cond_small);
2114          upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), upper, Operand(0u), cond_small);
2115          lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xffffffffu), lower, exponent_in_range);
2116          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xffffffffu), upper, exponent_in_range);
2117          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2118
2119       } else if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::sgpr) {
2120          if (src.type() == RegType::vgpr)
2121             src = bld.as_uniform(src);
2122          Temp exponent = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), src, Operand(0x80017u));
2123          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(126u));
2124          exponent = bld.sop2(aco_opcode::s_max_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), exponent);
2125          Temp mantissa = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0x7fffffu), src);
2126          mantissa = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(0x800000u), mantissa);
2127          Temp exponent_small = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), Operand(24u), exponent);
2128          Temp small = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), mantissa, exponent_small);
2129          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), mantissa);
2130          Temp exponent_large = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(24u));
2131          mantissa = bld.sop2(aco_opcode::s_lshl_b64, bld.def(s2), bld.def(s1, scc), mantissa, exponent_large);
2132          Temp cond = bld.sopc(aco_opcode::s_cmp_ge_i32, bld.def(s1, scc), Operand(64u), exponent);
2133          mantissa = bld.sop2(aco_opcode::s_cselect_b64, bld.def(s2), mantissa, Operand(0xffffffffu), cond);
2134          Temp lower = bld.tmp(s1), upper = bld.tmp(s1);
2135          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2136          Temp cond_small = bld.sopc(aco_opcode::s_cmp_le_i32, bld.def(s1, scc), exponent, Operand(24u));
2137          lower = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), small, lower, cond_small);
2138          upper = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), Operand(0u), upper, cond_small);
2139          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2140
2141       } else if (instr->src[0].src.ssa->bit_size == 64) {
2142          Temp vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0x3df00000u));
2143          Temp trunc = emit_trunc_f64(ctx, bld, bld.def(v2), src);
2144          Temp mul = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), trunc, vec);
2145          vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0xc1f00000u));
2146          Temp floor = emit_floor_f64(ctx, bld, bld.def(v2), mul);
2147          Temp fma = bld.vop3(aco_opcode::v_fma_f64, bld.def(v2), floor, vec, trunc);
2148          Temp lower = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), fma);
2149          Temp upper = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), floor);
2150          if (dst.type() == RegType::sgpr) {
2151             lower = bld.as_uniform(lower);
2152             upper = bld.as_uniform(upper);
2153          }
2154          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2155
2156       } else {
2157          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2158          nir_print_instr(&instr->instr, stderr);
2159          fprintf(stderr, "\n");
2160       }
2161       break;
2162    }
2163    case nir_op_b2f32: {
2164       Temp src = get_alu_src(ctx, instr->src[0]);
2165       assert(src.regClass() == bld.lm);
2166
2167       if (dst.regClass() == s1) {
2168          src = bool_to_scalar_condition(ctx, src);
2169          bld.sop2(aco_opcode::s_mul_i32, Definition(dst), Operand(0x3f800000u), src);
2170       } else if (dst.regClass() == v1) {
2171          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(0x3f800000u), src);
2172       } else {
2173          unreachable("Wrong destination register class for nir_op_b2f32.");
2174       }
2175       break;
2176    }
2177    case nir_op_b2f64: {
2178       Temp src = get_alu_src(ctx, instr->src[0]);
2179       assert(src.regClass() == bld.lm);
2180
2181       if (dst.regClass() == s2) {
2182          src = bool_to_scalar_condition(ctx, src);
2183          bld.sop2(aco_opcode::s_cselect_b64, Definition(dst), Operand(0x3f800000u), Operand(0u), bld.scc(src));
2184       } else if (dst.regClass() == v2) {
2185          Temp one = bld.vop1(aco_opcode::v_mov_b32, bld.def(v2), Operand(0x3FF00000u));
2186          Temp upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), one, src);
2187          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), Operand(0u), upper);
2188       } else {
2189          unreachable("Wrong destination register class for nir_op_b2f64.");
2190       }
2191       break;
2192    }
2193    case nir_op_i2i32: {
2194       Temp src = get_alu_src(ctx, instr->src[0]);
2195       if (instr->src[0].src.ssa->bit_size == 64) {
2196          /* we can actually just say dst = src, as it would map the lower register */
2197          emit_extract_vector(ctx, src, 0, dst);
2198       } else {
2199          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2200          nir_print_instr(&instr->instr, stderr);
2201          fprintf(stderr, "\n");
2202       }
2203       break;
2204    }
2205    case nir_op_u2u32: {
2206       Temp src = get_alu_src(ctx, instr->src[0]);
2207       if (instr->src[0].src.ssa->bit_size == 16) {
2208          if (dst.regClass() == s1) {
2209             bld.sop2(aco_opcode::s_and_b32, Definition(dst), bld.def(s1, scc), Operand(0xFFFFu), src);
2210          } else {
2211             // TODO: do better with SDWA
2212             bld.vop2(aco_opcode::v_and_b32, Definition(dst), Operand(0xFFFFu), src);
2213          }
2214       } else if (instr->src[0].src.ssa->bit_size == 64) {
2215          /* we can actually just say dst = src, as it would map the lower register */
2216          emit_extract_vector(ctx, src, 0, dst);
2217       } else {
2218          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2219          nir_print_instr(&instr->instr, stderr);
2220          fprintf(stderr, "\n");
2221       }
2222       break;
2223    }
2224    case nir_op_i2i64: {
2225       Temp src = get_alu_src(ctx, instr->src[0]);
2226       if (src.regClass() == s1) {
2227          Temp high = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
2228          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, high);
2229       } else if (src.regClass() == v1) {
2230          Temp high = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
2231          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, high);
2232       } else {
2233          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2234          nir_print_instr(&instr->instr, stderr);
2235          fprintf(stderr, "\n");
2236       }
2237       break;
2238    }
2239    case nir_op_u2u64: {
2240       Temp src = get_alu_src(ctx, instr->src[0]);
2241       if (instr->src[0].src.ssa->bit_size == 32) {
2242          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, Operand(0u));
2243       } else {
2244          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2245          nir_print_instr(&instr->instr, stderr);
2246          fprintf(stderr, "\n");
2247       }
2248       break;
2249    }
2250    case nir_op_b2i32: {
2251       Temp src = get_alu_src(ctx, instr->src[0]);
2252       assert(src.regClass() == bld.lm);
2253
2254       if (dst.regClass() == s1) {
2255          // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2256          bool_to_scalar_condition(ctx, src, dst);
2257       } else if (dst.regClass() == v1) {
2258          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), src);
2259       } else {
2260          unreachable("Invalid register class for b2i32");
2261       }
2262       break;
2263    }
2264    case nir_op_i2b1: {
2265       Temp src = get_alu_src(ctx, instr->src[0]);
2266       assert(dst.regClass() == bld.lm);
2267
2268       if (src.type() == RegType::vgpr) {
2269          assert(src.regClass() == v1 || src.regClass() == v2);
2270          assert(dst.regClass() == bld.lm);
2271          bld.vopc(src.size() == 2 ? aco_opcode::v_cmp_lg_u64 : aco_opcode::v_cmp_lg_u32,
2272                   Definition(dst), Operand(0u), src).def(0).setHint(vcc);
2273       } else {
2274          assert(src.regClass() == s1 || src.regClass() == s2);
2275          Temp tmp;
2276          if (src.regClass() == s2 && ctx->program->chip_class <= GFX7) {
2277             tmp = bld.sop2(aco_opcode::s_or_b64, bld.def(s2), bld.def(s1, scc), Operand(0u), src).def(1).getTemp();
2278          } else {
2279             tmp = bld.sopc(src.size() == 2 ? aco_opcode::s_cmp_lg_u64 : aco_opcode::s_cmp_lg_u32,
2280                            bld.scc(bld.def(s1)), Operand(0u), src);
2281          }
2282          bool_to_vector_condition(ctx, tmp, dst);
2283       }
2284       break;
2285    }
2286    case nir_op_pack_64_2x32_split: {
2287       Temp src0 = get_alu_src(ctx, instr->src[0]);
2288       Temp src1 = get_alu_src(ctx, instr->src[1]);
2289
2290       bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src0, src1);
2291       break;
2292    }
2293    case nir_op_unpack_64_2x32_split_x:
2294       bld.pseudo(aco_opcode::p_split_vector, Definition(dst), bld.def(dst.regClass()), get_alu_src(ctx, instr->src[0]));
2295       break;
2296    case nir_op_unpack_64_2x32_split_y:
2297       bld.pseudo(aco_opcode::p_split_vector, bld.def(dst.regClass()), Definition(dst), get_alu_src(ctx, instr->src[0]));
2298       break;
2299    case nir_op_pack_half_2x16: {
2300       Temp src = get_alu_src(ctx, instr->src[0], 2);
2301
2302       if (dst.regClass() == v1) {
2303          Temp src0 = bld.tmp(v1);
2304          Temp src1 = bld.tmp(v1);
2305          bld.pseudo(aco_opcode::p_split_vector, Definition(src0), Definition(src1), src);
2306          if (!ctx->block->fp_mode.care_about_round32 || ctx->block->fp_mode.round32 == fp_round_tz)
2307             bld.vop3(aco_opcode::v_cvt_pkrtz_f16_f32, Definition(dst), src0, src1);
2308          else
2309             bld.vop3(aco_opcode::v_cvt_pk_u16_u32, Definition(dst),
2310                      bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src0),
2311                      bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src1));
2312       } else {
2313          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2314          nir_print_instr(&instr->instr, stderr);
2315          fprintf(stderr, "\n");
2316       }
2317       break;
2318    }
2319    case nir_op_unpack_half_2x16_split_x: {
2320       if (dst.regClass() == v1) {
2321          Builder bld(ctx->program, ctx->block);
2322          bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst), get_alu_src(ctx, instr->src[0]));
2323       } else {
2324          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2325          nir_print_instr(&instr->instr, stderr);
2326          fprintf(stderr, "\n");
2327       }
2328       break;
2329    }
2330    case nir_op_unpack_half_2x16_split_y: {
2331       if (dst.regClass() == v1) {
2332          Builder bld(ctx->program, ctx->block);
2333          /* TODO: use SDWA here */
2334          bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst),
2335                   bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(16u), as_vgpr(ctx, get_alu_src(ctx, instr->src[0]))));
2336       } else {
2337          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2338          nir_print_instr(&instr->instr, stderr);
2339          fprintf(stderr, "\n");
2340       }
2341       break;
2342    }
2343    case nir_op_fquantize2f16: {
2344       Temp src = get_alu_src(ctx, instr->src[0]);
2345       Temp f16 = bld.vop1(aco_opcode::v_cvt_f16_f32, bld.def(v1), src);
2346       Temp f32, cmp_res;
2347
2348       if (ctx->program->chip_class >= GFX8) {
2349          Temp mask = bld.copy(bld.def(s1), Operand(0x36Fu)); /* value is NOT negative/positive denormal value */
2350          cmp_res = bld.vopc_e64(aco_opcode::v_cmp_class_f16, bld.hint_vcc(bld.def(bld.lm)), f16, mask);
2351          f32 = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), f16);
2352       } else {
2353          /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2354           * so compare the result and flush to 0 if it's smaller.
2355           */
2356          f32 = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), f16);
2357          Temp smallest = bld.copy(bld.def(s1), Operand(0x38800000u));
2358          Instruction* vop3 = bld.vopc_e64(aco_opcode::v_cmp_nlt_f32, bld.hint_vcc(bld.def(bld.lm)), f32, smallest);
2359          static_cast<VOP3A_instruction*>(vop3)->abs[0] = true;
2360          cmp_res = vop3->definitions[0].getTemp();
2361       }
2362
2363       if (ctx->block->fp_mode.preserve_signed_zero_inf_nan32 || ctx->program->chip_class < GFX8) {
2364          Temp copysign_0 = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0u), as_vgpr(ctx, src));
2365          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), copysign_0, f32, cmp_res);
2366       } else {
2367          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), f32, cmp_res);
2368       }
2369       break;
2370    }
2371    case nir_op_bfm: {
2372       Temp bits = get_alu_src(ctx, instr->src[0]);
2373       Temp offset = get_alu_src(ctx, instr->src[1]);
2374
2375       if (dst.regClass() == s1) {
2376          bld.sop2(aco_opcode::s_bfm_b32, Definition(dst), bits, offset);
2377       } else if (dst.regClass() == v1) {
2378          bld.vop3(aco_opcode::v_bfm_b32, Definition(dst), bits, offset);
2379       } else {
2380          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2381          nir_print_instr(&instr->instr, stderr);
2382          fprintf(stderr, "\n");
2383       }
2384       break;
2385    }
2386    case nir_op_bitfield_select: {
2387       /* (mask & insert) | (~mask & base) */
2388       Temp bitmask = get_alu_src(ctx, instr->src[0]);
2389       Temp insert = get_alu_src(ctx, instr->src[1]);
2390       Temp base = get_alu_src(ctx, instr->src[2]);
2391
2392       /* dst = (insert & bitmask) | (base & ~bitmask) */
2393       if (dst.regClass() == s1) {
2394          aco_ptr<Instruction> sop2;
2395          nir_const_value* const_bitmask = nir_src_as_const_value(instr->src[0].src);
2396          nir_const_value* const_insert = nir_src_as_const_value(instr->src[1].src);
2397          Operand lhs;
2398          if (const_insert && const_bitmask) {
2399             lhs = Operand(const_insert->u32 & const_bitmask->u32);
2400          } else {
2401             insert = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), insert, bitmask);
2402             lhs = Operand(insert);
2403          }
2404
2405          Operand rhs;
2406          nir_const_value* const_base = nir_src_as_const_value(instr->src[2].src);
2407          if (const_base && const_bitmask) {
2408             rhs = Operand(const_base->u32 & ~const_bitmask->u32);
2409          } else {
2410             base = bld.sop2(aco_opcode::s_andn2_b32, bld.def(s1), bld.def(s1, scc), base, bitmask);
2411             rhs = Operand(base);
2412          }
2413
2414          bld.sop2(aco_opcode::s_or_b32, Definition(dst), bld.def(s1, scc), rhs, lhs);
2415
2416       } else if (dst.regClass() == v1) {
2417          if (base.type() == RegType::sgpr && (bitmask.type() == RegType::sgpr || (insert.type() == RegType::sgpr)))
2418             base = as_vgpr(ctx, base);
2419          if (insert.type() == RegType::sgpr && bitmask.type() == RegType::sgpr)
2420             insert = as_vgpr(ctx, insert);
2421
2422          bld.vop3(aco_opcode::v_bfi_b32, Definition(dst), bitmask, insert, base);
2423
2424       } else {
2425          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2426          nir_print_instr(&instr->instr, stderr);
2427          fprintf(stderr, "\n");
2428       }
2429       break;
2430    }
2431    case nir_op_ubfe:
2432    case nir_op_ibfe: {
2433       Temp base = get_alu_src(ctx, instr->src[0]);
2434       Temp offset = get_alu_src(ctx, instr->src[1]);
2435       Temp bits = get_alu_src(ctx, instr->src[2]);
2436
2437       if (dst.type() == RegType::sgpr) {
2438          Operand extract;
2439          nir_const_value* const_offset = nir_src_as_const_value(instr->src[1].src);
2440          nir_const_value* const_bits = nir_src_as_const_value(instr->src[2].src);
2441          if (const_offset && const_bits) {
2442             uint32_t const_extract = (const_bits->u32 << 16) | const_offset->u32;
2443             extract = Operand(const_extract);
2444          } else {
2445             Operand width;
2446             if (const_bits) {
2447                width = Operand(const_bits->u32 << 16);
2448             } else {
2449                width = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), bits, Operand(16u));
2450             }
2451             extract = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), offset, width);
2452          }
2453
2454          aco_opcode opcode;
2455          if (dst.regClass() == s1) {
2456             if (instr->op == nir_op_ubfe)
2457                opcode = aco_opcode::s_bfe_u32;
2458             else
2459                opcode = aco_opcode::s_bfe_i32;
2460          } else if (dst.regClass() == s2) {
2461             if (instr->op == nir_op_ubfe)
2462                opcode = aco_opcode::s_bfe_u64;
2463             else
2464                opcode = aco_opcode::s_bfe_i64;
2465          } else {
2466             unreachable("Unsupported BFE bit size");
2467          }
2468
2469          bld.sop2(opcode, Definition(dst), bld.def(s1, scc), base, extract);
2470
2471       } else {
2472          aco_opcode opcode;
2473          if (dst.regClass() == v1) {
2474             if (instr->op == nir_op_ubfe)
2475                opcode = aco_opcode::v_bfe_u32;
2476             else
2477                opcode = aco_opcode::v_bfe_i32;
2478          } else {
2479             unreachable("Unsupported BFE bit size");
2480          }
2481
2482          emit_vop3a_instruction(ctx, instr, opcode, dst);
2483       }
2484       break;
2485    }
2486    case nir_op_bit_count: {
2487       Temp src = get_alu_src(ctx, instr->src[0]);
2488       if (src.regClass() == s1) {
2489          bld.sop1(aco_opcode::s_bcnt1_i32_b32, Definition(dst), bld.def(s1, scc), src);
2490       } else if (src.regClass() == v1) {
2491          bld.vop3(aco_opcode::v_bcnt_u32_b32, Definition(dst), src, Operand(0u));
2492       } else if (src.regClass() == v2) {
2493          bld.vop3(aco_opcode::v_bcnt_u32_b32, Definition(dst),
2494                   emit_extract_vector(ctx, src, 1, v1),
2495                   bld.vop3(aco_opcode::v_bcnt_u32_b32, bld.def(v1),
2496                            emit_extract_vector(ctx, src, 0, v1), Operand(0u)));
2497       } else if (src.regClass() == s2) {
2498          bld.sop1(aco_opcode::s_bcnt1_i32_b64, Definition(dst), bld.def(s1, scc), src);
2499       } else {
2500          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2501          nir_print_instr(&instr->instr, stderr);
2502          fprintf(stderr, "\n");
2503       }
2504       break;
2505    }
2506    case nir_op_flt: {
2507       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_f32, aco_opcode::v_cmp_lt_f64);
2508       break;
2509    }
2510    case nir_op_fge: {
2511       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_f32, aco_opcode::v_cmp_ge_f64);
2512       break;
2513    }
2514    case nir_op_feq: {
2515       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_eq_f32, aco_opcode::v_cmp_eq_f64);
2516       break;
2517    }
2518    case nir_op_fne: {
2519       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_neq_f32, aco_opcode::v_cmp_neq_f64);
2520       break;
2521    }
2522    case nir_op_ilt: {
2523       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_i32, aco_opcode::v_cmp_lt_i64, aco_opcode::s_cmp_lt_i32);
2524       break;
2525    }
2526    case nir_op_ige: {
2527       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_i32, aco_opcode::v_cmp_ge_i64, aco_opcode::s_cmp_ge_i32);
2528       break;
2529    }
2530    case nir_op_ieq: {
2531       if (instr->src[0].src.ssa->bit_size == 1)
2532          emit_boolean_logic(ctx, instr, Builder::s_xnor, dst);
2533       else
2534          emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_eq_i32, aco_opcode::v_cmp_eq_i64, aco_opcode::s_cmp_eq_i32,
2535                          ctx->program->chip_class >= GFX8 ? aco_opcode::s_cmp_eq_u64 : aco_opcode::num_opcodes);
2536       break;
2537    }
2538    case nir_op_ine: {
2539       if (instr->src[0].src.ssa->bit_size == 1)
2540          emit_boolean_logic(ctx, instr, Builder::s_xor, dst);
2541       else
2542          emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lg_i32, aco_opcode::v_cmp_lg_i64, aco_opcode::s_cmp_lg_i32,
2543                          ctx->program->chip_class >= GFX8 ? aco_opcode::s_cmp_lg_u64 : aco_opcode::num_opcodes);
2544       break;
2545    }
2546    case nir_op_ult: {
2547       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_u32, aco_opcode::v_cmp_lt_u64, aco_opcode::s_cmp_lt_u32);
2548       break;
2549    }
2550    case nir_op_uge: {
2551       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_u32, aco_opcode::v_cmp_ge_u64, aco_opcode::s_cmp_ge_u32);
2552       break;
2553    }
2554    case nir_op_fddx:
2555    case nir_op_fddy:
2556    case nir_op_fddx_fine:
2557    case nir_op_fddy_fine:
2558    case nir_op_fddx_coarse:
2559    case nir_op_fddy_coarse: {
2560       Temp src = get_alu_src(ctx, instr->src[0]);
2561       uint16_t dpp_ctrl1, dpp_ctrl2;
2562       if (instr->op == nir_op_fddx_fine) {
2563          dpp_ctrl1 = dpp_quad_perm(0, 0, 2, 2);
2564          dpp_ctrl2 = dpp_quad_perm(1, 1, 3, 3);
2565       } else if (instr->op == nir_op_fddy_fine) {
2566          dpp_ctrl1 = dpp_quad_perm(0, 1, 0, 1);
2567          dpp_ctrl2 = dpp_quad_perm(2, 3, 2, 3);
2568       } else {
2569          dpp_ctrl1 = dpp_quad_perm(0, 0, 0, 0);
2570          if (instr->op == nir_op_fddx || instr->op == nir_op_fddx_coarse)
2571             dpp_ctrl2 = dpp_quad_perm(1, 1, 1, 1);
2572          else
2573             dpp_ctrl2 = dpp_quad_perm(2, 2, 2, 2);
2574       }
2575
2576       Temp tmp;
2577       if (ctx->program->chip_class >= GFX8) {
2578          Temp tl = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl1);
2579          tmp = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), src, tl, dpp_ctrl2);
2580       } else {
2581          Temp tl = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl1);
2582          Temp tr = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl2);
2583          tmp = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), tr, tl);
2584       }
2585       emit_wqm(ctx, tmp, dst, true);
2586       break;
2587    }
2588    default:
2589       fprintf(stderr, "Unknown NIR ALU instr: ");
2590       nir_print_instr(&instr->instr, stderr);
2591       fprintf(stderr, "\n");
2592    }
2593 }
2594
2595 void visit_load_const(isel_context *ctx, nir_load_const_instr *instr)
2596 {
2597    Temp dst = get_ssa_temp(ctx, &instr->def);
2598
2599    // TODO: we really want to have the resulting type as this would allow for 64bit literals
2600    // which get truncated the lsb if double and msb if int
2601    // for now, we only use s_mov_b64 with 64bit inline constants
2602    assert(instr->def.num_components == 1 && "Vector load_const should be lowered to scalar.");
2603    assert(dst.type() == RegType::sgpr);
2604
2605    Builder bld(ctx->program, ctx->block);
2606
2607    if (instr->def.bit_size == 1) {
2608       assert(dst.regClass() == bld.lm);
2609       int val = instr->value[0].b ? -1 : 0;
2610       Operand op = bld.lm.size() == 1 ? Operand((uint32_t) val) : Operand((uint64_t) val);
2611       bld.sop1(Builder::s_mov, Definition(dst), op);
2612    } else if (dst.size() == 1) {
2613       bld.copy(Definition(dst), Operand(instr->value[0].u32));
2614    } else {
2615       assert(dst.size() != 1);
2616       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
2617       if (instr->def.bit_size == 64)
2618          for (unsigned i = 0; i < dst.size(); i++)
2619             vec->operands[i] = Operand{(uint32_t)(instr->value[0].u64 >> i * 32)};
2620       else {
2621          for (unsigned i = 0; i < dst.size(); i++)
2622             vec->operands[i] = Operand{instr->value[i].u32};
2623       }
2624       vec->definitions[0] = Definition(dst);
2625       ctx->block->instructions.emplace_back(std::move(vec));
2626    }
2627 }
2628
2629 uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2630 {
2631    uint32_t new_mask = 0;
2632    for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2633       if (mask & (1u << i))
2634          new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2635    return new_mask;
2636 }
2637
2638 Operand load_lds_size_m0(isel_context *ctx)
2639 {
2640    /* TODO: m0 does not need to be initialized on GFX9+ */
2641    Builder bld(ctx->program, ctx->block);
2642    return bld.m0((Temp)bld.sopk(aco_opcode::s_movk_i32, bld.def(s1, m0), 0xffff));
2643 }
2644
2645 Temp load_lds(isel_context *ctx, unsigned elem_size_bytes, Temp dst,
2646               Temp address, unsigned base_offset, unsigned align)
2647 {
2648    assert(util_is_power_of_two_nonzero(align) && align >= 4);
2649
2650    Builder bld(ctx->program, ctx->block);
2651
2652    Operand m = load_lds_size_m0(ctx);
2653
2654    unsigned num_components = dst.size() * 4u / elem_size_bytes;
2655    unsigned bytes_read = 0;
2656    unsigned result_size = 0;
2657    unsigned total_bytes = num_components * elem_size_bytes;
2658    std::array<Temp, NIR_MAX_VEC_COMPONENTS> result;
2659    bool large_ds_read = ctx->options->chip_class >= GFX7;
2660    bool usable_read2 = ctx->options->chip_class >= GFX7;
2661
2662    while (bytes_read < total_bytes) {
2663       unsigned todo = total_bytes - bytes_read;
2664       bool aligned8 = bytes_read % 8 == 0 && align % 8 == 0;
2665       bool aligned16 = bytes_read % 16 == 0 && align % 16 == 0;
2666
2667       aco_opcode op = aco_opcode::last_opcode;
2668       bool read2 = false;
2669       if (todo >= 16 && aligned16 && large_ds_read) {
2670          op = aco_opcode::ds_read_b128;
2671          todo = 16;
2672       } else if (todo >= 16 && aligned8 && usable_read2) {
2673          op = aco_opcode::ds_read2_b64;
2674          read2 = true;
2675          todo = 16;
2676       } else if (todo >= 12 && aligned16 && large_ds_read) {
2677          op = aco_opcode::ds_read_b96;
2678          todo = 12;
2679       } else if (todo >= 8 && aligned8) {
2680          op = aco_opcode::ds_read_b64;
2681          todo = 8;
2682       } else if (todo >= 8 && usable_read2) {
2683          op = aco_opcode::ds_read2_b32;
2684          read2 = true;
2685          todo = 8;
2686       } else if (todo >= 4) {
2687          op = aco_opcode::ds_read_b32;
2688          todo = 4;
2689       } else {
2690          assert(false);
2691       }
2692       assert(todo % elem_size_bytes == 0);
2693       unsigned num_elements = todo / elem_size_bytes;
2694       unsigned offset = base_offset + bytes_read;
2695       unsigned max_offset = read2 ? 1019 : 65535;
2696
2697       Temp address_offset = address;
2698       if (offset > max_offset) {
2699          address_offset = bld.vadd32(bld.def(v1), Operand(base_offset), address_offset);
2700          offset = bytes_read;
2701       }
2702       assert(offset <= max_offset); /* bytes_read shouldn't be large enough for this to happen */
2703
2704       Temp res;
2705       if (num_components == 1 && dst.type() == RegType::vgpr)
2706          res = dst;
2707       else
2708          res = bld.tmp(RegClass(RegType::vgpr, todo / 4));
2709
2710       if (read2)
2711          res = bld.ds(op, Definition(res), address_offset, m, offset / (todo / 2), (offset / (todo / 2)) + 1);
2712       else
2713          res = bld.ds(op, Definition(res), address_offset, m, offset);
2714
2715       if (num_components == 1) {
2716          assert(todo == total_bytes);
2717          if (dst.type() == RegType::sgpr)
2718             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), res);
2719          return dst;
2720       }
2721
2722       if (dst.type() == RegType::sgpr) {
2723          Temp new_res = bld.tmp(RegType::sgpr, res.size());
2724          expand_vector(ctx, res, new_res, res.size(), (1 << res.size()) - 1);
2725          res = new_res;
2726       }
2727
2728       if (num_elements == 1) {
2729          result[result_size++] = res;
2730       } else {
2731          assert(res != dst && res.size() % num_elements == 0);
2732          aco_ptr<Pseudo_instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector, Format::PSEUDO, 1, num_elements)};
2733          split->operands[0] = Operand(res);
2734          for (unsigned i = 0; i < num_elements; i++)
2735             split->definitions[i] = Definition(result[result_size++] = bld.tmp(res.type(), elem_size_bytes / 4));
2736          ctx->block->instructions.emplace_back(std::move(split));
2737       }
2738
2739       bytes_read += todo;
2740    }
2741
2742    assert(result_size == num_components && result_size > 1);
2743    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, result_size, 1)};
2744    for (unsigned i = 0; i < result_size; i++)
2745       vec->operands[i] = Operand(result[i]);
2746    vec->definitions[0] = Definition(dst);
2747    ctx->block->instructions.emplace_back(std::move(vec));
2748    ctx->allocated_vec.emplace(dst.id(), result);
2749
2750    return dst;
2751 }
2752
2753 Temp extract_subvector(isel_context *ctx, Temp data, unsigned start, unsigned size, RegType type)
2754 {
2755    if (start == 0 && size == data.size())
2756       return type == RegType::vgpr ? as_vgpr(ctx, data) : data;
2757
2758    unsigned size_hint = 1;
2759    auto it = ctx->allocated_vec.find(data.id());
2760    if (it != ctx->allocated_vec.end())
2761       size_hint = it->second[0].size();
2762    if (size % size_hint || start % size_hint)
2763       size_hint = 1;
2764
2765    start /= size_hint;
2766    size /= size_hint;
2767
2768    Temp elems[size];
2769    for (unsigned i = 0; i < size; i++)
2770       elems[i] = emit_extract_vector(ctx, data, start + i, RegClass(type, size_hint));
2771
2772    if (size == 1)
2773       return type == RegType::vgpr ? as_vgpr(ctx, elems[0]) : elems[0];
2774
2775    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, size, 1)};
2776    for (unsigned i = 0; i < size; i++)
2777       vec->operands[i] = Operand(elems[i]);
2778    Temp res = {ctx->program->allocateId(), RegClass(type, size * size_hint)};
2779    vec->definitions[0] = Definition(res);
2780    ctx->block->instructions.emplace_back(std::move(vec));
2781    return res;
2782 }
2783
2784 void ds_write_helper(isel_context *ctx, Operand m, Temp address, Temp data, unsigned data_start, unsigned total_size, unsigned offset0, unsigned offset1, unsigned align)
2785 {
2786    Builder bld(ctx->program, ctx->block);
2787    unsigned bytes_written = 0;
2788    bool large_ds_write = ctx->options->chip_class >= GFX7;
2789    bool usable_write2 = ctx->options->chip_class >= GFX7;
2790
2791    while (bytes_written < total_size * 4) {
2792       unsigned todo = total_size * 4 - bytes_written;
2793       bool aligned8 = bytes_written % 8 == 0 && align % 8 == 0;
2794       bool aligned16 = bytes_written % 16 == 0 && align % 16 == 0;
2795
2796       aco_opcode op = aco_opcode::last_opcode;
2797       bool write2 = false;
2798       unsigned size = 0;
2799       if (todo >= 16 && aligned16 && large_ds_write) {
2800          op = aco_opcode::ds_write_b128;
2801          size = 4;
2802       } else if (todo >= 16 && aligned8 && usable_write2) {
2803          op = aco_opcode::ds_write2_b64;
2804          write2 = true;
2805          size = 4;
2806       } else if (todo >= 12 && aligned16 && large_ds_write) {
2807          op = aco_opcode::ds_write_b96;
2808          size = 3;
2809       } else if (todo >= 8 && aligned8) {
2810          op = aco_opcode::ds_write_b64;
2811          size = 2;
2812       } else if (todo >= 8 && usable_write2) {
2813          op = aco_opcode::ds_write2_b32;
2814          write2 = true;
2815          size = 2;
2816       } else if (todo >= 4) {
2817          op = aco_opcode::ds_write_b32;
2818          size = 1;
2819       } else {
2820          assert(false);
2821       }
2822
2823       unsigned offset = offset0 + offset1 + bytes_written;
2824       unsigned max_offset = write2 ? 1020 : 65535;
2825       Temp address_offset = address;
2826       if (offset > max_offset) {
2827          address_offset = bld.vadd32(bld.def(v1), Operand(offset0), address_offset);
2828          offset = offset1 + bytes_written;
2829       }
2830       assert(offset <= max_offset); /* offset1 shouldn't be large enough for this to happen */
2831
2832       if (write2) {
2833          Temp val0 = extract_subvector(ctx, data, data_start + (bytes_written >> 2), size / 2, RegType::vgpr);
2834          Temp val1 = extract_subvector(ctx, data, data_start + (bytes_written >> 2) + 1, size / 2, RegType::vgpr);
2835          bld.ds(op, address_offset, val0, val1, m, offset / size / 2, (offset / size / 2) + 1);
2836       } else {
2837          Temp val = extract_subvector(ctx, data, data_start + (bytes_written >> 2), size, RegType::vgpr);
2838          bld.ds(op, address_offset, val, m, offset);
2839       }
2840
2841       bytes_written += size * 4;
2842    }
2843 }
2844
2845 void store_lds(isel_context *ctx, unsigned elem_size_bytes, Temp data, uint32_t wrmask,
2846                Temp address, unsigned base_offset, unsigned align)
2847 {
2848    assert(util_is_power_of_two_nonzero(align) && align >= 4);
2849    assert(elem_size_bytes == 4 || elem_size_bytes == 8);
2850
2851    Operand m = load_lds_size_m0(ctx);
2852
2853    /* we need at most two stores, assuming that the writemask is at most 4 bits wide */
2854    assert(wrmask <= 0x0f);
2855    int start[2], count[2];
2856    u_bit_scan_consecutive_range(&wrmask, &start[0], &count[0]);
2857    u_bit_scan_consecutive_range(&wrmask, &start[1], &count[1]);
2858    assert(wrmask == 0);
2859
2860    /* one combined store is sufficient */
2861    if (count[0] == count[1] && (align % elem_size_bytes) == 0 && (base_offset % elem_size_bytes) == 0) {
2862       Builder bld(ctx->program, ctx->block);
2863
2864       Temp address_offset = address;
2865       if ((base_offset / elem_size_bytes) + start[1] > 255) {
2866          address_offset = bld.vadd32(bld.def(v1), Operand(base_offset), address_offset);
2867          base_offset = 0;
2868       }
2869
2870       assert(count[0] == 1);
2871       RegClass xtract_rc(RegType::vgpr, elem_size_bytes / 4);
2872
2873       Temp val0 = emit_extract_vector(ctx, data, start[0], xtract_rc);
2874       Temp val1 = emit_extract_vector(ctx, data, start[1], xtract_rc);
2875       aco_opcode op = elem_size_bytes == 4 ? aco_opcode::ds_write2_b32 : aco_opcode::ds_write2_b64;
2876       base_offset = base_offset / elem_size_bytes;
2877       bld.ds(op, address_offset, val0, val1, m,
2878              base_offset + start[0], base_offset + start[1]);
2879       return;
2880    }
2881
2882    for (unsigned i = 0; i < 2; i++) {
2883       if (count[i] == 0)
2884          continue;
2885
2886       unsigned elem_size_words = elem_size_bytes / 4;
2887       ds_write_helper(ctx, m, address, data, start[i] * elem_size_words, count[i] * elem_size_words,
2888                       base_offset, start[i] * elem_size_bytes, align);
2889    }
2890    return;
2891 }
2892
2893 unsigned calculate_lds_alignment(isel_context *ctx, unsigned const_offset)
2894 {
2895    unsigned align = 16;
2896    if (const_offset)
2897       align = std::min(align, 1u << (ffs(const_offset) - 1));
2898
2899    return align;
2900 }
2901
2902
2903 Temp create_vec_from_array(isel_context *ctx, Temp arr[], unsigned cnt, RegType reg_type, unsigned split_cnt = 0u, Temp dst = Temp())
2904 {
2905    Builder bld(ctx->program, ctx->block);
2906
2907    if (!dst.id())
2908       dst = bld.tmp(RegClass(reg_type, cnt * arr[0].size()));
2909
2910    std::array<Temp, NIR_MAX_VEC_COMPONENTS> allocated_vec;
2911    aco_ptr<Pseudo_instruction> instr {create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, cnt, 1)};
2912    instr->definitions[0] = Definition(dst);
2913
2914    for (unsigned i = 0; i < cnt; ++i) {
2915       assert(arr[i].size() == arr[0].size());
2916       allocated_vec[i] = arr[i];
2917       instr->operands[i] = Operand(arr[i]);
2918    }
2919
2920    bld.insert(std::move(instr));
2921
2922    if (split_cnt)
2923       emit_split_vector(ctx, dst, split_cnt);
2924    else
2925       ctx->allocated_vec.emplace(dst.id(), allocated_vec); /* emit_split_vector already does this */
2926
2927    return dst;
2928 }
2929
2930 inline unsigned resolve_excess_vmem_const_offset(Builder &bld, Temp &voffset, unsigned const_offset)
2931 {
2932    if (const_offset >= 4096) {
2933       unsigned excess_const_offset = const_offset / 4096u * 4096u;
2934       const_offset %= 4096u;
2935
2936       if (!voffset.id())
2937          voffset = bld.copy(bld.def(v1), Operand(excess_const_offset));
2938       else if (unlikely(voffset.regClass() == s1))
2939          voffset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), Operand(excess_const_offset), Operand(voffset));
2940       else if (likely(voffset.regClass() == v1))
2941          voffset = bld.vadd32(bld.def(v1), Operand(voffset), Operand(excess_const_offset));
2942       else
2943          unreachable("Unsupported register class of voffset");
2944    }
2945
2946    return const_offset;
2947 }
2948
2949 void emit_single_mubuf_store(isel_context *ctx, Temp descriptor, Temp voffset, Temp soffset, Temp vdata,
2950                              unsigned const_offset = 0u, bool allow_reorder = true, bool slc = false)
2951 {
2952    assert(vdata.id());
2953    assert(vdata.size() != 3 || ctx->program->chip_class != GFX6);
2954    assert(vdata.size() >= 1 && vdata.size() <= 4);
2955
2956    Builder bld(ctx->program, ctx->block);
2957    aco_opcode op = (aco_opcode) ((unsigned) aco_opcode::buffer_store_dword + vdata.size() - 1);
2958    const_offset = resolve_excess_vmem_const_offset(bld, voffset, const_offset);
2959
2960    Operand voffset_op = voffset.id() ? Operand(as_vgpr(ctx, voffset)) : Operand(v1);
2961    Operand soffset_op = soffset.id() ? Operand(soffset) : Operand(0u);
2962    Builder::Result r = bld.mubuf(op, Operand(descriptor), voffset_op, soffset_op, Operand(vdata), const_offset,
2963                                  /* offen */ !voffset_op.isUndefined(), /* idxen*/ false, /* addr64 */ false,
2964                                  /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc);
2965
2966    static_cast<MUBUF_instruction *>(r.instr)->can_reorder = allow_reorder;
2967 }
2968
2969 void store_vmem_mubuf(isel_context *ctx, Temp src, Temp descriptor, Temp voffset, Temp soffset,
2970                                    unsigned base_const_offset, unsigned elem_size_bytes, unsigned write_mask,
2971                                    bool allow_combining = true, bool reorder = true, bool slc = false)
2972 {
2973    Builder bld(ctx->program, ctx->block);
2974    assert(elem_size_bytes == 4 || elem_size_bytes == 8);
2975    assert(write_mask);
2976
2977    if (elem_size_bytes == 8) {
2978       elem_size_bytes = 4;
2979       write_mask = widen_mask(write_mask, 2);
2980    }
2981
2982    while (write_mask) {
2983       int start = 0;
2984       int count = 0;
2985       u_bit_scan_consecutive_range(&write_mask, &start, &count);
2986       assert(count > 0);
2987       assert(start >= 0);
2988
2989       while (count > 0) {
2990          unsigned sub_count = allow_combining ? MIN2(count, 4) : 1;
2991          unsigned const_offset = (unsigned) start * elem_size_bytes + base_const_offset;
2992
2993          /* GFX6 doesn't have buffer_store_dwordx3, so make sure not to emit that here either. */
2994          if (unlikely(ctx->program->chip_class == GFX6 && sub_count == 3))
2995             sub_count = 2;
2996
2997          Temp elem = extract_subvector(ctx, src, start, sub_count, RegType::vgpr);
2998          emit_single_mubuf_store(ctx, descriptor, voffset, soffset, elem, const_offset, reorder, slc);
2999
3000          count -= sub_count;
3001          start += sub_count;
3002       }
3003
3004       assert(count == 0);
3005    }
3006 }
3007
3008 Temp emit_single_mubuf_load(isel_context *ctx, Temp descriptor, Temp voffset, Temp soffset,
3009                             unsigned const_offset, unsigned size_dwords, bool allow_reorder = true)
3010 {
3011    assert(size_dwords != 3 || ctx->program->chip_class != GFX6);
3012    assert(size_dwords >= 1 && size_dwords <= 4);
3013
3014    Builder bld(ctx->program, ctx->block);
3015    Temp vdata = bld.tmp(RegClass(RegType::vgpr, size_dwords));
3016    aco_opcode op = (aco_opcode) ((unsigned) aco_opcode::buffer_load_dword + size_dwords - 1);
3017    const_offset = resolve_excess_vmem_const_offset(bld, voffset, const_offset);
3018
3019    Operand voffset_op = voffset.id() ? Operand(as_vgpr(ctx, voffset)) : Operand(v1);
3020    Operand soffset_op = soffset.id() ? Operand(soffset) : Operand(0u);
3021    Builder::Result r = bld.mubuf(op, Definition(vdata), Operand(descriptor), voffset_op, soffset_op, const_offset,
3022                                  /* offen */ !voffset_op.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3023                                  /* disable_wqm */ false, /* glc */ true,
3024                                  /* dlc*/ ctx->program->chip_class >= GFX10, /* slc */ false);
3025
3026    static_cast<MUBUF_instruction *>(r.instr)->can_reorder = allow_reorder;
3027
3028    return vdata;
3029 }
3030
3031 void load_vmem_mubuf(isel_context *ctx, Temp dst, Temp descriptor, Temp voffset, Temp soffset,
3032                      unsigned base_const_offset, unsigned elem_size_bytes, unsigned num_components,
3033                      unsigned stride = 0u, bool allow_combining = true, bool allow_reorder = true)
3034 {
3035    assert(elem_size_bytes == 4 || elem_size_bytes == 8);
3036    assert((num_components * elem_size_bytes / 4) == dst.size());
3037    assert(!!stride != allow_combining);
3038
3039    Builder bld(ctx->program, ctx->block);
3040    unsigned split_cnt = num_components;
3041
3042    if (elem_size_bytes == 8) {
3043       elem_size_bytes = 4;
3044       num_components *= 2;
3045    }
3046
3047    if (!stride)
3048       stride = elem_size_bytes;
3049
3050    unsigned load_size = 1;
3051    if (allow_combining) {
3052       if ((num_components % 4) == 0)
3053          load_size = 4;
3054       else if ((num_components % 3) == 0 && ctx->program->chip_class != GFX6)
3055          load_size = 3;
3056       else if ((num_components % 2) == 0)
3057          load_size = 2;
3058    }
3059
3060    unsigned num_loads = num_components / load_size;
3061    std::array<Temp, NIR_MAX_VEC_COMPONENTS> elems;
3062
3063    for (unsigned i = 0; i < num_loads; ++i) {
3064       unsigned const_offset = i * stride * load_size + base_const_offset;
3065       elems[i] = emit_single_mubuf_load(ctx, descriptor, voffset, soffset, const_offset, load_size, allow_reorder);
3066    }
3067
3068    create_vec_from_array(ctx, elems.data(), num_loads, RegType::vgpr, split_cnt, dst);
3069 }
3070
3071 std::pair<Temp, unsigned> offset_add_from_nir(isel_context *ctx, const std::pair<Temp, unsigned> &base_offset, nir_src *off_src, unsigned stride = 1u)
3072 {
3073    Builder bld(ctx->program, ctx->block);
3074    Temp offset = base_offset.first;
3075    unsigned const_offset = base_offset.second;
3076
3077    if (!nir_src_is_const(*off_src)) {
3078       Temp indirect_offset_arg = get_ssa_temp(ctx, off_src->ssa);
3079       Temp with_stride;
3080
3081       /* Calculate indirect offset with stride */
3082       if (likely(indirect_offset_arg.regClass() == v1))
3083          with_stride = bld.v_mul_imm(bld.def(v1), indirect_offset_arg, stride);
3084       else if (indirect_offset_arg.regClass() == s1)
3085          with_stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), indirect_offset_arg);
3086       else
3087          unreachable("Unsupported register class of indirect offset");
3088
3089       /* Add to the supplied base offset */
3090       if (offset.id() == 0)
3091          offset = with_stride;
3092       else if (unlikely(offset.regClass() == s1 && with_stride.regClass() == s1))
3093          offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), with_stride, offset);
3094       else if (offset.size() == 1 && with_stride.size() == 1)
3095          offset = bld.vadd32(bld.def(v1), with_stride, offset);
3096       else
3097          unreachable("Unsupported register class of indirect offset");
3098    } else {
3099       unsigned const_offset_arg = nir_src_as_uint(*off_src);
3100       const_offset += const_offset_arg * stride;
3101    }
3102
3103    return std::make_pair(offset, const_offset);
3104 }
3105
3106 std::pair<Temp, unsigned> offset_add(isel_context *ctx, const std::pair<Temp, unsigned> &off1, const std::pair<Temp, unsigned> &off2)
3107 {
3108    Builder bld(ctx->program, ctx->block);
3109    Temp offset;
3110
3111    if (off1.first.id() && off2.first.id()) {
3112       if (unlikely(off1.first.regClass() == s1 && off2.first.regClass() == s1))
3113          offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), off1.first, off2.first);
3114       else if (off1.first.size() == 1 && off2.first.size() == 1)
3115          offset = bld.vadd32(bld.def(v1), off1.first, off2.first);
3116       else
3117          unreachable("Unsupported register class of indirect offset");
3118    } else {
3119       offset = off1.first.id() ? off1.first : off2.first;
3120    }
3121
3122    return std::make_pair(offset, off1.second + off2.second);
3123 }
3124
3125 std::pair<Temp, unsigned> offset_mul(isel_context *ctx, const std::pair<Temp, unsigned> &offs, unsigned multiplier)
3126 {
3127    Builder bld(ctx->program, ctx->block);
3128    unsigned const_offset = offs.second * multiplier;
3129
3130    if (!offs.first.id())
3131       return std::make_pair(offs.first, const_offset);
3132
3133    Temp offset = unlikely(offs.first.regClass() == s1)
3134                  ? bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(multiplier), offs.first)
3135                  : bld.v_mul_imm(bld.def(v1), offs.first, multiplier);
3136
3137    return std::make_pair(offset, const_offset);
3138 }
3139
3140 std::pair<Temp, unsigned> get_intrinsic_io_basic_offset(isel_context *ctx, nir_intrinsic_instr *instr, unsigned base_stride, unsigned component_stride)
3141 {
3142    Builder bld(ctx->program, ctx->block);
3143
3144    /* base is the driver_location, which is already multiplied by 4, so is in dwords */
3145    unsigned const_offset = nir_intrinsic_base(instr) * base_stride;
3146    /* component is in bytes */
3147    const_offset += nir_intrinsic_component(instr) * component_stride;
3148
3149    /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
3150    nir_src *off_src = nir_get_io_offset_src(instr);
3151    return offset_add_from_nir(ctx, std::make_pair(Temp(), const_offset), off_src, 4u * base_stride);
3152 }
3153
3154 std::pair<Temp, unsigned> get_intrinsic_io_basic_offset(isel_context *ctx, nir_intrinsic_instr *instr, unsigned stride = 1u)
3155 {
3156    return get_intrinsic_io_basic_offset(ctx, instr, stride, stride);
3157 }
3158
3159 Temp get_tess_rel_patch_id(isel_context *ctx)
3160 {
3161    Builder bld(ctx->program, ctx->block);
3162
3163    switch (ctx->shader->info.stage) {
3164    case MESA_SHADER_TESS_CTRL:
3165       return bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0xffu),
3166                       get_arg(ctx, ctx->args->ac.tcs_rel_ids));
3167    case MESA_SHADER_TESS_EVAL:
3168       return get_arg(ctx, ctx->args->tes_rel_patch_id);
3169    default:
3170       unreachable("Unsupported stage in get_tess_rel_patch_id");
3171    }
3172 }
3173
3174 std::pair<Temp, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context *ctx, nir_intrinsic_instr *instr)
3175 {
3176    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
3177    Builder bld(ctx->program, ctx->block);
3178
3179    uint32_t tcs_in_patch_stride = ctx->args->options->key.tcs.input_vertices * ctx->tcs_num_inputs * 4;
3180    uint32_t tcs_in_vertex_stride = ctx->tcs_num_inputs * 4;
3181
3182    std::pair<Temp, unsigned> offs = get_intrinsic_io_basic_offset(ctx, instr);
3183
3184    nir_src *vertex_index_src = nir_get_io_vertex_index_src(instr);
3185    offs = offset_add_from_nir(ctx, offs, vertex_index_src, tcs_in_vertex_stride);
3186
3187    Temp rel_patch_id = get_tess_rel_patch_id(ctx);
3188    Temp tcs_in_current_patch_offset = bld.v_mul24_imm(bld.def(v1), rel_patch_id, tcs_in_patch_stride);
3189    offs = offset_add(ctx, offs, std::make_pair(tcs_in_current_patch_offset, 0));
3190
3191    return offset_mul(ctx, offs, 4u);
3192 }
3193
3194 std::pair<Temp, unsigned> get_tcs_output_lds_offset(isel_context *ctx, nir_intrinsic_instr *instr = nullptr, bool per_vertex = false)
3195 {
3196    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
3197    Builder bld(ctx->program, ctx->block);
3198
3199    uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * ctx->tcs_num_inputs * 16;
3200    uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
3201    uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->args->shader_info->tcs.patch_outputs_written);
3202    uint32_t output_vertex_size = num_tcs_outputs * 16;
3203    uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
3204    uint32_t output_patch_stride = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
3205
3206    std::pair<Temp, unsigned> offs = instr
3207                                     ? get_intrinsic_io_basic_offset(ctx, instr, 4u)
3208                                     : std::make_pair(Temp(), 0u);
3209
3210    Temp rel_patch_id = get_tess_rel_patch_id(ctx);
3211    Temp patch_off = bld.v_mul24_imm(bld.def(v1), rel_patch_id, output_patch_stride);
3212
3213    if (per_vertex) {
3214       assert(instr);
3215
3216       nir_src *vertex_index_src = nir_get_io_vertex_index_src(instr);
3217       offs = offset_add_from_nir(ctx, offs, vertex_index_src, output_vertex_size);
3218
3219       uint32_t output_patch0_offset = (input_patch_size * ctx->tcs_num_patches);
3220       offs = offset_add(ctx, offs, std::make_pair(patch_off, output_patch0_offset));
3221    } else {
3222       uint32_t output_patch0_patch_data_offset = (input_patch_size * ctx->tcs_num_patches + pervertex_output_patch_size);
3223       offs = offset_add(ctx, offs, std::make_pair(patch_off, output_patch0_patch_data_offset));
3224    }
3225
3226    return offs;
3227 }
3228
3229 std::pair<Temp, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context *ctx, nir_intrinsic_instr *instr)
3230 {
3231    Builder bld(ctx->program, ctx->block);
3232
3233    unsigned vertices_per_patch = ctx->shader->info.tess.tcs_vertices_out;
3234    unsigned attr_stride = vertices_per_patch * ctx->tcs_num_patches;
3235
3236    std::pair<Temp, unsigned> offs = get_intrinsic_io_basic_offset(ctx, instr, attr_stride * 4u, 4u);
3237
3238    Temp rel_patch_id = get_tess_rel_patch_id(ctx);
3239    Temp patch_off = bld.v_mul24_imm(bld.def(v1), rel_patch_id, vertices_per_patch * 16u);
3240    offs = offset_add(ctx, offs, std::make_pair(patch_off, 0u));
3241
3242    nir_src *vertex_index_src = nir_get_io_vertex_index_src(instr);
3243    offs = offset_add_from_nir(ctx, offs, vertex_index_src, 16u);
3244
3245    return offs;
3246 }
3247
3248 std::pair<Temp, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context *ctx, nir_intrinsic_instr *instr = nullptr, unsigned const_base_offset = 0u)
3249 {
3250    Builder bld(ctx->program, ctx->block);
3251
3252    unsigned num_tcs_outputs = ctx->shader->info.stage == MESA_SHADER_TESS_CTRL
3253                               ? util_last_bit64(ctx->args->shader_info->tcs.outputs_written)
3254                               : ctx->args->options->key.tes.tcs_num_outputs;
3255
3256    unsigned output_vertex_size = num_tcs_outputs * 16;
3257    unsigned per_vertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
3258    unsigned per_patch_data_offset = per_vertex_output_patch_size * ctx->tcs_num_patches;
3259    unsigned attr_stride = ctx->tcs_num_patches;
3260
3261    std::pair<Temp, unsigned> offs = instr
3262                                     ? get_intrinsic_io_basic_offset(ctx, instr, attr_stride * 4u, 4u)
3263                                     : std::make_pair(Temp(), 0u);
3264
3265    if (const_base_offset)
3266       offs.second += const_base_offset * attr_stride;
3267
3268    Temp rel_patch_id = get_tess_rel_patch_id(ctx);
3269    Temp patch_off = bld.v_mul_imm(bld.def(v1), rel_patch_id, 16u);
3270    offs = offset_add(ctx, offs, std::make_pair(patch_off, per_patch_data_offset));
3271
3272    return offs;
3273 }
3274
3275 void visit_store_ls_or_es_output(isel_context *ctx, nir_intrinsic_instr *instr)
3276 {
3277    Builder bld(ctx->program, ctx->block);
3278
3279    std::pair<Temp, unsigned> offs = get_intrinsic_io_basic_offset(ctx, instr, 4u);
3280    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
3281    unsigned write_mask = nir_intrinsic_write_mask(instr);
3282    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8u;
3283
3284    if (ctx->stage == vertex_es || ctx->stage == tess_eval_es) {
3285       /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
3286       Temp esgs_ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_ESGS_VS * 16u));
3287       Temp es2gs_offset = get_arg(ctx, ctx->args->es2gs_offset);
3288       store_vmem_mubuf(ctx, src, esgs_ring, offs.first, es2gs_offset, offs.second, elem_size_bytes, write_mask, false, true, true);
3289    } else {
3290       Temp lds_base;
3291
3292       if (ctx->stage == vertex_geometry_gs || ctx->stage == tess_eval_geometry_gs) {
3293          /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
3294          unsigned itemsize = ctx->stage == vertex_geometry_gs
3295                              ? ctx->program->info->vs.es_info.esgs_itemsize
3296                              : ctx->program->info->tes.es_info.esgs_itemsize;
3297          Temp thread_id = emit_mbcnt(ctx, bld.def(v1));
3298          Temp wave_idx = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), get_arg(ctx, ctx->args->merged_wave_info), Operand(4u << 16 | 24));
3299          Temp vertex_idx = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), thread_id,
3300                                bld.v_mul24_imm(bld.def(v1), as_vgpr(ctx, wave_idx), ctx->program->wave_size));
3301          lds_base = bld.v_mul24_imm(bld.def(v1), vertex_idx, itemsize);
3302       } else if (ctx->stage == vertex_ls || ctx->stage == vertex_tess_control_hs) {
3303          /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
3304           * GFX9+: LS is merged into HS, but still uses the same LDS layout.
3305           */
3306          unsigned num_tcs_inputs = util_last_bit64(ctx->args->shader_info->vs.ls_outputs_written);
3307          Temp vertex_idx = get_arg(ctx, ctx->args->rel_auto_id);
3308          lds_base = bld.v_mul_imm(bld.def(v1), vertex_idx, num_tcs_inputs * 16u);
3309       } else {
3310          unreachable("Invalid LS or ES stage");
3311       }
3312
3313       offs = offset_add(ctx, offs, std::make_pair(lds_base, 0u));
3314       unsigned lds_align = calculate_lds_alignment(ctx, offs.second);
3315       store_lds(ctx, elem_size_bytes, src, write_mask, offs.first, offs.second, lds_align);
3316    }
3317 }
3318
3319 bool should_write_tcs_patch_output_to_vmem(isel_context *ctx, nir_intrinsic_instr *instr)
3320 {
3321    unsigned off = nir_intrinsic_base(instr) * 4u;
3322    nir_src *off_src = nir_get_io_offset_src(instr);
3323
3324    /* Indirect offset, we can't be sure if this is a tess factor, always write to VMEM */
3325    if (!nir_src_is_const(*off_src))
3326       return true;
3327
3328    off += nir_src_as_uint(*off_src) * 16u;
3329
3330    const unsigned tess_index_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
3331    const unsigned tess_index_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
3332
3333    return (off != (tess_index_inner * 16u)) &&
3334           (off != (tess_index_outer * 16u));
3335 }
3336
3337 bool should_write_tcs_patch_output_to_lds(isel_context *ctx, nir_intrinsic_instr *instr, bool per_vertex)
3338 {
3339    unsigned off = nir_intrinsic_base(instr) * 4u;
3340    nir_src *off_src = nir_get_io_offset_src(instr);
3341
3342    /* When none of the appropriate outputs are read, we are OK to never write to LDS */
3343    if (per_vertex ? ctx->shader->info.outputs_read == 0U : ctx->shader->info.patch_outputs_read == 0u)
3344       return false;
3345
3346    /* Indirect offset, we can't be sure if this is read or not, always write to LDS */
3347    if (!nir_src_is_const(*off_src))
3348       return true;
3349
3350    off += nir_src_as_uint(*off_src) * 16u;
3351
3352    uint64_t out_rd = per_vertex
3353                      ? ctx->shader->info.outputs_read
3354                      : ctx->shader->info.patch_outputs_read;
3355    while (out_rd) {
3356       unsigned slot = u_bit_scan64(&out_rd) + (per_vertex ? 0 : VARYING_SLOT_PATCH0);
3357       if (off == shader_io_get_unique_index((gl_varying_slot) slot) * 16u)
3358          return true;
3359    }
3360
3361    return false;
3362 }
3363
3364 void visit_store_tcs_output(isel_context *ctx, nir_intrinsic_instr *instr, bool per_vertex)
3365 {
3366    assert(ctx->stage == tess_control_hs || ctx->stage == vertex_tess_control_hs);
3367    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
3368
3369    Builder bld(ctx->program, ctx->block);
3370
3371    Temp store_val = get_ssa_temp(ctx, instr->src[0].ssa);
3372    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
3373    unsigned write_mask = nir_intrinsic_write_mask(instr);
3374
3375    /* Only write to VMEM if the output is per-vertex or it's per-patch non tess factor */
3376    bool write_to_vmem = per_vertex || should_write_tcs_patch_output_to_vmem(ctx, instr);
3377    /* Only write to LDS if the output is read by the shader, or it's per-patch tess factor */
3378    bool write_to_lds = !write_to_vmem || should_write_tcs_patch_output_to_lds(ctx, instr, per_vertex);
3379
3380    if (write_to_vmem) {
3381       std::pair<Temp, unsigned> vmem_offs = per_vertex
3382                                             ? get_tcs_per_vertex_output_vmem_offset(ctx, instr)
3383                                             : get_tcs_per_patch_output_vmem_offset(ctx, instr);
3384
3385       Temp hs_ring_tess_offchip = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_HS_TESS_OFFCHIP * 16u));
3386       Temp oc_lds = get_arg(ctx, ctx->args->oc_lds);
3387       store_vmem_mubuf(ctx, store_val, hs_ring_tess_offchip, vmem_offs.first, oc_lds, vmem_offs.second, elem_size_bytes, write_mask, false, false);
3388    }
3389
3390    if (write_to_lds) {
3391       std::pair<Temp, unsigned> lds_offs = get_tcs_output_lds_offset(ctx, instr, per_vertex);
3392       unsigned lds_align = calculate_lds_alignment(ctx, lds_offs.second);
3393       store_lds(ctx, elem_size_bytes, store_val, write_mask, lds_offs.first, lds_offs.second, lds_align);
3394    }
3395 }
3396
3397 void visit_load_tcs_output(isel_context *ctx, nir_intrinsic_instr *instr, bool per_vertex)
3398 {
3399    assert(ctx->stage == tess_control_hs || ctx->stage == vertex_tess_control_hs);
3400    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
3401
3402    Builder bld(ctx->program, ctx->block);
3403
3404    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3405    std::pair<Temp, unsigned> lds_offs = get_tcs_output_lds_offset(ctx, instr, per_vertex);
3406    unsigned lds_align = calculate_lds_alignment(ctx, lds_offs.second);
3407    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
3408
3409    load_lds(ctx, elem_size_bytes, dst, lds_offs.first, lds_offs.second, lds_align);
3410 }
3411
3412 void visit_store_output(isel_context *ctx, nir_intrinsic_instr *instr)
3413 {
3414    if (ctx->stage == vertex_vs ||
3415        ctx->stage == tess_eval_vs ||
3416        ctx->stage == fragment_fs ||
3417        ctx->shader->info.stage == MESA_SHADER_GEOMETRY) {
3418       unsigned write_mask = nir_intrinsic_write_mask(instr);
3419       unsigned component = nir_intrinsic_component(instr);
3420       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
3421       unsigned idx = nir_intrinsic_base(instr) + component;
3422
3423       nir_instr *off_instr = instr->src[1].ssa->parent_instr;
3424       if (off_instr->type != nir_instr_type_load_const) {
3425          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
3426          nir_print_instr(off_instr, stderr);
3427          fprintf(stderr, "\n");
3428       }
3429       idx += nir_instr_as_load_const(off_instr)->value[0].u32 * 4u;
3430
3431       if (instr->src[0].ssa->bit_size == 64)
3432          write_mask = widen_mask(write_mask, 2);
3433
3434       for (unsigned i = 0; i < 8; ++i) {
3435          if (write_mask & (1 << i)) {
3436             ctx->outputs.mask[idx / 4u] |= 1 << (idx % 4u);
3437             ctx->outputs.outputs[idx / 4u][idx % 4u] = emit_extract_vector(ctx, src, i, v1);
3438          }
3439          idx++;
3440       }
3441    } else if (ctx->stage == vertex_es ||
3442               ctx->stage == vertex_ls ||
3443               ctx->stage == tess_eval_es ||
3444               (ctx->stage == vertex_tess_control_hs && ctx->shader->info.stage == MESA_SHADER_VERTEX) ||
3445               (ctx->stage == vertex_geometry_gs && ctx->shader->info.stage == MESA_SHADER_VERTEX) ||
3446               (ctx->stage == tess_eval_geometry_gs && ctx->shader->info.stage == MESA_SHADER_TESS_EVAL)) {
3447       visit_store_ls_or_es_output(ctx, instr);
3448    } else if (ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) {
3449       visit_store_tcs_output(ctx, instr, false);
3450    } else {
3451       unreachable("Shader stage not implemented");
3452    }
3453 }
3454
3455 void visit_load_output(isel_context *ctx, nir_intrinsic_instr *instr)
3456 {
3457    visit_load_tcs_output(ctx, instr, false);
3458 }
3459
3460 void emit_interp_instr(isel_context *ctx, unsigned idx, unsigned component, Temp src, Temp dst, Temp prim_mask)
3461 {
3462    Temp coord1 = emit_extract_vector(ctx, src, 0, v1);
3463    Temp coord2 = emit_extract_vector(ctx, src, 1, v1);
3464
3465    Builder bld(ctx->program, ctx->block);
3466    Builder::Result interp_p1 = bld.vintrp(aco_opcode::v_interp_p1_f32, bld.def(v1), coord1, bld.m0(prim_mask), idx, component);
3467    if (ctx->program->has_16bank_lds)
3468       interp_p1.instr->operands[0].setLateKill(true);
3469    bld.vintrp(aco_opcode::v_interp_p2_f32, Definition(dst), coord2, bld.m0(prim_mask), interp_p1, idx, component);
3470 }
3471
3472 void emit_load_frag_coord(isel_context *ctx, Temp dst, unsigned num_components)
3473 {
3474    aco_ptr<Pseudo_instruction> vec(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1));
3475    for (unsigned i = 0; i < num_components; i++)
3476       vec->operands[i] = Operand(get_arg(ctx, ctx->args->ac.frag_pos[i]));
3477    if (G_0286CC_POS_W_FLOAT_ENA(ctx->program->config->spi_ps_input_ena)) {
3478       assert(num_components == 4);
3479       Builder bld(ctx->program, ctx->block);
3480       vec->operands[3] = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), get_arg(ctx, ctx->args->ac.frag_pos[3]));
3481    }
3482
3483    for (Operand& op : vec->operands)
3484       op = op.isUndefined() ? Operand(0u) : op;
3485
3486    vec->definitions[0] = Definition(dst);
3487    ctx->block->instructions.emplace_back(std::move(vec));
3488    emit_split_vector(ctx, dst, num_components);
3489    return;
3490 }
3491
3492 void visit_load_interpolated_input(isel_context *ctx, nir_intrinsic_instr *instr)
3493 {
3494    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3495    Temp coords = get_ssa_temp(ctx, instr->src[0].ssa);
3496    unsigned idx = nir_intrinsic_base(instr);
3497    unsigned component = nir_intrinsic_component(instr);
3498    Temp prim_mask = get_arg(ctx, ctx->args->ac.prim_mask);
3499
3500    nir_const_value* offset = nir_src_as_const_value(instr->src[1]);
3501    if (offset) {
3502       assert(offset->u32 == 0);
3503    } else {
3504       /* the lower 15bit of the prim_mask contain the offset into LDS
3505        * while the upper bits contain the number of prims */
3506       Temp offset_src = get_ssa_temp(ctx, instr->src[1].ssa);
3507       assert(offset_src.regClass() == s1 && "TODO: divergent offsets...");
3508       Builder bld(ctx->program, ctx->block);
3509       Temp stride = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), prim_mask, Operand(16u));
3510       stride = bld.sop1(aco_opcode::s_bcnt1_i32_b32, bld.def(s1), bld.def(s1, scc), stride);
3511       stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, Operand(48u));
3512       offset_src = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, offset_src);
3513       prim_mask = bld.sop2(aco_opcode::s_add_i32, bld.def(s1, m0), bld.def(s1, scc), offset_src, prim_mask);
3514    }
3515
3516    if (instr->dest.ssa.num_components == 1) {
3517       emit_interp_instr(ctx, idx, component, coords, dst, prim_mask);
3518    } else {
3519       aco_ptr<Pseudo_instruction> vec(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.ssa.num_components, 1));
3520       for (unsigned i = 0; i < instr->dest.ssa.num_components; i++)
3521       {
3522          Temp tmp = {ctx->program->allocateId(), v1};
3523          emit_interp_instr(ctx, idx, component+i, coords, tmp, prim_mask);
3524          vec->operands[i] = Operand(tmp);
3525       }
3526       vec->definitions[0] = Definition(dst);
3527       ctx->block->instructions.emplace_back(std::move(vec));
3528    }
3529 }
3530
3531 bool check_vertex_fetch_size(isel_context *ctx, const ac_data_format_info *vtx_info,
3532                              unsigned offset, unsigned stride, unsigned channels)
3533 {
3534    unsigned vertex_byte_size = vtx_info->chan_byte_size * channels;
3535    if (vtx_info->chan_byte_size != 4 && channels == 3)
3536       return false;
3537    return (ctx->options->chip_class != GFX6 && ctx->options->chip_class != GFX10) ||
3538           (offset % vertex_byte_size == 0 && stride % vertex_byte_size == 0);
3539 }
3540
3541 uint8_t get_fetch_data_format(isel_context *ctx, const ac_data_format_info *vtx_info,
3542                               unsigned offset, unsigned stride, unsigned *channels)
3543 {
3544    if (!vtx_info->chan_byte_size) {
3545       *channels = vtx_info->num_channels;
3546       return vtx_info->chan_format;
3547    }
3548
3549    unsigned num_channels = *channels;
3550    if (!check_vertex_fetch_size(ctx, vtx_info, offset, stride, *channels)) {
3551       unsigned new_channels = num_channels + 1;
3552       /* first, assume more loads is worse and try using a larger data format */
3553       while (new_channels <= 4 && !check_vertex_fetch_size(ctx, vtx_info, offset, stride, new_channels)) {
3554          new_channels++;
3555          /* don't make the attribute potentially out-of-bounds */
3556          if (offset + new_channels * vtx_info->chan_byte_size > stride)
3557             new_channels = 5;
3558       }
3559
3560       if (new_channels == 5) {
3561          /* then try decreasing load size (at the cost of more loads) */
3562          new_channels = *channels;
3563          while (new_channels > 1 && !check_vertex_fetch_size(ctx, vtx_info, offset, stride, new_channels))
3564             new_channels--;
3565       }
3566
3567       if (new_channels < *channels)
3568          *channels = new_channels;
3569       num_channels = new_channels;
3570    }
3571
3572    switch (vtx_info->chan_format) {
3573    case V_008F0C_BUF_DATA_FORMAT_8:
3574       return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8, V_008F0C_BUF_DATA_FORMAT_8_8,
3575                          V_008F0C_BUF_DATA_FORMAT_INVALID, V_008F0C_BUF_DATA_FORMAT_8_8_8_8}[num_channels - 1];
3576    case V_008F0C_BUF_DATA_FORMAT_16:
3577       return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16, V_008F0C_BUF_DATA_FORMAT_16_16,
3578                          V_008F0C_BUF_DATA_FORMAT_INVALID, V_008F0C_BUF_DATA_FORMAT_16_16_16_16}[num_channels - 1];
3579    case V_008F0C_BUF_DATA_FORMAT_32:
3580       return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32, V_008F0C_BUF_DATA_FORMAT_32_32,
3581                          V_008F0C_BUF_DATA_FORMAT_32_32_32, V_008F0C_BUF_DATA_FORMAT_32_32_32_32}[num_channels - 1];
3582    }
3583    unreachable("shouldn't reach here");
3584    return V_008F0C_BUF_DATA_FORMAT_INVALID;
3585 }
3586
3587 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
3588  * so we may need to fix it up. */
3589 Temp adjust_vertex_fetch_alpha(isel_context *ctx, unsigned adjustment, Temp alpha)
3590 {
3591    Builder bld(ctx->program, ctx->block);
3592
3593    if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
3594       alpha = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), alpha);
3595
3596    /* For the integer-like cases, do a natural sign extension.
3597     *
3598     * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
3599     * and happen to contain 0, 1, 2, 3 as the two LSBs of the
3600     * exponent.
3601     */
3602    alpha = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(adjustment == RADV_ALPHA_ADJUST_SNORM ? 7u : 30u), alpha);
3603    alpha = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(30u), alpha);
3604
3605    /* Convert back to the right type. */
3606    if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
3607       alpha = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), alpha);
3608       Temp clamp = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0xbf800000u), alpha);
3609       alpha = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xbf800000u), alpha, clamp);
3610    } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
3611       alpha = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), alpha);
3612    }
3613
3614    return alpha;
3615 }
3616
3617 void visit_load_input(isel_context *ctx, nir_intrinsic_instr *instr)
3618 {
3619    Builder bld(ctx->program, ctx->block);
3620    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3621    if (ctx->shader->info.stage == MESA_SHADER_VERTEX) {
3622
3623       nir_instr *off_instr = instr->src[0].ssa->parent_instr;
3624       if (off_instr->type != nir_instr_type_load_const) {
3625          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
3626          nir_print_instr(off_instr, stderr);
3627          fprintf(stderr, "\n");
3628       }
3629       uint32_t offset = nir_instr_as_load_const(off_instr)->value[0].u32;
3630
3631       Temp vertex_buffers = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->vertex_buffers));
3632
3633       unsigned location = nir_intrinsic_base(instr) / 4 - VERT_ATTRIB_GENERIC0 + offset;
3634       unsigned component = nir_intrinsic_component(instr);
3635       unsigned attrib_binding = ctx->options->key.vs.vertex_attribute_bindings[location];
3636       uint32_t attrib_offset = ctx->options->key.vs.vertex_attribute_offsets[location];
3637       uint32_t attrib_stride = ctx->options->key.vs.vertex_attribute_strides[location];
3638       unsigned attrib_format = ctx->options->key.vs.vertex_attribute_formats[location];
3639
3640       unsigned dfmt = attrib_format & 0xf;
3641       unsigned nfmt = (attrib_format >> 4) & 0x7;
3642       const struct ac_data_format_info *vtx_info = ac_get_data_format_info(dfmt);
3643
3644       unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa) << component;
3645       unsigned num_channels = MIN2(util_last_bit(mask), vtx_info->num_channels);
3646       unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> (location * 2)) & 3;
3647       bool post_shuffle = ctx->options->key.vs.post_shuffle & (1 << location);
3648       if (post_shuffle)
3649          num_channels = MAX2(num_channels, 3);
3650
3651       Operand off = bld.copy(bld.def(s1), Operand(attrib_binding * 16u));
3652       Temp list = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), vertex_buffers, off);
3653
3654       Temp index;
3655       if (ctx->options->key.vs.instance_rate_inputs & (1u << location)) {
3656          uint32_t divisor = ctx->options->key.vs.instance_rate_divisors[location];
3657          Temp start_instance = get_arg(ctx, ctx->args->ac.start_instance);
3658          if (divisor) {
3659             Temp instance_id = get_arg(ctx, ctx->args->ac.instance_id);
3660             if (divisor != 1) {
3661                Temp divided = bld.tmp(v1);
3662                emit_v_div_u32(ctx, divided, as_vgpr(ctx, instance_id), divisor);
3663                index = bld.vadd32(bld.def(v1), start_instance, divided);
3664             } else {
3665                index = bld.vadd32(bld.def(v1), start_instance, instance_id);
3666             }
3667          } else {
3668             index = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), start_instance);
3669          }
3670       } else {
3671          index = bld.vadd32(bld.def(v1),
3672                             get_arg(ctx, ctx->args->ac.base_vertex),
3673                             get_arg(ctx, ctx->args->ac.vertex_id));
3674       }
3675
3676       Temp channels[num_channels];
3677       unsigned channel_start = 0;
3678       bool direct_fetch = false;
3679
3680       /* skip unused channels at the start */
3681       if (vtx_info->chan_byte_size && !post_shuffle) {
3682          channel_start = ffs(mask) - 1;
3683          for (unsigned i = 0; i < channel_start; i++)
3684             channels[i] = Temp(0, s1);
3685       } else if (vtx_info->chan_byte_size && post_shuffle && !(mask & 0x8)) {
3686          num_channels = 3 - (ffs(mask) - 1);
3687       }
3688
3689       /* load channels */
3690       while (channel_start < num_channels) {
3691          unsigned fetch_size = num_channels - channel_start;
3692          unsigned fetch_offset = attrib_offset + channel_start * vtx_info->chan_byte_size;
3693          bool expanded = false;
3694
3695          /* use MUBUF when possible to avoid possible alignment issues */
3696          /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
3697          bool use_mubuf = (nfmt == V_008F0C_BUF_NUM_FORMAT_FLOAT ||
3698                            nfmt == V_008F0C_BUF_NUM_FORMAT_UINT ||
3699                            nfmt == V_008F0C_BUF_NUM_FORMAT_SINT) &&
3700                           vtx_info->chan_byte_size == 4;
3701          unsigned fetch_dfmt = V_008F0C_BUF_DATA_FORMAT_INVALID;
3702          if (!use_mubuf) {
3703             fetch_dfmt = get_fetch_data_format(ctx, vtx_info, fetch_offset, attrib_stride, &fetch_size);
3704          } else {
3705             if (fetch_size == 3 && ctx->options->chip_class == GFX6) {
3706                /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
3707                fetch_size = 4;
3708                expanded = true;
3709             }
3710          }
3711
3712          Temp fetch_index = index;
3713          if (attrib_stride != 0 && fetch_offset > attrib_stride) {
3714             fetch_index = bld.vadd32(bld.def(v1), Operand(fetch_offset / attrib_stride), fetch_index);
3715             fetch_offset = fetch_offset % attrib_stride;
3716          }
3717
3718          Operand soffset(0u);
3719          if (fetch_offset >= 4096) {
3720             soffset = bld.copy(bld.def(s1), Operand(fetch_offset / 4096 * 4096));
3721             fetch_offset %= 4096;
3722          }
3723
3724          aco_opcode opcode;
3725          switch (fetch_size) {
3726          case 1:
3727             opcode = use_mubuf ? aco_opcode::buffer_load_dword : aco_opcode::tbuffer_load_format_x;
3728             break;
3729          case 2:
3730             opcode = use_mubuf ? aco_opcode::buffer_load_dwordx2 : aco_opcode::tbuffer_load_format_xy;
3731             break;
3732          case 3:
3733             assert(ctx->options->chip_class >= GFX7 ||
3734                    (!use_mubuf && ctx->options->chip_class == GFX6));
3735             opcode = use_mubuf ? aco_opcode::buffer_load_dwordx3 : aco_opcode::tbuffer_load_format_xyz;
3736             break;
3737          case 4:
3738             opcode = use_mubuf ? aco_opcode::buffer_load_dwordx4 : aco_opcode::tbuffer_load_format_xyzw;
3739             break;
3740          default:
3741             unreachable("Unimplemented load_input vector size");
3742          }
3743
3744          Temp fetch_dst;
3745          if (channel_start == 0 && fetch_size == dst.size() && !post_shuffle &&
3746              !expanded && (alpha_adjust == RADV_ALPHA_ADJUST_NONE ||
3747                            num_channels <= 3)) {
3748             direct_fetch = true;
3749             fetch_dst = dst;
3750          } else {
3751             fetch_dst = bld.tmp(RegType::vgpr, fetch_size);
3752          }
3753
3754          if (use_mubuf) {
3755             Instruction *mubuf = bld.mubuf(opcode,
3756                                            Definition(fetch_dst), list, fetch_index, soffset,
3757                                            fetch_offset, false, true).instr;
3758             static_cast<MUBUF_instruction*>(mubuf)->can_reorder = true;
3759          } else {
3760             Instruction *mtbuf = bld.mtbuf(opcode,
3761                                            Definition(fetch_dst), list, fetch_index, soffset,
3762                                            fetch_dfmt, nfmt, fetch_offset, false, true).instr;
3763             static_cast<MTBUF_instruction*>(mtbuf)->can_reorder = true;
3764          }
3765
3766          emit_split_vector(ctx, fetch_dst, fetch_dst.size());
3767
3768          if (fetch_size == 1) {
3769             channels[channel_start] = fetch_dst;
3770          } else {
3771             for (unsigned i = 0; i < MIN2(fetch_size, num_channels - channel_start); i++)
3772                channels[channel_start + i] = emit_extract_vector(ctx, fetch_dst, i, v1);
3773          }
3774
3775          channel_start += fetch_size;
3776       }
3777
3778       if (!direct_fetch) {
3779          bool is_float = nfmt != V_008F0C_BUF_NUM_FORMAT_UINT &&
3780                          nfmt != V_008F0C_BUF_NUM_FORMAT_SINT;
3781
3782          static const unsigned swizzle_normal[4] = {0, 1, 2, 3};
3783          static const unsigned swizzle_post_shuffle[4] = {2, 1, 0, 3};
3784          const unsigned *swizzle = post_shuffle ? swizzle_post_shuffle : swizzle_normal;
3785
3786          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
3787          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
3788          unsigned num_temp = 0;
3789          for (unsigned i = 0; i < dst.size(); i++) {
3790             unsigned idx = i + component;
3791             if (swizzle[idx] < num_channels && channels[swizzle[idx]].id()) {
3792                Temp channel = channels[swizzle[idx]];
3793                if (idx == 3 && alpha_adjust != RADV_ALPHA_ADJUST_NONE)
3794                   channel = adjust_vertex_fetch_alpha(ctx, alpha_adjust, channel);
3795                vec->operands[i] = Operand(channel);
3796
3797                num_temp++;
3798                elems[i] = channel;
3799             } else if (is_float && idx == 3) {
3800                vec->operands[i] = Operand(0x3f800000u);
3801             } else if (!is_float && idx == 3) {
3802                vec->operands[i] = Operand(1u);
3803             } else {
3804                vec->operands[i] = Operand(0u);
3805             }
3806          }
3807          vec->definitions[0] = Definition(dst);
3808          ctx->block->instructions.emplace_back(std::move(vec));
3809          emit_split_vector(ctx, dst, dst.size());
3810
3811          if (num_temp == dst.size())
3812             ctx->allocated_vec.emplace(dst.id(), elems);
3813       }
3814    } else if (ctx->shader->info.stage == MESA_SHADER_FRAGMENT) {
3815       unsigned offset_idx = instr->intrinsic == nir_intrinsic_load_input ? 0 : 1;
3816       nir_instr *off_instr = instr->src[offset_idx].ssa->parent_instr;
3817       if (off_instr->type != nir_instr_type_load_const ||
3818           nir_instr_as_load_const(off_instr)->value[0].u32 != 0) {
3819          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
3820          nir_print_instr(off_instr, stderr);
3821          fprintf(stderr, "\n");
3822       }
3823
3824       Temp prim_mask = get_arg(ctx, ctx->args->ac.prim_mask);
3825       nir_const_value* offset = nir_src_as_const_value(instr->src[offset_idx]);
3826       if (offset) {
3827          assert(offset->u32 == 0);
3828       } else {
3829          /* the lower 15bit of the prim_mask contain the offset into LDS
3830           * while the upper bits contain the number of prims */
3831          Temp offset_src = get_ssa_temp(ctx, instr->src[offset_idx].ssa);
3832          assert(offset_src.regClass() == s1 && "TODO: divergent offsets...");
3833          Builder bld(ctx->program, ctx->block);
3834          Temp stride = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), prim_mask, Operand(16u));
3835          stride = bld.sop1(aco_opcode::s_bcnt1_i32_b32, bld.def(s1), bld.def(s1, scc), stride);
3836          stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, Operand(48u));
3837          offset_src = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, offset_src);
3838          prim_mask = bld.sop2(aco_opcode::s_add_i32, bld.def(s1, m0), bld.def(s1, scc), offset_src, prim_mask);
3839       }
3840
3841       unsigned idx = nir_intrinsic_base(instr);
3842       unsigned component = nir_intrinsic_component(instr);
3843       unsigned vertex_id = 2; /* P0 */
3844
3845       if (instr->intrinsic == nir_intrinsic_load_input_vertex) {
3846          nir_const_value* src0 = nir_src_as_const_value(instr->src[0]);
3847          switch (src0->u32) {
3848          case 0:
3849             vertex_id = 2; /* P0 */
3850             break;
3851          case 1:
3852             vertex_id = 0; /* P10 */
3853             break;
3854          case 2:
3855             vertex_id = 1; /* P20 */
3856             break;
3857          default:
3858             unreachable("invalid vertex index");
3859          }
3860       }
3861
3862       if (dst.size() == 1) {
3863          bld.vintrp(aco_opcode::v_interp_mov_f32, Definition(dst), Operand(vertex_id), bld.m0(prim_mask), idx, component);
3864       } else {
3865          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
3866          for (unsigned i = 0; i < dst.size(); i++)
3867             vec->operands[i] = bld.vintrp(aco_opcode::v_interp_mov_f32, bld.def(v1), Operand(vertex_id), bld.m0(prim_mask), idx, component + i);
3868          vec->definitions[0] = Definition(dst);
3869          bld.insert(std::move(vec));
3870       }
3871
3872    } else if (ctx->shader->info.stage == MESA_SHADER_TESS_EVAL) {
3873       Temp ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_HS_TESS_OFFCHIP * 16u));
3874       Temp soffset = get_arg(ctx, ctx->args->oc_lds);
3875       std::pair<Temp, unsigned> offs = get_tcs_per_patch_output_vmem_offset(ctx, instr);
3876       unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8u;
3877
3878       load_vmem_mubuf(ctx, dst, ring, offs.first, soffset, offs.second, elem_size_bytes, instr->dest.ssa.num_components);
3879    } else {
3880       unreachable("Shader stage not implemented");
3881    }
3882 }
3883
3884 std::pair<Temp, unsigned> get_gs_per_vertex_input_offset(isel_context *ctx, nir_intrinsic_instr *instr, unsigned base_stride = 1u)
3885 {
3886    assert(ctx->shader->info.stage == MESA_SHADER_GEOMETRY);
3887
3888    Builder bld(ctx->program, ctx->block);
3889    nir_src *vertex_src = nir_get_io_vertex_index_src(instr);
3890    Temp vertex_offset;
3891
3892    if (!nir_src_is_const(*vertex_src)) {
3893       /* better code could be created, but this case probably doesn't happen
3894        * much in practice */
3895       Temp indirect_vertex = as_vgpr(ctx, get_ssa_temp(ctx, vertex_src->ssa));
3896       for (unsigned i = 0; i < ctx->shader->info.gs.vertices_in; i++) {
3897          Temp elem;
3898
3899          if (ctx->stage == vertex_geometry_gs || ctx->stage == tess_eval_geometry_gs) {
3900             elem = get_arg(ctx, ctx->args->gs_vtx_offset[i / 2u * 2u]);
3901             if (i % 2u)
3902                elem = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(16u), elem);
3903          } else {
3904             elem = get_arg(ctx, ctx->args->gs_vtx_offset[i]);
3905          }
3906
3907          if (vertex_offset.id()) {
3908             Temp cond = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.hint_vcc(bld.def(bld.lm)),
3909                                  Operand(i), indirect_vertex);
3910             vertex_offset = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), vertex_offset, elem, cond);
3911          } else {
3912             vertex_offset = elem;
3913          }
3914       }
3915
3916       if (ctx->stage == vertex_geometry_gs || ctx->stage == tess_eval_geometry_gs)
3917          vertex_offset = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0xffffu), vertex_offset);
3918    } else {
3919       unsigned vertex = nir_src_as_uint(*vertex_src);
3920       if (ctx->stage == vertex_geometry_gs || ctx->stage == tess_eval_geometry_gs)
3921          vertex_offset = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1),
3922                                   get_arg(ctx, ctx->args->gs_vtx_offset[vertex / 2u * 2u]),
3923                                   Operand((vertex % 2u) * 16u), Operand(16u));
3924       else
3925          vertex_offset = get_arg(ctx, ctx->args->gs_vtx_offset[vertex]);
3926    }
3927
3928    std::pair<Temp, unsigned> offs = get_intrinsic_io_basic_offset(ctx, instr, base_stride);
3929    offs = offset_add(ctx, offs, std::make_pair(vertex_offset, 0u));
3930    return offset_mul(ctx, offs, 4u);
3931 }
3932
3933 void visit_load_gs_per_vertex_input(isel_context *ctx, nir_intrinsic_instr *instr)
3934 {
3935    assert(ctx->shader->info.stage == MESA_SHADER_GEOMETRY);
3936
3937    Builder bld(ctx->program, ctx->block);
3938    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3939    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
3940
3941    if (ctx->stage == geometry_gs) {
3942       std::pair<Temp, unsigned> offs = get_gs_per_vertex_input_offset(ctx, instr, ctx->program->wave_size);
3943       Temp ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_ESGS_GS * 16u));
3944       load_vmem_mubuf(ctx, dst, ring, offs.first, Temp(), offs.second, elem_size_bytes, instr->dest.ssa.num_components, 4u * ctx->program->wave_size, false, true);
3945    } else if (ctx->stage == vertex_geometry_gs || ctx->stage == tess_eval_geometry_gs) {
3946       std::pair<Temp, unsigned> offs = get_gs_per_vertex_input_offset(ctx, instr);
3947       unsigned lds_align = calculate_lds_alignment(ctx, offs.second);
3948       load_lds(ctx, elem_size_bytes, dst, offs.first, offs.second, lds_align);
3949    } else {
3950       unreachable("Unsupported GS stage.");
3951    }
3952 }
3953
3954 void visit_load_tcs_per_vertex_input(isel_context *ctx, nir_intrinsic_instr *instr)
3955 {
3956    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
3957
3958    Builder bld(ctx->program, ctx->block);
3959    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3960    std::pair<Temp, unsigned> offs = get_tcs_per_vertex_input_lds_offset(ctx, instr);
3961    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
3962    unsigned lds_align = calculate_lds_alignment(ctx, offs.second);
3963
3964    load_lds(ctx, elem_size_bytes, dst, offs.first, offs.second, lds_align);
3965 }
3966
3967 void visit_load_tes_per_vertex_input(isel_context *ctx, nir_intrinsic_instr *instr)
3968 {
3969    assert(ctx->shader->info.stage == MESA_SHADER_TESS_EVAL);
3970
3971    Builder bld(ctx->program, ctx->block);
3972
3973    Temp ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_HS_TESS_OFFCHIP * 16u));
3974    Temp oc_lds = get_arg(ctx, ctx->args->oc_lds);
3975    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3976
3977    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
3978    std::pair<Temp, unsigned> offs = get_tcs_per_vertex_output_vmem_offset(ctx, instr);
3979
3980    load_vmem_mubuf(ctx, dst, ring, offs.first, oc_lds, offs.second, elem_size_bytes, instr->dest.ssa.num_components, 0u, true, true);
3981 }
3982
3983 void visit_load_per_vertex_input(isel_context *ctx, nir_intrinsic_instr *instr)
3984 {
3985    switch (ctx->shader->info.stage) {
3986    case MESA_SHADER_GEOMETRY:
3987       visit_load_gs_per_vertex_input(ctx, instr);
3988       break;
3989    case MESA_SHADER_TESS_CTRL:
3990       visit_load_tcs_per_vertex_input(ctx, instr);
3991       break;
3992    case MESA_SHADER_TESS_EVAL:
3993       visit_load_tes_per_vertex_input(ctx, instr);
3994       break;
3995    default:
3996       unreachable("Unimplemented shader stage");
3997    }
3998 }
3999
4000 void visit_load_per_vertex_output(isel_context *ctx, nir_intrinsic_instr *instr)
4001 {
4002    visit_load_tcs_output(ctx, instr, true);
4003 }
4004
4005 void visit_store_per_vertex_output(isel_context *ctx, nir_intrinsic_instr *instr)
4006 {
4007    assert(ctx->stage == tess_control_hs || ctx->stage == vertex_tess_control_hs);
4008    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
4009
4010    visit_store_tcs_output(ctx, instr, true);
4011 }
4012
4013 void visit_load_tess_coord(isel_context *ctx, nir_intrinsic_instr *instr)
4014 {
4015    assert(ctx->shader->info.stage == MESA_SHADER_TESS_EVAL);
4016
4017    Builder bld(ctx->program, ctx->block);
4018    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4019
4020    Operand tes_u(get_arg(ctx, ctx->args->tes_u));
4021    Operand tes_v(get_arg(ctx, ctx->args->tes_v));
4022    Operand tes_w(0u);
4023
4024    if (ctx->shader->info.tess.primitive_mode == GL_TRIANGLES) {
4025       Temp tmp = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), tes_u, tes_v);
4026       tmp = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), Operand(0x3f800000u /* 1.0f */), tmp);
4027       tes_w = Operand(tmp);
4028    }
4029
4030    Temp tess_coord = bld.pseudo(aco_opcode::p_create_vector, Definition(dst), tes_u, tes_v, tes_w);
4031    emit_split_vector(ctx, tess_coord, 3);
4032 }
4033
4034 Temp load_desc_ptr(isel_context *ctx, unsigned desc_set)
4035 {
4036    if (ctx->program->info->need_indirect_descriptor_sets) {
4037       Builder bld(ctx->program, ctx->block);
4038       Temp ptr64 = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->descriptor_sets[0]));
4039       Operand off = bld.copy(bld.def(s1), Operand(desc_set << 2));
4040       return bld.smem(aco_opcode::s_load_dword, bld.def(s1), ptr64, off);//, false, false, false);
4041    }
4042
4043    return get_arg(ctx, ctx->args->descriptor_sets[desc_set]);
4044 }
4045
4046
4047 void visit_load_resource(isel_context *ctx, nir_intrinsic_instr *instr)
4048 {
4049    Builder bld(ctx->program, ctx->block);
4050    Temp index = get_ssa_temp(ctx, instr->src[0].ssa);
4051    if (!ctx->divergent_vals[instr->dest.ssa.index])
4052       index = bld.as_uniform(index);
4053    unsigned desc_set = nir_intrinsic_desc_set(instr);
4054    unsigned binding = nir_intrinsic_binding(instr);
4055
4056    Temp desc_ptr;
4057    radv_pipeline_layout *pipeline_layout = ctx->options->layout;
4058    radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
4059    unsigned offset = layout->binding[binding].offset;
4060    unsigned stride;
4061    if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
4062        layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
4063       unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start + layout->binding[binding].dynamic_offset_offset;
4064       desc_ptr = get_arg(ctx, ctx->args->ac.push_constants);
4065       offset = pipeline_layout->push_constant_size + 16 * idx;
4066       stride = 16;
4067    } else {
4068       desc_ptr = load_desc_ptr(ctx, desc_set);
4069       stride = layout->binding[binding].size;
4070    }
4071
4072    nir_const_value* nir_const_index = nir_src_as_const_value(instr->src[0]);
4073    unsigned const_index = nir_const_index ? nir_const_index->u32 : 0;
4074    if (stride != 1) {
4075       if (nir_const_index) {
4076          const_index = const_index * stride;
4077       } else if (index.type() == RegType::vgpr) {
4078          bool index24bit = layout->binding[binding].array_size <= 0x1000000;
4079          index = bld.v_mul_imm(bld.def(v1), index, stride, index24bit);
4080       } else {
4081          index = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), Operand(index));
4082       }
4083    }
4084    if (offset) {
4085       if (nir_const_index) {
4086          const_index = const_index + offset;
4087       } else if (index.type() == RegType::vgpr) {
4088          index = bld.vadd32(bld.def(v1), Operand(offset), index);
4089       } else {
4090          index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset), Operand(index));
4091       }
4092    }
4093
4094    if (nir_const_index && const_index == 0) {
4095       index = desc_ptr;
4096    } else if (index.type() == RegType::vgpr) {
4097       index = bld.vadd32(bld.def(v1),
4098                          nir_const_index ? Operand(const_index) : Operand(index),
4099                          Operand(desc_ptr));
4100    } else {
4101       index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
4102                        nir_const_index ? Operand(const_index) : Operand(index),
4103                        Operand(desc_ptr));
4104    }
4105
4106    bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), index);
4107 }
4108
4109 void load_buffer(isel_context *ctx, unsigned num_components, Temp dst,
4110                  Temp rsrc, Temp offset, bool glc=false, bool readonly=true)
4111 {
4112    Builder bld(ctx->program, ctx->block);
4113
4114    unsigned num_bytes = dst.size() * 4;
4115    bool dlc = glc && ctx->options->chip_class >= GFX10;
4116
4117    aco_opcode op;
4118    if (dst.type() == RegType::vgpr || (ctx->options->chip_class < GFX8 && !readonly)) {
4119       Operand vaddr = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
4120       Operand soffset = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
4121       unsigned const_offset = 0;
4122
4123       Temp lower = Temp();
4124       if (num_bytes > 16) {
4125          assert(num_components == 3 || num_components == 4);
4126          op = aco_opcode::buffer_load_dwordx4;
4127          lower = bld.tmp(v4);
4128          aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
4129          mubuf->definitions[0] = Definition(lower);
4130          mubuf->operands[0] = Operand(rsrc);
4131          mubuf->operands[1] = vaddr;
4132          mubuf->operands[2] = soffset;
4133          mubuf->offen = (offset.type() == RegType::vgpr);
4134          mubuf->glc = glc;
4135          mubuf->dlc = dlc;
4136          mubuf->barrier = readonly ? barrier_none : barrier_buffer;
4137          mubuf->can_reorder = readonly;
4138          bld.insert(std::move(mubuf));
4139          emit_split_vector(ctx, lower, 2);
4140          num_bytes -= 16;
4141          const_offset = 16;
4142       } else if (num_bytes == 12 && ctx->options->chip_class == GFX6) {
4143          /* GFX6 doesn't support loading vec3, expand to vec4. */
4144          num_bytes = 16;
4145       }
4146
4147       switch (num_bytes) {
4148          case 4:
4149             op = aco_opcode::buffer_load_dword;
4150             break;
4151          case 8:
4152             op = aco_opcode::buffer_load_dwordx2;
4153             break;
4154          case 12:
4155             assert(ctx->options->chip_class > GFX6);
4156             op = aco_opcode::buffer_load_dwordx3;
4157             break;
4158          case 16:
4159             op = aco_opcode::buffer_load_dwordx4;
4160             break;
4161          default:
4162             unreachable("Load SSBO not implemented for this size.");
4163       }
4164       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
4165       mubuf->operands[0] = Operand(rsrc);
4166       mubuf->operands[1] = vaddr;
4167       mubuf->operands[2] = soffset;
4168       mubuf->offen = (offset.type() == RegType::vgpr);
4169       mubuf->glc = glc;
4170       mubuf->dlc = dlc;
4171       mubuf->barrier = readonly ? barrier_none : barrier_buffer;
4172       mubuf->can_reorder = readonly;
4173       mubuf->offset = const_offset;
4174       aco_ptr<Instruction> instr = std::move(mubuf);
4175
4176       if (dst.size() > 4) {
4177          assert(lower != Temp());
4178          Temp upper = bld.tmp(RegType::vgpr, dst.size() - lower.size());
4179          instr->definitions[0] = Definition(upper);
4180          bld.insert(std::move(instr));
4181          if (dst.size() == 8)
4182             emit_split_vector(ctx, upper, 2);
4183          instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size() / 2, 1));
4184          instr->operands[0] = Operand(emit_extract_vector(ctx, lower, 0, v2));
4185          instr->operands[1] = Operand(emit_extract_vector(ctx, lower, 1, v2));
4186          instr->operands[2] = Operand(emit_extract_vector(ctx, upper, 0, v2));
4187          if (dst.size() == 8)
4188             instr->operands[3] = Operand(emit_extract_vector(ctx, upper, 1, v2));
4189       } else if (dst.size() == 3 && ctx->options->chip_class == GFX6) {
4190          Temp vec = bld.tmp(v4);
4191          instr->definitions[0] = Definition(vec);
4192          bld.insert(std::move(instr));
4193          emit_split_vector(ctx, vec, 4);
4194
4195          instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, 3, 1));
4196          instr->operands[0] = Operand(emit_extract_vector(ctx, vec, 0, v1));
4197          instr->operands[1] = Operand(emit_extract_vector(ctx, vec, 1, v1));
4198          instr->operands[2] = Operand(emit_extract_vector(ctx, vec, 2, v1));
4199       }
4200
4201       if (dst.type() == RegType::sgpr) {
4202          Temp vec = bld.tmp(RegType::vgpr, dst.size());
4203          instr->definitions[0] = Definition(vec);
4204          bld.insert(std::move(instr));
4205          expand_vector(ctx, vec, dst, num_components, (1 << num_components) - 1);
4206       } else {
4207          instr->definitions[0] = Definition(dst);
4208          bld.insert(std::move(instr));
4209          emit_split_vector(ctx, dst, num_components);
4210       }
4211    } else {
4212       switch (num_bytes) {
4213          case 4:
4214             op = aco_opcode::s_buffer_load_dword;
4215             break;
4216          case 8:
4217             op = aco_opcode::s_buffer_load_dwordx2;
4218             break;
4219          case 12:
4220          case 16:
4221             op = aco_opcode::s_buffer_load_dwordx4;
4222             break;
4223          case 24:
4224          case 32:
4225             op = aco_opcode::s_buffer_load_dwordx8;
4226             break;
4227          default:
4228             unreachable("Load SSBO not implemented for this size.");
4229       }
4230       aco_ptr<SMEM_instruction> load{create_instruction<SMEM_instruction>(op, Format::SMEM, 2, 1)};
4231       load->operands[0] = Operand(rsrc);
4232       load->operands[1] = Operand(bld.as_uniform(offset));
4233       assert(load->operands[1].getTemp().type() == RegType::sgpr);
4234       load->definitions[0] = Definition(dst);
4235       load->glc = glc;
4236       load->dlc = dlc;
4237       load->barrier = readonly ? barrier_none : barrier_buffer;
4238       load->can_reorder = false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
4239       assert(ctx->options->chip_class >= GFX8 || !glc);
4240
4241       /* trim vector */
4242       if (dst.size() == 3) {
4243          Temp vec = bld.tmp(s4);
4244          load->definitions[0] = Definition(vec);
4245          bld.insert(std::move(load));
4246          emit_split_vector(ctx, vec, 4);
4247
4248          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4249                     emit_extract_vector(ctx, vec, 0, s1),
4250                     emit_extract_vector(ctx, vec, 1, s1),
4251                     emit_extract_vector(ctx, vec, 2, s1));
4252       } else if (dst.size() == 6) {
4253          Temp vec = bld.tmp(s8);
4254          load->definitions[0] = Definition(vec);
4255          bld.insert(std::move(load));
4256          emit_split_vector(ctx, vec, 4);
4257
4258          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4259                     emit_extract_vector(ctx, vec, 0, s2),
4260                     emit_extract_vector(ctx, vec, 1, s2),
4261                     emit_extract_vector(ctx, vec, 2, s2));
4262       } else {
4263          bld.insert(std::move(load));
4264       }
4265       emit_split_vector(ctx, dst, num_components);
4266    }
4267 }
4268
4269 void visit_load_ubo(isel_context *ctx, nir_intrinsic_instr *instr)
4270 {
4271    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4272    Temp rsrc = get_ssa_temp(ctx, instr->src[0].ssa);
4273
4274    Builder bld(ctx->program, ctx->block);
4275
4276    nir_intrinsic_instr* idx_instr = nir_instr_as_intrinsic(instr->src[0].ssa->parent_instr);
4277    unsigned desc_set = nir_intrinsic_desc_set(idx_instr);
4278    unsigned binding = nir_intrinsic_binding(idx_instr);
4279    radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
4280
4281    if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
4282       uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
4283                            S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
4284                            S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
4285                            S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
4286       if (ctx->options->chip_class >= GFX10) {
4287          desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
4288                       S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
4289                       S_008F0C_RESOURCE_LEVEL(1);
4290       } else {
4291          desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
4292                       S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
4293       }
4294       Temp upper_dwords = bld.pseudo(aco_opcode::p_create_vector, bld.def(s3),
4295                                      Operand(S_008F04_BASE_ADDRESS_HI(ctx->options->address32_hi)),
4296                                      Operand(0xFFFFFFFFu),
4297                                      Operand(desc_type));
4298       rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
4299                         rsrc, upper_dwords);
4300    } else {
4301       rsrc = convert_pointer_to_64_bit(ctx, rsrc);
4302       rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
4303    }
4304
4305    load_buffer(ctx, instr->num_components, dst, rsrc, get_ssa_temp(ctx, instr->src[1].ssa));
4306 }
4307
4308 void visit_load_push_constant(isel_context *ctx, nir_intrinsic_instr *instr)
4309 {
4310    Builder bld(ctx->program, ctx->block);
4311    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4312
4313    unsigned offset = nir_intrinsic_base(instr);
4314    nir_const_value *index_cv = nir_src_as_const_value(instr->src[0]);
4315    if (index_cv && instr->dest.ssa.bit_size == 32) {
4316
4317       unsigned count = instr->dest.ssa.num_components;
4318       unsigned start = (offset + index_cv->u32) / 4u;
4319       start -= ctx->args->ac.base_inline_push_consts;
4320       if (start + count <= ctx->args->ac.num_inline_push_consts) {
4321          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
4322          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
4323          for (unsigned i = 0; i < count; ++i) {
4324             elems[i] = get_arg(ctx, ctx->args->ac.inline_push_consts[start + i]);
4325             vec->operands[i] = Operand{elems[i]};
4326          }
4327          vec->definitions[0] = Definition(dst);
4328          ctx->block->instructions.emplace_back(std::move(vec));
4329          ctx->allocated_vec.emplace(dst.id(), elems);
4330          return;
4331       }
4332    }
4333
4334    Temp index = bld.as_uniform(get_ssa_temp(ctx, instr->src[0].ssa));
4335    if (offset != 0) // TODO check if index != 0 as well
4336       index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset), index);
4337    Temp ptr = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->ac.push_constants));
4338    Temp vec = dst;
4339    bool trim = false;
4340    aco_opcode op;
4341
4342    switch (dst.size()) {
4343    case 1:
4344       op = aco_opcode::s_load_dword;
4345       break;
4346    case 2:
4347       op = aco_opcode::s_load_dwordx2;
4348       break;
4349    case 3:
4350       vec = bld.tmp(s4);
4351       trim = true;
4352    case 4:
4353       op = aco_opcode::s_load_dwordx4;
4354       break;
4355    case 6:
4356       vec = bld.tmp(s8);
4357       trim = true;
4358    case 8:
4359       op = aco_opcode::s_load_dwordx8;
4360       break;
4361    default:
4362       unreachable("unimplemented or forbidden load_push_constant.");
4363    }
4364
4365    bld.smem(op, Definition(vec), ptr, index);
4366
4367    if (trim) {
4368       emit_split_vector(ctx, vec, 4);
4369       RegClass rc = dst.size() == 3 ? s1 : s2;
4370       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4371                  emit_extract_vector(ctx, vec, 0, rc),
4372                  emit_extract_vector(ctx, vec, 1, rc),
4373                  emit_extract_vector(ctx, vec, 2, rc));
4374
4375    }
4376    emit_split_vector(ctx, dst, instr->dest.ssa.num_components);
4377 }
4378
4379 void visit_load_constant(isel_context *ctx, nir_intrinsic_instr *instr)
4380 {
4381    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4382
4383    Builder bld(ctx->program, ctx->block);
4384
4385    uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
4386                         S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
4387                         S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
4388                         S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
4389    if (ctx->options->chip_class >= GFX10) {
4390       desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
4391                    S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
4392                    S_008F0C_RESOURCE_LEVEL(1);
4393    } else {
4394       desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
4395                    S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
4396    }
4397
4398    unsigned base = nir_intrinsic_base(instr);
4399    unsigned range = nir_intrinsic_range(instr);
4400
4401    Temp offset = get_ssa_temp(ctx, instr->src[0].ssa);
4402    if (base && offset.type() == RegType::sgpr)
4403       offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), offset, Operand(base));
4404    else if (base && offset.type() == RegType::vgpr)
4405       offset = bld.vadd32(bld.def(v1), Operand(base), offset);
4406
4407    Temp rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
4408                           bld.sop1(aco_opcode::p_constaddr, bld.def(s2), bld.def(s1, scc), Operand(ctx->constant_data_offset)),
4409                           Operand(MIN2(base + range, ctx->shader->constant_data_size)),
4410                           Operand(desc_type));
4411
4412    load_buffer(ctx, instr->num_components, dst, rsrc, offset);
4413 }
4414
4415 void visit_discard_if(isel_context *ctx, nir_intrinsic_instr *instr)
4416 {
4417    if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
4418       ctx->cf_info.exec_potentially_empty_discard = true;
4419
4420    ctx->program->needs_exact = true;
4421
4422    // TODO: optimize uniform conditions
4423    Builder bld(ctx->program, ctx->block);
4424    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
4425    assert(src.regClass() == bld.lm);
4426    src = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
4427    bld.pseudo(aco_opcode::p_discard_if, src);
4428    ctx->block->kind |= block_kind_uses_discard_if;
4429    return;
4430 }
4431
4432 void visit_discard(isel_context* ctx, nir_intrinsic_instr *instr)
4433 {
4434    Builder bld(ctx->program, ctx->block);
4435
4436    if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
4437       ctx->cf_info.exec_potentially_empty_discard = true;
4438
4439    bool divergent = ctx->cf_info.parent_if.is_divergent ||
4440                     ctx->cf_info.parent_loop.has_divergent_continue;
4441
4442    if (ctx->block->loop_nest_depth &&
4443        ((nir_instr_is_last(&instr->instr) && !divergent) || divergent)) {
4444       /* we handle discards the same way as jump instructions */
4445       append_logical_end(ctx->block);
4446
4447       /* in loops, discard behaves like break */
4448       Block *linear_target = ctx->cf_info.parent_loop.exit;
4449       ctx->block->kind |= block_kind_discard;
4450
4451       if (!divergent) {
4452          /* uniform discard - loop ends here */
4453          assert(nir_instr_is_last(&instr->instr));
4454          ctx->block->kind |= block_kind_uniform;
4455          ctx->cf_info.has_branch = true;
4456          bld.branch(aco_opcode::p_branch);
4457          add_linear_edge(ctx->block->index, linear_target);
4458          return;
4459       }
4460
4461       /* we add a break right behind the discard() instructions */
4462       ctx->block->kind |= block_kind_break;
4463       unsigned idx = ctx->block->index;
4464
4465       ctx->cf_info.parent_loop.has_divergent_branch = true;
4466       ctx->cf_info.nir_to_aco[instr->instr.block->index] = idx;
4467
4468       /* remove critical edges from linear CFG */
4469       bld.branch(aco_opcode::p_branch);
4470       Block* break_block = ctx->program->create_and_insert_block();
4471       break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
4472       break_block->kind |= block_kind_uniform;
4473       add_linear_edge(idx, break_block);
4474       add_linear_edge(break_block->index, linear_target);
4475       bld.reset(break_block);
4476       bld.branch(aco_opcode::p_branch);
4477
4478       Block* continue_block = ctx->program->create_and_insert_block();
4479       continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
4480       add_linear_edge(idx, continue_block);
4481       append_logical_start(continue_block);
4482       ctx->block = continue_block;
4483
4484       return;
4485    }
4486
4487    /* it can currently happen that NIR doesn't remove the unreachable code */
4488    if (!nir_instr_is_last(&instr->instr)) {
4489       ctx->program->needs_exact = true;
4490       /* save exec somewhere temporarily so that it doesn't get
4491        * overwritten before the discard from outer exec masks */
4492       Temp cond = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), Operand(0xFFFFFFFF), Operand(exec, bld.lm));
4493       bld.pseudo(aco_opcode::p_discard_if, cond);
4494       ctx->block->kind |= block_kind_uses_discard_if;
4495       return;
4496    }
4497
4498    /* This condition is incorrect for uniformly branched discards in a loop
4499     * predicated by a divergent condition, but the above code catches that case
4500     * and the discard would end up turning into a discard_if.
4501     * For example:
4502     * if (divergent) {
4503     *    while (...) {
4504     *       if (uniform) {
4505     *          discard;
4506     *       }
4507     *    }
4508     * }
4509     */
4510    if (!ctx->cf_info.parent_if.is_divergent) {
4511       /* program just ends here */
4512       ctx->block->kind |= block_kind_uniform;
4513       bld.exp(aco_opcode::exp, Operand(v1), Operand(v1), Operand(v1), Operand(v1),
4514               0 /* enabled mask */, 9 /* dest */,
4515               false /* compressed */, true/* done */, true /* valid mask */);
4516       bld.sopp(aco_opcode::s_endpgm);
4517       // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
4518    } else {
4519       ctx->block->kind |= block_kind_discard;
4520       /* branch and linear edge is added by visit_if() */
4521    }
4522 }
4523
4524 enum aco_descriptor_type {
4525    ACO_DESC_IMAGE,
4526    ACO_DESC_FMASK,
4527    ACO_DESC_SAMPLER,
4528    ACO_DESC_BUFFER,
4529    ACO_DESC_PLANE_0,
4530    ACO_DESC_PLANE_1,
4531    ACO_DESC_PLANE_2,
4532 };
4533
4534 static bool
4535 should_declare_array(isel_context *ctx, enum glsl_sampler_dim sampler_dim, bool is_array) {
4536    if (sampler_dim == GLSL_SAMPLER_DIM_BUF)
4537       return false;
4538    ac_image_dim dim = ac_get_sampler_dim(ctx->options->chip_class, sampler_dim, is_array);
4539    return dim == ac_image_cube ||
4540           dim == ac_image_1darray ||
4541           dim == ac_image_2darray ||
4542           dim == ac_image_2darraymsaa;
4543 }
4544
4545 Temp get_sampler_desc(isel_context *ctx, nir_deref_instr *deref_instr,
4546                       enum aco_descriptor_type desc_type,
4547                       const nir_tex_instr *tex_instr, bool image, bool write)
4548 {
4549 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
4550    std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
4551    if (it != ctx->tex_desc.end())
4552       return it->second;
4553 */
4554    Temp index = Temp();
4555    bool index_set = false;
4556    unsigned constant_index = 0;
4557    unsigned descriptor_set;
4558    unsigned base_index;
4559    Builder bld(ctx->program, ctx->block);
4560
4561    if (!deref_instr) {
4562       assert(tex_instr && !image);
4563       descriptor_set = 0;
4564       base_index = tex_instr->sampler_index;
4565    } else {
4566       while(deref_instr->deref_type != nir_deref_type_var) {
4567          unsigned array_size = glsl_get_aoa_size(deref_instr->type);
4568          if (!array_size)
4569             array_size = 1;
4570
4571          assert(deref_instr->deref_type == nir_deref_type_array);
4572          nir_const_value *const_value = nir_src_as_const_value(deref_instr->arr.index);
4573          if (const_value) {
4574             constant_index += array_size * const_value->u32;
4575          } else {
4576             Temp indirect = get_ssa_temp(ctx, deref_instr->arr.index.ssa);
4577             if (indirect.type() == RegType::vgpr)
4578                indirect = bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), indirect);
4579
4580             if (array_size != 1)
4581                indirect = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(array_size), indirect);
4582
4583             if (!index_set) {
4584                index = indirect;
4585                index_set = true;
4586             } else {
4587                index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), index, indirect);
4588             }
4589          }
4590
4591          deref_instr = nir_src_as_deref(deref_instr->parent);
4592       }
4593       descriptor_set = deref_instr->var->data.descriptor_set;
4594       base_index = deref_instr->var->data.binding;
4595    }
4596
4597    Temp list = load_desc_ptr(ctx, descriptor_set);
4598    list = convert_pointer_to_64_bit(ctx, list);
4599
4600    struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4601    struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4602    unsigned offset = binding->offset;
4603    unsigned stride = binding->size;
4604    aco_opcode opcode;
4605    RegClass type;
4606
4607    assert(base_index < layout->binding_count);
4608
4609    switch (desc_type) {
4610    case ACO_DESC_IMAGE:
4611       type = s8;
4612       opcode = aco_opcode::s_load_dwordx8;
4613       break;
4614    case ACO_DESC_FMASK:
4615       type = s8;
4616       opcode = aco_opcode::s_load_dwordx8;
4617       offset += 32;
4618       break;
4619    case ACO_DESC_SAMPLER:
4620       type = s4;
4621       opcode = aco_opcode::s_load_dwordx4;
4622       if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4623          offset += radv_combined_image_descriptor_sampler_offset(binding);
4624       break;
4625    case ACO_DESC_BUFFER:
4626       type = s4;
4627       opcode = aco_opcode::s_load_dwordx4;
4628       break;
4629    case ACO_DESC_PLANE_0:
4630    case ACO_DESC_PLANE_1:
4631       type = s8;
4632       opcode = aco_opcode::s_load_dwordx8;
4633       offset += 32 * (desc_type - ACO_DESC_PLANE_0);
4634       break;
4635    case ACO_DESC_PLANE_2:
4636       type = s4;
4637       opcode = aco_opcode::s_load_dwordx4;
4638       offset += 64;
4639       break;
4640    default:
4641       unreachable("invalid desc_type\n");
4642    }
4643
4644    offset += constant_index * stride;
4645
4646    if (desc_type == ACO_DESC_SAMPLER && binding->immutable_samplers_offset &&
4647       (!index_set || binding->immutable_samplers_equal)) {
4648       if (binding->immutable_samplers_equal)
4649          constant_index = 0;
4650
4651       const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4652       return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
4653                         Operand(samplers[constant_index * 4 + 0]),
4654                         Operand(samplers[constant_index * 4 + 1]),
4655                         Operand(samplers[constant_index * 4 + 2]),
4656                         Operand(samplers[constant_index * 4 + 3]));
4657    }
4658
4659    Operand off;
4660    if (!index_set) {
4661       off = bld.copy(bld.def(s1), Operand(offset));
4662    } else {
4663       off = Operand((Temp)bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset),
4664                                    bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), index)));
4665    }
4666
4667    Temp res = bld.smem(opcode, bld.def(type), list, off);
4668
4669    if (desc_type == ACO_DESC_PLANE_2) {
4670       Temp components[8];
4671       for (unsigned i = 0; i < 8; i++)
4672          components[i] = bld.tmp(s1);
4673       bld.pseudo(aco_opcode::p_split_vector,
4674                  Definition(components[0]),
4675                  Definition(components[1]),
4676                  Definition(components[2]),
4677                  Definition(components[3]),
4678                  res);
4679
4680       Temp desc2 = get_sampler_desc(ctx, deref_instr, ACO_DESC_PLANE_1, tex_instr, image, write);
4681       bld.pseudo(aco_opcode::p_split_vector,
4682                  bld.def(s1), bld.def(s1), bld.def(s1), bld.def(s1),
4683                  Definition(components[4]),
4684                  Definition(components[5]),
4685                  Definition(components[6]),
4686                  Definition(components[7]),
4687                  desc2);
4688
4689       res = bld.pseudo(aco_opcode::p_create_vector, bld.def(s8),
4690                        components[0], components[1], components[2], components[3],
4691                        components[4], components[5], components[6], components[7]);
4692    }
4693
4694    return res;
4695 }
4696
4697 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
4698 {
4699    switch (dim) {
4700    case GLSL_SAMPLER_DIM_BUF:
4701       return 1;
4702    case GLSL_SAMPLER_DIM_1D:
4703       return array ? 2 : 1;
4704    case GLSL_SAMPLER_DIM_2D:
4705       return array ? 3 : 2;
4706    case GLSL_SAMPLER_DIM_MS:
4707       return array ? 4 : 3;
4708    case GLSL_SAMPLER_DIM_3D:
4709    case GLSL_SAMPLER_DIM_CUBE:
4710       return 3;
4711    case GLSL_SAMPLER_DIM_RECT:
4712    case GLSL_SAMPLER_DIM_SUBPASS:
4713       return 2;
4714    case GLSL_SAMPLER_DIM_SUBPASS_MS:
4715       return 3;
4716    default:
4717       break;
4718    }
4719    return 0;
4720 }
4721
4722
4723 /* Adjust the sample index according to FMASK.
4724  *
4725  * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4726  * which is the identity mapping. Each nibble says which physical sample
4727  * should be fetched to get that sample.
4728  *
4729  * For example, 0x11111100 means there are only 2 samples stored and
4730  * the second sample covers 3/4 of the pixel. When reading samples 0
4731  * and 1, return physical sample 0 (determined by the first two 0s
4732  * in FMASK), otherwise return physical sample 1.
4733  *
4734  * The sample index should be adjusted as follows:
4735  *   sample_index = (fmask >> (sample_index * 4)) & 0xF;
4736  */
4737 static Temp adjust_sample_index_using_fmask(isel_context *ctx, bool da, std::vector<Temp>& coords, Operand sample_index, Temp fmask_desc_ptr)
4738 {
4739    Builder bld(ctx->program, ctx->block);
4740    Temp fmask = bld.tmp(v1);
4741    unsigned dim = ctx->options->chip_class >= GFX10
4742                   ? ac_get_sampler_dim(ctx->options->chip_class, GLSL_SAMPLER_DIM_2D, da)
4743                   : 0;
4744
4745    Temp coord = da ? bld.pseudo(aco_opcode::p_create_vector, bld.def(v3), coords[0], coords[1], coords[2]) :
4746                      bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), coords[0], coords[1]);
4747    aco_ptr<MIMG_instruction> load{create_instruction<MIMG_instruction>(aco_opcode::image_load, Format::MIMG, 3, 1)};
4748    load->operands[0] = Operand(fmask_desc_ptr);
4749    load->operands[1] = Operand(s4); /* no sampler */
4750    load->operands[2] = Operand(coord);
4751    load->definitions[0] = Definition(fmask);
4752    load->glc = false;
4753    load->dlc = false;
4754    load->dmask = 0x1;
4755    load->unrm = true;
4756    load->da = da;
4757    load->dim = dim;
4758    load->can_reorder = true; /* fmask images shouldn't be modified */
4759    ctx->block->instructions.emplace_back(std::move(load));
4760
4761    Operand sample_index4;
4762    if (sample_index.isConstant() && sample_index.constantValue() < 16) {
4763       sample_index4 = Operand(sample_index.constantValue() << 2);
4764    } else if (sample_index.regClass() == s1) {
4765       sample_index4 = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), sample_index, Operand(2u));
4766    } else {
4767       assert(sample_index.regClass() == v1);
4768       sample_index4 = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), sample_index);
4769    }
4770
4771    Temp final_sample;
4772    if (sample_index4.isConstant() && sample_index4.constantValue() == 0)
4773       final_sample = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(15u), fmask);
4774    else if (sample_index4.isConstant() && sample_index4.constantValue() == 28)
4775       final_sample = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(28u), fmask);
4776    else
4777       final_sample = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1), fmask, sample_index4, Operand(4u));
4778
4779    /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4780     * resource descriptor is 0 (invalid),
4781     */
4782    Temp compare = bld.tmp(bld.lm);
4783    bld.vopc_e64(aco_opcode::v_cmp_lg_u32, Definition(compare),
4784                 Operand(0u), emit_extract_vector(ctx, fmask_desc_ptr, 1, s1)).def(0).setHint(vcc);
4785
4786    Temp sample_index_v = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), sample_index);
4787
4788    /* Replace the MSAA sample index. */
4789    return bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), sample_index_v, final_sample, compare);
4790 }
4791
4792 static Temp get_image_coords(isel_context *ctx, const nir_intrinsic_instr *instr, const struct glsl_type *type)
4793 {
4794
4795    Temp src0 = get_ssa_temp(ctx, instr->src[1].ssa);
4796    enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4797    bool is_array = glsl_sampler_type_is_array(type);
4798    ASSERTED bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS || dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
4799    assert(!add_frag_pos && "Input attachments should be lowered.");
4800    bool is_ms = (dim == GLSL_SAMPLER_DIM_MS || dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
4801    bool gfx9_1d = ctx->options->chip_class == GFX9 && dim == GLSL_SAMPLER_DIM_1D;
4802    int count = image_type_to_components_count(dim, is_array);
4803    std::vector<Temp> coords(count);
4804    Builder bld(ctx->program, ctx->block);
4805
4806    if (is_ms) {
4807       count--;
4808       Temp src2 = get_ssa_temp(ctx, instr->src[2].ssa);
4809       /* get sample index */
4810       if (instr->intrinsic == nir_intrinsic_image_deref_load) {
4811          nir_const_value *sample_cv = nir_src_as_const_value(instr->src[2]);
4812          Operand sample_index = sample_cv ? Operand(sample_cv->u32) : Operand(emit_extract_vector(ctx, src2, 0, v1));
4813          std::vector<Temp> fmask_load_address;
4814          for (unsigned i = 0; i < (is_array ? 3 : 2); i++)
4815             fmask_load_address.emplace_back(emit_extract_vector(ctx, src0, i, v1));
4816
4817          Temp fmask_desc_ptr = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_FMASK, nullptr, false, false);
4818          coords[count] = adjust_sample_index_using_fmask(ctx, is_array, fmask_load_address, sample_index, fmask_desc_ptr);
4819       } else {
4820          coords[count] = emit_extract_vector(ctx, src2, 0, v1);
4821       }
4822    }
4823
4824    if (gfx9_1d) {
4825       coords[0] = emit_extract_vector(ctx, src0, 0, v1);
4826       coords.resize(coords.size() + 1);
4827       coords[1] = bld.copy(bld.def(v1), Operand(0u));
4828       if (is_array)
4829          coords[2] = emit_extract_vector(ctx, src0, 1, v1);
4830    } else {
4831       for (int i = 0; i < count; i++)
4832          coords[i] = emit_extract_vector(ctx, src0, i, v1);
4833    }
4834
4835    if (instr->intrinsic == nir_intrinsic_image_deref_load ||
4836        instr->intrinsic == nir_intrinsic_image_deref_store) {
4837       int lod_index = instr->intrinsic == nir_intrinsic_image_deref_load ? 3 : 4;
4838       bool level_zero = nir_src_is_const(instr->src[lod_index]) && nir_src_as_uint(instr->src[lod_index]) == 0;
4839
4840       if (!level_zero)
4841          coords.emplace_back(get_ssa_temp(ctx, instr->src[lod_index].ssa));
4842    }
4843
4844    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, coords.size(), 1)};
4845    for (unsigned i = 0; i < coords.size(); i++)
4846       vec->operands[i] = Operand(coords[i]);
4847    Temp res = {ctx->program->allocateId(), RegClass(RegType::vgpr, coords.size())};
4848    vec->definitions[0] = Definition(res);
4849    ctx->block->instructions.emplace_back(std::move(vec));
4850    return res;
4851 }
4852
4853
4854 void visit_image_load(isel_context *ctx, nir_intrinsic_instr *instr)
4855 {
4856    Builder bld(ctx->program, ctx->block);
4857    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4858    const struct glsl_type *type = glsl_without_array(var->type);
4859    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4860    bool is_array = glsl_sampler_type_is_array(type);
4861    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4862
4863    if (dim == GLSL_SAMPLER_DIM_BUF) {
4864       unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
4865       unsigned num_channels = util_last_bit(mask);
4866       Temp rsrc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4867       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4868
4869       aco_opcode opcode;
4870       switch (num_channels) {
4871       case 1:
4872          opcode = aco_opcode::buffer_load_format_x;
4873          break;
4874       case 2:
4875          opcode = aco_opcode::buffer_load_format_xy;
4876          break;
4877       case 3:
4878          opcode = aco_opcode::buffer_load_format_xyz;
4879          break;
4880       case 4:
4881          opcode = aco_opcode::buffer_load_format_xyzw;
4882          break;
4883       default:
4884          unreachable(">4 channel buffer image load");
4885       }
4886       aco_ptr<MUBUF_instruction> load{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 3, 1)};
4887       load->operands[0] = Operand(rsrc);
4888       load->operands[1] = Operand(vindex);
4889       load->operands[2] = Operand((uint32_t) 0);
4890       Temp tmp;
4891       if (num_channels == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
4892          tmp = dst;
4893       else
4894          tmp = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_channels)};
4895       load->definitions[0] = Definition(tmp);
4896       load->idxen = true;
4897       load->glc = var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT);
4898       load->dlc = load->glc && ctx->options->chip_class >= GFX10;
4899       load->barrier = barrier_image;
4900       ctx->block->instructions.emplace_back(std::move(load));
4901
4902       expand_vector(ctx, tmp, dst, instr->dest.ssa.num_components, (1 << num_channels) - 1);
4903       return;
4904    }
4905
4906    Temp coords = get_image_coords(ctx, instr, type);
4907    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
4908
4909    unsigned dmask = nir_ssa_def_components_read(&instr->dest.ssa);
4910    unsigned num_components = util_bitcount(dmask);
4911    Temp tmp;
4912    if (num_components == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
4913       tmp = dst;
4914    else
4915       tmp = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_components)};
4916
4917    bool level_zero = nir_src_is_const(instr->src[3]) && nir_src_as_uint(instr->src[3]) == 0;
4918    aco_opcode opcode = level_zero ? aco_opcode::image_load : aco_opcode::image_load_mip;
4919
4920    aco_ptr<MIMG_instruction> load{create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 1)};
4921    load->operands[0] = Operand(resource);
4922    load->operands[1] = Operand(s4); /* no sampler */
4923    load->operands[2] = Operand(coords);
4924    load->definitions[0] = Definition(tmp);
4925    load->glc = var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT) ? 1 : 0;
4926    load->dlc = load->glc && ctx->options->chip_class >= GFX10;
4927    load->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4928    load->dmask = dmask;
4929    load->unrm = true;
4930    load->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
4931    load->barrier = barrier_image;
4932    ctx->block->instructions.emplace_back(std::move(load));
4933
4934    expand_vector(ctx, tmp, dst, instr->dest.ssa.num_components, dmask);
4935    return;
4936 }
4937
4938 void visit_image_store(isel_context *ctx, nir_intrinsic_instr *instr)
4939 {
4940    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4941    const struct glsl_type *type = glsl_without_array(var->type);
4942    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4943    bool is_array = glsl_sampler_type_is_array(type);
4944    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[3].ssa));
4945
4946    bool glc = ctx->options->chip_class == GFX6 || var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE) ? 1 : 0;
4947
4948    if (dim == GLSL_SAMPLER_DIM_BUF) {
4949       Temp rsrc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4950       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4951       aco_opcode opcode;
4952       switch (data.size()) {
4953       case 1:
4954          opcode = aco_opcode::buffer_store_format_x;
4955          break;
4956       case 2:
4957          opcode = aco_opcode::buffer_store_format_xy;
4958          break;
4959       case 3:
4960          opcode = aco_opcode::buffer_store_format_xyz;
4961          break;
4962       case 4:
4963          opcode = aco_opcode::buffer_store_format_xyzw;
4964          break;
4965       default:
4966          unreachable(">4 channel buffer image store");
4967       }
4968       aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 4, 0)};
4969       store->operands[0] = Operand(rsrc);
4970       store->operands[1] = Operand(vindex);
4971       store->operands[2] = Operand((uint32_t) 0);
4972       store->operands[3] = Operand(data);
4973       store->idxen = true;
4974       store->glc = glc;
4975       store->dlc = false;
4976       store->disable_wqm = true;
4977       store->barrier = barrier_image;
4978       ctx->program->needs_exact = true;
4979       ctx->block->instructions.emplace_back(std::move(store));
4980       return;
4981    }
4982
4983    assert(data.type() == RegType::vgpr);
4984    Temp coords = get_image_coords(ctx, instr, type);
4985    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
4986
4987    bool level_zero = nir_src_is_const(instr->src[4]) && nir_src_as_uint(instr->src[4]) == 0;
4988    aco_opcode opcode = level_zero ? aco_opcode::image_store : aco_opcode::image_store_mip;
4989
4990    aco_ptr<MIMG_instruction> store{create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 0)};
4991    store->operands[0] = Operand(resource);
4992    store->operands[1] = Operand(data);
4993    store->operands[2] = Operand(coords);
4994    store->glc = glc;
4995    store->dlc = false;
4996    store->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4997    store->dmask = (1 << data.size()) - 1;
4998    store->unrm = true;
4999    store->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
5000    store->disable_wqm = true;
5001    store->barrier = barrier_image;
5002    ctx->program->needs_exact = true;
5003    ctx->block->instructions.emplace_back(std::move(store));
5004    return;
5005 }
5006
5007 void visit_image_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
5008 {
5009    /* return the previous value if dest is ever used */
5010    bool return_previous = false;
5011    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
5012       return_previous = true;
5013       break;
5014    }
5015    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
5016       return_previous = true;
5017       break;
5018    }
5019
5020    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
5021    const struct glsl_type *type = glsl_without_array(var->type);
5022    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
5023    bool is_array = glsl_sampler_type_is_array(type);
5024    Builder bld(ctx->program, ctx->block);
5025
5026    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[3].ssa));
5027    assert(data.size() == 1 && "64bit ssbo atomics not yet implemented.");
5028
5029    if (instr->intrinsic == nir_intrinsic_image_deref_atomic_comp_swap)
5030       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), get_ssa_temp(ctx, instr->src[4].ssa), data);
5031
5032    aco_opcode buf_op, image_op;
5033    switch (instr->intrinsic) {
5034       case nir_intrinsic_image_deref_atomic_add:
5035          buf_op = aco_opcode::buffer_atomic_add;
5036          image_op = aco_opcode::image_atomic_add;
5037          break;
5038       case nir_intrinsic_image_deref_atomic_umin:
5039          buf_op = aco_opcode::buffer_atomic_umin;
5040          image_op = aco_opcode::image_atomic_umin;
5041          break;
5042       case nir_intrinsic_image_deref_atomic_imin:
5043          buf_op = aco_opcode::buffer_atomic_smin;
5044          image_op = aco_opcode::image_atomic_smin;
5045          break;
5046       case nir_intrinsic_image_deref_atomic_umax:
5047          buf_op = aco_opcode::buffer_atomic_umax;
5048          image_op = aco_opcode::image_atomic_umax;
5049          break;
5050       case nir_intrinsic_image_deref_atomic_imax:
5051          buf_op = aco_opcode::buffer_atomic_smax;
5052          image_op = aco_opcode::image_atomic_smax;
5053          break;
5054       case nir_intrinsic_image_deref_atomic_and:
5055          buf_op = aco_opcode::buffer_atomic_and;
5056          image_op = aco_opcode::image_atomic_and;
5057          break;
5058       case nir_intrinsic_image_deref_atomic_or:
5059          buf_op = aco_opcode::buffer_atomic_or;
5060          image_op = aco_opcode::image_atomic_or;
5061          break;
5062       case nir_intrinsic_image_deref_atomic_xor:
5063          buf_op = aco_opcode::buffer_atomic_xor;
5064          image_op = aco_opcode::image_atomic_xor;
5065          break;
5066       case nir_intrinsic_image_deref_atomic_exchange:
5067          buf_op = aco_opcode::buffer_atomic_swap;
5068          image_op = aco_opcode::image_atomic_swap;
5069          break;
5070       case nir_intrinsic_image_deref_atomic_comp_swap:
5071          buf_op = aco_opcode::buffer_atomic_cmpswap;
5072          image_op = aco_opcode::image_atomic_cmpswap;
5073          break;
5074       default:
5075          unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5076    }
5077
5078    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5079
5080    if (dim == GLSL_SAMPLER_DIM_BUF) {
5081       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
5082       Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
5083       //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5084       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(buf_op, Format::MUBUF, 4, return_previous ? 1 : 0)};
5085       mubuf->operands[0] = Operand(resource);
5086       mubuf->operands[1] = Operand(vindex);
5087       mubuf->operands[2] = Operand((uint32_t)0);
5088       mubuf->operands[3] = Operand(data);
5089       if (return_previous)
5090          mubuf->definitions[0] = Definition(dst);
5091       mubuf->offset = 0;
5092       mubuf->idxen = true;
5093       mubuf->glc = return_previous;
5094       mubuf->dlc = false; /* Not needed for atomics */
5095       mubuf->disable_wqm = true;
5096       mubuf->barrier = barrier_image;
5097       ctx->program->needs_exact = true;
5098       ctx->block->instructions.emplace_back(std::move(mubuf));
5099       return;
5100    }
5101
5102    Temp coords = get_image_coords(ctx, instr, type);
5103    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
5104    aco_ptr<MIMG_instruction> mimg{create_instruction<MIMG_instruction>(image_op, Format::MIMG, 3, return_previous ? 1 : 0)};
5105    mimg->operands[0] = Operand(resource);
5106    mimg->operands[1] = Operand(data);
5107    mimg->operands[2] = Operand(coords);
5108    if (return_previous)
5109       mimg->definitions[0] = Definition(dst);
5110    mimg->glc = return_previous;
5111    mimg->dlc = false; /* Not needed for atomics */
5112    mimg->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
5113    mimg->dmask = (1 << data.size()) - 1;
5114    mimg->unrm = true;
5115    mimg->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
5116    mimg->disable_wqm = true;
5117    mimg->barrier = barrier_image;
5118    ctx->program->needs_exact = true;
5119    ctx->block->instructions.emplace_back(std::move(mimg));
5120    return;
5121 }
5122
5123 void get_buffer_size(isel_context *ctx, Temp desc, Temp dst, bool in_elements)
5124 {
5125    if (in_elements && ctx->options->chip_class == GFX8) {
5126       /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
5127       Builder bld(ctx->program, ctx->block);
5128
5129       Temp size = emit_extract_vector(ctx, desc, 2, s1);
5130
5131       Temp size_div3 = bld.vop3(aco_opcode::v_mul_hi_u32, bld.def(v1), bld.copy(bld.def(v1), Operand(0xaaaaaaabu)), size);
5132       size_div3 = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.as_uniform(size_div3), Operand(1u));
5133
5134       Temp stride = emit_extract_vector(ctx, desc, 1, s1);
5135       stride = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), stride, Operand((5u << 16) | 16u));
5136
5137       Temp is12 = bld.sopc(aco_opcode::s_cmp_eq_i32, bld.def(s1, scc), stride, Operand(12u));
5138       size = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), size_div3, size, bld.scc(is12));
5139
5140       Temp shr_dst = dst.type() == RegType::vgpr ? bld.tmp(s1) : dst;
5141       bld.sop2(aco_opcode::s_lshr_b32, Definition(shr_dst), bld.def(s1, scc),
5142                size, bld.sop1(aco_opcode::s_ff1_i32_b32, bld.def(s1), stride));
5143       if (dst.type() == RegType::vgpr)
5144          bld.copy(Definition(dst), shr_dst);
5145
5146       /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
5147    } else {
5148       emit_extract_vector(ctx, desc, 2, dst);
5149    }
5150 }
5151
5152 void visit_image_size(isel_context *ctx, nir_intrinsic_instr *instr)
5153 {
5154    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
5155    const struct glsl_type *type = glsl_without_array(var->type);
5156    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
5157    bool is_array = glsl_sampler_type_is_array(type);
5158    Builder bld(ctx->program, ctx->block);
5159
5160    if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
5161       Temp desc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, NULL, true, false);
5162       return get_buffer_size(ctx, desc, get_ssa_temp(ctx, &instr->dest.ssa), true);
5163    }
5164
5165    /* LOD */
5166    Temp lod = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
5167
5168    /* Resource */
5169    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, NULL, true, false);
5170
5171    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5172
5173    aco_ptr<MIMG_instruction> mimg{create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 3, 1)};
5174    mimg->operands[0] = Operand(resource);
5175    mimg->operands[1] = Operand(s4); /* no sampler */
5176    mimg->operands[2] = Operand(lod);
5177    uint8_t& dmask = mimg->dmask;
5178    mimg->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
5179    mimg->dmask = (1 << instr->dest.ssa.num_components) - 1;
5180    mimg->da = glsl_sampler_type_is_array(type);
5181    mimg->can_reorder = true;
5182    Definition& def = mimg->definitions[0];
5183    ctx->block->instructions.emplace_back(std::move(mimg));
5184
5185    if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
5186        glsl_sampler_type_is_array(type)) {
5187
5188       assert(instr->dest.ssa.num_components == 3);
5189       Temp tmp = {ctx->program->allocateId(), v3};
5190       def = Definition(tmp);
5191       emit_split_vector(ctx, tmp, 3);
5192
5193       /* divide 3rd value by 6 by multiplying with magic number */
5194       Temp c = bld.copy(bld.def(s1), Operand((uint32_t) 0x2AAAAAAB));
5195       Temp by_6 = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), emit_extract_vector(ctx, tmp, 2, v1), c);
5196
5197       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
5198                  emit_extract_vector(ctx, tmp, 0, v1),
5199                  emit_extract_vector(ctx, tmp, 1, v1),
5200                  by_6);
5201
5202    } else if (ctx->options->chip_class == GFX9 &&
5203               glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
5204               glsl_sampler_type_is_array(type)) {
5205       assert(instr->dest.ssa.num_components == 2);
5206       def = Definition(dst);
5207       dmask = 0x5;
5208    } else {
5209       def = Definition(dst);
5210    }
5211
5212    emit_split_vector(ctx, dst, instr->dest.ssa.num_components);
5213 }
5214
5215 void visit_load_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
5216 {
5217    Builder bld(ctx->program, ctx->block);
5218    unsigned num_components = instr->num_components;
5219
5220    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5221    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5222    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
5223
5224    bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT);
5225    load_buffer(ctx, num_components, dst, rsrc, get_ssa_temp(ctx, instr->src[1].ssa), glc, false);
5226 }
5227
5228 void visit_store_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
5229 {
5230    Builder bld(ctx->program, ctx->block);
5231    Temp data = get_ssa_temp(ctx, instr->src[0].ssa);
5232    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
5233    unsigned writemask = nir_intrinsic_write_mask(instr);
5234    Temp offset = get_ssa_temp(ctx, instr->src[2].ssa);
5235
5236    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5237    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
5238
5239    bool smem = !ctx->divergent_vals[instr->src[2].ssa->index] &&
5240                ctx->options->chip_class >= GFX8;
5241    if (smem)
5242       offset = bld.as_uniform(offset);
5243    bool smem_nonfs = smem && ctx->stage != fragment_fs;
5244
5245    while (writemask) {
5246       int start, count;
5247       u_bit_scan_consecutive_range(&writemask, &start, &count);
5248       if (count == 3 && (smem || ctx->options->chip_class == GFX6)) {
5249          /* GFX6 doesn't support storing vec3, split it. */
5250          writemask |= 1u << (start + 2);
5251          count = 2;
5252       }
5253       int num_bytes = count * elem_size_bytes;
5254
5255       if (num_bytes > 16) {
5256          assert(elem_size_bytes == 8);
5257          writemask |= (((count - 2) << 1) - 1) << (start + 2);
5258          count = 2;
5259          num_bytes = 16;
5260       }
5261
5262       // TODO: check alignment of sub-dword stores
5263       // TODO: split 3 bytes. there is no store instruction for that
5264
5265       Temp write_data;
5266       if (count != instr->num_components) {
5267          emit_split_vector(ctx, data, instr->num_components);
5268          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
5269          for (int i = 0; i < count; i++) {
5270             Temp elem = emit_extract_vector(ctx, data, start + i, RegClass(data.type(), elem_size_bytes / 4));
5271             vec->operands[i] = Operand(smem_nonfs ? bld.as_uniform(elem) : elem);
5272          }
5273          write_data = bld.tmp(!smem ? RegType::vgpr : smem_nonfs ? RegType::sgpr : data.type(), count * elem_size_bytes / 4);
5274          vec->definitions[0] = Definition(write_data);
5275          ctx->block->instructions.emplace_back(std::move(vec));
5276       } else if (!smem && data.type() != RegType::vgpr) {
5277          assert(num_bytes % 4 == 0);
5278          write_data = bld.copy(bld.def(RegType::vgpr, num_bytes / 4), data);
5279       } else if (smem_nonfs && data.type() == RegType::vgpr) {
5280          assert(num_bytes % 4 == 0);
5281          write_data = bld.as_uniform(data);
5282       } else {
5283          write_data = data;
5284       }
5285
5286       aco_opcode vmem_op, smem_op;
5287       switch (num_bytes) {
5288          case 4:
5289             vmem_op = aco_opcode::buffer_store_dword;
5290             smem_op = aco_opcode::s_buffer_store_dword;
5291             break;
5292          case 8:
5293             vmem_op = aco_opcode::buffer_store_dwordx2;
5294             smem_op = aco_opcode::s_buffer_store_dwordx2;
5295             break;
5296          case 12:
5297             vmem_op = aco_opcode::buffer_store_dwordx3;
5298             smem_op = aco_opcode::last_opcode;
5299             assert(!smem && ctx->options->chip_class > GFX6);
5300             break;
5301          case 16:
5302             vmem_op = aco_opcode::buffer_store_dwordx4;
5303             smem_op = aco_opcode::s_buffer_store_dwordx4;
5304             break;
5305          default:
5306             unreachable("Store SSBO not implemented for this size.");
5307       }
5308       if (ctx->stage == fragment_fs)
5309          smem_op = aco_opcode::p_fs_buffer_store_smem;
5310
5311       if (smem) {
5312          aco_ptr<SMEM_instruction> store{create_instruction<SMEM_instruction>(smem_op, Format::SMEM, 3, 0)};
5313          store->operands[0] = Operand(rsrc);
5314          if (start) {
5315             Temp off = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
5316                                 offset, Operand(start * elem_size_bytes));
5317             store->operands[1] = Operand(off);
5318          } else {
5319             store->operands[1] = Operand(offset);
5320          }
5321          if (smem_op != aco_opcode::p_fs_buffer_store_smem)
5322             store->operands[1].setFixed(m0);
5323          store->operands[2] = Operand(write_data);
5324          store->glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
5325          store->dlc = false;
5326          store->disable_wqm = true;
5327          store->barrier = barrier_buffer;
5328          ctx->block->instructions.emplace_back(std::move(store));
5329          ctx->program->wb_smem_l1_on_end = true;
5330          if (smem_op == aco_opcode::p_fs_buffer_store_smem) {
5331             ctx->block->kind |= block_kind_needs_lowering;
5332             ctx->program->needs_exact = true;
5333          }
5334       } else {
5335          aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(vmem_op, Format::MUBUF, 4, 0)};
5336          store->operands[0] = Operand(rsrc);
5337          store->operands[1] = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
5338          store->operands[2] = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
5339          store->operands[3] = Operand(write_data);
5340          store->offset = start * elem_size_bytes;
5341          store->offen = (offset.type() == RegType::vgpr);
5342          store->glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
5343          store->dlc = false;
5344          store->disable_wqm = true;
5345          store->barrier = barrier_buffer;
5346          ctx->program->needs_exact = true;
5347          ctx->block->instructions.emplace_back(std::move(store));
5348       }
5349    }
5350 }
5351
5352 void visit_atomic_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
5353 {
5354    /* return the previous value if dest is ever used */
5355    bool return_previous = false;
5356    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
5357       return_previous = true;
5358       break;
5359    }
5360    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
5361       return_previous = true;
5362       break;
5363    }
5364
5365    Builder bld(ctx->program, ctx->block);
5366    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[2].ssa));
5367
5368    if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap)
5369       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(RegType::vgpr, data.size() * 2),
5370                         get_ssa_temp(ctx, instr->src[3].ssa), data);
5371
5372    Temp offset = get_ssa_temp(ctx, instr->src[1].ssa);
5373    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5374    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
5375
5376    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5377
5378    aco_opcode op32, op64;
5379    switch (instr->intrinsic) {
5380       case nir_intrinsic_ssbo_atomic_add:
5381          op32 = aco_opcode::buffer_atomic_add;
5382          op64 = aco_opcode::buffer_atomic_add_x2;
5383          break;
5384       case nir_intrinsic_ssbo_atomic_imin:
5385          op32 = aco_opcode::buffer_atomic_smin;
5386          op64 = aco_opcode::buffer_atomic_smin_x2;
5387          break;
5388       case nir_intrinsic_ssbo_atomic_umin:
5389          op32 = aco_opcode::buffer_atomic_umin;
5390          op64 = aco_opcode::buffer_atomic_umin_x2;
5391          break;
5392       case nir_intrinsic_ssbo_atomic_imax:
5393          op32 = aco_opcode::buffer_atomic_smax;
5394          op64 = aco_opcode::buffer_atomic_smax_x2;
5395          break;
5396       case nir_intrinsic_ssbo_atomic_umax:
5397          op32 = aco_opcode::buffer_atomic_umax;
5398          op64 = aco_opcode::buffer_atomic_umax_x2;
5399          break;
5400       case nir_intrinsic_ssbo_atomic_and:
5401          op32 = aco_opcode::buffer_atomic_and;
5402          op64 = aco_opcode::buffer_atomic_and_x2;
5403          break;
5404       case nir_intrinsic_ssbo_atomic_or:
5405          op32 = aco_opcode::buffer_atomic_or;
5406          op64 = aco_opcode::buffer_atomic_or_x2;
5407          break;
5408       case nir_intrinsic_ssbo_atomic_xor:
5409          op32 = aco_opcode::buffer_atomic_xor;
5410          op64 = aco_opcode::buffer_atomic_xor_x2;
5411          break;
5412       case nir_intrinsic_ssbo_atomic_exchange:
5413          op32 = aco_opcode::buffer_atomic_swap;
5414          op64 = aco_opcode::buffer_atomic_swap_x2;
5415          break;
5416       case nir_intrinsic_ssbo_atomic_comp_swap:
5417          op32 = aco_opcode::buffer_atomic_cmpswap;
5418          op64 = aco_opcode::buffer_atomic_cmpswap_x2;
5419          break;
5420       default:
5421          unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
5422    }
5423    aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
5424    aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, return_previous ? 1 : 0)};
5425    mubuf->operands[0] = Operand(rsrc);
5426    mubuf->operands[1] = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
5427    mubuf->operands[2] = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
5428    mubuf->operands[3] = Operand(data);
5429    if (return_previous)
5430       mubuf->definitions[0] = Definition(dst);
5431    mubuf->offset = 0;
5432    mubuf->offen = (offset.type() == RegType::vgpr);
5433    mubuf->glc = return_previous;
5434    mubuf->dlc = false; /* Not needed for atomics */
5435    mubuf->disable_wqm = true;
5436    mubuf->barrier = barrier_buffer;
5437    ctx->program->needs_exact = true;
5438    ctx->block->instructions.emplace_back(std::move(mubuf));
5439 }
5440
5441 void visit_get_buffer_size(isel_context *ctx, nir_intrinsic_instr *instr) {
5442
5443    Temp index = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5444    Builder bld(ctx->program, ctx->block);
5445    Temp desc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), index, Operand(0u));
5446    get_buffer_size(ctx, desc, get_ssa_temp(ctx, &instr->dest.ssa), false);
5447 }
5448
5449 Temp get_gfx6_global_rsrc(Builder& bld, Temp addr)
5450 {
5451    uint32_t rsrc_conf = S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5452                         S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
5453
5454    if (addr.type() == RegType::vgpr)
5455       return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf));
5456    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), addr, Operand(-1u), Operand(rsrc_conf));
5457 }
5458
5459 void visit_load_global(isel_context *ctx, nir_intrinsic_instr *instr)
5460 {
5461    Builder bld(ctx->program, ctx->block);
5462    unsigned num_components = instr->num_components;
5463    unsigned num_bytes = num_components * instr->dest.ssa.bit_size / 8;
5464
5465    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5466    Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
5467
5468    bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT);
5469    bool dlc = glc && ctx->options->chip_class >= GFX10;
5470    aco_opcode op;
5471    if (dst.type() == RegType::vgpr || (glc && ctx->options->chip_class < GFX8)) {
5472       bool global = ctx->options->chip_class >= GFX9;
5473
5474       if (ctx->options->chip_class >= GFX7) {
5475          aco_opcode op;
5476          switch (num_bytes) {
5477          case 4:
5478             op = global ? aco_opcode::global_load_dword : aco_opcode::flat_load_dword;
5479             break;
5480          case 8:
5481             op = global ? aco_opcode::global_load_dwordx2 : aco_opcode::flat_load_dwordx2;
5482             break;
5483          case 12:
5484             op = global ? aco_opcode::global_load_dwordx3 : aco_opcode::flat_load_dwordx3;
5485             break;
5486          case 16:
5487             op = global ? aco_opcode::global_load_dwordx4 : aco_opcode::flat_load_dwordx4;
5488             break;
5489          default:
5490             unreachable("load_global not implemented for this size.");
5491          }
5492
5493          aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 2, 1)};
5494          flat->operands[0] = Operand(addr);
5495          flat->operands[1] = Operand(s1);
5496          flat->glc = glc;
5497          flat->dlc = dlc;
5498          flat->barrier = barrier_buffer;
5499
5500          if (dst.type() == RegType::sgpr) {
5501             Temp vec = bld.tmp(RegType::vgpr, dst.size());
5502             flat->definitions[0] = Definition(vec);
5503             ctx->block->instructions.emplace_back(std::move(flat));
5504             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec);
5505          } else {
5506             flat->definitions[0] = Definition(dst);
5507             ctx->block->instructions.emplace_back(std::move(flat));
5508          }
5509          emit_split_vector(ctx, dst, num_components);
5510       } else {
5511          assert(ctx->options->chip_class == GFX6);
5512
5513          /* GFX6 doesn't support loading vec3, expand to vec4. */
5514          num_bytes = num_bytes == 12 ? 16 : num_bytes;
5515
5516          aco_opcode op;
5517          switch (num_bytes) {
5518          case 4:
5519             op = aco_opcode::buffer_load_dword;
5520             break;
5521          case 8:
5522             op = aco_opcode::buffer_load_dwordx2;
5523             break;
5524          case 16:
5525             op = aco_opcode::buffer_load_dwordx4;
5526             break;
5527          default:
5528             unreachable("load_global not implemented for this size.");
5529          }
5530
5531          Temp rsrc = get_gfx6_global_rsrc(bld, addr);
5532
5533          aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
5534          mubuf->operands[0] = Operand(rsrc);
5535          mubuf->operands[1] = addr.type() == RegType::vgpr ? Operand(addr) : Operand(v1);
5536          mubuf->operands[2] = Operand(0u);
5537          mubuf->glc = glc;
5538          mubuf->dlc = false;
5539          mubuf->offset = 0;
5540          mubuf->addr64 = addr.type() == RegType::vgpr;
5541          mubuf->disable_wqm = false;
5542          mubuf->barrier = barrier_buffer;
5543          aco_ptr<Instruction> instr = std::move(mubuf);
5544
5545          /* expand vector */
5546          if (dst.size() == 3) {
5547             Temp vec = bld.tmp(v4);
5548             instr->definitions[0] = Definition(vec);
5549             bld.insert(std::move(instr));
5550             emit_split_vector(ctx, vec, 4);
5551
5552             instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, 3, 1));
5553             instr->operands[0] = Operand(emit_extract_vector(ctx, vec, 0, v1));
5554             instr->operands[1] = Operand(emit_extract_vector(ctx, vec, 1, v1));
5555             instr->operands[2] = Operand(emit_extract_vector(ctx, vec, 2, v1));
5556          }
5557
5558          if (dst.type() == RegType::sgpr) {
5559             Temp vec = bld.tmp(RegType::vgpr, dst.size());
5560             instr->definitions[0] = Definition(vec);
5561             bld.insert(std::move(instr));
5562             expand_vector(ctx, vec, dst, num_components, (1 << num_components) - 1);
5563             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec);
5564          } else {
5565             instr->definitions[0] = Definition(dst);
5566             bld.insert(std::move(instr));
5567             emit_split_vector(ctx, dst, num_components);
5568          }
5569       }
5570    } else {
5571       switch (num_bytes) {
5572          case 4:
5573             op = aco_opcode::s_load_dword;
5574             break;
5575          case 8:
5576             op = aco_opcode::s_load_dwordx2;
5577             break;
5578          case 12:
5579          case 16:
5580             op = aco_opcode::s_load_dwordx4;
5581             break;
5582          default:
5583             unreachable("load_global not implemented for this size.");
5584       }
5585       aco_ptr<SMEM_instruction> load{create_instruction<SMEM_instruction>(op, Format::SMEM, 2, 1)};
5586       load->operands[0] = Operand(addr);
5587       load->operands[1] = Operand(0u);
5588       load->definitions[0] = Definition(dst);
5589       load->glc = glc;
5590       load->dlc = dlc;
5591       load->barrier = barrier_buffer;
5592       assert(ctx->options->chip_class >= GFX8 || !glc);
5593
5594       if (dst.size() == 3) {
5595          /* trim vector */
5596          Temp vec = bld.tmp(s4);
5597          load->definitions[0] = Definition(vec);
5598          ctx->block->instructions.emplace_back(std::move(load));
5599          emit_split_vector(ctx, vec, 4);
5600
5601          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
5602                     emit_extract_vector(ctx, vec, 0, s1),
5603                     emit_extract_vector(ctx, vec, 1, s1),
5604                     emit_extract_vector(ctx, vec, 2, s1));
5605       } else {
5606          ctx->block->instructions.emplace_back(std::move(load));
5607       }
5608    }
5609 }
5610
5611 void visit_store_global(isel_context *ctx, nir_intrinsic_instr *instr)
5612 {
5613    Builder bld(ctx->program, ctx->block);
5614    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
5615
5616    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5617    Temp addr = get_ssa_temp(ctx, instr->src[1].ssa);
5618
5619    if (ctx->options->chip_class >= GFX7)
5620       addr = as_vgpr(ctx, addr);
5621
5622    unsigned writemask = nir_intrinsic_write_mask(instr);
5623    while (writemask) {
5624       int start, count;
5625       u_bit_scan_consecutive_range(&writemask, &start, &count);
5626       if (count == 3 && ctx->options->chip_class == GFX6) {
5627          /* GFX6 doesn't support storing vec3, split it. */
5628          writemask |= 1u << (start + 2);
5629          count = 2;
5630       }
5631       unsigned num_bytes = count * elem_size_bytes;
5632
5633       Temp write_data = data;
5634       if (count != instr->num_components) {
5635          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
5636          for (int i = 0; i < count; i++)
5637             vec->operands[i] = Operand(emit_extract_vector(ctx, data, start + i, v1));
5638          write_data = bld.tmp(RegType::vgpr, count);
5639          vec->definitions[0] = Definition(write_data);
5640          ctx->block->instructions.emplace_back(std::move(vec));
5641       }
5642
5643       bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
5644       unsigned offset = start * elem_size_bytes;
5645
5646       if (ctx->options->chip_class >= GFX7) {
5647          if (offset > 0 && ctx->options->chip_class < GFX9) {
5648             Temp addr0 = bld.tmp(v1), addr1 = bld.tmp(v1);
5649             Temp new_addr0 = bld.tmp(v1), new_addr1 = bld.tmp(v1);
5650             Temp carry = bld.tmp(bld.lm);
5651             bld.pseudo(aco_opcode::p_split_vector, Definition(addr0), Definition(addr1), addr);
5652
5653             bld.vop2(aco_opcode::v_add_co_u32, Definition(new_addr0), bld.hint_vcc(Definition(carry)),
5654                      Operand(offset), addr0);
5655             bld.vop2(aco_opcode::v_addc_co_u32, Definition(new_addr1), bld.def(bld.lm),
5656                      Operand(0u), addr1,
5657                      carry).def(1).setHint(vcc);
5658
5659             addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), new_addr0, new_addr1);
5660
5661             offset = 0;
5662          }
5663
5664          bool global = ctx->options->chip_class >= GFX9;
5665          aco_opcode op;
5666          switch (num_bytes) {
5667          case 4:
5668             op = global ? aco_opcode::global_store_dword : aco_opcode::flat_store_dword;
5669             break;
5670          case 8:
5671             op = global ? aco_opcode::global_store_dwordx2 : aco_opcode::flat_store_dwordx2;
5672             break;
5673          case 12:
5674             op = global ? aco_opcode::global_store_dwordx3 : aco_opcode::flat_store_dwordx3;
5675             break;
5676          case 16:
5677             op = global ? aco_opcode::global_store_dwordx4 : aco_opcode::flat_store_dwordx4;
5678             break;
5679          default:
5680             unreachable("store_global not implemented for this size.");
5681          }
5682
5683          aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 3, 0)};
5684          flat->operands[0] = Operand(addr);
5685          flat->operands[1] = Operand(s1);
5686          flat->operands[2] = Operand(data);
5687          flat->glc = glc;
5688          flat->dlc = false;
5689          flat->offset = offset;
5690          flat->disable_wqm = true;
5691          flat->barrier = barrier_buffer;
5692          ctx->program->needs_exact = true;
5693          ctx->block->instructions.emplace_back(std::move(flat));
5694       } else {
5695          assert(ctx->options->chip_class == GFX6);
5696
5697          aco_opcode op;
5698          switch (num_bytes) {
5699          case 4:
5700             op = aco_opcode::buffer_store_dword;
5701             break;
5702          case 8:
5703             op = aco_opcode::buffer_store_dwordx2;
5704             break;
5705          case 16:
5706             op = aco_opcode::buffer_store_dwordx4;
5707             break;
5708          default:
5709             unreachable("store_global not implemented for this size.");
5710          }
5711
5712          Temp rsrc = get_gfx6_global_rsrc(bld, addr);
5713
5714          aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, 0)};
5715          mubuf->operands[0] = Operand(rsrc);
5716          mubuf->operands[1] = addr.type() == RegType::vgpr ? Operand(addr) : Operand(v1);
5717          mubuf->operands[2] = Operand(0u);
5718          mubuf->operands[3] = Operand(write_data);
5719          mubuf->glc = glc;
5720          mubuf->dlc = false;
5721          mubuf->offset = offset;
5722          mubuf->addr64 = addr.type() == RegType::vgpr;
5723          mubuf->disable_wqm = true;
5724          mubuf->barrier = barrier_buffer;
5725          ctx->program->needs_exact = true;
5726          ctx->block->instructions.emplace_back(std::move(mubuf));
5727       }
5728    }
5729 }
5730
5731 void visit_global_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
5732 {
5733    /* return the previous value if dest is ever used */
5734    bool return_previous = false;
5735    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
5736       return_previous = true;
5737       break;
5738    }
5739    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
5740       return_previous = true;
5741       break;
5742    }
5743
5744    Builder bld(ctx->program, ctx->block);
5745    Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
5746    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5747
5748    if (ctx->options->chip_class >= GFX7)
5749       addr = as_vgpr(ctx, addr);
5750
5751    if (instr->intrinsic == nir_intrinsic_global_atomic_comp_swap)
5752       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(RegType::vgpr, data.size() * 2),
5753                         get_ssa_temp(ctx, instr->src[2].ssa), data);
5754
5755    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5756
5757    aco_opcode op32, op64;
5758
5759    if (ctx->options->chip_class >= GFX7) {
5760       bool global = ctx->options->chip_class >= GFX9;
5761       switch (instr->intrinsic) {
5762          case nir_intrinsic_global_atomic_add:
5763             op32 = global ? aco_opcode::global_atomic_add : aco_opcode::flat_atomic_add;
5764             op64 = global ? aco_opcode::global_atomic_add_x2 : aco_opcode::flat_atomic_add_x2;
5765             break;
5766          case nir_intrinsic_global_atomic_imin:
5767             op32 = global ? aco_opcode::global_atomic_smin : aco_opcode::flat_atomic_smin;
5768             op64 = global ? aco_opcode::global_atomic_smin_x2 : aco_opcode::flat_atomic_smin_x2;
5769             break;
5770          case nir_intrinsic_global_atomic_umin:
5771             op32 = global ? aco_opcode::global_atomic_umin : aco_opcode::flat_atomic_umin;
5772             op64 = global ? aco_opcode::global_atomic_umin_x2 : aco_opcode::flat_atomic_umin_x2;
5773             break;
5774          case nir_intrinsic_global_atomic_imax:
5775             op32 = global ? aco_opcode::global_atomic_smax : aco_opcode::flat_atomic_smax;
5776             op64 = global ? aco_opcode::global_atomic_smax_x2 : aco_opcode::flat_atomic_smax_x2;
5777             break;
5778          case nir_intrinsic_global_atomic_umax:
5779             op32 = global ? aco_opcode::global_atomic_umax : aco_opcode::flat_atomic_umax;
5780             op64 = global ? aco_opcode::global_atomic_umax_x2 : aco_opcode::flat_atomic_umax_x2;
5781             break;
5782          case nir_intrinsic_global_atomic_and:
5783             op32 = global ? aco_opcode::global_atomic_and : aco_opcode::flat_atomic_and;
5784             op64 = global ? aco_opcode::global_atomic_and_x2 : aco_opcode::flat_atomic_and_x2;
5785             break;
5786          case nir_intrinsic_global_atomic_or:
5787             op32 = global ? aco_opcode::global_atomic_or : aco_opcode::flat_atomic_or;
5788             op64 = global ? aco_opcode::global_atomic_or_x2 : aco_opcode::flat_atomic_or_x2;
5789             break;
5790          case nir_intrinsic_global_atomic_xor:
5791             op32 = global ? aco_opcode::global_atomic_xor : aco_opcode::flat_atomic_xor;
5792             op64 = global ? aco_opcode::global_atomic_xor_x2 : aco_opcode::flat_atomic_xor_x2;
5793             break;
5794          case nir_intrinsic_global_atomic_exchange:
5795             op32 = global ? aco_opcode::global_atomic_swap : aco_opcode::flat_atomic_swap;
5796             op64 = global ? aco_opcode::global_atomic_swap_x2 : aco_opcode::flat_atomic_swap_x2;
5797             break;
5798          case nir_intrinsic_global_atomic_comp_swap:
5799             op32 = global ? aco_opcode::global_atomic_cmpswap : aco_opcode::flat_atomic_cmpswap;
5800             op64 = global ? aco_opcode::global_atomic_cmpswap_x2 : aco_opcode::flat_atomic_cmpswap_x2;
5801             break;
5802          default:
5803             unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
5804       }
5805
5806       aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
5807       aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 3, return_previous ? 1 : 0)};
5808       flat->operands[0] = Operand(addr);
5809       flat->operands[1] = Operand(s1);
5810       flat->operands[2] = Operand(data);
5811       if (return_previous)
5812          flat->definitions[0] = Definition(dst);
5813       flat->glc = return_previous;
5814       flat->dlc = false; /* Not needed for atomics */
5815       flat->offset = 0;
5816       flat->disable_wqm = true;
5817       flat->barrier = barrier_buffer;
5818       ctx->program->needs_exact = true;
5819       ctx->block->instructions.emplace_back(std::move(flat));
5820    } else {
5821       assert(ctx->options->chip_class == GFX6);
5822
5823       switch (instr->intrinsic) {
5824          case nir_intrinsic_global_atomic_add:
5825             op32 = aco_opcode::buffer_atomic_add;
5826             op64 = aco_opcode::buffer_atomic_add_x2;
5827             break;
5828          case nir_intrinsic_global_atomic_imin:
5829             op32 = aco_opcode::buffer_atomic_smin;
5830             op64 = aco_opcode::buffer_atomic_smin_x2;
5831             break;
5832          case nir_intrinsic_global_atomic_umin:
5833             op32 = aco_opcode::buffer_atomic_umin;
5834             op64 = aco_opcode::buffer_atomic_umin_x2;
5835             break;
5836          case nir_intrinsic_global_atomic_imax:
5837             op32 = aco_opcode::buffer_atomic_smax;
5838             op64 = aco_opcode::buffer_atomic_smax_x2;
5839             break;
5840          case nir_intrinsic_global_atomic_umax:
5841             op32 = aco_opcode::buffer_atomic_umax;
5842             op64 = aco_opcode::buffer_atomic_umax_x2;
5843             break;
5844          case nir_intrinsic_global_atomic_and:
5845             op32 = aco_opcode::buffer_atomic_and;
5846             op64 = aco_opcode::buffer_atomic_and_x2;
5847             break;
5848          case nir_intrinsic_global_atomic_or:
5849             op32 = aco_opcode::buffer_atomic_or;
5850             op64 = aco_opcode::buffer_atomic_or_x2;
5851             break;
5852          case nir_intrinsic_global_atomic_xor:
5853             op32 = aco_opcode::buffer_atomic_xor;
5854             op64 = aco_opcode::buffer_atomic_xor_x2;
5855             break;
5856          case nir_intrinsic_global_atomic_exchange:
5857             op32 = aco_opcode::buffer_atomic_swap;
5858             op64 = aco_opcode::buffer_atomic_swap_x2;
5859             break;
5860          case nir_intrinsic_global_atomic_comp_swap:
5861             op32 = aco_opcode::buffer_atomic_cmpswap;
5862             op64 = aco_opcode::buffer_atomic_cmpswap_x2;
5863             break;
5864          default:
5865             unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
5866       }
5867
5868       Temp rsrc = get_gfx6_global_rsrc(bld, addr);
5869
5870       aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
5871
5872       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, return_previous ? 1 : 0)};
5873       mubuf->operands[0] = Operand(rsrc);
5874       mubuf->operands[1] = addr.type() == RegType::vgpr ? Operand(addr) : Operand(v1);
5875       mubuf->operands[2] = Operand(0u);
5876       mubuf->operands[3] = Operand(data);
5877       if (return_previous)
5878          mubuf->definitions[0] = Definition(dst);
5879       mubuf->glc = return_previous;
5880       mubuf->dlc = false;
5881       mubuf->offset = 0;
5882       mubuf->addr64 = addr.type() == RegType::vgpr;
5883       mubuf->disable_wqm = true;
5884       mubuf->barrier = barrier_buffer;
5885       ctx->program->needs_exact = true;
5886       ctx->block->instructions.emplace_back(std::move(mubuf));
5887    }
5888 }
5889
5890 void emit_memory_barrier(isel_context *ctx, nir_intrinsic_instr *instr) {
5891    Builder bld(ctx->program, ctx->block);
5892    switch(instr->intrinsic) {
5893       case nir_intrinsic_group_memory_barrier:
5894       case nir_intrinsic_memory_barrier:
5895          bld.barrier(aco_opcode::p_memory_barrier_common);
5896          break;
5897       case nir_intrinsic_memory_barrier_buffer:
5898          bld.barrier(aco_opcode::p_memory_barrier_buffer);
5899          break;
5900       case nir_intrinsic_memory_barrier_image:
5901          bld.barrier(aco_opcode::p_memory_barrier_image);
5902          break;
5903       case nir_intrinsic_memory_barrier_tcs_patch:
5904       case nir_intrinsic_memory_barrier_shared:
5905          bld.barrier(aco_opcode::p_memory_barrier_shared);
5906          break;
5907       default:
5908          unreachable("Unimplemented memory barrier intrinsic");
5909          break;
5910    }
5911 }
5912
5913 void visit_load_shared(isel_context *ctx, nir_intrinsic_instr *instr)
5914 {
5915    // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
5916    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5917    assert(instr->dest.ssa.bit_size >= 32 && "Bitsize not supported in load_shared.");
5918    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5919    Builder bld(ctx->program, ctx->block);
5920
5921    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
5922    unsigned align = nir_intrinsic_align_mul(instr) ? nir_intrinsic_align(instr) : elem_size_bytes;
5923    load_lds(ctx, elem_size_bytes, dst, address, nir_intrinsic_base(instr), align);
5924 }
5925
5926 void visit_store_shared(isel_context *ctx, nir_intrinsic_instr *instr)
5927 {
5928    unsigned writemask = nir_intrinsic_write_mask(instr);
5929    Temp data = get_ssa_temp(ctx, instr->src[0].ssa);
5930    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5931    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
5932    assert(elem_size_bytes >= 4 && "Only 32bit & 64bit store_shared currently supported.");
5933
5934    unsigned align = nir_intrinsic_align_mul(instr) ? nir_intrinsic_align(instr) : elem_size_bytes;
5935    store_lds(ctx, elem_size_bytes, data, writemask, address, nir_intrinsic_base(instr), align);
5936 }
5937
5938 void visit_shared_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
5939 {
5940    unsigned offset = nir_intrinsic_base(instr);
5941    Operand m = load_lds_size_m0(ctx);
5942    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5943    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5944
5945    unsigned num_operands = 3;
5946    aco_opcode op32, op64, op32_rtn, op64_rtn;
5947    switch(instr->intrinsic) {
5948       case nir_intrinsic_shared_atomic_add:
5949          op32 = aco_opcode::ds_add_u32;
5950          op64 = aco_opcode::ds_add_u64;
5951          op32_rtn = aco_opcode::ds_add_rtn_u32;
5952          op64_rtn = aco_opcode::ds_add_rtn_u64;
5953          break;
5954       case nir_intrinsic_shared_atomic_imin:
5955          op32 = aco_opcode::ds_min_i32;
5956          op64 = aco_opcode::ds_min_i64;
5957          op32_rtn = aco_opcode::ds_min_rtn_i32;
5958          op64_rtn = aco_opcode::ds_min_rtn_i64;
5959          break;
5960       case nir_intrinsic_shared_atomic_umin:
5961          op32 = aco_opcode::ds_min_u32;
5962          op64 = aco_opcode::ds_min_u64;
5963          op32_rtn = aco_opcode::ds_min_rtn_u32;
5964          op64_rtn = aco_opcode::ds_min_rtn_u64;
5965          break;
5966       case nir_intrinsic_shared_atomic_imax:
5967          op32 = aco_opcode::ds_max_i32;
5968          op64 = aco_opcode::ds_max_i64;
5969          op32_rtn = aco_opcode::ds_max_rtn_i32;
5970          op64_rtn = aco_opcode::ds_max_rtn_i64;
5971          break;
5972       case nir_intrinsic_shared_atomic_umax:
5973          op32 = aco_opcode::ds_max_u32;
5974          op64 = aco_opcode::ds_max_u64;
5975          op32_rtn = aco_opcode::ds_max_rtn_u32;
5976          op64_rtn = aco_opcode::ds_max_rtn_u64;
5977          break;
5978       case nir_intrinsic_shared_atomic_and:
5979          op32 = aco_opcode::ds_and_b32;
5980          op64 = aco_opcode::ds_and_b64;
5981          op32_rtn = aco_opcode::ds_and_rtn_b32;
5982          op64_rtn = aco_opcode::ds_and_rtn_b64;
5983          break;
5984       case nir_intrinsic_shared_atomic_or:
5985          op32 = aco_opcode::ds_or_b32;
5986          op64 = aco_opcode::ds_or_b64;
5987          op32_rtn = aco_opcode::ds_or_rtn_b32;
5988          op64_rtn = aco_opcode::ds_or_rtn_b64;
5989          break;
5990       case nir_intrinsic_shared_atomic_xor:
5991          op32 = aco_opcode::ds_xor_b32;
5992          op64 = aco_opcode::ds_xor_b64;
5993          op32_rtn = aco_opcode::ds_xor_rtn_b32;
5994          op64_rtn = aco_opcode::ds_xor_rtn_b64;
5995          break;
5996       case nir_intrinsic_shared_atomic_exchange:
5997          op32 = aco_opcode::ds_write_b32;
5998          op64 = aco_opcode::ds_write_b64;
5999          op32_rtn = aco_opcode::ds_wrxchg_rtn_b32;
6000          op64_rtn = aco_opcode::ds_wrxchg2_rtn_b64;
6001          break;
6002       case nir_intrinsic_shared_atomic_comp_swap:
6003          op32 = aco_opcode::ds_cmpst_b32;
6004          op64 = aco_opcode::ds_cmpst_b64;
6005          op32_rtn = aco_opcode::ds_cmpst_rtn_b32;
6006          op64_rtn = aco_opcode::ds_cmpst_rtn_b64;
6007          num_operands = 4;
6008          break;
6009       default:
6010          unreachable("Unhandled shared atomic intrinsic");
6011    }
6012
6013    /* return the previous value if dest is ever used */
6014    bool return_previous = false;
6015    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
6016       return_previous = true;
6017       break;
6018    }
6019    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
6020       return_previous = true;
6021       break;
6022    }
6023
6024    aco_opcode op;
6025    if (data.size() == 1) {
6026       assert(instr->dest.ssa.bit_size == 32);
6027       op = return_previous ? op32_rtn : op32;
6028    } else {
6029       assert(instr->dest.ssa.bit_size == 64);
6030       op = return_previous ? op64_rtn : op64;
6031    }
6032
6033    if (offset > 65535) {
6034       Builder bld(ctx->program, ctx->block);
6035       address = bld.vadd32(bld.def(v1), Operand(offset), address);
6036       offset = 0;
6037    }
6038
6039    aco_ptr<DS_instruction> ds;
6040    ds.reset(create_instruction<DS_instruction>(op, Format::DS, num_operands, return_previous ? 1 : 0));
6041    ds->operands[0] = Operand(address);
6042    ds->operands[1] = Operand(data);
6043    if (num_operands == 4)
6044       ds->operands[2] = Operand(get_ssa_temp(ctx, instr->src[2].ssa));
6045    ds->operands[num_operands - 1] = m;
6046    ds->offset0 = offset;
6047    if (return_previous)
6048       ds->definitions[0] = Definition(get_ssa_temp(ctx, &instr->dest.ssa));
6049    ctx->block->instructions.emplace_back(std::move(ds));
6050 }
6051
6052 Temp get_scratch_resource(isel_context *ctx)
6053 {
6054    Builder bld(ctx->program, ctx->block);
6055    Temp scratch_addr = ctx->program->private_segment_buffer;
6056    if (ctx->stage != compute_cs)
6057       scratch_addr = bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), scratch_addr, Operand(0u));
6058
6059    uint32_t rsrc_conf = S_008F0C_ADD_TID_ENABLE(1) |
6060                         S_008F0C_INDEX_STRIDE(ctx->program->wave_size == 64 ? 3 : 2);;
6061
6062    if (ctx->program->chip_class >= GFX10) {
6063       rsrc_conf |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
6064                    S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
6065                    S_008F0C_RESOURCE_LEVEL(1);
6066    } else if (ctx->program->chip_class <= GFX7) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6067       rsrc_conf |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
6068                    S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
6069    }
6070
6071    /* older generations need element size = 16 bytes. element size removed in GFX9 */
6072    if (ctx->program->chip_class <= GFX8)
6073       rsrc_conf |= S_008F0C_ELEMENT_SIZE(3);
6074
6075    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), scratch_addr, Operand(-1u), Operand(rsrc_conf));
6076 }
6077
6078 void visit_load_scratch(isel_context *ctx, nir_intrinsic_instr *instr) {
6079    assert(instr->dest.ssa.bit_size == 32 || instr->dest.ssa.bit_size == 64);
6080    Builder bld(ctx->program, ctx->block);
6081    Temp rsrc = get_scratch_resource(ctx);
6082    Temp offset = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
6083    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6084
6085    aco_opcode op;
6086    switch (dst.size()) {
6087       case 1:
6088          op = aco_opcode::buffer_load_dword;
6089          break;
6090       case 2:
6091          op = aco_opcode::buffer_load_dwordx2;
6092          break;
6093       case 3:
6094          op = aco_opcode::buffer_load_dwordx3;
6095          break;
6096       case 4:
6097          op = aco_opcode::buffer_load_dwordx4;
6098          break;
6099       case 6:
6100       case 8: {
6101          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
6102          Temp lower = bld.mubuf(aco_opcode::buffer_load_dwordx4,
6103                                 bld.def(v4), rsrc, offset,
6104                                 ctx->program->scratch_offset, 0, true);
6105          Temp upper = bld.mubuf(dst.size() == 6 ? aco_opcode::buffer_load_dwordx2 :
6106                                                   aco_opcode::buffer_load_dwordx4,
6107                                 dst.size() == 6 ? bld.def(v2) : bld.def(v4),
6108                                 rsrc, offset, ctx->program->scratch_offset, 16, true);
6109          emit_split_vector(ctx, lower, 2);
6110          elems[0] = emit_extract_vector(ctx, lower, 0, v2);
6111          elems[1] = emit_extract_vector(ctx, lower, 1, v2);
6112          if (dst.size() == 8) {
6113             emit_split_vector(ctx, upper, 2);
6114             elems[2] = emit_extract_vector(ctx, upper, 0, v2);
6115             elems[3] = emit_extract_vector(ctx, upper, 1, v2);
6116          } else {
6117             elems[2] = upper;
6118          }
6119
6120          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector,
6121                                                                          Format::PSEUDO, dst.size() / 2, 1)};
6122          for (unsigned i = 0; i < dst.size() / 2; i++)
6123             vec->operands[i] = Operand(elems[i]);
6124          vec->definitions[0] = Definition(dst);
6125          bld.insert(std::move(vec));
6126          ctx->allocated_vec.emplace(dst.id(), elems);
6127          return;
6128       }
6129       default:
6130          unreachable("Wrong dst size for nir_intrinsic_load_scratch");
6131    }
6132
6133    bld.mubuf(op, Definition(dst), rsrc, offset, ctx->program->scratch_offset, 0, true);
6134    emit_split_vector(ctx, dst, instr->num_components);
6135 }
6136
6137 void visit_store_scratch(isel_context *ctx, nir_intrinsic_instr *instr) {
6138    assert(instr->src[0].ssa->bit_size == 32 || instr->src[0].ssa->bit_size == 64);
6139    Builder bld(ctx->program, ctx->block);
6140    Temp rsrc = get_scratch_resource(ctx);
6141    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
6142    Temp offset = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
6143
6144    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
6145    unsigned writemask = nir_intrinsic_write_mask(instr);
6146
6147    while (writemask) {
6148       int start, count;
6149       u_bit_scan_consecutive_range(&writemask, &start, &count);
6150       int num_bytes = count * elem_size_bytes;
6151
6152       if (num_bytes > 16) {
6153          assert(elem_size_bytes == 8);
6154          writemask |= (((count - 2) << 1) - 1) << (start + 2);
6155          count = 2;
6156          num_bytes = 16;
6157       }
6158
6159       // TODO: check alignment of sub-dword stores
6160       // TODO: split 3 bytes. there is no store instruction for that
6161
6162       Temp write_data;
6163       if (count != instr->num_components) {
6164          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
6165          for (int i = 0; i < count; i++) {
6166             Temp elem = emit_extract_vector(ctx, data, start + i, RegClass(RegType::vgpr, elem_size_bytes / 4));
6167             vec->operands[i] = Operand(elem);
6168          }
6169          write_data = bld.tmp(RegClass(RegType::vgpr, count * elem_size_bytes / 4));
6170          vec->definitions[0] = Definition(write_data);
6171          ctx->block->instructions.emplace_back(std::move(vec));
6172       } else {
6173          write_data = data;
6174       }
6175
6176       aco_opcode op;
6177       switch (num_bytes) {
6178          case 4:
6179             op = aco_opcode::buffer_store_dword;
6180             break;
6181          case 8:
6182             op = aco_opcode::buffer_store_dwordx2;
6183             break;
6184          case 12:
6185             op = aco_opcode::buffer_store_dwordx3;
6186             break;
6187          case 16:
6188             op = aco_opcode::buffer_store_dwordx4;
6189             break;
6190          default:
6191             unreachable("Invalid data size for nir_intrinsic_store_scratch.");
6192       }
6193
6194       bld.mubuf(op, rsrc, offset, ctx->program->scratch_offset, write_data, start * elem_size_bytes, true);
6195    }
6196 }
6197
6198 void visit_load_sample_mask_in(isel_context *ctx, nir_intrinsic_instr *instr) {
6199    uint8_t log2_ps_iter_samples;
6200    if (ctx->program->info->ps.force_persample) {
6201       log2_ps_iter_samples =
6202          util_logbase2(ctx->options->key.fs.num_samples);
6203    } else {
6204       log2_ps_iter_samples = ctx->options->key.fs.log2_ps_iter_samples;
6205    }
6206
6207    /* The bit pattern matches that used by fixed function fragment
6208     * processing. */
6209    static const unsigned ps_iter_masks[] = {
6210       0xffff, /* not used */
6211       0x5555,
6212       0x1111,
6213       0x0101,
6214       0x0001,
6215    };
6216    assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
6217
6218    Builder bld(ctx->program, ctx->block);
6219
6220    Temp sample_id = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1),
6221                              get_arg(ctx, ctx->args->ac.ancillary), Operand(8u), Operand(4u));
6222    Temp ps_iter_mask = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(ps_iter_masks[log2_ps_iter_samples]));
6223    Temp mask = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), sample_id, ps_iter_mask);
6224    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6225    bld.vop2(aco_opcode::v_and_b32, Definition(dst), mask, get_arg(ctx, ctx->args->ac.sample_coverage));
6226 }
6227
6228 void visit_emit_vertex_with_counter(isel_context *ctx, nir_intrinsic_instr *instr) {
6229    Builder bld(ctx->program, ctx->block);
6230
6231    unsigned stream = nir_intrinsic_stream_id(instr);
6232    Temp next_vertex = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
6233    next_vertex = bld.v_mul_imm(bld.def(v1), next_vertex, 4u);
6234    nir_const_value *next_vertex_cv = nir_src_as_const_value(instr->src[0]);
6235
6236    /* get GSVS ring */
6237    Temp gsvs_ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_GSVS_GS * 16u));
6238
6239    unsigned num_components =
6240       ctx->program->info->gs.num_stream_output_components[stream];
6241    assert(num_components);
6242
6243    unsigned stride = 4u * num_components * ctx->shader->info.gs.vertices_out;
6244    unsigned stream_offset = 0;
6245    for (unsigned i = 0; i < stream; i++) {
6246       unsigned prev_stride = 4u * ctx->program->info->gs.num_stream_output_components[i] * ctx->shader->info.gs.vertices_out;
6247       stream_offset += prev_stride * ctx->program->wave_size;
6248    }
6249
6250    /* Limit on the stride field for <= GFX7. */
6251    assert(stride < (1 << 14));
6252
6253    Temp gsvs_dwords[4];
6254    for (unsigned i = 0; i < 4; i++)
6255       gsvs_dwords[i] = bld.tmp(s1);
6256    bld.pseudo(aco_opcode::p_split_vector,
6257               Definition(gsvs_dwords[0]),
6258               Definition(gsvs_dwords[1]),
6259               Definition(gsvs_dwords[2]),
6260               Definition(gsvs_dwords[3]),
6261               gsvs_ring);
6262
6263    if (stream_offset) {
6264       Temp stream_offset_tmp = bld.copy(bld.def(s1), Operand(stream_offset));
6265
6266       Temp carry = bld.tmp(s1);
6267       gsvs_dwords[0] = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), gsvs_dwords[0], stream_offset_tmp);
6268       gsvs_dwords[1] = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), gsvs_dwords[1], Operand(0u), bld.scc(carry));
6269    }
6270
6271    gsvs_dwords[1] = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), gsvs_dwords[1], Operand(S_008F04_STRIDE(stride)));
6272    gsvs_dwords[2] = bld.copy(bld.def(s1), Operand((uint32_t)ctx->program->wave_size));
6273
6274    gsvs_ring = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
6275                           gsvs_dwords[0], gsvs_dwords[1], gsvs_dwords[2], gsvs_dwords[3]);
6276
6277    unsigned offset = 0;
6278    for (unsigned i = 0; i <= VARYING_SLOT_VAR31; i++) {
6279       if (ctx->program->info->gs.output_streams[i] != stream)
6280          continue;
6281
6282       for (unsigned j = 0; j < 4; j++) {
6283          if (!(ctx->program->info->gs.output_usage_mask[i] & (1 << j)))
6284             continue;
6285
6286          if (ctx->outputs.mask[i] & (1 << j)) {
6287             Operand vaddr_offset = next_vertex_cv ? Operand(v1) : Operand(next_vertex);
6288             unsigned const_offset = (offset + (next_vertex_cv ? next_vertex_cv->u32 : 0u)) * 4u;
6289             if (const_offset >= 4096u) {
6290                if (vaddr_offset.isUndefined())
6291                   vaddr_offset = bld.copy(bld.def(v1), Operand(const_offset / 4096u * 4096u));
6292                else
6293                   vaddr_offset = bld.vadd32(bld.def(v1), Operand(const_offset / 4096u * 4096u), vaddr_offset);
6294                const_offset %= 4096u;
6295             }
6296
6297             aco_ptr<MTBUF_instruction> mtbuf{create_instruction<MTBUF_instruction>(aco_opcode::tbuffer_store_format_x, Format::MTBUF, 4, 0)};
6298             mtbuf->operands[0] = Operand(gsvs_ring);
6299             mtbuf->operands[1] = vaddr_offset;
6300             mtbuf->operands[2] = Operand(get_arg(ctx, ctx->args->gs2vs_offset));
6301             mtbuf->operands[3] = Operand(ctx->outputs.outputs[i][j]);
6302             mtbuf->offen = !vaddr_offset.isUndefined();
6303             mtbuf->dfmt = V_008F0C_BUF_DATA_FORMAT_32;
6304             mtbuf->nfmt = V_008F0C_BUF_NUM_FORMAT_UINT;
6305             mtbuf->offset = const_offset;
6306             mtbuf->glc = true;
6307             mtbuf->slc = true;
6308             mtbuf->barrier = barrier_gs_data;
6309             mtbuf->can_reorder = true;
6310             bld.insert(std::move(mtbuf));
6311          }
6312
6313          offset += ctx->shader->info.gs.vertices_out;
6314       }
6315
6316       /* outputs for the next vertex are undefined and keeping them around can
6317        * create invalid IR with control flow */
6318       ctx->outputs.mask[i] = 0;
6319    }
6320
6321    bld.sopp(aco_opcode::s_sendmsg, bld.m0(ctx->gs_wave_id), -1, sendmsg_gs(false, true, stream));
6322 }
6323
6324 Temp emit_boolean_reduce(isel_context *ctx, nir_op op, unsigned cluster_size, Temp src)
6325 {
6326    Builder bld(ctx->program, ctx->block);
6327
6328    if (cluster_size == 1) {
6329       return src;
6330    } if (op == nir_op_iand && cluster_size == 4) {
6331       //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6332       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src);
6333       return bld.sop1(Builder::s_not, bld.def(bld.lm), bld.def(s1, scc),
6334                       bld.sop1(Builder::s_wqm, bld.def(bld.lm), bld.def(s1, scc), tmp));
6335    } else if (op == nir_op_ior && cluster_size == 4) {
6336       //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6337       return bld.sop1(Builder::s_wqm, bld.def(bld.lm), bld.def(s1, scc),
6338                       bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm)));
6339    } else if (op == nir_op_iand && cluster_size == ctx->program->wave_size) {
6340       //subgroupAnd(val) -> (exec & ~val) == 0
6341       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src).def(1).getTemp();
6342       Temp cond = bool_to_vector_condition(ctx, emit_wqm(ctx, tmp));
6343       return bld.sop1(Builder::s_not, bld.def(bld.lm), bld.def(s1, scc), cond);
6344    } else if (op == nir_op_ior && cluster_size == ctx->program->wave_size) {
6345       //subgroupOr(val) -> (val & exec) != 0
6346       Temp tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm)).def(1).getTemp();
6347       return bool_to_vector_condition(ctx, tmp);
6348    } else if (op == nir_op_ixor && cluster_size == ctx->program->wave_size) {
6349       //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6350       Temp tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
6351       tmp = bld.sop1(Builder::s_bcnt1_i32, bld.def(s1), bld.def(s1, scc), tmp);
6352       tmp = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), tmp, Operand(1u)).def(1).getTemp();
6353       return bool_to_vector_condition(ctx, tmp);
6354    } else {
6355       //subgroupClustered{And,Or,Xor}(val, n) ->
6356       //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ;  just v_mbcnt_lo_u32_b32 on wave32
6357       //cluster_offset = ~(n - 1) & lane_id
6358       //cluster_mask = ((1 << n) - 1)
6359       //subgroupClusteredAnd():
6360       //   return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6361       //subgroupClusteredOr():
6362       //   return ((val & exec) >> cluster_offset) & cluster_mask != 0
6363       //subgroupClusteredXor():
6364       //   return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6365       Temp lane_id = emit_mbcnt(ctx, bld.def(v1));
6366       Temp cluster_offset = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(~uint32_t(cluster_size - 1)), lane_id);
6367
6368       Temp tmp;
6369       if (op == nir_op_iand)
6370          tmp = bld.sop2(Builder::s_orn2, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
6371       else
6372          tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
6373
6374       uint32_t cluster_mask = cluster_size == 32 ? -1 : (1u << cluster_size) - 1u;
6375
6376       if (ctx->program->chip_class <= GFX7)
6377          tmp = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), tmp, cluster_offset);
6378       else if (ctx->program->wave_size == 64)
6379          tmp = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), cluster_offset, tmp);
6380       else
6381          tmp = bld.vop2_e64(aco_opcode::v_lshrrev_b32, bld.def(v1), cluster_offset, tmp);
6382       tmp = emit_extract_vector(ctx, tmp, 0, v1);
6383       if (cluster_mask != 0xffffffff)
6384          tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(cluster_mask), tmp);
6385
6386       Definition cmp_def = Definition();
6387       if (op == nir_op_iand) {
6388          cmp_def = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm), Operand(cluster_mask), tmp).def(0);
6389       } else if (op == nir_op_ior) {
6390          cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp).def(0);
6391       } else if (op == nir_op_ixor) {
6392          tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u),
6393                         bld.vop3(aco_opcode::v_bcnt_u32_b32, bld.def(v1), tmp, Operand(0u)));
6394          cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp).def(0);
6395       }
6396       cmp_def.setHint(vcc);
6397       return cmp_def.getTemp();
6398    }
6399 }
6400
6401 Temp emit_boolean_exclusive_scan(isel_context *ctx, nir_op op, Temp src)
6402 {
6403    Builder bld(ctx->program, ctx->block);
6404
6405    //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
6406    //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
6407    //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
6408    Temp tmp;
6409    if (op == nir_op_iand)
6410       tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src);
6411    else
6412       tmp = bld.sop2(Builder::s_and, bld.def(s2), bld.def(s1, scc), src, Operand(exec, bld.lm));
6413
6414    Builder::Result lohi = bld.pseudo(aco_opcode::p_split_vector, bld.def(s1), bld.def(s1), tmp);
6415    Temp lo = lohi.def(0).getTemp();
6416    Temp hi = lohi.def(1).getTemp();
6417    Temp mbcnt = emit_mbcnt(ctx, bld.def(v1), Operand(lo), Operand(hi));
6418
6419    Definition cmp_def = Definition();
6420    if (op == nir_op_iand)
6421       cmp_def = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm), Operand(0u), mbcnt).def(0);
6422    else if (op == nir_op_ior)
6423       cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), mbcnt).def(0);
6424    else if (op == nir_op_ixor)
6425       cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u),
6426                          bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u), mbcnt)).def(0);
6427    cmp_def.setHint(vcc);
6428    return cmp_def.getTemp();
6429 }
6430
6431 Temp emit_boolean_inclusive_scan(isel_context *ctx, nir_op op, Temp src)
6432 {
6433    Builder bld(ctx->program, ctx->block);
6434
6435    //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
6436    //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
6437    //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
6438    Temp tmp = emit_boolean_exclusive_scan(ctx, op, src);
6439    if (op == nir_op_iand)
6440       return bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
6441    else if (op == nir_op_ior)
6442       return bld.sop2(Builder::s_or, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
6443    else if (op == nir_op_ixor)
6444       return bld.sop2(Builder::s_xor, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
6445
6446    assert(false);
6447    return Temp();
6448 }
6449
6450 void emit_uniform_subgroup(isel_context *ctx, nir_intrinsic_instr *instr, Temp src)
6451 {
6452    Builder bld(ctx->program, ctx->block);
6453    Definition dst(get_ssa_temp(ctx, &instr->dest.ssa));
6454    if (src.regClass().type() == RegType::vgpr) {
6455       bld.pseudo(aco_opcode::p_as_uniform, dst, src);
6456    } else if (src.regClass() == s1) {
6457       bld.sop1(aco_opcode::s_mov_b32, dst, src);
6458    } else if (src.regClass() == s2) {
6459       bld.sop1(aco_opcode::s_mov_b64, dst, src);
6460    } else {
6461       fprintf(stderr, "Unimplemented NIR instr bit size: ");
6462       nir_print_instr(&instr->instr, stderr);
6463       fprintf(stderr, "\n");
6464    }
6465 }
6466
6467 void emit_interp_center(isel_context *ctx, Temp dst, Temp pos1, Temp pos2)
6468 {
6469    Builder bld(ctx->program, ctx->block);
6470    Temp persp_center = get_arg(ctx, ctx->args->ac.persp_center);
6471    Temp p1 = emit_extract_vector(ctx, persp_center, 0, v1);
6472    Temp p2 = emit_extract_vector(ctx, persp_center, 1, v1);
6473
6474    Temp ddx_1, ddx_2, ddy_1, ddy_2;
6475    uint32_t dpp_ctrl0 = dpp_quad_perm(0, 0, 0, 0);
6476    uint32_t dpp_ctrl1 = dpp_quad_perm(1, 1, 1, 1);
6477    uint32_t dpp_ctrl2 = dpp_quad_perm(2, 2, 2, 2);
6478
6479    /* Build DD X/Y */
6480    if (ctx->program->chip_class >= GFX8) {
6481       Temp tl_1 = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), p1, dpp_ctrl0);
6482       ddx_1 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p1, tl_1, dpp_ctrl1);
6483       ddy_1 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p1, tl_1, dpp_ctrl2);
6484       Temp tl_2 = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), p2, dpp_ctrl0);
6485       ddx_2 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p2, tl_2, dpp_ctrl1);
6486       ddy_2 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p2, tl_2, dpp_ctrl2);
6487    } else {
6488       Temp tl_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl0);
6489       ddx_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl1);
6490       ddx_1 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddx_1, tl_1);
6491       ddx_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl2);
6492       ddx_2 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddx_2, tl_1);
6493       Temp tl_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl0);
6494       ddy_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl1);
6495       ddy_1 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddy_1, tl_2);
6496       ddy_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl2);
6497       ddy_2 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddy_2, tl_2);
6498    }
6499
6500    /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
6501    Temp tmp1 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddx_1, pos1, p1);
6502    Temp tmp2 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddx_2, pos1, p2);
6503    tmp1 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddy_1, pos2, tmp1);
6504    tmp2 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddy_2, pos2, tmp2);
6505    Temp wqm1 = bld.tmp(v1);
6506    emit_wqm(ctx, tmp1, wqm1, true);
6507    Temp wqm2 = bld.tmp(v1);
6508    emit_wqm(ctx, tmp2, wqm2, true);
6509    bld.pseudo(aco_opcode::p_create_vector, Definition(dst), wqm1, wqm2);
6510    return;
6511 }
6512
6513 void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr)
6514 {
6515    Builder bld(ctx->program, ctx->block);
6516    switch(instr->intrinsic) {
6517    case nir_intrinsic_load_barycentric_sample:
6518    case nir_intrinsic_load_barycentric_pixel:
6519    case nir_intrinsic_load_barycentric_centroid: {
6520       glsl_interp_mode mode = (glsl_interp_mode)nir_intrinsic_interp_mode(instr);
6521       Temp bary = Temp(0, s2);
6522       switch (mode) {
6523       case INTERP_MODE_SMOOTH:
6524       case INTERP_MODE_NONE:
6525          if (instr->intrinsic == nir_intrinsic_load_barycentric_pixel)
6526             bary = get_arg(ctx, ctx->args->ac.persp_center);
6527          else if (instr->intrinsic == nir_intrinsic_load_barycentric_centroid)
6528             bary = ctx->persp_centroid;
6529          else if (instr->intrinsic == nir_intrinsic_load_barycentric_sample)
6530             bary = get_arg(ctx, ctx->args->ac.persp_sample);
6531          break;
6532       case INTERP_MODE_NOPERSPECTIVE:
6533          if (instr->intrinsic == nir_intrinsic_load_barycentric_pixel)
6534             bary = get_arg(ctx, ctx->args->ac.linear_center);
6535          else if (instr->intrinsic == nir_intrinsic_load_barycentric_centroid)
6536             bary = ctx->linear_centroid;
6537          else if (instr->intrinsic == nir_intrinsic_load_barycentric_sample)
6538             bary = get_arg(ctx, ctx->args->ac.linear_sample);
6539          break;
6540       default:
6541          break;
6542       }
6543       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6544       Temp p1 = emit_extract_vector(ctx, bary, 0, v1);
6545       Temp p2 = emit_extract_vector(ctx, bary, 1, v1);
6546       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
6547                  Operand(p1), Operand(p2));
6548       emit_split_vector(ctx, dst, 2);
6549       break;
6550    }
6551    case nir_intrinsic_load_barycentric_model: {
6552       Temp model = get_arg(ctx, ctx->args->ac.pull_model);
6553
6554       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6555       Temp p1 = emit_extract_vector(ctx, model, 0, v1);
6556       Temp p2 = emit_extract_vector(ctx, model, 1, v1);
6557       Temp p3 = emit_extract_vector(ctx, model, 2, v1);
6558       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
6559                  Operand(p1), Operand(p2), Operand(p3));
6560       emit_split_vector(ctx, dst, 3);
6561       break;
6562    }
6563    case nir_intrinsic_load_barycentric_at_sample: {
6564       uint32_t sample_pos_offset = RING_PS_SAMPLE_POSITIONS * 16;
6565       switch (ctx->options->key.fs.num_samples) {
6566          case 2: sample_pos_offset += 1 << 3; break;
6567          case 4: sample_pos_offset += 3 << 3; break;
6568          case 8: sample_pos_offset += 7 << 3; break;
6569          default: break;
6570       }
6571       Temp sample_pos;
6572       Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
6573       nir_const_value* const_addr = nir_src_as_const_value(instr->src[0]);
6574       Temp private_segment_buffer = ctx->program->private_segment_buffer;
6575       if (addr.type() == RegType::sgpr) {
6576          Operand offset;
6577          if (const_addr) {
6578             sample_pos_offset += const_addr->u32 << 3;
6579             offset = Operand(sample_pos_offset);
6580          } else if (ctx->options->chip_class >= GFX9) {
6581             offset = bld.sop2(aco_opcode::s_lshl3_add_u32, bld.def(s1), bld.def(s1, scc), addr, Operand(sample_pos_offset));
6582          } else {
6583             offset = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), addr, Operand(3u));
6584             offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), addr, Operand(sample_pos_offset));
6585          }
6586
6587          Operand off = bld.copy(bld.def(s1), Operand(offset));
6588          sample_pos = bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), private_segment_buffer, off);
6589
6590       } else if (ctx->options->chip_class >= GFX9) {
6591          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
6592          sample_pos = bld.global(aco_opcode::global_load_dwordx2, bld.def(v2), addr, private_segment_buffer, sample_pos_offset);
6593       } else if (ctx->options->chip_class >= GFX7) {
6594          /* addr += private_segment_buffer + sample_pos_offset */
6595          Temp tmp0 = bld.tmp(s1);
6596          Temp tmp1 = bld.tmp(s1);
6597          bld.pseudo(aco_opcode::p_split_vector, Definition(tmp0), Definition(tmp1), private_segment_buffer);
6598          Definition scc_tmp = bld.def(s1, scc);
6599          tmp0 = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), scc_tmp, tmp0, Operand(sample_pos_offset));
6600          tmp1 = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), tmp1, Operand(0u), bld.scc(scc_tmp.getTemp()));
6601          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
6602          Temp pck0 = bld.tmp(v1);
6603          Temp carry = bld.vadd32(Definition(pck0), tmp0, addr, true).def(1).getTemp();
6604          tmp1 = as_vgpr(ctx, tmp1);
6605          Temp pck1 = bld.vop2_e64(aco_opcode::v_addc_co_u32, bld.def(v1), bld.hint_vcc(bld.def(bld.lm)), tmp1, Operand(0u), carry);
6606          addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), pck0, pck1);
6607
6608          /* sample_pos = flat_load_dwordx2 addr */
6609          sample_pos = bld.flat(aco_opcode::flat_load_dwordx2, bld.def(v2), addr, Operand(s1));
6610       } else {
6611          assert(ctx->options->chip_class == GFX6);
6612
6613          uint32_t rsrc_conf = S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
6614                               S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
6615          Temp rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), private_segment_buffer, Operand(0u), Operand(rsrc_conf));
6616
6617          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
6618          addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), addr, Operand(0u));
6619
6620          sample_pos = bld.tmp(v2);
6621
6622          aco_ptr<MUBUF_instruction> load{create_instruction<MUBUF_instruction>(aco_opcode::buffer_load_dwordx2, Format::MUBUF, 3, 1)};
6623          load->definitions[0] = Definition(sample_pos);
6624          load->operands[0] = Operand(rsrc);
6625          load->operands[1] = Operand(addr);
6626          load->operands[2] = Operand(0u);
6627          load->offset = sample_pos_offset;
6628          load->offen = 0;
6629          load->addr64 = true;
6630          load->glc = false;
6631          load->dlc = false;
6632          load->disable_wqm = false;
6633          load->barrier = barrier_none;
6634          load->can_reorder = true;
6635          ctx->block->instructions.emplace_back(std::move(load));
6636       }
6637
6638       /* sample_pos -= 0.5 */
6639       Temp pos1 = bld.tmp(RegClass(sample_pos.type(), 1));
6640       Temp pos2 = bld.tmp(RegClass(sample_pos.type(), 1));
6641       bld.pseudo(aco_opcode::p_split_vector, Definition(pos1), Definition(pos2), sample_pos);
6642       pos1 = bld.vop2_e64(aco_opcode::v_sub_f32, bld.def(v1), pos1, Operand(0x3f000000u));
6643       pos2 = bld.vop2_e64(aco_opcode::v_sub_f32, bld.def(v1), pos2, Operand(0x3f000000u));
6644
6645       emit_interp_center(ctx, get_ssa_temp(ctx, &instr->dest.ssa), pos1, pos2);
6646       break;
6647    }
6648    case nir_intrinsic_load_barycentric_at_offset: {
6649       Temp offset = get_ssa_temp(ctx, instr->src[0].ssa);
6650       RegClass rc = RegClass(offset.type(), 1);
6651       Temp pos1 = bld.tmp(rc), pos2 = bld.tmp(rc);
6652       bld.pseudo(aco_opcode::p_split_vector, Definition(pos1), Definition(pos2), offset);
6653       emit_interp_center(ctx, get_ssa_temp(ctx, &instr->dest.ssa), pos1, pos2);
6654       break;
6655    }
6656    case nir_intrinsic_load_front_face: {
6657       bld.vopc(aco_opcode::v_cmp_lg_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6658                Operand(0u), get_arg(ctx, ctx->args->ac.front_face)).def(0).setHint(vcc);
6659       break;
6660    }
6661    case nir_intrinsic_load_view_index: {
6662       if (ctx->stage & (sw_vs | sw_gs | sw_tcs | sw_tes)) {
6663          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6664          bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.view_index)));
6665          break;
6666       }
6667
6668       /* fallthrough */
6669    }
6670    case nir_intrinsic_load_layer_id: {
6671       unsigned idx = nir_intrinsic_base(instr);
6672       bld.vintrp(aco_opcode::v_interp_mov_f32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6673                  Operand(2u), bld.m0(get_arg(ctx, ctx->args->ac.prim_mask)), idx, 0);
6674       break;
6675    }
6676    case nir_intrinsic_load_frag_coord: {
6677       emit_load_frag_coord(ctx, get_ssa_temp(ctx, &instr->dest.ssa), 4);
6678       break;
6679    }
6680    case nir_intrinsic_load_sample_pos: {
6681       Temp posx = get_arg(ctx, ctx->args->ac.frag_pos[0]);
6682       Temp posy = get_arg(ctx, ctx->args->ac.frag_pos[1]);
6683       bld.pseudo(aco_opcode::p_create_vector, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6684                  posx.id() ? bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), posx) : Operand(0u),
6685                  posy.id() ? bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), posy) : Operand(0u));
6686       break;
6687    }
6688    case nir_intrinsic_load_tess_coord:
6689       visit_load_tess_coord(ctx, instr);
6690       break;
6691    case nir_intrinsic_load_interpolated_input:
6692       visit_load_interpolated_input(ctx, instr);
6693       break;
6694    case nir_intrinsic_store_output:
6695       visit_store_output(ctx, instr);
6696       break;
6697    case nir_intrinsic_load_input:
6698    case nir_intrinsic_load_input_vertex:
6699       visit_load_input(ctx, instr);
6700       break;
6701    case nir_intrinsic_load_output:
6702       visit_load_output(ctx, instr);
6703       break;
6704    case nir_intrinsic_load_per_vertex_input:
6705       visit_load_per_vertex_input(ctx, instr);
6706       break;
6707    case nir_intrinsic_load_per_vertex_output:
6708       visit_load_per_vertex_output(ctx, instr);
6709       break;
6710    case nir_intrinsic_store_per_vertex_output:
6711       visit_store_per_vertex_output(ctx, instr);
6712       break;
6713    case nir_intrinsic_load_ubo:
6714       visit_load_ubo(ctx, instr);
6715       break;
6716    case nir_intrinsic_load_push_constant:
6717       visit_load_push_constant(ctx, instr);
6718       break;
6719    case nir_intrinsic_load_constant:
6720       visit_load_constant(ctx, instr);
6721       break;
6722    case nir_intrinsic_vulkan_resource_index:
6723       visit_load_resource(ctx, instr);
6724       break;
6725    case nir_intrinsic_discard:
6726       visit_discard(ctx, instr);
6727       break;
6728    case nir_intrinsic_discard_if:
6729       visit_discard_if(ctx, instr);
6730       break;
6731    case nir_intrinsic_load_shared:
6732       visit_load_shared(ctx, instr);
6733       break;
6734    case nir_intrinsic_store_shared:
6735       visit_store_shared(ctx, instr);
6736       break;
6737    case nir_intrinsic_shared_atomic_add:
6738    case nir_intrinsic_shared_atomic_imin:
6739    case nir_intrinsic_shared_atomic_umin:
6740    case nir_intrinsic_shared_atomic_imax:
6741    case nir_intrinsic_shared_atomic_umax:
6742    case nir_intrinsic_shared_atomic_and:
6743    case nir_intrinsic_shared_atomic_or:
6744    case nir_intrinsic_shared_atomic_xor:
6745    case nir_intrinsic_shared_atomic_exchange:
6746    case nir_intrinsic_shared_atomic_comp_swap:
6747       visit_shared_atomic(ctx, instr);
6748       break;
6749    case nir_intrinsic_image_deref_load:
6750       visit_image_load(ctx, instr);
6751       break;
6752    case nir_intrinsic_image_deref_store:
6753       visit_image_store(ctx, instr);
6754       break;
6755    case nir_intrinsic_image_deref_atomic_add:
6756    case nir_intrinsic_image_deref_atomic_umin:
6757    case nir_intrinsic_image_deref_atomic_imin:
6758    case nir_intrinsic_image_deref_atomic_umax:
6759    case nir_intrinsic_image_deref_atomic_imax:
6760    case nir_intrinsic_image_deref_atomic_and:
6761    case nir_intrinsic_image_deref_atomic_or:
6762    case nir_intrinsic_image_deref_atomic_xor:
6763    case nir_intrinsic_image_deref_atomic_exchange:
6764    case nir_intrinsic_image_deref_atomic_comp_swap:
6765       visit_image_atomic(ctx, instr);
6766       break;
6767    case nir_intrinsic_image_deref_size:
6768       visit_image_size(ctx, instr);
6769       break;
6770    case nir_intrinsic_load_ssbo:
6771       visit_load_ssbo(ctx, instr);
6772       break;
6773    case nir_intrinsic_store_ssbo:
6774       visit_store_ssbo(ctx, instr);
6775       break;
6776    case nir_intrinsic_load_global:
6777       visit_load_global(ctx, instr);
6778       break;
6779    case nir_intrinsic_store_global:
6780       visit_store_global(ctx, instr);
6781       break;
6782    case nir_intrinsic_global_atomic_add:
6783    case nir_intrinsic_global_atomic_imin:
6784    case nir_intrinsic_global_atomic_umin:
6785    case nir_intrinsic_global_atomic_imax:
6786    case nir_intrinsic_global_atomic_umax:
6787    case nir_intrinsic_global_atomic_and:
6788    case nir_intrinsic_global_atomic_or:
6789    case nir_intrinsic_global_atomic_xor:
6790    case nir_intrinsic_global_atomic_exchange:
6791    case nir_intrinsic_global_atomic_comp_swap:
6792       visit_global_atomic(ctx, instr);
6793       break;
6794    case nir_intrinsic_ssbo_atomic_add:
6795    case nir_intrinsic_ssbo_atomic_imin:
6796    case nir_intrinsic_ssbo_atomic_umin:
6797    case nir_intrinsic_ssbo_atomic_imax:
6798    case nir_intrinsic_ssbo_atomic_umax:
6799    case nir_intrinsic_ssbo_atomic_and:
6800    case nir_intrinsic_ssbo_atomic_or:
6801    case nir_intrinsic_ssbo_atomic_xor:
6802    case nir_intrinsic_ssbo_atomic_exchange:
6803    case nir_intrinsic_ssbo_atomic_comp_swap:
6804       visit_atomic_ssbo(ctx, instr);
6805       break;
6806    case nir_intrinsic_load_scratch:
6807       visit_load_scratch(ctx, instr);
6808       break;
6809    case nir_intrinsic_store_scratch:
6810       visit_store_scratch(ctx, instr);
6811       break;
6812    case nir_intrinsic_get_buffer_size:
6813       visit_get_buffer_size(ctx, instr);
6814       break;
6815    case nir_intrinsic_control_barrier: {
6816       if (ctx->program->chip_class == GFX6 && ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) {
6817          /* GFX6 only (thanks to a hw bug workaround):
6818           * The real barrier instruction isn’t needed, because an entire patch
6819           * always fits into a single wave.
6820           */
6821          break;
6822       }
6823
6824       if (ctx->shader->info.stage == MESA_SHADER_COMPUTE) {
6825          unsigned* bsize = ctx->program->info->cs.block_size;
6826          unsigned workgroup_size = bsize[0] * bsize[1] * bsize[2];
6827          if (workgroup_size > ctx->program->wave_size)
6828             bld.sopp(aco_opcode::s_barrier);
6829       } else if (ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) {
6830          /* For each patch provided during rendering, n TCS shader invocations will be processed,
6831           * where n is the number of vertices in the output patch.
6832           */
6833          unsigned workgroup_size = ctx->tcs_num_patches * ctx->shader->info.tess.tcs_vertices_out;
6834          if (workgroup_size > ctx->program->wave_size)
6835             bld.sopp(aco_opcode::s_barrier);
6836       } else {
6837          /* We don't know the workgroup size, so always emit the s_barrier. */
6838          bld.sopp(aco_opcode::s_barrier);
6839       }
6840
6841       break;
6842    }
6843    case nir_intrinsic_memory_barrier_tcs_patch:
6844    case nir_intrinsic_group_memory_barrier:
6845    case nir_intrinsic_memory_barrier:
6846    case nir_intrinsic_memory_barrier_buffer:
6847    case nir_intrinsic_memory_barrier_image:
6848    case nir_intrinsic_memory_barrier_shared:
6849       emit_memory_barrier(ctx, instr);
6850       break;
6851    case nir_intrinsic_load_num_work_groups: {
6852       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6853       bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.num_work_groups)));
6854       emit_split_vector(ctx, dst, 3);
6855       break;
6856    }
6857    case nir_intrinsic_load_local_invocation_id: {
6858       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6859       bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.local_invocation_ids)));
6860       emit_split_vector(ctx, dst, 3);
6861       break;
6862    }
6863    case nir_intrinsic_load_work_group_id: {
6864       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6865       struct ac_arg *args = ctx->args->ac.workgroup_ids;
6866       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
6867                  args[0].used ? Operand(get_arg(ctx, args[0])) : Operand(0u),
6868                  args[1].used ? Operand(get_arg(ctx, args[1])) : Operand(0u),
6869                  args[2].used ? Operand(get_arg(ctx, args[2])) : Operand(0u));
6870       emit_split_vector(ctx, dst, 3);
6871       break;
6872    }
6873    case nir_intrinsic_load_local_invocation_index: {
6874       Temp id = emit_mbcnt(ctx, bld.def(v1));
6875
6876       /* The tg_size bits [6:11] contain the subgroup id,
6877        * we need this multiplied by the wave size, and then OR the thread id to it.
6878        */
6879       if (ctx->program->wave_size == 64) {
6880          /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
6881          Temp tg_num = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0xfc0u),
6882                                 get_arg(ctx, ctx->args->ac.tg_size));
6883          bld.vop2(aco_opcode::v_or_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), tg_num, id);
6884       } else {
6885          /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR  */
6886          Temp tg_num = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
6887                                 get_arg(ctx, ctx->args->ac.tg_size), Operand(0x6u | (0x6u << 16)));
6888          bld.vop3(aco_opcode::v_lshl_or_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), tg_num, Operand(0x5u), id);
6889       }
6890       break;
6891    }
6892    case nir_intrinsic_load_subgroup_id: {
6893       if (ctx->stage == compute_cs) {
6894          bld.sop2(aco_opcode::s_bfe_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), bld.def(s1, scc),
6895                   get_arg(ctx, ctx->args->ac.tg_size), Operand(0x6u | (0x6u << 16)));
6896       } else {
6897          bld.sop1(aco_opcode::s_mov_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand(0x0u));
6898       }
6899       break;
6900    }
6901    case nir_intrinsic_load_subgroup_invocation: {
6902       emit_mbcnt(ctx, Definition(get_ssa_temp(ctx, &instr->dest.ssa)));
6903       break;
6904    }
6905    case nir_intrinsic_load_num_subgroups: {
6906       if (ctx->stage == compute_cs)
6907          bld.sop2(aco_opcode::s_and_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), bld.def(s1, scc), Operand(0x3fu),
6908                   get_arg(ctx, ctx->args->ac.tg_size));
6909       else
6910          bld.sop1(aco_opcode::s_mov_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand(0x1u));
6911       break;
6912    }
6913    case nir_intrinsic_ballot: {
6914       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6915       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6916       Definition tmp = bld.def(dst.regClass());
6917       Definition lanemask_tmp = dst.size() == bld.lm.size() ? tmp : bld.def(src.regClass());
6918       if (instr->src[0].ssa->bit_size == 1) {
6919          assert(src.regClass() == bld.lm);
6920          bld.sop2(Builder::s_and, lanemask_tmp, bld.def(s1, scc), Operand(exec, bld.lm), src);
6921       } else if (instr->src[0].ssa->bit_size == 32 && src.regClass() == v1) {
6922          bld.vopc(aco_opcode::v_cmp_lg_u32, lanemask_tmp, Operand(0u), src);
6923       } else if (instr->src[0].ssa->bit_size == 64 && src.regClass() == v2) {
6924          bld.vopc(aco_opcode::v_cmp_lg_u64, lanemask_tmp, Operand(0u), src);
6925       } else {
6926          fprintf(stderr, "Unimplemented NIR instr bit size: ");
6927          nir_print_instr(&instr->instr, stderr);
6928          fprintf(stderr, "\n");
6929       }
6930       if (dst.size() != bld.lm.size()) {
6931          /* Wave32 with ballot size set to 64 */
6932          bld.pseudo(aco_opcode::p_create_vector, Definition(tmp), lanemask_tmp.getTemp(), Operand(0u));
6933       }
6934       emit_wqm(ctx, tmp.getTemp(), dst);
6935       break;
6936    }
6937    case nir_intrinsic_shuffle:
6938    case nir_intrinsic_read_invocation: {
6939       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6940       if (!ctx->divergent_vals[instr->src[0].ssa->index]) {
6941          emit_uniform_subgroup(ctx, instr, src);
6942       } else {
6943          Temp tid = get_ssa_temp(ctx, instr->src[1].ssa);
6944          if (instr->intrinsic == nir_intrinsic_read_invocation || !ctx->divergent_vals[instr->src[1].ssa->index])
6945             tid = bld.as_uniform(tid);
6946          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6947          if (src.regClass() == v1) {
6948             emit_wqm(ctx, emit_bpermute(ctx, bld, tid, src), dst);
6949          } else if (src.regClass() == v2) {
6950             Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6951             bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6952             lo = emit_wqm(ctx, emit_bpermute(ctx, bld, tid, lo));
6953             hi = emit_wqm(ctx, emit_bpermute(ctx, bld, tid, hi));
6954             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6955             emit_split_vector(ctx, dst, 2);
6956          } else if (instr->dest.ssa.bit_size == 1 && tid.regClass() == s1) {
6957             assert(src.regClass() == bld.lm);
6958             Temp tmp = bld.sopc(Builder::s_bitcmp1, bld.def(s1, scc), src, tid);
6959             bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
6960          } else if (instr->dest.ssa.bit_size == 1 && tid.regClass() == v1) {
6961             assert(src.regClass() == bld.lm);
6962             Temp tmp;
6963             if (ctx->program->chip_class <= GFX7)
6964                tmp = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), src, tid);
6965             else if (ctx->program->wave_size == 64)
6966                tmp = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), tid, src);
6967             else
6968                tmp = bld.vop2_e64(aco_opcode::v_lshrrev_b32, bld.def(v1), tid, src);
6969             tmp = emit_extract_vector(ctx, tmp, 0, v1);
6970             tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u), tmp);
6971             emit_wqm(ctx, bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp), dst);
6972          } else {
6973             fprintf(stderr, "Unimplemented NIR instr bit size: ");
6974             nir_print_instr(&instr->instr, stderr);
6975             fprintf(stderr, "\n");
6976          }
6977       }
6978       break;
6979    }
6980    case nir_intrinsic_load_sample_id: {
6981       bld.vop3(aco_opcode::v_bfe_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6982                get_arg(ctx, ctx->args->ac.ancillary), Operand(8u), Operand(4u));
6983       break;
6984    }
6985    case nir_intrinsic_load_sample_mask_in: {
6986       visit_load_sample_mask_in(ctx, instr);
6987       break;
6988    }
6989    case nir_intrinsic_read_first_invocation: {
6990       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6991       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6992       if (src.regClass() == v1) {
6993          emit_wqm(ctx,
6994                   bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), src),
6995                   dst);
6996       } else if (src.regClass() == v2) {
6997          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6998          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6999          lo = emit_wqm(ctx, bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), lo));
7000          hi = emit_wqm(ctx, bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), hi));
7001          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
7002          emit_split_vector(ctx, dst, 2);
7003       } else if (instr->dest.ssa.bit_size == 1) {
7004          assert(src.regClass() == bld.lm);
7005          Temp tmp = bld.sopc(Builder::s_bitcmp1, bld.def(s1, scc), src,
7006                              bld.sop1(Builder::s_ff1_i32, bld.def(s1), Operand(exec, bld.lm)));
7007          bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
7008       } else if (src.regClass() == s1) {
7009          bld.sop1(aco_opcode::s_mov_b32, Definition(dst), src);
7010       } else if (src.regClass() == s2) {
7011          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src);
7012       } else {
7013          fprintf(stderr, "Unimplemented NIR instr bit size: ");
7014          nir_print_instr(&instr->instr, stderr);
7015          fprintf(stderr, "\n");
7016       }
7017       break;
7018    }
7019    case nir_intrinsic_vote_all: {
7020       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7021       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7022       assert(src.regClass() == bld.lm);
7023       assert(dst.regClass() == bld.lm);
7024
7025       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src).def(1).getTemp();
7026       Temp cond = bool_to_vector_condition(ctx, emit_wqm(ctx, tmp));
7027       bld.sop1(Builder::s_not, Definition(dst), bld.def(s1, scc), cond);
7028       break;
7029    }
7030    case nir_intrinsic_vote_any: {
7031       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7032       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7033       assert(src.regClass() == bld.lm);
7034       assert(dst.regClass() == bld.lm);
7035
7036       Temp tmp = bool_to_scalar_condition(ctx, src);
7037       bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
7038       break;
7039    }
7040    case nir_intrinsic_reduce:
7041    case nir_intrinsic_inclusive_scan:
7042    case nir_intrinsic_exclusive_scan: {
7043       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7044       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7045       nir_op op = (nir_op) nir_intrinsic_reduction_op(instr);
7046       unsigned cluster_size = instr->intrinsic == nir_intrinsic_reduce ?
7047          nir_intrinsic_cluster_size(instr) : 0;
7048       cluster_size = util_next_power_of_two(MIN2(cluster_size ? cluster_size : ctx->program->wave_size, ctx->program->wave_size));
7049
7050       if (!ctx->divergent_vals[instr->src[0].ssa->index] && (op == nir_op_ior || op == nir_op_iand)) {
7051          emit_uniform_subgroup(ctx, instr, src);
7052       } else if (instr->dest.ssa.bit_size == 1) {
7053          if (op == nir_op_imul || op == nir_op_umin || op == nir_op_imin)
7054             op = nir_op_iand;
7055          else if (op == nir_op_iadd)
7056             op = nir_op_ixor;
7057          else if (op == nir_op_umax || op == nir_op_imax)
7058             op = nir_op_ior;
7059          assert(op == nir_op_iand || op == nir_op_ior || op == nir_op_ixor);
7060
7061          switch (instr->intrinsic) {
7062          case nir_intrinsic_reduce:
7063             emit_wqm(ctx, emit_boolean_reduce(ctx, op, cluster_size, src), dst);
7064             break;
7065          case nir_intrinsic_exclusive_scan:
7066             emit_wqm(ctx, emit_boolean_exclusive_scan(ctx, op, src), dst);
7067             break;
7068          case nir_intrinsic_inclusive_scan:
7069             emit_wqm(ctx, emit_boolean_inclusive_scan(ctx, op, src), dst);
7070             break;
7071          default:
7072             assert(false);
7073          }
7074       } else if (cluster_size == 1) {
7075          bld.copy(Definition(dst), src);
7076       } else {
7077          src = as_vgpr(ctx, src);
7078
7079          ReduceOp reduce_op;
7080          switch (op) {
7081          #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
7082             CASE(iadd)
7083             CASE(imul)
7084             CASE(fadd)
7085             CASE(fmul)
7086             CASE(imin)
7087             CASE(umin)
7088             CASE(fmin)
7089             CASE(imax)
7090             CASE(umax)
7091             CASE(fmax)
7092             CASE(iand)
7093             CASE(ior)
7094             CASE(ixor)
7095             default:
7096                unreachable("unknown reduction op");
7097          #undef CASE
7098          }
7099
7100          aco_opcode aco_op;
7101          switch (instr->intrinsic) {
7102             case nir_intrinsic_reduce: aco_op = aco_opcode::p_reduce; break;
7103             case nir_intrinsic_inclusive_scan: aco_op = aco_opcode::p_inclusive_scan; break;
7104             case nir_intrinsic_exclusive_scan: aco_op = aco_opcode::p_exclusive_scan; break;
7105             default:
7106                unreachable("unknown reduce intrinsic");
7107          }
7108
7109          aco_ptr<Pseudo_reduction_instruction> reduce{create_instruction<Pseudo_reduction_instruction>(aco_op, Format::PSEUDO_REDUCTION, 3, 5)};
7110          reduce->operands[0] = Operand(src);
7111          // filled in by aco_reduce_assign.cpp, used internally as part of the
7112          // reduce sequence
7113          assert(dst.size() == 1 || dst.size() == 2);
7114          reduce->operands[1] = Operand(RegClass(RegType::vgpr, dst.size()).as_linear());
7115          reduce->operands[2] = Operand(v1.as_linear());
7116
7117          Temp tmp_dst = bld.tmp(dst.regClass());
7118          reduce->definitions[0] = Definition(tmp_dst);
7119          reduce->definitions[1] = bld.def(ctx->program->lane_mask); // used internally
7120          reduce->definitions[2] = Definition();
7121          reduce->definitions[3] = Definition(scc, s1);
7122          reduce->definitions[4] = Definition();
7123          reduce->reduce_op = reduce_op;
7124          reduce->cluster_size = cluster_size;
7125          ctx->block->instructions.emplace_back(std::move(reduce));
7126
7127          emit_wqm(ctx, tmp_dst, dst);
7128       }
7129       break;
7130    }
7131    case nir_intrinsic_quad_broadcast: {
7132       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7133       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
7134          emit_uniform_subgroup(ctx, instr, src);
7135       } else {
7136          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7137          unsigned lane = nir_src_as_const_value(instr->src[1])->u32;
7138          uint32_t dpp_ctrl = dpp_quad_perm(lane, lane, lane, lane);
7139
7140          if (instr->dest.ssa.bit_size == 1) {
7141             assert(src.regClass() == bld.lm);
7142             assert(dst.regClass() == bld.lm);
7143             uint32_t half_mask = 0x11111111u << lane;
7144             Temp mask_tmp = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(half_mask), Operand(half_mask));
7145             Temp tmp = bld.tmp(bld.lm);
7146             bld.sop1(Builder::s_wqm, Definition(tmp),
7147                      bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), mask_tmp,
7148                               bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm))));
7149             emit_wqm(ctx, tmp, dst);
7150          } else if (instr->dest.ssa.bit_size == 32) {
7151             if (ctx->program->chip_class >= GFX8)
7152                emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl), dst);
7153             else
7154                emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl), dst);
7155          } else if (instr->dest.ssa.bit_size == 64) {
7156             Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
7157             bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
7158             if (ctx->program->chip_class >= GFX8) {
7159                lo = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), lo, dpp_ctrl));
7160                hi = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), hi, dpp_ctrl));
7161             } else {
7162                lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, (1 << 15) | dpp_ctrl));
7163                hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, (1 << 15) | dpp_ctrl));
7164             }
7165             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
7166             emit_split_vector(ctx, dst, 2);
7167          } else {
7168             fprintf(stderr, "Unimplemented NIR instr bit size: ");
7169             nir_print_instr(&instr->instr, stderr);
7170             fprintf(stderr, "\n");
7171          }
7172       }
7173       break;
7174    }
7175    case nir_intrinsic_quad_swap_horizontal:
7176    case nir_intrinsic_quad_swap_vertical:
7177    case nir_intrinsic_quad_swap_diagonal:
7178    case nir_intrinsic_quad_swizzle_amd: {
7179       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7180       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
7181          emit_uniform_subgroup(ctx, instr, src);
7182          break;
7183       }
7184       uint16_t dpp_ctrl = 0;
7185       switch (instr->intrinsic) {
7186       case nir_intrinsic_quad_swap_horizontal:
7187          dpp_ctrl = dpp_quad_perm(1, 0, 3, 2);
7188          break;
7189       case nir_intrinsic_quad_swap_vertical:
7190          dpp_ctrl = dpp_quad_perm(2, 3, 0, 1);
7191          break;
7192       case nir_intrinsic_quad_swap_diagonal:
7193          dpp_ctrl = dpp_quad_perm(3, 2, 1, 0);
7194          break;
7195       case nir_intrinsic_quad_swizzle_amd:
7196          dpp_ctrl = nir_intrinsic_swizzle_mask(instr);
7197          break;
7198       default:
7199          break;
7200       }
7201       if (ctx->program->chip_class < GFX8)
7202          dpp_ctrl |= (1 << 15);
7203
7204       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7205       if (instr->dest.ssa.bit_size == 1) {
7206          assert(src.regClass() == bld.lm);
7207          src = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand((uint32_t)-1), src);
7208          if (ctx->program->chip_class >= GFX8)
7209             src = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl);
7210          else
7211             src = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, dpp_ctrl);
7212          Temp tmp = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), src);
7213          emit_wqm(ctx, tmp, dst);
7214       } else if (instr->dest.ssa.bit_size == 32) {
7215          Temp tmp;
7216          if (ctx->program->chip_class >= GFX8)
7217             tmp = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl);
7218          else
7219             tmp = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, dpp_ctrl);
7220          emit_wqm(ctx, tmp, dst);
7221       } else if (instr->dest.ssa.bit_size == 64) {
7222          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
7223          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
7224          if (ctx->program->chip_class >= GFX8) {
7225             lo = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), lo, dpp_ctrl));
7226             hi = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), hi, dpp_ctrl));
7227          } else {
7228             lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, dpp_ctrl));
7229             hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, dpp_ctrl));
7230          }
7231          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
7232          emit_split_vector(ctx, dst, 2);
7233       } else {
7234          fprintf(stderr, "Unimplemented NIR instr bit size: ");
7235          nir_print_instr(&instr->instr, stderr);
7236          fprintf(stderr, "\n");
7237       }
7238       break;
7239    }
7240    case nir_intrinsic_masked_swizzle_amd: {
7241       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7242       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
7243          emit_uniform_subgroup(ctx, instr, src);
7244          break;
7245       }
7246       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7247       uint32_t mask = nir_intrinsic_swizzle_mask(instr);
7248       if (dst.regClass() == v1) {
7249          emit_wqm(ctx,
7250                   bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, mask, 0, false),
7251                   dst);
7252       } else if (dst.regClass() == v2) {
7253          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
7254          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
7255          lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, mask, 0, false));
7256          hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, mask, 0, false));
7257          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
7258          emit_split_vector(ctx, dst, 2);
7259       } else {
7260          fprintf(stderr, "Unimplemented NIR instr bit size: ");
7261          nir_print_instr(&instr->instr, stderr);
7262          fprintf(stderr, "\n");
7263       }
7264       break;
7265    }
7266    case nir_intrinsic_write_invocation_amd: {
7267       Temp src = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
7268       Temp val = bld.as_uniform(get_ssa_temp(ctx, instr->src[1].ssa));
7269       Temp lane = bld.as_uniform(get_ssa_temp(ctx, instr->src[2].ssa));
7270       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7271       if (dst.regClass() == v1) {
7272          /* src2 is ignored for writelane. RA assigns the same reg for dst */
7273          emit_wqm(ctx, bld.writelane(bld.def(v1), val, lane, src), dst);
7274       } else if (dst.regClass() == v2) {
7275          Temp src_lo = bld.tmp(v1), src_hi = bld.tmp(v1);
7276          Temp val_lo = bld.tmp(s1), val_hi = bld.tmp(s1);
7277          bld.pseudo(aco_opcode::p_split_vector, Definition(src_lo), Definition(src_hi), src);
7278          bld.pseudo(aco_opcode::p_split_vector, Definition(val_lo), Definition(val_hi), val);
7279          Temp lo = emit_wqm(ctx, bld.writelane(bld.def(v1), val_lo, lane, src_hi));
7280          Temp hi = emit_wqm(ctx, bld.writelane(bld.def(v1), val_hi, lane, src_hi));
7281          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
7282          emit_split_vector(ctx, dst, 2);
7283       } else {
7284          fprintf(stderr, "Unimplemented NIR instr bit size: ");
7285          nir_print_instr(&instr->instr, stderr);
7286          fprintf(stderr, "\n");
7287       }
7288       break;
7289    }
7290    case nir_intrinsic_mbcnt_amd: {
7291       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7292       RegClass rc = RegClass(src.type(), 1);
7293       Temp mask_lo = bld.tmp(rc), mask_hi = bld.tmp(rc);
7294       bld.pseudo(aco_opcode::p_split_vector, Definition(mask_lo), Definition(mask_hi), src);
7295       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7296       Temp wqm_tmp = emit_mbcnt(ctx, bld.def(v1), Operand(mask_lo), Operand(mask_hi));
7297       emit_wqm(ctx, wqm_tmp, dst);
7298       break;
7299    }
7300    case nir_intrinsic_load_helper_invocation: {
7301       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7302       bld.pseudo(aco_opcode::p_load_helper, Definition(dst));
7303       ctx->block->kind |= block_kind_needs_lowering;
7304       ctx->program->needs_exact = true;
7305       break;
7306    }
7307    case nir_intrinsic_is_helper_invocation: {
7308       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7309       bld.pseudo(aco_opcode::p_is_helper, Definition(dst));
7310       ctx->block->kind |= block_kind_needs_lowering;
7311       ctx->program->needs_exact = true;
7312       break;
7313    }
7314    case nir_intrinsic_demote:
7315       bld.pseudo(aco_opcode::p_demote_to_helper, Operand(-1u));
7316
7317       if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
7318          ctx->cf_info.exec_potentially_empty_discard = true;
7319       ctx->block->kind |= block_kind_uses_demote;
7320       ctx->program->needs_exact = true;
7321       break;
7322    case nir_intrinsic_demote_if: {
7323       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7324       assert(src.regClass() == bld.lm);
7325       Temp cond = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
7326       bld.pseudo(aco_opcode::p_demote_to_helper, cond);
7327
7328       if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
7329          ctx->cf_info.exec_potentially_empty_discard = true;
7330       ctx->block->kind |= block_kind_uses_demote;
7331       ctx->program->needs_exact = true;
7332       break;
7333    }
7334    case nir_intrinsic_first_invocation: {
7335       emit_wqm(ctx, bld.sop1(Builder::s_ff1_i32, bld.def(s1), Operand(exec, bld.lm)),
7336                get_ssa_temp(ctx, &instr->dest.ssa));
7337       break;
7338    }
7339    case nir_intrinsic_shader_clock:
7340       bld.smem(aco_opcode::s_memtime, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), false);
7341       emit_split_vector(ctx, get_ssa_temp(ctx, &instr->dest.ssa), 2);
7342       break;
7343    case nir_intrinsic_load_vertex_id_zero_base: {
7344       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7345       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.vertex_id));
7346       break;
7347    }
7348    case nir_intrinsic_load_first_vertex: {
7349       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7350       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.base_vertex));
7351       break;
7352    }
7353    case nir_intrinsic_load_base_instance: {
7354       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7355       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.start_instance));
7356       break;
7357    }
7358    case nir_intrinsic_load_instance_id: {
7359       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7360       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.instance_id));
7361       break;
7362    }
7363    case nir_intrinsic_load_draw_id: {
7364       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7365       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.draw_id));
7366       break;
7367    }
7368    case nir_intrinsic_load_invocation_id: {
7369       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7370
7371       if (ctx->shader->info.stage == MESA_SHADER_GEOMETRY) {
7372          if (ctx->options->chip_class >= GFX10)
7373             bld.vop2_e64(aco_opcode::v_and_b32, Definition(dst), Operand(127u), get_arg(ctx, ctx->args->ac.gs_invocation_id));
7374          else
7375             bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.gs_invocation_id));
7376       } else if (ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) {
7377          bld.vop3(aco_opcode::v_bfe_u32, Definition(dst),
7378                   get_arg(ctx, ctx->args->ac.tcs_rel_ids), Operand(8u), Operand(5u));
7379       } else {
7380          unreachable("Unsupported stage for load_invocation_id");
7381       }
7382
7383       break;
7384    }
7385    case nir_intrinsic_load_primitive_id: {
7386       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7387
7388       switch (ctx->shader->info.stage) {
7389       case MESA_SHADER_GEOMETRY:
7390          bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.gs_prim_id));
7391          break;
7392       case MESA_SHADER_TESS_CTRL:
7393          bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.tcs_patch_id));
7394          break;
7395       case MESA_SHADER_TESS_EVAL:
7396          bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.tes_patch_id));
7397          break;
7398       default:
7399          unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
7400       }
7401
7402       break;
7403    }
7404    case nir_intrinsic_load_patch_vertices_in: {
7405       assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL ||
7406              ctx->shader->info.stage == MESA_SHADER_TESS_EVAL);
7407
7408       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7409       bld.copy(Definition(dst), Operand(ctx->args->options->key.tcs.input_vertices));
7410       break;
7411    }
7412    case nir_intrinsic_emit_vertex_with_counter: {
7413       visit_emit_vertex_with_counter(ctx, instr);
7414       break;
7415    }
7416    case nir_intrinsic_end_primitive_with_counter: {
7417       unsigned stream = nir_intrinsic_stream_id(instr);
7418       bld.sopp(aco_opcode::s_sendmsg, bld.m0(ctx->gs_wave_id), -1, sendmsg_gs(true, false, stream));
7419       break;
7420    }
7421    case nir_intrinsic_set_vertex_count: {
7422       /* unused, the HW keeps track of this for us */
7423       break;
7424    }
7425    default:
7426       fprintf(stderr, "Unimplemented intrinsic instr: ");
7427       nir_print_instr(&instr->instr, stderr);
7428       fprintf(stderr, "\n");
7429       abort();
7430
7431       break;
7432    }
7433 }
7434
7435
7436 void tex_fetch_ptrs(isel_context *ctx, nir_tex_instr *instr,
7437                     Temp *res_ptr, Temp *samp_ptr, Temp *fmask_ptr,
7438                     enum glsl_base_type *stype)
7439 {
7440    nir_deref_instr *texture_deref_instr = NULL;
7441    nir_deref_instr *sampler_deref_instr = NULL;
7442    int plane = -1;
7443
7444    for (unsigned i = 0; i < instr->num_srcs; i++) {
7445       switch (instr->src[i].src_type) {
7446       case nir_tex_src_texture_deref:
7447          texture_deref_instr = nir_src_as_deref(instr->src[i].src);
7448          break;
7449       case nir_tex_src_sampler_deref:
7450          sampler_deref_instr = nir_src_as_deref(instr->src[i].src);
7451          break;
7452       case nir_tex_src_plane:
7453          plane = nir_src_as_int(instr->src[i].src);
7454          break;
7455       default:
7456          break;
7457       }
7458    }
7459
7460    *stype = glsl_get_sampler_result_type(texture_deref_instr->type);
7461
7462    if (!sampler_deref_instr)
7463       sampler_deref_instr = texture_deref_instr;
7464
7465    if (plane >= 0) {
7466       assert(instr->op != nir_texop_txf_ms &&
7467              instr->op != nir_texop_samples_identical);
7468       assert(instr->sampler_dim  != GLSL_SAMPLER_DIM_BUF);
7469       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, (aco_descriptor_type)(ACO_DESC_PLANE_0 + plane), instr, false, false);
7470    } else if (instr->sampler_dim  == GLSL_SAMPLER_DIM_BUF) {
7471       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_BUFFER, instr, false, false);
7472    } else if (instr->op == nir_texop_fragment_mask_fetch) {
7473       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_FMASK, instr, false, false);
7474    } else {
7475       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_IMAGE, instr, false, false);
7476    }
7477    if (samp_ptr) {
7478       *samp_ptr = get_sampler_desc(ctx, sampler_deref_instr, ACO_DESC_SAMPLER, instr, false, false);
7479
7480       if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT && ctx->options->chip_class < GFX8) {
7481          /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
7482          Builder bld(ctx->program, ctx->block);
7483
7484          /* to avoid unnecessary moves, we split and recombine sampler and image */
7485          Temp img[8] = {bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1),
7486                         bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1)};
7487          Temp samp[4] = {bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1)};
7488          bld.pseudo(aco_opcode::p_split_vector, Definition(img[0]), Definition(img[1]),
7489                     Definition(img[2]), Definition(img[3]), Definition(img[4]),
7490                     Definition(img[5]), Definition(img[6]), Definition(img[7]), *res_ptr);
7491          bld.pseudo(aco_opcode::p_split_vector, Definition(samp[0]), Definition(samp[1]),
7492                     Definition(samp[2]), Definition(samp[3]), *samp_ptr);
7493
7494          samp[0] = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), samp[0], img[7]);
7495          *res_ptr = bld.pseudo(aco_opcode::p_create_vector, bld.def(s8),
7496                                img[0], img[1], img[2], img[3],
7497                                img[4], img[5], img[6], img[7]);
7498          *samp_ptr = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
7499                                 samp[0], samp[1], samp[2], samp[3]);
7500       }
7501    }
7502    if (fmask_ptr && (instr->op == nir_texop_txf_ms ||
7503                      instr->op == nir_texop_samples_identical))
7504       *fmask_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_FMASK, instr, false, false);
7505 }
7506
7507 void build_cube_select(isel_context *ctx, Temp ma, Temp id, Temp deriv,
7508                        Temp *out_ma, Temp *out_sc, Temp *out_tc)
7509 {
7510    Builder bld(ctx->program, ctx->block);
7511
7512    Temp deriv_x = emit_extract_vector(ctx, deriv, 0, v1);
7513    Temp deriv_y = emit_extract_vector(ctx, deriv, 1, v1);
7514    Temp deriv_z = emit_extract_vector(ctx, deriv, 2, v1);
7515
7516    Operand neg_one(0xbf800000u);
7517    Operand one(0x3f800000u);
7518    Operand two(0x40000000u);
7519    Operand four(0x40800000u);
7520
7521    Temp is_ma_positive = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), ma);
7522    Temp sgn_ma = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), neg_one, one, is_ma_positive);
7523    Temp neg_sgn_ma = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), Operand(0u), sgn_ma);
7524
7525    Temp is_ma_z = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), four, id);
7526    Temp is_ma_y = bld.vopc(aco_opcode::v_cmp_le_f32, bld.def(bld.lm), two, id);
7527    is_ma_y = bld.sop2(Builder::s_andn2, bld.hint_vcc(bld.def(bld.lm)), is_ma_y, is_ma_z);
7528    Temp is_not_ma_x = bld.sop2(aco_opcode::s_or_b64, bld.hint_vcc(bld.def(bld.lm)), bld.def(s1, scc), is_ma_z, is_ma_y);
7529
7530    // select sc
7531    Temp tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_z, deriv_x, is_not_ma_x);
7532    Temp sgn = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1),
7533                        bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), neg_sgn_ma, sgn_ma, is_ma_z),
7534                        one, is_ma_y);
7535    *out_sc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tmp, sgn);
7536
7537    // select tc
7538    tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_y, deriv_z, is_ma_y);
7539    sgn = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), neg_one, sgn_ma, is_ma_y);
7540    *out_tc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tmp, sgn);
7541
7542    // select ma
7543    tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
7544                   bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_x, deriv_y, is_ma_y),
7545                   deriv_z, is_ma_z);
7546    tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffffu), tmp);
7547    *out_ma = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), two, tmp);
7548 }
7549
7550 void prepare_cube_coords(isel_context *ctx, std::vector<Temp>& coords, Temp* ddx, Temp* ddy, bool is_deriv, bool is_array)
7551 {
7552    Builder bld(ctx->program, ctx->block);
7553    Temp ma, tc, sc, id;
7554
7555    if (is_array) {
7556       coords[3] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coords[3]);
7557
7558       // see comment in ac_prepare_cube_coords()
7559       if (ctx->options->chip_class <= GFX8)
7560          coords[3] = bld.vop2(aco_opcode::v_max_f32, bld.def(v1), Operand(0u), coords[3]);
7561    }
7562
7563    ma = bld.vop3(aco_opcode::v_cubema_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7564
7565    aco_ptr<VOP3A_instruction> vop3a{create_instruction<VOP3A_instruction>(aco_opcode::v_rcp_f32, asVOP3(Format::VOP1), 1, 1)};
7566    vop3a->operands[0] = Operand(ma);
7567    vop3a->abs[0] = true;
7568    Temp invma = bld.tmp(v1);
7569    vop3a->definitions[0] = Definition(invma);
7570    ctx->block->instructions.emplace_back(std::move(vop3a));
7571
7572    sc = bld.vop3(aco_opcode::v_cubesc_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7573    if (!is_deriv)
7574       sc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), sc, invma, Operand(0x3fc00000u/*1.5*/));
7575
7576    tc = bld.vop3(aco_opcode::v_cubetc_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7577    if (!is_deriv)
7578       tc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), tc, invma, Operand(0x3fc00000u/*1.5*/));
7579
7580    id = bld.vop3(aco_opcode::v_cubeid_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7581
7582    if (is_deriv) {
7583       sc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), sc, invma);
7584       tc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tc, invma);
7585
7586       for (unsigned i = 0; i < 2; i++) {
7587          // see comment in ac_prepare_cube_coords()
7588          Temp deriv_ma;
7589          Temp deriv_sc, deriv_tc;
7590          build_cube_select(ctx, ma, id, i ? *ddy : *ddx,
7591                            &deriv_ma, &deriv_sc, &deriv_tc);
7592
7593          deriv_ma = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, invma);
7594
7595          Temp x = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1),
7596                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_sc, invma),
7597                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, sc));
7598          Temp y = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1),
7599                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_tc, invma),
7600                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, tc));
7601          *(i ? ddy : ddx) = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), x, y);
7602       }
7603
7604       sc = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), Operand(0x3fc00000u/*1.5*/), sc);
7605       tc = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), Operand(0x3fc00000u/*1.5*/), tc);
7606    }
7607
7608    if (is_array)
7609       id = bld.vop2(aco_opcode::v_madmk_f32, bld.def(v1), coords[3], id, Operand(0x41000000u/*8.0*/));
7610    coords.resize(3);
7611    coords[0] = sc;
7612    coords[1] = tc;
7613    coords[2] = id;
7614 }
7615
7616 void get_const_vec(nir_ssa_def *vec, nir_const_value *cv[4])
7617 {
7618    if (vec->parent_instr->type != nir_instr_type_alu)
7619       return;
7620    nir_alu_instr *vec_instr = nir_instr_as_alu(vec->parent_instr);
7621    if (vec_instr->op != nir_op_vec(vec->num_components))
7622       return;
7623
7624    for (unsigned i = 0; i < vec->num_components; i++) {
7625       cv[i] = vec_instr->src[i].swizzle[0] == 0 ?
7626               nir_src_as_const_value(vec_instr->src[i].src) : NULL;
7627    }
7628 }
7629
7630 void visit_tex(isel_context *ctx, nir_tex_instr *instr)
7631 {
7632    Builder bld(ctx->program, ctx->block);
7633    bool has_bias = false, has_lod = false, level_zero = false, has_compare = false,
7634         has_offset = false, has_ddx = false, has_ddy = false, has_derivs = false, has_sample_index = false;
7635    Temp resource, sampler, fmask_ptr, bias = Temp(), compare = Temp(), sample_index = Temp(),
7636         lod = Temp(), offset = Temp(), ddx = Temp(), ddy = Temp();
7637    std::vector<Temp> coords;
7638    std::vector<Temp> derivs;
7639    nir_const_value *sample_index_cv = NULL;
7640    nir_const_value *const_offset[4] = {NULL, NULL, NULL, NULL};
7641    enum glsl_base_type stype;
7642    tex_fetch_ptrs(ctx, instr, &resource, &sampler, &fmask_ptr, &stype);
7643
7644    bool tg4_integer_workarounds = ctx->options->chip_class <= GFX8 && instr->op == nir_texop_tg4 &&
7645                                   (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT);
7646    bool tg4_integer_cube_workaround = tg4_integer_workarounds &&
7647                                       instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
7648
7649    for (unsigned i = 0; i < instr->num_srcs; i++) {
7650       switch (instr->src[i].src_type) {
7651       case nir_tex_src_coord: {
7652          Temp coord = get_ssa_temp(ctx, instr->src[i].src.ssa);
7653          for (unsigned i = 0; i < coord.size(); i++)
7654             coords.emplace_back(emit_extract_vector(ctx, coord, i, v1));
7655          break;
7656       }
7657       case nir_tex_src_bias:
7658          if (instr->op == nir_texop_txb) {
7659             bias = get_ssa_temp(ctx, instr->src[i].src.ssa);
7660             has_bias = true;
7661          }
7662          break;
7663       case nir_tex_src_lod: {
7664          nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
7665
7666          if (val && val->f32 <= 0.0) {
7667             level_zero = true;
7668          } else {
7669             lod = get_ssa_temp(ctx, instr->src[i].src.ssa);
7670             has_lod = true;
7671          }
7672          break;
7673       }
7674       case nir_tex_src_comparator:
7675          if (instr->is_shadow) {
7676             compare = get_ssa_temp(ctx, instr->src[i].src.ssa);
7677             has_compare = true;
7678          }
7679          break;
7680       case nir_tex_src_offset:
7681          offset = get_ssa_temp(ctx, instr->src[i].src.ssa);
7682          get_const_vec(instr->src[i].src.ssa, const_offset);
7683          has_offset = true;
7684          break;
7685       case nir_tex_src_ddx:
7686          ddx = get_ssa_temp(ctx, instr->src[i].src.ssa);
7687          has_ddx = true;
7688          break;
7689       case nir_tex_src_ddy:
7690          ddy = get_ssa_temp(ctx, instr->src[i].src.ssa);
7691          has_ddy = true;
7692          break;
7693       case nir_tex_src_ms_index:
7694          sample_index = get_ssa_temp(ctx, instr->src[i].src.ssa);
7695          sample_index_cv = nir_src_as_const_value(instr->src[i].src);
7696          has_sample_index = true;
7697          break;
7698       case nir_tex_src_texture_offset:
7699       case nir_tex_src_sampler_offset:
7700       default:
7701          break;
7702       }
7703    }
7704
7705    if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
7706       return get_buffer_size(ctx, resource, get_ssa_temp(ctx, &instr->dest.ssa), true);
7707
7708    if (instr->op == nir_texop_texture_samples) {
7709       Temp dword3 = emit_extract_vector(ctx, resource, 3, s1);
7710
7711       Temp samples_log2 = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), dword3, Operand(16u | 4u<<16));
7712       Temp samples = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), Operand(1u), samples_log2);
7713       Temp type = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), dword3, Operand(28u | 4u<<16 /* offset=28, width=4 */));
7714       Temp is_msaa = bld.sopc(aco_opcode::s_cmp_ge_u32, bld.def(s1, scc), type, Operand(14u));
7715
7716       bld.sop2(aco_opcode::s_cselect_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
7717                samples, Operand(1u), bld.scc(is_msaa));
7718       return;
7719    }
7720
7721    if (has_offset && instr->op != nir_texop_txf && instr->op != nir_texop_txf_ms) {
7722       aco_ptr<Instruction> tmp_instr;
7723       Temp acc, pack = Temp();
7724
7725       uint32_t pack_const = 0;
7726       for (unsigned i = 0; i < offset.size(); i++) {
7727          if (!const_offset[i])
7728             continue;
7729          pack_const |= (const_offset[i]->u32 & 0x3Fu) << (8u * i);
7730       }
7731
7732       if (offset.type() == RegType::sgpr) {
7733          for (unsigned i = 0; i < offset.size(); i++) {
7734             if (const_offset[i])
7735                continue;
7736
7737             acc = emit_extract_vector(ctx, offset, i, s1);
7738             acc = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), acc, Operand(0x3Fu));
7739
7740             if (i) {
7741                acc = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), acc, Operand(8u * i));
7742             }
7743
7744             if (pack == Temp()) {
7745                pack = acc;
7746             } else {
7747                pack = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), pack, acc);
7748             }
7749          }
7750
7751          if (pack_const && pack != Temp())
7752             pack = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(pack_const), pack);
7753       } else {
7754          for (unsigned i = 0; i < offset.size(); i++) {
7755             if (const_offset[i])
7756                continue;
7757
7758             acc = emit_extract_vector(ctx, offset, i, v1);
7759             acc = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x3Fu), acc);
7760
7761             if (i) {
7762                acc = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(8u * i), acc);
7763             }
7764
7765             if (pack == Temp()) {
7766                pack = acc;
7767             } else {
7768                pack = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), pack, acc);
7769             }
7770          }
7771
7772          if (pack_const && pack != Temp())
7773             pack = bld.sop2(aco_opcode::v_or_b32, bld.def(v1), Operand(pack_const), pack);
7774       }
7775       if (pack_const && pack == Temp())
7776          offset = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(pack_const));
7777       else if (pack == Temp())
7778          has_offset = false;
7779       else
7780          offset = pack;
7781    }
7782
7783    if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && instr->coord_components)
7784       prepare_cube_coords(ctx, coords, &ddx, &ddy, instr->op == nir_texop_txd, instr->is_array && instr->op != nir_texop_lod);
7785
7786    /* pack derivatives */
7787    if (has_ddx || has_ddy) {
7788       if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && ctx->options->chip_class == GFX9) {
7789          assert(has_ddx && has_ddy && ddx.size() == 1 && ddy.size() == 1);
7790          Temp zero = bld.copy(bld.def(v1), Operand(0u));
7791          derivs = {ddy, zero, ddy, zero};
7792       } else {
7793          for (unsigned i = 0; has_ddx && i < ddx.size(); i++)
7794             derivs.emplace_back(emit_extract_vector(ctx, ddx, i, v1));
7795          for (unsigned i = 0; has_ddy && i < ddy.size(); i++)
7796             derivs.emplace_back(emit_extract_vector(ctx, ddy, i, v1));
7797       }
7798       has_derivs = true;
7799    }
7800
7801    if (instr->coord_components > 1 &&
7802        instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
7803        instr->is_array &&
7804        instr->op != nir_texop_txf)
7805       coords[1] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coords[1]);
7806
7807    if (instr->coord_components > 2 &&
7808       (instr->sampler_dim == GLSL_SAMPLER_DIM_2D ||
7809        instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
7810        instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS ||
7811        instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
7812        instr->is_array &&
7813        instr->op != nir_texop_txf &&
7814        instr->op != nir_texop_txf_ms &&
7815        instr->op != nir_texop_fragment_fetch &&
7816        instr->op != nir_texop_fragment_mask_fetch)
7817       coords[2] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coords[2]);
7818
7819    if (ctx->options->chip_class == GFX9 &&
7820        instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
7821        instr->op != nir_texop_lod && instr->coord_components) {
7822       assert(coords.size() > 0 && coords.size() < 3);
7823
7824       coords.insert(std::next(coords.begin()), bld.copy(bld.def(v1), instr->op == nir_texop_txf ?
7825                                                                      Operand((uint32_t) 0) :
7826                                                                      Operand((uint32_t) 0x3f000000)));
7827    }
7828
7829    bool da = should_declare_array(ctx, instr->sampler_dim, instr->is_array);
7830
7831    if (instr->op == nir_texop_samples_identical)
7832       resource = fmask_ptr;
7833
7834    else if ((instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
7835              instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
7836             instr->op != nir_texop_txs &&
7837             instr->op != nir_texop_fragment_fetch &&
7838             instr->op != nir_texop_fragment_mask_fetch) {
7839       assert(has_sample_index);
7840       Operand op(sample_index);
7841       if (sample_index_cv)
7842          op = Operand(sample_index_cv->u32);
7843       sample_index = adjust_sample_index_using_fmask(ctx, da, coords, op, fmask_ptr);
7844    }
7845
7846    if (has_offset && (instr->op == nir_texop_txf || instr->op == nir_texop_txf_ms)) {
7847       for (unsigned i = 0; i < std::min(offset.size(), instr->coord_components); i++) {
7848          Temp off = emit_extract_vector(ctx, offset, i, v1);
7849          coords[i] = bld.vadd32(bld.def(v1), coords[i], off);
7850       }
7851       has_offset = false;
7852    }
7853
7854    /* Build tex instruction */
7855    unsigned dmask = nir_ssa_def_components_read(&instr->dest.ssa);
7856    unsigned dim = ctx->options->chip_class >= GFX10 && instr->sampler_dim != GLSL_SAMPLER_DIM_BUF
7857                   ? ac_get_sampler_dim(ctx->options->chip_class, instr->sampler_dim, instr->is_array)
7858                   : 0;
7859    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7860    Temp tmp_dst = dst;
7861
7862    /* gather4 selects the component by dmask and always returns vec4 */
7863    if (instr->op == nir_texop_tg4) {
7864       assert(instr->dest.ssa.num_components == 4);
7865       if (instr->is_shadow)
7866          dmask = 1;
7867       else
7868          dmask = 1 << instr->component;
7869       if (tg4_integer_cube_workaround || dst.type() == RegType::sgpr)
7870          tmp_dst = bld.tmp(v4);
7871    } else if (instr->op == nir_texop_samples_identical) {
7872       tmp_dst = bld.tmp(v1);
7873    } else if (util_bitcount(dmask) != instr->dest.ssa.num_components || dst.type() == RegType::sgpr) {
7874       tmp_dst = bld.tmp(RegClass(RegType::vgpr, util_bitcount(dmask)));
7875    }
7876
7877    aco_ptr<MIMG_instruction> tex;
7878    if (instr->op == nir_texop_txs || instr->op == nir_texop_query_levels) {
7879       if (!has_lod)
7880          lod = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
7881
7882       bool div_by_6 = instr->op == nir_texop_txs &&
7883                       instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
7884                       instr->is_array &&
7885                       (dmask & (1 << 2));
7886       if (tmp_dst.id() == dst.id() && div_by_6)
7887          tmp_dst = bld.tmp(tmp_dst.regClass());
7888
7889       tex.reset(create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 3, 1));
7890       tex->operands[0] = Operand(resource);
7891       tex->operands[1] = Operand(s4); /* no sampler */
7892       tex->operands[2] = Operand(as_vgpr(ctx,lod));
7893       if (ctx->options->chip_class == GFX9 &&
7894           instr->op == nir_texop_txs &&
7895           instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
7896           instr->is_array) {
7897          tex->dmask = (dmask & 0x1) | ((dmask & 0x2) << 1);
7898       } else if (instr->op == nir_texop_query_levels) {
7899          tex->dmask = 1 << 3;
7900       } else {
7901          tex->dmask = dmask;
7902       }
7903       tex->da = da;
7904       tex->definitions[0] = Definition(tmp_dst);
7905       tex->dim = dim;
7906       tex->can_reorder = true;
7907       ctx->block->instructions.emplace_back(std::move(tex));
7908
7909       if (div_by_6) {
7910          /* divide 3rd value by 6 by multiplying with magic number */
7911          emit_split_vector(ctx, tmp_dst, tmp_dst.size());
7912          Temp c = bld.copy(bld.def(s1), Operand((uint32_t) 0x2AAAAAAB));
7913          Temp by_6 = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), emit_extract_vector(ctx, tmp_dst, 2, v1), c);
7914          assert(instr->dest.ssa.num_components == 3);
7915          Temp tmp = dst.type() == RegType::vgpr ? dst : bld.tmp(v3);
7916          tmp_dst = bld.pseudo(aco_opcode::p_create_vector, Definition(tmp),
7917                               emit_extract_vector(ctx, tmp_dst, 0, v1),
7918                               emit_extract_vector(ctx, tmp_dst, 1, v1),
7919                               by_6);
7920
7921       }
7922
7923       expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, dmask);
7924       return;
7925    }
7926
7927    Temp tg4_compare_cube_wa64 = Temp();
7928
7929    if (tg4_integer_workarounds) {
7930       tex.reset(create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 3, 1));
7931       tex->operands[0] = Operand(resource);
7932       tex->operands[1] = Operand(s4); /* no sampler */
7933       tex->operands[2] = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
7934       tex->dim = dim;
7935       tex->dmask = 0x3;
7936       tex->da = da;
7937       Temp size = bld.tmp(v2);
7938       tex->definitions[0] = Definition(size);
7939       tex->can_reorder = true;
7940       ctx->block->instructions.emplace_back(std::move(tex));
7941       emit_split_vector(ctx, size, size.size());
7942
7943       Temp half_texel[2];
7944       for (unsigned i = 0; i < 2; i++) {
7945          half_texel[i] = emit_extract_vector(ctx, size, i, v1);
7946          half_texel[i] = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), half_texel[i]);
7947          half_texel[i] = bld.vop1(aco_opcode::v_rcp_iflag_f32, bld.def(v1), half_texel[i]);
7948          half_texel[i] = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0xbf000000/*-0.5*/), half_texel[i]);
7949       }
7950
7951       Temp new_coords[2] = {
7952          bld.vop2(aco_opcode::v_add_f32, bld.def(v1), coords[0], half_texel[0]),
7953          bld.vop2(aco_opcode::v_add_f32, bld.def(v1), coords[1], half_texel[1])
7954       };
7955
7956       if (tg4_integer_cube_workaround) {
7957          // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
7958          Temp desc[resource.size()];
7959          aco_ptr<Instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector,
7960                                                                            Format::PSEUDO, 1, resource.size())};
7961          split->operands[0] = Operand(resource);
7962          for (unsigned i = 0; i < resource.size(); i++) {
7963             desc[i] = bld.tmp(s1);
7964             split->definitions[i] = Definition(desc[i]);
7965          }
7966          ctx->block->instructions.emplace_back(std::move(split));
7967
7968          Temp dfmt = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), desc[1], Operand(20u | (6u << 16)));
7969          Temp compare_cube_wa = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), dfmt,
7970                                          Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8));
7971
7972          Temp nfmt;
7973          if (stype == GLSL_TYPE_UINT) {
7974             nfmt = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1),
7975                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED),
7976                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT),
7977                             bld.scc(compare_cube_wa));
7978          } else {
7979             nfmt = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1),
7980                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED),
7981                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT),
7982                             bld.scc(compare_cube_wa));
7983          }
7984          tg4_compare_cube_wa64 = bld.tmp(bld.lm);
7985          bool_to_vector_condition(ctx, compare_cube_wa, tg4_compare_cube_wa64);
7986
7987          nfmt = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), nfmt, Operand(26u));
7988
7989          desc[1] = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), desc[1],
7990                             Operand((uint32_t)C_008F14_NUM_FORMAT));
7991          desc[1] = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), desc[1], nfmt);
7992
7993          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector,
7994                                                                          Format::PSEUDO, resource.size(), 1)};
7995          for (unsigned i = 0; i < resource.size(); i++)
7996             vec->operands[i] = Operand(desc[i]);
7997          resource = bld.tmp(resource.regClass());
7998          vec->definitions[0] = Definition(resource);
7999          ctx->block->instructions.emplace_back(std::move(vec));
8000
8001          new_coords[0] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
8002                                   new_coords[0], coords[0], tg4_compare_cube_wa64);
8003          new_coords[1] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
8004                                   new_coords[1], coords[1], tg4_compare_cube_wa64);
8005       }
8006       coords[0] = new_coords[0];
8007       coords[1] = new_coords[1];
8008    }
8009
8010    if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
8011       //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8012
8013       assert(coords.size() == 1);
8014       unsigned last_bit = util_last_bit(nir_ssa_def_components_read(&instr->dest.ssa));
8015       aco_opcode op;
8016       switch (last_bit) {
8017       case 1:
8018          op = aco_opcode::buffer_load_format_x; break;
8019       case 2:
8020          op = aco_opcode::buffer_load_format_xy; break;
8021       case 3:
8022          op = aco_opcode::buffer_load_format_xyz; break;
8023       case 4:
8024          op = aco_opcode::buffer_load_format_xyzw; break;
8025       default:
8026          unreachable("Tex instruction loads more than 4 components.");
8027       }
8028
8029       /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8030       if (last_bit == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
8031          tmp_dst = dst;
8032       else
8033          tmp_dst = bld.tmp(RegType::vgpr, last_bit);
8034
8035       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
8036       mubuf->operands[0] = Operand(resource);
8037       mubuf->operands[1] = Operand(coords[0]);
8038       mubuf->operands[2] = Operand((uint32_t) 0);
8039       mubuf->definitions[0] = Definition(tmp_dst);
8040       mubuf->idxen = true;
8041       mubuf->can_reorder = true;
8042       ctx->block->instructions.emplace_back(std::move(mubuf));
8043
8044       expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, (1 << last_bit) - 1);
8045       return;
8046    }
8047
8048    /* gather MIMG address components */
8049    std::vector<Temp> args;
8050    if (has_offset)
8051       args.emplace_back(offset);
8052    if (has_bias)
8053       args.emplace_back(bias);
8054    if (has_compare)
8055       args.emplace_back(compare);
8056    if (has_derivs)
8057       args.insert(args.end(), derivs.begin(), derivs.end());
8058
8059    args.insert(args.end(), coords.begin(), coords.end());
8060    if (has_sample_index)
8061       args.emplace_back(sample_index);
8062    if (has_lod)
8063       args.emplace_back(lod);
8064
8065    Temp arg = bld.tmp(RegClass(RegType::vgpr, args.size()));
8066    aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, args.size(), 1)};
8067    vec->definitions[0] = Definition(arg);
8068    for (unsigned i = 0; i < args.size(); i++)
8069       vec->operands[i] = Operand(args[i]);
8070    ctx->block->instructions.emplace_back(std::move(vec));
8071
8072
8073    if (instr->op == nir_texop_txf ||
8074        instr->op == nir_texop_txf_ms ||
8075        instr->op == nir_texop_samples_identical ||
8076        instr->op == nir_texop_fragment_fetch ||
8077        instr->op == nir_texop_fragment_mask_fetch) {
8078       aco_opcode op = level_zero || instr->sampler_dim == GLSL_SAMPLER_DIM_MS || instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS ? aco_opcode::image_load : aco_opcode::image_load_mip;
8079       tex.reset(create_instruction<MIMG_instruction>(op, Format::MIMG, 3, 1));
8080       tex->operands[0] = Operand(resource);
8081       tex->operands[1] = Operand(s4); /* no sampler */
8082       tex->operands[2] = Operand(arg);
8083       tex->dim = dim;
8084       tex->dmask = dmask;
8085       tex->unrm = true;
8086       tex->da = da;
8087       tex->definitions[0] = Definition(tmp_dst);
8088       tex->can_reorder = true;
8089       ctx->block->instructions.emplace_back(std::move(tex));
8090
8091       if (instr->op == nir_texop_samples_identical) {
8092          assert(dmask == 1 && dst.regClass() == v1);
8093          assert(dst.id() != tmp_dst.id());
8094
8095          Temp tmp = bld.tmp(bld.lm);
8096          bld.vopc(aco_opcode::v_cmp_eq_u32, Definition(tmp), Operand(0u), tmp_dst).def(0).setHint(vcc);
8097          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand((uint32_t)-1), tmp);
8098
8099       } else {
8100          expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, dmask);
8101       }
8102       return;
8103    }
8104
8105    // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8106    aco_opcode opcode = aco_opcode::image_sample;
8107    if (has_offset) { /* image_sample_*_o */
8108       if (has_compare) {
8109          opcode = aco_opcode::image_sample_c_o;
8110          if (has_derivs)
8111             opcode = aco_opcode::image_sample_c_d_o;
8112          if (has_bias)
8113             opcode = aco_opcode::image_sample_c_b_o;
8114          if (level_zero)
8115             opcode = aco_opcode::image_sample_c_lz_o;
8116          if (has_lod)
8117             opcode = aco_opcode::image_sample_c_l_o;
8118       } else {
8119          opcode = aco_opcode::image_sample_o;
8120          if (has_derivs)
8121             opcode = aco_opcode::image_sample_d_o;
8122          if (has_bias)
8123             opcode = aco_opcode::image_sample_b_o;
8124          if (level_zero)
8125             opcode = aco_opcode::image_sample_lz_o;
8126          if (has_lod)
8127             opcode = aco_opcode::image_sample_l_o;
8128       }
8129    } else { /* no offset */
8130       if (has_compare) {
8131          opcode = aco_opcode::image_sample_c;
8132          if (has_derivs)
8133             opcode = aco_opcode::image_sample_c_d;
8134          if (has_bias)
8135             opcode = aco_opcode::image_sample_c_b;
8136          if (level_zero)
8137             opcode = aco_opcode::image_sample_c_lz;
8138          if (has_lod)
8139             opcode = aco_opcode::image_sample_c_l;
8140       } else {
8141          opcode = aco_opcode::image_sample;
8142          if (has_derivs)
8143             opcode = aco_opcode::image_sample_d;
8144          if (has_bias)
8145             opcode = aco_opcode::image_sample_b;
8146          if (level_zero)
8147             opcode = aco_opcode::image_sample_lz;
8148          if (has_lod)
8149             opcode = aco_opcode::image_sample_l;
8150       }
8151    }
8152
8153    if (instr->op == nir_texop_tg4) {
8154       if (has_offset) {
8155          opcode = aco_opcode::image_gather4_lz_o;
8156          if (has_compare)
8157             opcode = aco_opcode::image_gather4_c_lz_o;
8158       } else {
8159          opcode = aco_opcode::image_gather4_lz;
8160          if (has_compare)
8161             opcode = aco_opcode::image_gather4_c_lz;
8162       }
8163    } else if (instr->op == nir_texop_lod) {
8164       opcode = aco_opcode::image_get_lod;
8165    }
8166
8167    /* we don't need the bias, sample index, compare value or offset to be
8168     * computed in WQM but if the p_create_vector copies the coordinates, then it
8169     * needs to be in WQM */
8170    if (ctx->stage == fragment_fs &&
8171        !has_derivs && !has_lod && !level_zero &&
8172        instr->sampler_dim != GLSL_SAMPLER_DIM_MS &&
8173        instr->sampler_dim != GLSL_SAMPLER_DIM_SUBPASS_MS)
8174       arg = emit_wqm(ctx, arg, bld.tmp(arg.regClass()), true);
8175
8176    tex.reset(create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 1));
8177    tex->operands[0] = Operand(resource);
8178    tex->operands[1] = Operand(sampler);
8179    tex->operands[2] = Operand(arg);
8180    tex->dim = dim;
8181    tex->dmask = dmask;
8182    tex->da = da;
8183    tex->definitions[0] = Definition(tmp_dst);
8184    tex->can_reorder = true;
8185    ctx->block->instructions.emplace_back(std::move(tex));
8186
8187    if (tg4_integer_cube_workaround) {
8188       assert(tmp_dst.id() != dst.id());
8189       assert(tmp_dst.size() == dst.size() && dst.size() == 4);
8190
8191       emit_split_vector(ctx, tmp_dst, tmp_dst.size());
8192       Temp val[4];
8193       for (unsigned i = 0; i < dst.size(); i++) {
8194          val[i] = emit_extract_vector(ctx, tmp_dst, i, v1);
8195          Temp cvt_val;
8196          if (stype == GLSL_TYPE_UINT)
8197             cvt_val = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), val[i]);
8198          else
8199             cvt_val = bld.vop1(aco_opcode::v_cvt_i32_f32, bld.def(v1), val[i]);
8200          val[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), val[i], cvt_val, tg4_compare_cube_wa64);
8201       }
8202       Temp tmp = dst.regClass() == v4 ? dst : bld.tmp(v4);
8203       tmp_dst = bld.pseudo(aco_opcode::p_create_vector, Definition(tmp),
8204                            val[0], val[1], val[2], val[3]);
8205    }
8206    unsigned mask = instr->op == nir_texop_tg4 ? 0xF : dmask;
8207    expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, mask);
8208
8209 }
8210
8211
8212 Operand get_phi_operand(isel_context *ctx, nir_ssa_def *ssa)
8213 {
8214    Temp tmp = get_ssa_temp(ctx, ssa);
8215    if (ssa->parent_instr->type == nir_instr_type_ssa_undef)
8216       return Operand(tmp.regClass());
8217    else
8218       return Operand(tmp);
8219 }
8220
8221 void visit_phi(isel_context *ctx, nir_phi_instr *instr)
8222 {
8223    aco_ptr<Pseudo_instruction> phi;
8224    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
8225    assert(instr->dest.ssa.bit_size != 1 || dst.regClass() == ctx->program->lane_mask);
8226
8227    bool logical = !dst.is_linear() || ctx->divergent_vals[instr->dest.ssa.index];
8228    logical |= ctx->block->kind & block_kind_merge;
8229    aco_opcode opcode = logical ? aco_opcode::p_phi : aco_opcode::p_linear_phi;
8230
8231    /* we want a sorted list of sources, since the predecessor list is also sorted */
8232    std::map<unsigned, nir_ssa_def*> phi_src;
8233    nir_foreach_phi_src(src, instr)
8234       phi_src[src->pred->index] = src->src.ssa;
8235
8236    std::vector<unsigned>& preds = logical ? ctx->block->logical_preds : ctx->block->linear_preds;
8237    unsigned num_operands = 0;
8238    Operand operands[std::max(exec_list_length(&instr->srcs), (unsigned)preds.size()) + 1];
8239    unsigned num_defined = 0;
8240    unsigned cur_pred_idx = 0;
8241    for (std::pair<unsigned, nir_ssa_def *> src : phi_src) {
8242       if (cur_pred_idx < preds.size()) {
8243          /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8244          unsigned block = ctx->cf_info.nir_to_aco[src.first];
8245          unsigned skipped = 0;
8246          while (cur_pred_idx + skipped < preds.size() && preds[cur_pred_idx + skipped] != block)
8247             skipped++;
8248          if (cur_pred_idx + skipped < preds.size()) {
8249             for (unsigned i = 0; i < skipped; i++)
8250                operands[num_operands++] = Operand(dst.regClass());
8251             cur_pred_idx += skipped;
8252          } else {
8253             continue;
8254          }
8255       }
8256       /* Handle missing predecessors at the end. This shouldn't happen with loop
8257        * headers and we can't ignore these sources for loop header phis. */
8258       if (!(ctx->block->kind & block_kind_loop_header) && cur_pred_idx >= preds.size())
8259          continue;
8260       cur_pred_idx++;
8261       Operand op = get_phi_operand(ctx, src.second);
8262       operands[num_operands++] = op;
8263       num_defined += !op.isUndefined();
8264    }
8265    /* handle block_kind_continue_or_break at loop exit blocks */
8266    while (cur_pred_idx++ < preds.size())
8267       operands[num_operands++] = Operand(dst.regClass());
8268
8269    /* If the loop ends with a break, still add a linear continue edge in case
8270     * that break is divergent or continue_or_break is used. We'll either remove
8271     * this operand later in visit_loop() if it's not necessary or replace the
8272     * undef with something correct. */
8273    if (!logical && ctx->block->kind & block_kind_loop_header) {
8274       nir_loop *loop = nir_cf_node_as_loop(instr->instr.block->cf_node.parent);
8275       nir_block *last = nir_loop_last_block(loop);
8276       if (last->successors[0] != instr->instr.block)
8277          operands[num_operands++] = Operand(RegClass());
8278    }
8279
8280    if (num_defined == 0) {
8281       Builder bld(ctx->program, ctx->block);
8282       if (dst.regClass() == s1) {
8283          bld.sop1(aco_opcode::s_mov_b32, Definition(dst), Operand(0u));
8284       } else if (dst.regClass() == v1) {
8285          bld.vop1(aco_opcode::v_mov_b32, Definition(dst), Operand(0u));
8286       } else {
8287          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
8288          for (unsigned i = 0; i < dst.size(); i++)
8289             vec->operands[i] = Operand(0u);
8290          vec->definitions[0] = Definition(dst);
8291          ctx->block->instructions.emplace_back(std::move(vec));
8292       }
8293       return;
8294    }
8295
8296    /* we can use a linear phi in some cases if one src is undef */
8297    if (dst.is_linear() && ctx->block->kind & block_kind_merge && num_defined == 1) {
8298       phi.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_linear_phi, Format::PSEUDO, num_operands, 1));
8299
8300       Block *linear_else = &ctx->program->blocks[ctx->block->linear_preds[1]];
8301       Block *invert = &ctx->program->blocks[linear_else->linear_preds[0]];
8302       assert(invert->kind & block_kind_invert);
8303
8304       unsigned then_block = invert->linear_preds[0];
8305
8306       Block* insert_block = NULL;
8307       for (unsigned i = 0; i < num_operands; i++) {
8308          Operand op = operands[i];
8309          if (op.isUndefined())
8310             continue;
8311          insert_block = ctx->block->logical_preds[i] == then_block ? invert : ctx->block;
8312          phi->operands[0] = op;
8313          break;
8314       }
8315       assert(insert_block); /* should be handled by the "num_defined == 0" case above */
8316       phi->operands[1] = Operand(dst.regClass());
8317       phi->definitions[0] = Definition(dst);
8318       insert_block->instructions.emplace(insert_block->instructions.begin(), std::move(phi));
8319       return;
8320    }
8321
8322    /* try to scalarize vector phis */
8323    if (instr->dest.ssa.bit_size != 1 && dst.size() > 1) {
8324       // TODO: scalarize linear phis on divergent ifs
8325       bool can_scalarize = (opcode == aco_opcode::p_phi || !(ctx->block->kind & block_kind_merge));
8326       std::array<Temp, NIR_MAX_VEC_COMPONENTS> new_vec;
8327       for (unsigned i = 0; can_scalarize && (i < num_operands); i++) {
8328          Operand src = operands[i];
8329          if (src.isTemp() && ctx->allocated_vec.find(src.tempId()) == ctx->allocated_vec.end())
8330             can_scalarize = false;
8331       }
8332       if (can_scalarize) {
8333          unsigned num_components = instr->dest.ssa.num_components;
8334          assert(dst.size() % num_components == 0);
8335          RegClass rc = RegClass(dst.type(), dst.size() / num_components);
8336
8337          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1)};
8338          for (unsigned k = 0; k < num_components; k++) {
8339             phi.reset(create_instruction<Pseudo_instruction>(opcode, Format::PSEUDO, num_operands, 1));
8340             for (unsigned i = 0; i < num_operands; i++) {
8341                Operand src = operands[i];
8342                phi->operands[i] = src.isTemp() ? Operand(ctx->allocated_vec[src.tempId()][k]) : Operand(rc);
8343             }
8344             Temp phi_dst = {ctx->program->allocateId(), rc};
8345             phi->definitions[0] = Definition(phi_dst);
8346             ctx->block->instructions.emplace(ctx->block->instructions.begin(), std::move(phi));
8347             new_vec[k] = phi_dst;
8348             vec->operands[k] = Operand(phi_dst);
8349          }
8350          vec->definitions[0] = Definition(dst);
8351          ctx->block->instructions.emplace_back(std::move(vec));
8352          ctx->allocated_vec.emplace(dst.id(), new_vec);
8353          return;
8354       }
8355    }
8356
8357    phi.reset(create_instruction<Pseudo_instruction>(opcode, Format::PSEUDO, num_operands, 1));
8358    for (unsigned i = 0; i < num_operands; i++)
8359       phi->operands[i] = operands[i];
8360    phi->definitions[0] = Definition(dst);
8361    ctx->block->instructions.emplace(ctx->block->instructions.begin(), std::move(phi));
8362 }
8363
8364
8365 void visit_undef(isel_context *ctx, nir_ssa_undef_instr *instr)
8366 {
8367    Temp dst = get_ssa_temp(ctx, &instr->def);
8368
8369    assert(dst.type() == RegType::sgpr);
8370
8371    if (dst.size() == 1) {
8372       Builder(ctx->program, ctx->block).copy(Definition(dst), Operand(0u));
8373    } else {
8374       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
8375       for (unsigned i = 0; i < dst.size(); i++)
8376          vec->operands[i] = Operand(0u);
8377       vec->definitions[0] = Definition(dst);
8378       ctx->block->instructions.emplace_back(std::move(vec));
8379    }
8380 }
8381
8382 void visit_jump(isel_context *ctx, nir_jump_instr *instr)
8383 {
8384    Builder bld(ctx->program, ctx->block);
8385    Block *logical_target;
8386    append_logical_end(ctx->block);
8387    unsigned idx = ctx->block->index;
8388
8389    switch (instr->type) {
8390    case nir_jump_break:
8391       logical_target = ctx->cf_info.parent_loop.exit;
8392       add_logical_edge(idx, logical_target);
8393       ctx->block->kind |= block_kind_break;
8394
8395       if (!ctx->cf_info.parent_if.is_divergent &&
8396           !ctx->cf_info.parent_loop.has_divergent_continue) {
8397          /* uniform break - directly jump out of the loop */
8398          ctx->block->kind |= block_kind_uniform;
8399          ctx->cf_info.has_branch = true;
8400          bld.branch(aco_opcode::p_branch);
8401          add_linear_edge(idx, logical_target);
8402          return;
8403       }
8404       ctx->cf_info.parent_loop.has_divergent_branch = true;
8405       ctx->cf_info.nir_to_aco[instr->instr.block->index] = ctx->block->index;
8406       break;
8407    case nir_jump_continue:
8408       logical_target = &ctx->program->blocks[ctx->cf_info.parent_loop.header_idx];
8409       add_logical_edge(idx, logical_target);
8410       ctx->block->kind |= block_kind_continue;
8411
8412       if (ctx->cf_info.parent_if.is_divergent) {
8413          /* for potential uniform breaks after this continue,
8414             we must ensure that they are handled correctly */
8415          ctx->cf_info.parent_loop.has_divergent_continue = true;
8416          ctx->cf_info.parent_loop.has_divergent_branch = true;
8417          ctx->cf_info.nir_to_aco[instr->instr.block->index] = ctx->block->index;
8418       } else {
8419          /* uniform continue - directly jump to the loop header */
8420          ctx->block->kind |= block_kind_uniform;
8421          ctx->cf_info.has_branch = true;
8422          bld.branch(aco_opcode::p_branch);
8423          add_linear_edge(idx, logical_target);
8424          return;
8425       }
8426       break;
8427    default:
8428       fprintf(stderr, "Unknown NIR jump instr: ");
8429       nir_print_instr(&instr->instr, stderr);
8430       fprintf(stderr, "\n");
8431       abort();
8432    }
8433
8434    if (ctx->cf_info.parent_if.is_divergent && !ctx->cf_info.exec_potentially_empty_break) {
8435       ctx->cf_info.exec_potentially_empty_break = true;
8436       ctx->cf_info.exec_potentially_empty_break_depth = ctx->cf_info.loop_nest_depth;
8437    }
8438
8439    /* remove critical edges from linear CFG */
8440    bld.branch(aco_opcode::p_branch);
8441    Block* break_block = ctx->program->create_and_insert_block();
8442    break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8443    break_block->kind |= block_kind_uniform;
8444    add_linear_edge(idx, break_block);
8445    /* the loop_header pointer might be invalidated by this point */
8446    if (instr->type == nir_jump_continue)
8447       logical_target = &ctx->program->blocks[ctx->cf_info.parent_loop.header_idx];
8448    add_linear_edge(break_block->index, logical_target);
8449    bld.reset(break_block);
8450    bld.branch(aco_opcode::p_branch);
8451
8452    Block* continue_block = ctx->program->create_and_insert_block();
8453    continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8454    add_linear_edge(idx, continue_block);
8455    append_logical_start(continue_block);
8456    ctx->block = continue_block;
8457    return;
8458 }
8459
8460 void visit_block(isel_context *ctx, nir_block *block)
8461 {
8462    nir_foreach_instr(instr, block) {
8463       switch (instr->type) {
8464       case nir_instr_type_alu:
8465          visit_alu_instr(ctx, nir_instr_as_alu(instr));
8466          break;
8467       case nir_instr_type_load_const:
8468          visit_load_const(ctx, nir_instr_as_load_const(instr));
8469          break;
8470       case nir_instr_type_intrinsic:
8471          visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
8472          break;
8473       case nir_instr_type_tex:
8474          visit_tex(ctx, nir_instr_as_tex(instr));
8475          break;
8476       case nir_instr_type_phi:
8477          visit_phi(ctx, nir_instr_as_phi(instr));
8478          break;
8479       case nir_instr_type_ssa_undef:
8480          visit_undef(ctx, nir_instr_as_ssa_undef(instr));
8481          break;
8482       case nir_instr_type_deref:
8483          break;
8484       case nir_instr_type_jump:
8485          visit_jump(ctx, nir_instr_as_jump(instr));
8486          break;
8487       default:
8488          fprintf(stderr, "Unknown NIR instr type: ");
8489          nir_print_instr(instr, stderr);
8490          fprintf(stderr, "\n");
8491          //abort();
8492       }
8493    }
8494
8495    if (!ctx->cf_info.parent_loop.has_divergent_branch)
8496       ctx->cf_info.nir_to_aco[block->index] = ctx->block->index;
8497 }
8498
8499
8500
8501 static Operand create_continue_phis(isel_context *ctx, unsigned first, unsigned last,
8502                                     aco_ptr<Instruction>& header_phi, Operand *vals)
8503 {
8504    vals[0] = Operand(header_phi->definitions[0].getTemp());
8505    RegClass rc = vals[0].regClass();
8506
8507    unsigned loop_nest_depth = ctx->program->blocks[first].loop_nest_depth;
8508
8509    unsigned next_pred = 1;
8510
8511    for (unsigned idx = first + 1; idx <= last; idx++) {
8512       Block& block = ctx->program->blocks[idx];
8513       if (block.loop_nest_depth != loop_nest_depth) {
8514          vals[idx - first] = vals[idx - 1 - first];
8515          continue;
8516       }
8517
8518       if (block.kind & block_kind_continue) {
8519          vals[idx - first] = header_phi->operands[next_pred];
8520          next_pred++;
8521          continue;
8522       }
8523
8524       bool all_same = true;
8525       for (unsigned i = 1; all_same && (i < block.linear_preds.size()); i++)
8526          all_same = vals[block.linear_preds[i] - first] == vals[block.linear_preds[0] - first];
8527
8528       Operand val;
8529       if (all_same) {
8530          val = vals[block.linear_preds[0] - first];
8531       } else {
8532          aco_ptr<Instruction> phi(create_instruction<Pseudo_instruction>(
8533             aco_opcode::p_linear_phi, Format::PSEUDO, block.linear_preds.size(), 1));
8534          for (unsigned i = 0; i < block.linear_preds.size(); i++)
8535             phi->operands[i] = vals[block.linear_preds[i] - first];
8536          val = Operand(Temp(ctx->program->allocateId(), rc));
8537          phi->definitions[0] = Definition(val.getTemp());
8538          block.instructions.emplace(block.instructions.begin(), std::move(phi));
8539       }
8540       vals[idx - first] = val;
8541    }
8542
8543    return vals[last - first];
8544 }
8545
8546 static void visit_loop(isel_context *ctx, nir_loop *loop)
8547 {
8548    //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
8549    append_logical_end(ctx->block);
8550    ctx->block->kind |= block_kind_loop_preheader | block_kind_uniform;
8551    Builder bld(ctx->program, ctx->block);
8552    bld.branch(aco_opcode::p_branch);
8553    unsigned loop_preheader_idx = ctx->block->index;
8554
8555    Block loop_exit = Block();
8556    loop_exit.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8557    loop_exit.kind |= (block_kind_loop_exit | (ctx->block->kind & block_kind_top_level));
8558
8559    Block* loop_header = ctx->program->create_and_insert_block();
8560    loop_header->loop_nest_depth = ctx->cf_info.loop_nest_depth + 1;
8561    loop_header->kind |= block_kind_loop_header;
8562    add_edge(loop_preheader_idx, loop_header);
8563    ctx->block = loop_header;
8564
8565    /* emit loop body */
8566    unsigned loop_header_idx = loop_header->index;
8567    loop_info_RAII loop_raii(ctx, loop_header_idx, &loop_exit);
8568    append_logical_start(ctx->block);
8569    visit_cf_list(ctx, &loop->body);
8570
8571    //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
8572    if (!ctx->cf_info.has_branch) {
8573       append_logical_end(ctx->block);
8574       if (ctx->cf_info.exec_potentially_empty_discard || ctx->cf_info.exec_potentially_empty_break) {
8575          /* Discards can result in code running with an empty exec mask.
8576           * This would result in divergent breaks not ever being taken. As a
8577           * workaround, break the loop when the loop mask is empty instead of
8578           * always continuing. */
8579          ctx->block->kind |= (block_kind_continue_or_break | block_kind_uniform);
8580          unsigned block_idx = ctx->block->index;
8581
8582          /* create helper blocks to avoid critical edges */
8583          Block *break_block = ctx->program->create_and_insert_block();
8584          break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8585          break_block->kind = block_kind_uniform;
8586          bld.reset(break_block);
8587          bld.branch(aco_opcode::p_branch);
8588          add_linear_edge(block_idx, break_block);
8589          add_linear_edge(break_block->index, &loop_exit);
8590
8591          Block *continue_block = ctx->program->create_and_insert_block();
8592          continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8593          continue_block->kind = block_kind_uniform;
8594          bld.reset(continue_block);
8595          bld.branch(aco_opcode::p_branch);
8596          add_linear_edge(block_idx, continue_block);
8597          add_linear_edge(continue_block->index, &ctx->program->blocks[loop_header_idx]);
8598
8599          if (!ctx->cf_info.parent_loop.has_divergent_branch)
8600             add_logical_edge(block_idx, &ctx->program->blocks[loop_header_idx]);
8601          ctx->block = &ctx->program->blocks[block_idx];
8602       } else {
8603          ctx->block->kind |= (block_kind_continue | block_kind_uniform);
8604          if (!ctx->cf_info.parent_loop.has_divergent_branch)
8605             add_edge(ctx->block->index, &ctx->program->blocks[loop_header_idx]);
8606          else
8607             add_linear_edge(ctx->block->index, &ctx->program->blocks[loop_header_idx]);
8608       }
8609
8610       bld.reset(ctx->block);
8611       bld.branch(aco_opcode::p_branch);
8612    }
8613
8614    /* fixup phis in loop header from unreachable blocks */
8615    if (ctx->cf_info.has_branch || ctx->cf_info.parent_loop.has_divergent_branch) {
8616       bool linear = ctx->cf_info.has_branch;
8617       bool logical = ctx->cf_info.has_branch || ctx->cf_info.parent_loop.has_divergent_branch;
8618       for (aco_ptr<Instruction>& instr : ctx->program->blocks[loop_header_idx].instructions) {
8619          if ((logical && instr->opcode == aco_opcode::p_phi) ||
8620              (linear && instr->opcode == aco_opcode::p_linear_phi)) {
8621             /* the last operand should be the one that needs to be removed */
8622             instr->operands.pop_back();
8623          } else if (!is_phi(instr)) {
8624             break;
8625          }
8626       }
8627    }
8628
8629    /* Fixup linear phis in loop header from expecting a continue. Both this fixup
8630     * and the previous one shouldn't both happen at once because a break in the
8631     * merge block would get CSE'd */
8632    if (nir_loop_last_block(loop)->successors[0] != nir_loop_first_block(loop)) {
8633       unsigned num_vals = ctx->cf_info.has_branch ? 1 : (ctx->block->index - loop_header_idx + 1);
8634       Operand vals[num_vals];
8635       for (aco_ptr<Instruction>& instr : ctx->program->blocks[loop_header_idx].instructions) {
8636          if (instr->opcode == aco_opcode::p_linear_phi) {
8637             if (ctx->cf_info.has_branch)
8638                instr->operands.pop_back();
8639             else
8640                instr->operands.back() = create_continue_phis(ctx, loop_header_idx, ctx->block->index, instr, vals);
8641          } else if (!is_phi(instr)) {
8642             break;
8643          }
8644       }
8645    }
8646
8647    ctx->cf_info.has_branch = false;
8648
8649    // TODO: if the loop has not a single exit, we must add one °°
8650    /* emit loop successor block */
8651    ctx->block = ctx->program->insert_block(std::move(loop_exit));
8652    append_logical_start(ctx->block);
8653
8654    #if 0
8655    // TODO: check if it is beneficial to not branch on continues
8656    /* trim linear phis in loop header */
8657    for (auto&& instr : loop_entry->instructions) {
8658       if (instr->opcode == aco_opcode::p_linear_phi) {
8659          aco_ptr<Pseudo_instruction> new_phi{create_instruction<Pseudo_instruction>(aco_opcode::p_linear_phi, Format::PSEUDO, loop_entry->linear_predecessors.size(), 1)};
8660          new_phi->definitions[0] = instr->definitions[0];
8661          for (unsigned i = 0; i < new_phi->operands.size(); i++)
8662             new_phi->operands[i] = instr->operands[i];
8663          /* check that the remaining operands are all the same */
8664          for (unsigned i = new_phi->operands.size(); i < instr->operands.size(); i++)
8665             assert(instr->operands[i].tempId() == instr->operands.back().tempId());
8666          instr.swap(new_phi);
8667       } else if (instr->opcode == aco_opcode::p_phi) {
8668          continue;
8669       } else {
8670          break;
8671       }
8672    }
8673    #endif
8674 }
8675
8676 static void begin_divergent_if_then(isel_context *ctx, if_context *ic, Temp cond)
8677 {
8678    ic->cond = cond;
8679
8680    append_logical_end(ctx->block);
8681    ctx->block->kind |= block_kind_branch;
8682
8683    /* branch to linear then block */
8684    assert(cond.regClass() == ctx->program->lane_mask);
8685    aco_ptr<Pseudo_branch_instruction> branch;
8686    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_z, Format::PSEUDO_BRANCH, 1, 0));
8687    branch->operands[0] = Operand(cond);
8688    ctx->block->instructions.push_back(std::move(branch));
8689
8690    ic->BB_if_idx = ctx->block->index;
8691    ic->BB_invert = Block();
8692    ic->BB_invert.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8693    /* Invert blocks are intentionally not marked as top level because they
8694     * are not part of the logical cfg. */
8695    ic->BB_invert.kind |= block_kind_invert;
8696    ic->BB_endif = Block();
8697    ic->BB_endif.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8698    ic->BB_endif.kind |= (block_kind_merge | (ctx->block->kind & block_kind_top_level));
8699
8700    ic->exec_potentially_empty_discard_old = ctx->cf_info.exec_potentially_empty_discard;
8701    ic->exec_potentially_empty_break_old = ctx->cf_info.exec_potentially_empty_break;
8702    ic->exec_potentially_empty_break_depth_old = ctx->cf_info.exec_potentially_empty_break_depth;
8703    ic->divergent_old = ctx->cf_info.parent_if.is_divergent;
8704    ctx->cf_info.parent_if.is_divergent = true;
8705
8706    /* divergent branches use cbranch_execz */
8707    ctx->cf_info.exec_potentially_empty_discard = false;
8708    ctx->cf_info.exec_potentially_empty_break = false;
8709    ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8710
8711    /** emit logical then block */
8712    Block* BB_then_logical = ctx->program->create_and_insert_block();
8713    BB_then_logical->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8714    add_edge(ic->BB_if_idx, BB_then_logical);
8715    ctx->block = BB_then_logical;
8716    append_logical_start(BB_then_logical);
8717 }
8718
8719 static void begin_divergent_if_else(isel_context *ctx, if_context *ic)
8720 {
8721    Block *BB_then_logical = ctx->block;
8722    append_logical_end(BB_then_logical);
8723     /* branch from logical then block to invert block */
8724    aco_ptr<Pseudo_branch_instruction> branch;
8725    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8726    BB_then_logical->instructions.emplace_back(std::move(branch));
8727    add_linear_edge(BB_then_logical->index, &ic->BB_invert);
8728    if (!ctx->cf_info.parent_loop.has_divergent_branch)
8729       add_logical_edge(BB_then_logical->index, &ic->BB_endif);
8730    BB_then_logical->kind |= block_kind_uniform;
8731    assert(!ctx->cf_info.has_branch);
8732    ic->then_branch_divergent = ctx->cf_info.parent_loop.has_divergent_branch;
8733    ctx->cf_info.parent_loop.has_divergent_branch = false;
8734
8735    /** emit linear then block */
8736    Block* BB_then_linear = ctx->program->create_and_insert_block();
8737    BB_then_linear->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8738    BB_then_linear->kind |= block_kind_uniform;
8739    add_linear_edge(ic->BB_if_idx, BB_then_linear);
8740    /* branch from linear then block to invert block */
8741    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8742    BB_then_linear->instructions.emplace_back(std::move(branch));
8743    add_linear_edge(BB_then_linear->index, &ic->BB_invert);
8744
8745    /** emit invert merge block */
8746    ctx->block = ctx->program->insert_block(std::move(ic->BB_invert));
8747    ic->invert_idx = ctx->block->index;
8748
8749    /* branch to linear else block (skip else) */
8750    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_nz, Format::PSEUDO_BRANCH, 1, 0));
8751    branch->operands[0] = Operand(ic->cond);
8752    ctx->block->instructions.push_back(std::move(branch));
8753
8754    ic->exec_potentially_empty_discard_old |= ctx->cf_info.exec_potentially_empty_discard;
8755    ic->exec_potentially_empty_break_old |= ctx->cf_info.exec_potentially_empty_break;
8756    ic->exec_potentially_empty_break_depth_old =
8757       std::min(ic->exec_potentially_empty_break_depth_old, ctx->cf_info.exec_potentially_empty_break_depth);
8758    /* divergent branches use cbranch_execz */
8759    ctx->cf_info.exec_potentially_empty_discard = false;
8760    ctx->cf_info.exec_potentially_empty_break = false;
8761    ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8762
8763    /** emit logical else block */
8764    Block* BB_else_logical = ctx->program->create_and_insert_block();
8765    BB_else_logical->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8766    add_logical_edge(ic->BB_if_idx, BB_else_logical);
8767    add_linear_edge(ic->invert_idx, BB_else_logical);
8768    ctx->block = BB_else_logical;
8769    append_logical_start(BB_else_logical);
8770 }
8771
8772 static void end_divergent_if(isel_context *ctx, if_context *ic)
8773 {
8774    Block *BB_else_logical = ctx->block;
8775    append_logical_end(BB_else_logical);
8776
8777    /* branch from logical else block to endif block */
8778    aco_ptr<Pseudo_branch_instruction> branch;
8779    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8780    BB_else_logical->instructions.emplace_back(std::move(branch));
8781    add_linear_edge(BB_else_logical->index, &ic->BB_endif);
8782    if (!ctx->cf_info.parent_loop.has_divergent_branch)
8783       add_logical_edge(BB_else_logical->index, &ic->BB_endif);
8784    BB_else_logical->kind |= block_kind_uniform;
8785
8786    assert(!ctx->cf_info.has_branch);
8787    ctx->cf_info.parent_loop.has_divergent_branch &= ic->then_branch_divergent;
8788
8789
8790    /** emit linear else block */
8791    Block* BB_else_linear = ctx->program->create_and_insert_block();
8792    BB_else_linear->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8793    BB_else_linear->kind |= block_kind_uniform;
8794    add_linear_edge(ic->invert_idx, BB_else_linear);
8795
8796    /* branch from linear else block to endif block */
8797    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8798    BB_else_linear->instructions.emplace_back(std::move(branch));
8799    add_linear_edge(BB_else_linear->index, &ic->BB_endif);
8800
8801
8802    /** emit endif merge block */
8803    ctx->block = ctx->program->insert_block(std::move(ic->BB_endif));
8804    append_logical_start(ctx->block);
8805
8806
8807    ctx->cf_info.parent_if.is_divergent = ic->divergent_old;
8808    ctx->cf_info.exec_potentially_empty_discard |= ic->exec_potentially_empty_discard_old;
8809    ctx->cf_info.exec_potentially_empty_break |= ic->exec_potentially_empty_break_old;
8810    ctx->cf_info.exec_potentially_empty_break_depth =
8811       std::min(ic->exec_potentially_empty_break_depth_old, ctx->cf_info.exec_potentially_empty_break_depth);
8812    if (ctx->cf_info.loop_nest_depth == ctx->cf_info.exec_potentially_empty_break_depth &&
8813        !ctx->cf_info.parent_if.is_divergent) {
8814       ctx->cf_info.exec_potentially_empty_break = false;
8815       ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8816    }
8817    /* uniform control flow never has an empty exec-mask */
8818    if (!ctx->cf_info.loop_nest_depth && !ctx->cf_info.parent_if.is_divergent) {
8819       ctx->cf_info.exec_potentially_empty_discard = false;
8820       ctx->cf_info.exec_potentially_empty_break = false;
8821       ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8822    }
8823 }
8824
8825 static void visit_if(isel_context *ctx, nir_if *if_stmt)
8826 {
8827    Temp cond = get_ssa_temp(ctx, if_stmt->condition.ssa);
8828    Builder bld(ctx->program, ctx->block);
8829    aco_ptr<Pseudo_branch_instruction> branch;
8830
8831    if (!ctx->divergent_vals[if_stmt->condition.ssa->index]) { /* uniform condition */
8832       /**
8833        * Uniform conditionals are represented in the following way*) :
8834        *
8835        * The linear and logical CFG:
8836        *                        BB_IF
8837        *                        /    \
8838        *       BB_THEN (logical)      BB_ELSE (logical)
8839        *                        \    /
8840        *                        BB_ENDIF
8841        *
8842        * *) Exceptions may be due to break and continue statements within loops
8843        *    If a break/continue happens within uniform control flow, it branches
8844        *    to the loop exit/entry block. Otherwise, it branches to the next
8845        *    merge block.
8846        **/
8847       append_logical_end(ctx->block);
8848       ctx->block->kind |= block_kind_uniform;
8849
8850       /* emit branch */
8851       assert(cond.regClass() == bld.lm);
8852       // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
8853       cond = bool_to_scalar_condition(ctx, cond);
8854
8855       branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_z, Format::PSEUDO_BRANCH, 1, 0));
8856       branch->operands[0] = Operand(cond);
8857       branch->operands[0].setFixed(scc);
8858       ctx->block->instructions.emplace_back(std::move(branch));
8859
8860       unsigned BB_if_idx = ctx->block->index;
8861       Block BB_endif = Block();
8862       BB_endif.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8863       BB_endif.kind |= ctx->block->kind & block_kind_top_level;
8864
8865       /** emit then block */
8866       Block* BB_then = ctx->program->create_and_insert_block();
8867       BB_then->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8868       add_edge(BB_if_idx, BB_then);
8869       append_logical_start(BB_then);
8870       ctx->block = BB_then;
8871       visit_cf_list(ctx, &if_stmt->then_list);
8872       BB_then = ctx->block;
8873       bool then_branch = ctx->cf_info.has_branch;
8874       bool then_branch_divergent = ctx->cf_info.parent_loop.has_divergent_branch;
8875
8876       if (!then_branch) {
8877          append_logical_end(BB_then);
8878          /* branch from then block to endif block */
8879          branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8880          BB_then->instructions.emplace_back(std::move(branch));
8881          add_linear_edge(BB_then->index, &BB_endif);
8882          if (!then_branch_divergent)
8883             add_logical_edge(BB_then->index, &BB_endif);
8884          BB_then->kind |= block_kind_uniform;
8885       }
8886
8887       ctx->cf_info.has_branch = false;
8888       ctx->cf_info.parent_loop.has_divergent_branch = false;
8889
8890       /** emit else block */
8891       Block* BB_else = ctx->program->create_and_insert_block();
8892       BB_else->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8893       add_edge(BB_if_idx, BB_else);
8894       append_logical_start(BB_else);
8895       ctx->block = BB_else;
8896       visit_cf_list(ctx, &if_stmt->else_list);
8897       BB_else = ctx->block;
8898
8899       if (!ctx->cf_info.has_branch) {
8900          append_logical_end(BB_else);
8901          /* branch from then block to endif block */
8902          branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8903          BB_else->instructions.emplace_back(std::move(branch));
8904          add_linear_edge(BB_else->index, &BB_endif);
8905          if (!ctx->cf_info.parent_loop.has_divergent_branch)
8906             add_logical_edge(BB_else->index, &BB_endif);
8907          BB_else->kind |= block_kind_uniform;
8908       }
8909
8910       ctx->cf_info.has_branch &= then_branch;
8911       ctx->cf_info.parent_loop.has_divergent_branch &= then_branch_divergent;
8912
8913       /** emit endif merge block */
8914       if (!ctx->cf_info.has_branch) {
8915          ctx->block = ctx->program->insert_block(std::move(BB_endif));
8916          append_logical_start(ctx->block);
8917       }
8918    } else { /* non-uniform condition */
8919       /**
8920        * To maintain a logical and linear CFG without critical edges,
8921        * non-uniform conditionals are represented in the following way*) :
8922        *
8923        * The linear CFG:
8924        *                        BB_IF
8925        *                        /    \
8926        *       BB_THEN (logical)      BB_THEN (linear)
8927        *                        \    /
8928        *                        BB_INVERT (linear)
8929        *                        /    \
8930        *       BB_ELSE (logical)      BB_ELSE (linear)
8931        *                        \    /
8932        *                        BB_ENDIF
8933        *
8934        * The logical CFG:
8935        *                        BB_IF
8936        *                        /    \
8937        *       BB_THEN (logical)      BB_ELSE (logical)
8938        *                        \    /
8939        *                        BB_ENDIF
8940        *
8941        * *) Exceptions may be due to break and continue statements within loops
8942        **/
8943
8944       if_context ic;
8945
8946       begin_divergent_if_then(ctx, &ic, cond);
8947       visit_cf_list(ctx, &if_stmt->then_list);
8948
8949       begin_divergent_if_else(ctx, &ic);
8950       visit_cf_list(ctx, &if_stmt->else_list);
8951
8952       end_divergent_if(ctx, &ic);
8953    }
8954 }
8955
8956 static void visit_cf_list(isel_context *ctx,
8957                           struct exec_list *list)
8958 {
8959    foreach_list_typed(nir_cf_node, node, node, list) {
8960       switch (node->type) {
8961       case nir_cf_node_block:
8962          visit_block(ctx, nir_cf_node_as_block(node));
8963          break;
8964       case nir_cf_node_if:
8965          visit_if(ctx, nir_cf_node_as_if(node));
8966          break;
8967       case nir_cf_node_loop:
8968          visit_loop(ctx, nir_cf_node_as_loop(node));
8969          break;
8970       default:
8971          unreachable("unimplemented cf list type");
8972       }
8973    }
8974 }
8975
8976 static void export_vs_varying(isel_context *ctx, int slot, bool is_pos, int *next_pos)
8977 {
8978    assert(ctx->stage == vertex_vs ||
8979           ctx->stage == tess_eval_vs ||
8980           ctx->stage == gs_copy_vs);
8981
8982    int offset = ctx->stage == tess_eval_vs
8983                 ? ctx->program->info->tes.outinfo.vs_output_param_offset[slot]
8984                 : ctx->program->info->vs.outinfo.vs_output_param_offset[slot];
8985    uint64_t mask = ctx->outputs.mask[slot];
8986    if (!is_pos && !mask)
8987       return;
8988    if (!is_pos && offset == AC_EXP_PARAM_UNDEFINED)
8989       return;
8990    aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
8991    exp->enabled_mask = mask;
8992    for (unsigned i = 0; i < 4; ++i) {
8993       if (mask & (1 << i))
8994          exp->operands[i] = Operand(ctx->outputs.outputs[slot][i]);
8995       else
8996          exp->operands[i] = Operand(v1);
8997    }
8998    /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
8999     * Setting valid_mask=1 prevents it and has no other effect.
9000     */
9001    exp->valid_mask = ctx->options->chip_class >= GFX10 && is_pos && *next_pos == 0;
9002    exp->done = false;
9003    exp->compressed = false;
9004    if (is_pos)
9005       exp->dest = V_008DFC_SQ_EXP_POS + (*next_pos)++;
9006    else
9007       exp->dest = V_008DFC_SQ_EXP_PARAM + offset;
9008    ctx->block->instructions.emplace_back(std::move(exp));
9009 }
9010
9011 static void export_vs_psiz_layer_viewport(isel_context *ctx, int *next_pos)
9012 {
9013    aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
9014    exp->enabled_mask = 0;
9015    for (unsigned i = 0; i < 4; ++i)
9016       exp->operands[i] = Operand(v1);
9017    if (ctx->outputs.mask[VARYING_SLOT_PSIZ]) {
9018       exp->operands[0] = Operand(ctx->outputs.outputs[VARYING_SLOT_PSIZ][0]);
9019       exp->enabled_mask |= 0x1;
9020    }
9021    if (ctx->outputs.mask[VARYING_SLOT_LAYER]) {
9022       exp->operands[2] = Operand(ctx->outputs.outputs[VARYING_SLOT_LAYER][0]);
9023       exp->enabled_mask |= 0x4;
9024    }
9025    if (ctx->outputs.mask[VARYING_SLOT_VIEWPORT]) {
9026       if (ctx->options->chip_class < GFX9) {
9027          exp->operands[3] = Operand(ctx->outputs.outputs[VARYING_SLOT_VIEWPORT][0]);
9028          exp->enabled_mask |= 0x8;
9029       } else {
9030          Builder bld(ctx->program, ctx->block);
9031
9032          Temp out = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(16u),
9033                              Operand(ctx->outputs.outputs[VARYING_SLOT_VIEWPORT][0]));
9034          if (exp->operands[2].isTemp())
9035             out = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(out), exp->operands[2]);
9036
9037          exp->operands[2] = Operand(out);
9038          exp->enabled_mask |= 0x4;
9039       }
9040    }
9041    exp->valid_mask = ctx->options->chip_class >= GFX10 && *next_pos == 0;
9042    exp->done = false;
9043    exp->compressed = false;
9044    exp->dest = V_008DFC_SQ_EXP_POS + (*next_pos)++;
9045    ctx->block->instructions.emplace_back(std::move(exp));
9046 }
9047
9048 static void create_vs_exports(isel_context *ctx)
9049 {
9050    assert(ctx->stage == vertex_vs ||
9051           ctx->stage == tess_eval_vs ||
9052           ctx->stage == gs_copy_vs);
9053
9054    radv_vs_output_info *outinfo = ctx->stage == tess_eval_vs
9055                                   ? &ctx->program->info->tes.outinfo
9056                                   : &ctx->program->info->vs.outinfo;
9057
9058    if (outinfo->export_prim_id) {
9059       ctx->outputs.mask[VARYING_SLOT_PRIMITIVE_ID] |= 0x1;
9060       ctx->outputs.outputs[VARYING_SLOT_PRIMITIVE_ID][0] = get_arg(ctx, ctx->args->vs_prim_id);
9061    }
9062
9063    if (ctx->options->key.has_multiview_view_index) {
9064       ctx->outputs.mask[VARYING_SLOT_LAYER] |= 0x1;
9065       ctx->outputs.outputs[VARYING_SLOT_LAYER][0] = as_vgpr(ctx, get_arg(ctx, ctx->args->ac.view_index));
9066    }
9067
9068    /* the order these position exports are created is important */
9069    int next_pos = 0;
9070    export_vs_varying(ctx, VARYING_SLOT_POS, true, &next_pos);
9071    if (outinfo->writes_pointsize || outinfo->writes_layer || outinfo->writes_viewport_index) {
9072       export_vs_psiz_layer_viewport(ctx, &next_pos);
9073    }
9074    if (ctx->num_clip_distances + ctx->num_cull_distances > 0)
9075       export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST0, true, &next_pos);
9076    if (ctx->num_clip_distances + ctx->num_cull_distances > 4)
9077       export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST1, true, &next_pos);
9078
9079    if (ctx->export_clip_dists) {
9080       if (ctx->num_clip_distances + ctx->num_cull_distances > 0)
9081          export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST0, false, &next_pos);
9082       if (ctx->num_clip_distances + ctx->num_cull_distances > 4)
9083          export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST1, false, &next_pos);
9084    }
9085
9086    for (unsigned i = 0; i <= VARYING_SLOT_VAR31; ++i) {
9087       if (i < VARYING_SLOT_VAR0 && i != VARYING_SLOT_LAYER &&
9088           i != VARYING_SLOT_PRIMITIVE_ID)
9089          continue;
9090
9091       export_vs_varying(ctx, i, false, NULL);
9092    }
9093 }
9094
9095 static void export_fs_mrt_z(isel_context *ctx)
9096 {
9097    Builder bld(ctx->program, ctx->block);
9098    unsigned enabled_channels = 0;
9099    bool compr = false;
9100    Operand values[4];
9101
9102    for (unsigned i = 0; i < 4; ++i) {
9103       values[i] = Operand(v1);
9104    }
9105
9106    /* Both stencil and sample mask only need 16-bits. */
9107    if (!ctx->program->info->ps.writes_z &&
9108        (ctx->program->info->ps.writes_stencil ||
9109         ctx->program->info->ps.writes_sample_mask)) {
9110       compr = true; /* COMPR flag */
9111
9112       if (ctx->program->info->ps.writes_stencil) {
9113          /* Stencil should be in X[23:16]. */
9114          values[0] = Operand(ctx->outputs.outputs[FRAG_RESULT_STENCIL][0]);
9115          values[0] = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(16u), values[0]);
9116          enabled_channels |= 0x3;
9117       }
9118
9119       if (ctx->program->info->ps.writes_sample_mask) {
9120          /* SampleMask should be in Y[15:0]. */
9121          values[1] = Operand(ctx->outputs.outputs[FRAG_RESULT_SAMPLE_MASK][0]);
9122          enabled_channels |= 0xc;
9123      }
9124    } else {
9125       if (ctx->program->info->ps.writes_z) {
9126          values[0] = Operand(ctx->outputs.outputs[FRAG_RESULT_DEPTH][0]);
9127          enabled_channels |= 0x1;
9128       }
9129
9130       if (ctx->program->info->ps.writes_stencil) {
9131          values[1] = Operand(ctx->outputs.outputs[FRAG_RESULT_STENCIL][0]);
9132          enabled_channels |= 0x2;
9133       }
9134
9135       if (ctx->program->info->ps.writes_sample_mask) {
9136          values[2] = Operand(ctx->outputs.outputs[FRAG_RESULT_SAMPLE_MASK][0]);
9137          enabled_channels |= 0x4;
9138       }
9139    }
9140
9141    /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9142     * writemask component.
9143     */
9144    if (ctx->options->chip_class == GFX6 &&
9145        ctx->options->family != CHIP_OLAND &&
9146        ctx->options->family != CHIP_HAINAN) {
9147             enabled_channels |= 0x1;
9148    }
9149
9150    bld.exp(aco_opcode::exp, values[0], values[1], values[2], values[3],
9151            enabled_channels, V_008DFC_SQ_EXP_MRTZ, compr);
9152 }
9153
9154 static void export_fs_mrt_color(isel_context *ctx, int slot)
9155 {
9156    Builder bld(ctx->program, ctx->block);
9157    unsigned write_mask = ctx->outputs.mask[slot];
9158    Operand values[4];
9159
9160    for (unsigned i = 0; i < 4; ++i) {
9161       if (write_mask & (1 << i)) {
9162          values[i] = Operand(ctx->outputs.outputs[slot][i]);
9163       } else {
9164          values[i] = Operand(v1);
9165       }
9166    }
9167
9168    unsigned target, col_format;
9169    unsigned enabled_channels = 0;
9170    aco_opcode compr_op = (aco_opcode)0;
9171
9172    slot -= FRAG_RESULT_DATA0;
9173    target = V_008DFC_SQ_EXP_MRT + slot;
9174    col_format = (ctx->options->key.fs.col_format >> (4 * slot)) & 0xf;
9175
9176    bool is_int8 = (ctx->options->key.fs.is_int8 >> slot) & 1;
9177    bool is_int10 = (ctx->options->key.fs.is_int10 >> slot) & 1;
9178
9179    switch (col_format)
9180    {
9181    case V_028714_SPI_SHADER_ZERO:
9182       enabled_channels = 0; /* writemask */
9183       target = V_008DFC_SQ_EXP_NULL;
9184       break;
9185
9186    case V_028714_SPI_SHADER_32_R:
9187       enabled_channels = 1;
9188       break;
9189
9190    case V_028714_SPI_SHADER_32_GR:
9191       enabled_channels = 0x3;
9192       break;
9193
9194    case V_028714_SPI_SHADER_32_AR:
9195       if (ctx->options->chip_class >= GFX10) {
9196          /* Special case: on GFX10, the outputs are different for 32_AR */
9197          enabled_channels = 0x3;
9198          values[1] = values[3];
9199          values[3] = Operand(v1);
9200       } else {
9201          enabled_channels = 0x9;
9202       }
9203       break;
9204
9205    case V_028714_SPI_SHADER_FP16_ABGR:
9206       enabled_channels = 0x5;
9207       compr_op = aco_opcode::v_cvt_pkrtz_f16_f32;
9208       break;
9209
9210    case V_028714_SPI_SHADER_UNORM16_ABGR:
9211       enabled_channels = 0x5;
9212       compr_op = aco_opcode::v_cvt_pknorm_u16_f32;
9213       break;
9214
9215    case V_028714_SPI_SHADER_SNORM16_ABGR:
9216       enabled_channels = 0x5;
9217       compr_op = aco_opcode::v_cvt_pknorm_i16_f32;
9218       break;
9219
9220    case V_028714_SPI_SHADER_UINT16_ABGR: {
9221       enabled_channels = 0x5;
9222       compr_op = aco_opcode::v_cvt_pk_u16_u32;
9223       if (is_int8 || is_int10) {
9224          /* clamp */
9225          uint32_t max_rgb = is_int8 ? 255 : is_int10 ? 1023 : 0;
9226          Temp max_rgb_val = bld.copy(bld.def(s1), Operand(max_rgb));
9227
9228          for (unsigned i = 0; i < 4; i++) {
9229             if ((write_mask >> i) & 1) {
9230                values[i] = bld.vop2(aco_opcode::v_min_u32, bld.def(v1),
9231                                     i == 3 && is_int10 ? Operand(3u) : Operand(max_rgb_val),
9232                                     values[i]);
9233             }
9234          }
9235       }
9236       break;
9237    }
9238
9239    case V_028714_SPI_SHADER_SINT16_ABGR:
9240       enabled_channels = 0x5;
9241       compr_op = aco_opcode::v_cvt_pk_i16_i32;
9242       if (is_int8 || is_int10) {
9243          /* clamp */
9244          uint32_t max_rgb = is_int8 ? 127 : is_int10 ? 511 : 0;
9245          uint32_t min_rgb = is_int8 ? -128 :is_int10 ? -512 : 0;
9246          Temp max_rgb_val = bld.copy(bld.def(s1), Operand(max_rgb));
9247          Temp min_rgb_val = bld.copy(bld.def(s1), Operand(min_rgb));
9248
9249          for (unsigned i = 0; i < 4; i++) {
9250             if ((write_mask >> i) & 1) {
9251                values[i] = bld.vop2(aco_opcode::v_min_i32, bld.def(v1),
9252                                     i == 3 && is_int10 ? Operand(1u) : Operand(max_rgb_val),
9253                                     values[i]);
9254                values[i] = bld.vop2(aco_opcode::v_max_i32, bld.def(v1),
9255                                     i == 3 && is_int10 ? Operand(-2u) : Operand(min_rgb_val),
9256                                     values[i]);
9257             }
9258          }
9259       }
9260       break;
9261
9262    case V_028714_SPI_SHADER_32_ABGR:
9263       enabled_channels = 0xF;
9264       break;
9265
9266    default:
9267       break;
9268    }
9269
9270    if (target == V_008DFC_SQ_EXP_NULL)
9271       return;
9272
9273    if ((bool) compr_op) {
9274       for (int i = 0; i < 2; i++) {
9275          /* check if at least one of the values to be compressed is enabled */
9276          unsigned enabled = (write_mask >> (i*2) | write_mask >> (i*2+1)) & 0x1;
9277          if (enabled) {
9278             enabled_channels |= enabled << (i*2);
9279             values[i] = bld.vop3(compr_op, bld.def(v1),
9280                                  values[i*2].isUndefined() ? Operand(0u) : values[i*2],
9281                                  values[i*2+1].isUndefined() ? Operand(0u): values[i*2+1]);
9282          } else {
9283             values[i] = Operand(v1);
9284          }
9285       }
9286       values[2] = Operand(v1);
9287       values[3] = Operand(v1);
9288    } else {
9289       for (int i = 0; i < 4; i++)
9290          values[i] = enabled_channels & (1 << i) ? values[i] : Operand(v1);
9291    }
9292
9293    bld.exp(aco_opcode::exp, values[0], values[1], values[2], values[3],
9294            enabled_channels, target, (bool) compr_op);
9295 }
9296
9297 static void create_fs_exports(isel_context *ctx)
9298 {
9299    /* Export depth, stencil and sample mask. */
9300    if (ctx->outputs.mask[FRAG_RESULT_DEPTH] ||
9301        ctx->outputs.mask[FRAG_RESULT_STENCIL] ||
9302        ctx->outputs.mask[FRAG_RESULT_SAMPLE_MASK]) {
9303       export_fs_mrt_z(ctx);
9304    }
9305
9306    /* Export all color render targets. */
9307    for (unsigned i = FRAG_RESULT_DATA0; i < FRAG_RESULT_DATA7 + 1; ++i) {
9308       if (ctx->outputs.mask[i])
9309          export_fs_mrt_color(ctx, i);
9310    }
9311 }
9312
9313 static void write_tcs_tess_factors(isel_context *ctx)
9314 {
9315    unsigned outer_comps;
9316    unsigned inner_comps;
9317
9318    switch (ctx->args->options->key.tcs.primitive_mode) {
9319    case GL_ISOLINES:
9320       outer_comps = 2;
9321       inner_comps = 0;
9322       break;
9323    case GL_TRIANGLES:
9324       outer_comps = 3;
9325       inner_comps = 1;
9326       break;
9327    case GL_QUADS:
9328       outer_comps = 4;
9329       inner_comps = 2;
9330       break;
9331    default:
9332       return;
9333    }
9334
9335    const unsigned tess_index_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
9336    const unsigned tess_index_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
9337
9338    Builder bld(ctx->program, ctx->block);
9339
9340    bld.barrier(aco_opcode::p_memory_barrier_shared);
9341    unsigned workgroup_size = ctx->tcs_num_patches * ctx->shader->info.tess.tcs_vertices_out;
9342    if (unlikely(ctx->program->chip_class != GFX6 && workgroup_size > ctx->program->wave_size))
9343       bld.sopp(aco_opcode::s_barrier);
9344
9345    Temp tcs_rel_ids = get_arg(ctx, ctx->args->ac.tcs_rel_ids);
9346    Temp invocation_id = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1), tcs_rel_ids, Operand(8u), Operand(5u));
9347
9348    Temp invocation_id_is_zero = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), invocation_id);
9349    if_context ic_invocation_id_is_zero;
9350    begin_divergent_if_then(ctx, &ic_invocation_id_is_zero, invocation_id_is_zero);
9351    bld.reset(ctx->block);
9352
9353    Temp hs_ring_tess_factor = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_HS_TESS_FACTOR * 16u));
9354
9355    std::pair<Temp, unsigned> lds_base = get_tcs_output_lds_offset(ctx);
9356    unsigned stride = inner_comps + outer_comps;
9357    Temp inner[4];
9358    Temp outer[4];
9359    Temp out[6];
9360    assert(inner_comps <= (sizeof(inner) / sizeof(Temp)));
9361    assert(outer_comps <= (sizeof(outer) / sizeof(Temp)));
9362    assert(stride <= (sizeof(out) / sizeof(Temp)));
9363
9364    if (ctx->args->options->key.tcs.primitive_mode == GL_ISOLINES) {
9365       // LINES reversal
9366       outer[0] = out[1] = load_lds(ctx, 4, bld.tmp(v1), lds_base.first, lds_base.second + tess_index_outer * 16 + 0 * 4, 4);
9367       outer[1] = out[0] = load_lds(ctx, 4, bld.tmp(v1), lds_base.first, lds_base.second + tess_index_outer * 16 + 1 * 4, 4);
9368    } else {
9369       for (unsigned i = 0; i < outer_comps; ++i)
9370          outer[i] = out[i] = load_lds(ctx, 4, bld.tmp(v1), lds_base.first, lds_base.second + tess_index_outer * 16 + i * 4, 4);
9371
9372       for (unsigned i = 0; i < inner_comps; ++i)
9373          inner[i] = out[outer_comps + i] = load_lds(ctx, 4, bld.tmp(v1), lds_base.first, lds_base.second + tess_index_inner * 16 + i * 4, 4);
9374    }
9375
9376    Temp rel_patch_id = get_tess_rel_patch_id(ctx);
9377    Temp tf_base = get_arg(ctx, ctx->args->tess_factor_offset);
9378    Temp byte_offset = bld.v_mul_imm(bld.def(v1), rel_patch_id, stride * 4u);
9379    unsigned tf_const_offset = 0;
9380
9381    if (ctx->program->chip_class <= GFX8) {
9382       Temp rel_patch_id_is_zero = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), rel_patch_id);
9383       if_context ic_rel_patch_id_is_zero;
9384       begin_divergent_if_then(ctx, &ic_rel_patch_id_is_zero, rel_patch_id_is_zero);
9385       bld.reset(ctx->block);
9386
9387       /* Store the dynamic HS control word. */
9388       Temp control_word = bld.copy(bld.def(v1), Operand(0x80000000u));
9389       bld.mubuf(aco_opcode::buffer_store_dword,
9390                 /* SRSRC */ hs_ring_tess_factor, /* VADDR */ Operand(v1), /* SOFFSET */ tf_base, /* VDATA */ control_word,
9391                 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
9392                 /* disable_wqm */ false, /* glc */ true);
9393       tf_const_offset += 4;
9394
9395       begin_divergent_if_else(ctx, &ic_rel_patch_id_is_zero);
9396       end_divergent_if(ctx, &ic_rel_patch_id_is_zero);
9397       bld.reset(ctx->block);
9398    }
9399
9400    assert(stride == 2 || stride == 4 || stride == 6);
9401    Temp tf_vec = create_vec_from_array(ctx, out, stride, RegType::vgpr);
9402    store_vmem_mubuf(ctx, tf_vec, hs_ring_tess_factor, byte_offset, tf_base, tf_const_offset, 4, (1 << stride) - 1, true, false);
9403
9404    /* Store to offchip for TES to read - only if TES reads them */
9405    if (ctx->args->options->key.tcs.tes_reads_tess_factors) {
9406       Temp hs_ring_tess_offchip = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_HS_TESS_OFFCHIP * 16u));
9407       Temp oc_lds = get_arg(ctx, ctx->args->oc_lds);
9408
9409       std::pair<Temp, unsigned> vmem_offs_outer = get_tcs_per_patch_output_vmem_offset(ctx, nullptr, tess_index_outer * 16);
9410       Temp outer_vec = create_vec_from_array(ctx, outer, outer_comps, RegType::vgpr);
9411       store_vmem_mubuf(ctx, outer_vec, hs_ring_tess_offchip, vmem_offs_outer.first, oc_lds, vmem_offs_outer.second, 4, (1 << outer_comps) - 1, true, false);
9412
9413       if (likely(inner_comps)) {
9414          std::pair<Temp, unsigned> vmem_offs_inner = get_tcs_per_patch_output_vmem_offset(ctx, nullptr, tess_index_inner * 16);
9415          Temp inner_vec = create_vec_from_array(ctx, inner, inner_comps, RegType::vgpr);
9416          store_vmem_mubuf(ctx, inner_vec, hs_ring_tess_offchip, vmem_offs_inner.first, oc_lds, vmem_offs_inner.second, 4, (1 << inner_comps) - 1, true, false);
9417       }
9418    }
9419
9420    begin_divergent_if_else(ctx, &ic_invocation_id_is_zero);
9421    end_divergent_if(ctx, &ic_invocation_id_is_zero);
9422 }
9423
9424 static void emit_stream_output(isel_context *ctx,
9425                                Temp const *so_buffers,
9426                                Temp const *so_write_offset,
9427                                const struct radv_stream_output *output)
9428 {
9429    unsigned num_comps = util_bitcount(output->component_mask);
9430    unsigned writemask = (1 << num_comps) - 1;
9431    unsigned loc = output->location;
9432    unsigned buf = output->buffer;
9433
9434    assert(num_comps && num_comps <= 4);
9435    if (!num_comps || num_comps > 4)
9436       return;
9437
9438    unsigned start = ffs(output->component_mask) - 1;
9439
9440    Temp out[4];
9441    bool all_undef = true;
9442    assert(ctx->stage == vertex_vs || ctx->stage == gs_copy_vs);
9443    for (unsigned i = 0; i < num_comps; i++) {
9444       out[i] = ctx->outputs.outputs[loc][start + i];
9445       all_undef = all_undef && !out[i].id();
9446    }
9447    if (all_undef)
9448       return;
9449
9450    while (writemask) {
9451       int start, count;
9452       u_bit_scan_consecutive_range(&writemask, &start, &count);
9453       if (count == 3 && ctx->options->chip_class == GFX6) {
9454          /* GFX6 doesn't support storing vec3, split it. */
9455          writemask |= 1u << (start + 2);
9456          count = 2;
9457       }
9458
9459       unsigned offset = output->offset + start * 4;
9460
9461       Temp write_data = {ctx->program->allocateId(), RegClass(RegType::vgpr, count)};
9462       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
9463       for (int i = 0; i < count; ++i)
9464          vec->operands[i] = (ctx->outputs.mask[loc] & 1 << (start + i)) ? Operand(out[start + i]) : Operand(0u);
9465       vec->definitions[0] = Definition(write_data);
9466       ctx->block->instructions.emplace_back(std::move(vec));
9467
9468       aco_opcode opcode;
9469       switch (count) {
9470       case 1:
9471          opcode = aco_opcode::buffer_store_dword;
9472          break;
9473       case 2:
9474          opcode = aco_opcode::buffer_store_dwordx2;
9475          break;
9476       case 3:
9477          opcode = aco_opcode::buffer_store_dwordx3;
9478          break;
9479       case 4:
9480          opcode = aco_opcode::buffer_store_dwordx4;
9481          break;
9482       default:
9483          unreachable("Unsupported dword count.");
9484       }
9485
9486       aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 4, 0)};
9487       store->operands[0] = Operand(so_buffers[buf]);
9488       store->operands[1] = Operand(so_write_offset[buf]);
9489       store->operands[2] = Operand((uint32_t) 0);
9490       store->operands[3] = Operand(write_data);
9491       if (offset > 4095) {
9492          /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
9493          Builder bld(ctx->program, ctx->block);
9494          store->operands[0] = bld.vadd32(bld.def(v1), Operand(offset), Operand(so_write_offset[buf]));
9495       } else {
9496          store->offset = offset;
9497       }
9498       store->offen = true;
9499       store->glc = true;
9500       store->dlc = false;
9501       store->slc = true;
9502       store->can_reorder = true;
9503       ctx->block->instructions.emplace_back(std::move(store));
9504    }
9505 }
9506
9507 static void emit_streamout(isel_context *ctx, unsigned stream)
9508 {
9509    Builder bld(ctx->program, ctx->block);
9510
9511    Temp so_buffers[4];
9512    Temp buf_ptr = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->streamout_buffers));
9513    for (unsigned i = 0; i < 4; i++) {
9514       unsigned stride = ctx->program->info->so.strides[i];
9515       if (!stride)
9516          continue;
9517
9518       Operand off = bld.copy(bld.def(s1), Operand(i * 16u));
9519       so_buffers[i] = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), buf_ptr, off);
9520    }
9521
9522    Temp so_vtx_count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
9523                                 get_arg(ctx, ctx->args->streamout_config), Operand(0x70010u));
9524
9525    Temp tid = emit_mbcnt(ctx, bld.def(v1));
9526
9527    Temp can_emit = bld.vopc(aco_opcode::v_cmp_gt_i32, bld.def(bld.lm), so_vtx_count, tid);
9528
9529    if_context ic;
9530    begin_divergent_if_then(ctx, &ic, can_emit);
9531
9532    bld.reset(ctx->block);
9533
9534    Temp so_write_index = bld.vadd32(bld.def(v1), get_arg(ctx, ctx->args->streamout_write_idx), tid);
9535
9536    Temp so_write_offset[4];
9537
9538    for (unsigned i = 0; i < 4; i++) {
9539       unsigned stride = ctx->program->info->so.strides[i];
9540       if (!stride)
9541          continue;
9542
9543       if (stride == 1) {
9544          Temp offset = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
9545                                 get_arg(ctx, ctx->args->streamout_write_idx),
9546                                 get_arg(ctx, ctx->args->streamout_offset[i]));
9547          Temp new_offset = bld.vadd32(bld.def(v1), offset, tid);
9548
9549          so_write_offset[i] = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), new_offset);
9550       } else {
9551          Temp offset = bld.v_mul_imm(bld.def(v1), so_write_index, stride * 4u);
9552          Temp offset2 = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(4u),
9553                                  get_arg(ctx, ctx->args->streamout_offset[i]));
9554          so_write_offset[i] = bld.vadd32(bld.def(v1), offset, offset2);
9555       }
9556    }
9557
9558    for (unsigned i = 0; i < ctx->program->info->so.num_outputs; i++) {
9559       struct radv_stream_output *output =
9560          &ctx->program->info->so.outputs[i];
9561       if (stream != output->stream)
9562          continue;
9563
9564       emit_stream_output(ctx, so_buffers, so_write_offset, output);
9565    }
9566
9567    begin_divergent_if_else(ctx, &ic);
9568    end_divergent_if(ctx, &ic);
9569 }
9570
9571 } /* end namespace */
9572
9573 void fix_ls_vgpr_init_bug(isel_context *ctx, Pseudo_instruction *startpgm)
9574 {
9575    assert(ctx->shader->info.stage == MESA_SHADER_VERTEX);
9576    Builder bld(ctx->program, ctx->block);
9577    constexpr unsigned hs_idx = 1u;
9578    Builder::Result hs_thread_count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
9579                                               get_arg(ctx, ctx->args->merged_wave_info),
9580                                               Operand((8u << 16) | (hs_idx * 8u)));
9581    Temp ls_has_nonzero_hs_threads = bool_to_vector_condition(ctx, hs_thread_count.def(1).getTemp());
9582
9583    /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
9584
9585    Temp instance_id = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
9586                                get_arg(ctx, ctx->args->rel_auto_id),
9587                                get_arg(ctx, ctx->args->ac.instance_id),
9588                                ls_has_nonzero_hs_threads);
9589    Temp rel_auto_id = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
9590                                get_arg(ctx, ctx->args->ac.tcs_rel_ids),
9591                                get_arg(ctx, ctx->args->rel_auto_id),
9592                                ls_has_nonzero_hs_threads);
9593    Temp vertex_id = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
9594                              get_arg(ctx, ctx->args->ac.tcs_patch_id),
9595                              get_arg(ctx, ctx->args->ac.vertex_id),
9596                              ls_has_nonzero_hs_threads);
9597
9598    ctx->arg_temps[ctx->args->ac.instance_id.arg_index] = instance_id;
9599    ctx->arg_temps[ctx->args->rel_auto_id.arg_index] = rel_auto_id;
9600    ctx->arg_temps[ctx->args->ac.vertex_id.arg_index] = vertex_id;
9601 }
9602
9603 void split_arguments(isel_context *ctx, Pseudo_instruction *startpgm)
9604 {
9605    /* Split all arguments except for the first (ring_offsets) and the last
9606     * (exec) so that the dead channels don't stay live throughout the program.
9607     */
9608    for (int i = 1; i < startpgm->definitions.size() - 1; i++) {
9609       if (startpgm->definitions[i].regClass().size() > 1) {
9610          emit_split_vector(ctx, startpgm->definitions[i].getTemp(),
9611                            startpgm->definitions[i].regClass().size());
9612       }
9613    }
9614 }
9615
9616 void handle_bc_optimize(isel_context *ctx)
9617 {
9618    /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
9619    Builder bld(ctx->program, ctx->block);
9620    uint32_t spi_ps_input_ena = ctx->program->config->spi_ps_input_ena;
9621    bool uses_center = G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena);
9622    bool uses_centroid = G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena);
9623    ctx->persp_centroid = get_arg(ctx, ctx->args->ac.persp_centroid);
9624    ctx->linear_centroid = get_arg(ctx, ctx->args->ac.linear_centroid);
9625    if (uses_center && uses_centroid) {
9626       Temp sel = bld.vopc_e64(aco_opcode::v_cmp_lt_i32, bld.hint_vcc(bld.def(bld.lm)),
9627                               get_arg(ctx, ctx->args->ac.prim_mask), Operand(0u));
9628
9629       if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena)) {
9630          Temp new_coord[2];
9631          for (unsigned i = 0; i < 2; i++) {
9632             Temp persp_centroid = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.persp_centroid), i, v1);
9633             Temp persp_center = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.persp_center), i, v1);
9634             new_coord[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
9635                                     persp_centroid, persp_center, sel);
9636          }
9637          ctx->persp_centroid = bld.tmp(v2);
9638          bld.pseudo(aco_opcode::p_create_vector, Definition(ctx->persp_centroid),
9639                     Operand(new_coord[0]), Operand(new_coord[1]));
9640          emit_split_vector(ctx, ctx->persp_centroid, 2);
9641       }
9642
9643       if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena)) {
9644          Temp new_coord[2];
9645          for (unsigned i = 0; i < 2; i++) {
9646             Temp linear_centroid = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.linear_centroid), i, v1);
9647             Temp linear_center = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.linear_center), i, v1);
9648             new_coord[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
9649                                     linear_centroid, linear_center, sel);
9650          }
9651          ctx->linear_centroid = bld.tmp(v2);
9652          bld.pseudo(aco_opcode::p_create_vector, Definition(ctx->linear_centroid),
9653                     Operand(new_coord[0]), Operand(new_coord[1]));
9654          emit_split_vector(ctx, ctx->linear_centroid, 2);
9655       }
9656    }
9657 }
9658
9659 void setup_fp_mode(isel_context *ctx, nir_shader *shader)
9660 {
9661    Program *program = ctx->program;
9662
9663    unsigned float_controls = shader->info.float_controls_execution_mode;
9664
9665    program->next_fp_mode.preserve_signed_zero_inf_nan32 =
9666       float_controls & FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32;
9667    program->next_fp_mode.preserve_signed_zero_inf_nan16_64 =
9668       float_controls & (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16 |
9669                         FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64);
9670
9671    program->next_fp_mode.must_flush_denorms32 =
9672       float_controls & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32;
9673    program->next_fp_mode.must_flush_denorms16_64 =
9674       float_controls & (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16 |
9675                         FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64);
9676
9677    program->next_fp_mode.care_about_round32 =
9678       float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32 | FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32);
9679
9680    program->next_fp_mode.care_about_round16_64 =
9681       float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64 |
9682                         FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64);
9683
9684    /* default to preserving fp16 and fp64 denorms, since it's free */
9685    if (program->next_fp_mode.must_flush_denorms16_64)
9686       program->next_fp_mode.denorm16_64 = 0;
9687    else
9688       program->next_fp_mode.denorm16_64 = fp_denorm_keep;
9689
9690    /* preserving fp32 denorms is expensive, so only do it if asked */
9691    if (float_controls & FLOAT_CONTROLS_DENORM_PRESERVE_FP32)
9692       program->next_fp_mode.denorm32 = fp_denorm_keep;
9693    else
9694       program->next_fp_mode.denorm32 = 0;
9695
9696    if (float_controls & FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32)
9697       program->next_fp_mode.round32 = fp_round_tz;
9698    else
9699       program->next_fp_mode.round32 = fp_round_ne;
9700
9701    if (float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64))
9702       program->next_fp_mode.round16_64 = fp_round_tz;
9703    else
9704       program->next_fp_mode.round16_64 = fp_round_ne;
9705
9706    ctx->block->fp_mode = program->next_fp_mode;
9707 }
9708
9709 void cleanup_cfg(Program *program)
9710 {
9711    /* create linear_succs/logical_succs */
9712    for (Block& BB : program->blocks) {
9713       for (unsigned idx : BB.linear_preds)
9714          program->blocks[idx].linear_succs.emplace_back(BB.index);
9715       for (unsigned idx : BB.logical_preds)
9716          program->blocks[idx].logical_succs.emplace_back(BB.index);
9717    }
9718 }
9719
9720 void select_program(Program *program,
9721                     unsigned shader_count,
9722                     struct nir_shader *const *shaders,
9723                     ac_shader_config* config,
9724                     struct radv_shader_args *args)
9725 {
9726    isel_context ctx = setup_isel_context(program, shader_count, shaders, config, args, false);
9727
9728    for (unsigned i = 0; i < shader_count; i++) {
9729       nir_shader *nir = shaders[i];
9730       init_context(&ctx, nir);
9731
9732       setup_fp_mode(&ctx, nir);
9733
9734       if (!i) {
9735          /* needs to be after init_context() for FS */
9736          Pseudo_instruction *startpgm = add_startpgm(&ctx);
9737          append_logical_start(ctx.block);
9738
9739          if (unlikely(args->options->has_ls_vgpr_init_bug && ctx.stage == vertex_tess_control_hs))
9740             fix_ls_vgpr_init_bug(&ctx, startpgm);
9741
9742          split_arguments(&ctx, startpgm);
9743       }
9744
9745       /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
9746       nir_function_impl *func = nir_shader_get_entrypoint(nir);
9747       bool empty_shader = nir_cf_list_is_empty_block(&func->body) &&
9748                           ((nir->info.stage == MESA_SHADER_VERTEX &&
9749                             (ctx.stage == vertex_tess_control_hs || ctx.stage == vertex_geometry_gs)) ||
9750                            (nir->info.stage == MESA_SHADER_TESS_EVAL &&
9751                             ctx.stage == tess_eval_geometry_gs));
9752
9753       if_context ic;
9754       if (shader_count >= 2 && !empty_shader) {
9755          Builder bld(ctx.program, ctx.block);
9756          Temp count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), get_arg(&ctx, args->merged_wave_info), Operand((8u << 16) | (i * 8u)));
9757          Temp thread_id = emit_mbcnt(&ctx, bld.def(v1));
9758          Temp cond = bld.vopc(aco_opcode::v_cmp_gt_u32, bld.hint_vcc(bld.def(bld.lm)), count, thread_id);
9759
9760          begin_divergent_if_then(&ctx, &ic, cond);
9761       }
9762
9763       if (i) {
9764          Builder bld(ctx.program, ctx.block);
9765
9766          bld.barrier(aco_opcode::p_memory_barrier_shared);
9767          bld.sopp(aco_opcode::s_barrier);
9768
9769          if (ctx.stage == vertex_geometry_gs || ctx.stage == tess_eval_geometry_gs) {
9770             ctx.gs_wave_id = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1, m0), bld.def(s1, scc), get_arg(&ctx, args->merged_wave_info), Operand((8u << 16) | 16u));
9771          }
9772       } else if (ctx.stage == geometry_gs)
9773          ctx.gs_wave_id = get_arg(&ctx, args->gs_wave_id);
9774
9775       if (ctx.stage == fragment_fs)
9776          handle_bc_optimize(&ctx);
9777
9778       visit_cf_list(&ctx, &func->body);
9779
9780       if (ctx.program->info->so.num_outputs && (ctx.stage == vertex_vs || ctx.stage == tess_eval_vs))
9781          emit_streamout(&ctx, 0);
9782
9783       if (ctx.stage == vertex_vs || ctx.stage == tess_eval_vs) {
9784          create_vs_exports(&ctx);
9785       } else if (nir->info.stage == MESA_SHADER_GEOMETRY) {
9786          Builder bld(ctx.program, ctx.block);
9787          bld.barrier(aco_opcode::p_memory_barrier_gs_data);
9788          bld.sopp(aco_opcode::s_sendmsg, bld.m0(ctx.gs_wave_id), -1, sendmsg_gs_done(false, false, 0));
9789       } else if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
9790          write_tcs_tess_factors(&ctx);
9791       }
9792
9793       if (ctx.stage == fragment_fs)
9794          create_fs_exports(&ctx);
9795
9796       if (shader_count >= 2 && !empty_shader) {
9797          begin_divergent_if_else(&ctx, &ic);
9798          end_divergent_if(&ctx, &ic);
9799       }
9800
9801       ralloc_free(ctx.divergent_vals);
9802    }
9803
9804    program->config->float_mode = program->blocks[0].fp_mode.val;
9805
9806    append_logical_end(ctx.block);
9807    ctx.block->kind |= block_kind_uniform | block_kind_export_end;
9808    Builder bld(ctx.program, ctx.block);
9809    if (ctx.program->wb_smem_l1_on_end)
9810       bld.smem(aco_opcode::s_dcache_wb, false);
9811    bld.sopp(aco_opcode::s_endpgm);
9812
9813    cleanup_cfg(program);
9814 }
9815
9816 void select_gs_copy_shader(Program *program, struct nir_shader *gs_shader,
9817                            ac_shader_config* config,
9818                            struct radv_shader_args *args)
9819 {
9820    isel_context ctx = setup_isel_context(program, 1, &gs_shader, config, args, true);
9821
9822    program->next_fp_mode.preserve_signed_zero_inf_nan32 = false;
9823    program->next_fp_mode.preserve_signed_zero_inf_nan16_64 = false;
9824    program->next_fp_mode.must_flush_denorms32 = false;
9825    program->next_fp_mode.must_flush_denorms16_64 = false;
9826    program->next_fp_mode.care_about_round32 = false;
9827    program->next_fp_mode.care_about_round16_64 = false;
9828    program->next_fp_mode.denorm16_64 = fp_denorm_keep;
9829    program->next_fp_mode.denorm32 = 0;
9830    program->next_fp_mode.round32 = fp_round_ne;
9831    program->next_fp_mode.round16_64 = fp_round_ne;
9832    ctx.block->fp_mode = program->next_fp_mode;
9833
9834    add_startpgm(&ctx);
9835    append_logical_start(ctx.block);
9836
9837    Builder bld(ctx.program, ctx.block);
9838
9839    Temp gsvs_ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), program->private_segment_buffer, Operand(RING_GSVS_VS * 16u));
9840
9841    Operand stream_id(0u);
9842    if (args->shader_info->so.num_outputs)
9843       stream_id = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
9844                            get_arg(&ctx, ctx.args->streamout_config), Operand(0x20018u));
9845
9846    Temp vtx_offset = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), get_arg(&ctx, ctx.args->ac.vertex_id));
9847
9848    std::stack<Block> endif_blocks;
9849
9850    for (unsigned stream = 0; stream < 4; stream++) {
9851       if (stream_id.isConstant() && stream != stream_id.constantValue())
9852          continue;
9853
9854       unsigned num_components = args->shader_info->gs.num_stream_output_components[stream];
9855       if (stream > 0 && (!num_components || !args->shader_info->so.num_outputs))
9856          continue;
9857
9858       memset(ctx.outputs.mask, 0, sizeof(ctx.outputs.mask));
9859
9860       unsigned BB_if_idx = ctx.block->index;
9861       Block BB_endif = Block();
9862       if (!stream_id.isConstant()) {
9863          /* begin IF */
9864          Temp cond = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), stream_id, Operand(stream));
9865          append_logical_end(ctx.block);
9866          ctx.block->kind |= block_kind_uniform;
9867          bld.branch(aco_opcode::p_cbranch_z, cond);
9868
9869          BB_endif.kind |= ctx.block->kind & block_kind_top_level;
9870
9871          ctx.block = ctx.program->create_and_insert_block();
9872          add_edge(BB_if_idx, ctx.block);
9873          bld.reset(ctx.block);
9874          append_logical_start(ctx.block);
9875       }
9876
9877       unsigned offset = 0;
9878       for (unsigned i = 0; i <= VARYING_SLOT_VAR31; ++i) {
9879          if (args->shader_info->gs.output_streams[i] != stream)
9880             continue;
9881
9882          unsigned output_usage_mask = args->shader_info->gs.output_usage_mask[i];
9883          unsigned length = util_last_bit(output_usage_mask);
9884          for (unsigned j = 0; j < length; ++j) {
9885             if (!(output_usage_mask & (1 << j)))
9886                continue;
9887
9888             unsigned const_offset = offset * args->shader_info->gs.vertices_out * 16 * 4;
9889             Temp voffset = vtx_offset;
9890             if (const_offset >= 4096u) {
9891                voffset = bld.vadd32(bld.def(v1), Operand(const_offset / 4096u * 4096u), voffset);
9892                const_offset %= 4096u;
9893             }
9894
9895             aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(aco_opcode::buffer_load_dword, Format::MUBUF, 3, 1)};
9896             mubuf->definitions[0] = bld.def(v1);
9897             mubuf->operands[0] = Operand(gsvs_ring);
9898             mubuf->operands[1] = Operand(voffset);
9899             mubuf->operands[2] = Operand(0u);
9900             mubuf->offen = true;
9901             mubuf->offset = const_offset;
9902             mubuf->glc = true;
9903             mubuf->slc = true;
9904             mubuf->dlc = args->options->chip_class >= GFX10;
9905             mubuf->barrier = barrier_none;
9906             mubuf->can_reorder = true;
9907
9908             ctx.outputs.mask[i] |= 1 << j;
9909             ctx.outputs.outputs[i][j] = mubuf->definitions[0].getTemp();
9910
9911             bld.insert(std::move(mubuf));
9912
9913             offset++;
9914          }
9915       }
9916
9917       if (args->shader_info->so.num_outputs) {
9918          emit_streamout(&ctx, stream);
9919          bld.reset(ctx.block);
9920       }
9921
9922       if (stream == 0) {
9923          create_vs_exports(&ctx);
9924          ctx.block->kind |= block_kind_export_end;
9925       }
9926
9927       if (!stream_id.isConstant()) {
9928          append_logical_end(ctx.block);
9929
9930          /* branch from then block to endif block */
9931          bld.branch(aco_opcode::p_branch);
9932          add_edge(ctx.block->index, &BB_endif);
9933          ctx.block->kind |= block_kind_uniform;
9934
9935          /* emit else block */
9936          ctx.block = ctx.program->create_and_insert_block();
9937          add_edge(BB_if_idx, ctx.block);
9938          bld.reset(ctx.block);
9939          append_logical_start(ctx.block);
9940
9941          endif_blocks.push(std::move(BB_endif));
9942       }
9943    }
9944
9945    while (!endif_blocks.empty()) {
9946       Block BB_endif = std::move(endif_blocks.top());
9947       endif_blocks.pop();
9948
9949       Block *BB_else = ctx.block;
9950
9951       append_logical_end(BB_else);
9952       /* branch from else block to endif block */
9953       bld.branch(aco_opcode::p_branch);
9954       add_edge(BB_else->index, &BB_endif);
9955       BB_else->kind |= block_kind_uniform;
9956
9957       /** emit endif merge block */
9958       ctx.block = program->insert_block(std::move(BB_endif));
9959       bld.reset(ctx.block);
9960       append_logical_start(ctx.block);
9961    }
9962
9963    program->config->float_mode = program->blocks[0].fp_mode.val;
9964
9965    append_logical_end(ctx.block);
9966    ctx.block->kind |= block_kind_uniform;
9967    bld.sopp(aco_opcode::s_endpgm);
9968
9969    cleanup_cfg(program);
9970 }
9971 }