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3 * Copyright © 2018 Google
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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
140 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
145 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
147 Builder
bld(ctx
->program
, ctx
->block
);
150 dst
= bld
.tmp(src
.regClass());
152 assert(src
.size() == dst
.size());
154 if (ctx
->stage
!= fragment_fs
) {
158 bld
.copy(Definition(dst
), src
);
162 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
163 ctx
->program
->needs_wqm
|= program_needs_wqm
;
167 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
169 if (index
.regClass() == s1
)
170 return bld
.readlane(bld
.def(s1
), data
, index
);
172 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
174 /* Currently not implemented on GFX6-7 */
175 assert(ctx
->options
->chip_class
>= GFX8
);
177 if (ctx
->options
->chip_class
<= GFX9
|| ctx
->program
->wave_size
== 32) {
178 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
181 /* GFX10, wave64 mode:
182 * The bpermute instruction is limited to half-wave operation, which means that it can't
183 * properly support subgroup shuffle like older generations (or wave32 mode), so we
186 if (!ctx
->has_gfx10_wave64_bpermute
) {
187 ctx
->has_gfx10_wave64_bpermute
= true;
188 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
189 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
192 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
193 Temp lane_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), lane_id
);
194 Temp index_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), index
);
195 Temp cmp
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
, vcc
), lane_is_hi
, index_is_hi
);
197 return bld
.reduction(aco_opcode::p_wave64_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
),
198 bld
.vcc(cmp
), Operand(v2
.as_linear()), index_x4
, data
, gfx10_wave64_bpermute
);
201 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
203 if (val
.type() == RegType::sgpr
) {
204 Builder
bld(ctx
->program
, ctx
->block
);
205 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
207 assert(val
.type() == RegType::vgpr
);
211 //assumes a != 0xffffffff
212 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
215 Builder
bld(ctx
->program
, ctx
->block
);
217 if (util_is_power_of_two_or_zero(b
)) {
218 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
222 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
224 assert(info
.multiplier
<= 0xffffffff);
226 bool pre_shift
= info
.pre_shift
!= 0;
227 bool increment
= info
.increment
!= 0;
228 bool multiply
= true;
229 bool post_shift
= info
.post_shift
!= 0;
231 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
232 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
236 Temp pre_shift_dst
= a
;
238 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
239 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
242 Temp increment_dst
= pre_shift_dst
;
244 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
245 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
248 Temp multiply_dst
= increment_dst
;
250 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
251 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
252 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
256 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
260 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
262 Builder
bld(ctx
->program
, ctx
->block
);
263 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
267 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
269 /* no need to extract the whole vector */
270 if (src
.regClass() == dst_rc
) {
275 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
276 Builder
bld(ctx
->program
, ctx
->block
);
277 auto it
= ctx
->allocated_vec
.find(src
.id());
278 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
279 if (it
->second
[idx
].regClass() == dst_rc
) {
280 return it
->second
[idx
];
282 assert(!dst_rc
.is_subdword());
283 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
284 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
288 if (dst_rc
.is_subdword())
289 src
= as_vgpr(ctx
, src
);
291 if (src
.bytes() == dst_rc
.bytes()) {
293 return bld
.copy(bld
.def(dst_rc
), src
);
295 Temp dst
= bld
.tmp(dst_rc
);
296 emit_extract_vector(ctx
, src
, idx
, dst
);
301 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
303 if (num_components
== 1)
305 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
307 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
308 split
->operands
[0] = Operand(vec_src
);
309 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
311 if (num_components
> vec_src
.size()) {
312 if (vec_src
.type() == RegType::sgpr
)
315 /* sub-dword split */
316 assert(vec_src
.type() == RegType::vgpr
);
317 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
319 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
321 for (unsigned i
= 0; i
< num_components
; i
++) {
322 elems
[i
] = {ctx
->program
->allocateId(), rc
};
323 split
->definitions
[i
] = Definition(elems
[i
]);
325 ctx
->block
->instructions
.emplace_back(std::move(split
));
326 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
329 /* This vector expansion uses a mask to determine which elements in the new vector
330 * come from the original vector. The other elements are undefined. */
331 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
333 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
338 Builder
bld(ctx
->program
, ctx
->block
);
339 if (num_components
== 1) {
340 if (dst
.type() == RegType::sgpr
)
341 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
343 bld
.copy(Definition(dst
), vec_src
);
347 unsigned component_size
= dst
.size() / num_components
;
348 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
350 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
351 vec
->definitions
[0] = Definition(dst
);
353 for (unsigned i
= 0; i
< num_components
; i
++) {
354 if (mask
& (1 << i
)) {
355 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
356 if (dst
.type() == RegType::sgpr
)
357 src
= bld
.as_uniform(src
);
358 vec
->operands
[i
] = Operand(src
);
360 vec
->operands
[i
] = Operand(0u);
362 elems
[i
] = vec
->operands
[i
].getTemp();
364 ctx
->block
->instructions
.emplace_back(std::move(vec
));
365 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
368 /* adjust misaligned small bit size loads */
369 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
371 Builder
bld(ctx
->program
, ctx
->block
);
373 Temp select
= Temp();
374 if (offset
.isConstant()) {
375 assert(offset
.constantValue() && offset
.constantValue() < 4);
376 shift
= Operand(offset
.constantValue() * 8);
378 /* bit_offset = 8 * (offset & 0x3) */
379 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
380 select
= bld
.tmp(s1
);
381 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
384 if (vec
.size() == 1) {
385 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
386 } else if (vec
.size() == 2) {
387 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
388 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
390 emit_split_vector(ctx
, dst
, 2);
392 emit_extract_vector(ctx
, tmp
, 0, dst
);
393 } else if (vec
.size() == 4) {
394 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
395 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
396 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
397 if (select
!= Temp())
398 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), select
);
399 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
400 Temp mid
= bld
.tmp(s1
);
401 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
402 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
403 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
404 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
405 emit_split_vector(ctx
, dst
, 2);
409 /* this function trims subdword vectors:
410 * if dst is vgpr - split the src and create a shrunk version according to the mask.
411 * if dst is sgpr - split the src, but move the original to sgpr. */
412 void trim_subdword_vector(isel_context
*ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
414 assert(vec_src
.type() == RegType::vgpr
);
415 emit_split_vector(ctx
, vec_src
, num_components
);
417 Builder
bld(ctx
->program
, ctx
->block
);
418 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
419 unsigned component_size
= vec_src
.bytes() / num_components
;
420 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
423 for (unsigned i
= 0; i
< num_components
; i
++) {
425 elems
[k
++] = emit_extract_vector(ctx
, vec_src
, i
, rc
);
428 if (dst
.type() == RegType::vgpr
) {
429 assert(dst
.bytes() == k
* component_size
);
430 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, k
, 1)};
431 for (unsigned i
= 0; i
< k
; i
++)
432 vec
->operands
[i
] = Operand(elems
[i
]);
433 vec
->definitions
[0] = Definition(dst
);
434 bld
.insert(std::move(vec
));
436 // TODO: alignbyte if mask doesn't start with 1?
438 assert(dst
.size() == vec_src
.size());
439 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
441 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
444 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
446 Builder
bld(ctx
->program
, ctx
->block
);
448 dst
= bld
.tmp(bld
.lm
);
450 assert(val
.regClass() == s1
);
451 assert(dst
.regClass() == bld
.lm
);
453 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
456 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
458 Builder
bld(ctx
->program
, ctx
->block
);
462 assert(val
.regClass() == bld
.lm
);
463 assert(dst
.regClass() == s1
);
465 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
466 Temp tmp
= bld
.tmp(s1
);
467 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
468 return emit_wqm(ctx
, tmp
, dst
);
471 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
473 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
474 return get_ssa_temp(ctx
, src
.src
.ssa
);
476 if (src
.src
.ssa
->num_components
== size
) {
477 bool identity_swizzle
= true;
478 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
479 if (src
.swizzle
[i
] != i
)
480 identity_swizzle
= false;
482 if (identity_swizzle
)
483 return get_ssa_temp(ctx
, src
.src
.ssa
);
486 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
487 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
488 assert(elem_size
> 0);
489 assert(vec
.bytes() % elem_size
== 0);
491 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
492 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
494 unsigned swizzle
= src
.swizzle
[0];
495 if (vec
.size() > 1) {
496 assert(src
.src
.ssa
->bit_size
== 16);
497 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
498 swizzle
= swizzle
& 1;
503 Temp dst
{ctx
->program
->allocateId(), s1
};
504 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 1)};
505 bfe
->operands
[0] = Operand(vec
);
506 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
507 bfe
->definitions
[0] = Definition(dst
);
508 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
512 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
514 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
517 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
518 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
519 for (unsigned i
= 0; i
< size
; ++i
) {
520 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
521 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
523 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
524 vec_instr
->definitions
[0] = Definition(dst
);
525 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
526 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
531 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
535 Builder
bld(ctx
->program
, ctx
->block
);
536 if (ptr
.type() == RegType::vgpr
)
537 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
538 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
539 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
542 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
544 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
545 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
546 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
547 sop2
->definitions
[0] = Definition(dst
);
549 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
550 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
553 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
554 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
556 Builder
bld(ctx
->program
, ctx
->block
);
557 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
558 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
559 if (src1
.type() == RegType::sgpr
) {
560 if (commutative
&& src0
.type() == RegType::vgpr
) {
564 } else if (src0
.type() == RegType::vgpr
&&
565 op
!= aco_opcode::v_madmk_f32
&&
566 op
!= aco_opcode::v_madak_f32
&&
567 op
!= aco_opcode::v_madmk_f16
&&
568 op
!= aco_opcode::v_madak_f16
) {
569 /* If the instruction is not commutative, we emit a VOP3A instruction */
570 bld
.vop2_e64(op
, Definition(dst
), src0
, src1
);
573 src1
= bld
.copy(bld
.def(RegType::vgpr
, src1
.size()), src1
); //TODO: as_vgpr
577 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
578 assert(dst
.size() == 1);
579 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
580 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
582 bld
.vop2(op
, Definition(dst
), src0
, src1
);
586 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
587 bool flush_denorms
= false)
589 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
590 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
591 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
593 /* ensure that the instruction has at most 1 sgpr operand
594 * The optimizer will inline constants for us */
595 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
596 src0
= as_vgpr(ctx
, src0
);
597 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
598 src1
= as_vgpr(ctx
, src1
);
599 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
600 src2
= as_vgpr(ctx
, src2
);
602 Builder
bld(ctx
->program
, ctx
->block
);
603 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
604 assert(dst
.size() == 1);
605 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
606 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
608 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
612 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
614 Builder
bld(ctx
->program
, ctx
->block
);
615 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
618 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
620 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
621 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
622 assert(src0
.size() == src1
.size());
624 aco_ptr
<Instruction
> vopc
;
625 if (src1
.type() == RegType::sgpr
) {
626 if (src0
.type() == RegType::vgpr
) {
627 /* to swap the operands, we might also have to change the opcode */
629 case aco_opcode::v_cmp_lt_f16
:
630 op
= aco_opcode::v_cmp_gt_f16
;
632 case aco_opcode::v_cmp_ge_f16
:
633 op
= aco_opcode::v_cmp_le_f16
;
635 case aco_opcode::v_cmp_lt_i16
:
636 op
= aco_opcode::v_cmp_gt_i16
;
638 case aco_opcode::v_cmp_ge_i16
:
639 op
= aco_opcode::v_cmp_le_i16
;
641 case aco_opcode::v_cmp_lt_u16
:
642 op
= aco_opcode::v_cmp_gt_u16
;
644 case aco_opcode::v_cmp_ge_u16
:
645 op
= aco_opcode::v_cmp_le_u16
;
647 case aco_opcode::v_cmp_lt_f32
:
648 op
= aco_opcode::v_cmp_gt_f32
;
650 case aco_opcode::v_cmp_ge_f32
:
651 op
= aco_opcode::v_cmp_le_f32
;
653 case aco_opcode::v_cmp_lt_i32
:
654 op
= aco_opcode::v_cmp_gt_i32
;
656 case aco_opcode::v_cmp_ge_i32
:
657 op
= aco_opcode::v_cmp_le_i32
;
659 case aco_opcode::v_cmp_lt_u32
:
660 op
= aco_opcode::v_cmp_gt_u32
;
662 case aco_opcode::v_cmp_ge_u32
:
663 op
= aco_opcode::v_cmp_le_u32
;
665 case aco_opcode::v_cmp_lt_f64
:
666 op
= aco_opcode::v_cmp_gt_f64
;
668 case aco_opcode::v_cmp_ge_f64
:
669 op
= aco_opcode::v_cmp_le_f64
;
671 case aco_opcode::v_cmp_lt_i64
:
672 op
= aco_opcode::v_cmp_gt_i64
;
674 case aco_opcode::v_cmp_ge_i64
:
675 op
= aco_opcode::v_cmp_le_i64
;
677 case aco_opcode::v_cmp_lt_u64
:
678 op
= aco_opcode::v_cmp_gt_u64
;
680 case aco_opcode::v_cmp_ge_u64
:
681 op
= aco_opcode::v_cmp_le_u64
;
683 default: /* eq and ne are commutative */
690 src1
= as_vgpr(ctx
, src1
);
694 Builder
bld(ctx
->program
, ctx
->block
);
695 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
698 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
700 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
701 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
702 Builder
bld(ctx
->program
, ctx
->block
);
704 assert(dst
.regClass() == bld
.lm
);
705 assert(src0
.type() == RegType::sgpr
);
706 assert(src1
.type() == RegType::sgpr
);
707 assert(src0
.regClass() == src1
.regClass());
709 /* Emit the SALU comparison instruction */
710 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
711 /* Turn the result into a per-lane bool */
712 bool_to_vector_condition(ctx
, cmp
, dst
);
715 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
716 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
718 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
719 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
720 bool divergent_vals
= ctx
->divergent_vals
[instr
->dest
.dest
.ssa
.index
];
721 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
723 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
724 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
725 aco_opcode op
= use_valu
? v_op
: s_op
;
726 assert(op
!= aco_opcode::num_opcodes
);
727 assert(dst
.regClass() == ctx
->program
->lane_mask
);
730 emit_vopc_instruction(ctx
, instr
, op
, dst
);
732 emit_sopc_instruction(ctx
, instr
, op
, dst
);
735 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
737 Builder
bld(ctx
->program
, ctx
->block
);
738 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
739 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
741 assert(dst
.regClass() == bld
.lm
);
742 assert(src0
.regClass() == bld
.lm
);
743 assert(src1
.regClass() == bld
.lm
);
745 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
748 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
750 Builder
bld(ctx
->program
, ctx
->block
);
751 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
752 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
753 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
755 assert(cond
.regClass() == bld
.lm
);
757 if (dst
.type() == RegType::vgpr
) {
758 aco_ptr
<Instruction
> bcsel
;
759 if (dst
.regClass() == v2b
) {
760 then
= as_vgpr(ctx
, then
);
761 els
= as_vgpr(ctx
, els
);
763 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), els
, then
, cond
);
764 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
765 } else if (dst
.regClass() == v1
) {
766 then
= as_vgpr(ctx
, then
);
767 els
= as_vgpr(ctx
, els
);
769 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
770 } else if (dst
.regClass() == v2
) {
771 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
772 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
773 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
774 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
776 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
777 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
779 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
781 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
782 nir_print_instr(&instr
->instr
, stderr
);
783 fprintf(stderr
, "\n");
788 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
789 assert(dst
.regClass() == bld
.lm
);
790 assert(then
.regClass() == bld
.lm
);
791 assert(els
.regClass() == bld
.lm
);
794 if (!ctx
->divergent_vals
[instr
->src
[0].src
.ssa
->index
]) { /* uniform condition and values in sgpr */
795 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
796 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
797 assert(dst
.size() == then
.size());
798 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
799 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
801 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
802 nir_print_instr(&instr
->instr
, stderr
);
803 fprintf(stderr
, "\n");
808 /* divergent boolean bcsel
809 * this implements bcsel on bools: dst = s0 ? s1 : s2
810 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
811 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
813 if (cond
.id() != then
.id())
814 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
816 if (cond
.id() == els
.id())
817 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
819 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
820 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
823 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
824 aco_opcode op
, uint32_t undo
)
826 /* multiply by 16777216 to handle denormals */
827 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
828 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
829 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
830 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
831 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
833 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
835 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
838 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
840 if (ctx
->block
->fp_mode
.denorm32
== 0) {
841 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
845 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
848 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
850 if (ctx
->block
->fp_mode
.denorm32
== 0) {
851 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
855 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
858 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
860 if (ctx
->block
->fp_mode
.denorm32
== 0) {
861 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
865 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
868 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
870 if (ctx
->block
->fp_mode
.denorm32
== 0) {
871 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
875 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
878 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
880 if (ctx
->options
->chip_class
>= GFX7
)
881 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
883 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
884 /* TODO: create more efficient code! */
885 if (val
.type() == RegType::sgpr
)
886 val
= as_vgpr(ctx
, val
);
888 /* Split the input value. */
889 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
890 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
892 /* Extract the exponent and compute the unbiased value. */
893 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, bld
.def(v1
), val
);
895 /* Extract the fractional part. */
896 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
897 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
899 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
900 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
902 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
903 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
904 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
905 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
906 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
908 /* Get the sign bit. */
909 Temp sign
= bld
.vop2(aco_opcode::v_ashr_i32
, bld
.def(v1
), Operand(31u), val_hi
);
911 /* Decide the operation to apply depending on the unbiased exponent. */
912 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
913 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
914 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
915 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
916 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
917 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
919 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
922 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
924 if (ctx
->options
->chip_class
>= GFX7
)
925 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
927 /* GFX6 doesn't support V_FLOOR_F64, lower it. */
928 Temp src0
= as_vgpr(ctx
, val
);
930 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
931 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
933 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
934 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
935 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
937 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
938 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
939 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
940 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
942 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
943 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
945 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
947 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
948 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
950 return add
->definitions
[0].getTemp();
953 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
955 if (!instr
->dest
.dest
.is_ssa
) {
956 fprintf(stderr
, "nir alu dst not in ssa: ");
957 nir_print_instr(&instr
->instr
, stderr
);
958 fprintf(stderr
, "\n");
961 Builder
bld(ctx
->program
, ctx
->block
);
962 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
967 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
968 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
969 for (unsigned i
= 0; i
< num
; ++i
)
970 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
972 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
973 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
974 for (unsigned i
= 0; i
< num
; ++i
)
975 vec
->operands
[i
] = Operand
{elems
[i
]};
976 vec
->definitions
[0] = Definition(dst
);
977 ctx
->block
->instructions
.emplace_back(std::move(vec
));
978 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
980 // TODO: that is a bit suboptimal..
981 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
982 for (unsigned i
= 0; i
< num
- 1; ++i
)
983 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
984 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
985 for (unsigned i
= 0; i
< num
; ++i
) {
986 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
988 elems
[bit
/ 32] = elems
[i
];
990 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
991 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
992 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
996 bld
.copy(Definition(dst
), elems
[0]);
998 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1003 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1004 aco_ptr
<Instruction
> mov
;
1005 if (dst
.type() == RegType::sgpr
) {
1006 if (src
.type() == RegType::vgpr
)
1007 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1008 else if (src
.regClass() == s1
)
1009 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1010 else if (src
.regClass() == s2
)
1011 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1013 unreachable("wrong src register class for nir_op_imov");
1014 } else if (dst
.regClass() == v1
) {
1015 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1016 } else if (dst
.regClass() == v2
) {
1017 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1019 nir_print_instr(&instr
->instr
, stderr
);
1020 unreachable("Should have been lowered to scalar.");
1025 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1026 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1027 assert(src
.regClass() == bld
.lm
);
1028 assert(dst
.regClass() == bld
.lm
);
1029 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1030 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1031 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1032 } else if (dst
.regClass() == v1
) {
1033 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1034 } else if (dst
.type() == RegType::sgpr
) {
1035 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1036 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1038 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1039 nir_print_instr(&instr
->instr
, stderr
);
1040 fprintf(stderr
, "\n");
1045 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1046 if (dst
.regClass() == v1
) {
1047 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1048 } else if (dst
.regClass() == s1
) {
1049 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1050 } else if (dst
.size() == 2) {
1051 Temp src0
= bld
.tmp(dst
.type(), 1);
1052 Temp src1
= bld
.tmp(dst
.type(), 1);
1053 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1055 if (dst
.regClass() == s2
) {
1056 Temp carry
= bld
.tmp(s1
);
1057 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1058 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1059 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1061 Temp lower
= bld
.tmp(v1
);
1062 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1063 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1064 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1067 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1068 nir_print_instr(&instr
->instr
, stderr
);
1069 fprintf(stderr
, "\n");
1074 if (dst
.regClass() == s1
) {
1075 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1076 } else if (dst
.regClass() == v1
) {
1077 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1078 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1080 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1081 nir_print_instr(&instr
->instr
, stderr
);
1082 fprintf(stderr
, "\n");
1086 case nir_op_isign
: {
1087 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1088 if (dst
.regClass() == s1
) {
1089 Temp tmp
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
1090 Temp gtz
= bld
.sopc(aco_opcode::s_cmp_gt_i32
, bld
.def(s1
, scc
), src
, Operand(0u));
1091 bld
.sop2(aco_opcode::s_add_i32
, Definition(dst
), bld
.def(s1
, scc
), gtz
, tmp
);
1092 } else if (dst
.regClass() == s2
) {
1093 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1095 if (ctx
->program
->chip_class
>= GFX8
)
1096 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1098 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1099 /* SCC gets zero-extended to 64 bit */
1100 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1101 } else if (dst
.regClass() == v1
) {
1102 Temp tmp
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
1103 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1104 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(1u), tmp
, gtz
);
1105 } else if (dst
.regClass() == v2
) {
1106 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1107 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1108 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1109 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1110 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1111 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1113 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1114 nir_print_instr(&instr
->instr
, stderr
);
1115 fprintf(stderr
, "\n");
1120 if (dst
.regClass() == v1
) {
1121 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1122 } else if (dst
.regClass() == s1
) {
1123 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1125 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1126 nir_print_instr(&instr
->instr
, stderr
);
1127 fprintf(stderr
, "\n");
1132 if (dst
.regClass() == v1
) {
1133 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1134 } else if (dst
.regClass() == s1
) {
1135 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1137 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1138 nir_print_instr(&instr
->instr
, stderr
);
1139 fprintf(stderr
, "\n");
1144 if (dst
.regClass() == v1
) {
1145 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1146 } else if (dst
.regClass() == s1
) {
1147 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1149 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1150 nir_print_instr(&instr
->instr
, stderr
);
1151 fprintf(stderr
, "\n");
1156 if (dst
.regClass() == v1
) {
1157 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1158 } else if (dst
.regClass() == s1
) {
1159 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1161 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1162 nir_print_instr(&instr
->instr
, stderr
);
1163 fprintf(stderr
, "\n");
1168 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1169 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1170 } else if (dst
.regClass() == v1
) {
1171 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1172 } else if (dst
.regClass() == s1
) {
1173 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1174 } else if (dst
.regClass() == s2
) {
1175 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1177 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1178 nir_print_instr(&instr
->instr
, stderr
);
1179 fprintf(stderr
, "\n");
1184 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1185 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1186 } else if (dst
.regClass() == v1
) {
1187 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1188 } else if (dst
.regClass() == s1
) {
1189 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1190 } else if (dst
.regClass() == s2
) {
1191 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1193 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1194 nir_print_instr(&instr
->instr
, stderr
);
1195 fprintf(stderr
, "\n");
1200 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1201 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1202 } else if (dst
.regClass() == v1
) {
1203 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1204 } else if (dst
.regClass() == s1
) {
1205 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1206 } else if (dst
.regClass() == s2
) {
1207 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1209 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1210 nir_print_instr(&instr
->instr
, stderr
);
1211 fprintf(stderr
, "\n");
1216 if (dst
.regClass() == v1
) {
1217 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1218 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1219 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1220 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1221 } else if (dst
.regClass() == v2
) {
1222 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1223 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1224 } else if (dst
.regClass() == s2
) {
1225 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1226 } else if (dst
.regClass() == s1
) {
1227 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1229 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1230 nir_print_instr(&instr
->instr
, stderr
);
1231 fprintf(stderr
, "\n");
1236 if (dst
.regClass() == v1
) {
1237 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1238 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1239 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1240 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1241 } else if (dst
.regClass() == v2
) {
1242 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1243 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1244 } else if (dst
.regClass() == s1
) {
1245 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1246 } else if (dst
.regClass() == s2
) {
1247 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1249 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1250 nir_print_instr(&instr
->instr
, stderr
);
1251 fprintf(stderr
, "\n");
1256 if (dst
.regClass() == v1
) {
1257 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1258 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1259 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1260 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1261 } else if (dst
.regClass() == v2
) {
1262 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1263 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1264 } else if (dst
.regClass() == s1
) {
1265 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1266 } else if (dst
.regClass() == s2
) {
1267 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1269 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1270 nir_print_instr(&instr
->instr
, stderr
);
1271 fprintf(stderr
, "\n");
1275 case nir_op_find_lsb
: {
1276 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1277 if (src
.regClass() == s1
) {
1278 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1279 } else if (src
.regClass() == v1
) {
1280 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1281 } else if (src
.regClass() == s2
) {
1282 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1284 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1285 nir_print_instr(&instr
->instr
, stderr
);
1286 fprintf(stderr
, "\n");
1290 case nir_op_ufind_msb
:
1291 case nir_op_ifind_msb
: {
1292 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1293 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1294 aco_opcode op
= src
.regClass() == s2
?
1295 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1296 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1297 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1299 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1300 Operand(src
.size() * 32u - 1u), msb_rev
);
1301 Temp msb
= sub
.def(0).getTemp();
1302 Temp carry
= sub
.def(1).getTemp();
1304 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1305 } else if (src
.regClass() == v1
) {
1306 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1307 Temp msb_rev
= bld
.tmp(v1
);
1308 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1309 Temp msb
= bld
.tmp(v1
);
1310 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1311 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1313 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1314 nir_print_instr(&instr
->instr
, stderr
);
1315 fprintf(stderr
, "\n");
1319 case nir_op_bitfield_reverse
: {
1320 if (dst
.regClass() == s1
) {
1321 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1322 } else if (dst
.regClass() == v1
) {
1323 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1325 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1326 nir_print_instr(&instr
->instr
, stderr
);
1327 fprintf(stderr
, "\n");
1332 if (dst
.regClass() == s1
) {
1333 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1337 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1338 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1339 if (dst
.regClass() == v1
) {
1340 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1344 assert(src0
.size() == 2 && src1
.size() == 2);
1345 Temp src00
= bld
.tmp(src0
.type(), 1);
1346 Temp src01
= bld
.tmp(dst
.type(), 1);
1347 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1348 Temp src10
= bld
.tmp(src1
.type(), 1);
1349 Temp src11
= bld
.tmp(dst
.type(), 1);
1350 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1352 if (dst
.regClass() == s2
) {
1353 Temp carry
= bld
.tmp(s1
);
1354 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1355 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1356 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1357 } else if (dst
.regClass() == v2
) {
1358 Temp dst0
= bld
.tmp(v1
);
1359 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1360 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1361 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1363 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1364 nir_print_instr(&instr
->instr
, stderr
);
1365 fprintf(stderr
, "\n");
1369 case nir_op_uadd_sat
: {
1370 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1371 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1372 if (dst
.regClass() == s1
) {
1373 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1374 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1376 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1377 } else if (dst
.regClass() == v1
) {
1378 if (ctx
->options
->chip_class
>= GFX9
) {
1379 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1380 add
->operands
[0] = Operand(src0
);
1381 add
->operands
[1] = Operand(src1
);
1382 add
->definitions
[0] = Definition(dst
);
1384 ctx
->block
->instructions
.emplace_back(std::move(add
));
1386 if (src1
.regClass() != v1
)
1387 std::swap(src0
, src1
);
1388 assert(src1
.regClass() == v1
);
1389 Temp tmp
= bld
.tmp(v1
);
1390 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1391 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1394 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1395 nir_print_instr(&instr
->instr
, stderr
);
1396 fprintf(stderr
, "\n");
1400 case nir_op_uadd_carry
: {
1401 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1402 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1403 if (dst
.regClass() == s1
) {
1404 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1407 if (dst
.regClass() == v1
) {
1408 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1409 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1413 Temp src00
= bld
.tmp(src0
.type(), 1);
1414 Temp src01
= bld
.tmp(dst
.type(), 1);
1415 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1416 Temp src10
= bld
.tmp(src1
.type(), 1);
1417 Temp src11
= bld
.tmp(dst
.type(), 1);
1418 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1419 if (dst
.regClass() == s2
) {
1420 Temp carry
= bld
.tmp(s1
);
1421 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1422 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1423 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1424 } else if (dst
.regClass() == v2
) {
1425 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1426 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1427 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1428 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1430 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1431 nir_print_instr(&instr
->instr
, stderr
);
1432 fprintf(stderr
, "\n");
1437 if (dst
.regClass() == s1
) {
1438 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1442 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1443 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1444 if (dst
.regClass() == v1
) {
1445 bld
.vsub32(Definition(dst
), src0
, src1
);
1449 Temp src00
= bld
.tmp(src0
.type(), 1);
1450 Temp src01
= bld
.tmp(dst
.type(), 1);
1451 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1452 Temp src10
= bld
.tmp(src1
.type(), 1);
1453 Temp src11
= bld
.tmp(dst
.type(), 1);
1454 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1455 if (dst
.regClass() == s2
) {
1456 Temp carry
= bld
.tmp(s1
);
1457 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1458 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1459 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1460 } else if (dst
.regClass() == v2
) {
1461 Temp lower
= bld
.tmp(v1
);
1462 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1463 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1464 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1466 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1467 nir_print_instr(&instr
->instr
, stderr
);
1468 fprintf(stderr
, "\n");
1472 case nir_op_usub_borrow
: {
1473 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1474 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1475 if (dst
.regClass() == s1
) {
1476 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1478 } else if (dst
.regClass() == v1
) {
1479 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1480 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1484 Temp src00
= bld
.tmp(src0
.type(), 1);
1485 Temp src01
= bld
.tmp(dst
.type(), 1);
1486 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1487 Temp src10
= bld
.tmp(src1
.type(), 1);
1488 Temp src11
= bld
.tmp(dst
.type(), 1);
1489 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1490 if (dst
.regClass() == s2
) {
1491 Temp borrow
= bld
.tmp(s1
);
1492 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1493 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1494 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1495 } else if (dst
.regClass() == v2
) {
1496 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1497 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1498 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1499 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1501 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1502 nir_print_instr(&instr
->instr
, stderr
);
1503 fprintf(stderr
, "\n");
1508 if (dst
.regClass() == v1
) {
1509 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1510 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1511 } else if (dst
.regClass() == s1
) {
1512 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1514 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1515 nir_print_instr(&instr
->instr
, stderr
);
1516 fprintf(stderr
, "\n");
1520 case nir_op_umul_high
: {
1521 if (dst
.regClass() == v1
) {
1522 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1523 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1524 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1525 } else if (dst
.regClass() == s1
) {
1526 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1527 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1528 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1530 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1531 nir_print_instr(&instr
->instr
, stderr
);
1532 fprintf(stderr
, "\n");
1536 case nir_op_imul_high
: {
1537 if (dst
.regClass() == v1
) {
1538 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1539 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1540 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1541 } else if (dst
.regClass() == s1
) {
1542 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1543 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1544 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1546 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1547 nir_print_instr(&instr
->instr
, stderr
);
1548 fprintf(stderr
, "\n");
1553 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1554 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1555 if (dst
.regClass() == v2b
) {
1556 Temp tmp
= bld
.tmp(v1
);
1557 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, tmp
, true);
1558 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1559 } else if (dst
.regClass() == v1
) {
1560 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1561 } else if (dst
.regClass() == v2
) {
1562 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1564 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1565 nir_print_instr(&instr
->instr
, stderr
);
1566 fprintf(stderr
, "\n");
1571 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1572 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1573 if (dst
.regClass() == v2b
) {
1574 Temp tmp
= bld
.tmp(v1
);
1575 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, tmp
, true);
1576 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1577 } else if (dst
.regClass() == v1
) {
1578 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1579 } else if (dst
.regClass() == v2
) {
1580 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1582 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1583 nir_print_instr(&instr
->instr
, stderr
);
1584 fprintf(stderr
, "\n");
1589 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1590 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1591 if (dst
.regClass() == v2b
) {
1592 Temp tmp
= bld
.tmp(v1
);
1593 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1594 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, tmp
, false);
1596 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, tmp
, true);
1597 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1598 } else if (dst
.regClass() == v1
) {
1599 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1600 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1602 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1603 } else if (dst
.regClass() == v2
) {
1604 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1606 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1609 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1610 nir_print_instr(&instr
->instr
, stderr
);
1611 fprintf(stderr
, "\n");
1616 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1617 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1618 if (dst
.regClass() == v2b
) {
1619 // TODO: check fp_mode.must_flush_denorms16_64
1620 Temp tmp
= bld
.tmp(v1
);
1621 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, tmp
, true);
1622 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1623 } else if (dst
.regClass() == v1
) {
1624 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1625 } else if (dst
.regClass() == v2
) {
1626 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1627 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1628 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1630 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1633 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1634 nir_print_instr(&instr
->instr
, stderr
);
1635 fprintf(stderr
, "\n");
1640 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1641 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1642 if (dst
.regClass() == v2b
) {
1643 // TODO: check fp_mode.must_flush_denorms16_64
1644 Temp tmp
= bld
.tmp(v1
);
1645 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, tmp
, true);
1646 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1647 } else if (dst
.regClass() == v1
) {
1648 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1649 } else if (dst
.regClass() == v2
) {
1650 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1651 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1652 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1654 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1657 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1658 nir_print_instr(&instr
->instr
, stderr
);
1659 fprintf(stderr
, "\n");
1663 case nir_op_fmax3
: {
1664 if (dst
.regClass() == v2b
) {
1665 Temp tmp
= bld
.tmp(v1
);
1666 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f16
, tmp
, false);
1667 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1668 } else if (dst
.regClass() == v1
) {
1669 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1671 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1672 nir_print_instr(&instr
->instr
, stderr
);
1673 fprintf(stderr
, "\n");
1677 case nir_op_fmin3
: {
1678 if (dst
.regClass() == v2b
) {
1679 Temp tmp
= bld
.tmp(v1
);
1680 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f16
, tmp
, false);
1681 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1682 } else if (dst
.regClass() == v1
) {
1683 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1685 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1686 nir_print_instr(&instr
->instr
, stderr
);
1687 fprintf(stderr
, "\n");
1691 case nir_op_fmed3
: {
1692 if (dst
.regClass() == v2b
) {
1693 Temp tmp
= bld
.tmp(v1
);
1694 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f16
, tmp
, false);
1695 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1696 } else if (dst
.regClass() == v1
) {
1697 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1699 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1700 nir_print_instr(&instr
->instr
, stderr
);
1701 fprintf(stderr
, "\n");
1705 case nir_op_umax3
: {
1706 if (dst
.size() == 1) {
1707 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1709 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1710 nir_print_instr(&instr
->instr
, stderr
);
1711 fprintf(stderr
, "\n");
1715 case nir_op_umin3
: {
1716 if (dst
.size() == 1) {
1717 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1719 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1720 nir_print_instr(&instr
->instr
, stderr
);
1721 fprintf(stderr
, "\n");
1725 case nir_op_umed3
: {
1726 if (dst
.size() == 1) {
1727 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1729 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1730 nir_print_instr(&instr
->instr
, stderr
);
1731 fprintf(stderr
, "\n");
1735 case nir_op_imax3
: {
1736 if (dst
.size() == 1) {
1737 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1739 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1740 nir_print_instr(&instr
->instr
, stderr
);
1741 fprintf(stderr
, "\n");
1745 case nir_op_imin3
: {
1746 if (dst
.size() == 1) {
1747 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1749 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1750 nir_print_instr(&instr
->instr
, stderr
);
1751 fprintf(stderr
, "\n");
1755 case nir_op_imed3
: {
1756 if (dst
.size() == 1) {
1757 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1759 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1760 nir_print_instr(&instr
->instr
, stderr
);
1761 fprintf(stderr
, "\n");
1765 case nir_op_cube_face_coord
: {
1766 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1767 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1768 emit_extract_vector(ctx
, in
, 1, v1
),
1769 emit_extract_vector(ctx
, in
, 2, v1
) };
1770 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1771 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1772 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1773 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1774 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1775 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1776 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1779 case nir_op_cube_face_index
: {
1780 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1781 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1782 emit_extract_vector(ctx
, in
, 1, v1
),
1783 emit_extract_vector(ctx
, in
, 2, v1
) };
1784 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1787 case nir_op_bcsel
: {
1788 emit_bcsel(ctx
, instr
, dst
);
1792 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1793 if (dst
.regClass() == v2b
) {
1794 Temp tmp
= bld
.vop1(aco_opcode::v_rsq_f16
, bld
.def(v1
), src
);
1795 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1796 } else if (dst
.regClass() == v1
) {
1797 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1798 } else if (dst
.regClass() == v2
) {
1799 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1801 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1802 nir_print_instr(&instr
->instr
, stderr
);
1803 fprintf(stderr
, "\n");
1808 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1809 if (dst
.regClass() == v2b
) {
1810 Temp tmp
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1811 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1812 } else if (dst
.regClass() == v1
) {
1813 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1814 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1815 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1816 } else if (dst
.regClass() == v2
) {
1817 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1818 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1819 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1820 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1821 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1822 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1824 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1825 nir_print_instr(&instr
->instr
, stderr
);
1826 fprintf(stderr
, "\n");
1831 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1832 if (dst
.regClass() == v2b
) {
1833 Temp tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1834 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1835 } else if (dst
.regClass() == v1
) {
1836 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1837 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1838 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1839 } else if (dst
.regClass() == v2
) {
1840 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1841 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1842 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1843 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1844 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1845 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1847 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1848 nir_print_instr(&instr
->instr
, stderr
);
1849 fprintf(stderr
, "\n");
1854 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1855 if (dst
.regClass() == v2b
) {
1856 Temp tmp
= bld
.vop3(aco_opcode::v_med3_f16
, bld
.def(v1
), Operand(0u), Operand(0x3f800000u
), src
);
1857 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1858 } else if (dst
.regClass() == v1
) {
1859 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1860 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1861 // TODO: confirm that this holds under any circumstances
1862 } else if (dst
.regClass() == v2
) {
1863 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1864 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1867 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1868 nir_print_instr(&instr
->instr
, stderr
);
1869 fprintf(stderr
, "\n");
1873 case nir_op_flog2
: {
1874 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1875 if (dst
.regClass() == v2b
) {
1876 Temp tmp
= bld
.vop1(aco_opcode::v_log_f16
, bld
.def(v1
), src
);
1877 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1878 } else if (dst
.regClass() == v1
) {
1879 emit_log2(ctx
, bld
, Definition(dst
), src
);
1881 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1882 nir_print_instr(&instr
->instr
, stderr
);
1883 fprintf(stderr
, "\n");
1888 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1889 if (dst
.regClass() == v2b
) {
1890 Temp tmp
= bld
.vop1(aco_opcode::v_rcp_f16
, bld
.def(v1
), src
);
1891 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1892 } else if (dst
.regClass() == v1
) {
1893 emit_rcp(ctx
, bld
, Definition(dst
), src
);
1894 } else if (dst
.regClass() == v2
) {
1895 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1897 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1898 nir_print_instr(&instr
->instr
, stderr
);
1899 fprintf(stderr
, "\n");
1903 case nir_op_fexp2
: {
1904 if (dst
.regClass() == v2b
) {
1905 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1906 Temp tmp
= bld
.vop1(aco_opcode::v_exp_f16
, bld
.def(v1
), src
);
1907 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1908 } else if (dst
.regClass() == v1
) {
1909 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1911 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1912 nir_print_instr(&instr
->instr
, stderr
);
1913 fprintf(stderr
, "\n");
1917 case nir_op_fsqrt
: {
1918 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1919 if (dst
.regClass() == v2b
) {
1920 Temp tmp
= bld
.vop1(aco_opcode::v_sqrt_f16
, bld
.def(v1
), src
);
1921 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1922 } else if (dst
.regClass() == v1
) {
1923 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
1924 } else if (dst
.regClass() == v2
) {
1925 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1927 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1928 nir_print_instr(&instr
->instr
, stderr
);
1929 fprintf(stderr
, "\n");
1933 case nir_op_ffract
: {
1934 if (dst
.regClass() == v2b
) {
1935 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1936 Temp tmp
= bld
.vop1(aco_opcode::v_fract_f16
, bld
.def(v1
), src
);
1937 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1938 } else if (dst
.regClass() == v1
) {
1939 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1940 } else if (dst
.regClass() == v2
) {
1941 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1943 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1944 nir_print_instr(&instr
->instr
, stderr
);
1945 fprintf(stderr
, "\n");
1949 case nir_op_ffloor
: {
1950 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1951 if (dst
.regClass() == v2b
) {
1952 Temp tmp
= bld
.vop1(aco_opcode::v_floor_f16
, bld
.def(v1
), src
);
1953 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1954 } else if (dst
.regClass() == v1
) {
1955 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
1956 } else if (dst
.regClass() == v2
) {
1957 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
1959 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1960 nir_print_instr(&instr
->instr
, stderr
);
1961 fprintf(stderr
, "\n");
1965 case nir_op_fceil
: {
1966 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1967 if (dst
.regClass() == v2b
) {
1968 Temp tmp
= bld
.vop1(aco_opcode::v_ceil_f16
, bld
.def(v1
), src0
);
1969 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1970 } else if (dst
.regClass() == v1
) {
1971 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
1972 } else if (dst
.regClass() == v2
) {
1973 if (ctx
->options
->chip_class
>= GFX7
) {
1974 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
1976 /* GFX6 doesn't support V_CEIL_F64, lower it. */
1977 /* trunc = trunc(src0)
1978 * if (src0 > 0.0 && src0 != trunc)
1981 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
1982 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
1983 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
1984 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
1985 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
1986 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
1987 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
1990 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1991 nir_print_instr(&instr
->instr
, stderr
);
1992 fprintf(stderr
, "\n");
1996 case nir_op_ftrunc
: {
1997 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1998 if (dst
.regClass() == v2b
) {
1999 Temp tmp
= bld
.vop1(aco_opcode::v_trunc_f16
, bld
.def(v1
), src
);
2000 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2001 } else if (dst
.regClass() == v1
) {
2002 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2003 } else if (dst
.regClass() == v2
) {
2004 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2006 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2007 nir_print_instr(&instr
->instr
, stderr
);
2008 fprintf(stderr
, "\n");
2012 case nir_op_fround_even
: {
2013 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2014 if (dst
.regClass() == v2b
) {
2015 Temp tmp
= bld
.vop1(aco_opcode::v_rndne_f16
, bld
.def(v1
), src0
);
2016 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2017 } else if (dst
.regClass() == v1
) {
2018 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2019 } else if (dst
.regClass() == v2
) {
2020 if (ctx
->options
->chip_class
>= GFX7
) {
2021 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2023 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2024 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2025 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2027 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2028 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2029 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2030 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2031 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2032 tmp
= sub
->definitions
[0].getTemp();
2034 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2035 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2036 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2037 Temp cond
= vop3
->definitions
[0].getTemp();
2039 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2040 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2041 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2042 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2044 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2047 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2048 nir_print_instr(&instr
->instr
, stderr
);
2049 fprintf(stderr
, "\n");
2055 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2056 aco_ptr
<Instruction
> norm
;
2057 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2058 if (dst
.regClass() == v2b
) {
2059 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2060 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2061 tmp
= bld
.vop1(opcode
, bld
.def(v1
), tmp
);
2062 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2063 } else if (dst
.regClass() == v1
) {
2064 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2066 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2067 if (ctx
->options
->chip_class
< GFX9
)
2068 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2070 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2071 bld
.vop1(opcode
, Definition(dst
), tmp
);
2073 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2074 nir_print_instr(&instr
->instr
, stderr
);
2075 fprintf(stderr
, "\n");
2079 case nir_op_ldexp
: {
2080 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2081 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2082 if (dst
.regClass() == v2b
) {
2083 Temp tmp
= bld
.tmp(v1
);
2084 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, tmp
, false);
2085 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2086 } else if (dst
.regClass() == v1
) {
2087 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2088 } else if (dst
.regClass() == v2
) {
2089 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2091 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2092 nir_print_instr(&instr
->instr
, stderr
);
2093 fprintf(stderr
, "\n");
2097 case nir_op_frexp_sig
: {
2098 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2099 if (dst
.regClass() == v2b
) {
2100 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_mant_f16
, bld
.def(v1
), src
);
2101 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2102 } else if (dst
.regClass() == v1
) {
2103 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2104 } else if (dst
.regClass() == v2
) {
2105 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2107 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2108 nir_print_instr(&instr
->instr
, stderr
);
2109 fprintf(stderr
, "\n");
2113 case nir_op_frexp_exp
: {
2114 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2115 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2116 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2117 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), tmp
, Operand(0u));
2118 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2119 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2120 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2121 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2123 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2124 nir_print_instr(&instr
->instr
, stderr
);
2125 fprintf(stderr
, "\n");
2129 case nir_op_fsign
: {
2130 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2131 if (dst
.regClass() == v2b
) {
2132 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2133 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2134 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2135 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2136 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2137 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), minus_one
, src
, cond
);
2138 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2139 } else if (dst
.regClass() == v1
) {
2140 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2141 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2142 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2143 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2144 } else if (dst
.regClass() == v2
) {
2145 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2146 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2147 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2149 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2150 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2151 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2153 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2155 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2156 nir_print_instr(&instr
->instr
, stderr
);
2157 fprintf(stderr
, "\n");
2162 case nir_op_f2f16_rtne
: {
2163 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2164 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2165 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2166 src
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2167 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2170 case nir_op_f2f16_rtz
: {
2171 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2172 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2173 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2174 src
= bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, bld
.def(v1
), src
, Operand(0u));
2175 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2178 case nir_op_f2f32
: {
2179 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2180 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2181 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2182 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2184 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2185 nir_print_instr(&instr
->instr
, stderr
);
2186 fprintf(stderr
, "\n");
2190 case nir_op_f2f64
: {
2191 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2192 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2193 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2194 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2197 case nir_op_i2f16
: {
2198 assert(dst
.regClass() == v2b
);
2199 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f16_i16
, bld
.def(v1
),
2200 get_alu_src(ctx
, instr
->src
[0]));
2201 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2204 case nir_op_i2f32
: {
2205 assert(dst
.size() == 1);
2206 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_i32
, dst
);
2209 case nir_op_i2f64
: {
2210 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2211 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_i32
, dst
);
2212 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2213 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2214 RegClass rc
= RegClass(src
.type(), 1);
2215 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2216 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2217 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2218 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2219 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2220 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2223 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2224 nir_print_instr(&instr
->instr
, stderr
);
2225 fprintf(stderr
, "\n");
2229 case nir_op_u2f16
: {
2230 assert(dst
.regClass() == v2b
);
2231 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f16_u16
, bld
.def(v1
),
2232 get_alu_src(ctx
, instr
->src
[0]));
2233 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2236 case nir_op_u2f32
: {
2237 assert(dst
.size() == 1);
2238 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_u32
, dst
);
2241 case nir_op_u2f64
: {
2242 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2243 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_u32
, dst
);
2244 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2245 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2246 RegClass rc
= RegClass(src
.type(), 1);
2247 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2248 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2249 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2250 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2251 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2252 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2254 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2255 nir_print_instr(&instr
->instr
, stderr
);
2256 fprintf(stderr
, "\n");
2260 case nir_op_f2i16
: {
2261 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2262 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2263 src
= bld
.vop1(aco_opcode::v_cvt_i16_f16
, bld
.def(v1
), src
);
2264 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2265 src
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
);
2267 src
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
);
2269 if (dst
.type() == RegType::vgpr
)
2270 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2272 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2275 case nir_op_f2u16
: {
2276 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2277 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2278 src
= bld
.vop1(aco_opcode::v_cvt_u16_f16
, bld
.def(v1
), src
);
2279 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2280 src
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
);
2282 src
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
);
2284 if (dst
.type() == RegType::vgpr
)
2285 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2287 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2290 case nir_op_f2i32
: {
2291 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2292 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2293 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2294 if (dst
.type() == RegType::vgpr
) {
2295 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2297 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2298 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2300 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2301 if (dst
.type() == RegType::vgpr
)
2302 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), src
);
2304 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2305 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
));
2307 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2308 if (dst
.type() == RegType::vgpr
)
2309 bld
.vop1(aco_opcode::v_cvt_i32_f64
, Definition(dst
), src
);
2311 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2312 bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
));
2315 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2316 nir_print_instr(&instr
->instr
, stderr
);
2317 fprintf(stderr
, "\n");
2321 case nir_op_f2u32
: {
2322 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2323 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2324 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2325 if (dst
.type() == RegType::vgpr
) {
2326 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2328 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2329 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2331 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2332 if (dst
.type() == RegType::vgpr
)
2333 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), src
);
2335 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2336 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
));
2338 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2339 if (dst
.type() == RegType::vgpr
)
2340 bld
.vop1(aco_opcode::v_cvt_u32_f64
, Definition(dst
), src
);
2342 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2343 bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
));
2346 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2347 nir_print_instr(&instr
->instr
, stderr
);
2348 fprintf(stderr
, "\n");
2352 case nir_op_f2i64
: {
2353 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2354 if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::vgpr
) {
2355 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2356 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2357 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2358 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2359 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2360 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2361 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2362 Temp new_exponent
= bld
.tmp(v1
);
2363 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2364 if (ctx
->program
->chip_class
>= GFX8
)
2365 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2367 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2368 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2369 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2370 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2371 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2372 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2373 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2374 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2375 Temp new_lower
= bld
.tmp(v1
);
2376 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2377 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2378 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2380 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::sgpr
) {
2381 if (src
.type() == RegType::vgpr
)
2382 src
= bld
.as_uniform(src
);
2383 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2384 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2385 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2386 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2387 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2388 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2389 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2390 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2391 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2392 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2393 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2394 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2395 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2396 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2397 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2398 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2399 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2400 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2401 Temp borrow
= bld
.tmp(s1
);
2402 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2403 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2404 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2406 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2407 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2408 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2409 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2410 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2411 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2412 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2413 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2414 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2415 if (dst
.type() == RegType::sgpr
) {
2416 lower
= bld
.as_uniform(lower
);
2417 upper
= bld
.as_uniform(upper
);
2419 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2422 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2423 nir_print_instr(&instr
->instr
, stderr
);
2424 fprintf(stderr
, "\n");
2428 case nir_op_f2u64
: {
2429 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2430 if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::vgpr
) {
2431 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2432 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2433 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2434 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2435 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2436 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2437 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2438 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2439 Temp new_exponent
= bld
.tmp(v1
);
2440 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2441 if (ctx
->program
->chip_class
>= GFX8
)
2442 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2444 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2445 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2446 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2447 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2448 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2449 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2450 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2451 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2453 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::sgpr
) {
2454 if (src
.type() == RegType::vgpr
)
2455 src
= bld
.as_uniform(src
);
2456 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2457 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2458 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2459 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2460 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2461 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2462 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2463 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2464 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2465 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2466 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2467 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2468 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2469 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2470 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2471 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2472 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2473 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2475 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2476 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2477 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2478 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2479 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2480 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2481 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2482 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2483 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2484 if (dst
.type() == RegType::sgpr
) {
2485 lower
= bld
.as_uniform(lower
);
2486 upper
= bld
.as_uniform(upper
);
2488 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2491 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2492 nir_print_instr(&instr
->instr
, stderr
);
2493 fprintf(stderr
, "\n");
2497 case nir_op_b2f16
: {
2498 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2499 assert(src
.regClass() == bld
.lm
);
2501 if (dst
.regClass() == s1
) {
2502 src
= bool_to_scalar_condition(ctx
, src
);
2503 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2504 } else if (dst
.regClass() == v2b
) {
2505 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2506 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2507 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2509 unreachable("Wrong destination register class for nir_op_b2f16.");
2513 case nir_op_b2f32
: {
2514 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2515 assert(src
.regClass() == bld
.lm
);
2517 if (dst
.regClass() == s1
) {
2518 src
= bool_to_scalar_condition(ctx
, src
);
2519 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2520 } else if (dst
.regClass() == v1
) {
2521 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2523 unreachable("Wrong destination register class for nir_op_b2f32.");
2527 case nir_op_b2f64
: {
2528 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2529 assert(src
.regClass() == bld
.lm
);
2531 if (dst
.regClass() == s2
) {
2532 src
= bool_to_scalar_condition(ctx
, src
);
2533 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2534 } else if (dst
.regClass() == v2
) {
2535 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2536 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2537 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2539 unreachable("Wrong destination register class for nir_op_b2f64.");
2545 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2546 /* we can actually just say dst = src */
2547 if (src
.regClass() == s1
)
2548 bld
.copy(Definition(dst
), src
);
2550 emit_extract_vector(ctx
, src
, 0, dst
);
2553 case nir_op_i2i16
: {
2554 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2555 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2556 if (dst
.regClass() == s1
) {
2557 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(dst
), Operand(src
));
2559 assert(src
.regClass() == v1b
);
2560 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2561 sdwa
->operands
[0] = Operand(src
);
2562 sdwa
->definitions
[0] = Definition(dst
);
2563 sdwa
->sel
[0] = sdwa_sbyte
;
2564 sdwa
->dst_sel
= sdwa_sword
;
2565 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2568 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2569 /* we can actually just say dst = src */
2570 if (src
.regClass() == s1
)
2571 bld
.copy(Definition(dst
), src
);
2573 emit_extract_vector(ctx
, src
, 0, dst
);
2577 case nir_op_u2u16
: {
2578 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2579 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2580 if (dst
.regClass() == s1
)
2581 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFu
), src
);
2583 assert(src
.regClass() == v1b
);
2584 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2585 sdwa
->operands
[0] = Operand(src
);
2586 sdwa
->definitions
[0] = Definition(dst
);
2587 sdwa
->sel
[0] = sdwa_ubyte
;
2588 sdwa
->dst_sel
= sdwa_uword
;
2589 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2592 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2593 /* we can actually just say dst = src */
2594 if (src
.regClass() == s1
)
2595 bld
.copy(Definition(dst
), src
);
2597 emit_extract_vector(ctx
, src
, 0, dst
);
2601 case nir_op_i2i32
: {
2602 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2603 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2604 if (dst
.regClass() == s1
) {
2605 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(dst
), Operand(src
));
2607 assert(src
.regClass() == v1b
);
2608 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2609 sdwa
->operands
[0] = Operand(src
);
2610 sdwa
->definitions
[0] = Definition(dst
);
2611 sdwa
->sel
[0] = sdwa_sbyte
;
2612 sdwa
->dst_sel
= sdwa_sdword
;
2613 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2615 } else if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2616 if (dst
.regClass() == s1
) {
2617 bld
.sop1(aco_opcode::s_sext_i32_i16
, Definition(dst
), Operand(src
));
2619 assert(src
.regClass() == v2b
);
2620 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2621 sdwa
->operands
[0] = Operand(src
);
2622 sdwa
->definitions
[0] = Definition(dst
);
2623 sdwa
->sel
[0] = sdwa_sword
;
2624 sdwa
->dst_sel
= sdwa_udword
;
2625 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2627 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2628 /* we can actually just say dst = src, as it would map the lower register */
2629 emit_extract_vector(ctx
, src
, 0, dst
);
2631 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2632 nir_print_instr(&instr
->instr
, stderr
);
2633 fprintf(stderr
, "\n");
2637 case nir_op_u2u32
: {
2638 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2639 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2640 if (dst
.regClass() == s1
)
2641 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFu
), src
);
2643 assert(src
.regClass() == v1b
);
2644 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2645 sdwa
->operands
[0] = Operand(src
);
2646 sdwa
->definitions
[0] = Definition(dst
);
2647 sdwa
->sel
[0] = sdwa_ubyte
;
2648 sdwa
->dst_sel
= sdwa_udword
;
2649 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2651 } else if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2652 if (dst
.regClass() == s1
) {
2653 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFFFu
), src
);
2655 assert(src
.regClass() == v2b
);
2656 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2657 sdwa
->operands
[0] = Operand(src
);
2658 sdwa
->definitions
[0] = Definition(dst
);
2659 sdwa
->sel
[0] = sdwa_uword
;
2660 sdwa
->dst_sel
= sdwa_udword
;
2661 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2663 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2664 /* we can actually just say dst = src, as it would map the lower register */
2665 emit_extract_vector(ctx
, src
, 0, dst
);
2667 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2668 nir_print_instr(&instr
->instr
, stderr
);
2669 fprintf(stderr
, "\n");
2673 case nir_op_i2i64
: {
2674 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2675 if (src
.regClass() == s1
) {
2676 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2677 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, high
);
2678 } else if (src
.regClass() == v1
) {
2679 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2680 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, high
);
2682 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2683 nir_print_instr(&instr
->instr
, stderr
);
2684 fprintf(stderr
, "\n");
2688 case nir_op_u2u64
: {
2689 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2690 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2691 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, Operand(0u));
2693 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2694 nir_print_instr(&instr
->instr
, stderr
);
2695 fprintf(stderr
, "\n");
2700 case nir_op_b2i32
: {
2701 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2702 assert(src
.regClass() == bld
.lm
);
2704 if (dst
.regClass() == s1
) {
2705 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2706 bool_to_scalar_condition(ctx
, src
, dst
);
2707 } else if (dst
.regClass() == v1
) {
2708 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2710 unreachable("Invalid register class for b2i32");
2716 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2717 assert(dst
.regClass() == bld
.lm
);
2719 if (src
.type() == RegType::vgpr
) {
2720 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2721 assert(dst
.regClass() == bld
.lm
);
2722 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2723 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2725 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2727 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2728 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2730 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2731 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2733 bool_to_vector_condition(ctx
, tmp
, dst
);
2737 case nir_op_pack_64_2x32_split
: {
2738 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2739 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2741 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2744 case nir_op_unpack_64_2x32_split_x
:
2745 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2747 case nir_op_unpack_64_2x32_split_y
:
2748 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2750 case nir_op_unpack_32_2x16_split_x
:
2751 if (dst
.type() == RegType::vgpr
) {
2752 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2754 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2757 case nir_op_unpack_32_2x16_split_y
:
2758 if (dst
.type() == RegType::vgpr
) {
2759 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2761 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2764 case nir_op_pack_32_2x16_split
: {
2765 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2766 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2767 if (dst
.regClass() == v1
) {
2768 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2770 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2771 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2772 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2776 case nir_op_pack_half_2x16
: {
2777 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2779 if (dst
.regClass() == v1
) {
2780 Temp src0
= bld
.tmp(v1
);
2781 Temp src1
= bld
.tmp(v1
);
2782 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2783 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2784 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2786 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2787 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2788 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2790 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2791 nir_print_instr(&instr
->instr
, stderr
);
2792 fprintf(stderr
, "\n");
2796 case nir_op_unpack_half_2x16_split_x
: {
2797 if (dst
.regClass() == v1
) {
2798 Builder
bld(ctx
->program
, ctx
->block
);
2799 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2801 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2802 nir_print_instr(&instr
->instr
, stderr
);
2803 fprintf(stderr
, "\n");
2807 case nir_op_unpack_half_2x16_split_y
: {
2808 if (dst
.regClass() == v1
) {
2809 Builder
bld(ctx
->program
, ctx
->block
);
2810 /* TODO: use SDWA here */
2811 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2812 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2814 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2815 nir_print_instr(&instr
->instr
, stderr
);
2816 fprintf(stderr
, "\n");
2820 case nir_op_fquantize2f16
: {
2821 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2822 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2825 if (ctx
->program
->chip_class
>= GFX8
) {
2826 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2827 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2828 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2830 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2831 * so compare the result and flush to 0 if it's smaller.
2833 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2834 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2835 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2836 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2837 cmp_res
= vop3
->definitions
[0].getTemp();
2840 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2841 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2842 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2844 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2849 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2850 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2852 if (dst
.regClass() == s1
) {
2853 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2854 } else if (dst
.regClass() == v1
) {
2855 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2857 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2858 nir_print_instr(&instr
->instr
, stderr
);
2859 fprintf(stderr
, "\n");
2863 case nir_op_bitfield_select
: {
2864 /* (mask & insert) | (~mask & base) */
2865 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2866 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2867 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2869 /* dst = (insert & bitmask) | (base & ~bitmask) */
2870 if (dst
.regClass() == s1
) {
2871 aco_ptr
<Instruction
> sop2
;
2872 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2873 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2875 if (const_insert
&& const_bitmask
) {
2876 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2878 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2879 lhs
= Operand(insert
);
2883 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2884 if (const_base
&& const_bitmask
) {
2885 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2887 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2888 rhs
= Operand(base
);
2891 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2893 } else if (dst
.regClass() == v1
) {
2894 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2895 base
= as_vgpr(ctx
, base
);
2896 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2897 insert
= as_vgpr(ctx
, insert
);
2899 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2902 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2903 nir_print_instr(&instr
->instr
, stderr
);
2904 fprintf(stderr
, "\n");
2910 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2911 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2912 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2914 if (dst
.type() == RegType::sgpr
) {
2916 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2917 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2918 if (const_offset
&& const_bits
) {
2919 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2920 extract
= Operand(const_extract
);
2924 width
= Operand(const_bits
->u32
<< 16);
2926 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2928 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2932 if (dst
.regClass() == s1
) {
2933 if (instr
->op
== nir_op_ubfe
)
2934 opcode
= aco_opcode::s_bfe_u32
;
2936 opcode
= aco_opcode::s_bfe_i32
;
2937 } else if (dst
.regClass() == s2
) {
2938 if (instr
->op
== nir_op_ubfe
)
2939 opcode
= aco_opcode::s_bfe_u64
;
2941 opcode
= aco_opcode::s_bfe_i64
;
2943 unreachable("Unsupported BFE bit size");
2946 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2950 if (dst
.regClass() == v1
) {
2951 if (instr
->op
== nir_op_ubfe
)
2952 opcode
= aco_opcode::v_bfe_u32
;
2954 opcode
= aco_opcode::v_bfe_i32
;
2956 unreachable("Unsupported BFE bit size");
2959 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2963 case nir_op_bit_count
: {
2964 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2965 if (src
.regClass() == s1
) {
2966 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2967 } else if (src
.regClass() == v1
) {
2968 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2969 } else if (src
.regClass() == v2
) {
2970 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2971 emit_extract_vector(ctx
, src
, 1, v1
),
2972 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2973 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2974 } else if (src
.regClass() == s2
) {
2975 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2977 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2978 nir_print_instr(&instr
->instr
, stderr
);
2979 fprintf(stderr
, "\n");
2984 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2988 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2992 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2996 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
3000 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
3004 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
3008 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
3009 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
3011 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
3012 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
3016 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
3017 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
3019 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
3020 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
3024 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
3028 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
3033 case nir_op_fddx_fine
:
3034 case nir_op_fddy_fine
:
3035 case nir_op_fddx_coarse
:
3036 case nir_op_fddy_coarse
: {
3037 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
3038 uint16_t dpp_ctrl1
, dpp_ctrl2
;
3039 if (instr
->op
== nir_op_fddx_fine
) {
3040 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
3041 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
3042 } else if (instr
->op
== nir_op_fddy_fine
) {
3043 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
3044 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
3046 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
3047 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
3048 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
3050 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
3054 if (ctx
->program
->chip_class
>= GFX8
) {
3055 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
3056 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
3058 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
3059 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
3060 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
3062 emit_wqm(ctx
, tmp
, dst
, true);
3066 fprintf(stderr
, "Unknown NIR ALU instr: ");
3067 nir_print_instr(&instr
->instr
, stderr
);
3068 fprintf(stderr
, "\n");
3072 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
3074 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
3076 // TODO: we really want to have the resulting type as this would allow for 64bit literals
3077 // which get truncated the lsb if double and msb if int
3078 // for now, we only use s_mov_b64 with 64bit inline constants
3079 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
3080 assert(dst
.type() == RegType::sgpr
);
3082 Builder
bld(ctx
->program
, ctx
->block
);
3084 if (instr
->def
.bit_size
== 1) {
3085 assert(dst
.regClass() == bld
.lm
);
3086 int val
= instr
->value
[0].b
? -1 : 0;
3087 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
3088 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
3089 } else if (instr
->def
.bit_size
== 8) {
3090 /* ensure that the value is correctly represented in the low byte of the register */
3091 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
3092 } else if (instr
->def
.bit_size
== 16) {
3093 /* ensure that the value is correctly represented in the low half of the register */
3094 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
3095 } else if (dst
.size() == 1) {
3096 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
3098 assert(dst
.size() != 1);
3099 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3100 if (instr
->def
.bit_size
== 64)
3101 for (unsigned i
= 0; i
< dst
.size(); i
++)
3102 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
3104 for (unsigned i
= 0; i
< dst
.size(); i
++)
3105 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3107 vec
->definitions
[0] = Definition(dst
);
3108 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3112 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3114 uint32_t new_mask
= 0;
3115 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3116 if (mask
& (1u << i
))
3117 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3121 Operand
load_lds_size_m0(isel_context
*ctx
)
3123 /* TODO: m0 does not need to be initialized on GFX9+ */
3124 Builder
bld(ctx
->program
, ctx
->block
);
3125 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3128 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3129 Temp address
, unsigned base_offset
, unsigned align
)
3131 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
3133 Builder
bld(ctx
->program
, ctx
->block
);
3135 Operand m
= load_lds_size_m0(ctx
);
3137 unsigned num_components
= dst
.size() * 4u / elem_size_bytes
;
3138 unsigned bytes_read
= 0;
3139 unsigned result_size
= 0;
3140 unsigned total_bytes
= num_components
* elem_size_bytes
;
3141 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> result
;
3142 bool large_ds_read
= ctx
->options
->chip_class
>= GFX7
;
3143 bool usable_read2
= ctx
->options
->chip_class
>= GFX7
;
3145 while (bytes_read
< total_bytes
) {
3146 unsigned todo
= total_bytes
- bytes_read
;
3147 bool aligned8
= bytes_read
% 8 == 0 && align
% 8 == 0;
3148 bool aligned16
= bytes_read
% 16 == 0 && align
% 16 == 0;
3150 aco_opcode op
= aco_opcode::last_opcode
;
3152 if (todo
>= 16 && aligned16
&& large_ds_read
) {
3153 op
= aco_opcode::ds_read_b128
;
3155 } else if (todo
>= 16 && aligned8
&& usable_read2
) {
3156 op
= aco_opcode::ds_read2_b64
;
3159 } else if (todo
>= 12 && aligned16
&& large_ds_read
) {
3160 op
= aco_opcode::ds_read_b96
;
3162 } else if (todo
>= 8 && aligned8
) {
3163 op
= aco_opcode::ds_read_b64
;
3165 } else if (todo
>= 8 && usable_read2
) {
3166 op
= aco_opcode::ds_read2_b32
;
3169 } else if (todo
>= 4) {
3170 op
= aco_opcode::ds_read_b32
;
3175 assert(todo
% elem_size_bytes
== 0);
3176 unsigned num_elements
= todo
/ elem_size_bytes
;
3177 unsigned offset
= base_offset
+ bytes_read
;
3178 unsigned max_offset
= read2
? 1019 : 65535;
3180 Temp address_offset
= address
;
3181 if (offset
> max_offset
) {
3182 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3183 offset
= bytes_read
;
3185 assert(offset
<= max_offset
); /* bytes_read shouldn't be large enough for this to happen */
3188 if (num_components
== 1 && dst
.type() == RegType::vgpr
)
3191 res
= bld
.tmp(RegClass(RegType::vgpr
, todo
/ 4));
3194 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
/ (todo
/ 2), (offset
/ (todo
/ 2)) + 1);
3196 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
);
3198 if (num_components
== 1) {
3199 assert(todo
== total_bytes
);
3200 if (dst
.type() == RegType::sgpr
)
3201 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), res
);
3205 if (dst
.type() == RegType::sgpr
) {
3206 Temp new_res
= bld
.tmp(RegType::sgpr
, res
.size());
3207 expand_vector(ctx
, res
, new_res
, res
.size(), (1 << res
.size()) - 1);
3211 if (num_elements
== 1) {
3212 result
[result_size
++] = res
;
3214 assert(res
!= dst
&& res
.size() % num_elements
== 0);
3215 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_elements
)};
3216 split
->operands
[0] = Operand(res
);
3217 for (unsigned i
= 0; i
< num_elements
; i
++)
3218 split
->definitions
[i
] = Definition(result
[result_size
++] = bld
.tmp(res
.type(), elem_size_bytes
/ 4));
3219 ctx
->block
->instructions
.emplace_back(std::move(split
));
3225 assert(result_size
== num_components
&& result_size
> 1);
3226 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, result_size
, 1)};
3227 for (unsigned i
= 0; i
< result_size
; i
++)
3228 vec
->operands
[i
] = Operand(result
[i
]);
3229 vec
->definitions
[0] = Definition(dst
);
3230 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3231 ctx
->allocated_vec
.emplace(dst
.id(), result
);
3236 Temp
extract_subvector(isel_context
*ctx
, Temp data
, unsigned start
, unsigned size
, RegType type
)
3238 if (start
== 0 && size
== data
.size())
3239 return type
== RegType::vgpr
? as_vgpr(ctx
, data
) : data
;
3241 unsigned size_hint
= 1;
3242 auto it
= ctx
->allocated_vec
.find(data
.id());
3243 if (it
!= ctx
->allocated_vec
.end())
3244 size_hint
= it
->second
[0].size();
3245 if (size
% size_hint
|| start
% size_hint
)
3252 for (unsigned i
= 0; i
< size
; i
++)
3253 elems
[i
] = emit_extract_vector(ctx
, data
, start
+ i
, RegClass(type
, size_hint
));
3256 return type
== RegType::vgpr
? as_vgpr(ctx
, elems
[0]) : elems
[0];
3258 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
3259 for (unsigned i
= 0; i
< size
; i
++)
3260 vec
->operands
[i
] = Operand(elems
[i
]);
3261 Temp res
= {ctx
->program
->allocateId(), RegClass(type
, size
* size_hint
)};
3262 vec
->definitions
[0] = Definition(res
);
3263 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3267 void ds_write_helper(isel_context
*ctx
, Operand m
, Temp address
, Temp data
, unsigned data_start
, unsigned total_size
, unsigned offset0
, unsigned offset1
, unsigned align
)
3269 Builder
bld(ctx
->program
, ctx
->block
);
3270 unsigned bytes_written
= 0;
3271 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3272 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3274 while (bytes_written
< total_size
* 4) {
3275 unsigned todo
= total_size
* 4 - bytes_written
;
3276 bool aligned8
= bytes_written
% 8 == 0 && align
% 8 == 0;
3277 bool aligned16
= bytes_written
% 16 == 0 && align
% 16 == 0;
3279 aco_opcode op
= aco_opcode::last_opcode
;
3280 bool write2
= false;
3282 if (todo
>= 16 && aligned16
&& large_ds_write
) {
3283 op
= aco_opcode::ds_write_b128
;
3285 } else if (todo
>= 16 && aligned8
&& usable_write2
) {
3286 op
= aco_opcode::ds_write2_b64
;
3289 } else if (todo
>= 12 && aligned16
&& large_ds_write
) {
3290 op
= aco_opcode::ds_write_b96
;
3292 } else if (todo
>= 8 && aligned8
) {
3293 op
= aco_opcode::ds_write_b64
;
3295 } else if (todo
>= 8 && usable_write2
) {
3296 op
= aco_opcode::ds_write2_b32
;
3299 } else if (todo
>= 4) {
3300 op
= aco_opcode::ds_write_b32
;
3306 unsigned offset
= offset0
+ offset1
+ bytes_written
;
3307 unsigned max_offset
= write2
? 1020 : 65535;
3308 Temp address_offset
= address
;
3309 if (offset
> max_offset
) {
3310 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(offset0
), address_offset
);
3311 offset
= offset1
+ bytes_written
;
3313 assert(offset
<= max_offset
); /* offset1 shouldn't be large enough for this to happen */
3316 Temp val0
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
/ 2, RegType::vgpr
);
3317 Temp val1
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2) + 1, size
/ 2, RegType::vgpr
);
3318 bld
.ds(op
, address_offset
, val0
, val1
, m
, offset
/ size
/ 2, (offset
/ size
/ 2) + 1);
3320 Temp val
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
, RegType::vgpr
);
3321 bld
.ds(op
, address_offset
, val
, m
, offset
);
3324 bytes_written
+= size
* 4;
3328 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3329 Temp address
, unsigned base_offset
, unsigned align
)
3331 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
3332 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3334 Operand m
= load_lds_size_m0(ctx
);
3336 /* we need at most two stores, assuming that the writemask is at most 4 bits wide */
3337 assert(wrmask
<= 0x0f);
3338 int start
[2], count
[2];
3339 u_bit_scan_consecutive_range(&wrmask
, &start
[0], &count
[0]);
3340 u_bit_scan_consecutive_range(&wrmask
, &start
[1], &count
[1]);
3341 assert(wrmask
== 0);
3343 /* one combined store is sufficient */
3344 if (count
[0] == count
[1] && (align
% elem_size_bytes
) == 0 && (base_offset
% elem_size_bytes
) == 0) {
3345 Builder
bld(ctx
->program
, ctx
->block
);
3347 Temp address_offset
= address
;
3348 if ((base_offset
/ elem_size_bytes
) + start
[1] > 255) {
3349 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3353 assert(count
[0] == 1);
3354 RegClass
xtract_rc(RegType::vgpr
, elem_size_bytes
/ 4);
3356 Temp val0
= emit_extract_vector(ctx
, data
, start
[0], xtract_rc
);
3357 Temp val1
= emit_extract_vector(ctx
, data
, start
[1], xtract_rc
);
3358 aco_opcode op
= elem_size_bytes
== 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3359 base_offset
= base_offset
/ elem_size_bytes
;
3360 bld
.ds(op
, address_offset
, val0
, val1
, m
,
3361 base_offset
+ start
[0], base_offset
+ start
[1]);
3365 for (unsigned i
= 0; i
< 2; i
++) {
3369 unsigned elem_size_words
= elem_size_bytes
/ 4;
3370 ds_write_helper(ctx
, m
, address
, data
, start
[i
] * elem_size_words
, count
[i
] * elem_size_words
,
3371 base_offset
, start
[i
] * elem_size_bytes
, align
);
3376 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3378 unsigned align
= 16;
3380 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3386 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3387 unsigned split_cnt
= 0u, Temp dst
= Temp())
3389 Builder
bld(ctx
->program
, ctx
->block
);
3390 unsigned dword_size
= elem_size_bytes
/ 4;
3393 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3395 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3396 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3397 instr
->definitions
[0] = Definition(dst
);
3399 for (unsigned i
= 0; i
< cnt
; ++i
) {
3401 assert(arr
[i
].size() == dword_size
);
3402 allocated_vec
[i
] = arr
[i
];
3403 instr
->operands
[i
] = Operand(arr
[i
]);
3405 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3406 allocated_vec
[i
] = zero
;
3407 instr
->operands
[i
] = Operand(zero
);
3411 bld
.insert(std::move(instr
));
3414 emit_split_vector(ctx
, dst
, split_cnt
);
3416 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3421 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3423 if (const_offset
>= 4096) {
3424 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3425 const_offset
%= 4096u;
3428 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3429 else if (unlikely(voffset
.regClass() == s1
))
3430 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3431 else if (likely(voffset
.regClass() == v1
))
3432 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3434 unreachable("Unsupported register class of voffset");
3437 return const_offset
;
3440 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3441 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3444 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3445 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3447 Builder
bld(ctx
->program
, ctx
->block
);
3448 aco_opcode op
= (aco_opcode
) ((unsigned) aco_opcode::buffer_store_dword
+ vdata
.size() - 1);
3449 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3451 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3452 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3453 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3454 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3455 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3457 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3460 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3461 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3462 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3464 Builder
bld(ctx
->program
, ctx
->block
);
3465 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3468 if (elem_size_bytes
== 8) {
3469 elem_size_bytes
= 4;
3470 write_mask
= widen_mask(write_mask
, 2);
3473 while (write_mask
) {
3476 u_bit_scan_consecutive_range(&write_mask
, &start
, &count
);
3481 unsigned sub_count
= allow_combining
? MIN2(count
, 4) : 1;
3482 unsigned const_offset
= (unsigned) start
* elem_size_bytes
+ base_const_offset
;
3484 /* GFX6 doesn't have buffer_store_dwordx3, so make sure not to emit that here either. */
3485 if (unlikely(ctx
->program
->chip_class
== GFX6
&& sub_count
== 3))
3488 Temp elem
= extract_subvector(ctx
, src
, start
, sub_count
, RegType::vgpr
);
3489 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, elem
, const_offset
, reorder
, slc
);
3499 Temp
emit_single_mubuf_load(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
,
3500 unsigned const_offset
, unsigned size_dwords
, bool allow_reorder
= true)
3502 assert(size_dwords
!= 3 || ctx
->program
->chip_class
!= GFX6
);
3503 assert(size_dwords
>= 1 && size_dwords
<= 4);
3505 Builder
bld(ctx
->program
, ctx
->block
);
3506 Temp vdata
= bld
.tmp(RegClass(RegType::vgpr
, size_dwords
));
3507 aco_opcode op
= (aco_opcode
) ((unsigned) aco_opcode::buffer_load_dword
+ size_dwords
- 1);
3508 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3510 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3511 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3512 Builder::Result r
= bld
.mubuf(op
, Definition(vdata
), Operand(descriptor
), voffset_op
, soffset_op
, const_offset
,
3513 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3514 /* disable_wqm */ false, /* glc */ true,
3515 /* dlc*/ ctx
->program
->chip_class
>= GFX10
, /* slc */ false);
3517 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3522 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3523 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3524 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3526 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3527 assert((num_components
* elem_size_bytes
/ 4) == dst
.size());
3528 assert(!!stride
!= allow_combining
);
3530 Builder
bld(ctx
->program
, ctx
->block
);
3531 unsigned split_cnt
= num_components
;
3533 if (elem_size_bytes
== 8) {
3534 elem_size_bytes
= 4;
3535 num_components
*= 2;
3539 stride
= elem_size_bytes
;
3541 unsigned load_size
= 1;
3542 if (allow_combining
) {
3543 if ((num_components
% 4) == 0)
3545 else if ((num_components
% 3) == 0 && ctx
->program
->chip_class
!= GFX6
)
3547 else if ((num_components
% 2) == 0)
3551 unsigned num_loads
= num_components
/ load_size
;
3552 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
3554 for (unsigned i
= 0; i
< num_loads
; ++i
) {
3555 unsigned const_offset
= i
* stride
* load_size
+ base_const_offset
;
3556 elems
[i
] = emit_single_mubuf_load(ctx
, descriptor
, voffset
, soffset
, const_offset
, load_size
, allow_reorder
);
3559 create_vec_from_array(ctx
, elems
.data(), num_loads
, RegType::vgpr
, load_size
* 4u, split_cnt
, dst
);
3562 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
3564 Builder
bld(ctx
->program
, ctx
->block
);
3565 Temp offset
= base_offset
.first
;
3566 unsigned const_offset
= base_offset
.second
;
3568 if (!nir_src_is_const(*off_src
)) {
3569 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
3572 /* Calculate indirect offset with stride */
3573 if (likely(indirect_offset_arg
.regClass() == v1
))
3574 with_stride
= bld
.v_mul_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
3575 else if (indirect_offset_arg
.regClass() == s1
)
3576 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
3578 unreachable("Unsupported register class of indirect offset");
3580 /* Add to the supplied base offset */
3581 if (offset
.id() == 0)
3582 offset
= with_stride
;
3583 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
3584 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
3585 else if (offset
.size() == 1 && with_stride
.size() == 1)
3586 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
3588 unreachable("Unsupported register class of indirect offset");
3590 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
3591 const_offset
+= const_offset_arg
* stride
;
3594 return std::make_pair(offset
, const_offset
);
3597 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
3599 Builder
bld(ctx
->program
, ctx
->block
);
3602 if (off1
.first
.id() && off2
.first
.id()) {
3603 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
3604 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
3605 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
3606 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
3608 unreachable("Unsupported register class of indirect offset");
3610 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
3613 return std::make_pair(offset
, off1
.second
+ off2
.second
);
3616 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
3618 Builder
bld(ctx
->program
, ctx
->block
);
3619 unsigned const_offset
= offs
.second
* multiplier
;
3621 if (!offs
.first
.id())
3622 return std::make_pair(offs
.first
, const_offset
);
3624 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
3625 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
3626 : bld
.v_mul_imm(bld
.def(v1
), offs
.first
, multiplier
);
3628 return std::make_pair(offset
, const_offset
);
3631 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
3633 Builder
bld(ctx
->program
, ctx
->block
);
3635 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
3636 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
3637 /* component is in bytes */
3638 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
3640 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
3641 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3642 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
3645 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
3647 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
3650 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
3652 Builder
bld(ctx
->program
, ctx
->block
);
3654 switch (ctx
->shader
->info
.stage
) {
3655 case MESA_SHADER_TESS_CTRL
:
3656 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
3657 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
3658 case MESA_SHADER_TESS_EVAL
:
3659 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
3661 unreachable("Unsupported stage in get_tess_rel_patch_id");
3665 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3667 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3668 Builder
bld(ctx
->program
, ctx
->block
);
3670 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
3671 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
3673 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
3675 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3676 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
3678 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3679 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
3680 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
3682 return offset_mul(ctx
, offs
, 4u);
3685 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
3687 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3688 Builder
bld(ctx
->program
, ctx
->block
);
3690 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
3691 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
3692 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
3693 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
3694 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
3695 uint32_t output_patch_stride
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
3697 std::pair
<Temp
, unsigned> offs
= instr
3698 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
3699 : std::make_pair(Temp(), 0u);
3701 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3702 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
3707 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3708 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
3710 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
3711 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
3713 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
3714 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
3720 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3722 Builder
bld(ctx
->program
, ctx
->block
);
3724 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
3725 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
3727 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
3729 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3730 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
3731 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
3733 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3734 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
3739 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
3741 Builder
bld(ctx
->program
, ctx
->block
);
3743 unsigned num_tcs_outputs
= ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
3744 ? util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
)
3745 : ctx
->args
->options
->key
.tes
.tcs_num_outputs
;
3747 unsigned output_vertex_size
= num_tcs_outputs
* 16;
3748 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
3749 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
3750 unsigned attr_stride
= ctx
->tcs_num_patches
;
3752 std::pair
<Temp
, unsigned> offs
= instr
3753 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
3754 : std::make_pair(Temp(), 0u);
3756 if (const_base_offset
)
3757 offs
.second
+= const_base_offset
* attr_stride
;
3759 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3760 Temp patch_off
= bld
.v_mul_imm(bld
.def(v1
), rel_patch_id
, 16u);
3761 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
3766 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
3768 unsigned off
= nir_intrinsic_base(instr
) * 4u;
3769 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3771 if (!nir_src_is_const(*off_src
)) {
3777 off
+= nir_src_as_uint(*off_src
) * 16u;
3780 unsigned slot
= u_bit_scan64(&mask
) + (per_vertex
? 0 : VARYING_SLOT_PATCH0
);
3781 if (off
== shader_io_get_unique_index((gl_varying_slot
) slot
) * 16u)
3788 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3790 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3791 unsigned component
= nir_intrinsic_component(instr
);
3792 unsigned idx
= nir_intrinsic_base(instr
) + component
;
3794 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
3795 if (off_instr
->type
!= nir_instr_type_load_const
)
3798 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3799 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
3801 if (instr
->src
[0].ssa
->bit_size
== 64)
3802 write_mask
= widen_mask(write_mask
, 2);
3804 for (unsigned i
= 0; i
< 8; ++i
) {
3805 if (write_mask
& (1 << i
)) {
3806 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
3807 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, v1
);
3815 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
3817 /* Only TCS per-vertex inputs are supported by this function.
3818 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
3820 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
3823 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3824 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3825 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
3826 bool can_use_temps
= nir_src_is_const(*off_src
) &&
3827 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
3828 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
3833 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
3834 Temp
*src
= &ctx
->inputs
.temps
[idx
];
3835 Temp vec
= create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u);
3836 assert(vec
.size() == dst
.size());
3838 Builder
bld(ctx
->program
, ctx
->block
);
3839 bld
.copy(Definition(dst
), vec
);
3843 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3845 Builder
bld(ctx
->program
, ctx
->block
);
3847 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
3848 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3849 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3850 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
3852 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
3853 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
3854 bool indirect_write
;
3855 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
3856 if (temp_only_input
&& !indirect_write
)
3860 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
3861 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
3862 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
3863 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
3864 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
3868 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
3869 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
3870 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
3871 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
3872 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
3873 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
3874 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
3875 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
3876 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
3877 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
3878 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
3879 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
3880 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
3882 unsigned num_tcs_inputs
= util_last_bit64(ctx
->args
->shader_info
->vs
.ls_outputs_written
);
3883 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
3884 lds_base
= bld
.v_mul_imm(bld
.def(v1
), vertex_idx
, num_tcs_inputs
* 16u);
3886 unreachable("Invalid LS or ES stage");
3889 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
3890 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
3891 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
3895 bool should_write_tcs_patch_output_to_vmem(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3897 unsigned off
= nir_intrinsic_base(instr
) * 4u;
3898 return off
!= ctx
->tcs_tess_lvl_out_loc
&&
3899 off
!= ctx
->tcs_tess_lvl_in_loc
;
3902 bool should_write_tcs_output_to_lds(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3904 /* When none of the appropriate outputs are read, we are OK to never write to LDS */
3905 if (per_vertex
? ctx
->shader
->info
.outputs_read
== 0U : ctx
->shader
->info
.patch_outputs_read
== 0u)
3908 uint64_t mask
= per_vertex
3909 ? ctx
->shader
->info
.outputs_read
3910 : ctx
->shader
->info
.patch_outputs_read
;
3911 bool indirect_write
;
3912 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
3913 return indirect_write
|| output_read
;
3916 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3918 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
3919 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3921 Builder
bld(ctx
->program
, ctx
->block
);
3923 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3924 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
3925 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3927 /* Only write to VMEM if the output is per-vertex or it's per-patch non tess factor */
3928 bool write_to_vmem
= per_vertex
|| should_write_tcs_patch_output_to_vmem(ctx
, instr
);
3929 /* Only write to LDS if the output is read by the shader, or it's per-patch tess factor */
3930 bool write_to_lds
= !write_to_vmem
|| should_write_tcs_output_to_lds(ctx
, instr
, per_vertex
);
3932 if (write_to_vmem
) {
3933 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
3934 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
3935 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
3937 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
3938 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
3939 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
3943 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
3944 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
3945 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
3949 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3951 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
3952 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3954 Builder
bld(ctx
->program
, ctx
->block
);
3956 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3957 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
3958 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
3959 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
3961 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
3964 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3966 if (ctx
->stage
== vertex_vs
||
3967 ctx
->stage
== tess_eval_vs
||
3968 ctx
->stage
== fragment_fs
||
3969 ctx
->stage
== ngg_vertex_gs
||
3970 ctx
->stage
== ngg_tess_eval_gs
||
3971 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
3972 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
3973 if (!stored_to_temps
) {
3974 fprintf(stderr
, "Unimplemented output offset instruction:\n");
3975 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
3976 fprintf(stderr
, "\n");
3979 } else if (ctx
->stage
== vertex_es
||
3980 ctx
->stage
== vertex_ls
||
3981 ctx
->stage
== tess_eval_es
||
3982 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
3983 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
3984 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
3985 visit_store_ls_or_es_output(ctx
, instr
);
3986 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
3987 visit_store_tcs_output(ctx
, instr
, false);
3989 unreachable("Shader stage not implemented");
3993 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3995 visit_load_tcs_output(ctx
, instr
, false);
3998 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4000 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4001 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4003 Builder
bld(ctx
->program
, ctx
->block
);
4004 Builder::Result interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
, bld
.m0(prim_mask
), idx
, component
);
4005 if (ctx
->program
->has_16bank_lds
)
4006 interp_p1
.instr
->operands
[0].setLateKill(true);
4007 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4010 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4012 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4013 for (unsigned i
= 0; i
< num_components
; i
++)
4014 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4015 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4016 assert(num_components
== 4);
4017 Builder
bld(ctx
->program
, ctx
->block
);
4018 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4021 for (Operand
& op
: vec
->operands
)
4022 op
= op
.isUndefined() ? Operand(0u) : op
;
4024 vec
->definitions
[0] = Definition(dst
);
4025 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4026 emit_split_vector(ctx
, dst
, num_components
);
4030 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4032 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4033 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4034 unsigned idx
= nir_intrinsic_base(instr
);
4035 unsigned component
= nir_intrinsic_component(instr
);
4036 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4038 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4040 assert(offset
->u32
== 0);
4042 /* the lower 15bit of the prim_mask contain the offset into LDS
4043 * while the upper bits contain the number of prims */
4044 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4045 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4046 Builder
bld(ctx
->program
, ctx
->block
);
4047 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4048 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4049 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4050 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4051 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4054 if (instr
->dest
.ssa
.num_components
== 1) {
4055 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4057 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4058 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4060 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4061 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4062 vec
->operands
[i
] = Operand(tmp
);
4064 vec
->definitions
[0] = Definition(dst
);
4065 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4069 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4070 unsigned offset
, unsigned stride
, unsigned channels
)
4072 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4073 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4075 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4076 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4079 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4080 unsigned offset
, unsigned stride
, unsigned *channels
)
4082 if (!vtx_info
->chan_byte_size
) {
4083 *channels
= vtx_info
->num_channels
;
4084 return vtx_info
->chan_format
;
4087 unsigned num_channels
= *channels
;
4088 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4089 unsigned new_channels
= num_channels
+ 1;
4090 /* first, assume more loads is worse and try using a larger data format */
4091 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4093 /* don't make the attribute potentially out-of-bounds */
4094 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4098 if (new_channels
== 5) {
4099 /* then try decreasing load size (at the cost of more loads) */
4100 new_channels
= *channels
;
4101 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4105 if (new_channels
< *channels
)
4106 *channels
= new_channels
;
4107 num_channels
= new_channels
;
4110 switch (vtx_info
->chan_format
) {
4111 case V_008F0C_BUF_DATA_FORMAT_8
:
4112 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4113 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4114 case V_008F0C_BUF_DATA_FORMAT_16
:
4115 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4116 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4117 case V_008F0C_BUF_DATA_FORMAT_32
:
4118 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4119 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4121 unreachable("shouldn't reach here");
4122 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4125 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4126 * so we may need to fix it up. */
4127 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4129 Builder
bld(ctx
->program
, ctx
->block
);
4131 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4132 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4134 /* For the integer-like cases, do a natural sign extension.
4136 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4137 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4140 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4141 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4143 /* Convert back to the right type. */
4144 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4145 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4146 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4147 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4148 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4149 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4155 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4157 Builder
bld(ctx
->program
, ctx
->block
);
4158 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4159 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4161 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4162 if (off_instr
->type
!= nir_instr_type_load_const
) {
4163 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4164 nir_print_instr(off_instr
, stderr
);
4165 fprintf(stderr
, "\n");
4167 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4169 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4171 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4172 unsigned component
= nir_intrinsic_component(instr
);
4173 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4174 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4175 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4176 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4178 unsigned dfmt
= attrib_format
& 0xf;
4179 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4180 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4182 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4183 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4184 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4185 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4187 num_channels
= MAX2(num_channels
, 3);
4189 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4190 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4193 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4194 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4195 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4197 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4199 Temp divided
= bld
.tmp(v1
);
4200 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4201 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4203 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4206 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4209 index
= bld
.vadd32(bld
.def(v1
),
4210 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4211 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4214 Temp channels
[num_channels
];
4215 unsigned channel_start
= 0;
4216 bool direct_fetch
= false;
4218 /* skip unused channels at the start */
4219 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4220 channel_start
= ffs(mask
) - 1;
4221 for (unsigned i
= 0; i
< channel_start
; i
++)
4222 channels
[i
] = Temp(0, s1
);
4223 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4224 num_channels
= 3 - (ffs(mask
) - 1);
4228 while (channel_start
< num_channels
) {
4229 unsigned fetch_size
= num_channels
- channel_start
;
4230 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4231 bool expanded
= false;
4233 /* use MUBUF when possible to avoid possible alignment issues */
4234 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4235 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4236 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4237 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4238 vtx_info
->chan_byte_size
== 4;
4239 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4241 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_size
);
4243 if (fetch_size
== 3 && ctx
->options
->chip_class
== GFX6
) {
4244 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4250 Temp fetch_index
= index
;
4251 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4252 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4253 fetch_offset
= fetch_offset
% attrib_stride
;
4256 Operand
soffset(0u);
4257 if (fetch_offset
>= 4096) {
4258 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4259 fetch_offset
%= 4096;
4263 switch (fetch_size
) {
4265 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4268 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4271 assert(ctx
->options
->chip_class
>= GFX7
||
4272 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4273 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4276 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4279 unreachable("Unimplemented load_input vector size");
4283 if (channel_start
== 0 && fetch_size
== dst
.size() && !post_shuffle
&&
4284 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4285 num_channels
<= 3)) {
4286 direct_fetch
= true;
4289 fetch_dst
= bld
.tmp(RegType::vgpr
, fetch_size
);
4293 Instruction
*mubuf
= bld
.mubuf(opcode
,
4294 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4295 fetch_offset
, false, true).instr
;
4296 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4298 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4299 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4300 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4301 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4304 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4306 if (fetch_size
== 1) {
4307 channels
[channel_start
] = fetch_dst
;
4309 for (unsigned i
= 0; i
< MIN2(fetch_size
, num_channels
- channel_start
); i
++)
4310 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
, v1
);
4313 channel_start
+= fetch_size
;
4316 if (!direct_fetch
) {
4317 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4318 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4320 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4321 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4322 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4324 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4325 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4326 unsigned num_temp
= 0;
4327 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4328 unsigned idx
= i
+ component
;
4329 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4330 Temp channel
= channels
[swizzle
[idx
]];
4331 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4332 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4333 vec
->operands
[i
] = Operand(channel
);
4337 } else if (is_float
&& idx
== 3) {
4338 vec
->operands
[i
] = Operand(0x3f800000u
);
4339 } else if (!is_float
&& idx
== 3) {
4340 vec
->operands
[i
] = Operand(1u);
4342 vec
->operands
[i
] = Operand(0u);
4345 vec
->definitions
[0] = Definition(dst
);
4346 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4347 emit_split_vector(ctx
, dst
, dst
.size());
4349 if (num_temp
== dst
.size())
4350 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4352 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4353 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4354 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4355 if (off_instr
->type
!= nir_instr_type_load_const
||
4356 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4357 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4358 nir_print_instr(off_instr
, stderr
);
4359 fprintf(stderr
, "\n");
4362 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4363 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4365 assert(offset
->u32
== 0);
4367 /* the lower 15bit of the prim_mask contain the offset into LDS
4368 * while the upper bits contain the number of prims */
4369 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4370 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4371 Builder
bld(ctx
->program
, ctx
->block
);
4372 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4373 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4374 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4375 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4376 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4379 unsigned idx
= nir_intrinsic_base(instr
);
4380 unsigned component
= nir_intrinsic_component(instr
);
4381 unsigned vertex_id
= 2; /* P0 */
4383 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4384 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4385 switch (src0
->u32
) {
4387 vertex_id
= 2; /* P0 */
4390 vertex_id
= 0; /* P10 */
4393 vertex_id
= 1; /* P20 */
4396 unreachable("invalid vertex index");
4400 if (dst
.size() == 1) {
4401 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4403 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4404 for (unsigned i
= 0; i
< dst
.size(); i
++)
4405 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4406 vec
->definitions
[0] = Definition(dst
);
4407 bld
.insert(std::move(vec
));
4410 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4411 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4412 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4413 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4414 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4416 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4418 unreachable("Shader stage not implemented");
4422 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4424 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4426 Builder
bld(ctx
->program
, ctx
->block
);
4427 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4430 if (!nir_src_is_const(*vertex_src
)) {
4431 /* better code could be created, but this case probably doesn't happen
4432 * much in practice */
4433 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4434 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4437 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4438 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4440 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4442 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4445 if (vertex_offset
.id()) {
4446 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4447 Operand(i
), indirect_vertex
);
4448 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4450 vertex_offset
= elem
;
4454 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4455 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4457 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4458 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4459 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4460 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4461 Operand((vertex
% 2u) * 16u), Operand(16u));
4463 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4466 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4467 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4468 return offset_mul(ctx
, offs
, 4u);
4471 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4473 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4475 Builder
bld(ctx
->program
, ctx
->block
);
4476 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4477 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4479 if (ctx
->stage
== geometry_gs
) {
4480 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4481 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4482 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4483 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4484 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4485 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4486 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4488 unreachable("Unsupported GS stage.");
4492 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4494 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4496 Builder
bld(ctx
->program
, ctx
->block
);
4497 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4499 if (load_input_from_temps(ctx
, instr
, dst
))
4502 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4503 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4504 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4506 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4509 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4511 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4513 Builder
bld(ctx
->program
, ctx
->block
);
4515 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4516 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4517 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4519 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4520 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
4522 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
4525 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4527 switch (ctx
->shader
->info
.stage
) {
4528 case MESA_SHADER_GEOMETRY
:
4529 visit_load_gs_per_vertex_input(ctx
, instr
);
4531 case MESA_SHADER_TESS_CTRL
:
4532 visit_load_tcs_per_vertex_input(ctx
, instr
);
4534 case MESA_SHADER_TESS_EVAL
:
4535 visit_load_tes_per_vertex_input(ctx
, instr
);
4538 unreachable("Unimplemented shader stage");
4542 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4544 visit_load_tcs_output(ctx
, instr
, true);
4547 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4549 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4550 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4552 visit_store_tcs_output(ctx
, instr
, true);
4555 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4557 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4559 Builder
bld(ctx
->program
, ctx
->block
);
4560 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4562 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
4563 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
4566 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
4567 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
4568 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
4569 tes_w
= Operand(tmp
);
4572 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
4573 emit_split_vector(ctx
, tess_coord
, 3);
4576 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
4578 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
4579 Builder
bld(ctx
->program
, ctx
->block
);
4580 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
4581 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
4582 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
4585 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
4589 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4591 Builder
bld(ctx
->program
, ctx
->block
);
4592 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4593 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
])
4594 index
= bld
.as_uniform(index
);
4595 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
4596 unsigned binding
= nir_intrinsic_binding(instr
);
4599 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
4600 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
4601 unsigned offset
= layout
->binding
[binding
].offset
;
4603 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
4604 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
4605 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
4606 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
4607 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
4610 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
4611 stride
= layout
->binding
[binding
].size
;
4614 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
4615 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
4617 if (nir_const_index
) {
4618 const_index
= const_index
* stride
;
4619 } else if (index
.type() == RegType::vgpr
) {
4620 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
4621 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
4623 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
4627 if (nir_const_index
) {
4628 const_index
= const_index
+ offset
;
4629 } else if (index
.type() == RegType::vgpr
) {
4630 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
4632 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
4636 if (nir_const_index
&& const_index
== 0) {
4638 } else if (index
.type() == RegType::vgpr
) {
4639 index
= bld
.vadd32(bld
.def(v1
),
4640 nir_const_index
? Operand(const_index
) : Operand(index
),
4643 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
4644 nir_const_index
? Operand(const_index
) : Operand(index
),
4648 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
4651 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
4652 Temp dst
, Temp rsrc
, Temp offset
, int byte_align
,
4653 bool glc
=false, bool readonly
=true)
4655 Builder
bld(ctx
->program
, ctx
->block
);
4656 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
4657 unsigned num_bytes
= num_components
* component_size
;
4660 if (dst
.type() == RegType::vgpr
|| ((ctx
->options
->chip_class
< GFX8
|| component_size
< 4) && !readonly
)) {
4661 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
4662 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
4663 unsigned const_offset
= 0;
4665 /* for small bit sizes add buffer for unaligned loads */
4668 num_bytes
+= byte_align
== -1 ? 4 - component_size
: byte_align
;
4673 Temp lower
= Temp();
4674 if (num_bytes
> 16) {
4675 assert(num_components
== 3 || num_components
== 4);
4676 op
= aco_opcode::buffer_load_dwordx4
;
4677 lower
= bld
.tmp(v4
);
4678 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
4679 mubuf
->definitions
[0] = Definition(lower
);
4680 mubuf
->operands
[0] = Operand(rsrc
);
4681 mubuf
->operands
[1] = vaddr
;
4682 mubuf
->operands
[2] = soffset
;
4683 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
4686 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4687 mubuf
->can_reorder
= readonly
;
4688 bld
.insert(std::move(mubuf
));
4689 emit_split_vector(ctx
, lower
, 2);
4692 } else if (num_bytes
== 12 && ctx
->options
->chip_class
== GFX6
) {
4693 /* GFX6 doesn't support loading vec3, expand to vec4. */
4697 switch (num_bytes
) {
4699 op
= aco_opcode::buffer_load_ubyte
;
4702 op
= aco_opcode::buffer_load_ushort
;
4706 op
= aco_opcode::buffer_load_dword
;
4712 op
= aco_opcode::buffer_load_dwordx2
;
4716 assert(ctx
->options
->chip_class
> GFX6
);
4717 op
= aco_opcode::buffer_load_dwordx3
;
4720 op
= aco_opcode::buffer_load_dwordx4
;
4723 unreachable("Load SSBO not implemented for this size.");
4725 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
4726 mubuf
->operands
[0] = Operand(rsrc
);
4727 mubuf
->operands
[1] = vaddr
;
4728 mubuf
->operands
[2] = soffset
;
4729 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
4732 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4733 mubuf
->can_reorder
= readonly
;
4734 mubuf
->offset
= const_offset
;
4735 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
4737 if (component_size
< 4) {
4738 Temp vec
= num_bytes
<= 4 ? bld
.tmp(v1
) : num_bytes
<= 8 ? bld
.tmp(v2
) : bld
.tmp(v3
);
4739 instr
->definitions
[0] = Definition(vec
);
4740 bld
.insert(std::move(instr
));
4742 if (byte_align
== -1 || (byte_align
&& dst
.type() == RegType::sgpr
)) {
4743 Operand align
= byte_align
== -1 ? Operand(offset
) : Operand((uint32_t)byte_align
);
4744 Temp tmp
[3] = {vec
, vec
, vec
};
4746 if (vec
.size() == 3) {
4747 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
4748 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
4749 } else if (vec
.size() == 2) {
4750 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
4751 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
4753 for (unsigned i
= 0; i
< dst
.size(); i
++)
4754 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], align
);
4757 if (dst
.size() == 2)
4758 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
4763 if (dst
.type() == RegType::vgpr
&& num_components
== 1) {
4764 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), vec
, Operand(byte_align
/ component_size
));
4766 trim_subdword_vector(ctx
, vec
, dst
, 4 * vec
.size() / component_size
, ((1 << num_components
) - 1) << byte_align
/ component_size
);
4771 } else if (dst
.size() > 4) {
4772 assert(lower
!= Temp());
4773 Temp upper
= bld
.tmp(RegType::vgpr
, dst
.size() - lower
.size());
4774 instr
->definitions
[0] = Definition(upper
);
4775 bld
.insert(std::move(instr
));
4776 if (dst
.size() == 8)
4777 emit_split_vector(ctx
, upper
, 2);
4778 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size() / 2, 1));
4779 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, lower
, 0, v2
));
4780 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, lower
, 1, v2
));
4781 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, upper
, 0, v2
));
4782 if (dst
.size() == 8)
4783 instr
->operands
[3] = Operand(emit_extract_vector(ctx
, upper
, 1, v2
));
4784 } else if (dst
.size() == 3 && ctx
->options
->chip_class
== GFX6
) {
4785 Temp vec
= bld
.tmp(v4
);
4786 instr
->definitions
[0] = Definition(vec
);
4787 bld
.insert(std::move(instr
));
4788 emit_split_vector(ctx
, vec
, 4);
4790 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 3, 1));
4791 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, vec
, 0, v1
));
4792 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, vec
, 1, v1
));
4793 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, vec
, 2, v1
));
4796 if (dst
.type() == RegType::sgpr
) {
4797 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
4798 instr
->definitions
[0] = Definition(vec
);
4799 bld
.insert(std::move(instr
));
4800 expand_vector(ctx
, vec
, dst
, num_components
, (1 << num_components
) - 1);
4802 instr
->definitions
[0] = Definition(dst
);
4803 bld
.insert(std::move(instr
));
4804 emit_split_vector(ctx
, dst
, num_components
);
4807 /* for small bit sizes add buffer for unaligned loads */
4809 num_bytes
+= byte_align
== -1 ? 4 - component_size
: byte_align
;
4811 switch (num_bytes
) {
4816 op
= aco_opcode::s_buffer_load_dword
;
4822 op
= aco_opcode::s_buffer_load_dwordx2
;
4827 op
= aco_opcode::s_buffer_load_dwordx4
;
4831 op
= aco_opcode::s_buffer_load_dwordx8
;
4834 unreachable("Load SSBO not implemented for this size.");
4836 offset
= bld
.as_uniform(offset
);
4837 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
4838 load
->operands
[0] = Operand(rsrc
);
4839 load
->operands
[1] = Operand(offset
);
4840 assert(load
->operands
[1].getTemp().type() == RegType::sgpr
);
4841 load
->definitions
[0] = Definition(dst
);
4844 load
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4845 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
4846 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
4848 /* adjust misaligned small bit size loads */
4850 Temp vec
= num_bytes
<= 4 ? bld
.tmp(s1
) : num_bytes
<= 8 ? bld
.tmp(s2
) : bld
.tmp(s4
);
4851 load
->definitions
[0] = Definition(vec
);
4852 bld
.insert(std::move(load
));
4853 Operand byte_offset
= byte_align
> 0 ? Operand(uint32_t(byte_align
)) : Operand(offset
);
4854 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
4857 } else if (dst
.size() == 3) {
4858 Temp vec
= bld
.tmp(s4
);
4859 load
->definitions
[0] = Definition(vec
);
4860 bld
.insert(std::move(load
));
4861 emit_split_vector(ctx
, vec
, 4);
4863 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4864 emit_extract_vector(ctx
, vec
, 0, s1
),
4865 emit_extract_vector(ctx
, vec
, 1, s1
),
4866 emit_extract_vector(ctx
, vec
, 2, s1
));
4867 } else if (dst
.size() == 6) {
4868 Temp vec
= bld
.tmp(s8
);
4869 load
->definitions
[0] = Definition(vec
);
4870 bld
.insert(std::move(load
));
4871 emit_split_vector(ctx
, vec
, 4);
4873 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4874 emit_extract_vector(ctx
, vec
, 0, s2
),
4875 emit_extract_vector(ctx
, vec
, 1, s2
),
4876 emit_extract_vector(ctx
, vec
, 2, s2
));
4878 bld
.insert(std::move(load
));
4880 emit_split_vector(ctx
, dst
, num_components
);
4884 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4886 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4887 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4889 Builder
bld(ctx
->program
, ctx
->block
);
4891 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
4892 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
4893 unsigned binding
= nir_intrinsic_binding(idx_instr
);
4894 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
4896 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
4897 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
4898 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
4899 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
4900 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
4901 if (ctx
->options
->chip_class
>= GFX10
) {
4902 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
4903 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
4904 S_008F0C_RESOURCE_LEVEL(1);
4906 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
4907 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
4909 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
4910 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
4911 Operand(0xFFFFFFFFu
),
4912 Operand(desc_type
));
4913 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
4914 rsrc
, upper_dwords
);
4916 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
4917 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
4919 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
4922 unsigned align_mul
= nir_intrinsic_align_mul(instr
);
4923 unsigned align_offset
= nir_intrinsic_align_offset(instr
);
4924 byte_align
= align_mul
% 4 == 0 ? align_offset
: -1;
4926 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), byte_align
);
4929 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4931 Builder
bld(ctx
->program
, ctx
->block
);
4932 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4933 unsigned offset
= nir_intrinsic_base(instr
);
4934 unsigned count
= instr
->dest
.ssa
.num_components
;
4935 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
4937 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
4938 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
4939 start
-= ctx
->args
->ac
.base_inline_push_consts
;
4940 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
4941 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4942 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
4943 for (unsigned i
= 0; i
< count
; ++i
) {
4944 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
4945 vec
->operands
[i
] = Operand
{elems
[i
]};
4947 vec
->definitions
[0] = Definition(dst
);
4948 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4949 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4954 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
4955 if (offset
!= 0) // TODO check if index != 0 as well
4956 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
4957 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
4960 bool aligned
= true;
4962 if (instr
->dest
.ssa
.bit_size
== 8) {
4963 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
4964 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
4966 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
4967 } else if (instr
->dest
.ssa
.bit_size
== 16) {
4968 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
4970 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
4975 switch (vec
.size()) {
4977 op
= aco_opcode::s_load_dword
;
4980 op
= aco_opcode::s_load_dwordx2
;
4986 op
= aco_opcode::s_load_dwordx4
;
4992 op
= aco_opcode::s_load_dwordx8
;
4995 unreachable("unimplemented or forbidden load_push_constant.");
4998 bld
.smem(op
, Definition(vec
), ptr
, index
);
5001 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5002 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5007 emit_split_vector(ctx
, vec
, 4);
5008 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5009 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5010 emit_extract_vector(ctx
, vec
, 0, rc
),
5011 emit_extract_vector(ctx
, vec
, 1, rc
),
5012 emit_extract_vector(ctx
, vec
, 2, rc
));
5015 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5018 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5020 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5022 Builder
bld(ctx
->program
, ctx
->block
);
5024 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5025 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5026 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5027 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5028 if (ctx
->options
->chip_class
>= GFX10
) {
5029 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5030 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5031 S_008F0C_RESOURCE_LEVEL(1);
5033 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5034 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5037 unsigned base
= nir_intrinsic_base(instr
);
5038 unsigned range
= nir_intrinsic_range(instr
);
5040 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5041 if (base
&& offset
.type() == RegType::sgpr
)
5042 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5043 else if (base
&& offset
.type() == RegType::vgpr
)
5044 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5046 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5047 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5048 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5049 Operand(desc_type
));
5050 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5051 // TODO: get alignment information for subdword constants
5052 unsigned byte_align
= size
< 4 ? -1 : 0;
5053 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, byte_align
);
5056 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5058 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5059 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5061 ctx
->program
->needs_exact
= true;
5063 // TODO: optimize uniform conditions
5064 Builder
bld(ctx
->program
, ctx
->block
);
5065 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5066 assert(src
.regClass() == bld
.lm
);
5067 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5068 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5069 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5073 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5075 Builder
bld(ctx
->program
, ctx
->block
);
5077 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5078 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5080 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5081 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5083 if (ctx
->block
->loop_nest_depth
&&
5084 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5085 /* we handle discards the same way as jump instructions */
5086 append_logical_end(ctx
->block
);
5088 /* in loops, discard behaves like break */
5089 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5090 ctx
->block
->kind
|= block_kind_discard
;
5093 /* uniform discard - loop ends here */
5094 assert(nir_instr_is_last(&instr
->instr
));
5095 ctx
->block
->kind
|= block_kind_uniform
;
5096 ctx
->cf_info
.has_branch
= true;
5097 bld
.branch(aco_opcode::p_branch
);
5098 add_linear_edge(ctx
->block
->index
, linear_target
);
5102 /* we add a break right behind the discard() instructions */
5103 ctx
->block
->kind
|= block_kind_break
;
5104 unsigned idx
= ctx
->block
->index
;
5106 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5107 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5109 /* remove critical edges from linear CFG */
5110 bld
.branch(aco_opcode::p_branch
);
5111 Block
* break_block
= ctx
->program
->create_and_insert_block();
5112 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5113 break_block
->kind
|= block_kind_uniform
;
5114 add_linear_edge(idx
, break_block
);
5115 add_linear_edge(break_block
->index
, linear_target
);
5116 bld
.reset(break_block
);
5117 bld
.branch(aco_opcode::p_branch
);
5119 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5120 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5121 add_linear_edge(idx
, continue_block
);
5122 append_logical_start(continue_block
);
5123 ctx
->block
= continue_block
;
5128 /* it can currently happen that NIR doesn't remove the unreachable code */
5129 if (!nir_instr_is_last(&instr
->instr
)) {
5130 ctx
->program
->needs_exact
= true;
5131 /* save exec somewhere temporarily so that it doesn't get
5132 * overwritten before the discard from outer exec masks */
5133 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5134 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5135 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5139 /* This condition is incorrect for uniformly branched discards in a loop
5140 * predicated by a divergent condition, but the above code catches that case
5141 * and the discard would end up turning into a discard_if.
5151 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5152 /* program just ends here */
5153 ctx
->block
->kind
|= block_kind_uniform
;
5154 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5155 0 /* enabled mask */, 9 /* dest */,
5156 false /* compressed */, true/* done */, true /* valid mask */);
5157 bld
.sopp(aco_opcode::s_endpgm
);
5158 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5160 ctx
->block
->kind
|= block_kind_discard
;
5161 /* branch and linear edge is added by visit_if() */
5165 enum aco_descriptor_type
{
5176 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5177 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5179 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5180 return dim
== ac_image_cube
||
5181 dim
== ac_image_1darray
||
5182 dim
== ac_image_2darray
||
5183 dim
== ac_image_2darraymsaa
;
5186 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5187 enum aco_descriptor_type desc_type
,
5188 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5190 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5191 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5192 if (it != ctx->tex_desc.end())
5195 Temp index
= Temp();
5196 bool index_set
= false;
5197 unsigned constant_index
= 0;
5198 unsigned descriptor_set
;
5199 unsigned base_index
;
5200 Builder
bld(ctx
->program
, ctx
->block
);
5203 assert(tex_instr
&& !image
);
5205 base_index
= tex_instr
->sampler_index
;
5207 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5208 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5212 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5213 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5215 constant_index
+= array_size
* const_value
->u32
;
5217 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5218 if (indirect
.type() == RegType::vgpr
)
5219 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5221 if (array_size
!= 1)
5222 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5228 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5232 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5234 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5235 base_index
= deref_instr
->var
->data
.binding
;
5238 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5239 list
= convert_pointer_to_64_bit(ctx
, list
);
5241 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5242 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5243 unsigned offset
= binding
->offset
;
5244 unsigned stride
= binding
->size
;
5248 assert(base_index
< layout
->binding_count
);
5250 switch (desc_type
) {
5251 case ACO_DESC_IMAGE
:
5253 opcode
= aco_opcode::s_load_dwordx8
;
5255 case ACO_DESC_FMASK
:
5257 opcode
= aco_opcode::s_load_dwordx8
;
5260 case ACO_DESC_SAMPLER
:
5262 opcode
= aco_opcode::s_load_dwordx4
;
5263 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5264 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5266 case ACO_DESC_BUFFER
:
5268 opcode
= aco_opcode::s_load_dwordx4
;
5270 case ACO_DESC_PLANE_0
:
5271 case ACO_DESC_PLANE_1
:
5273 opcode
= aco_opcode::s_load_dwordx8
;
5274 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5276 case ACO_DESC_PLANE_2
:
5278 opcode
= aco_opcode::s_load_dwordx4
;
5282 unreachable("invalid desc_type\n");
5285 offset
+= constant_index
* stride
;
5287 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5288 (!index_set
|| binding
->immutable_samplers_equal
)) {
5289 if (binding
->immutable_samplers_equal
)
5292 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5293 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5294 Operand(samplers
[constant_index
* 4 + 0]),
5295 Operand(samplers
[constant_index
* 4 + 1]),
5296 Operand(samplers
[constant_index
* 4 + 2]),
5297 Operand(samplers
[constant_index
* 4 + 3]));
5302 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5304 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5305 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5308 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5310 if (desc_type
== ACO_DESC_PLANE_2
) {
5312 for (unsigned i
= 0; i
< 8; i
++)
5313 components
[i
] = bld
.tmp(s1
);
5314 bld
.pseudo(aco_opcode::p_split_vector
,
5315 Definition(components
[0]),
5316 Definition(components
[1]),
5317 Definition(components
[2]),
5318 Definition(components
[3]),
5321 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5322 bld
.pseudo(aco_opcode::p_split_vector
,
5323 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5324 Definition(components
[4]),
5325 Definition(components
[5]),
5326 Definition(components
[6]),
5327 Definition(components
[7]),
5330 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5331 components
[0], components
[1], components
[2], components
[3],
5332 components
[4], components
[5], components
[6], components
[7]);
5338 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5341 case GLSL_SAMPLER_DIM_BUF
:
5343 case GLSL_SAMPLER_DIM_1D
:
5344 return array
? 2 : 1;
5345 case GLSL_SAMPLER_DIM_2D
:
5346 return array
? 3 : 2;
5347 case GLSL_SAMPLER_DIM_MS
:
5348 return array
? 4 : 3;
5349 case GLSL_SAMPLER_DIM_3D
:
5350 case GLSL_SAMPLER_DIM_CUBE
:
5352 case GLSL_SAMPLER_DIM_RECT
:
5353 case GLSL_SAMPLER_DIM_SUBPASS
:
5355 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5364 /* Adjust the sample index according to FMASK.
5366 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5367 * which is the identity mapping. Each nibble says which physical sample
5368 * should be fetched to get that sample.
5370 * For example, 0x11111100 means there are only 2 samples stored and
5371 * the second sample covers 3/4 of the pixel. When reading samples 0
5372 * and 1, return physical sample 0 (determined by the first two 0s
5373 * in FMASK), otherwise return physical sample 1.
5375 * The sample index should be adjusted as follows:
5376 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5378 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5380 Builder
bld(ctx
->program
, ctx
->block
);
5381 Temp fmask
= bld
.tmp(v1
);
5382 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5383 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5386 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5387 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5388 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5389 load
->operands
[0] = Operand(fmask_desc_ptr
);
5390 load
->operands
[1] = Operand(s4
); /* no sampler */
5391 load
->operands
[2] = Operand(coord
);
5392 load
->definitions
[0] = Definition(fmask
);
5399 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5400 ctx
->block
->instructions
.emplace_back(std::move(load
));
5402 Operand sample_index4
;
5403 if (sample_index
.isConstant() && sample_index
.constantValue() < 16) {
5404 sample_index4
= Operand(sample_index
.constantValue() << 2);
5405 } else if (sample_index
.regClass() == s1
) {
5406 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5408 assert(sample_index
.regClass() == v1
);
5409 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5413 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5414 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5415 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5416 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5418 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5420 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5421 * resource descriptor is 0 (invalid),
5423 Temp compare
= bld
.tmp(bld
.lm
);
5424 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5425 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5427 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5429 /* Replace the MSAA sample index. */
5430 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5433 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5436 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5437 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5438 bool is_array
= glsl_sampler_type_is_array(type
);
5439 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5440 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5441 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5442 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5443 int count
= image_type_to_components_count(dim
, is_array
);
5444 std::vector
<Temp
> coords(count
);
5445 Builder
bld(ctx
->program
, ctx
->block
);
5449 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5450 /* get sample index */
5451 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5452 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5453 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5454 std::vector
<Temp
> fmask_load_address
;
5455 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5456 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5458 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5459 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5461 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5466 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5467 coords
.resize(coords
.size() + 1);
5468 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5470 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5472 for (int i
= 0; i
< count
; i
++)
5473 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5476 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5477 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5478 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5479 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5482 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5485 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5486 for (unsigned i
= 0; i
< coords
.size(); i
++)
5487 vec
->operands
[i
] = Operand(coords
[i
]);
5488 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5489 vec
->definitions
[0] = Definition(res
);
5490 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5495 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5497 Builder
bld(ctx
->program
, ctx
->block
);
5498 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5499 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5500 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5501 bool is_array
= glsl_sampler_type_is_array(type
);
5502 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5504 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5505 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5506 unsigned num_channels
= util_last_bit(mask
);
5507 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5508 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5511 switch (num_channels
) {
5513 opcode
= aco_opcode::buffer_load_format_x
;
5516 opcode
= aco_opcode::buffer_load_format_xy
;
5519 opcode
= aco_opcode::buffer_load_format_xyz
;
5522 opcode
= aco_opcode::buffer_load_format_xyzw
;
5525 unreachable(">4 channel buffer image load");
5527 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5528 load
->operands
[0] = Operand(rsrc
);
5529 load
->operands
[1] = Operand(vindex
);
5530 load
->operands
[2] = Operand((uint32_t) 0);
5532 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5535 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5536 load
->definitions
[0] = Definition(tmp
);
5538 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5539 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5540 load
->barrier
= barrier_image
;
5541 ctx
->block
->instructions
.emplace_back(std::move(load
));
5543 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5547 Temp coords
= get_image_coords(ctx
, instr
, type
);
5548 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5550 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5551 unsigned num_components
= util_bitcount(dmask
);
5553 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5556 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5558 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5559 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5561 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5562 load
->operands
[0] = Operand(resource
);
5563 load
->operands
[1] = Operand(s4
); /* no sampler */
5564 load
->operands
[2] = Operand(coords
);
5565 load
->definitions
[0] = Definition(tmp
);
5566 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5567 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5568 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5569 load
->dmask
= dmask
;
5571 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5572 load
->barrier
= barrier_image
;
5573 ctx
->block
->instructions
.emplace_back(std::move(load
));
5575 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5579 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5581 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5582 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5583 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5584 bool is_array
= glsl_sampler_type_is_array(type
);
5585 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5587 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5589 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5590 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5591 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5593 switch (data
.size()) {
5595 opcode
= aco_opcode::buffer_store_format_x
;
5598 opcode
= aco_opcode::buffer_store_format_xy
;
5601 opcode
= aco_opcode::buffer_store_format_xyz
;
5604 opcode
= aco_opcode::buffer_store_format_xyzw
;
5607 unreachable(">4 channel buffer image store");
5609 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5610 store
->operands
[0] = Operand(rsrc
);
5611 store
->operands
[1] = Operand(vindex
);
5612 store
->operands
[2] = Operand((uint32_t) 0);
5613 store
->operands
[3] = Operand(data
);
5614 store
->idxen
= true;
5617 store
->disable_wqm
= true;
5618 store
->barrier
= barrier_image
;
5619 ctx
->program
->needs_exact
= true;
5620 ctx
->block
->instructions
.emplace_back(std::move(store
));
5624 assert(data
.type() == RegType::vgpr
);
5625 Temp coords
= get_image_coords(ctx
, instr
, type
);
5626 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5628 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5629 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5631 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5632 store
->operands
[0] = Operand(resource
);
5633 store
->operands
[1] = Operand(data
);
5634 store
->operands
[2] = Operand(coords
);
5637 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5638 store
->dmask
= (1 << data
.size()) - 1;
5640 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5641 store
->disable_wqm
= true;
5642 store
->barrier
= barrier_image
;
5643 ctx
->program
->needs_exact
= true;
5644 ctx
->block
->instructions
.emplace_back(std::move(store
));
5648 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5650 /* return the previous value if dest is ever used */
5651 bool return_previous
= false;
5652 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5653 return_previous
= true;
5656 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5657 return_previous
= true;
5661 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5662 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5663 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5664 bool is_array
= glsl_sampler_type_is_array(type
);
5665 Builder
bld(ctx
->program
, ctx
->block
);
5667 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5668 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5670 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5671 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5673 aco_opcode buf_op
, image_op
;
5674 switch (instr
->intrinsic
) {
5675 case nir_intrinsic_image_deref_atomic_add
:
5676 buf_op
= aco_opcode::buffer_atomic_add
;
5677 image_op
= aco_opcode::image_atomic_add
;
5679 case nir_intrinsic_image_deref_atomic_umin
:
5680 buf_op
= aco_opcode::buffer_atomic_umin
;
5681 image_op
= aco_opcode::image_atomic_umin
;
5683 case nir_intrinsic_image_deref_atomic_imin
:
5684 buf_op
= aco_opcode::buffer_atomic_smin
;
5685 image_op
= aco_opcode::image_atomic_smin
;
5687 case nir_intrinsic_image_deref_atomic_umax
:
5688 buf_op
= aco_opcode::buffer_atomic_umax
;
5689 image_op
= aco_opcode::image_atomic_umax
;
5691 case nir_intrinsic_image_deref_atomic_imax
:
5692 buf_op
= aco_opcode::buffer_atomic_smax
;
5693 image_op
= aco_opcode::image_atomic_smax
;
5695 case nir_intrinsic_image_deref_atomic_and
:
5696 buf_op
= aco_opcode::buffer_atomic_and
;
5697 image_op
= aco_opcode::image_atomic_and
;
5699 case nir_intrinsic_image_deref_atomic_or
:
5700 buf_op
= aco_opcode::buffer_atomic_or
;
5701 image_op
= aco_opcode::image_atomic_or
;
5703 case nir_intrinsic_image_deref_atomic_xor
:
5704 buf_op
= aco_opcode::buffer_atomic_xor
;
5705 image_op
= aco_opcode::image_atomic_xor
;
5707 case nir_intrinsic_image_deref_atomic_exchange
:
5708 buf_op
= aco_opcode::buffer_atomic_swap
;
5709 image_op
= aco_opcode::image_atomic_swap
;
5711 case nir_intrinsic_image_deref_atomic_comp_swap
:
5712 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5713 image_op
= aco_opcode::image_atomic_cmpswap
;
5716 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5719 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5721 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5722 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5723 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5724 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5725 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5726 mubuf
->operands
[0] = Operand(resource
);
5727 mubuf
->operands
[1] = Operand(vindex
);
5728 mubuf
->operands
[2] = Operand((uint32_t)0);
5729 mubuf
->operands
[3] = Operand(data
);
5730 if (return_previous
)
5731 mubuf
->definitions
[0] = Definition(dst
);
5733 mubuf
->idxen
= true;
5734 mubuf
->glc
= return_previous
;
5735 mubuf
->dlc
= false; /* Not needed for atomics */
5736 mubuf
->disable_wqm
= true;
5737 mubuf
->barrier
= barrier_image
;
5738 ctx
->program
->needs_exact
= true;
5739 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5743 Temp coords
= get_image_coords(ctx
, instr
, type
);
5744 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5745 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
5746 mimg
->operands
[0] = Operand(resource
);
5747 mimg
->operands
[1] = Operand(data
);
5748 mimg
->operands
[2] = Operand(coords
);
5749 if (return_previous
)
5750 mimg
->definitions
[0] = Definition(dst
);
5751 mimg
->glc
= return_previous
;
5752 mimg
->dlc
= false; /* Not needed for atomics */
5753 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5754 mimg
->dmask
= (1 << data
.size()) - 1;
5756 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5757 mimg
->disable_wqm
= true;
5758 mimg
->barrier
= barrier_image
;
5759 ctx
->program
->needs_exact
= true;
5760 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5764 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
5766 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
5767 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
5768 Builder
bld(ctx
->program
, ctx
->block
);
5770 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
5772 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
5773 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
5775 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
5776 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
5778 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
5779 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
5781 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
5782 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
5783 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
5784 if (dst
.type() == RegType::vgpr
)
5785 bld
.copy(Definition(dst
), shr_dst
);
5787 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
5789 emit_extract_vector(ctx
, desc
, 2, dst
);
5793 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5795 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5796 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5797 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5798 bool is_array
= glsl_sampler_type_is_array(type
);
5799 Builder
bld(ctx
->program
, ctx
->block
);
5801 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
5802 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
5803 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
5807 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
5810 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
5812 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5814 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
5815 mimg
->operands
[0] = Operand(resource
);
5816 mimg
->operands
[1] = Operand(s4
); /* no sampler */
5817 mimg
->operands
[2] = Operand(lod
);
5818 uint8_t& dmask
= mimg
->dmask
;
5819 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5820 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
5821 mimg
->da
= glsl_sampler_type_is_array(type
);
5822 mimg
->can_reorder
= true;
5823 Definition
& def
= mimg
->definitions
[0];
5824 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5826 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
5827 glsl_sampler_type_is_array(type
)) {
5829 assert(instr
->dest
.ssa
.num_components
== 3);
5830 Temp tmp
= {ctx
->program
->allocateId(), v3
};
5831 def
= Definition(tmp
);
5832 emit_split_vector(ctx
, tmp
, 3);
5834 /* divide 3rd value by 6 by multiplying with magic number */
5835 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
5836 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
5838 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5839 emit_extract_vector(ctx
, tmp
, 0, v1
),
5840 emit_extract_vector(ctx
, tmp
, 1, v1
),
5843 } else if (ctx
->options
->chip_class
== GFX9
&&
5844 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
5845 glsl_sampler_type_is_array(type
)) {
5846 assert(instr
->dest
.ssa
.num_components
== 2);
5847 def
= Definition(dst
);
5850 def
= Definition(dst
);
5853 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5856 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5858 Builder
bld(ctx
->program
, ctx
->block
);
5859 unsigned num_components
= instr
->num_components
;
5861 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5862 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5863 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5865 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5866 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5869 unsigned align_mul
= nir_intrinsic_align_mul(instr
);
5870 unsigned align_offset
= nir_intrinsic_align_offset(instr
);
5871 byte_align
= align_mul
% 4 == 0 ? align_offset
: -1;
5873 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), byte_align
, glc
, false);
5876 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5878 Builder
bld(ctx
->program
, ctx
->block
);
5879 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5880 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
5881 unsigned writemask
= nir_intrinsic_write_mask(instr
);
5882 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5884 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
5885 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5887 bool smem
= !ctx
->divergent_vals
[instr
->src
[2].ssa
->index
] &&
5888 ctx
->options
->chip_class
>= GFX8
&&
5889 elem_size_bytes
>= 4;
5891 offset
= bld
.as_uniform(offset
);
5892 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
5896 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
5897 if (count
== 3 && (smem
|| ctx
->options
->chip_class
== GFX6
)) {
5898 /* GFX6 doesn't support storing vec3, split it. */
5899 writemask
|= 1u << (start
+ 2);
5902 int num_bytes
= count
* elem_size_bytes
;
5904 /* dword or larger stores have to be dword-aligned */
5905 if (elem_size_bytes
< 4 && num_bytes
> 2) {
5906 // TODO: improve alignment check of sub-dword stores
5907 unsigned count_new
= 2 / elem_size_bytes
;
5908 writemask
|= ((1 << (count
- count_new
)) - 1) << (start
+ count_new
);
5913 if (num_bytes
> 16) {
5914 assert(elem_size_bytes
== 8);
5915 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
5921 if (elem_size_bytes
< 4) {
5922 if (data
.type() == RegType::sgpr
) {
5923 data
= as_vgpr(ctx
, data
);
5924 emit_split_vector(ctx
, data
, 4 * data
.size() / elem_size_bytes
);
5926 RegClass rc
= RegClass(RegType::vgpr
, elem_size_bytes
).as_subdword();
5927 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5928 for (int i
= 0; i
< count
; i
++)
5929 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, data
, start
+ i
, rc
));
5930 write_data
= bld
.tmp(RegClass(RegType::vgpr
, num_bytes
).as_subdword());
5931 vec
->definitions
[0] = Definition(write_data
);
5932 bld
.insert(std::move(vec
));
5933 } else if (count
!= instr
->num_components
) {
5934 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5935 for (int i
= 0; i
< count
; i
++) {
5936 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(data
.type(), elem_size_bytes
/ 4));
5937 vec
->operands
[i
] = Operand(smem_nonfs
? bld
.as_uniform(elem
) : elem
);
5939 write_data
= bld
.tmp(!smem
? RegType::vgpr
: smem_nonfs
? RegType::sgpr
: data
.type(), count
* elem_size_bytes
/ 4);
5940 vec
->definitions
[0] = Definition(write_data
);
5941 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5942 } else if (!smem
&& data
.type() != RegType::vgpr
) {
5943 assert(num_bytes
% 4 == 0);
5944 write_data
= bld
.copy(bld
.def(RegType::vgpr
, num_bytes
/ 4), data
);
5945 } else if (smem_nonfs
&& data
.type() == RegType::vgpr
) {
5946 assert(num_bytes
% 4 == 0);
5947 write_data
= bld
.as_uniform(data
);
5952 aco_opcode vmem_op
, smem_op
= aco_opcode::last_opcode
;
5953 switch (num_bytes
) {
5955 vmem_op
= aco_opcode::buffer_store_byte
;
5958 vmem_op
= aco_opcode::buffer_store_short
;
5961 vmem_op
= aco_opcode::buffer_store_dword
;
5962 smem_op
= aco_opcode::s_buffer_store_dword
;
5965 vmem_op
= aco_opcode::buffer_store_dwordx2
;
5966 smem_op
= aco_opcode::s_buffer_store_dwordx2
;
5969 vmem_op
= aco_opcode::buffer_store_dwordx3
;
5970 assert(!smem
&& ctx
->options
->chip_class
> GFX6
);
5973 vmem_op
= aco_opcode::buffer_store_dwordx4
;
5974 smem_op
= aco_opcode::s_buffer_store_dwordx4
;
5977 unreachable("Store SSBO not implemented for this size.");
5979 if (ctx
->stage
== fragment_fs
)
5980 smem_op
= aco_opcode::p_fs_buffer_store_smem
;
5983 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(smem_op
, Format::SMEM
, 3, 0)};
5984 store
->operands
[0] = Operand(rsrc
);
5986 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5987 offset
, Operand(start
* elem_size_bytes
));
5988 store
->operands
[1] = Operand(off
);
5990 store
->operands
[1] = Operand(offset
);
5992 if (smem_op
!= aco_opcode::p_fs_buffer_store_smem
)
5993 store
->operands
[1].setFixed(m0
);
5994 store
->operands
[2] = Operand(write_data
);
5995 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
5997 store
->disable_wqm
= true;
5998 store
->barrier
= barrier_buffer
;
5999 ctx
->block
->instructions
.emplace_back(std::move(store
));
6000 ctx
->program
->wb_smem_l1_on_end
= true;
6001 if (smem_op
== aco_opcode::p_fs_buffer_store_smem
) {
6002 ctx
->block
->kind
|= block_kind_needs_lowering
;
6003 ctx
->program
->needs_exact
= true;
6006 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(vmem_op
, Format::MUBUF
, 4, 0)};
6007 store
->operands
[0] = Operand(rsrc
);
6008 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6009 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6010 store
->operands
[3] = Operand(write_data
);
6011 store
->offset
= start
* elem_size_bytes
;
6012 store
->offen
= (offset
.type() == RegType::vgpr
);
6013 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6015 store
->disable_wqm
= true;
6016 store
->barrier
= barrier_buffer
;
6017 ctx
->program
->needs_exact
= true;
6018 ctx
->block
->instructions
.emplace_back(std::move(store
));
6023 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6025 /* return the previous value if dest is ever used */
6026 bool return_previous
= false;
6027 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6028 return_previous
= true;
6031 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6032 return_previous
= true;
6036 Builder
bld(ctx
->program
, ctx
->block
);
6037 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6039 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6040 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6041 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6043 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6044 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6045 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6047 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6049 aco_opcode op32
, op64
;
6050 switch (instr
->intrinsic
) {
6051 case nir_intrinsic_ssbo_atomic_add
:
6052 op32
= aco_opcode::buffer_atomic_add
;
6053 op64
= aco_opcode::buffer_atomic_add_x2
;
6055 case nir_intrinsic_ssbo_atomic_imin
:
6056 op32
= aco_opcode::buffer_atomic_smin
;
6057 op64
= aco_opcode::buffer_atomic_smin_x2
;
6059 case nir_intrinsic_ssbo_atomic_umin
:
6060 op32
= aco_opcode::buffer_atomic_umin
;
6061 op64
= aco_opcode::buffer_atomic_umin_x2
;
6063 case nir_intrinsic_ssbo_atomic_imax
:
6064 op32
= aco_opcode::buffer_atomic_smax
;
6065 op64
= aco_opcode::buffer_atomic_smax_x2
;
6067 case nir_intrinsic_ssbo_atomic_umax
:
6068 op32
= aco_opcode::buffer_atomic_umax
;
6069 op64
= aco_opcode::buffer_atomic_umax_x2
;
6071 case nir_intrinsic_ssbo_atomic_and
:
6072 op32
= aco_opcode::buffer_atomic_and
;
6073 op64
= aco_opcode::buffer_atomic_and_x2
;
6075 case nir_intrinsic_ssbo_atomic_or
:
6076 op32
= aco_opcode::buffer_atomic_or
;
6077 op64
= aco_opcode::buffer_atomic_or_x2
;
6079 case nir_intrinsic_ssbo_atomic_xor
:
6080 op32
= aco_opcode::buffer_atomic_xor
;
6081 op64
= aco_opcode::buffer_atomic_xor_x2
;
6083 case nir_intrinsic_ssbo_atomic_exchange
:
6084 op32
= aco_opcode::buffer_atomic_swap
;
6085 op64
= aco_opcode::buffer_atomic_swap_x2
;
6087 case nir_intrinsic_ssbo_atomic_comp_swap
:
6088 op32
= aco_opcode::buffer_atomic_cmpswap
;
6089 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6092 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6094 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6095 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6096 mubuf
->operands
[0] = Operand(rsrc
);
6097 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6098 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6099 mubuf
->operands
[3] = Operand(data
);
6100 if (return_previous
)
6101 mubuf
->definitions
[0] = Definition(dst
);
6103 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6104 mubuf
->glc
= return_previous
;
6105 mubuf
->dlc
= false; /* Not needed for atomics */
6106 mubuf
->disable_wqm
= true;
6107 mubuf
->barrier
= barrier_buffer
;
6108 ctx
->program
->needs_exact
= true;
6109 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6112 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6114 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6115 Builder
bld(ctx
->program
, ctx
->block
);
6116 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6117 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6120 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
6122 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6123 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6125 if (addr
.type() == RegType::vgpr
)
6126 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
6127 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
6130 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6132 Builder
bld(ctx
->program
, ctx
->block
);
6133 unsigned num_components
= instr
->num_components
;
6134 unsigned num_bytes
= num_components
* instr
->dest
.ssa
.bit_size
/ 8;
6136 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6137 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6139 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6140 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
6142 if (dst
.type() == RegType::vgpr
|| (glc
&& ctx
->options
->chip_class
< GFX8
)) {
6143 bool global
= ctx
->options
->chip_class
>= GFX9
;
6145 if (ctx
->options
->chip_class
>= GFX7
) {
6147 switch (num_bytes
) {
6149 op
= global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
6152 op
= global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
6155 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
6158 op
= global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
6161 unreachable("load_global not implemented for this size.");
6164 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
6165 flat
->operands
[0] = Operand(addr
);
6166 flat
->operands
[1] = Operand(s1
);
6169 flat
->barrier
= barrier_buffer
;
6171 if (dst
.type() == RegType::sgpr
) {
6172 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
6173 flat
->definitions
[0] = Definition(vec
);
6174 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6175 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
6177 flat
->definitions
[0] = Definition(dst
);
6178 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6180 emit_split_vector(ctx
, dst
, num_components
);
6182 assert(ctx
->options
->chip_class
== GFX6
);
6184 /* GFX6 doesn't support loading vec3, expand to vec4. */
6185 num_bytes
= num_bytes
== 12 ? 16 : num_bytes
;
6188 switch (num_bytes
) {
6190 op
= aco_opcode::buffer_load_dword
;
6193 op
= aco_opcode::buffer_load_dwordx2
;
6196 op
= aco_opcode::buffer_load_dwordx4
;
6199 unreachable("load_global not implemented for this size.");
6202 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6204 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
6205 mubuf
->operands
[0] = Operand(rsrc
);
6206 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6207 mubuf
->operands
[2] = Operand(0u);
6211 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6212 mubuf
->disable_wqm
= false;
6213 mubuf
->barrier
= barrier_buffer
;
6214 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
6217 if (dst
.size() == 3) {
6218 Temp vec
= bld
.tmp(v4
);
6219 instr
->definitions
[0] = Definition(vec
);
6220 bld
.insert(std::move(instr
));
6221 emit_split_vector(ctx
, vec
, 4);
6223 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 3, 1));
6224 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, vec
, 0, v1
));
6225 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, vec
, 1, v1
));
6226 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, vec
, 2, v1
));
6229 if (dst
.type() == RegType::sgpr
) {
6230 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
6231 instr
->definitions
[0] = Definition(vec
);
6232 bld
.insert(std::move(instr
));
6233 expand_vector(ctx
, vec
, dst
, num_components
, (1 << num_components
) - 1);
6234 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
6236 instr
->definitions
[0] = Definition(dst
);
6237 bld
.insert(std::move(instr
));
6238 emit_split_vector(ctx
, dst
, num_components
);
6242 switch (num_bytes
) {
6244 op
= aco_opcode::s_load_dword
;
6247 op
= aco_opcode::s_load_dwordx2
;
6251 op
= aco_opcode::s_load_dwordx4
;
6254 unreachable("load_global not implemented for this size.");
6256 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
6257 load
->operands
[0] = Operand(addr
);
6258 load
->operands
[1] = Operand(0u);
6259 load
->definitions
[0] = Definition(dst
);
6262 load
->barrier
= barrier_buffer
;
6263 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
6265 if (dst
.size() == 3) {
6267 Temp vec
= bld
.tmp(s4
);
6268 load
->definitions
[0] = Definition(vec
);
6269 ctx
->block
->instructions
.emplace_back(std::move(load
));
6270 emit_split_vector(ctx
, vec
, 4);
6272 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6273 emit_extract_vector(ctx
, vec
, 0, s1
),
6274 emit_extract_vector(ctx
, vec
, 1, s1
),
6275 emit_extract_vector(ctx
, vec
, 2, s1
));
6277 ctx
->block
->instructions
.emplace_back(std::move(load
));
6282 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6284 Builder
bld(ctx
->program
, ctx
->block
);
6285 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6287 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6288 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6290 if (ctx
->options
->chip_class
>= GFX7
)
6291 addr
= as_vgpr(ctx
, addr
);
6293 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6296 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
6297 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
6298 /* GFX6 doesn't support storing vec3, split it. */
6299 writemask
|= 1u << (start
+ 2);
6302 unsigned num_bytes
= count
* elem_size_bytes
;
6304 Temp write_data
= data
;
6305 if (count
!= instr
->num_components
) {
6306 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6307 for (int i
= 0; i
< count
; i
++)
6308 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, data
, start
+ i
, v1
));
6309 write_data
= bld
.tmp(RegType::vgpr
, count
);
6310 vec
->definitions
[0] = Definition(write_data
);
6311 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6314 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6315 unsigned offset
= start
* elem_size_bytes
;
6317 if (ctx
->options
->chip_class
>= GFX7
) {
6318 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6319 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6320 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6321 Temp carry
= bld
.tmp(bld
.lm
);
6322 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6324 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6325 Operand(offset
), addr0
);
6326 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6328 carry
).def(1).setHint(vcc
);
6330 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6335 bool global
= ctx
->options
->chip_class
>= GFX9
;
6337 switch (num_bytes
) {
6339 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6342 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6345 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6348 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6351 unreachable("store_global not implemented for this size.");
6354 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6355 flat
->operands
[0] = Operand(addr
);
6356 flat
->operands
[1] = Operand(s1
);
6357 flat
->operands
[2] = Operand(data
);
6360 flat
->offset
= offset
;
6361 flat
->disable_wqm
= true;
6362 flat
->barrier
= barrier_buffer
;
6363 ctx
->program
->needs_exact
= true;
6364 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6366 assert(ctx
->options
->chip_class
== GFX6
);
6369 switch (num_bytes
) {
6371 op
= aco_opcode::buffer_store_dword
;
6374 op
= aco_opcode::buffer_store_dwordx2
;
6377 op
= aco_opcode::buffer_store_dwordx4
;
6380 unreachable("store_global not implemented for this size.");
6383 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6385 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6386 mubuf
->operands
[0] = Operand(rsrc
);
6387 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6388 mubuf
->operands
[2] = Operand(0u);
6389 mubuf
->operands
[3] = Operand(write_data
);
6392 mubuf
->offset
= offset
;
6393 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6394 mubuf
->disable_wqm
= true;
6395 mubuf
->barrier
= barrier_buffer
;
6396 ctx
->program
->needs_exact
= true;
6397 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6402 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6404 /* return the previous value if dest is ever used */
6405 bool return_previous
= false;
6406 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6407 return_previous
= true;
6410 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6411 return_previous
= true;
6415 Builder
bld(ctx
->program
, ctx
->block
);
6416 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6417 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6419 if (ctx
->options
->chip_class
>= GFX7
)
6420 addr
= as_vgpr(ctx
, addr
);
6422 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6423 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6424 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6426 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6428 aco_opcode op32
, op64
;
6430 if (ctx
->options
->chip_class
>= GFX7
) {
6431 bool global
= ctx
->options
->chip_class
>= GFX9
;
6432 switch (instr
->intrinsic
) {
6433 case nir_intrinsic_global_atomic_add
:
6434 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6435 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6437 case nir_intrinsic_global_atomic_imin
:
6438 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6439 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6441 case nir_intrinsic_global_atomic_umin
:
6442 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6443 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6445 case nir_intrinsic_global_atomic_imax
:
6446 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6447 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6449 case nir_intrinsic_global_atomic_umax
:
6450 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6451 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6453 case nir_intrinsic_global_atomic_and
:
6454 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6455 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6457 case nir_intrinsic_global_atomic_or
:
6458 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6459 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6461 case nir_intrinsic_global_atomic_xor
:
6462 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6463 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6465 case nir_intrinsic_global_atomic_exchange
:
6466 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6467 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6469 case nir_intrinsic_global_atomic_comp_swap
:
6470 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6471 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6474 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6477 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6478 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6479 flat
->operands
[0] = Operand(addr
);
6480 flat
->operands
[1] = Operand(s1
);
6481 flat
->operands
[2] = Operand(data
);
6482 if (return_previous
)
6483 flat
->definitions
[0] = Definition(dst
);
6484 flat
->glc
= return_previous
;
6485 flat
->dlc
= false; /* Not needed for atomics */
6487 flat
->disable_wqm
= true;
6488 flat
->barrier
= barrier_buffer
;
6489 ctx
->program
->needs_exact
= true;
6490 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6492 assert(ctx
->options
->chip_class
== GFX6
);
6494 switch (instr
->intrinsic
) {
6495 case nir_intrinsic_global_atomic_add
:
6496 op32
= aco_opcode::buffer_atomic_add
;
6497 op64
= aco_opcode::buffer_atomic_add_x2
;
6499 case nir_intrinsic_global_atomic_imin
:
6500 op32
= aco_opcode::buffer_atomic_smin
;
6501 op64
= aco_opcode::buffer_atomic_smin_x2
;
6503 case nir_intrinsic_global_atomic_umin
:
6504 op32
= aco_opcode::buffer_atomic_umin
;
6505 op64
= aco_opcode::buffer_atomic_umin_x2
;
6507 case nir_intrinsic_global_atomic_imax
:
6508 op32
= aco_opcode::buffer_atomic_smax
;
6509 op64
= aco_opcode::buffer_atomic_smax_x2
;
6511 case nir_intrinsic_global_atomic_umax
:
6512 op32
= aco_opcode::buffer_atomic_umax
;
6513 op64
= aco_opcode::buffer_atomic_umax_x2
;
6515 case nir_intrinsic_global_atomic_and
:
6516 op32
= aco_opcode::buffer_atomic_and
;
6517 op64
= aco_opcode::buffer_atomic_and_x2
;
6519 case nir_intrinsic_global_atomic_or
:
6520 op32
= aco_opcode::buffer_atomic_or
;
6521 op64
= aco_opcode::buffer_atomic_or_x2
;
6523 case nir_intrinsic_global_atomic_xor
:
6524 op32
= aco_opcode::buffer_atomic_xor
;
6525 op64
= aco_opcode::buffer_atomic_xor_x2
;
6527 case nir_intrinsic_global_atomic_exchange
:
6528 op32
= aco_opcode::buffer_atomic_swap
;
6529 op64
= aco_opcode::buffer_atomic_swap_x2
;
6531 case nir_intrinsic_global_atomic_comp_swap
:
6532 op32
= aco_opcode::buffer_atomic_cmpswap
;
6533 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6536 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6539 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6541 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6543 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6544 mubuf
->operands
[0] = Operand(rsrc
);
6545 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6546 mubuf
->operands
[2] = Operand(0u);
6547 mubuf
->operands
[3] = Operand(data
);
6548 if (return_previous
)
6549 mubuf
->definitions
[0] = Definition(dst
);
6550 mubuf
->glc
= return_previous
;
6553 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6554 mubuf
->disable_wqm
= true;
6555 mubuf
->barrier
= barrier_buffer
;
6556 ctx
->program
->needs_exact
= true;
6557 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6561 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6562 Builder
bld(ctx
->program
, ctx
->block
);
6563 switch(instr
->intrinsic
) {
6564 case nir_intrinsic_group_memory_barrier
:
6565 case nir_intrinsic_memory_barrier
:
6566 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6568 case nir_intrinsic_memory_barrier_buffer
:
6569 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6571 case nir_intrinsic_memory_barrier_image
:
6572 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6574 case nir_intrinsic_memory_barrier_tcs_patch
:
6575 case nir_intrinsic_memory_barrier_shared
:
6576 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6579 unreachable("Unimplemented memory barrier intrinsic");
6584 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6586 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6587 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6588 assert(instr
->dest
.ssa
.bit_size
>= 32 && "Bitsize not supported in load_shared.");
6589 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6590 Builder
bld(ctx
->program
, ctx
->block
);
6592 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6593 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6594 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6597 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6599 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6600 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6601 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6602 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6603 assert(elem_size_bytes
>= 4 && "Only 32bit & 64bit store_shared currently supported.");
6605 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6606 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6609 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6611 unsigned offset
= nir_intrinsic_base(instr
);
6612 Operand m
= load_lds_size_m0(ctx
);
6613 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6614 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6616 unsigned num_operands
= 3;
6617 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6618 switch(instr
->intrinsic
) {
6619 case nir_intrinsic_shared_atomic_add
:
6620 op32
= aco_opcode::ds_add_u32
;
6621 op64
= aco_opcode::ds_add_u64
;
6622 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6623 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6625 case nir_intrinsic_shared_atomic_imin
:
6626 op32
= aco_opcode::ds_min_i32
;
6627 op64
= aco_opcode::ds_min_i64
;
6628 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6629 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6631 case nir_intrinsic_shared_atomic_umin
:
6632 op32
= aco_opcode::ds_min_u32
;
6633 op64
= aco_opcode::ds_min_u64
;
6634 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6635 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6637 case nir_intrinsic_shared_atomic_imax
:
6638 op32
= aco_opcode::ds_max_i32
;
6639 op64
= aco_opcode::ds_max_i64
;
6640 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6641 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6643 case nir_intrinsic_shared_atomic_umax
:
6644 op32
= aco_opcode::ds_max_u32
;
6645 op64
= aco_opcode::ds_max_u64
;
6646 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6647 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6649 case nir_intrinsic_shared_atomic_and
:
6650 op32
= aco_opcode::ds_and_b32
;
6651 op64
= aco_opcode::ds_and_b64
;
6652 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6653 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6655 case nir_intrinsic_shared_atomic_or
:
6656 op32
= aco_opcode::ds_or_b32
;
6657 op64
= aco_opcode::ds_or_b64
;
6658 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6659 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6661 case nir_intrinsic_shared_atomic_xor
:
6662 op32
= aco_opcode::ds_xor_b32
;
6663 op64
= aco_opcode::ds_xor_b64
;
6664 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6665 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6667 case nir_intrinsic_shared_atomic_exchange
:
6668 op32
= aco_opcode::ds_write_b32
;
6669 op64
= aco_opcode::ds_write_b64
;
6670 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6671 op64_rtn
= aco_opcode::ds_wrxchg2_rtn_b64
;
6673 case nir_intrinsic_shared_atomic_comp_swap
:
6674 op32
= aco_opcode::ds_cmpst_b32
;
6675 op64
= aco_opcode::ds_cmpst_b64
;
6676 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6677 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6681 unreachable("Unhandled shared atomic intrinsic");
6684 /* return the previous value if dest is ever used */
6685 bool return_previous
= false;
6686 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6687 return_previous
= true;
6690 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6691 return_previous
= true;
6696 if (data
.size() == 1) {
6697 assert(instr
->dest
.ssa
.bit_size
== 32);
6698 op
= return_previous
? op32_rtn
: op32
;
6700 assert(instr
->dest
.ssa
.bit_size
== 64);
6701 op
= return_previous
? op64_rtn
: op64
;
6704 if (offset
> 65535) {
6705 Builder
bld(ctx
->program
, ctx
->block
);
6706 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6710 aco_ptr
<DS_instruction
> ds
;
6711 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6712 ds
->operands
[0] = Operand(address
);
6713 ds
->operands
[1] = Operand(data
);
6714 if (num_operands
== 4)
6715 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6716 ds
->operands
[num_operands
- 1] = m
;
6717 ds
->offset0
= offset
;
6718 if (return_previous
)
6719 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6720 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6723 Temp
get_scratch_resource(isel_context
*ctx
)
6725 Builder
bld(ctx
->program
, ctx
->block
);
6726 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6727 if (ctx
->stage
!= compute_cs
)
6728 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6730 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6731 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6733 if (ctx
->program
->chip_class
>= GFX10
) {
6734 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6735 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6736 S_008F0C_RESOURCE_LEVEL(1);
6737 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6738 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6739 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6742 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6743 if (ctx
->program
->chip_class
<= GFX8
)
6744 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6746 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6749 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6750 assert(instr
->dest
.ssa
.bit_size
== 32 || instr
->dest
.ssa
.bit_size
== 64);
6751 Builder
bld(ctx
->program
, ctx
->block
);
6752 Temp rsrc
= get_scratch_resource(ctx
);
6753 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6754 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6757 switch (dst
.size()) {
6759 op
= aco_opcode::buffer_load_dword
;
6762 op
= aco_opcode::buffer_load_dwordx2
;
6765 op
= aco_opcode::buffer_load_dwordx3
;
6768 op
= aco_opcode::buffer_load_dwordx4
;
6772 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
6773 Temp lower
= bld
.mubuf(aco_opcode::buffer_load_dwordx4
,
6774 bld
.def(v4
), rsrc
, offset
,
6775 ctx
->program
->scratch_offset
, 0, true);
6776 Temp upper
= bld
.mubuf(dst
.size() == 6 ? aco_opcode::buffer_load_dwordx2
:
6777 aco_opcode::buffer_load_dwordx4
,
6778 dst
.size() == 6 ? bld
.def(v2
) : bld
.def(v4
),
6779 rsrc
, offset
, ctx
->program
->scratch_offset
, 16, true);
6780 emit_split_vector(ctx
, lower
, 2);
6781 elems
[0] = emit_extract_vector(ctx
, lower
, 0, v2
);
6782 elems
[1] = emit_extract_vector(ctx
, lower
, 1, v2
);
6783 if (dst
.size() == 8) {
6784 emit_split_vector(ctx
, upper
, 2);
6785 elems
[2] = emit_extract_vector(ctx
, upper
, 0, v2
);
6786 elems
[3] = emit_extract_vector(ctx
, upper
, 1, v2
);
6791 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
6792 Format::PSEUDO
, dst
.size() / 2, 1)};
6793 for (unsigned i
= 0; i
< dst
.size() / 2; i
++)
6794 vec
->operands
[i
] = Operand(elems
[i
]);
6795 vec
->definitions
[0] = Definition(dst
);
6796 bld
.insert(std::move(vec
));
6797 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
6801 unreachable("Wrong dst size for nir_intrinsic_load_scratch");
6804 bld
.mubuf(op
, Definition(dst
), rsrc
, offset
, ctx
->program
->scratch_offset
, 0, true);
6805 emit_split_vector(ctx
, dst
, instr
->num_components
);
6808 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6809 assert(instr
->src
[0].ssa
->bit_size
== 32 || instr
->src
[0].ssa
->bit_size
== 64);
6810 Builder
bld(ctx
->program
, ctx
->block
);
6811 Temp rsrc
= get_scratch_resource(ctx
);
6812 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6813 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6815 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6816 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6820 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
6821 int num_bytes
= count
* elem_size_bytes
;
6823 if (num_bytes
> 16) {
6824 assert(elem_size_bytes
== 8);
6825 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
6830 // TODO: check alignment of sub-dword stores
6831 // TODO: split 3 bytes. there is no store instruction for that
6834 if (count
!= instr
->num_components
) {
6835 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6836 for (int i
= 0; i
< count
; i
++) {
6837 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(RegType::vgpr
, elem_size_bytes
/ 4));
6838 vec
->operands
[i
] = Operand(elem
);
6840 write_data
= bld
.tmp(RegClass(RegType::vgpr
, count
* elem_size_bytes
/ 4));
6841 vec
->definitions
[0] = Definition(write_data
);
6842 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6848 switch (num_bytes
) {
6850 op
= aco_opcode::buffer_store_dword
;
6853 op
= aco_opcode::buffer_store_dwordx2
;
6856 op
= aco_opcode::buffer_store_dwordx3
;
6859 op
= aco_opcode::buffer_store_dwordx4
;
6862 unreachable("Invalid data size for nir_intrinsic_store_scratch.");
6865 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_data
, start
* elem_size_bytes
, true);
6869 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6870 uint8_t log2_ps_iter_samples
;
6871 if (ctx
->program
->info
->ps
.force_persample
) {
6872 log2_ps_iter_samples
=
6873 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6875 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6878 /* The bit pattern matches that used by fixed function fragment
6880 static const unsigned ps_iter_masks
[] = {
6881 0xffff, /* not used */
6887 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6889 Builder
bld(ctx
->program
, ctx
->block
);
6891 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6892 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6893 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6894 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6895 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6896 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6899 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6900 Builder
bld(ctx
->program
, ctx
->block
);
6902 unsigned stream
= nir_intrinsic_stream_id(instr
);
6903 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6904 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6905 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6908 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6910 unsigned num_components
=
6911 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6912 assert(num_components
);
6914 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6915 unsigned stream_offset
= 0;
6916 for (unsigned i
= 0; i
< stream
; i
++) {
6917 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6918 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6921 /* Limit on the stride field for <= GFX7. */
6922 assert(stride
< (1 << 14));
6924 Temp gsvs_dwords
[4];
6925 for (unsigned i
= 0; i
< 4; i
++)
6926 gsvs_dwords
[i
] = bld
.tmp(s1
);
6927 bld
.pseudo(aco_opcode::p_split_vector
,
6928 Definition(gsvs_dwords
[0]),
6929 Definition(gsvs_dwords
[1]),
6930 Definition(gsvs_dwords
[2]),
6931 Definition(gsvs_dwords
[3]),
6934 if (stream_offset
) {
6935 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6937 Temp carry
= bld
.tmp(s1
);
6938 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6939 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6942 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6943 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6945 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6946 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6948 unsigned offset
= 0;
6949 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6950 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6953 for (unsigned j
= 0; j
< 4; j
++) {
6954 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6957 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6958 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6959 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6960 if (const_offset
>= 4096u) {
6961 if (vaddr_offset
.isUndefined())
6962 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6964 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6965 const_offset
%= 4096u;
6968 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6969 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6970 mtbuf
->operands
[1] = vaddr_offset
;
6971 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6972 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6973 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6974 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6975 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6976 mtbuf
->offset
= const_offset
;
6979 mtbuf
->barrier
= barrier_gs_data
;
6980 mtbuf
->can_reorder
= true;
6981 bld
.insert(std::move(mtbuf
));
6984 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6987 /* outputs for the next vertex are undefined and keeping them around can
6988 * create invalid IR with control flow */
6989 ctx
->outputs
.mask
[i
] = 0;
6992 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6995 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6997 Builder
bld(ctx
->program
, ctx
->block
);
6999 if (cluster_size
== 1) {
7001 } if (op
== nir_op_iand
&& cluster_size
== 4) {
7002 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
7003 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7004 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
7005 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
7006 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
7007 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
7008 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
7009 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
7010 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
7011 //subgroupAnd(val) -> (exec & ~val) == 0
7012 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7013 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7014 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
7015 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
7016 //subgroupOr(val) -> (val & exec) != 0
7017 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
7018 return bool_to_vector_condition(ctx
, tmp
);
7019 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
7020 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
7021 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7022 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
7023 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
7024 return bool_to_vector_condition(ctx
, tmp
);
7026 //subgroupClustered{And,Or,Xor}(val, n) ->
7027 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
7028 //cluster_offset = ~(n - 1) & lane_id
7029 //cluster_mask = ((1 << n) - 1)
7030 //subgroupClusteredAnd():
7031 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
7032 //subgroupClusteredOr():
7033 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
7034 //subgroupClusteredXor():
7035 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
7036 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
7037 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
7040 if (op
== nir_op_iand
)
7041 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7043 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7045 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
7047 if (ctx
->program
->chip_class
<= GFX7
)
7048 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
7049 else if (ctx
->program
->wave_size
== 64)
7050 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
7052 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
7053 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7054 if (cluster_mask
!= 0xffffffff)
7055 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
7057 Definition cmp_def
= Definition();
7058 if (op
== nir_op_iand
) {
7059 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
7060 } else if (op
== nir_op_ior
) {
7061 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7062 } else if (op
== nir_op_ixor
) {
7063 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
7064 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
7065 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7067 cmp_def
.setHint(vcc
);
7068 return cmp_def
.getTemp();
7072 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7074 Builder
bld(ctx
->program
, ctx
->block
);
7076 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
7077 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
7078 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
7080 if (op
== nir_op_iand
)
7081 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7083 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7085 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
7086 Temp lo
= lohi
.def(0).getTemp();
7087 Temp hi
= lohi
.def(1).getTemp();
7088 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7090 Definition cmp_def
= Definition();
7091 if (op
== nir_op_iand
)
7092 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7093 else if (op
== nir_op_ior
)
7094 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7095 else if (op
== nir_op_ixor
)
7096 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7097 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7098 cmp_def
.setHint(vcc
);
7099 return cmp_def
.getTemp();
7102 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7104 Builder
bld(ctx
->program
, ctx
->block
);
7106 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7107 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7108 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7109 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7110 if (op
== nir_op_iand
)
7111 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7112 else if (op
== nir_op_ior
)
7113 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7114 else if (op
== nir_op_ixor
)
7115 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7121 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7123 Builder
bld(ctx
->program
, ctx
->block
);
7124 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7125 if (src
.regClass().type() == RegType::vgpr
) {
7126 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7127 } else if (src
.regClass() == s1
) {
7128 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7129 } else if (src
.regClass() == s2
) {
7130 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7132 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7133 nir_print_instr(&instr
->instr
, stderr
);
7134 fprintf(stderr
, "\n");
7138 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7140 Builder
bld(ctx
->program
, ctx
->block
);
7141 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7142 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7143 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7145 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7146 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7147 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7148 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7151 if (ctx
->program
->chip_class
>= GFX8
) {
7152 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7153 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7154 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7155 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7156 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7157 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7159 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7160 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7161 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7162 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7163 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7164 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7165 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7166 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7167 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7168 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7171 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7172 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7173 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7174 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7175 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7176 Temp wqm1
= bld
.tmp(v1
);
7177 emit_wqm(ctx
, tmp1
, wqm1
, true);
7178 Temp wqm2
= bld
.tmp(v1
);
7179 emit_wqm(ctx
, tmp2
, wqm2
, true);
7180 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7184 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7186 Builder
bld(ctx
->program
, ctx
->block
);
7187 switch(instr
->intrinsic
) {
7188 case nir_intrinsic_load_barycentric_sample
:
7189 case nir_intrinsic_load_barycentric_pixel
:
7190 case nir_intrinsic_load_barycentric_centroid
: {
7191 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7192 Temp bary
= Temp(0, s2
);
7194 case INTERP_MODE_SMOOTH
:
7195 case INTERP_MODE_NONE
:
7196 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7197 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7198 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7199 bary
= ctx
->persp_centroid
;
7200 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7201 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7203 case INTERP_MODE_NOPERSPECTIVE
:
7204 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7205 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7206 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7207 bary
= ctx
->linear_centroid
;
7208 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7209 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7214 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7215 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7216 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7217 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7218 Operand(p1
), Operand(p2
));
7219 emit_split_vector(ctx
, dst
, 2);
7222 case nir_intrinsic_load_barycentric_model
: {
7223 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7225 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7226 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7227 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7228 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7229 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7230 Operand(p1
), Operand(p2
), Operand(p3
));
7231 emit_split_vector(ctx
, dst
, 3);
7234 case nir_intrinsic_load_barycentric_at_sample
: {
7235 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7236 switch (ctx
->options
->key
.fs
.num_samples
) {
7237 case 2: sample_pos_offset
+= 1 << 3; break;
7238 case 4: sample_pos_offset
+= 3 << 3; break;
7239 case 8: sample_pos_offset
+= 7 << 3; break;
7243 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7244 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7245 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7246 if (addr
.type() == RegType::sgpr
) {
7249 sample_pos_offset
+= const_addr
->u32
<< 3;
7250 offset
= Operand(sample_pos_offset
);
7251 } else if (ctx
->options
->chip_class
>= GFX9
) {
7252 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7254 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7255 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7258 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7259 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7261 } else if (ctx
->options
->chip_class
>= GFX9
) {
7262 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7263 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7264 } else if (ctx
->options
->chip_class
>= GFX7
) {
7265 /* addr += private_segment_buffer + sample_pos_offset */
7266 Temp tmp0
= bld
.tmp(s1
);
7267 Temp tmp1
= bld
.tmp(s1
);
7268 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7269 Definition scc_tmp
= bld
.def(s1
, scc
);
7270 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7271 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7272 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7273 Temp pck0
= bld
.tmp(v1
);
7274 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7275 tmp1
= as_vgpr(ctx
, tmp1
);
7276 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7277 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7279 /* sample_pos = flat_load_dwordx2 addr */
7280 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7282 assert(ctx
->options
->chip_class
== GFX6
);
7284 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7285 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7286 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7288 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7289 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7291 sample_pos
= bld
.tmp(v2
);
7293 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7294 load
->definitions
[0] = Definition(sample_pos
);
7295 load
->operands
[0] = Operand(rsrc
);
7296 load
->operands
[1] = Operand(addr
);
7297 load
->operands
[2] = Operand(0u);
7298 load
->offset
= sample_pos_offset
;
7300 load
->addr64
= true;
7303 load
->disable_wqm
= false;
7304 load
->barrier
= barrier_none
;
7305 load
->can_reorder
= true;
7306 ctx
->block
->instructions
.emplace_back(std::move(load
));
7309 /* sample_pos -= 0.5 */
7310 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7311 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7312 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7313 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7314 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7316 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7319 case nir_intrinsic_load_barycentric_at_offset
: {
7320 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7321 RegClass rc
= RegClass(offset
.type(), 1);
7322 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7323 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7324 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7327 case nir_intrinsic_load_front_face
: {
7328 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7329 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7332 case nir_intrinsic_load_view_index
: {
7333 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7334 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7335 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7341 case nir_intrinsic_load_layer_id
: {
7342 unsigned idx
= nir_intrinsic_base(instr
);
7343 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7344 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7347 case nir_intrinsic_load_frag_coord
: {
7348 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7351 case nir_intrinsic_load_sample_pos
: {
7352 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7353 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7354 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7355 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7356 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7359 case nir_intrinsic_load_tess_coord
:
7360 visit_load_tess_coord(ctx
, instr
);
7362 case nir_intrinsic_load_interpolated_input
:
7363 visit_load_interpolated_input(ctx
, instr
);
7365 case nir_intrinsic_store_output
:
7366 visit_store_output(ctx
, instr
);
7368 case nir_intrinsic_load_input
:
7369 case nir_intrinsic_load_input_vertex
:
7370 visit_load_input(ctx
, instr
);
7372 case nir_intrinsic_load_output
:
7373 visit_load_output(ctx
, instr
);
7375 case nir_intrinsic_load_per_vertex_input
:
7376 visit_load_per_vertex_input(ctx
, instr
);
7378 case nir_intrinsic_load_per_vertex_output
:
7379 visit_load_per_vertex_output(ctx
, instr
);
7381 case nir_intrinsic_store_per_vertex_output
:
7382 visit_store_per_vertex_output(ctx
, instr
);
7384 case nir_intrinsic_load_ubo
:
7385 visit_load_ubo(ctx
, instr
);
7387 case nir_intrinsic_load_push_constant
:
7388 visit_load_push_constant(ctx
, instr
);
7390 case nir_intrinsic_load_constant
:
7391 visit_load_constant(ctx
, instr
);
7393 case nir_intrinsic_vulkan_resource_index
:
7394 visit_load_resource(ctx
, instr
);
7396 case nir_intrinsic_discard
:
7397 visit_discard(ctx
, instr
);
7399 case nir_intrinsic_discard_if
:
7400 visit_discard_if(ctx
, instr
);
7402 case nir_intrinsic_load_shared
:
7403 visit_load_shared(ctx
, instr
);
7405 case nir_intrinsic_store_shared
:
7406 visit_store_shared(ctx
, instr
);
7408 case nir_intrinsic_shared_atomic_add
:
7409 case nir_intrinsic_shared_atomic_imin
:
7410 case nir_intrinsic_shared_atomic_umin
:
7411 case nir_intrinsic_shared_atomic_imax
:
7412 case nir_intrinsic_shared_atomic_umax
:
7413 case nir_intrinsic_shared_atomic_and
:
7414 case nir_intrinsic_shared_atomic_or
:
7415 case nir_intrinsic_shared_atomic_xor
:
7416 case nir_intrinsic_shared_atomic_exchange
:
7417 case nir_intrinsic_shared_atomic_comp_swap
:
7418 visit_shared_atomic(ctx
, instr
);
7420 case nir_intrinsic_image_deref_load
:
7421 visit_image_load(ctx
, instr
);
7423 case nir_intrinsic_image_deref_store
:
7424 visit_image_store(ctx
, instr
);
7426 case nir_intrinsic_image_deref_atomic_add
:
7427 case nir_intrinsic_image_deref_atomic_umin
:
7428 case nir_intrinsic_image_deref_atomic_imin
:
7429 case nir_intrinsic_image_deref_atomic_umax
:
7430 case nir_intrinsic_image_deref_atomic_imax
:
7431 case nir_intrinsic_image_deref_atomic_and
:
7432 case nir_intrinsic_image_deref_atomic_or
:
7433 case nir_intrinsic_image_deref_atomic_xor
:
7434 case nir_intrinsic_image_deref_atomic_exchange
:
7435 case nir_intrinsic_image_deref_atomic_comp_swap
:
7436 visit_image_atomic(ctx
, instr
);
7438 case nir_intrinsic_image_deref_size
:
7439 visit_image_size(ctx
, instr
);
7441 case nir_intrinsic_load_ssbo
:
7442 visit_load_ssbo(ctx
, instr
);
7444 case nir_intrinsic_store_ssbo
:
7445 visit_store_ssbo(ctx
, instr
);
7447 case nir_intrinsic_load_global
:
7448 visit_load_global(ctx
, instr
);
7450 case nir_intrinsic_store_global
:
7451 visit_store_global(ctx
, instr
);
7453 case nir_intrinsic_global_atomic_add
:
7454 case nir_intrinsic_global_atomic_imin
:
7455 case nir_intrinsic_global_atomic_umin
:
7456 case nir_intrinsic_global_atomic_imax
:
7457 case nir_intrinsic_global_atomic_umax
:
7458 case nir_intrinsic_global_atomic_and
:
7459 case nir_intrinsic_global_atomic_or
:
7460 case nir_intrinsic_global_atomic_xor
:
7461 case nir_intrinsic_global_atomic_exchange
:
7462 case nir_intrinsic_global_atomic_comp_swap
:
7463 visit_global_atomic(ctx
, instr
);
7465 case nir_intrinsic_ssbo_atomic_add
:
7466 case nir_intrinsic_ssbo_atomic_imin
:
7467 case nir_intrinsic_ssbo_atomic_umin
:
7468 case nir_intrinsic_ssbo_atomic_imax
:
7469 case nir_intrinsic_ssbo_atomic_umax
:
7470 case nir_intrinsic_ssbo_atomic_and
:
7471 case nir_intrinsic_ssbo_atomic_or
:
7472 case nir_intrinsic_ssbo_atomic_xor
:
7473 case nir_intrinsic_ssbo_atomic_exchange
:
7474 case nir_intrinsic_ssbo_atomic_comp_swap
:
7475 visit_atomic_ssbo(ctx
, instr
);
7477 case nir_intrinsic_load_scratch
:
7478 visit_load_scratch(ctx
, instr
);
7480 case nir_intrinsic_store_scratch
:
7481 visit_store_scratch(ctx
, instr
);
7483 case nir_intrinsic_get_buffer_size
:
7484 visit_get_buffer_size(ctx
, instr
);
7486 case nir_intrinsic_control_barrier
: {
7487 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7488 /* GFX6 only (thanks to a hw bug workaround):
7489 * The real barrier instruction isn’t needed, because an entire patch
7490 * always fits into a single wave.
7495 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7496 bld
.sopp(aco_opcode::s_barrier
);
7500 case nir_intrinsic_memory_barrier_tcs_patch
:
7501 case nir_intrinsic_group_memory_barrier
:
7502 case nir_intrinsic_memory_barrier
:
7503 case nir_intrinsic_memory_barrier_buffer
:
7504 case nir_intrinsic_memory_barrier_image
:
7505 case nir_intrinsic_memory_barrier_shared
:
7506 emit_memory_barrier(ctx
, instr
);
7508 case nir_intrinsic_load_num_work_groups
: {
7509 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7510 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7511 emit_split_vector(ctx
, dst
, 3);
7514 case nir_intrinsic_load_local_invocation_id
: {
7515 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7516 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7517 emit_split_vector(ctx
, dst
, 3);
7520 case nir_intrinsic_load_work_group_id
: {
7521 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7522 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7523 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7524 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7525 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7526 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7527 emit_split_vector(ctx
, dst
, 3);
7530 case nir_intrinsic_load_local_invocation_index
: {
7531 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7533 /* The tg_size bits [6:11] contain the subgroup id,
7534 * we need this multiplied by the wave size, and then OR the thread id to it.
7536 if (ctx
->program
->wave_size
== 64) {
7537 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7538 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7539 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7540 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7542 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7543 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7544 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7545 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7549 case nir_intrinsic_load_subgroup_id
: {
7550 if (ctx
->stage
== compute_cs
) {
7551 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7552 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7554 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7558 case nir_intrinsic_load_subgroup_invocation
: {
7559 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7562 case nir_intrinsic_load_num_subgroups
: {
7563 if (ctx
->stage
== compute_cs
)
7564 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7565 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7567 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7570 case nir_intrinsic_ballot
: {
7571 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7572 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7573 Definition tmp
= bld
.def(dst
.regClass());
7574 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7575 if (instr
->src
[0].ssa
->bit_size
== 1) {
7576 assert(src
.regClass() == bld
.lm
);
7577 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7578 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7579 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7580 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7581 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7583 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7584 nir_print_instr(&instr
->instr
, stderr
);
7585 fprintf(stderr
, "\n");
7587 if (dst
.size() != bld
.lm
.size()) {
7588 /* Wave32 with ballot size set to 64 */
7589 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7591 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7594 case nir_intrinsic_shuffle
:
7595 case nir_intrinsic_read_invocation
: {
7596 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7597 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
]) {
7598 emit_uniform_subgroup(ctx
, instr
, src
);
7600 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7601 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !ctx
->divergent_vals
[instr
->src
[1].ssa
->index
])
7602 tid
= bld
.as_uniform(tid
);
7603 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7604 if (src
.regClass() == v1
) {
7605 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7606 } else if (src
.regClass() == v2
) {
7607 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7608 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7609 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7610 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7611 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7612 emit_split_vector(ctx
, dst
, 2);
7613 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7614 assert(src
.regClass() == bld
.lm
);
7615 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7616 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7617 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7618 assert(src
.regClass() == bld
.lm
);
7620 if (ctx
->program
->chip_class
<= GFX7
)
7621 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7622 else if (ctx
->program
->wave_size
== 64)
7623 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7625 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7626 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7627 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7628 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7630 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7631 nir_print_instr(&instr
->instr
, stderr
);
7632 fprintf(stderr
, "\n");
7637 case nir_intrinsic_load_sample_id
: {
7638 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7639 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7642 case nir_intrinsic_load_sample_mask_in
: {
7643 visit_load_sample_mask_in(ctx
, instr
);
7646 case nir_intrinsic_read_first_invocation
: {
7647 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7648 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7649 if (src
.regClass() == v1
) {
7651 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7653 } else if (src
.regClass() == v2
) {
7654 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7655 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7656 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7657 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7658 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7659 emit_split_vector(ctx
, dst
, 2);
7660 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7661 assert(src
.regClass() == bld
.lm
);
7662 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7663 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7664 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7665 } else if (src
.regClass() == s1
) {
7666 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7667 } else if (src
.regClass() == s2
) {
7668 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7670 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7671 nir_print_instr(&instr
->instr
, stderr
);
7672 fprintf(stderr
, "\n");
7676 case nir_intrinsic_vote_all
: {
7677 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7678 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7679 assert(src
.regClass() == bld
.lm
);
7680 assert(dst
.regClass() == bld
.lm
);
7682 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7683 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7684 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7687 case nir_intrinsic_vote_any
: {
7688 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7689 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7690 assert(src
.regClass() == bld
.lm
);
7691 assert(dst
.regClass() == bld
.lm
);
7693 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7694 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7697 case nir_intrinsic_reduce
:
7698 case nir_intrinsic_inclusive_scan
:
7699 case nir_intrinsic_exclusive_scan
: {
7700 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7701 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7702 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7703 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7704 nir_intrinsic_cluster_size(instr
) : 0;
7705 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7707 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
] && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7708 emit_uniform_subgroup(ctx
, instr
, src
);
7709 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7710 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7712 else if (op
== nir_op_iadd
)
7714 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7716 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7718 switch (instr
->intrinsic
) {
7719 case nir_intrinsic_reduce
:
7720 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7722 case nir_intrinsic_exclusive_scan
:
7723 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7725 case nir_intrinsic_inclusive_scan
:
7726 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7731 } else if (cluster_size
== 1) {
7732 bld
.copy(Definition(dst
), src
);
7734 src
= as_vgpr(ctx
, src
);
7738 #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
7753 unreachable("unknown reduction op");
7758 switch (instr
->intrinsic
) {
7759 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7760 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7761 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7763 unreachable("unknown reduce intrinsic");
7766 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7767 reduce
->operands
[0] = Operand(src
);
7768 // filled in by aco_reduce_assign.cpp, used internally as part of the
7770 assert(dst
.size() == 1 || dst
.size() == 2);
7771 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7772 reduce
->operands
[2] = Operand(v1
.as_linear());
7774 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7775 reduce
->definitions
[0] = Definition(tmp_dst
);
7776 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7777 reduce
->definitions
[2] = Definition();
7778 reduce
->definitions
[3] = Definition(scc
, s1
);
7779 reduce
->definitions
[4] = Definition();
7780 reduce
->reduce_op
= reduce_op
;
7781 reduce
->cluster_size
= cluster_size
;
7782 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7784 emit_wqm(ctx
, tmp_dst
, dst
);
7788 case nir_intrinsic_quad_broadcast
: {
7789 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7790 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7791 emit_uniform_subgroup(ctx
, instr
, src
);
7793 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7794 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7795 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7797 if (instr
->dest
.ssa
.bit_size
== 1) {
7798 assert(src
.regClass() == bld
.lm
);
7799 assert(dst
.regClass() == bld
.lm
);
7800 uint32_t half_mask
= 0x11111111u
<< lane
;
7801 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7802 Temp tmp
= bld
.tmp(bld
.lm
);
7803 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7804 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7805 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7806 emit_wqm(ctx
, tmp
, dst
);
7807 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7808 if (ctx
->program
->chip_class
>= GFX8
)
7809 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7811 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7812 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7813 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7814 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7815 if (ctx
->program
->chip_class
>= GFX8
) {
7816 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7817 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7819 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7820 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7822 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7823 emit_split_vector(ctx
, dst
, 2);
7825 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7826 nir_print_instr(&instr
->instr
, stderr
);
7827 fprintf(stderr
, "\n");
7832 case nir_intrinsic_quad_swap_horizontal
:
7833 case nir_intrinsic_quad_swap_vertical
:
7834 case nir_intrinsic_quad_swap_diagonal
:
7835 case nir_intrinsic_quad_swizzle_amd
: {
7836 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7837 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7838 emit_uniform_subgroup(ctx
, instr
, src
);
7841 uint16_t dpp_ctrl
= 0;
7842 switch (instr
->intrinsic
) {
7843 case nir_intrinsic_quad_swap_horizontal
:
7844 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7846 case nir_intrinsic_quad_swap_vertical
:
7847 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7849 case nir_intrinsic_quad_swap_diagonal
:
7850 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7852 case nir_intrinsic_quad_swizzle_amd
:
7853 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7858 if (ctx
->program
->chip_class
< GFX8
)
7859 dpp_ctrl
|= (1 << 15);
7861 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7862 if (instr
->dest
.ssa
.bit_size
== 1) {
7863 assert(src
.regClass() == bld
.lm
);
7864 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7865 if (ctx
->program
->chip_class
>= GFX8
)
7866 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7868 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7869 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7870 emit_wqm(ctx
, tmp
, dst
);
7871 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7873 if (ctx
->program
->chip_class
>= GFX8
)
7874 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7876 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7877 emit_wqm(ctx
, tmp
, dst
);
7878 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7879 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7880 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7881 if (ctx
->program
->chip_class
>= GFX8
) {
7882 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7883 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7885 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7886 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7888 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7889 emit_split_vector(ctx
, dst
, 2);
7891 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7892 nir_print_instr(&instr
->instr
, stderr
);
7893 fprintf(stderr
, "\n");
7897 case nir_intrinsic_masked_swizzle_amd
: {
7898 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7899 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7900 emit_uniform_subgroup(ctx
, instr
, src
);
7903 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7904 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7905 if (dst
.regClass() == v1
) {
7907 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
7909 } else if (dst
.regClass() == v2
) {
7910 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7911 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7912 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
7913 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
7914 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7915 emit_split_vector(ctx
, dst
, 2);
7917 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7918 nir_print_instr(&instr
->instr
, stderr
);
7919 fprintf(stderr
, "\n");
7923 case nir_intrinsic_write_invocation_amd
: {
7924 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7925 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7926 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7927 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7928 if (dst
.regClass() == v1
) {
7929 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7930 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7931 } else if (dst
.regClass() == v2
) {
7932 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7933 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7934 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7935 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7936 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7937 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7938 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7939 emit_split_vector(ctx
, dst
, 2);
7941 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7942 nir_print_instr(&instr
->instr
, stderr
);
7943 fprintf(stderr
, "\n");
7947 case nir_intrinsic_mbcnt_amd
: {
7948 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7949 RegClass rc
= RegClass(src
.type(), 1);
7950 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7951 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7952 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7953 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7954 emit_wqm(ctx
, wqm_tmp
, dst
);
7957 case nir_intrinsic_load_helper_invocation
: {
7958 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7959 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7960 ctx
->block
->kind
|= block_kind_needs_lowering
;
7961 ctx
->program
->needs_exact
= true;
7964 case nir_intrinsic_is_helper_invocation
: {
7965 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7966 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7967 ctx
->block
->kind
|= block_kind_needs_lowering
;
7968 ctx
->program
->needs_exact
= true;
7971 case nir_intrinsic_demote
:
7972 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7974 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7975 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7976 ctx
->block
->kind
|= block_kind_uses_demote
;
7977 ctx
->program
->needs_exact
= true;
7979 case nir_intrinsic_demote_if
: {
7980 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7981 assert(src
.regClass() == bld
.lm
);
7982 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7983 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
7985 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7986 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7987 ctx
->block
->kind
|= block_kind_uses_demote
;
7988 ctx
->program
->needs_exact
= true;
7991 case nir_intrinsic_first_invocation
: {
7992 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
7993 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7996 case nir_intrinsic_shader_clock
:
7997 bld
.smem(aco_opcode::s_memtime
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
7998 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
8000 case nir_intrinsic_load_vertex_id_zero_base
: {
8001 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8002 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
8005 case nir_intrinsic_load_first_vertex
: {
8006 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8007 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
8010 case nir_intrinsic_load_base_instance
: {
8011 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8012 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
8015 case nir_intrinsic_load_instance_id
: {
8016 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8017 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
8020 case nir_intrinsic_load_draw_id
: {
8021 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8022 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
8025 case nir_intrinsic_load_invocation_id
: {
8026 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8028 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
8029 if (ctx
->options
->chip_class
>= GFX10
)
8030 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8032 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8033 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
8034 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
8035 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
8037 unreachable("Unsupported stage for load_invocation_id");
8042 case nir_intrinsic_load_primitive_id
: {
8043 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8045 switch (ctx
->shader
->info
.stage
) {
8046 case MESA_SHADER_GEOMETRY
:
8047 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
8049 case MESA_SHADER_TESS_CTRL
:
8050 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
8052 case MESA_SHADER_TESS_EVAL
:
8053 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
8056 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
8061 case nir_intrinsic_load_patch_vertices_in
: {
8062 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
8063 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8065 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8066 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8069 case nir_intrinsic_emit_vertex_with_counter
: {
8070 visit_emit_vertex_with_counter(ctx
, instr
);
8073 case nir_intrinsic_end_primitive_with_counter
: {
8074 unsigned stream
= nir_intrinsic_stream_id(instr
);
8075 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8078 case nir_intrinsic_set_vertex_count
: {
8079 /* unused, the HW keeps track of this for us */
8083 fprintf(stderr
, "Unimplemented intrinsic instr: ");
8084 nir_print_instr(&instr
->instr
, stderr
);
8085 fprintf(stderr
, "\n");
8093 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8094 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8095 enum glsl_base_type
*stype
)
8097 nir_deref_instr
*texture_deref_instr
= NULL
;
8098 nir_deref_instr
*sampler_deref_instr
= NULL
;
8101 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8102 switch (instr
->src
[i
].src_type
) {
8103 case nir_tex_src_texture_deref
:
8104 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8106 case nir_tex_src_sampler_deref
:
8107 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8109 case nir_tex_src_plane
:
8110 plane
= nir_src_as_int(instr
->src
[i
].src
);
8117 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8119 if (!sampler_deref_instr
)
8120 sampler_deref_instr
= texture_deref_instr
;
8123 assert(instr
->op
!= nir_texop_txf_ms
&&
8124 instr
->op
!= nir_texop_samples_identical
);
8125 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8126 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8127 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8128 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8129 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8130 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8132 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8135 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8137 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8138 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8139 Builder
bld(ctx
->program
, ctx
->block
);
8141 /* to avoid unnecessary moves, we split and recombine sampler and image */
8142 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8143 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8144 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8145 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8146 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8147 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8148 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8149 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8151 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8152 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8153 img
[0], img
[1], img
[2], img
[3],
8154 img
[4], img
[5], img
[6], img
[7]);
8155 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8156 samp
[0], samp
[1], samp
[2], samp
[3]);
8159 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8160 instr
->op
== nir_texop_samples_identical
))
8161 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8164 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8165 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8167 Builder
bld(ctx
->program
, ctx
->block
);
8169 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8170 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8171 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8173 Operand
neg_one(0xbf800000u
);
8174 Operand
one(0x3f800000u
);
8175 Operand
two(0x40000000u
);
8176 Operand
four(0x40800000u
);
8178 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8179 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8180 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8182 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8183 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8184 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8185 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8188 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8189 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8190 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8192 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8195 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8196 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8197 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8200 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8201 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8203 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8204 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8207 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8209 Builder
bld(ctx
->program
, ctx
->block
);
8210 Temp ma
, tc
, sc
, id
;
8213 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8215 // see comment in ac_prepare_cube_coords()
8216 if (ctx
->options
->chip_class
<= GFX8
)
8217 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8220 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8222 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8223 vop3a
->operands
[0] = Operand(ma
);
8224 vop3a
->abs
[0] = true;
8225 Temp invma
= bld
.tmp(v1
);
8226 vop3a
->definitions
[0] = Definition(invma
);
8227 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8229 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8231 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8233 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8235 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8237 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8240 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8241 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8243 for (unsigned i
= 0; i
< 2; i
++) {
8244 // see comment in ac_prepare_cube_coords()
8246 Temp deriv_sc
, deriv_tc
;
8247 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8248 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8250 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8252 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8253 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8254 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8255 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8256 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8257 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8258 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8261 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8262 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8266 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8273 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8275 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8277 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8278 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8281 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8282 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8283 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8287 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8289 Builder
bld(ctx
->program
, ctx
->block
);
8290 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8291 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false;
8292 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8293 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp();
8294 std::vector
<Temp
> coords
;
8295 std::vector
<Temp
> derivs
;
8296 nir_const_value
*sample_index_cv
= NULL
;
8297 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8298 enum glsl_base_type stype
;
8299 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8301 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8302 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8303 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8304 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8306 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8307 switch (instr
->src
[i
].src_type
) {
8308 case nir_tex_src_coord
: {
8309 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8310 for (unsigned i
= 0; i
< coord
.size(); i
++)
8311 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8314 case nir_tex_src_bias
:
8315 if (instr
->op
== nir_texop_txb
) {
8316 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8320 case nir_tex_src_lod
: {
8321 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8323 if (val
&& val
->f32
<= 0.0) {
8326 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8331 case nir_tex_src_comparator
:
8332 if (instr
->is_shadow
) {
8333 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8337 case nir_tex_src_offset
:
8338 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8339 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8342 case nir_tex_src_ddx
:
8343 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8346 case nir_tex_src_ddy
:
8347 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8350 case nir_tex_src_ms_index
:
8351 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8352 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8353 has_sample_index
= true;
8355 case nir_tex_src_texture_offset
:
8356 case nir_tex_src_sampler_offset
:
8362 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8363 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8365 if (instr
->op
== nir_texop_texture_samples
) {
8366 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8368 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8369 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8370 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8371 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8373 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8374 samples
, Operand(1u), bld
.scc(is_msaa
));
8378 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8379 aco_ptr
<Instruction
> tmp_instr
;
8380 Temp acc
, pack
= Temp();
8382 uint32_t pack_const
= 0;
8383 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8384 if (!const_offset
[i
])
8386 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8389 if (offset
.type() == RegType::sgpr
) {
8390 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8391 if (const_offset
[i
])
8394 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8395 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8398 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8401 if (pack
== Temp()) {
8404 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8408 if (pack_const
&& pack
!= Temp())
8409 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8411 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8412 if (const_offset
[i
])
8415 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8416 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8419 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8422 if (pack
== Temp()) {
8425 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8429 if (pack_const
&& pack
!= Temp())
8430 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8432 if (pack_const
&& pack
== Temp())
8433 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8434 else if (pack
== Temp())
8440 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8441 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8443 /* pack derivatives */
8444 if (has_ddx
|| has_ddy
) {
8445 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8446 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8447 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8448 derivs
= {ddy
, zero
, ddy
, zero
};
8450 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8451 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8452 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8453 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8458 if (instr
->coord_components
> 1 &&
8459 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8461 instr
->op
!= nir_texop_txf
)
8462 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8464 if (instr
->coord_components
> 2 &&
8465 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8466 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8467 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8468 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8470 instr
->op
!= nir_texop_txf
&&
8471 instr
->op
!= nir_texop_txf_ms
&&
8472 instr
->op
!= nir_texop_fragment_fetch
&&
8473 instr
->op
!= nir_texop_fragment_mask_fetch
)
8474 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8476 if (ctx
->options
->chip_class
== GFX9
&&
8477 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8478 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8479 assert(coords
.size() > 0 && coords
.size() < 3);
8481 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8482 Operand((uint32_t) 0) :
8483 Operand((uint32_t) 0x3f000000)));
8486 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8488 if (instr
->op
== nir_texop_samples_identical
)
8489 resource
= fmask_ptr
;
8491 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8492 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8493 instr
->op
!= nir_texop_txs
&&
8494 instr
->op
!= nir_texop_fragment_fetch
&&
8495 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8496 assert(has_sample_index
);
8497 Operand
op(sample_index
);
8498 if (sample_index_cv
)
8499 op
= Operand(sample_index_cv
->u32
);
8500 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8503 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8504 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8505 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8506 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8511 /* Build tex instruction */
8512 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8513 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8514 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8516 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8519 /* gather4 selects the component by dmask and always returns vec4 */
8520 if (instr
->op
== nir_texop_tg4
) {
8521 assert(instr
->dest
.ssa
.num_components
== 4);
8522 if (instr
->is_shadow
)
8525 dmask
= 1 << instr
->component
;
8526 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8527 tmp_dst
= bld
.tmp(v4
);
8528 } else if (instr
->op
== nir_texop_samples_identical
) {
8529 tmp_dst
= bld
.tmp(v1
);
8530 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8531 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8534 aco_ptr
<MIMG_instruction
> tex
;
8535 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8537 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8539 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8540 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8543 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8544 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8546 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8547 tex
->operands
[0] = Operand(resource
);
8548 tex
->operands
[1] = Operand(s4
); /* no sampler */
8549 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8550 if (ctx
->options
->chip_class
== GFX9
&&
8551 instr
->op
== nir_texop_txs
&&
8552 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8554 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8555 } else if (instr
->op
== nir_texop_query_levels
) {
8556 tex
->dmask
= 1 << 3;
8561 tex
->definitions
[0] = Definition(tmp_dst
);
8563 tex
->can_reorder
= true;
8564 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8567 /* divide 3rd value by 6 by multiplying with magic number */
8568 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8569 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8570 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8571 assert(instr
->dest
.ssa
.num_components
== 3);
8572 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8573 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8574 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8575 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8580 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8584 Temp tg4_compare_cube_wa64
= Temp();
8586 if (tg4_integer_workarounds
) {
8587 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8588 tex
->operands
[0] = Operand(resource
);
8589 tex
->operands
[1] = Operand(s4
); /* no sampler */
8590 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8594 Temp size
= bld
.tmp(v2
);
8595 tex
->definitions
[0] = Definition(size
);
8596 tex
->can_reorder
= true;
8597 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8598 emit_split_vector(ctx
, size
, size
.size());
8601 for (unsigned i
= 0; i
< 2; i
++) {
8602 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8603 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8604 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8605 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8608 Temp new_coords
[2] = {
8609 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8610 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8613 if (tg4_integer_cube_workaround
) {
8614 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8615 Temp desc
[resource
.size()];
8616 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8617 Format::PSEUDO
, 1, resource
.size())};
8618 split
->operands
[0] = Operand(resource
);
8619 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8620 desc
[i
] = bld
.tmp(s1
);
8621 split
->definitions
[i
] = Definition(desc
[i
]);
8623 ctx
->block
->instructions
.emplace_back(std::move(split
));
8625 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8626 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8627 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8630 if (stype
== GLSL_TYPE_UINT
) {
8631 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8632 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8633 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8634 bld
.scc(compare_cube_wa
));
8636 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8637 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8638 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8639 bld
.scc(compare_cube_wa
));
8641 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8642 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8644 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8646 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8647 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8648 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8650 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8651 Format::PSEUDO
, resource
.size(), 1)};
8652 for (unsigned i
= 0; i
< resource
.size(); i
++)
8653 vec
->operands
[i
] = Operand(desc
[i
]);
8654 resource
= bld
.tmp(resource
.regClass());
8655 vec
->definitions
[0] = Definition(resource
);
8656 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8658 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8659 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8660 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8661 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8663 coords
[0] = new_coords
[0];
8664 coords
[1] = new_coords
[1];
8667 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8668 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8670 assert(coords
.size() == 1);
8671 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8675 op
= aco_opcode::buffer_load_format_x
; break;
8677 op
= aco_opcode::buffer_load_format_xy
; break;
8679 op
= aco_opcode::buffer_load_format_xyz
; break;
8681 op
= aco_opcode::buffer_load_format_xyzw
; break;
8683 unreachable("Tex instruction loads more than 4 components.");
8686 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8687 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8690 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8692 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8693 mubuf
->operands
[0] = Operand(resource
);
8694 mubuf
->operands
[1] = Operand(coords
[0]);
8695 mubuf
->operands
[2] = Operand((uint32_t) 0);
8696 mubuf
->definitions
[0] = Definition(tmp_dst
);
8697 mubuf
->idxen
= true;
8698 mubuf
->can_reorder
= true;
8699 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8701 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8705 /* gather MIMG address components */
8706 std::vector
<Temp
> args
;
8708 args
.emplace_back(offset
);
8710 args
.emplace_back(bias
);
8712 args
.emplace_back(compare
);
8714 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8716 args
.insert(args
.end(), coords
.begin(), coords
.end());
8717 if (has_sample_index
)
8718 args
.emplace_back(sample_index
);
8720 args
.emplace_back(lod
);
8722 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8723 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8724 vec
->definitions
[0] = Definition(arg
);
8725 for (unsigned i
= 0; i
< args
.size(); i
++)
8726 vec
->operands
[i
] = Operand(args
[i
]);
8727 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8730 if (instr
->op
== nir_texop_txf
||
8731 instr
->op
== nir_texop_txf_ms
||
8732 instr
->op
== nir_texop_samples_identical
||
8733 instr
->op
== nir_texop_fragment_fetch
||
8734 instr
->op
== nir_texop_fragment_mask_fetch
) {
8735 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8736 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8737 tex
->operands
[0] = Operand(resource
);
8738 tex
->operands
[1] = Operand(s4
); /* no sampler */
8739 tex
->operands
[2] = Operand(arg
);
8744 tex
->definitions
[0] = Definition(tmp_dst
);
8745 tex
->can_reorder
= true;
8746 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8748 if (instr
->op
== nir_texop_samples_identical
) {
8749 assert(dmask
== 1 && dst
.regClass() == v1
);
8750 assert(dst
.id() != tmp_dst
.id());
8752 Temp tmp
= bld
.tmp(bld
.lm
);
8753 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8754 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8757 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8762 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8763 aco_opcode opcode
= aco_opcode::image_sample
;
8764 if (has_offset
) { /* image_sample_*_o */
8766 opcode
= aco_opcode::image_sample_c_o
;
8768 opcode
= aco_opcode::image_sample_c_d_o
;
8770 opcode
= aco_opcode::image_sample_c_b_o
;
8772 opcode
= aco_opcode::image_sample_c_lz_o
;
8774 opcode
= aco_opcode::image_sample_c_l_o
;
8776 opcode
= aco_opcode::image_sample_o
;
8778 opcode
= aco_opcode::image_sample_d_o
;
8780 opcode
= aco_opcode::image_sample_b_o
;
8782 opcode
= aco_opcode::image_sample_lz_o
;
8784 opcode
= aco_opcode::image_sample_l_o
;
8786 } else { /* no offset */
8788 opcode
= aco_opcode::image_sample_c
;
8790 opcode
= aco_opcode::image_sample_c_d
;
8792 opcode
= aco_opcode::image_sample_c_b
;
8794 opcode
= aco_opcode::image_sample_c_lz
;
8796 opcode
= aco_opcode::image_sample_c_l
;
8798 opcode
= aco_opcode::image_sample
;
8800 opcode
= aco_opcode::image_sample_d
;
8802 opcode
= aco_opcode::image_sample_b
;
8804 opcode
= aco_opcode::image_sample_lz
;
8806 opcode
= aco_opcode::image_sample_l
;
8810 if (instr
->op
== nir_texop_tg4
) {
8812 opcode
= aco_opcode::image_gather4_lz_o
;
8814 opcode
= aco_opcode::image_gather4_c_lz_o
;
8816 opcode
= aco_opcode::image_gather4_lz
;
8818 opcode
= aco_opcode::image_gather4_c_lz
;
8820 } else if (instr
->op
== nir_texop_lod
) {
8821 opcode
= aco_opcode::image_get_lod
;
8824 /* we don't need the bias, sample index, compare value or offset to be
8825 * computed in WQM but if the p_create_vector copies the coordinates, then it
8826 * needs to be in WQM */
8827 if (ctx
->stage
== fragment_fs
&&
8828 !has_derivs
&& !has_lod
&& !level_zero
&&
8829 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8830 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8831 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8833 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8834 tex
->operands
[0] = Operand(resource
);
8835 tex
->operands
[1] = Operand(sampler
);
8836 tex
->operands
[2] = Operand(arg
);
8840 tex
->definitions
[0] = Definition(tmp_dst
);
8841 tex
->can_reorder
= true;
8842 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8844 if (tg4_integer_cube_workaround
) {
8845 assert(tmp_dst
.id() != dst
.id());
8846 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8848 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8850 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8851 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8853 if (stype
== GLSL_TYPE_UINT
)
8854 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8856 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8857 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8859 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8860 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8861 val
[0], val
[1], val
[2], val
[3]);
8863 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8864 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8869 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
)
8871 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8872 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
8873 return Operand(tmp
.regClass());
8875 return Operand(tmp
);
8878 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8880 aco_ptr
<Pseudo_instruction
> phi
;
8881 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8882 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8884 bool logical
= !dst
.is_linear() || ctx
->divergent_vals
[instr
->dest
.ssa
.index
];
8885 logical
|= ctx
->block
->kind
& block_kind_merge
;
8886 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8888 /* we want a sorted list of sources, since the predecessor list is also sorted */
8889 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8890 nir_foreach_phi_src(src
, instr
)
8891 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8893 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8894 unsigned num_operands
= 0;
8895 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8896 unsigned num_defined
= 0;
8897 unsigned cur_pred_idx
= 0;
8898 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8899 if (cur_pred_idx
< preds
.size()) {
8900 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8901 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8902 unsigned skipped
= 0;
8903 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8905 if (cur_pred_idx
+ skipped
< preds
.size()) {
8906 for (unsigned i
= 0; i
< skipped
; i
++)
8907 operands
[num_operands
++] = Operand(dst
.regClass());
8908 cur_pred_idx
+= skipped
;
8913 /* Handle missing predecessors at the end. This shouldn't happen with loop
8914 * headers and we can't ignore these sources for loop header phis. */
8915 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8918 Operand op
= get_phi_operand(ctx
, src
.second
);
8919 operands
[num_operands
++] = op
;
8920 num_defined
+= !op
.isUndefined();
8922 /* handle block_kind_continue_or_break at loop exit blocks */
8923 while (cur_pred_idx
++ < preds
.size())
8924 operands
[num_operands
++] = Operand(dst
.regClass());
8926 /* If the loop ends with a break, still add a linear continue edge in case
8927 * that break is divergent or continue_or_break is used. We'll either remove
8928 * this operand later in visit_loop() if it's not necessary or replace the
8929 * undef with something correct. */
8930 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
8931 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
8932 nir_block
*last
= nir_loop_last_block(loop
);
8933 if (last
->successors
[0] != instr
->instr
.block
)
8934 operands
[num_operands
++] = Operand(RegClass());
8937 if (num_defined
== 0) {
8938 Builder
bld(ctx
->program
, ctx
->block
);
8939 if (dst
.regClass() == s1
) {
8940 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
8941 } else if (dst
.regClass() == v1
) {
8942 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
8944 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8945 for (unsigned i
= 0; i
< dst
.size(); i
++)
8946 vec
->operands
[i
] = Operand(0u);
8947 vec
->definitions
[0] = Definition(dst
);
8948 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8953 /* we can use a linear phi in some cases if one src is undef */
8954 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
8955 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
8957 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
8958 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
8959 assert(invert
->kind
& block_kind_invert
);
8961 unsigned then_block
= invert
->linear_preds
[0];
8963 Block
* insert_block
= NULL
;
8964 for (unsigned i
= 0; i
< num_operands
; i
++) {
8965 Operand op
= operands
[i
];
8966 if (op
.isUndefined())
8968 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
8969 phi
->operands
[0] = op
;
8972 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
8973 phi
->operands
[1] = Operand(dst
.regClass());
8974 phi
->definitions
[0] = Definition(dst
);
8975 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
8979 /* try to scalarize vector phis */
8980 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
8981 // TODO: scalarize linear phis on divergent ifs
8982 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
8983 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
8984 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
8985 Operand src
= operands
[i
];
8986 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
8987 can_scalarize
= false;
8989 if (can_scalarize
) {
8990 unsigned num_components
= instr
->dest
.ssa
.num_components
;
8991 assert(dst
.size() % num_components
== 0);
8992 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
8994 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
8995 for (unsigned k
= 0; k
< num_components
; k
++) {
8996 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8997 for (unsigned i
= 0; i
< num_operands
; i
++) {
8998 Operand src
= operands
[i
];
8999 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
9001 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
9002 phi
->definitions
[0] = Definition(phi_dst
);
9003 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9004 new_vec
[k
] = phi_dst
;
9005 vec
->operands
[k
] = Operand(phi_dst
);
9007 vec
->definitions
[0] = Definition(dst
);
9008 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9009 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
9014 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9015 for (unsigned i
= 0; i
< num_operands
; i
++)
9016 phi
->operands
[i
] = operands
[i
];
9017 phi
->definitions
[0] = Definition(dst
);
9018 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9022 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
9024 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
9026 assert(dst
.type() == RegType::sgpr
);
9028 if (dst
.size() == 1) {
9029 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
9031 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9032 for (unsigned i
= 0; i
< dst
.size(); i
++)
9033 vec
->operands
[i
] = Operand(0u);
9034 vec
->definitions
[0] = Definition(dst
);
9035 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9039 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
9041 Builder
bld(ctx
->program
, ctx
->block
);
9042 Block
*logical_target
;
9043 append_logical_end(ctx
->block
);
9044 unsigned idx
= ctx
->block
->index
;
9046 switch (instr
->type
) {
9047 case nir_jump_break
:
9048 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
9049 add_logical_edge(idx
, logical_target
);
9050 ctx
->block
->kind
|= block_kind_break
;
9052 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
9053 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
9054 /* uniform break - directly jump out of the loop */
9055 ctx
->block
->kind
|= block_kind_uniform
;
9056 ctx
->cf_info
.has_branch
= true;
9057 bld
.branch(aco_opcode::p_branch
);
9058 add_linear_edge(idx
, logical_target
);
9061 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9062 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9064 case nir_jump_continue
:
9065 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9066 add_logical_edge(idx
, logical_target
);
9067 ctx
->block
->kind
|= block_kind_continue
;
9069 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9070 /* for potential uniform breaks after this continue,
9071 we must ensure that they are handled correctly */
9072 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9073 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9074 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9076 /* uniform continue - directly jump to the loop header */
9077 ctx
->block
->kind
|= block_kind_uniform
;
9078 ctx
->cf_info
.has_branch
= true;
9079 bld
.branch(aco_opcode::p_branch
);
9080 add_linear_edge(idx
, logical_target
);
9085 fprintf(stderr
, "Unknown NIR jump instr: ");
9086 nir_print_instr(&instr
->instr
, stderr
);
9087 fprintf(stderr
, "\n");
9091 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9092 ctx
->cf_info
.exec_potentially_empty_break
= true;
9093 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9096 /* remove critical edges from linear CFG */
9097 bld
.branch(aco_opcode::p_branch
);
9098 Block
* break_block
= ctx
->program
->create_and_insert_block();
9099 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9100 break_block
->kind
|= block_kind_uniform
;
9101 add_linear_edge(idx
, break_block
);
9102 /* the loop_header pointer might be invalidated by this point */
9103 if (instr
->type
== nir_jump_continue
)
9104 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9105 add_linear_edge(break_block
->index
, logical_target
);
9106 bld
.reset(break_block
);
9107 bld
.branch(aco_opcode::p_branch
);
9109 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9110 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9111 add_linear_edge(idx
, continue_block
);
9112 append_logical_start(continue_block
);
9113 ctx
->block
= continue_block
;
9117 void visit_block(isel_context
*ctx
, nir_block
*block
)
9119 nir_foreach_instr(instr
, block
) {
9120 switch (instr
->type
) {
9121 case nir_instr_type_alu
:
9122 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9124 case nir_instr_type_load_const
:
9125 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9127 case nir_instr_type_intrinsic
:
9128 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9130 case nir_instr_type_tex
:
9131 visit_tex(ctx
, nir_instr_as_tex(instr
));
9133 case nir_instr_type_phi
:
9134 visit_phi(ctx
, nir_instr_as_phi(instr
));
9136 case nir_instr_type_ssa_undef
:
9137 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9139 case nir_instr_type_deref
:
9141 case nir_instr_type_jump
:
9142 visit_jump(ctx
, nir_instr_as_jump(instr
));
9145 fprintf(stderr
, "Unknown NIR instr type: ");
9146 nir_print_instr(instr
, stderr
);
9147 fprintf(stderr
, "\n");
9152 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9153 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9158 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9159 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9161 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9162 RegClass rc
= vals
[0].regClass();
9164 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9166 unsigned next_pred
= 1;
9168 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9169 Block
& block
= ctx
->program
->blocks
[idx
];
9170 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9171 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9175 if (block
.kind
& block_kind_continue
) {
9176 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9181 bool all_same
= true;
9182 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9183 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9187 val
= vals
[block
.linear_preds
[0] - first
];
9189 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9190 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9191 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9192 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9193 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9194 phi
->definitions
[0] = Definition(val
.getTemp());
9195 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9197 vals
[idx
- first
] = val
;
9200 return vals
[last
- first
];
9203 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9205 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9206 append_logical_end(ctx
->block
);
9207 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9208 Builder
bld(ctx
->program
, ctx
->block
);
9209 bld
.branch(aco_opcode::p_branch
);
9210 unsigned loop_preheader_idx
= ctx
->block
->index
;
9212 Block loop_exit
= Block();
9213 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9214 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9216 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9217 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9218 loop_header
->kind
|= block_kind_loop_header
;
9219 add_edge(loop_preheader_idx
, loop_header
);
9220 ctx
->block
= loop_header
;
9222 /* emit loop body */
9223 unsigned loop_header_idx
= loop_header
->index
;
9224 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9225 append_logical_start(ctx
->block
);
9226 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9228 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9229 if (!ctx
->cf_info
.has_branch
) {
9230 append_logical_end(ctx
->block
);
9231 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9232 /* Discards can result in code running with an empty exec mask.
9233 * This would result in divergent breaks not ever being taken. As a
9234 * workaround, break the loop when the loop mask is empty instead of
9235 * always continuing. */
9236 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9237 unsigned block_idx
= ctx
->block
->index
;
9239 /* create helper blocks to avoid critical edges */
9240 Block
*break_block
= ctx
->program
->create_and_insert_block();
9241 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9242 break_block
->kind
= block_kind_uniform
;
9243 bld
.reset(break_block
);
9244 bld
.branch(aco_opcode::p_branch
);
9245 add_linear_edge(block_idx
, break_block
);
9246 add_linear_edge(break_block
->index
, &loop_exit
);
9248 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9249 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9250 continue_block
->kind
= block_kind_uniform
;
9251 bld
.reset(continue_block
);
9252 bld
.branch(aco_opcode::p_branch
);
9253 add_linear_edge(block_idx
, continue_block
);
9254 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9256 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9257 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9258 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9260 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9261 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9262 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9264 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9267 bld
.reset(ctx
->block
);
9268 bld
.branch(aco_opcode::p_branch
);
9271 /* Fixup phis in loop header from unreachable blocks.
9272 * has_branch/has_divergent_branch also indicates if the loop ends with a
9273 * break/continue instruction, but we don't emit those if unreachable=true */
9275 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9276 bool linear
= ctx
->cf_info
.has_branch
;
9277 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9278 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9279 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9280 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9281 /* the last operand should be the one that needs to be removed */
9282 instr
->operands
.pop_back();
9283 } else if (!is_phi(instr
)) {
9289 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9290 * and the previous one shouldn't both happen at once because a break in the
9291 * merge block would get CSE'd */
9292 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9293 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9294 Operand vals
[num_vals
];
9295 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9296 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9297 if (ctx
->cf_info
.has_branch
)
9298 instr
->operands
.pop_back();
9300 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9301 } else if (!is_phi(instr
)) {
9307 ctx
->cf_info
.has_branch
= false;
9309 // TODO: if the loop has not a single exit, we must add one °°
9310 /* emit loop successor block */
9311 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9312 append_logical_start(ctx
->block
);
9315 // TODO: check if it is beneficial to not branch on continues
9316 /* trim linear phis in loop header */
9317 for (auto&& instr
: loop_entry
->instructions
) {
9318 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9319 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9320 new_phi
->definitions
[0] = instr
->definitions
[0];
9321 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9322 new_phi
->operands
[i
] = instr
->operands
[i
];
9323 /* check that the remaining operands are all the same */
9324 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9325 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9326 instr
.swap(new_phi
);
9327 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9336 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9340 append_logical_end(ctx
->block
);
9341 ctx
->block
->kind
|= block_kind_branch
;
9343 /* branch to linear then block */
9344 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9345 aco_ptr
<Pseudo_branch_instruction
> branch
;
9346 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9347 branch
->operands
[0] = Operand(cond
);
9348 ctx
->block
->instructions
.push_back(std::move(branch
));
9350 ic
->BB_if_idx
= ctx
->block
->index
;
9351 ic
->BB_invert
= Block();
9352 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9353 /* Invert blocks are intentionally not marked as top level because they
9354 * are not part of the logical cfg. */
9355 ic
->BB_invert
.kind
|= block_kind_invert
;
9356 ic
->BB_endif
= Block();
9357 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9358 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9360 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9361 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9362 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9363 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9364 ctx
->cf_info
.parent_if
.is_divergent
= true;
9366 /* divergent branches use cbranch_execz */
9367 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9368 ctx
->cf_info
.exec_potentially_empty_break
= false;
9369 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9371 /** emit logical then block */
9372 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9373 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9374 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9375 ctx
->block
= BB_then_logical
;
9376 append_logical_start(BB_then_logical
);
9379 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9381 Block
*BB_then_logical
= ctx
->block
;
9382 append_logical_end(BB_then_logical
);
9383 /* branch from logical then block to invert block */
9384 aco_ptr
<Pseudo_branch_instruction
> branch
;
9385 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9386 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9387 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9388 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9389 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9390 BB_then_logical
->kind
|= block_kind_uniform
;
9391 assert(!ctx
->cf_info
.has_branch
);
9392 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9393 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9395 /** emit linear then block */
9396 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9397 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9398 BB_then_linear
->kind
|= block_kind_uniform
;
9399 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9400 /* branch from linear then block to invert block */
9401 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9402 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9403 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9405 /** emit invert merge block */
9406 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9407 ic
->invert_idx
= ctx
->block
->index
;
9409 /* branch to linear else block (skip else) */
9410 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9411 branch
->operands
[0] = Operand(ic
->cond
);
9412 ctx
->block
->instructions
.push_back(std::move(branch
));
9414 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9415 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9416 ic
->exec_potentially_empty_break_depth_old
=
9417 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9418 /* divergent branches use cbranch_execz */
9419 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9420 ctx
->cf_info
.exec_potentially_empty_break
= false;
9421 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9423 /** emit logical else block */
9424 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9425 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9426 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9427 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9428 ctx
->block
= BB_else_logical
;
9429 append_logical_start(BB_else_logical
);
9432 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9434 Block
*BB_else_logical
= ctx
->block
;
9435 append_logical_end(BB_else_logical
);
9437 /* branch from logical else block to endif block */
9438 aco_ptr
<Pseudo_branch_instruction
> branch
;
9439 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9440 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9441 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9442 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9443 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9444 BB_else_logical
->kind
|= block_kind_uniform
;
9446 assert(!ctx
->cf_info
.has_branch
);
9447 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9450 /** emit linear else block */
9451 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9452 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9453 BB_else_linear
->kind
|= block_kind_uniform
;
9454 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9456 /* branch from linear else block to endif block */
9457 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9458 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9459 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9462 /** emit endif merge block */
9463 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9464 append_logical_start(ctx
->block
);
9467 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9468 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9469 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9470 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9471 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9472 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9473 !ctx
->cf_info
.parent_if
.is_divergent
) {
9474 ctx
->cf_info
.exec_potentially_empty_break
= false;
9475 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9477 /* uniform control flow never has an empty exec-mask */
9478 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9479 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9480 ctx
->cf_info
.exec_potentially_empty_break
= false;
9481 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9485 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9487 assert(cond
.regClass() == s1
);
9489 append_logical_end(ctx
->block
);
9490 ctx
->block
->kind
|= block_kind_uniform
;
9492 aco_ptr
<Pseudo_branch_instruction
> branch
;
9493 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9494 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9495 branch
->operands
[0] = Operand(cond
);
9496 branch
->operands
[0].setFixed(scc
);
9497 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9499 ic
->BB_if_idx
= ctx
->block
->index
;
9500 ic
->BB_endif
= Block();
9501 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9502 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9504 ctx
->cf_info
.has_branch
= false;
9505 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9507 /** emit then block */
9508 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9509 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9510 add_edge(ic
->BB_if_idx
, BB_then
);
9511 append_logical_start(BB_then
);
9512 ctx
->block
= BB_then
;
9515 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9517 Block
*BB_then
= ctx
->block
;
9519 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9520 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9522 if (!ic
->uniform_has_then_branch
) {
9523 append_logical_end(BB_then
);
9524 /* branch from then block to endif block */
9525 aco_ptr
<Pseudo_branch_instruction
> branch
;
9526 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9527 BB_then
->instructions
.emplace_back(std::move(branch
));
9528 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9529 if (!ic
->then_branch_divergent
)
9530 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9531 BB_then
->kind
|= block_kind_uniform
;
9534 ctx
->cf_info
.has_branch
= false;
9535 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9537 /** emit else block */
9538 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9539 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9540 add_edge(ic
->BB_if_idx
, BB_else
);
9541 append_logical_start(BB_else
);
9542 ctx
->block
= BB_else
;
9545 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9547 Block
*BB_else
= ctx
->block
;
9549 if (!ctx
->cf_info
.has_branch
) {
9550 append_logical_end(BB_else
);
9551 /* branch from then block to endif block */
9552 aco_ptr
<Pseudo_branch_instruction
> branch
;
9553 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9554 BB_else
->instructions
.emplace_back(std::move(branch
));
9555 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9556 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9557 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9558 BB_else
->kind
|= block_kind_uniform
;
9561 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9562 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9564 /** emit endif merge block */
9565 if (!ctx
->cf_info
.has_branch
) {
9566 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9567 append_logical_start(ctx
->block
);
9571 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9573 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9574 Builder
bld(ctx
->program
, ctx
->block
);
9575 aco_ptr
<Pseudo_branch_instruction
> branch
;
9578 if (!ctx
->divergent_vals
[if_stmt
->condition
.ssa
->index
]) { /* uniform condition */
9580 * Uniform conditionals are represented in the following way*) :
9582 * The linear and logical CFG:
9585 * BB_THEN (logical) BB_ELSE (logical)
9589 * *) Exceptions may be due to break and continue statements within loops
9590 * If a break/continue happens within uniform control flow, it branches
9591 * to the loop exit/entry block. Otherwise, it branches to the next
9595 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9596 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9597 cond
= bool_to_scalar_condition(ctx
, cond
);
9599 begin_uniform_if_then(ctx
, &ic
, cond
);
9600 visit_cf_list(ctx
, &if_stmt
->then_list
);
9602 begin_uniform_if_else(ctx
, &ic
);
9603 visit_cf_list(ctx
, &if_stmt
->else_list
);
9605 end_uniform_if(ctx
, &ic
);
9607 return !ctx
->cf_info
.has_branch
;
9608 } else { /* non-uniform condition */
9610 * To maintain a logical and linear CFG without critical edges,
9611 * non-uniform conditionals are represented in the following way*) :
9616 * BB_THEN (logical) BB_THEN (linear)
9618 * BB_INVERT (linear)
9620 * BB_ELSE (logical) BB_ELSE (linear)
9627 * BB_THEN (logical) BB_ELSE (logical)
9631 * *) Exceptions may be due to break and continue statements within loops
9634 begin_divergent_if_then(ctx
, &ic
, cond
);
9635 visit_cf_list(ctx
, &if_stmt
->then_list
);
9637 begin_divergent_if_else(ctx
, &ic
);
9638 visit_cf_list(ctx
, &if_stmt
->else_list
);
9640 end_divergent_if(ctx
, &ic
);
9646 static bool visit_cf_list(isel_context
*ctx
,
9647 struct exec_list
*list
)
9649 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9650 switch (node
->type
) {
9651 case nir_cf_node_block
:
9652 visit_block(ctx
, nir_cf_node_as_block(node
));
9654 case nir_cf_node_if
:
9655 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9658 case nir_cf_node_loop
:
9659 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9662 unreachable("unimplemented cf list type");
9668 static void create_null_export(isel_context
*ctx
)
9670 /* Some shader stages always need to have exports.
9671 * So when there is none, we need to add a null export.
9674 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9675 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9676 Builder
bld(ctx
->program
, ctx
->block
);
9677 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9678 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9681 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9683 assert(ctx
->stage
== vertex_vs
||
9684 ctx
->stage
== tess_eval_vs
||
9685 ctx
->stage
== gs_copy_vs
||
9686 ctx
->stage
== ngg_vertex_gs
||
9687 ctx
->stage
== ngg_tess_eval_gs
);
9689 int offset
= (ctx
->stage
& sw_tes
)
9690 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9691 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9692 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9693 if (!is_pos
&& !mask
)
9695 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9697 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9698 exp
->enabled_mask
= mask
;
9699 for (unsigned i
= 0; i
< 4; ++i
) {
9700 if (mask
& (1 << i
))
9701 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9703 exp
->operands
[i
] = Operand(v1
);
9705 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9706 * Setting valid_mask=1 prevents it and has no other effect.
9708 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9710 exp
->compressed
= false;
9712 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9714 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9715 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9720 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9722 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9723 exp
->enabled_mask
= 0;
9724 for (unsigned i
= 0; i
< 4; ++i
)
9725 exp
->operands
[i
] = Operand(v1
);
9726 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9727 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9728 exp
->enabled_mask
|= 0x1;
9730 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9731 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9732 exp
->enabled_mask
|= 0x4;
9734 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9735 if (ctx
->options
->chip_class
< GFX9
) {
9736 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9737 exp
->enabled_mask
|= 0x8;
9739 Builder
bld(ctx
->program
, ctx
->block
);
9741 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9742 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9743 if (exp
->operands
[2].isTemp())
9744 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9746 exp
->operands
[2] = Operand(out
);
9747 exp
->enabled_mask
|= 0x4;
9750 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9752 exp
->compressed
= false;
9753 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9754 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9757 static void create_export_phis(isel_context
*ctx
)
9759 /* Used when exports are needed, but the output temps are defined in a preceding block.
9760 * This function will set up phis in order to access the outputs in the next block.
9763 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9764 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9765 ctx
->block
->instructions
.pop_back();
9767 Builder
bld(ctx
->program
, ctx
->block
);
9769 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9770 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9771 for (unsigned i
= 0; i
< 4; ++i
) {
9772 if (!(mask
& (1 << i
)))
9775 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9776 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9777 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9781 bld
.insert(std::move(logical_start
));
9784 static void create_vs_exports(isel_context
*ctx
)
9786 assert(ctx
->stage
== vertex_vs
||
9787 ctx
->stage
== tess_eval_vs
||
9788 ctx
->stage
== gs_copy_vs
||
9789 ctx
->stage
== ngg_vertex_gs
||
9790 ctx
->stage
== ngg_tess_eval_gs
);
9792 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9793 ? &ctx
->program
->info
->tes
.outinfo
9794 : &ctx
->program
->info
->vs
.outinfo
;
9796 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9797 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9798 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9801 if (ctx
->options
->key
.has_multiview_view_index
) {
9802 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9803 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9806 /* the order these position exports are created is important */
9808 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9809 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9810 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9811 exported_pos
= true;
9813 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9814 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9815 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9816 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9818 if (ctx
->export_clip_dists
) {
9819 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9820 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9821 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9822 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9825 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9826 if (i
< VARYING_SLOT_VAR0
&&
9827 i
!= VARYING_SLOT_LAYER
&&
9828 i
!= VARYING_SLOT_PRIMITIVE_ID
)
9831 export_vs_varying(ctx
, i
, false, NULL
);
9835 create_null_export(ctx
);
9838 static bool export_fs_mrt_z(isel_context
*ctx
)
9840 Builder
bld(ctx
->program
, ctx
->block
);
9841 unsigned enabled_channels
= 0;
9845 for (unsigned i
= 0; i
< 4; ++i
) {
9846 values
[i
] = Operand(v1
);
9849 /* Both stencil and sample mask only need 16-bits. */
9850 if (!ctx
->program
->info
->ps
.writes_z
&&
9851 (ctx
->program
->info
->ps
.writes_stencil
||
9852 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9853 compr
= true; /* COMPR flag */
9855 if (ctx
->program
->info
->ps
.writes_stencil
) {
9856 /* Stencil should be in X[23:16]. */
9857 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9858 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9859 enabled_channels
|= 0x3;
9862 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9863 /* SampleMask should be in Y[15:0]. */
9864 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9865 enabled_channels
|= 0xc;
9868 if (ctx
->program
->info
->ps
.writes_z
) {
9869 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9870 enabled_channels
|= 0x1;
9873 if (ctx
->program
->info
->ps
.writes_stencil
) {
9874 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9875 enabled_channels
|= 0x2;
9878 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9879 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9880 enabled_channels
|= 0x4;
9884 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9885 * writemask component.
9887 if (ctx
->options
->chip_class
== GFX6
&&
9888 ctx
->options
->family
!= CHIP_OLAND
&&
9889 ctx
->options
->family
!= CHIP_HAINAN
) {
9890 enabled_channels
|= 0x1;
9893 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9894 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9899 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9901 Builder
bld(ctx
->program
, ctx
->block
);
9902 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9905 for (unsigned i
= 0; i
< 4; ++i
) {
9906 if (write_mask
& (1 << i
)) {
9907 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9909 values
[i
] = Operand(v1
);
9913 unsigned target
, col_format
;
9914 unsigned enabled_channels
= 0;
9915 aco_opcode compr_op
= (aco_opcode
)0;
9917 slot
-= FRAG_RESULT_DATA0
;
9918 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9919 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9921 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9922 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
9926 case V_028714_SPI_SHADER_ZERO
:
9927 enabled_channels
= 0; /* writemask */
9928 target
= V_008DFC_SQ_EXP_NULL
;
9931 case V_028714_SPI_SHADER_32_R
:
9932 enabled_channels
= 1;
9935 case V_028714_SPI_SHADER_32_GR
:
9936 enabled_channels
= 0x3;
9939 case V_028714_SPI_SHADER_32_AR
:
9940 if (ctx
->options
->chip_class
>= GFX10
) {
9941 /* Special case: on GFX10, the outputs are different for 32_AR */
9942 enabled_channels
= 0x3;
9943 values
[1] = values
[3];
9944 values
[3] = Operand(v1
);
9946 enabled_channels
= 0x9;
9950 case V_028714_SPI_SHADER_FP16_ABGR
:
9951 enabled_channels
= 0x5;
9952 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
9955 case V_028714_SPI_SHADER_UNORM16_ABGR
:
9956 enabled_channels
= 0x5;
9957 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
9960 case V_028714_SPI_SHADER_SNORM16_ABGR
:
9961 enabled_channels
= 0x5;
9962 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
9965 case V_028714_SPI_SHADER_UINT16_ABGR
: {
9966 enabled_channels
= 0x5;
9967 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
9968 if (is_int8
|| is_int10
) {
9970 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
9971 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9973 for (unsigned i
= 0; i
< 4; i
++) {
9974 if ((write_mask
>> i
) & 1) {
9975 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
9976 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
9984 case V_028714_SPI_SHADER_SINT16_ABGR
:
9985 enabled_channels
= 0x5;
9986 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
9987 if (is_int8
|| is_int10
) {
9989 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
9990 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
9991 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9992 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
9994 for (unsigned i
= 0; i
< 4; i
++) {
9995 if ((write_mask
>> i
) & 1) {
9996 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
9997 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
9999 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
10000 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
10007 case V_028714_SPI_SHADER_32_ABGR
:
10008 enabled_channels
= 0xF;
10015 if (target
== V_008DFC_SQ_EXP_NULL
)
10018 if ((bool) compr_op
) {
10019 for (int i
= 0; i
< 2; i
++) {
10020 /* check if at least one of the values to be compressed is enabled */
10021 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
10023 enabled_channels
|= enabled
<< (i
*2);
10024 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
10025 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
10026 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
10028 values
[i
] = Operand(v1
);
10031 values
[2] = Operand(v1
);
10032 values
[3] = Operand(v1
);
10034 for (int i
= 0; i
< 4; i
++)
10035 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
10038 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10039 enabled_channels
, target
, (bool) compr_op
);
10043 static void create_fs_exports(isel_context
*ctx
)
10045 bool exported
= false;
10047 /* Export depth, stencil and sample mask. */
10048 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
10049 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
10050 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
10051 exported
|= export_fs_mrt_z(ctx
);
10053 /* Export all color render targets. */
10054 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10055 if (ctx
->outputs
.mask
[i
])
10056 exported
|= export_fs_mrt_color(ctx
, i
);
10059 create_null_export(ctx
);
10062 static void write_tcs_tess_factors(isel_context
*ctx
)
10064 unsigned outer_comps
;
10065 unsigned inner_comps
;
10067 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10084 Builder
bld(ctx
->program
, ctx
->block
);
10086 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10087 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
10088 bld
.sopp(aco_opcode::s_barrier
);
10090 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10091 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10093 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10094 if_context ic_invocation_id_is_zero
;
10095 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10096 bld
.reset(ctx
->block
);
10098 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10100 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10101 unsigned stride
= inner_comps
+ outer_comps
;
10102 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10106 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10108 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10110 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10111 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10112 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10114 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10115 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10117 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10118 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10119 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10120 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10123 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10124 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10125 Temp byte_offset
= bld
.v_mul_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10126 unsigned tf_const_offset
= 0;
10128 if (ctx
->program
->chip_class
<= GFX8
) {
10129 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10130 if_context ic_rel_patch_id_is_zero
;
10131 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10132 bld
.reset(ctx
->block
);
10134 /* Store the dynamic HS control word. */
10135 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10136 bld
.mubuf(aco_opcode::buffer_store_dword
,
10137 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10138 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
10139 /* disable_wqm */ false, /* glc */ true);
10140 tf_const_offset
+= 4;
10142 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10143 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10144 bld
.reset(ctx
->block
);
10147 assert(stride
== 2 || stride
== 4 || stride
== 6);
10148 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10149 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
10151 /* Store to offchip for TES to read - only if TES reads them */
10152 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10153 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10154 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10156 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10157 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
10159 if (likely(inner_comps
)) {
10160 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10161 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
10165 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10166 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10169 static void emit_stream_output(isel_context
*ctx
,
10170 Temp
const *so_buffers
,
10171 Temp
const *so_write_offset
,
10172 const struct radv_stream_output
*output
)
10174 unsigned num_comps
= util_bitcount(output
->component_mask
);
10175 unsigned writemask
= (1 << num_comps
) - 1;
10176 unsigned loc
= output
->location
;
10177 unsigned buf
= output
->buffer
;
10179 assert(num_comps
&& num_comps
<= 4);
10180 if (!num_comps
|| num_comps
> 4)
10183 unsigned start
= ffs(output
->component_mask
) - 1;
10186 bool all_undef
= true;
10187 assert(ctx
->stage
== vertex_vs
|| ctx
->stage
== gs_copy_vs
);
10188 for (unsigned i
= 0; i
< num_comps
; i
++) {
10189 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10190 all_undef
= all_undef
&& !out
[i
].id();
10195 while (writemask
) {
10197 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10198 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10199 /* GFX6 doesn't support storing vec3, split it. */
10200 writemask
|= 1u << (start
+ 2);
10204 unsigned offset
= output
->offset
+ start
* 4;
10206 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10207 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10208 for (int i
= 0; i
< count
; ++i
)
10209 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10210 vec
->definitions
[0] = Definition(write_data
);
10211 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10216 opcode
= aco_opcode::buffer_store_dword
;
10219 opcode
= aco_opcode::buffer_store_dwordx2
;
10222 opcode
= aco_opcode::buffer_store_dwordx3
;
10225 opcode
= aco_opcode::buffer_store_dwordx4
;
10228 unreachable("Unsupported dword count.");
10231 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10232 store
->operands
[0] = Operand(so_buffers
[buf
]);
10233 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10234 store
->operands
[2] = Operand((uint32_t) 0);
10235 store
->operands
[3] = Operand(write_data
);
10236 if (offset
> 4095) {
10237 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10238 Builder
bld(ctx
->program
, ctx
->block
);
10239 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10241 store
->offset
= offset
;
10243 store
->offen
= true;
10245 store
->dlc
= false;
10247 store
->can_reorder
= true;
10248 ctx
->block
->instructions
.emplace_back(std::move(store
));
10252 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10254 Builder
bld(ctx
->program
, ctx
->block
);
10256 Temp so_buffers
[4];
10257 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10258 for (unsigned i
= 0; i
< 4; i
++) {
10259 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10263 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10264 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10267 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10268 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10270 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10272 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10275 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10277 bld
.reset(ctx
->block
);
10279 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10281 Temp so_write_offset
[4];
10283 for (unsigned i
= 0; i
< 4; i
++) {
10284 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10289 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10290 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10291 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10292 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10294 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10296 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10297 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10298 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10299 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10303 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10304 struct radv_stream_output
*output
=
10305 &ctx
->program
->info
->so
.outputs
[i
];
10306 if (stream
!= output
->stream
)
10309 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10312 begin_divergent_if_else(ctx
, &ic
);
10313 end_divergent_if(ctx
, &ic
);
10316 } /* end namespace */
10318 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10320 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10321 Builder
bld(ctx
->program
, ctx
->block
);
10322 constexpr unsigned hs_idx
= 1u;
10323 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10324 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10325 Operand((8u << 16) | (hs_idx
* 8u)));
10326 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10328 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10330 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10331 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10332 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10333 ls_has_nonzero_hs_threads
);
10334 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10335 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10336 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10337 ls_has_nonzero_hs_threads
);
10338 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10339 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10340 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10341 ls_has_nonzero_hs_threads
);
10343 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10344 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10345 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10348 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10350 /* Split all arguments except for the first (ring_offsets) and the last
10351 * (exec) so that the dead channels don't stay live throughout the program.
10353 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10354 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10355 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10356 startpgm
->definitions
[i
].regClass().size());
10361 void handle_bc_optimize(isel_context
*ctx
)
10363 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10364 Builder
bld(ctx
->program
, ctx
->block
);
10365 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10366 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10367 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10368 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10369 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10370 if (uses_center
&& uses_centroid
) {
10371 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10372 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10374 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10376 for (unsigned i
= 0; i
< 2; i
++) {
10377 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10378 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10379 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10380 persp_centroid
, persp_center
, sel
);
10382 ctx
->persp_centroid
= bld
.tmp(v2
);
10383 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10384 Operand(new_coord
[0]), Operand(new_coord
[1]));
10385 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10388 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10390 for (unsigned i
= 0; i
< 2; i
++) {
10391 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10392 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10393 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10394 linear_centroid
, linear_center
, sel
);
10396 ctx
->linear_centroid
= bld
.tmp(v2
);
10397 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10398 Operand(new_coord
[0]), Operand(new_coord
[1]));
10399 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10404 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10406 Program
*program
= ctx
->program
;
10408 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10410 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10411 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10412 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10413 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10414 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10416 program
->next_fp_mode
.must_flush_denorms32
=
10417 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10418 program
->next_fp_mode
.must_flush_denorms16_64
=
10419 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10420 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10422 program
->next_fp_mode
.care_about_round32
=
10423 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10425 program
->next_fp_mode
.care_about_round16_64
=
10426 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10427 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10429 /* default to preserving fp16 and fp64 denorms, since it's free */
10430 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10431 program
->next_fp_mode
.denorm16_64
= 0;
10433 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10435 /* preserving fp32 denorms is expensive, so only do it if asked */
10436 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10437 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10439 program
->next_fp_mode
.denorm32
= 0;
10441 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10442 program
->next_fp_mode
.round32
= fp_round_tz
;
10444 program
->next_fp_mode
.round32
= fp_round_ne
;
10446 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10447 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10449 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10451 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10454 void cleanup_cfg(Program
*program
)
10456 /* create linear_succs/logical_succs */
10457 for (Block
& BB
: program
->blocks
) {
10458 for (unsigned idx
: BB
.linear_preds
)
10459 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10460 for (unsigned idx
: BB
.logical_preds
)
10461 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10465 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10467 Builder
bld(ctx
->program
, ctx
->block
);
10469 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10470 Temp count
= i
== 0
10471 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10472 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10473 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10475 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10478 if (ctx
->program
->wave_size
== 64) {
10479 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10480 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10481 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10483 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10484 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10490 bool ngg_early_prim_export(isel_context
*ctx
)
10492 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10496 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10498 Builder
bld(ctx
->program
, ctx
->block
);
10500 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10501 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10503 /* Get the id of the current wave within the threadgroup (workgroup) */
10504 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10505 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10507 /* Execute the following code only on the first wave (wave id 0),
10508 * use the SCC def to tell if the wave id is zero or not.
10510 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10512 begin_uniform_if_then(ctx
, &ic
, cond
);
10513 begin_uniform_if_else(ctx
, &ic
);
10514 bld
.reset(ctx
->block
);
10516 /* Number of vertices output by VS/TES */
10517 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10518 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10519 /* Number of primitives output by VS/TES */
10520 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10521 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10523 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10524 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10525 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10527 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10528 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10530 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10531 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10533 end_uniform_if(ctx
, &ic
);
10536 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10538 Builder
bld(ctx
->program
, ctx
->block
);
10540 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10541 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10544 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10547 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10548 assert(vtxindex
[i
].id());
10551 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10555 /* The initial edge flag is always false in tess eval shaders. */
10556 if (ctx
->stage
== ngg_vertex_gs
) {
10557 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10558 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10562 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10567 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10569 Builder
bld(ctx
->program
, ctx
->block
);
10570 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10572 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10573 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10574 false /* compressed */, true/* done */, false /* valid mask */);
10577 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10579 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10580 * These must always come before VS exports.
10582 * It is recommended to do these as early as possible. They can be at the beginning when
10583 * there is no SW GS and the shader doesn't write edge flags.
10587 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10588 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10590 Builder
bld(ctx
->program
, ctx
->block
);
10591 constexpr unsigned max_vertices_per_primitive
= 3;
10592 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10594 if (ctx
->stage
== ngg_vertex_gs
) {
10595 /* TODO: optimize for points & lines */
10596 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10597 if (ctx
->shader
->info
.tess
.point_mode
)
10598 num_vertices_per_primitive
= 1;
10599 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10600 num_vertices_per_primitive
= 2;
10602 unreachable("Unsupported NGG shader stage");
10605 Temp vtxindex
[max_vertices_per_primitive
];
10606 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10607 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10608 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10609 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10610 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10611 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10612 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10613 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10615 /* Export primitive data to the index buffer. */
10616 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10618 /* Export primitive ID. */
10619 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10620 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10621 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10622 Temp provoking_vtx_index
= vtxindex
[0];
10623 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10625 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10628 begin_divergent_if_else(ctx
, &ic
);
10629 end_divergent_if(ctx
, &ic
);
10632 void ngg_emit_nogs_output(isel_context
*ctx
)
10634 /* Emits NGG GS output, for stages that don't have SW GS. */
10637 Builder
bld(ctx
->program
, ctx
->block
);
10638 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10640 /* NGG streamout is currently disabled by default. */
10641 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10643 if (late_prim_export
) {
10644 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10645 create_export_phis(ctx
);
10646 /* Do what we need to do in the GS threads. */
10647 ngg_emit_nogs_gsthreads(ctx
);
10649 /* What comes next should be executed on ES threads. */
10650 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10651 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10652 bld
.reset(ctx
->block
);
10655 /* Export VS outputs */
10656 ctx
->block
->kind
|= block_kind_export_end
;
10657 create_vs_exports(ctx
);
10659 /* Export primitive ID */
10660 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10663 if (ctx
->stage
== ngg_vertex_gs
) {
10664 /* Wait for GS threads to store primitive ID in LDS. */
10665 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10666 bld
.sopp(aco_opcode::s_barrier
);
10668 /* Calculate LDS address where the GS threads stored the primitive ID. */
10669 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10670 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10671 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10672 Temp wave_id_mul
= bld
.v_mul_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10673 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10674 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10676 /* Load primitive ID from LDS. */
10677 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10678 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10679 /* TES: Just use the patch ID as the primitive ID. */
10680 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10682 unreachable("unsupported NGG shader stage.");
10685 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10686 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10688 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10691 if (late_prim_export
) {
10692 begin_divergent_if_else(ctx
, &ic
);
10693 end_divergent_if(ctx
, &ic
);
10694 bld
.reset(ctx
->block
);
10698 void select_program(Program
*program
,
10699 unsigned shader_count
,
10700 struct nir_shader
*const *shaders
,
10701 ac_shader_config
* config
,
10702 struct radv_shader_args
*args
)
10704 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10705 if_context ic_merged_wave_info
;
10706 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10708 for (unsigned i
= 0; i
< shader_count
; i
++) {
10709 nir_shader
*nir
= shaders
[i
];
10710 init_context(&ctx
, nir
);
10712 setup_fp_mode(&ctx
, nir
);
10715 /* needs to be after init_context() for FS */
10716 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10717 append_logical_start(ctx
.block
);
10719 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10720 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10722 split_arguments(&ctx
, startpgm
);
10726 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10728 if (ngg_early_prim_export(&ctx
))
10729 ngg_emit_nogs_gsthreads(&ctx
);
10732 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10733 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10734 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10735 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10736 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10737 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10738 ctx
.stage
== tess_eval_geometry_gs
));
10740 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10741 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10742 if (check_merged_wave_info
) {
10743 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10744 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10748 Builder
bld(ctx
.program
, ctx
.block
);
10750 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10751 bld
.sopp(aco_opcode::s_barrier
);
10753 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10754 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10756 } else if (ctx
.stage
== geometry_gs
)
10757 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10759 if (ctx
.stage
== fragment_fs
)
10760 handle_bc_optimize(&ctx
);
10762 visit_cf_list(&ctx
, &func
->body
);
10764 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10765 emit_streamout(&ctx
, 0);
10767 if (ctx
.stage
& hw_vs
) {
10768 create_vs_exports(&ctx
);
10769 ctx
.block
->kind
|= block_kind_export_end
;
10770 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10771 ngg_emit_nogs_output(&ctx
);
10772 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10773 Builder
bld(ctx
.program
, ctx
.block
);
10774 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10775 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10776 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10777 write_tcs_tess_factors(&ctx
);
10780 if (ctx
.stage
== fragment_fs
) {
10781 create_fs_exports(&ctx
);
10782 ctx
.block
->kind
|= block_kind_export_end
;
10785 if (endif_merged_wave_info
) {
10786 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10787 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10790 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10791 ngg_emit_nogs_output(&ctx
);
10793 ralloc_free(ctx
.divergent_vals
);
10795 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10796 /* Outputs of the previous stage are inputs to the next stage */
10797 ctx
.inputs
= ctx
.outputs
;
10798 ctx
.outputs
= shader_io_state();
10802 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10804 append_logical_end(ctx
.block
);
10805 ctx
.block
->kind
|= block_kind_uniform
;
10806 Builder
bld(ctx
.program
, ctx
.block
);
10807 if (ctx
.program
->wb_smem_l1_on_end
)
10808 bld
.smem(aco_opcode::s_dcache_wb
, false);
10809 bld
.sopp(aco_opcode::s_endpgm
);
10811 cleanup_cfg(program
);
10814 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10815 ac_shader_config
* config
,
10816 struct radv_shader_args
*args
)
10818 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10820 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
10821 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
10822 program
->next_fp_mode
.must_flush_denorms32
= false;
10823 program
->next_fp_mode
.must_flush_denorms16_64
= false;
10824 program
->next_fp_mode
.care_about_round32
= false;
10825 program
->next_fp_mode
.care_about_round16_64
= false;
10826 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10827 program
->next_fp_mode
.denorm32
= 0;
10828 program
->next_fp_mode
.round32
= fp_round_ne
;
10829 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10830 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10832 add_startpgm(&ctx
);
10833 append_logical_start(ctx
.block
);
10835 Builder
bld(ctx
.program
, ctx
.block
);
10837 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10839 Operand
stream_id(0u);
10840 if (args
->shader_info
->so
.num_outputs
)
10841 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10842 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10844 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10846 std::stack
<Block
> endif_blocks
;
10848 for (unsigned stream
= 0; stream
< 4; stream
++) {
10849 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10852 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10853 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10856 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10858 unsigned BB_if_idx
= ctx
.block
->index
;
10859 Block BB_endif
= Block();
10860 if (!stream_id
.isConstant()) {
10862 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10863 append_logical_end(ctx
.block
);
10864 ctx
.block
->kind
|= block_kind_uniform
;
10865 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
10867 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10869 ctx
.block
= ctx
.program
->create_and_insert_block();
10870 add_edge(BB_if_idx
, ctx
.block
);
10871 bld
.reset(ctx
.block
);
10872 append_logical_start(ctx
.block
);
10875 unsigned offset
= 0;
10876 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10877 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10880 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10881 unsigned length
= util_last_bit(output_usage_mask
);
10882 for (unsigned j
= 0; j
< length
; ++j
) {
10883 if (!(output_usage_mask
& (1 << j
)))
10886 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10887 Temp voffset
= vtx_offset
;
10888 if (const_offset
>= 4096u) {
10889 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10890 const_offset
%= 4096u;
10893 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10894 mubuf
->definitions
[0] = bld
.def(v1
);
10895 mubuf
->operands
[0] = Operand(gsvs_ring
);
10896 mubuf
->operands
[1] = Operand(voffset
);
10897 mubuf
->operands
[2] = Operand(0u);
10898 mubuf
->offen
= true;
10899 mubuf
->offset
= const_offset
;
10902 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
10903 mubuf
->barrier
= barrier_none
;
10904 mubuf
->can_reorder
= true;
10906 ctx
.outputs
.mask
[i
] |= 1 << j
;
10907 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
10909 bld
.insert(std::move(mubuf
));
10915 if (args
->shader_info
->so
.num_outputs
) {
10916 emit_streamout(&ctx
, stream
);
10917 bld
.reset(ctx
.block
);
10921 create_vs_exports(&ctx
);
10922 ctx
.block
->kind
|= block_kind_export_end
;
10925 if (!stream_id
.isConstant()) {
10926 append_logical_end(ctx
.block
);
10928 /* branch from then block to endif block */
10929 bld
.branch(aco_opcode::p_branch
);
10930 add_edge(ctx
.block
->index
, &BB_endif
);
10931 ctx
.block
->kind
|= block_kind_uniform
;
10933 /* emit else block */
10934 ctx
.block
= ctx
.program
->create_and_insert_block();
10935 add_edge(BB_if_idx
, ctx
.block
);
10936 bld
.reset(ctx
.block
);
10937 append_logical_start(ctx
.block
);
10939 endif_blocks
.push(std::move(BB_endif
));
10943 while (!endif_blocks
.empty()) {
10944 Block BB_endif
= std::move(endif_blocks
.top());
10945 endif_blocks
.pop();
10947 Block
*BB_else
= ctx
.block
;
10949 append_logical_end(BB_else
);
10950 /* branch from else block to endif block */
10951 bld
.branch(aco_opcode::p_branch
);
10952 add_edge(BB_else
->index
, &BB_endif
);
10953 BB_else
->kind
|= block_kind_uniform
;
10955 /** emit endif merge block */
10956 ctx
.block
= program
->insert_block(std::move(BB_endif
));
10957 bld
.reset(ctx
.block
);
10958 append_logical_start(ctx
.block
);
10961 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10963 append_logical_end(ctx
.block
);
10964 ctx
.block
->kind
|= block_kind_uniform
;
10965 bld
.sopp(aco_opcode::s_endpgm
);
10967 cleanup_cfg(program
);