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3 * Copyright © 2018 Google
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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
140 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
145 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
147 Builder
bld(ctx
->program
, ctx
->block
);
150 dst
= bld
.tmp(src
.regClass());
152 assert(src
.size() == dst
.size());
154 if (ctx
->stage
!= fragment_fs
) {
158 bld
.copy(Definition(dst
), src
);
162 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
163 ctx
->program
->needs_wqm
|= program_needs_wqm
;
167 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
169 if (index
.regClass() == s1
)
170 return bld
.readlane(bld
.def(s1
), data
, index
);
172 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
174 /* Currently not implemented on GFX6-7 */
175 assert(ctx
->options
->chip_class
>= GFX8
);
177 if (ctx
->options
->chip_class
<= GFX9
|| ctx
->program
->wave_size
== 32) {
178 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
181 /* GFX10, wave64 mode:
182 * The bpermute instruction is limited to half-wave operation, which means that it can't
183 * properly support subgroup shuffle like older generations (or wave32 mode), so we
186 if (!ctx
->has_gfx10_wave64_bpermute
) {
187 ctx
->has_gfx10_wave64_bpermute
= true;
188 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
189 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
192 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
193 Temp lane_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), lane_id
);
194 Temp index_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), index
);
195 Temp cmp
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
, vcc
), lane_is_hi
, index_is_hi
);
197 return bld
.reduction(aco_opcode::p_wave64_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
),
198 bld
.vcc(cmp
), Operand(v2
.as_linear()), index_x4
, data
, gfx10_wave64_bpermute
);
201 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
203 if (val
.type() == RegType::sgpr
) {
204 Builder
bld(ctx
->program
, ctx
->block
);
205 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
207 assert(val
.type() == RegType::vgpr
);
211 //assumes a != 0xffffffff
212 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
215 Builder
bld(ctx
->program
, ctx
->block
);
217 if (util_is_power_of_two_or_zero(b
)) {
218 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
222 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
224 assert(info
.multiplier
<= 0xffffffff);
226 bool pre_shift
= info
.pre_shift
!= 0;
227 bool increment
= info
.increment
!= 0;
228 bool multiply
= true;
229 bool post_shift
= info
.post_shift
!= 0;
231 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
232 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
236 Temp pre_shift_dst
= a
;
238 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
239 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
242 Temp increment_dst
= pre_shift_dst
;
244 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
245 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
248 Temp multiply_dst
= increment_dst
;
250 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
251 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
252 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
256 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
260 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
262 Builder
bld(ctx
->program
, ctx
->block
);
263 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
267 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
269 /* no need to extract the whole vector */
270 if (src
.regClass() == dst_rc
) {
275 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
276 Builder
bld(ctx
->program
, ctx
->block
);
277 auto it
= ctx
->allocated_vec
.find(src
.id());
278 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
279 if (it
->second
[idx
].regClass() == dst_rc
) {
280 return it
->second
[idx
];
282 assert(!dst_rc
.is_subdword());
283 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
284 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
288 if (dst_rc
.is_subdword())
289 src
= as_vgpr(ctx
, src
);
291 if (src
.bytes() == dst_rc
.bytes()) {
293 return bld
.copy(bld
.def(dst_rc
), src
);
295 Temp dst
= bld
.tmp(dst_rc
);
296 emit_extract_vector(ctx
, src
, idx
, dst
);
301 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
303 if (num_components
== 1)
305 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
307 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
308 split
->operands
[0] = Operand(vec_src
);
309 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
311 if (num_components
> vec_src
.size()) {
312 if (vec_src
.type() == RegType::sgpr
)
315 /* sub-dword split */
316 assert(vec_src
.type() == RegType::vgpr
);
317 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
319 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
321 for (unsigned i
= 0; i
< num_components
; i
++) {
322 elems
[i
] = {ctx
->program
->allocateId(), rc
};
323 split
->definitions
[i
] = Definition(elems
[i
]);
325 ctx
->block
->instructions
.emplace_back(std::move(split
));
326 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
329 /* This vector expansion uses a mask to determine which elements in the new vector
330 * come from the original vector. The other elements are undefined. */
331 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
333 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
338 Builder
bld(ctx
->program
, ctx
->block
);
339 if (num_components
== 1) {
340 if (dst
.type() == RegType::sgpr
)
341 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
343 bld
.copy(Definition(dst
), vec_src
);
347 unsigned component_size
= dst
.size() / num_components
;
348 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
350 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
351 vec
->definitions
[0] = Definition(dst
);
353 for (unsigned i
= 0; i
< num_components
; i
++) {
354 if (mask
& (1 << i
)) {
355 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
356 if (dst
.type() == RegType::sgpr
)
357 src
= bld
.as_uniform(src
);
358 vec
->operands
[i
] = Operand(src
);
360 vec
->operands
[i
] = Operand(0u);
362 elems
[i
] = vec
->operands
[i
].getTemp();
364 ctx
->block
->instructions
.emplace_back(std::move(vec
));
365 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
368 /* adjust misaligned small bit size loads */
369 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
371 Builder
bld(ctx
->program
, ctx
->block
);
373 Temp select
= Temp();
374 if (offset
.isConstant()) {
375 assert(offset
.constantValue() && offset
.constantValue() < 4);
376 shift
= Operand(offset
.constantValue() * 8);
378 /* bit_offset = 8 * (offset & 0x3) */
379 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
380 select
= bld
.tmp(s1
);
381 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
384 if (vec
.size() == 1) {
385 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
386 } else if (vec
.size() == 2) {
387 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
388 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
390 emit_split_vector(ctx
, dst
, 2);
392 emit_extract_vector(ctx
, tmp
, 0, dst
);
393 } else if (vec
.size() == 4) {
394 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
395 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
396 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
397 if (select
!= Temp())
398 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), select
);
399 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
400 Temp mid
= bld
.tmp(s1
);
401 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
402 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
403 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
404 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
405 emit_split_vector(ctx
, dst
, 2);
409 /* this function trims subdword vectors:
410 * if dst is vgpr - split the src and create a shrunk version according to the mask.
411 * if dst is sgpr - split the src, but move the original to sgpr. */
412 void trim_subdword_vector(isel_context
*ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
414 assert(vec_src
.type() == RegType::vgpr
);
415 emit_split_vector(ctx
, vec_src
, num_components
);
417 Builder
bld(ctx
->program
, ctx
->block
);
418 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
419 unsigned component_size
= vec_src
.bytes() / num_components
;
420 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
423 for (unsigned i
= 0; i
< num_components
; i
++) {
425 elems
[k
++] = emit_extract_vector(ctx
, vec_src
, i
, rc
);
428 if (dst
.type() == RegType::vgpr
) {
429 assert(dst
.bytes() == k
* component_size
);
430 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, k
, 1)};
431 for (unsigned i
= 0; i
< k
; i
++)
432 vec
->operands
[i
] = Operand(elems
[i
]);
433 vec
->definitions
[0] = Definition(dst
);
434 bld
.insert(std::move(vec
));
436 // TODO: alignbyte if mask doesn't start with 1?
438 assert(dst
.size() == vec_src
.size());
439 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
441 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
444 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
446 Builder
bld(ctx
->program
, ctx
->block
);
448 dst
= bld
.tmp(bld
.lm
);
450 assert(val
.regClass() == s1
);
451 assert(dst
.regClass() == bld
.lm
);
453 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
456 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
458 Builder
bld(ctx
->program
, ctx
->block
);
462 assert(val
.regClass() == bld
.lm
);
463 assert(dst
.regClass() == s1
);
465 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
466 Temp tmp
= bld
.tmp(s1
);
467 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
468 return emit_wqm(ctx
, tmp
, dst
);
471 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
473 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
474 return get_ssa_temp(ctx
, src
.src
.ssa
);
476 if (src
.src
.ssa
->num_components
== size
) {
477 bool identity_swizzle
= true;
478 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
479 if (src
.swizzle
[i
] != i
)
480 identity_swizzle
= false;
482 if (identity_swizzle
)
483 return get_ssa_temp(ctx
, src
.src
.ssa
);
486 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
487 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
488 assert(elem_size
> 0);
489 assert(vec
.bytes() % elem_size
== 0);
491 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
492 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
494 unsigned swizzle
= src
.swizzle
[0];
495 if (vec
.size() > 1) {
496 assert(src
.src
.ssa
->bit_size
== 16);
497 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
498 swizzle
= swizzle
& 1;
503 Temp dst
{ctx
->program
->allocateId(), s1
};
504 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 1)};
505 bfe
->operands
[0] = Operand(vec
);
506 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
507 bfe
->definitions
[0] = Definition(dst
);
508 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
512 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
514 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
517 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
518 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
519 for (unsigned i
= 0; i
< size
; ++i
) {
520 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
521 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
523 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
524 vec_instr
->definitions
[0] = Definition(dst
);
525 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
526 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
531 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
535 Builder
bld(ctx
->program
, ctx
->block
);
536 if (ptr
.type() == RegType::vgpr
)
537 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
538 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
539 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
542 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
544 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
545 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
546 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
547 sop2
->definitions
[0] = Definition(dst
);
549 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
550 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
553 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
554 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
556 Builder
bld(ctx
->program
, ctx
->block
);
557 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
558 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
559 if (src1
.type() == RegType::sgpr
) {
560 if (commutative
&& src0
.type() == RegType::vgpr
) {
564 } else if (src0
.type() == RegType::vgpr
&&
565 op
!= aco_opcode::v_madmk_f32
&&
566 op
!= aco_opcode::v_madak_f32
&&
567 op
!= aco_opcode::v_madmk_f16
&&
568 op
!= aco_opcode::v_madak_f16
) {
569 /* If the instruction is not commutative, we emit a VOP3A instruction */
570 bld
.vop2_e64(op
, Definition(dst
), src0
, src1
);
573 src1
= bld
.copy(bld
.def(RegType::vgpr
, src1
.size()), src1
); //TODO: as_vgpr
577 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
578 assert(dst
.size() == 1);
579 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
580 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
582 bld
.vop2(op
, Definition(dst
), src0
, src1
);
586 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
587 bool flush_denorms
= false)
589 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
590 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
591 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
593 /* ensure that the instruction has at most 1 sgpr operand
594 * The optimizer will inline constants for us */
595 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
596 src0
= as_vgpr(ctx
, src0
);
597 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
598 src1
= as_vgpr(ctx
, src1
);
599 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
600 src2
= as_vgpr(ctx
, src2
);
602 Builder
bld(ctx
->program
, ctx
->block
);
603 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
604 assert(dst
.size() == 1);
605 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
606 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
608 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
612 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
614 Builder
bld(ctx
->program
, ctx
->block
);
615 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
618 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
620 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
621 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
622 assert(src0
.size() == src1
.size());
624 aco_ptr
<Instruction
> vopc
;
625 if (src1
.type() == RegType::sgpr
) {
626 if (src0
.type() == RegType::vgpr
) {
627 /* to swap the operands, we might also have to change the opcode */
629 case aco_opcode::v_cmp_lt_f32
:
630 op
= aco_opcode::v_cmp_gt_f32
;
632 case aco_opcode::v_cmp_ge_f32
:
633 op
= aco_opcode::v_cmp_le_f32
;
635 case aco_opcode::v_cmp_lt_i32
:
636 op
= aco_opcode::v_cmp_gt_i32
;
638 case aco_opcode::v_cmp_ge_i32
:
639 op
= aco_opcode::v_cmp_le_i32
;
641 case aco_opcode::v_cmp_lt_u32
:
642 op
= aco_opcode::v_cmp_gt_u32
;
644 case aco_opcode::v_cmp_ge_u32
:
645 op
= aco_opcode::v_cmp_le_u32
;
647 case aco_opcode::v_cmp_lt_f64
:
648 op
= aco_opcode::v_cmp_gt_f64
;
650 case aco_opcode::v_cmp_ge_f64
:
651 op
= aco_opcode::v_cmp_le_f64
;
653 case aco_opcode::v_cmp_lt_i64
:
654 op
= aco_opcode::v_cmp_gt_i64
;
656 case aco_opcode::v_cmp_ge_i64
:
657 op
= aco_opcode::v_cmp_le_i64
;
659 case aco_opcode::v_cmp_lt_u64
:
660 op
= aco_opcode::v_cmp_gt_u64
;
662 case aco_opcode::v_cmp_ge_u64
:
663 op
= aco_opcode::v_cmp_le_u64
;
665 default: /* eq and ne are commutative */
672 src1
= as_vgpr(ctx
, src1
);
676 Builder
bld(ctx
->program
, ctx
->block
);
677 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
680 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
682 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
683 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
684 Builder
bld(ctx
->program
, ctx
->block
);
686 assert(dst
.regClass() == bld
.lm
);
687 assert(src0
.type() == RegType::sgpr
);
688 assert(src1
.type() == RegType::sgpr
);
689 assert(src0
.regClass() == src1
.regClass());
691 /* Emit the SALU comparison instruction */
692 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
693 /* Turn the result into a per-lane bool */
694 bool_to_vector_condition(ctx
, cmp
, dst
);
697 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
698 aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
700 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: s32_op
;
701 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: v32_op
;
702 bool divergent_vals
= ctx
->divergent_vals
[instr
->dest
.dest
.ssa
.index
];
703 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
705 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
706 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
707 aco_opcode op
= use_valu
? v_op
: s_op
;
708 assert(op
!= aco_opcode::num_opcodes
);
709 assert(dst
.regClass() == ctx
->program
->lane_mask
);
712 emit_vopc_instruction(ctx
, instr
, op
, dst
);
714 emit_sopc_instruction(ctx
, instr
, op
, dst
);
717 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
719 Builder
bld(ctx
->program
, ctx
->block
);
720 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
721 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
723 assert(dst
.regClass() == bld
.lm
);
724 assert(src0
.regClass() == bld
.lm
);
725 assert(src1
.regClass() == bld
.lm
);
727 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
730 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
732 Builder
bld(ctx
->program
, ctx
->block
);
733 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
734 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
735 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
737 assert(cond
.regClass() == bld
.lm
);
739 if (dst
.type() == RegType::vgpr
) {
740 aco_ptr
<Instruction
> bcsel
;
741 if (dst
.regClass() == v2b
) {
742 then
= as_vgpr(ctx
, then
);
743 els
= as_vgpr(ctx
, els
);
745 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), els
, then
, cond
);
746 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
747 } else if (dst
.regClass() == v1
) {
748 then
= as_vgpr(ctx
, then
);
749 els
= as_vgpr(ctx
, els
);
751 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
752 } else if (dst
.regClass() == v2
) {
753 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
754 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
755 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
756 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
758 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
759 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
761 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
763 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
764 nir_print_instr(&instr
->instr
, stderr
);
765 fprintf(stderr
, "\n");
770 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
771 assert(dst
.regClass() == bld
.lm
);
772 assert(then
.regClass() == bld
.lm
);
773 assert(els
.regClass() == bld
.lm
);
776 if (!ctx
->divergent_vals
[instr
->src
[0].src
.ssa
->index
]) { /* uniform condition and values in sgpr */
777 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
778 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
779 assert(dst
.size() == then
.size());
780 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
781 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
783 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
784 nir_print_instr(&instr
->instr
, stderr
);
785 fprintf(stderr
, "\n");
790 /* divergent boolean bcsel
791 * this implements bcsel on bools: dst = s0 ? s1 : s2
792 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
793 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
795 if (cond
.id() != then
.id())
796 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
798 if (cond
.id() == els
.id())
799 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
801 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
802 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
805 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
806 aco_opcode op
, uint32_t undo
)
808 /* multiply by 16777216 to handle denormals */
809 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
810 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
811 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
812 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
813 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
815 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
817 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
820 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
822 if (ctx
->block
->fp_mode
.denorm32
== 0) {
823 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
827 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
830 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
832 if (ctx
->block
->fp_mode
.denorm32
== 0) {
833 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
837 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
840 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
842 if (ctx
->block
->fp_mode
.denorm32
== 0) {
843 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
847 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
850 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
852 if (ctx
->block
->fp_mode
.denorm32
== 0) {
853 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
857 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
860 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
862 if (ctx
->options
->chip_class
>= GFX7
)
863 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
865 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
866 /* TODO: create more efficient code! */
867 if (val
.type() == RegType::sgpr
)
868 val
= as_vgpr(ctx
, val
);
870 /* Split the input value. */
871 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
872 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
874 /* Extract the exponent and compute the unbiased value. */
875 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, bld
.def(v1
), val
);
877 /* Extract the fractional part. */
878 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
879 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
881 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
882 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
884 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
885 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
886 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
887 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
888 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
890 /* Get the sign bit. */
891 Temp sign
= bld
.vop2(aco_opcode::v_ashr_i32
, bld
.def(v1
), Operand(31u), val_hi
);
893 /* Decide the operation to apply depending on the unbiased exponent. */
894 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
895 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
896 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
897 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
898 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
899 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
901 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
904 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
906 if (ctx
->options
->chip_class
>= GFX7
)
907 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
909 /* GFX6 doesn't support V_FLOOR_F64, lower it. */
910 Temp src0
= as_vgpr(ctx
, val
);
912 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
913 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
915 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
916 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
917 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
919 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
920 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
921 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
922 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
924 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
925 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
927 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
929 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
930 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
932 return add
->definitions
[0].getTemp();
935 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
937 if (!instr
->dest
.dest
.is_ssa
) {
938 fprintf(stderr
, "nir alu dst not in ssa: ");
939 nir_print_instr(&instr
->instr
, stderr
);
940 fprintf(stderr
, "\n");
943 Builder
bld(ctx
->program
, ctx
->block
);
944 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
949 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
950 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
951 for (unsigned i
= 0; i
< num
; ++i
)
952 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
954 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
955 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
956 for (unsigned i
= 0; i
< num
; ++i
)
957 vec
->operands
[i
] = Operand
{elems
[i
]};
958 vec
->definitions
[0] = Definition(dst
);
959 ctx
->block
->instructions
.emplace_back(std::move(vec
));
960 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
962 // TODO: that is a bit suboptimal..
963 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
964 for (unsigned i
= 0; i
< num
- 1; ++i
)
965 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
966 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
967 for (unsigned i
= 0; i
< num
; ++i
) {
968 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
970 elems
[bit
/ 32] = elems
[i
];
972 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
973 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
974 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
978 bld
.copy(Definition(dst
), elems
[0]);
980 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
985 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
986 aco_ptr
<Instruction
> mov
;
987 if (dst
.type() == RegType::sgpr
) {
988 if (src
.type() == RegType::vgpr
)
989 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
990 else if (src
.regClass() == s1
)
991 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
992 else if (src
.regClass() == s2
)
993 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
995 unreachable("wrong src register class for nir_op_imov");
996 } else if (dst
.regClass() == v1
) {
997 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
998 } else if (dst
.regClass() == v2
) {
999 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1001 nir_print_instr(&instr
->instr
, stderr
);
1002 unreachable("Should have been lowered to scalar.");
1007 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1008 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1009 assert(src
.regClass() == bld
.lm
);
1010 assert(dst
.regClass() == bld
.lm
);
1011 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1012 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1013 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1014 } else if (dst
.regClass() == v1
) {
1015 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1016 } else if (dst
.type() == RegType::sgpr
) {
1017 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1018 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1020 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1021 nir_print_instr(&instr
->instr
, stderr
);
1022 fprintf(stderr
, "\n");
1027 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1028 if (dst
.regClass() == v1
) {
1029 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1030 } else if (dst
.regClass() == s1
) {
1031 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1032 } else if (dst
.size() == 2) {
1033 Temp src0
= bld
.tmp(dst
.type(), 1);
1034 Temp src1
= bld
.tmp(dst
.type(), 1);
1035 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1037 if (dst
.regClass() == s2
) {
1038 Temp carry
= bld
.tmp(s1
);
1039 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1040 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1041 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1043 Temp lower
= bld
.tmp(v1
);
1044 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1045 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1046 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1049 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1050 nir_print_instr(&instr
->instr
, stderr
);
1051 fprintf(stderr
, "\n");
1056 if (dst
.regClass() == s1
) {
1057 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1058 } else if (dst
.regClass() == v1
) {
1059 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1060 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1062 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1063 nir_print_instr(&instr
->instr
, stderr
);
1064 fprintf(stderr
, "\n");
1068 case nir_op_isign
: {
1069 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1070 if (dst
.regClass() == s1
) {
1071 Temp tmp
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
1072 Temp gtz
= bld
.sopc(aco_opcode::s_cmp_gt_i32
, bld
.def(s1
, scc
), src
, Operand(0u));
1073 bld
.sop2(aco_opcode::s_add_i32
, Definition(dst
), bld
.def(s1
, scc
), gtz
, tmp
);
1074 } else if (dst
.regClass() == s2
) {
1075 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1077 if (ctx
->program
->chip_class
>= GFX8
)
1078 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1080 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1081 /* SCC gets zero-extended to 64 bit */
1082 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1083 } else if (dst
.regClass() == v1
) {
1084 Temp tmp
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
1085 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1086 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(1u), tmp
, gtz
);
1087 } else if (dst
.regClass() == v2
) {
1088 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1089 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1090 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1091 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1092 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1093 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1095 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1096 nir_print_instr(&instr
->instr
, stderr
);
1097 fprintf(stderr
, "\n");
1102 if (dst
.regClass() == v1
) {
1103 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1104 } else if (dst
.regClass() == s1
) {
1105 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1107 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1108 nir_print_instr(&instr
->instr
, stderr
);
1109 fprintf(stderr
, "\n");
1114 if (dst
.regClass() == v1
) {
1115 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1116 } else if (dst
.regClass() == s1
) {
1117 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1119 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1120 nir_print_instr(&instr
->instr
, stderr
);
1121 fprintf(stderr
, "\n");
1126 if (dst
.regClass() == v1
) {
1127 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1128 } else if (dst
.regClass() == s1
) {
1129 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1131 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1132 nir_print_instr(&instr
->instr
, stderr
);
1133 fprintf(stderr
, "\n");
1138 if (dst
.regClass() == v1
) {
1139 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1140 } else if (dst
.regClass() == s1
) {
1141 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1143 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1144 nir_print_instr(&instr
->instr
, stderr
);
1145 fprintf(stderr
, "\n");
1150 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1151 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1152 } else if (dst
.regClass() == v1
) {
1153 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1154 } else if (dst
.regClass() == s1
) {
1155 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1156 } else if (dst
.regClass() == s2
) {
1157 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1159 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1160 nir_print_instr(&instr
->instr
, stderr
);
1161 fprintf(stderr
, "\n");
1166 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1167 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1168 } else if (dst
.regClass() == v1
) {
1169 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1170 } else if (dst
.regClass() == s1
) {
1171 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1172 } else if (dst
.regClass() == s2
) {
1173 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1175 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1176 nir_print_instr(&instr
->instr
, stderr
);
1177 fprintf(stderr
, "\n");
1182 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1183 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1184 } else if (dst
.regClass() == v1
) {
1185 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1186 } else if (dst
.regClass() == s1
) {
1187 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1188 } else if (dst
.regClass() == s2
) {
1189 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1191 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1192 nir_print_instr(&instr
->instr
, stderr
);
1193 fprintf(stderr
, "\n");
1198 if (dst
.regClass() == v1
) {
1199 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1200 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1201 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1202 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1203 } else if (dst
.regClass() == v2
) {
1204 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1205 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1206 } else if (dst
.regClass() == s2
) {
1207 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1208 } else if (dst
.regClass() == s1
) {
1209 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1211 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1212 nir_print_instr(&instr
->instr
, stderr
);
1213 fprintf(stderr
, "\n");
1218 if (dst
.regClass() == v1
) {
1219 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1220 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1221 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1222 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1223 } else if (dst
.regClass() == v2
) {
1224 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1225 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1226 } else if (dst
.regClass() == s1
) {
1227 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1228 } else if (dst
.regClass() == s2
) {
1229 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1231 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1232 nir_print_instr(&instr
->instr
, stderr
);
1233 fprintf(stderr
, "\n");
1238 if (dst
.regClass() == v1
) {
1239 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1240 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1241 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1242 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1243 } else if (dst
.regClass() == v2
) {
1244 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1245 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1246 } else if (dst
.regClass() == s1
) {
1247 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1248 } else if (dst
.regClass() == s2
) {
1249 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1251 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1252 nir_print_instr(&instr
->instr
, stderr
);
1253 fprintf(stderr
, "\n");
1257 case nir_op_find_lsb
: {
1258 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1259 if (src
.regClass() == s1
) {
1260 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1261 } else if (src
.regClass() == v1
) {
1262 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1263 } else if (src
.regClass() == s2
) {
1264 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1266 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1267 nir_print_instr(&instr
->instr
, stderr
);
1268 fprintf(stderr
, "\n");
1272 case nir_op_ufind_msb
:
1273 case nir_op_ifind_msb
: {
1274 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1275 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1276 aco_opcode op
= src
.regClass() == s2
?
1277 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1278 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1279 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1281 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1282 Operand(src
.size() * 32u - 1u), msb_rev
);
1283 Temp msb
= sub
.def(0).getTemp();
1284 Temp carry
= sub
.def(1).getTemp();
1286 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1287 } else if (src
.regClass() == v1
) {
1288 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1289 Temp msb_rev
= bld
.tmp(v1
);
1290 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1291 Temp msb
= bld
.tmp(v1
);
1292 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1293 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1295 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1296 nir_print_instr(&instr
->instr
, stderr
);
1297 fprintf(stderr
, "\n");
1301 case nir_op_bitfield_reverse
: {
1302 if (dst
.regClass() == s1
) {
1303 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1304 } else if (dst
.regClass() == v1
) {
1305 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1307 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1308 nir_print_instr(&instr
->instr
, stderr
);
1309 fprintf(stderr
, "\n");
1314 if (dst
.regClass() == s1
) {
1315 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1319 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1320 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1321 if (dst
.regClass() == v1
) {
1322 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1326 assert(src0
.size() == 2 && src1
.size() == 2);
1327 Temp src00
= bld
.tmp(src0
.type(), 1);
1328 Temp src01
= bld
.tmp(dst
.type(), 1);
1329 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1330 Temp src10
= bld
.tmp(src1
.type(), 1);
1331 Temp src11
= bld
.tmp(dst
.type(), 1);
1332 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1334 if (dst
.regClass() == s2
) {
1335 Temp carry
= bld
.tmp(s1
);
1336 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1337 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1338 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1339 } else if (dst
.regClass() == v2
) {
1340 Temp dst0
= bld
.tmp(v1
);
1341 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1342 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1343 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1345 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1346 nir_print_instr(&instr
->instr
, stderr
);
1347 fprintf(stderr
, "\n");
1351 case nir_op_uadd_sat
: {
1352 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1353 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1354 if (dst
.regClass() == s1
) {
1355 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1356 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1358 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1359 } else if (dst
.regClass() == v1
) {
1360 if (ctx
->options
->chip_class
>= GFX9
) {
1361 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1362 add
->operands
[0] = Operand(src0
);
1363 add
->operands
[1] = Operand(src1
);
1364 add
->definitions
[0] = Definition(dst
);
1366 ctx
->block
->instructions
.emplace_back(std::move(add
));
1368 if (src1
.regClass() != v1
)
1369 std::swap(src0
, src1
);
1370 assert(src1
.regClass() == v1
);
1371 Temp tmp
= bld
.tmp(v1
);
1372 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1373 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1376 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1377 nir_print_instr(&instr
->instr
, stderr
);
1378 fprintf(stderr
, "\n");
1382 case nir_op_uadd_carry
: {
1383 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1384 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1385 if (dst
.regClass() == s1
) {
1386 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1389 if (dst
.regClass() == v1
) {
1390 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1391 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1395 Temp src00
= bld
.tmp(src0
.type(), 1);
1396 Temp src01
= bld
.tmp(dst
.type(), 1);
1397 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1398 Temp src10
= bld
.tmp(src1
.type(), 1);
1399 Temp src11
= bld
.tmp(dst
.type(), 1);
1400 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1401 if (dst
.regClass() == s2
) {
1402 Temp carry
= bld
.tmp(s1
);
1403 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1404 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1405 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1406 } else if (dst
.regClass() == v2
) {
1407 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1408 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1409 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1410 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1412 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1413 nir_print_instr(&instr
->instr
, stderr
);
1414 fprintf(stderr
, "\n");
1419 if (dst
.regClass() == s1
) {
1420 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1424 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1425 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1426 if (dst
.regClass() == v1
) {
1427 bld
.vsub32(Definition(dst
), src0
, src1
);
1431 Temp src00
= bld
.tmp(src0
.type(), 1);
1432 Temp src01
= bld
.tmp(dst
.type(), 1);
1433 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1434 Temp src10
= bld
.tmp(src1
.type(), 1);
1435 Temp src11
= bld
.tmp(dst
.type(), 1);
1436 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1437 if (dst
.regClass() == s2
) {
1438 Temp carry
= bld
.tmp(s1
);
1439 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1440 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1441 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1442 } else if (dst
.regClass() == v2
) {
1443 Temp lower
= bld
.tmp(v1
);
1444 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1445 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1446 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1448 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1449 nir_print_instr(&instr
->instr
, stderr
);
1450 fprintf(stderr
, "\n");
1454 case nir_op_usub_borrow
: {
1455 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1456 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1457 if (dst
.regClass() == s1
) {
1458 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1460 } else if (dst
.regClass() == v1
) {
1461 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1462 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1466 Temp src00
= bld
.tmp(src0
.type(), 1);
1467 Temp src01
= bld
.tmp(dst
.type(), 1);
1468 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1469 Temp src10
= bld
.tmp(src1
.type(), 1);
1470 Temp src11
= bld
.tmp(dst
.type(), 1);
1471 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1472 if (dst
.regClass() == s2
) {
1473 Temp borrow
= bld
.tmp(s1
);
1474 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1475 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1476 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1477 } else if (dst
.regClass() == v2
) {
1478 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1479 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1480 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1481 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1483 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1484 nir_print_instr(&instr
->instr
, stderr
);
1485 fprintf(stderr
, "\n");
1490 if (dst
.regClass() == v1
) {
1491 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1492 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1493 } else if (dst
.regClass() == s1
) {
1494 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1496 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1497 nir_print_instr(&instr
->instr
, stderr
);
1498 fprintf(stderr
, "\n");
1502 case nir_op_umul_high
: {
1503 if (dst
.regClass() == v1
) {
1504 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1505 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1506 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1507 } else if (dst
.regClass() == s1
) {
1508 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1509 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1510 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1512 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1513 nir_print_instr(&instr
->instr
, stderr
);
1514 fprintf(stderr
, "\n");
1518 case nir_op_imul_high
: {
1519 if (dst
.regClass() == v1
) {
1520 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1521 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1522 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1523 } else if (dst
.regClass() == s1
) {
1524 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1525 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1526 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1528 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1529 nir_print_instr(&instr
->instr
, stderr
);
1530 fprintf(stderr
, "\n");
1535 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1536 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1537 if (dst
.regClass() == v2b
) {
1538 Temp tmp
= bld
.tmp(v1
);
1539 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, tmp
, true);
1540 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1541 } else if (dst
.regClass() == v1
) {
1542 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1543 } else if (dst
.regClass() == v2
) {
1544 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1546 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1547 nir_print_instr(&instr
->instr
, stderr
);
1548 fprintf(stderr
, "\n");
1553 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1554 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1555 if (dst
.regClass() == v2b
) {
1556 Temp tmp
= bld
.tmp(v1
);
1557 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, tmp
, true);
1558 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1559 } else if (dst
.regClass() == v1
) {
1560 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1561 } else if (dst
.regClass() == v2
) {
1562 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1564 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1565 nir_print_instr(&instr
->instr
, stderr
);
1566 fprintf(stderr
, "\n");
1571 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1572 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1573 if (dst
.regClass() == v2b
) {
1574 Temp tmp
= bld
.tmp(v1
);
1575 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1576 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, tmp
, false);
1578 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, tmp
, true);
1579 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1580 } else if (dst
.regClass() == v1
) {
1581 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1582 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1584 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1585 } else if (dst
.regClass() == v2
) {
1586 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1588 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1591 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1592 nir_print_instr(&instr
->instr
, stderr
);
1593 fprintf(stderr
, "\n");
1598 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1599 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1600 if (dst
.regClass() == v2b
) {
1601 // TODO: check fp_mode.must_flush_denorms16_64
1602 Temp tmp
= bld
.tmp(v1
);
1603 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, tmp
, true);
1604 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1605 } else if (dst
.regClass() == v1
) {
1606 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1607 } else if (dst
.regClass() == v2
) {
1608 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1609 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1610 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1612 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1615 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1616 nir_print_instr(&instr
->instr
, stderr
);
1617 fprintf(stderr
, "\n");
1622 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1623 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1624 if (dst
.regClass() == v2b
) {
1625 // TODO: check fp_mode.must_flush_denorms16_64
1626 Temp tmp
= bld
.tmp(v1
);
1627 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, tmp
, true);
1628 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1629 } else if (dst
.regClass() == v1
) {
1630 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1631 } else if (dst
.regClass() == v2
) {
1632 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1633 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1634 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1636 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1639 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1640 nir_print_instr(&instr
->instr
, stderr
);
1641 fprintf(stderr
, "\n");
1645 case nir_op_fmax3
: {
1646 if (dst
.size() == 1) {
1647 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1649 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1650 nir_print_instr(&instr
->instr
, stderr
);
1651 fprintf(stderr
, "\n");
1655 case nir_op_fmin3
: {
1656 if (dst
.size() == 1) {
1657 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1659 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1660 nir_print_instr(&instr
->instr
, stderr
);
1661 fprintf(stderr
, "\n");
1665 case nir_op_fmed3
: {
1666 if (dst
.size() == 1) {
1667 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1669 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1670 nir_print_instr(&instr
->instr
, stderr
);
1671 fprintf(stderr
, "\n");
1675 case nir_op_umax3
: {
1676 if (dst
.size() == 1) {
1677 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1679 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1680 nir_print_instr(&instr
->instr
, stderr
);
1681 fprintf(stderr
, "\n");
1685 case nir_op_umin3
: {
1686 if (dst
.size() == 1) {
1687 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1689 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1690 nir_print_instr(&instr
->instr
, stderr
);
1691 fprintf(stderr
, "\n");
1695 case nir_op_umed3
: {
1696 if (dst
.size() == 1) {
1697 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1699 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1700 nir_print_instr(&instr
->instr
, stderr
);
1701 fprintf(stderr
, "\n");
1705 case nir_op_imax3
: {
1706 if (dst
.size() == 1) {
1707 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1709 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1710 nir_print_instr(&instr
->instr
, stderr
);
1711 fprintf(stderr
, "\n");
1715 case nir_op_imin3
: {
1716 if (dst
.size() == 1) {
1717 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1719 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1720 nir_print_instr(&instr
->instr
, stderr
);
1721 fprintf(stderr
, "\n");
1725 case nir_op_imed3
: {
1726 if (dst
.size() == 1) {
1727 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1729 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1730 nir_print_instr(&instr
->instr
, stderr
);
1731 fprintf(stderr
, "\n");
1735 case nir_op_cube_face_coord
: {
1736 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1737 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1738 emit_extract_vector(ctx
, in
, 1, v1
),
1739 emit_extract_vector(ctx
, in
, 2, v1
) };
1740 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1741 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1742 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1743 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1744 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1745 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1746 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1749 case nir_op_cube_face_index
: {
1750 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1751 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1752 emit_extract_vector(ctx
, in
, 1, v1
),
1753 emit_extract_vector(ctx
, in
, 2, v1
) };
1754 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1757 case nir_op_bcsel
: {
1758 emit_bcsel(ctx
, instr
, dst
);
1762 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1763 if (dst
.regClass() == v2b
) {
1764 Temp tmp
= bld
.vop1(aco_opcode::v_rsq_f16
, bld
.def(v1
), src
);
1765 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1766 } else if (dst
.regClass() == v1
) {
1767 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1768 } else if (dst
.regClass() == v2
) {
1769 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1771 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1772 nir_print_instr(&instr
->instr
, stderr
);
1773 fprintf(stderr
, "\n");
1778 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1779 if (dst
.regClass() == v2b
) {
1780 Temp tmp
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1781 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1782 } else if (dst
.regClass() == v1
) {
1783 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1784 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1785 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1786 } else if (dst
.regClass() == v2
) {
1787 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1788 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1789 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1790 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1791 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1792 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1794 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1795 nir_print_instr(&instr
->instr
, stderr
);
1796 fprintf(stderr
, "\n");
1801 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1802 if (dst
.regClass() == v2b
) {
1803 Temp tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1804 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1805 } else if (dst
.regClass() == v1
) {
1806 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1807 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1808 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1809 } else if (dst
.regClass() == v2
) {
1810 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1811 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1812 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1813 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1814 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1815 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1817 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1818 nir_print_instr(&instr
->instr
, stderr
);
1819 fprintf(stderr
, "\n");
1824 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1825 if (dst
.regClass() == v2b
) {
1826 Temp one
= bld
.copy(bld
.def(s1
), Operand(0x3c00u
));
1827 Temp tmp
= bld
.vop3(aco_opcode::v_med3_f16
, bld
.def(v1
), Operand(0u), one
, src
);
1828 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1829 } else if (dst
.regClass() == v1
) {
1830 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1831 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1832 // TODO: confirm that this holds under any circumstances
1833 } else if (dst
.regClass() == v2
) {
1834 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1835 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1838 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1839 nir_print_instr(&instr
->instr
, stderr
);
1840 fprintf(stderr
, "\n");
1844 case nir_op_flog2
: {
1845 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1846 if (dst
.regClass() == v2b
) {
1847 Temp tmp
= bld
.vop1(aco_opcode::v_log_f16
, bld
.def(v1
), src
);
1848 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1849 } else if (dst
.regClass() == v1
) {
1850 emit_log2(ctx
, bld
, Definition(dst
), src
);
1852 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1853 nir_print_instr(&instr
->instr
, stderr
);
1854 fprintf(stderr
, "\n");
1859 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1860 if (dst
.regClass() == v2b
) {
1861 Temp tmp
= bld
.vop1(aco_opcode::v_rcp_f16
, bld
.def(v1
), src
);
1862 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1863 } else if (dst
.regClass() == v1
) {
1864 emit_rcp(ctx
, bld
, Definition(dst
), src
);
1865 } else if (dst
.regClass() == v2
) {
1866 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1868 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1869 nir_print_instr(&instr
->instr
, stderr
);
1870 fprintf(stderr
, "\n");
1874 case nir_op_fexp2
: {
1875 if (dst
.regClass() == v2b
) {
1876 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1877 Temp tmp
= bld
.vop1(aco_opcode::v_exp_f16
, bld
.def(v1
), src
);
1878 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1879 } else if (dst
.regClass() == v1
) {
1880 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1882 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1883 nir_print_instr(&instr
->instr
, stderr
);
1884 fprintf(stderr
, "\n");
1888 case nir_op_fsqrt
: {
1889 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1890 if (dst
.regClass() == v2b
) {
1891 Temp tmp
= bld
.vop1(aco_opcode::v_sqrt_f16
, bld
.def(v1
), src
);
1892 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1893 } else if (dst
.regClass() == v1
) {
1894 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
1895 } else if (dst
.regClass() == v2
) {
1896 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1898 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1899 nir_print_instr(&instr
->instr
, stderr
);
1900 fprintf(stderr
, "\n");
1904 case nir_op_ffract
: {
1905 if (dst
.regClass() == v2b
) {
1906 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1907 Temp tmp
= bld
.vop1(aco_opcode::v_fract_f16
, bld
.def(v1
), src
);
1908 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1909 } else if (dst
.regClass() == v1
) {
1910 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1911 } else if (dst
.regClass() == v2
) {
1912 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1914 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1915 nir_print_instr(&instr
->instr
, stderr
);
1916 fprintf(stderr
, "\n");
1920 case nir_op_ffloor
: {
1921 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1922 if (dst
.regClass() == v2b
) {
1923 Temp tmp
= bld
.vop1(aco_opcode::v_floor_f16
, bld
.def(v1
), src
);
1924 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1925 } else if (dst
.regClass() == v1
) {
1926 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
1927 } else if (dst
.regClass() == v2
) {
1928 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
1930 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1931 nir_print_instr(&instr
->instr
, stderr
);
1932 fprintf(stderr
, "\n");
1936 case nir_op_fceil
: {
1937 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1938 if (dst
.regClass() == v2b
) {
1939 Temp tmp
= bld
.vop1(aco_opcode::v_ceil_f16
, bld
.def(v1
), src0
);
1940 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1941 } else if (dst
.regClass() == v1
) {
1942 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
1943 } else if (dst
.regClass() == v2
) {
1944 if (ctx
->options
->chip_class
>= GFX7
) {
1945 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
1947 /* GFX6 doesn't support V_CEIL_F64, lower it. */
1948 /* trunc = trunc(src0)
1949 * if (src0 > 0.0 && src0 != trunc)
1952 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
1953 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
1954 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
1955 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
1956 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
1957 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
1958 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
1961 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1962 nir_print_instr(&instr
->instr
, stderr
);
1963 fprintf(stderr
, "\n");
1967 case nir_op_ftrunc
: {
1968 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1969 if (dst
.regClass() == v2b
) {
1970 Temp tmp
= bld
.vop1(aco_opcode::v_trunc_f16
, bld
.def(v1
), src
);
1971 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1972 } else if (dst
.regClass() == v1
) {
1973 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
1974 } else if (dst
.regClass() == v2
) {
1975 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
1977 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1978 nir_print_instr(&instr
->instr
, stderr
);
1979 fprintf(stderr
, "\n");
1983 case nir_op_fround_even
: {
1984 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1985 if (dst
.regClass() == v2b
) {
1986 Temp tmp
= bld
.vop1(aco_opcode::v_rndne_f16
, bld
.def(v1
), src0
);
1987 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1988 } else if (dst
.regClass() == v1
) {
1989 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
1990 } else if (dst
.regClass() == v2
) {
1991 if (ctx
->options
->chip_class
>= GFX7
) {
1992 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
1994 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
1995 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
1996 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
1998 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
1999 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2000 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2001 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2002 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2003 tmp
= sub
->definitions
[0].getTemp();
2005 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2006 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2007 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2008 Temp cond
= vop3
->definitions
[0].getTemp();
2010 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2011 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2012 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2013 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2015 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2018 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2019 nir_print_instr(&instr
->instr
, stderr
);
2020 fprintf(stderr
, "\n");
2026 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2027 aco_ptr
<Instruction
> norm
;
2028 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2029 if (dst
.regClass() == v2b
) {
2030 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2031 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2032 tmp
= bld
.vop1(opcode
, bld
.def(v1
), tmp
);
2033 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2034 } else if (dst
.regClass() == v1
) {
2035 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2037 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2038 if (ctx
->options
->chip_class
< GFX9
)
2039 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2041 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2042 bld
.vop1(opcode
, Definition(dst
), tmp
);
2044 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2045 nir_print_instr(&instr
->instr
, stderr
);
2046 fprintf(stderr
, "\n");
2050 case nir_op_ldexp
: {
2051 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2052 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2053 if (dst
.regClass() == v2b
) {
2054 Temp tmp
= bld
.tmp(v1
);
2055 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, tmp
, false);
2056 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2057 } else if (dst
.regClass() == v1
) {
2058 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2059 } else if (dst
.regClass() == v2
) {
2060 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2062 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2063 nir_print_instr(&instr
->instr
, stderr
);
2064 fprintf(stderr
, "\n");
2068 case nir_op_frexp_sig
: {
2069 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2070 if (dst
.regClass() == v2b
) {
2071 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_mant_f16
, bld
.def(v1
), src
);
2072 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2073 } else if (dst
.regClass() == v1
) {
2074 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2075 } else if (dst
.regClass() == v2
) {
2076 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2078 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2079 nir_print_instr(&instr
->instr
, stderr
);
2080 fprintf(stderr
, "\n");
2084 case nir_op_frexp_exp
: {
2085 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2086 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2087 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2088 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), tmp
, Operand(0u));
2089 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2090 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2091 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2092 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2094 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2095 nir_print_instr(&instr
->instr
, stderr
);
2096 fprintf(stderr
, "\n");
2100 case nir_op_fsign
: {
2101 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2102 if (dst
.regClass() == v2b
) {
2103 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2104 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2105 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2106 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2107 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2108 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), minus_one
, src
, cond
);
2109 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2110 } else if (dst
.regClass() == v1
) {
2111 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2112 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2113 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2114 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2115 } else if (dst
.regClass() == v2
) {
2116 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2117 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2118 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2120 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2121 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2122 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2124 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2126 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2127 nir_print_instr(&instr
->instr
, stderr
);
2128 fprintf(stderr
, "\n");
2133 case nir_op_f2f16_rtne
: {
2134 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2135 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2136 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2137 src
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2138 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2141 case nir_op_f2f16_rtz
: {
2142 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2143 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2144 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2145 src
= bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, bld
.def(v1
), src
, Operand(0u));
2146 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2149 case nir_op_f2f32
: {
2150 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2151 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2152 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2153 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2155 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2156 nir_print_instr(&instr
->instr
, stderr
);
2157 fprintf(stderr
, "\n");
2161 case nir_op_f2f64
: {
2162 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2163 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2164 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2165 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2168 case nir_op_i2f32
: {
2169 assert(dst
.size() == 1);
2170 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_i32
, dst
);
2173 case nir_op_i2f64
: {
2174 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2175 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_i32
, dst
);
2176 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2177 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2178 RegClass rc
= RegClass(src
.type(), 1);
2179 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2180 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2181 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2182 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2183 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2184 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2187 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2188 nir_print_instr(&instr
->instr
, stderr
);
2189 fprintf(stderr
, "\n");
2193 case nir_op_u2f32
: {
2194 assert(dst
.size() == 1);
2195 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_u32
, dst
);
2198 case nir_op_u2f64
: {
2199 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2200 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_u32
, dst
);
2201 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2202 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2203 RegClass rc
= RegClass(src
.type(), 1);
2204 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2205 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2206 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2207 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2208 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2209 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2211 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2212 nir_print_instr(&instr
->instr
, stderr
);
2213 fprintf(stderr
, "\n");
2217 case nir_op_f2i16
: {
2218 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2219 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2220 src
= bld
.vop1(aco_opcode::v_cvt_i16_f16
, bld
.def(v1
), src
);
2221 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2222 src
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
);
2224 src
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
);
2226 if (dst
.type() == RegType::vgpr
)
2227 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2229 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2232 case nir_op_f2u16
: {
2233 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2234 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2235 src
= bld
.vop1(aco_opcode::v_cvt_u16_f16
, bld
.def(v1
), src
);
2236 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2237 src
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
);
2239 src
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
);
2241 if (dst
.type() == RegType::vgpr
)
2242 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2244 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2247 case nir_op_f2i32
: {
2248 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2249 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2250 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2251 if (dst
.type() == RegType::vgpr
) {
2252 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2254 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2255 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2257 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2258 if (dst
.type() == RegType::vgpr
)
2259 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), src
);
2261 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2262 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
));
2264 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2265 if (dst
.type() == RegType::vgpr
)
2266 bld
.vop1(aco_opcode::v_cvt_i32_f64
, Definition(dst
), src
);
2268 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2269 bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
));
2272 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2273 nir_print_instr(&instr
->instr
, stderr
);
2274 fprintf(stderr
, "\n");
2278 case nir_op_f2u32
: {
2279 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2280 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2281 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2282 if (dst
.type() == RegType::vgpr
) {
2283 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2285 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2286 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2288 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2289 if (dst
.type() == RegType::vgpr
)
2290 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), src
);
2292 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2293 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
));
2295 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2296 if (dst
.type() == RegType::vgpr
)
2297 bld
.vop1(aco_opcode::v_cvt_u32_f64
, Definition(dst
), src
);
2299 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2300 bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
));
2303 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2304 nir_print_instr(&instr
->instr
, stderr
);
2305 fprintf(stderr
, "\n");
2309 case nir_op_f2i64
: {
2310 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2311 if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::vgpr
) {
2312 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2313 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2314 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2315 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2316 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2317 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2318 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2319 Temp new_exponent
= bld
.tmp(v1
);
2320 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2321 if (ctx
->program
->chip_class
>= GFX8
)
2322 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2324 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2325 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2326 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2327 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2328 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2329 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2330 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2331 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2332 Temp new_lower
= bld
.tmp(v1
);
2333 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2334 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2335 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2337 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::sgpr
) {
2338 if (src
.type() == RegType::vgpr
)
2339 src
= bld
.as_uniform(src
);
2340 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2341 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2342 exponent
= bld
.sop2(aco_opcode::s_max_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2343 exponent
= bld
.sop2(aco_opcode::s_min_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2344 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2345 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2346 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2347 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2348 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2349 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2350 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2351 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2352 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2353 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2354 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2355 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2356 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2357 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2358 Temp borrow
= bld
.tmp(s1
);
2359 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2360 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2361 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2363 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2364 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2365 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2366 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2367 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2368 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2369 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2370 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2371 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2372 if (dst
.type() == RegType::sgpr
) {
2373 lower
= bld
.as_uniform(lower
);
2374 upper
= bld
.as_uniform(upper
);
2376 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2379 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2380 nir_print_instr(&instr
->instr
, stderr
);
2381 fprintf(stderr
, "\n");
2385 case nir_op_f2u64
: {
2386 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2387 if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::vgpr
) {
2388 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2389 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2390 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2391 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2392 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2393 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2394 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2395 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2396 Temp new_exponent
= bld
.tmp(v1
);
2397 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2398 if (ctx
->program
->chip_class
>= GFX8
)
2399 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2401 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2402 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2403 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2404 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2405 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2406 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2407 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2408 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2410 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::sgpr
) {
2411 if (src
.type() == RegType::vgpr
)
2412 src
= bld
.as_uniform(src
);
2413 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2414 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2415 exponent
= bld
.sop2(aco_opcode::s_max_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2416 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2417 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2418 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2419 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2420 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2421 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2422 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2423 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2424 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2425 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2426 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2427 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2428 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2429 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2430 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2432 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2433 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2434 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2435 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2436 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2437 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2438 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2439 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2440 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2441 if (dst
.type() == RegType::sgpr
) {
2442 lower
= bld
.as_uniform(lower
);
2443 upper
= bld
.as_uniform(upper
);
2445 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2448 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2449 nir_print_instr(&instr
->instr
, stderr
);
2450 fprintf(stderr
, "\n");
2454 case nir_op_b2f32
: {
2455 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2456 assert(src
.regClass() == bld
.lm
);
2458 if (dst
.regClass() == s1
) {
2459 src
= bool_to_scalar_condition(ctx
, src
);
2460 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2461 } else if (dst
.regClass() == v1
) {
2462 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2464 unreachable("Wrong destination register class for nir_op_b2f32.");
2468 case nir_op_b2f64
: {
2469 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2470 assert(src
.regClass() == bld
.lm
);
2472 if (dst
.regClass() == s2
) {
2473 src
= bool_to_scalar_condition(ctx
, src
);
2474 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2475 } else if (dst
.regClass() == v2
) {
2476 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2477 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2478 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2480 unreachable("Wrong destination register class for nir_op_b2f64.");
2486 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2487 /* we can actually just say dst = src */
2488 if (src
.regClass() == s1
)
2489 bld
.copy(Definition(dst
), src
);
2491 emit_extract_vector(ctx
, src
, 0, dst
);
2494 case nir_op_i2i16
: {
2495 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2496 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2497 if (dst
.regClass() == s1
) {
2498 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(dst
), Operand(src
));
2500 assert(src
.regClass() == v1b
);
2501 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2502 sdwa
->operands
[0] = Operand(src
);
2503 sdwa
->definitions
[0] = Definition(dst
);
2504 sdwa
->sel
[0] = sdwa_sbyte
;
2505 sdwa
->dst_sel
= sdwa_sword
;
2506 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2509 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2510 /* we can actually just say dst = src */
2511 if (src
.regClass() == s1
)
2512 bld
.copy(Definition(dst
), src
);
2514 emit_extract_vector(ctx
, src
, 0, dst
);
2518 case nir_op_u2u16
: {
2519 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2520 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2521 if (dst
.regClass() == s1
)
2522 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFu
), src
);
2524 assert(src
.regClass() == v1b
);
2525 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2526 sdwa
->operands
[0] = Operand(src
);
2527 sdwa
->definitions
[0] = Definition(dst
);
2528 sdwa
->sel
[0] = sdwa_ubyte
;
2529 sdwa
->dst_sel
= sdwa_uword
;
2530 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2533 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2534 /* we can actually just say dst = src */
2535 if (src
.regClass() == s1
)
2536 bld
.copy(Definition(dst
), src
);
2538 emit_extract_vector(ctx
, src
, 0, dst
);
2542 case nir_op_i2i32
: {
2543 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2544 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2545 if (dst
.regClass() == s1
) {
2546 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(dst
), Operand(src
));
2548 assert(src
.regClass() == v1b
);
2549 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2550 sdwa
->operands
[0] = Operand(src
);
2551 sdwa
->definitions
[0] = Definition(dst
);
2552 sdwa
->sel
[0] = sdwa_sbyte
;
2553 sdwa
->dst_sel
= sdwa_sdword
;
2554 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2556 } else if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2557 if (dst
.regClass() == s1
) {
2558 bld
.sop1(aco_opcode::s_sext_i32_i16
, Definition(dst
), Operand(src
));
2560 assert(src
.regClass() == v2b
);
2561 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2562 sdwa
->operands
[0] = Operand(src
);
2563 sdwa
->definitions
[0] = Definition(dst
);
2564 sdwa
->sel
[0] = sdwa_sword
;
2565 sdwa
->dst_sel
= sdwa_udword
;
2566 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2568 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2569 /* we can actually just say dst = src, as it would map the lower register */
2570 emit_extract_vector(ctx
, src
, 0, dst
);
2572 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2573 nir_print_instr(&instr
->instr
, stderr
);
2574 fprintf(stderr
, "\n");
2578 case nir_op_u2u32
: {
2579 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2580 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2581 if (dst
.regClass() == s1
)
2582 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFu
), src
);
2584 assert(src
.regClass() == v1b
);
2585 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2586 sdwa
->operands
[0] = Operand(src
);
2587 sdwa
->definitions
[0] = Definition(dst
);
2588 sdwa
->sel
[0] = sdwa_ubyte
;
2589 sdwa
->dst_sel
= sdwa_udword
;
2590 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2592 } else if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2593 if (dst
.regClass() == s1
) {
2594 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFFFu
), src
);
2596 assert(src
.regClass() == v2b
);
2597 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2598 sdwa
->operands
[0] = Operand(src
);
2599 sdwa
->definitions
[0] = Definition(dst
);
2600 sdwa
->sel
[0] = sdwa_uword
;
2601 sdwa
->dst_sel
= sdwa_udword
;
2602 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2604 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2605 /* we can actually just say dst = src, as it would map the lower register */
2606 emit_extract_vector(ctx
, src
, 0, dst
);
2608 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2609 nir_print_instr(&instr
->instr
, stderr
);
2610 fprintf(stderr
, "\n");
2614 case nir_op_i2i64
: {
2615 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2616 if (src
.regClass() == s1
) {
2617 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2618 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, high
);
2619 } else if (src
.regClass() == v1
) {
2620 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2621 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, high
);
2623 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2624 nir_print_instr(&instr
->instr
, stderr
);
2625 fprintf(stderr
, "\n");
2629 case nir_op_u2u64
: {
2630 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2631 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2632 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, Operand(0u));
2634 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2635 nir_print_instr(&instr
->instr
, stderr
);
2636 fprintf(stderr
, "\n");
2641 case nir_op_b2i32
: {
2642 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2643 assert(src
.regClass() == bld
.lm
);
2645 if (dst
.regClass() == s1
) {
2646 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2647 bool_to_scalar_condition(ctx
, src
, dst
);
2648 } else if (dst
.regClass() == v1
) {
2649 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2651 unreachable("Invalid register class for b2i32");
2657 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2658 assert(dst
.regClass() == bld
.lm
);
2660 if (src
.type() == RegType::vgpr
) {
2661 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2662 assert(dst
.regClass() == bld
.lm
);
2663 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2664 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2666 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2668 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2669 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2671 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2672 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2674 bool_to_vector_condition(ctx
, tmp
, dst
);
2678 case nir_op_pack_64_2x32_split
: {
2679 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2680 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2682 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2685 case nir_op_unpack_64_2x32_split_x
:
2686 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2688 case nir_op_unpack_64_2x32_split_y
:
2689 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2691 case nir_op_unpack_32_2x16_split_x
:
2692 if (dst
.type() == RegType::vgpr
) {
2693 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2695 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2698 case nir_op_unpack_32_2x16_split_y
:
2699 if (dst
.type() == RegType::vgpr
) {
2700 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2702 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2705 case nir_op_pack_32_2x16_split
: {
2706 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2707 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2708 if (dst
.regClass() == v1
) {
2709 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2711 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2712 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2713 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2717 case nir_op_pack_half_2x16
: {
2718 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2720 if (dst
.regClass() == v1
) {
2721 Temp src0
= bld
.tmp(v1
);
2722 Temp src1
= bld
.tmp(v1
);
2723 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2724 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2725 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2727 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2728 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2729 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2731 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2732 nir_print_instr(&instr
->instr
, stderr
);
2733 fprintf(stderr
, "\n");
2737 case nir_op_unpack_half_2x16_split_x
: {
2738 if (dst
.regClass() == v1
) {
2739 Builder
bld(ctx
->program
, ctx
->block
);
2740 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2742 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2743 nir_print_instr(&instr
->instr
, stderr
);
2744 fprintf(stderr
, "\n");
2748 case nir_op_unpack_half_2x16_split_y
: {
2749 if (dst
.regClass() == v1
) {
2750 Builder
bld(ctx
->program
, ctx
->block
);
2751 /* TODO: use SDWA here */
2752 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2753 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2755 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2756 nir_print_instr(&instr
->instr
, stderr
);
2757 fprintf(stderr
, "\n");
2761 case nir_op_fquantize2f16
: {
2762 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2763 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2766 if (ctx
->program
->chip_class
>= GFX8
) {
2767 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2768 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2769 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2771 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2772 * so compare the result and flush to 0 if it's smaller.
2774 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2775 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2776 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2777 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2778 cmp_res
= vop3
->definitions
[0].getTemp();
2781 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2782 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2783 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2785 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2790 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2791 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2793 if (dst
.regClass() == s1
) {
2794 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2795 } else if (dst
.regClass() == v1
) {
2796 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2798 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2799 nir_print_instr(&instr
->instr
, stderr
);
2800 fprintf(stderr
, "\n");
2804 case nir_op_bitfield_select
: {
2805 /* (mask & insert) | (~mask & base) */
2806 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2807 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2808 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2810 /* dst = (insert & bitmask) | (base & ~bitmask) */
2811 if (dst
.regClass() == s1
) {
2812 aco_ptr
<Instruction
> sop2
;
2813 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2814 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2816 if (const_insert
&& const_bitmask
) {
2817 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2819 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2820 lhs
= Operand(insert
);
2824 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2825 if (const_base
&& const_bitmask
) {
2826 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2828 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2829 rhs
= Operand(base
);
2832 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2834 } else if (dst
.regClass() == v1
) {
2835 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2836 base
= as_vgpr(ctx
, base
);
2837 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2838 insert
= as_vgpr(ctx
, insert
);
2840 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2843 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2844 nir_print_instr(&instr
->instr
, stderr
);
2845 fprintf(stderr
, "\n");
2851 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2852 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2853 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2855 if (dst
.type() == RegType::sgpr
) {
2857 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2858 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2859 if (const_offset
&& const_bits
) {
2860 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2861 extract
= Operand(const_extract
);
2865 width
= Operand(const_bits
->u32
<< 16);
2867 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2869 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2873 if (dst
.regClass() == s1
) {
2874 if (instr
->op
== nir_op_ubfe
)
2875 opcode
= aco_opcode::s_bfe_u32
;
2877 opcode
= aco_opcode::s_bfe_i32
;
2878 } else if (dst
.regClass() == s2
) {
2879 if (instr
->op
== nir_op_ubfe
)
2880 opcode
= aco_opcode::s_bfe_u64
;
2882 opcode
= aco_opcode::s_bfe_i64
;
2884 unreachable("Unsupported BFE bit size");
2887 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2891 if (dst
.regClass() == v1
) {
2892 if (instr
->op
== nir_op_ubfe
)
2893 opcode
= aco_opcode::v_bfe_u32
;
2895 opcode
= aco_opcode::v_bfe_i32
;
2897 unreachable("Unsupported BFE bit size");
2900 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2904 case nir_op_bit_count
: {
2905 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2906 if (src
.regClass() == s1
) {
2907 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2908 } else if (src
.regClass() == v1
) {
2909 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2910 } else if (src
.regClass() == v2
) {
2911 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2912 emit_extract_vector(ctx
, src
, 1, v1
),
2913 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2914 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2915 } else if (src
.regClass() == s2
) {
2916 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2918 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2919 nir_print_instr(&instr
->instr
, stderr
);
2920 fprintf(stderr
, "\n");
2925 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2929 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2933 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2937 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2941 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2945 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2949 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2950 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2952 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2953 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2957 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2958 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2960 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2961 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2965 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2969 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2974 case nir_op_fddx_fine
:
2975 case nir_op_fddy_fine
:
2976 case nir_op_fddx_coarse
:
2977 case nir_op_fddy_coarse
: {
2978 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2979 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2980 if (instr
->op
== nir_op_fddx_fine
) {
2981 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2982 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2983 } else if (instr
->op
== nir_op_fddy_fine
) {
2984 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2985 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2987 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2988 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2989 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2991 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2995 if (ctx
->program
->chip_class
>= GFX8
) {
2996 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2997 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2999 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
3000 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
3001 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
3003 emit_wqm(ctx
, tmp
, dst
, true);
3007 fprintf(stderr
, "Unknown NIR ALU instr: ");
3008 nir_print_instr(&instr
->instr
, stderr
);
3009 fprintf(stderr
, "\n");
3013 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
3015 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
3017 // TODO: we really want to have the resulting type as this would allow for 64bit literals
3018 // which get truncated the lsb if double and msb if int
3019 // for now, we only use s_mov_b64 with 64bit inline constants
3020 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
3021 assert(dst
.type() == RegType::sgpr
);
3023 Builder
bld(ctx
->program
, ctx
->block
);
3025 if (instr
->def
.bit_size
== 1) {
3026 assert(dst
.regClass() == bld
.lm
);
3027 int val
= instr
->value
[0].b
? -1 : 0;
3028 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
3029 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
3030 } else if (dst
.size() == 1) {
3031 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
3033 assert(dst
.size() != 1);
3034 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3035 if (instr
->def
.bit_size
== 64)
3036 for (unsigned i
= 0; i
< dst
.size(); i
++)
3037 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
3039 for (unsigned i
= 0; i
< dst
.size(); i
++)
3040 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3042 vec
->definitions
[0] = Definition(dst
);
3043 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3047 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3049 uint32_t new_mask
= 0;
3050 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3051 if (mask
& (1u << i
))
3052 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3056 Operand
load_lds_size_m0(isel_context
*ctx
)
3058 /* TODO: m0 does not need to be initialized on GFX9+ */
3059 Builder
bld(ctx
->program
, ctx
->block
);
3060 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3063 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3064 Temp address
, unsigned base_offset
, unsigned align
)
3066 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
3068 Builder
bld(ctx
->program
, ctx
->block
);
3070 Operand m
= load_lds_size_m0(ctx
);
3072 unsigned num_components
= dst
.size() * 4u / elem_size_bytes
;
3073 unsigned bytes_read
= 0;
3074 unsigned result_size
= 0;
3075 unsigned total_bytes
= num_components
* elem_size_bytes
;
3076 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> result
;
3077 bool large_ds_read
= ctx
->options
->chip_class
>= GFX7
;
3078 bool usable_read2
= ctx
->options
->chip_class
>= GFX7
;
3080 while (bytes_read
< total_bytes
) {
3081 unsigned todo
= total_bytes
- bytes_read
;
3082 bool aligned8
= bytes_read
% 8 == 0 && align
% 8 == 0;
3083 bool aligned16
= bytes_read
% 16 == 0 && align
% 16 == 0;
3085 aco_opcode op
= aco_opcode::last_opcode
;
3087 if (todo
>= 16 && aligned16
&& large_ds_read
) {
3088 op
= aco_opcode::ds_read_b128
;
3090 } else if (todo
>= 16 && aligned8
&& usable_read2
) {
3091 op
= aco_opcode::ds_read2_b64
;
3094 } else if (todo
>= 12 && aligned16
&& large_ds_read
) {
3095 op
= aco_opcode::ds_read_b96
;
3097 } else if (todo
>= 8 && aligned8
) {
3098 op
= aco_opcode::ds_read_b64
;
3100 } else if (todo
>= 8 && usable_read2
) {
3101 op
= aco_opcode::ds_read2_b32
;
3104 } else if (todo
>= 4) {
3105 op
= aco_opcode::ds_read_b32
;
3110 assert(todo
% elem_size_bytes
== 0);
3111 unsigned num_elements
= todo
/ elem_size_bytes
;
3112 unsigned offset
= base_offset
+ bytes_read
;
3113 unsigned max_offset
= read2
? 1019 : 65535;
3115 Temp address_offset
= address
;
3116 if (offset
> max_offset
) {
3117 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3118 offset
= bytes_read
;
3120 assert(offset
<= max_offset
); /* bytes_read shouldn't be large enough for this to happen */
3123 if (num_components
== 1 && dst
.type() == RegType::vgpr
)
3126 res
= bld
.tmp(RegClass(RegType::vgpr
, todo
/ 4));
3129 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
/ (todo
/ 2), (offset
/ (todo
/ 2)) + 1);
3131 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
);
3133 if (num_components
== 1) {
3134 assert(todo
== total_bytes
);
3135 if (dst
.type() == RegType::sgpr
)
3136 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), res
);
3140 if (dst
.type() == RegType::sgpr
) {
3141 Temp new_res
= bld
.tmp(RegType::sgpr
, res
.size());
3142 expand_vector(ctx
, res
, new_res
, res
.size(), (1 << res
.size()) - 1);
3146 if (num_elements
== 1) {
3147 result
[result_size
++] = res
;
3149 assert(res
!= dst
&& res
.size() % num_elements
== 0);
3150 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_elements
)};
3151 split
->operands
[0] = Operand(res
);
3152 for (unsigned i
= 0; i
< num_elements
; i
++)
3153 split
->definitions
[i
] = Definition(result
[result_size
++] = bld
.tmp(res
.type(), elem_size_bytes
/ 4));
3154 ctx
->block
->instructions
.emplace_back(std::move(split
));
3160 assert(result_size
== num_components
&& result_size
> 1);
3161 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, result_size
, 1)};
3162 for (unsigned i
= 0; i
< result_size
; i
++)
3163 vec
->operands
[i
] = Operand(result
[i
]);
3164 vec
->definitions
[0] = Definition(dst
);
3165 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3166 ctx
->allocated_vec
.emplace(dst
.id(), result
);
3171 Temp
extract_subvector(isel_context
*ctx
, Temp data
, unsigned start
, unsigned size
, RegType type
)
3173 if (start
== 0 && size
== data
.size())
3174 return type
== RegType::vgpr
? as_vgpr(ctx
, data
) : data
;
3176 unsigned size_hint
= 1;
3177 auto it
= ctx
->allocated_vec
.find(data
.id());
3178 if (it
!= ctx
->allocated_vec
.end())
3179 size_hint
= it
->second
[0].size();
3180 if (size
% size_hint
|| start
% size_hint
)
3187 for (unsigned i
= 0; i
< size
; i
++)
3188 elems
[i
] = emit_extract_vector(ctx
, data
, start
+ i
, RegClass(type
, size_hint
));
3191 return type
== RegType::vgpr
? as_vgpr(ctx
, elems
[0]) : elems
[0];
3193 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
3194 for (unsigned i
= 0; i
< size
; i
++)
3195 vec
->operands
[i
] = Operand(elems
[i
]);
3196 Temp res
= {ctx
->program
->allocateId(), RegClass(type
, size
* size_hint
)};
3197 vec
->definitions
[0] = Definition(res
);
3198 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3202 void ds_write_helper(isel_context
*ctx
, Operand m
, Temp address
, Temp data
, unsigned data_start
, unsigned total_size
, unsigned offset0
, unsigned offset1
, unsigned align
)
3204 Builder
bld(ctx
->program
, ctx
->block
);
3205 unsigned bytes_written
= 0;
3206 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3207 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3209 while (bytes_written
< total_size
* 4) {
3210 unsigned todo
= total_size
* 4 - bytes_written
;
3211 bool aligned8
= bytes_written
% 8 == 0 && align
% 8 == 0;
3212 bool aligned16
= bytes_written
% 16 == 0 && align
% 16 == 0;
3214 aco_opcode op
= aco_opcode::last_opcode
;
3215 bool write2
= false;
3217 if (todo
>= 16 && aligned16
&& large_ds_write
) {
3218 op
= aco_opcode::ds_write_b128
;
3220 } else if (todo
>= 16 && aligned8
&& usable_write2
) {
3221 op
= aco_opcode::ds_write2_b64
;
3224 } else if (todo
>= 12 && aligned16
&& large_ds_write
) {
3225 op
= aco_opcode::ds_write_b96
;
3227 } else if (todo
>= 8 && aligned8
) {
3228 op
= aco_opcode::ds_write_b64
;
3230 } else if (todo
>= 8 && usable_write2
) {
3231 op
= aco_opcode::ds_write2_b32
;
3234 } else if (todo
>= 4) {
3235 op
= aco_opcode::ds_write_b32
;
3241 unsigned offset
= offset0
+ offset1
+ bytes_written
;
3242 unsigned max_offset
= write2
? 1020 : 65535;
3243 Temp address_offset
= address
;
3244 if (offset
> max_offset
) {
3245 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(offset0
), address_offset
);
3246 offset
= offset1
+ bytes_written
;
3248 assert(offset
<= max_offset
); /* offset1 shouldn't be large enough for this to happen */
3251 Temp val0
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
/ 2, RegType::vgpr
);
3252 Temp val1
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2) + 1, size
/ 2, RegType::vgpr
);
3253 bld
.ds(op
, address_offset
, val0
, val1
, m
, offset
/ size
/ 2, (offset
/ size
/ 2) + 1);
3255 Temp val
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
, RegType::vgpr
);
3256 bld
.ds(op
, address_offset
, val
, m
, offset
);
3259 bytes_written
+= size
* 4;
3263 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3264 Temp address
, unsigned base_offset
, unsigned align
)
3266 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
3267 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3269 Operand m
= load_lds_size_m0(ctx
);
3271 /* we need at most two stores, assuming that the writemask is at most 4 bits wide */
3272 assert(wrmask
<= 0x0f);
3273 int start
[2], count
[2];
3274 u_bit_scan_consecutive_range(&wrmask
, &start
[0], &count
[0]);
3275 u_bit_scan_consecutive_range(&wrmask
, &start
[1], &count
[1]);
3276 assert(wrmask
== 0);
3278 /* one combined store is sufficient */
3279 if (count
[0] == count
[1] && (align
% elem_size_bytes
) == 0 && (base_offset
% elem_size_bytes
) == 0) {
3280 Builder
bld(ctx
->program
, ctx
->block
);
3282 Temp address_offset
= address
;
3283 if ((base_offset
/ elem_size_bytes
) + start
[1] > 255) {
3284 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3288 assert(count
[0] == 1);
3289 RegClass
xtract_rc(RegType::vgpr
, elem_size_bytes
/ 4);
3291 Temp val0
= emit_extract_vector(ctx
, data
, start
[0], xtract_rc
);
3292 Temp val1
= emit_extract_vector(ctx
, data
, start
[1], xtract_rc
);
3293 aco_opcode op
= elem_size_bytes
== 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3294 base_offset
= base_offset
/ elem_size_bytes
;
3295 bld
.ds(op
, address_offset
, val0
, val1
, m
,
3296 base_offset
+ start
[0], base_offset
+ start
[1]);
3300 for (unsigned i
= 0; i
< 2; i
++) {
3304 unsigned elem_size_words
= elem_size_bytes
/ 4;
3305 ds_write_helper(ctx
, m
, address
, data
, start
[i
] * elem_size_words
, count
[i
] * elem_size_words
,
3306 base_offset
, start
[i
] * elem_size_bytes
, align
);
3311 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3313 unsigned align
= 16;
3315 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3321 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3322 unsigned split_cnt
= 0u, Temp dst
= Temp())
3324 Builder
bld(ctx
->program
, ctx
->block
);
3325 unsigned dword_size
= elem_size_bytes
/ 4;
3328 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3330 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3331 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3332 instr
->definitions
[0] = Definition(dst
);
3334 for (unsigned i
= 0; i
< cnt
; ++i
) {
3336 assert(arr
[i
].size() == dword_size
);
3337 allocated_vec
[i
] = arr
[i
];
3338 instr
->operands
[i
] = Operand(arr
[i
]);
3340 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3341 allocated_vec
[i
] = zero
;
3342 instr
->operands
[i
] = Operand(zero
);
3346 bld
.insert(std::move(instr
));
3349 emit_split_vector(ctx
, dst
, split_cnt
);
3351 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3356 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3358 if (const_offset
>= 4096) {
3359 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3360 const_offset
%= 4096u;
3363 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3364 else if (unlikely(voffset
.regClass() == s1
))
3365 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3366 else if (likely(voffset
.regClass() == v1
))
3367 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3369 unreachable("Unsupported register class of voffset");
3372 return const_offset
;
3375 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3376 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3379 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3380 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3382 Builder
bld(ctx
->program
, ctx
->block
);
3383 aco_opcode op
= (aco_opcode
) ((unsigned) aco_opcode::buffer_store_dword
+ vdata
.size() - 1);
3384 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3386 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3387 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3388 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3389 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3390 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3392 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3395 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3396 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3397 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3399 Builder
bld(ctx
->program
, ctx
->block
);
3400 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3403 if (elem_size_bytes
== 8) {
3404 elem_size_bytes
= 4;
3405 write_mask
= widen_mask(write_mask
, 2);
3408 while (write_mask
) {
3411 u_bit_scan_consecutive_range(&write_mask
, &start
, &count
);
3416 unsigned sub_count
= allow_combining
? MIN2(count
, 4) : 1;
3417 unsigned const_offset
= (unsigned) start
* elem_size_bytes
+ base_const_offset
;
3419 /* GFX6 doesn't have buffer_store_dwordx3, so make sure not to emit that here either. */
3420 if (unlikely(ctx
->program
->chip_class
== GFX6
&& sub_count
== 3))
3423 Temp elem
= extract_subvector(ctx
, src
, start
, sub_count
, RegType::vgpr
);
3424 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, elem
, const_offset
, reorder
, slc
);
3434 Temp
emit_single_mubuf_load(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
,
3435 unsigned const_offset
, unsigned size_dwords
, bool allow_reorder
= true)
3437 assert(size_dwords
!= 3 || ctx
->program
->chip_class
!= GFX6
);
3438 assert(size_dwords
>= 1 && size_dwords
<= 4);
3440 Builder
bld(ctx
->program
, ctx
->block
);
3441 Temp vdata
= bld
.tmp(RegClass(RegType::vgpr
, size_dwords
));
3442 aco_opcode op
= (aco_opcode
) ((unsigned) aco_opcode::buffer_load_dword
+ size_dwords
- 1);
3443 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3445 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3446 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3447 Builder::Result r
= bld
.mubuf(op
, Definition(vdata
), Operand(descriptor
), voffset_op
, soffset_op
, const_offset
,
3448 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3449 /* disable_wqm */ false, /* glc */ true,
3450 /* dlc*/ ctx
->program
->chip_class
>= GFX10
, /* slc */ false);
3452 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3457 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3458 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3459 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3461 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3462 assert((num_components
* elem_size_bytes
/ 4) == dst
.size());
3463 assert(!!stride
!= allow_combining
);
3465 Builder
bld(ctx
->program
, ctx
->block
);
3466 unsigned split_cnt
= num_components
;
3468 if (elem_size_bytes
== 8) {
3469 elem_size_bytes
= 4;
3470 num_components
*= 2;
3474 stride
= elem_size_bytes
;
3476 unsigned load_size
= 1;
3477 if (allow_combining
) {
3478 if ((num_components
% 4) == 0)
3480 else if ((num_components
% 3) == 0 && ctx
->program
->chip_class
!= GFX6
)
3482 else if ((num_components
% 2) == 0)
3486 unsigned num_loads
= num_components
/ load_size
;
3487 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
3489 for (unsigned i
= 0; i
< num_loads
; ++i
) {
3490 unsigned const_offset
= i
* stride
* load_size
+ base_const_offset
;
3491 elems
[i
] = emit_single_mubuf_load(ctx
, descriptor
, voffset
, soffset
, const_offset
, load_size
, allow_reorder
);
3494 create_vec_from_array(ctx
, elems
.data(), num_loads
, RegType::vgpr
, load_size
* 4u, split_cnt
, dst
);
3497 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
3499 Builder
bld(ctx
->program
, ctx
->block
);
3500 Temp offset
= base_offset
.first
;
3501 unsigned const_offset
= base_offset
.second
;
3503 if (!nir_src_is_const(*off_src
)) {
3504 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
3507 /* Calculate indirect offset with stride */
3508 if (likely(indirect_offset_arg
.regClass() == v1
))
3509 with_stride
= bld
.v_mul_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
3510 else if (indirect_offset_arg
.regClass() == s1
)
3511 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
3513 unreachable("Unsupported register class of indirect offset");
3515 /* Add to the supplied base offset */
3516 if (offset
.id() == 0)
3517 offset
= with_stride
;
3518 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
3519 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
3520 else if (offset
.size() == 1 && with_stride
.size() == 1)
3521 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
3523 unreachable("Unsupported register class of indirect offset");
3525 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
3526 const_offset
+= const_offset_arg
* stride
;
3529 return std::make_pair(offset
, const_offset
);
3532 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
3534 Builder
bld(ctx
->program
, ctx
->block
);
3537 if (off1
.first
.id() && off2
.first
.id()) {
3538 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
3539 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
3540 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
3541 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
3543 unreachable("Unsupported register class of indirect offset");
3545 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
3548 return std::make_pair(offset
, off1
.second
+ off2
.second
);
3551 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
3553 Builder
bld(ctx
->program
, ctx
->block
);
3554 unsigned const_offset
= offs
.second
* multiplier
;
3556 if (!offs
.first
.id())
3557 return std::make_pair(offs
.first
, const_offset
);
3559 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
3560 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
3561 : bld
.v_mul_imm(bld
.def(v1
), offs
.first
, multiplier
);
3563 return std::make_pair(offset
, const_offset
);
3566 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
3568 Builder
bld(ctx
->program
, ctx
->block
);
3570 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
3571 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
3572 /* component is in bytes */
3573 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
3575 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
3576 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3577 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
3580 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
3582 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
3585 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
3587 Builder
bld(ctx
->program
, ctx
->block
);
3589 switch (ctx
->shader
->info
.stage
) {
3590 case MESA_SHADER_TESS_CTRL
:
3591 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
3592 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
3593 case MESA_SHADER_TESS_EVAL
:
3594 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
3596 unreachable("Unsupported stage in get_tess_rel_patch_id");
3600 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3602 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3603 Builder
bld(ctx
->program
, ctx
->block
);
3605 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
3606 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
3608 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
3610 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3611 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
3613 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3614 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
3615 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
3617 return offset_mul(ctx
, offs
, 4u);
3620 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
3622 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3623 Builder
bld(ctx
->program
, ctx
->block
);
3625 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
3626 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
3627 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
3628 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
3629 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
3630 uint32_t output_patch_stride
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
3632 std::pair
<Temp
, unsigned> offs
= instr
3633 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
3634 : std::make_pair(Temp(), 0u);
3636 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3637 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
3642 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3643 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
3645 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
3646 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
3648 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
3649 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
3655 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3657 Builder
bld(ctx
->program
, ctx
->block
);
3659 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
3660 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
3662 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
3664 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3665 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
3666 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
3668 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3669 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
3674 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
3676 Builder
bld(ctx
->program
, ctx
->block
);
3678 unsigned num_tcs_outputs
= ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
3679 ? util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
)
3680 : ctx
->args
->options
->key
.tes
.tcs_num_outputs
;
3682 unsigned output_vertex_size
= num_tcs_outputs
* 16;
3683 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
3684 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
3685 unsigned attr_stride
= ctx
->tcs_num_patches
;
3687 std::pair
<Temp
, unsigned> offs
= instr
3688 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
3689 : std::make_pair(Temp(), 0u);
3691 if (const_base_offset
)
3692 offs
.second
+= const_base_offset
* attr_stride
;
3694 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3695 Temp patch_off
= bld
.v_mul_imm(bld
.def(v1
), rel_patch_id
, 16u);
3696 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
3701 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
3703 unsigned off
= nir_intrinsic_base(instr
) * 4u;
3704 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3706 if (!nir_src_is_const(*off_src
)) {
3712 off
+= nir_src_as_uint(*off_src
) * 16u;
3715 unsigned slot
= u_bit_scan64(&mask
) + (per_vertex
? 0 : VARYING_SLOT_PATCH0
);
3716 if (off
== shader_io_get_unique_index((gl_varying_slot
) slot
) * 16u)
3723 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3725 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3726 unsigned component
= nir_intrinsic_component(instr
);
3727 unsigned idx
= nir_intrinsic_base(instr
) + component
;
3729 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
3730 if (off_instr
->type
!= nir_instr_type_load_const
)
3733 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3734 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
3736 if (instr
->src
[0].ssa
->bit_size
== 64)
3737 write_mask
= widen_mask(write_mask
, 2);
3739 for (unsigned i
= 0; i
< 8; ++i
) {
3740 if (write_mask
& (1 << i
)) {
3741 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
3742 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, v1
);
3750 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
3752 /* Only TCS per-vertex inputs are supported by this function.
3753 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
3755 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
3758 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3759 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3760 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
3761 bool can_use_temps
= nir_src_is_const(*off_src
) &&
3762 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
3763 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
3768 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
3769 Temp
*src
= &ctx
->inputs
.temps
[idx
];
3770 Temp vec
= create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u);
3771 assert(vec
.size() == dst
.size());
3773 Builder
bld(ctx
->program
, ctx
->block
);
3774 bld
.copy(Definition(dst
), vec
);
3778 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3780 Builder
bld(ctx
->program
, ctx
->block
);
3782 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
3783 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3784 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3785 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
3787 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
3788 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
3789 bool indirect_write
;
3790 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
3791 if (temp_only_input
&& !indirect_write
)
3795 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
3796 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
3797 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
3798 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
3799 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
3803 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
3804 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
3805 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
3806 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
3807 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
3808 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
3809 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
3810 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
3811 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
3812 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
3813 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
3814 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
3815 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
3817 unsigned num_tcs_inputs
= util_last_bit64(ctx
->args
->shader_info
->vs
.ls_outputs_written
);
3818 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
3819 lds_base
= bld
.v_mul_imm(bld
.def(v1
), vertex_idx
, num_tcs_inputs
* 16u);
3821 unreachable("Invalid LS or ES stage");
3824 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
3825 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
3826 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
3830 bool should_write_tcs_patch_output_to_vmem(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3832 unsigned off
= nir_intrinsic_base(instr
) * 4u;
3833 return off
!= ctx
->tcs_tess_lvl_out_loc
&&
3834 off
!= ctx
->tcs_tess_lvl_in_loc
;
3837 bool should_write_tcs_output_to_lds(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3839 /* When none of the appropriate outputs are read, we are OK to never write to LDS */
3840 if (per_vertex
? ctx
->shader
->info
.outputs_read
== 0U : ctx
->shader
->info
.patch_outputs_read
== 0u)
3843 uint64_t mask
= per_vertex
3844 ? ctx
->shader
->info
.outputs_read
3845 : ctx
->shader
->info
.patch_outputs_read
;
3846 bool indirect_write
;
3847 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
3848 return indirect_write
|| output_read
;
3851 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3853 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
3854 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3856 Builder
bld(ctx
->program
, ctx
->block
);
3858 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3859 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
3860 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3862 /* Only write to VMEM if the output is per-vertex or it's per-patch non tess factor */
3863 bool write_to_vmem
= per_vertex
|| should_write_tcs_patch_output_to_vmem(ctx
, instr
);
3864 /* Only write to LDS if the output is read by the shader, or it's per-patch tess factor */
3865 bool write_to_lds
= !write_to_vmem
|| should_write_tcs_output_to_lds(ctx
, instr
, per_vertex
);
3867 if (write_to_vmem
) {
3868 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
3869 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
3870 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
3872 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
3873 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
3874 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
3878 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
3879 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
3880 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
3884 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3886 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
3887 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3889 Builder
bld(ctx
->program
, ctx
->block
);
3891 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3892 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
3893 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
3894 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
3896 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
3899 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3901 if (ctx
->stage
== vertex_vs
||
3902 ctx
->stage
== tess_eval_vs
||
3903 ctx
->stage
== fragment_fs
||
3904 ctx
->stage
== ngg_vertex_gs
||
3905 ctx
->stage
== ngg_tess_eval_gs
||
3906 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
3907 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
3908 if (!stored_to_temps
) {
3909 fprintf(stderr
, "Unimplemented output offset instruction:\n");
3910 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
3911 fprintf(stderr
, "\n");
3914 } else if (ctx
->stage
== vertex_es
||
3915 ctx
->stage
== vertex_ls
||
3916 ctx
->stage
== tess_eval_es
||
3917 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
3918 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
3919 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
3920 visit_store_ls_or_es_output(ctx
, instr
);
3921 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
3922 visit_store_tcs_output(ctx
, instr
, false);
3924 unreachable("Shader stage not implemented");
3928 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3930 visit_load_tcs_output(ctx
, instr
, false);
3933 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
3935 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
3936 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
3938 Builder
bld(ctx
->program
, ctx
->block
);
3939 Builder::Result interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
, bld
.m0(prim_mask
), idx
, component
);
3940 if (ctx
->program
->has_16bank_lds
)
3941 interp_p1
.instr
->operands
[0].setLateKill(true);
3942 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
3945 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
3947 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
3948 for (unsigned i
= 0; i
< num_components
; i
++)
3949 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
3950 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
3951 assert(num_components
== 4);
3952 Builder
bld(ctx
->program
, ctx
->block
);
3953 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
3956 for (Operand
& op
: vec
->operands
)
3957 op
= op
.isUndefined() ? Operand(0u) : op
;
3959 vec
->definitions
[0] = Definition(dst
);
3960 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3961 emit_split_vector(ctx
, dst
, num_components
);
3965 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3967 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3968 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3969 unsigned idx
= nir_intrinsic_base(instr
);
3970 unsigned component
= nir_intrinsic_component(instr
);
3971 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
3973 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
3975 assert(offset
->u32
== 0);
3977 /* the lower 15bit of the prim_mask contain the offset into LDS
3978 * while the upper bits contain the number of prims */
3979 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
3980 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
3981 Builder
bld(ctx
->program
, ctx
->block
);
3982 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
3983 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
3984 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
3985 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
3986 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
3989 if (instr
->dest
.ssa
.num_components
== 1) {
3990 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
3992 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
3993 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
3995 Temp tmp
= {ctx
->program
->allocateId(), v1
};
3996 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
3997 vec
->operands
[i
] = Operand(tmp
);
3999 vec
->definitions
[0] = Definition(dst
);
4000 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4004 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4005 unsigned offset
, unsigned stride
, unsigned channels
)
4007 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4008 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4010 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4011 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4014 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4015 unsigned offset
, unsigned stride
, unsigned *channels
)
4017 if (!vtx_info
->chan_byte_size
) {
4018 *channels
= vtx_info
->num_channels
;
4019 return vtx_info
->chan_format
;
4022 unsigned num_channels
= *channels
;
4023 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4024 unsigned new_channels
= num_channels
+ 1;
4025 /* first, assume more loads is worse and try using a larger data format */
4026 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4028 /* don't make the attribute potentially out-of-bounds */
4029 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4033 if (new_channels
== 5) {
4034 /* then try decreasing load size (at the cost of more loads) */
4035 new_channels
= *channels
;
4036 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4040 if (new_channels
< *channels
)
4041 *channels
= new_channels
;
4042 num_channels
= new_channels
;
4045 switch (vtx_info
->chan_format
) {
4046 case V_008F0C_BUF_DATA_FORMAT_8
:
4047 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4048 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4049 case V_008F0C_BUF_DATA_FORMAT_16
:
4050 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4051 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4052 case V_008F0C_BUF_DATA_FORMAT_32
:
4053 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4054 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4056 unreachable("shouldn't reach here");
4057 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4060 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4061 * so we may need to fix it up. */
4062 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4064 Builder
bld(ctx
->program
, ctx
->block
);
4066 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4067 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4069 /* For the integer-like cases, do a natural sign extension.
4071 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4072 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4075 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4076 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4078 /* Convert back to the right type. */
4079 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4080 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4081 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4082 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4083 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4084 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4090 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4092 Builder
bld(ctx
->program
, ctx
->block
);
4093 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4094 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4096 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4097 if (off_instr
->type
!= nir_instr_type_load_const
) {
4098 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4099 nir_print_instr(off_instr
, stderr
);
4100 fprintf(stderr
, "\n");
4102 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4104 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4106 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4107 unsigned component
= nir_intrinsic_component(instr
);
4108 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4109 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4110 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4111 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4113 unsigned dfmt
= attrib_format
& 0xf;
4114 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4115 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4117 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4118 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4119 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4120 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4122 num_channels
= MAX2(num_channels
, 3);
4124 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4125 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4128 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4129 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4130 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4132 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4134 Temp divided
= bld
.tmp(v1
);
4135 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4136 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4138 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4141 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4144 index
= bld
.vadd32(bld
.def(v1
),
4145 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4146 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4149 Temp channels
[num_channels
];
4150 unsigned channel_start
= 0;
4151 bool direct_fetch
= false;
4153 /* skip unused channels at the start */
4154 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4155 channel_start
= ffs(mask
) - 1;
4156 for (unsigned i
= 0; i
< channel_start
; i
++)
4157 channels
[i
] = Temp(0, s1
);
4158 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4159 num_channels
= 3 - (ffs(mask
) - 1);
4163 while (channel_start
< num_channels
) {
4164 unsigned fetch_size
= num_channels
- channel_start
;
4165 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4166 bool expanded
= false;
4168 /* use MUBUF when possible to avoid possible alignment issues */
4169 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4170 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4171 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4172 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4173 vtx_info
->chan_byte_size
== 4;
4174 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4176 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_size
);
4178 if (fetch_size
== 3 && ctx
->options
->chip_class
== GFX6
) {
4179 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4185 Temp fetch_index
= index
;
4186 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4187 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4188 fetch_offset
= fetch_offset
% attrib_stride
;
4191 Operand
soffset(0u);
4192 if (fetch_offset
>= 4096) {
4193 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4194 fetch_offset
%= 4096;
4198 switch (fetch_size
) {
4200 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4203 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4206 assert(ctx
->options
->chip_class
>= GFX7
||
4207 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4208 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4211 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4214 unreachable("Unimplemented load_input vector size");
4218 if (channel_start
== 0 && fetch_size
== dst
.size() && !post_shuffle
&&
4219 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4220 num_channels
<= 3)) {
4221 direct_fetch
= true;
4224 fetch_dst
= bld
.tmp(RegType::vgpr
, fetch_size
);
4228 Instruction
*mubuf
= bld
.mubuf(opcode
,
4229 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4230 fetch_offset
, false, true).instr
;
4231 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4233 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4234 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4235 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4236 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4239 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4241 if (fetch_size
== 1) {
4242 channels
[channel_start
] = fetch_dst
;
4244 for (unsigned i
= 0; i
< MIN2(fetch_size
, num_channels
- channel_start
); i
++)
4245 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
, v1
);
4248 channel_start
+= fetch_size
;
4251 if (!direct_fetch
) {
4252 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4253 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4255 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4256 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4257 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4259 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4260 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4261 unsigned num_temp
= 0;
4262 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4263 unsigned idx
= i
+ component
;
4264 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4265 Temp channel
= channels
[swizzle
[idx
]];
4266 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4267 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4268 vec
->operands
[i
] = Operand(channel
);
4272 } else if (is_float
&& idx
== 3) {
4273 vec
->operands
[i
] = Operand(0x3f800000u
);
4274 } else if (!is_float
&& idx
== 3) {
4275 vec
->operands
[i
] = Operand(1u);
4277 vec
->operands
[i
] = Operand(0u);
4280 vec
->definitions
[0] = Definition(dst
);
4281 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4282 emit_split_vector(ctx
, dst
, dst
.size());
4284 if (num_temp
== dst
.size())
4285 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4287 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4288 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4289 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4290 if (off_instr
->type
!= nir_instr_type_load_const
||
4291 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4292 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4293 nir_print_instr(off_instr
, stderr
);
4294 fprintf(stderr
, "\n");
4297 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4298 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4300 assert(offset
->u32
== 0);
4302 /* the lower 15bit of the prim_mask contain the offset into LDS
4303 * while the upper bits contain the number of prims */
4304 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4305 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4306 Builder
bld(ctx
->program
, ctx
->block
);
4307 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4308 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4309 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4310 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4311 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4314 unsigned idx
= nir_intrinsic_base(instr
);
4315 unsigned component
= nir_intrinsic_component(instr
);
4316 unsigned vertex_id
= 2; /* P0 */
4318 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4319 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4320 switch (src0
->u32
) {
4322 vertex_id
= 2; /* P0 */
4325 vertex_id
= 0; /* P10 */
4328 vertex_id
= 1; /* P20 */
4331 unreachable("invalid vertex index");
4335 if (dst
.size() == 1) {
4336 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4338 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4339 for (unsigned i
= 0; i
< dst
.size(); i
++)
4340 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4341 vec
->definitions
[0] = Definition(dst
);
4342 bld
.insert(std::move(vec
));
4345 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4346 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4347 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4348 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4349 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4351 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4353 unreachable("Shader stage not implemented");
4357 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4359 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4361 Builder
bld(ctx
->program
, ctx
->block
);
4362 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4365 if (!nir_src_is_const(*vertex_src
)) {
4366 /* better code could be created, but this case probably doesn't happen
4367 * much in practice */
4368 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4369 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4372 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4373 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4375 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4377 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4380 if (vertex_offset
.id()) {
4381 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4382 Operand(i
), indirect_vertex
);
4383 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4385 vertex_offset
= elem
;
4389 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4390 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4392 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4393 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4394 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4395 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4396 Operand((vertex
% 2u) * 16u), Operand(16u));
4398 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4401 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4402 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4403 return offset_mul(ctx
, offs
, 4u);
4406 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4408 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4410 Builder
bld(ctx
->program
, ctx
->block
);
4411 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4412 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4414 if (ctx
->stage
== geometry_gs
) {
4415 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4416 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4417 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4418 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4419 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4420 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4421 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4423 unreachable("Unsupported GS stage.");
4427 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4429 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4431 Builder
bld(ctx
->program
, ctx
->block
);
4432 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4434 if (load_input_from_temps(ctx
, instr
, dst
))
4437 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4438 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4439 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4441 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4444 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4446 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4448 Builder
bld(ctx
->program
, ctx
->block
);
4450 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4451 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4452 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4454 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4455 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
4457 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
4460 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4462 switch (ctx
->shader
->info
.stage
) {
4463 case MESA_SHADER_GEOMETRY
:
4464 visit_load_gs_per_vertex_input(ctx
, instr
);
4466 case MESA_SHADER_TESS_CTRL
:
4467 visit_load_tcs_per_vertex_input(ctx
, instr
);
4469 case MESA_SHADER_TESS_EVAL
:
4470 visit_load_tes_per_vertex_input(ctx
, instr
);
4473 unreachable("Unimplemented shader stage");
4477 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4479 visit_load_tcs_output(ctx
, instr
, true);
4482 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4484 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4485 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4487 visit_store_tcs_output(ctx
, instr
, true);
4490 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4492 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4494 Builder
bld(ctx
->program
, ctx
->block
);
4495 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4497 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
4498 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
4501 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
4502 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
4503 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
4504 tes_w
= Operand(tmp
);
4507 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
4508 emit_split_vector(ctx
, tess_coord
, 3);
4511 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
4513 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
4514 Builder
bld(ctx
->program
, ctx
->block
);
4515 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
4516 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
4517 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
4520 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
4524 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4526 Builder
bld(ctx
->program
, ctx
->block
);
4527 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4528 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
])
4529 index
= bld
.as_uniform(index
);
4530 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
4531 unsigned binding
= nir_intrinsic_binding(instr
);
4534 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
4535 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
4536 unsigned offset
= layout
->binding
[binding
].offset
;
4538 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
4539 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
4540 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
4541 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
4542 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
4545 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
4546 stride
= layout
->binding
[binding
].size
;
4549 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
4550 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
4552 if (nir_const_index
) {
4553 const_index
= const_index
* stride
;
4554 } else if (index
.type() == RegType::vgpr
) {
4555 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
4556 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
4558 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
4562 if (nir_const_index
) {
4563 const_index
= const_index
+ offset
;
4564 } else if (index
.type() == RegType::vgpr
) {
4565 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
4567 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
4571 if (nir_const_index
&& const_index
== 0) {
4573 } else if (index
.type() == RegType::vgpr
) {
4574 index
= bld
.vadd32(bld
.def(v1
),
4575 nir_const_index
? Operand(const_index
) : Operand(index
),
4578 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
4579 nir_const_index
? Operand(const_index
) : Operand(index
),
4583 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
4586 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
4587 Temp dst
, Temp rsrc
, Temp offset
, int byte_align
,
4588 bool glc
=false, bool readonly
=true)
4590 Builder
bld(ctx
->program
, ctx
->block
);
4591 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
4592 unsigned num_bytes
= num_components
* component_size
;
4595 if (dst
.type() == RegType::vgpr
|| ((ctx
->options
->chip_class
< GFX8
|| component_size
< 4) && !readonly
)) {
4596 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
4597 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
4598 unsigned const_offset
= 0;
4600 /* for small bit sizes add buffer for unaligned loads */
4603 num_bytes
+= byte_align
== -1 ? 4 - component_size
: byte_align
;
4608 Temp lower
= Temp();
4609 if (num_bytes
> 16) {
4610 assert(num_components
== 3 || num_components
== 4);
4611 op
= aco_opcode::buffer_load_dwordx4
;
4612 lower
= bld
.tmp(v4
);
4613 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
4614 mubuf
->definitions
[0] = Definition(lower
);
4615 mubuf
->operands
[0] = Operand(rsrc
);
4616 mubuf
->operands
[1] = vaddr
;
4617 mubuf
->operands
[2] = soffset
;
4618 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
4621 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4622 mubuf
->can_reorder
= readonly
;
4623 bld
.insert(std::move(mubuf
));
4624 emit_split_vector(ctx
, lower
, 2);
4627 } else if (num_bytes
== 12 && ctx
->options
->chip_class
== GFX6
) {
4628 /* GFX6 doesn't support loading vec3, expand to vec4. */
4632 switch (num_bytes
) {
4634 op
= aco_opcode::buffer_load_ubyte
;
4637 op
= aco_opcode::buffer_load_ushort
;
4641 op
= aco_opcode::buffer_load_dword
;
4647 op
= aco_opcode::buffer_load_dwordx2
;
4651 assert(ctx
->options
->chip_class
> GFX6
);
4652 op
= aco_opcode::buffer_load_dwordx3
;
4655 op
= aco_opcode::buffer_load_dwordx4
;
4658 unreachable("Load SSBO not implemented for this size.");
4660 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
4661 mubuf
->operands
[0] = Operand(rsrc
);
4662 mubuf
->operands
[1] = vaddr
;
4663 mubuf
->operands
[2] = soffset
;
4664 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
4667 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4668 mubuf
->can_reorder
= readonly
;
4669 mubuf
->offset
= const_offset
;
4670 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
4672 if (component_size
< 4) {
4673 Temp vec
= num_bytes
<= 4 ? bld
.tmp(v1
) : num_bytes
<= 8 ? bld
.tmp(v2
) : bld
.tmp(v3
);
4674 instr
->definitions
[0] = Definition(vec
);
4675 bld
.insert(std::move(instr
));
4677 if (byte_align
== -1 || (byte_align
&& dst
.type() == RegType::sgpr
)) {
4678 Operand align
= byte_align
== -1 ? Operand(offset
) : Operand((uint32_t)byte_align
);
4679 Temp tmp
[3] = {vec
, vec
, vec
};
4681 if (vec
.size() == 3) {
4682 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
4683 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
4684 } else if (vec
.size() == 2) {
4685 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
4686 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
4688 for (unsigned i
= 0; i
< dst
.size(); i
++)
4689 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], align
);
4692 if (dst
.size() == 2)
4693 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
4698 if (dst
.type() == RegType::vgpr
&& num_components
== 1) {
4699 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), vec
, Operand(byte_align
/ component_size
));
4701 trim_subdword_vector(ctx
, vec
, dst
, 4 * vec
.size() / component_size
, ((1 << num_components
) - 1) << byte_align
/ component_size
);
4706 } else if (dst
.size() > 4) {
4707 assert(lower
!= Temp());
4708 Temp upper
= bld
.tmp(RegType::vgpr
, dst
.size() - lower
.size());
4709 instr
->definitions
[0] = Definition(upper
);
4710 bld
.insert(std::move(instr
));
4711 if (dst
.size() == 8)
4712 emit_split_vector(ctx
, upper
, 2);
4713 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size() / 2, 1));
4714 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, lower
, 0, v2
));
4715 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, lower
, 1, v2
));
4716 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, upper
, 0, v2
));
4717 if (dst
.size() == 8)
4718 instr
->operands
[3] = Operand(emit_extract_vector(ctx
, upper
, 1, v2
));
4719 } else if (dst
.size() == 3 && ctx
->options
->chip_class
== GFX6
) {
4720 Temp vec
= bld
.tmp(v4
);
4721 instr
->definitions
[0] = Definition(vec
);
4722 bld
.insert(std::move(instr
));
4723 emit_split_vector(ctx
, vec
, 4);
4725 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 3, 1));
4726 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, vec
, 0, v1
));
4727 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, vec
, 1, v1
));
4728 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, vec
, 2, v1
));
4731 if (dst
.type() == RegType::sgpr
) {
4732 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
4733 instr
->definitions
[0] = Definition(vec
);
4734 bld
.insert(std::move(instr
));
4735 expand_vector(ctx
, vec
, dst
, num_components
, (1 << num_components
) - 1);
4737 instr
->definitions
[0] = Definition(dst
);
4738 bld
.insert(std::move(instr
));
4739 emit_split_vector(ctx
, dst
, num_components
);
4742 /* for small bit sizes add buffer for unaligned loads */
4744 num_bytes
+= byte_align
== -1 ? 4 - component_size
: byte_align
;
4746 switch (num_bytes
) {
4751 op
= aco_opcode::s_buffer_load_dword
;
4757 op
= aco_opcode::s_buffer_load_dwordx2
;
4762 op
= aco_opcode::s_buffer_load_dwordx4
;
4766 op
= aco_opcode::s_buffer_load_dwordx8
;
4769 unreachable("Load SSBO not implemented for this size.");
4771 offset
= bld
.as_uniform(offset
);
4772 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
4773 load
->operands
[0] = Operand(rsrc
);
4774 load
->operands
[1] = Operand(offset
);
4775 assert(load
->operands
[1].getTemp().type() == RegType::sgpr
);
4776 load
->definitions
[0] = Definition(dst
);
4779 load
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4780 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
4781 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
4783 /* adjust misaligned small bit size loads */
4785 Temp vec
= num_bytes
<= 4 ? bld
.tmp(s1
) : num_bytes
<= 8 ? bld
.tmp(s2
) : bld
.tmp(s4
);
4786 load
->definitions
[0] = Definition(vec
);
4787 bld
.insert(std::move(load
));
4788 Operand byte_offset
= byte_align
> 0 ? Operand(uint32_t(byte_align
)) : Operand(offset
);
4789 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
4792 } else if (dst
.size() == 3) {
4793 Temp vec
= bld
.tmp(s4
);
4794 load
->definitions
[0] = Definition(vec
);
4795 bld
.insert(std::move(load
));
4796 emit_split_vector(ctx
, vec
, 4);
4798 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4799 emit_extract_vector(ctx
, vec
, 0, s1
),
4800 emit_extract_vector(ctx
, vec
, 1, s1
),
4801 emit_extract_vector(ctx
, vec
, 2, s1
));
4802 } else if (dst
.size() == 6) {
4803 Temp vec
= bld
.tmp(s8
);
4804 load
->definitions
[0] = Definition(vec
);
4805 bld
.insert(std::move(load
));
4806 emit_split_vector(ctx
, vec
, 4);
4808 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4809 emit_extract_vector(ctx
, vec
, 0, s2
),
4810 emit_extract_vector(ctx
, vec
, 1, s2
),
4811 emit_extract_vector(ctx
, vec
, 2, s2
));
4813 bld
.insert(std::move(load
));
4815 emit_split_vector(ctx
, dst
, num_components
);
4819 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4821 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4822 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4824 Builder
bld(ctx
->program
, ctx
->block
);
4826 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
4827 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
4828 unsigned binding
= nir_intrinsic_binding(idx_instr
);
4829 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
4831 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
4832 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
4833 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
4834 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
4835 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
4836 if (ctx
->options
->chip_class
>= GFX10
) {
4837 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
4838 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
4839 S_008F0C_RESOURCE_LEVEL(1);
4841 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
4842 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
4844 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
4845 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
4846 Operand(0xFFFFFFFFu
),
4847 Operand(desc_type
));
4848 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
4849 rsrc
, upper_dwords
);
4851 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
4852 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
4854 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
4857 unsigned align_mul
= nir_intrinsic_align_mul(instr
);
4858 unsigned align_offset
= nir_intrinsic_align_offset(instr
);
4859 byte_align
= align_mul
% 4 == 0 ? align_offset
: -1;
4861 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), byte_align
);
4864 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4866 Builder
bld(ctx
->program
, ctx
->block
);
4867 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4868 unsigned offset
= nir_intrinsic_base(instr
);
4869 unsigned count
= instr
->dest
.ssa
.num_components
;
4870 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
4872 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
4873 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
4874 start
-= ctx
->args
->ac
.base_inline_push_consts
;
4875 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
4876 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4877 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
4878 for (unsigned i
= 0; i
< count
; ++i
) {
4879 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
4880 vec
->operands
[i
] = Operand
{elems
[i
]};
4882 vec
->definitions
[0] = Definition(dst
);
4883 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4884 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4889 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
4890 if (offset
!= 0) // TODO check if index != 0 as well
4891 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
4892 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
4895 bool aligned
= true;
4897 if (instr
->dest
.ssa
.bit_size
== 8) {
4898 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
4899 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
4901 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
4902 } else if (instr
->dest
.ssa
.bit_size
== 16) {
4903 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
4905 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
4910 switch (vec
.size()) {
4912 op
= aco_opcode::s_load_dword
;
4915 op
= aco_opcode::s_load_dwordx2
;
4921 op
= aco_opcode::s_load_dwordx4
;
4927 op
= aco_opcode::s_load_dwordx8
;
4930 unreachable("unimplemented or forbidden load_push_constant.");
4933 bld
.smem(op
, Definition(vec
), ptr
, index
);
4936 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
4937 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
4942 emit_split_vector(ctx
, vec
, 4);
4943 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
4944 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4945 emit_extract_vector(ctx
, vec
, 0, rc
),
4946 emit_extract_vector(ctx
, vec
, 1, rc
),
4947 emit_extract_vector(ctx
, vec
, 2, rc
));
4950 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
4953 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4955 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4957 Builder
bld(ctx
->program
, ctx
->block
);
4959 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
4960 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
4961 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
4962 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
4963 if (ctx
->options
->chip_class
>= GFX10
) {
4964 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
4965 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
4966 S_008F0C_RESOURCE_LEVEL(1);
4968 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
4969 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
4972 unsigned base
= nir_intrinsic_base(instr
);
4973 unsigned range
= nir_intrinsic_range(instr
);
4975 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4976 if (base
&& offset
.type() == RegType::sgpr
)
4977 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
4978 else if (base
&& offset
.type() == RegType::vgpr
)
4979 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
4981 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
4982 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
4983 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
4984 Operand(desc_type
));
4985 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
4986 // TODO: get alignment information for subdword constants
4987 unsigned byte_align
= size
< 4 ? -1 : 0;
4988 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, byte_align
);
4991 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4993 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
4994 ctx
->cf_info
.exec_potentially_empty_discard
= true;
4996 ctx
->program
->needs_exact
= true;
4998 // TODO: optimize uniform conditions
4999 Builder
bld(ctx
->program
, ctx
->block
);
5000 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5001 assert(src
.regClass() == bld
.lm
);
5002 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5003 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5004 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5008 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5010 Builder
bld(ctx
->program
, ctx
->block
);
5012 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5013 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5015 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5016 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5018 if (ctx
->block
->loop_nest_depth
&&
5019 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5020 /* we handle discards the same way as jump instructions */
5021 append_logical_end(ctx
->block
);
5023 /* in loops, discard behaves like break */
5024 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5025 ctx
->block
->kind
|= block_kind_discard
;
5028 /* uniform discard - loop ends here */
5029 assert(nir_instr_is_last(&instr
->instr
));
5030 ctx
->block
->kind
|= block_kind_uniform
;
5031 ctx
->cf_info
.has_branch
= true;
5032 bld
.branch(aco_opcode::p_branch
);
5033 add_linear_edge(ctx
->block
->index
, linear_target
);
5037 /* we add a break right behind the discard() instructions */
5038 ctx
->block
->kind
|= block_kind_break
;
5039 unsigned idx
= ctx
->block
->index
;
5041 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5042 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5044 /* remove critical edges from linear CFG */
5045 bld
.branch(aco_opcode::p_branch
);
5046 Block
* break_block
= ctx
->program
->create_and_insert_block();
5047 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5048 break_block
->kind
|= block_kind_uniform
;
5049 add_linear_edge(idx
, break_block
);
5050 add_linear_edge(break_block
->index
, linear_target
);
5051 bld
.reset(break_block
);
5052 bld
.branch(aco_opcode::p_branch
);
5054 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5055 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5056 add_linear_edge(idx
, continue_block
);
5057 append_logical_start(continue_block
);
5058 ctx
->block
= continue_block
;
5063 /* it can currently happen that NIR doesn't remove the unreachable code */
5064 if (!nir_instr_is_last(&instr
->instr
)) {
5065 ctx
->program
->needs_exact
= true;
5066 /* save exec somewhere temporarily so that it doesn't get
5067 * overwritten before the discard from outer exec masks */
5068 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5069 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5070 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5074 /* This condition is incorrect for uniformly branched discards in a loop
5075 * predicated by a divergent condition, but the above code catches that case
5076 * and the discard would end up turning into a discard_if.
5086 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5087 /* program just ends here */
5088 ctx
->block
->kind
|= block_kind_uniform
;
5089 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5090 0 /* enabled mask */, 9 /* dest */,
5091 false /* compressed */, true/* done */, true /* valid mask */);
5092 bld
.sopp(aco_opcode::s_endpgm
);
5093 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5095 ctx
->block
->kind
|= block_kind_discard
;
5096 /* branch and linear edge is added by visit_if() */
5100 enum aco_descriptor_type
{
5111 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5112 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5114 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5115 return dim
== ac_image_cube
||
5116 dim
== ac_image_1darray
||
5117 dim
== ac_image_2darray
||
5118 dim
== ac_image_2darraymsaa
;
5121 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5122 enum aco_descriptor_type desc_type
,
5123 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5125 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5126 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5127 if (it != ctx->tex_desc.end())
5130 Temp index
= Temp();
5131 bool index_set
= false;
5132 unsigned constant_index
= 0;
5133 unsigned descriptor_set
;
5134 unsigned base_index
;
5135 Builder
bld(ctx
->program
, ctx
->block
);
5138 assert(tex_instr
&& !image
);
5140 base_index
= tex_instr
->sampler_index
;
5142 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5143 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5147 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5148 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5150 constant_index
+= array_size
* const_value
->u32
;
5152 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5153 if (indirect
.type() == RegType::vgpr
)
5154 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5156 if (array_size
!= 1)
5157 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5163 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5167 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5169 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5170 base_index
= deref_instr
->var
->data
.binding
;
5173 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5174 list
= convert_pointer_to_64_bit(ctx
, list
);
5176 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5177 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5178 unsigned offset
= binding
->offset
;
5179 unsigned stride
= binding
->size
;
5183 assert(base_index
< layout
->binding_count
);
5185 switch (desc_type
) {
5186 case ACO_DESC_IMAGE
:
5188 opcode
= aco_opcode::s_load_dwordx8
;
5190 case ACO_DESC_FMASK
:
5192 opcode
= aco_opcode::s_load_dwordx8
;
5195 case ACO_DESC_SAMPLER
:
5197 opcode
= aco_opcode::s_load_dwordx4
;
5198 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5199 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5201 case ACO_DESC_BUFFER
:
5203 opcode
= aco_opcode::s_load_dwordx4
;
5205 case ACO_DESC_PLANE_0
:
5206 case ACO_DESC_PLANE_1
:
5208 opcode
= aco_opcode::s_load_dwordx8
;
5209 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5211 case ACO_DESC_PLANE_2
:
5213 opcode
= aco_opcode::s_load_dwordx4
;
5217 unreachable("invalid desc_type\n");
5220 offset
+= constant_index
* stride
;
5222 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5223 (!index_set
|| binding
->immutable_samplers_equal
)) {
5224 if (binding
->immutable_samplers_equal
)
5227 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5228 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5229 Operand(samplers
[constant_index
* 4 + 0]),
5230 Operand(samplers
[constant_index
* 4 + 1]),
5231 Operand(samplers
[constant_index
* 4 + 2]),
5232 Operand(samplers
[constant_index
* 4 + 3]));
5237 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5239 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5240 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5243 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5245 if (desc_type
== ACO_DESC_PLANE_2
) {
5247 for (unsigned i
= 0; i
< 8; i
++)
5248 components
[i
] = bld
.tmp(s1
);
5249 bld
.pseudo(aco_opcode::p_split_vector
,
5250 Definition(components
[0]),
5251 Definition(components
[1]),
5252 Definition(components
[2]),
5253 Definition(components
[3]),
5256 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5257 bld
.pseudo(aco_opcode::p_split_vector
,
5258 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5259 Definition(components
[4]),
5260 Definition(components
[5]),
5261 Definition(components
[6]),
5262 Definition(components
[7]),
5265 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5266 components
[0], components
[1], components
[2], components
[3],
5267 components
[4], components
[5], components
[6], components
[7]);
5273 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5276 case GLSL_SAMPLER_DIM_BUF
:
5278 case GLSL_SAMPLER_DIM_1D
:
5279 return array
? 2 : 1;
5280 case GLSL_SAMPLER_DIM_2D
:
5281 return array
? 3 : 2;
5282 case GLSL_SAMPLER_DIM_MS
:
5283 return array
? 4 : 3;
5284 case GLSL_SAMPLER_DIM_3D
:
5285 case GLSL_SAMPLER_DIM_CUBE
:
5287 case GLSL_SAMPLER_DIM_RECT
:
5288 case GLSL_SAMPLER_DIM_SUBPASS
:
5290 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5299 /* Adjust the sample index according to FMASK.
5301 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5302 * which is the identity mapping. Each nibble says which physical sample
5303 * should be fetched to get that sample.
5305 * For example, 0x11111100 means there are only 2 samples stored and
5306 * the second sample covers 3/4 of the pixel. When reading samples 0
5307 * and 1, return physical sample 0 (determined by the first two 0s
5308 * in FMASK), otherwise return physical sample 1.
5310 * The sample index should be adjusted as follows:
5311 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5313 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5315 Builder
bld(ctx
->program
, ctx
->block
);
5316 Temp fmask
= bld
.tmp(v1
);
5317 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5318 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5321 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5322 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5323 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5324 load
->operands
[0] = Operand(fmask_desc_ptr
);
5325 load
->operands
[1] = Operand(s4
); /* no sampler */
5326 load
->operands
[2] = Operand(coord
);
5327 load
->definitions
[0] = Definition(fmask
);
5334 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5335 ctx
->block
->instructions
.emplace_back(std::move(load
));
5337 Operand sample_index4
;
5338 if (sample_index
.isConstant() && sample_index
.constantValue() < 16) {
5339 sample_index4
= Operand(sample_index
.constantValue() << 2);
5340 } else if (sample_index
.regClass() == s1
) {
5341 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5343 assert(sample_index
.regClass() == v1
);
5344 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5348 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5349 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5350 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5351 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5353 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5355 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5356 * resource descriptor is 0 (invalid),
5358 Temp compare
= bld
.tmp(bld
.lm
);
5359 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5360 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5362 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5364 /* Replace the MSAA sample index. */
5365 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5368 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5371 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5372 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5373 bool is_array
= glsl_sampler_type_is_array(type
);
5374 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5375 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5376 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5377 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5378 int count
= image_type_to_components_count(dim
, is_array
);
5379 std::vector
<Temp
> coords(count
);
5380 Builder
bld(ctx
->program
, ctx
->block
);
5384 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5385 /* get sample index */
5386 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5387 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5388 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5389 std::vector
<Temp
> fmask_load_address
;
5390 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5391 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5393 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5394 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5396 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5401 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5402 coords
.resize(coords
.size() + 1);
5403 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5405 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5407 for (int i
= 0; i
< count
; i
++)
5408 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5411 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5412 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5413 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5414 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5417 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5420 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5421 for (unsigned i
= 0; i
< coords
.size(); i
++)
5422 vec
->operands
[i
] = Operand(coords
[i
]);
5423 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5424 vec
->definitions
[0] = Definition(res
);
5425 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5430 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5432 Builder
bld(ctx
->program
, ctx
->block
);
5433 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5434 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5435 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5436 bool is_array
= glsl_sampler_type_is_array(type
);
5437 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5439 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5440 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5441 unsigned num_channels
= util_last_bit(mask
);
5442 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5443 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5446 switch (num_channels
) {
5448 opcode
= aco_opcode::buffer_load_format_x
;
5451 opcode
= aco_opcode::buffer_load_format_xy
;
5454 opcode
= aco_opcode::buffer_load_format_xyz
;
5457 opcode
= aco_opcode::buffer_load_format_xyzw
;
5460 unreachable(">4 channel buffer image load");
5462 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5463 load
->operands
[0] = Operand(rsrc
);
5464 load
->operands
[1] = Operand(vindex
);
5465 load
->operands
[2] = Operand((uint32_t) 0);
5467 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5470 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5471 load
->definitions
[0] = Definition(tmp
);
5473 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5474 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5475 load
->barrier
= barrier_image
;
5476 ctx
->block
->instructions
.emplace_back(std::move(load
));
5478 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5482 Temp coords
= get_image_coords(ctx
, instr
, type
);
5483 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5485 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5486 unsigned num_components
= util_bitcount(dmask
);
5488 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5491 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5493 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5494 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5496 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5497 load
->operands
[0] = Operand(resource
);
5498 load
->operands
[1] = Operand(s4
); /* no sampler */
5499 load
->operands
[2] = Operand(coords
);
5500 load
->definitions
[0] = Definition(tmp
);
5501 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5502 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5503 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5504 load
->dmask
= dmask
;
5506 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5507 load
->barrier
= barrier_image
;
5508 ctx
->block
->instructions
.emplace_back(std::move(load
));
5510 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5514 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5516 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5517 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5518 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5519 bool is_array
= glsl_sampler_type_is_array(type
);
5520 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5522 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5524 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5525 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5526 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5528 switch (data
.size()) {
5530 opcode
= aco_opcode::buffer_store_format_x
;
5533 opcode
= aco_opcode::buffer_store_format_xy
;
5536 opcode
= aco_opcode::buffer_store_format_xyz
;
5539 opcode
= aco_opcode::buffer_store_format_xyzw
;
5542 unreachable(">4 channel buffer image store");
5544 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5545 store
->operands
[0] = Operand(rsrc
);
5546 store
->operands
[1] = Operand(vindex
);
5547 store
->operands
[2] = Operand((uint32_t) 0);
5548 store
->operands
[3] = Operand(data
);
5549 store
->idxen
= true;
5552 store
->disable_wqm
= true;
5553 store
->barrier
= barrier_image
;
5554 ctx
->program
->needs_exact
= true;
5555 ctx
->block
->instructions
.emplace_back(std::move(store
));
5559 assert(data
.type() == RegType::vgpr
);
5560 Temp coords
= get_image_coords(ctx
, instr
, type
);
5561 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5563 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5564 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5566 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5567 store
->operands
[0] = Operand(resource
);
5568 store
->operands
[1] = Operand(data
);
5569 store
->operands
[2] = Operand(coords
);
5572 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5573 store
->dmask
= (1 << data
.size()) - 1;
5575 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5576 store
->disable_wqm
= true;
5577 store
->barrier
= barrier_image
;
5578 ctx
->program
->needs_exact
= true;
5579 ctx
->block
->instructions
.emplace_back(std::move(store
));
5583 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5585 /* return the previous value if dest is ever used */
5586 bool return_previous
= false;
5587 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5588 return_previous
= true;
5591 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5592 return_previous
= true;
5596 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5597 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5598 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5599 bool is_array
= glsl_sampler_type_is_array(type
);
5600 Builder
bld(ctx
->program
, ctx
->block
);
5602 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5603 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5605 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5606 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5608 aco_opcode buf_op
, image_op
;
5609 switch (instr
->intrinsic
) {
5610 case nir_intrinsic_image_deref_atomic_add
:
5611 buf_op
= aco_opcode::buffer_atomic_add
;
5612 image_op
= aco_opcode::image_atomic_add
;
5614 case nir_intrinsic_image_deref_atomic_umin
:
5615 buf_op
= aco_opcode::buffer_atomic_umin
;
5616 image_op
= aco_opcode::image_atomic_umin
;
5618 case nir_intrinsic_image_deref_atomic_imin
:
5619 buf_op
= aco_opcode::buffer_atomic_smin
;
5620 image_op
= aco_opcode::image_atomic_smin
;
5622 case nir_intrinsic_image_deref_atomic_umax
:
5623 buf_op
= aco_opcode::buffer_atomic_umax
;
5624 image_op
= aco_opcode::image_atomic_umax
;
5626 case nir_intrinsic_image_deref_atomic_imax
:
5627 buf_op
= aco_opcode::buffer_atomic_smax
;
5628 image_op
= aco_opcode::image_atomic_smax
;
5630 case nir_intrinsic_image_deref_atomic_and
:
5631 buf_op
= aco_opcode::buffer_atomic_and
;
5632 image_op
= aco_opcode::image_atomic_and
;
5634 case nir_intrinsic_image_deref_atomic_or
:
5635 buf_op
= aco_opcode::buffer_atomic_or
;
5636 image_op
= aco_opcode::image_atomic_or
;
5638 case nir_intrinsic_image_deref_atomic_xor
:
5639 buf_op
= aco_opcode::buffer_atomic_xor
;
5640 image_op
= aco_opcode::image_atomic_xor
;
5642 case nir_intrinsic_image_deref_atomic_exchange
:
5643 buf_op
= aco_opcode::buffer_atomic_swap
;
5644 image_op
= aco_opcode::image_atomic_swap
;
5646 case nir_intrinsic_image_deref_atomic_comp_swap
:
5647 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5648 image_op
= aco_opcode::image_atomic_cmpswap
;
5651 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5654 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5656 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5657 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5658 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5659 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5660 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5661 mubuf
->operands
[0] = Operand(resource
);
5662 mubuf
->operands
[1] = Operand(vindex
);
5663 mubuf
->operands
[2] = Operand((uint32_t)0);
5664 mubuf
->operands
[3] = Operand(data
);
5665 if (return_previous
)
5666 mubuf
->definitions
[0] = Definition(dst
);
5668 mubuf
->idxen
= true;
5669 mubuf
->glc
= return_previous
;
5670 mubuf
->dlc
= false; /* Not needed for atomics */
5671 mubuf
->disable_wqm
= true;
5672 mubuf
->barrier
= barrier_image
;
5673 ctx
->program
->needs_exact
= true;
5674 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5678 Temp coords
= get_image_coords(ctx
, instr
, type
);
5679 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5680 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
5681 mimg
->operands
[0] = Operand(resource
);
5682 mimg
->operands
[1] = Operand(data
);
5683 mimg
->operands
[2] = Operand(coords
);
5684 if (return_previous
)
5685 mimg
->definitions
[0] = Definition(dst
);
5686 mimg
->glc
= return_previous
;
5687 mimg
->dlc
= false; /* Not needed for atomics */
5688 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5689 mimg
->dmask
= (1 << data
.size()) - 1;
5691 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5692 mimg
->disable_wqm
= true;
5693 mimg
->barrier
= barrier_image
;
5694 ctx
->program
->needs_exact
= true;
5695 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5699 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
5701 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
5702 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
5703 Builder
bld(ctx
->program
, ctx
->block
);
5705 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
5707 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
5708 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
5710 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
5711 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
5713 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
5714 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
5716 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
5717 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
5718 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
5719 if (dst
.type() == RegType::vgpr
)
5720 bld
.copy(Definition(dst
), shr_dst
);
5722 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
5724 emit_extract_vector(ctx
, desc
, 2, dst
);
5728 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5730 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5731 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5732 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5733 bool is_array
= glsl_sampler_type_is_array(type
);
5734 Builder
bld(ctx
->program
, ctx
->block
);
5736 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
5737 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
5738 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
5742 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
5745 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
5747 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5749 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
5750 mimg
->operands
[0] = Operand(resource
);
5751 mimg
->operands
[1] = Operand(s4
); /* no sampler */
5752 mimg
->operands
[2] = Operand(lod
);
5753 uint8_t& dmask
= mimg
->dmask
;
5754 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5755 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
5756 mimg
->da
= glsl_sampler_type_is_array(type
);
5757 mimg
->can_reorder
= true;
5758 Definition
& def
= mimg
->definitions
[0];
5759 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5761 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
5762 glsl_sampler_type_is_array(type
)) {
5764 assert(instr
->dest
.ssa
.num_components
== 3);
5765 Temp tmp
= {ctx
->program
->allocateId(), v3
};
5766 def
= Definition(tmp
);
5767 emit_split_vector(ctx
, tmp
, 3);
5769 /* divide 3rd value by 6 by multiplying with magic number */
5770 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
5771 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
5773 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5774 emit_extract_vector(ctx
, tmp
, 0, v1
),
5775 emit_extract_vector(ctx
, tmp
, 1, v1
),
5778 } else if (ctx
->options
->chip_class
== GFX9
&&
5779 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
5780 glsl_sampler_type_is_array(type
)) {
5781 assert(instr
->dest
.ssa
.num_components
== 2);
5782 def
= Definition(dst
);
5785 def
= Definition(dst
);
5788 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5791 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5793 Builder
bld(ctx
->program
, ctx
->block
);
5794 unsigned num_components
= instr
->num_components
;
5796 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5797 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5798 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5800 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5801 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5804 unsigned align_mul
= nir_intrinsic_align_mul(instr
);
5805 unsigned align_offset
= nir_intrinsic_align_offset(instr
);
5806 byte_align
= align_mul
% 4 == 0 ? align_offset
: -1;
5808 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), byte_align
, glc
, false);
5811 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5813 Builder
bld(ctx
->program
, ctx
->block
);
5814 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5815 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
5816 unsigned writemask
= nir_intrinsic_write_mask(instr
);
5817 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5819 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
5820 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5822 bool smem
= !ctx
->divergent_vals
[instr
->src
[2].ssa
->index
] &&
5823 ctx
->options
->chip_class
>= GFX8
&&
5824 elem_size_bytes
>= 4;
5826 offset
= bld
.as_uniform(offset
);
5827 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
5831 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
5832 if (count
== 3 && (smem
|| ctx
->options
->chip_class
== GFX6
)) {
5833 /* GFX6 doesn't support storing vec3, split it. */
5834 writemask
|= 1u << (start
+ 2);
5837 int num_bytes
= count
* elem_size_bytes
;
5839 /* dword or larger stores have to be dword-aligned */
5840 if (elem_size_bytes
< 4 && num_bytes
> 2) {
5841 // TODO: improve alignment check of sub-dword stores
5842 unsigned count_new
= 2 / elem_size_bytes
;
5843 writemask
|= ((1 << (count
- count_new
)) - 1) << (start
+ count_new
);
5848 if (num_bytes
> 16) {
5849 assert(elem_size_bytes
== 8);
5850 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
5856 if (elem_size_bytes
< 4) {
5857 if (data
.type() == RegType::sgpr
) {
5858 data
= as_vgpr(ctx
, data
);
5859 emit_split_vector(ctx
, data
, 4 * data
.size() / elem_size_bytes
);
5861 RegClass rc
= RegClass(RegType::vgpr
, elem_size_bytes
).as_subdword();
5862 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5863 for (int i
= 0; i
< count
; i
++)
5864 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, data
, start
+ i
, rc
));
5865 write_data
= bld
.tmp(RegClass(RegType::vgpr
, num_bytes
).as_subdword());
5866 vec
->definitions
[0] = Definition(write_data
);
5867 bld
.insert(std::move(vec
));
5868 } else if (count
!= instr
->num_components
) {
5869 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5870 for (int i
= 0; i
< count
; i
++) {
5871 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(data
.type(), elem_size_bytes
/ 4));
5872 vec
->operands
[i
] = Operand(smem_nonfs
? bld
.as_uniform(elem
) : elem
);
5874 write_data
= bld
.tmp(!smem
? RegType::vgpr
: smem_nonfs
? RegType::sgpr
: data
.type(), count
* elem_size_bytes
/ 4);
5875 vec
->definitions
[0] = Definition(write_data
);
5876 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5877 } else if (!smem
&& data
.type() != RegType::vgpr
) {
5878 assert(num_bytes
% 4 == 0);
5879 write_data
= bld
.copy(bld
.def(RegType::vgpr
, num_bytes
/ 4), data
);
5880 } else if (smem_nonfs
&& data
.type() == RegType::vgpr
) {
5881 assert(num_bytes
% 4 == 0);
5882 write_data
= bld
.as_uniform(data
);
5887 aco_opcode vmem_op
, smem_op
= aco_opcode::last_opcode
;
5888 switch (num_bytes
) {
5890 vmem_op
= aco_opcode::buffer_store_byte
;
5893 vmem_op
= aco_opcode::buffer_store_short
;
5896 vmem_op
= aco_opcode::buffer_store_dword
;
5897 smem_op
= aco_opcode::s_buffer_store_dword
;
5900 vmem_op
= aco_opcode::buffer_store_dwordx2
;
5901 smem_op
= aco_opcode::s_buffer_store_dwordx2
;
5904 vmem_op
= aco_opcode::buffer_store_dwordx3
;
5905 assert(!smem
&& ctx
->options
->chip_class
> GFX6
);
5908 vmem_op
= aco_opcode::buffer_store_dwordx4
;
5909 smem_op
= aco_opcode::s_buffer_store_dwordx4
;
5912 unreachable("Store SSBO not implemented for this size.");
5914 if (ctx
->stage
== fragment_fs
)
5915 smem_op
= aco_opcode::p_fs_buffer_store_smem
;
5918 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(smem_op
, Format::SMEM
, 3, 0)};
5919 store
->operands
[0] = Operand(rsrc
);
5921 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5922 offset
, Operand(start
* elem_size_bytes
));
5923 store
->operands
[1] = Operand(off
);
5925 store
->operands
[1] = Operand(offset
);
5927 if (smem_op
!= aco_opcode::p_fs_buffer_store_smem
)
5928 store
->operands
[1].setFixed(m0
);
5929 store
->operands
[2] = Operand(write_data
);
5930 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
5932 store
->disable_wqm
= true;
5933 store
->barrier
= barrier_buffer
;
5934 ctx
->block
->instructions
.emplace_back(std::move(store
));
5935 ctx
->program
->wb_smem_l1_on_end
= true;
5936 if (smem_op
== aco_opcode::p_fs_buffer_store_smem
) {
5937 ctx
->block
->kind
|= block_kind_needs_lowering
;
5938 ctx
->program
->needs_exact
= true;
5941 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(vmem_op
, Format::MUBUF
, 4, 0)};
5942 store
->operands
[0] = Operand(rsrc
);
5943 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
5944 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
5945 store
->operands
[3] = Operand(write_data
);
5946 store
->offset
= start
* elem_size_bytes
;
5947 store
->offen
= (offset
.type() == RegType::vgpr
);
5948 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
5950 store
->disable_wqm
= true;
5951 store
->barrier
= barrier_buffer
;
5952 ctx
->program
->needs_exact
= true;
5953 ctx
->block
->instructions
.emplace_back(std::move(store
));
5958 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5960 /* return the previous value if dest is ever used */
5961 bool return_previous
= false;
5962 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5963 return_previous
= true;
5966 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5967 return_previous
= true;
5971 Builder
bld(ctx
->program
, ctx
->block
);
5972 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
5974 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
5975 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
5976 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
5978 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5979 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5980 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5982 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5984 aco_opcode op32
, op64
;
5985 switch (instr
->intrinsic
) {
5986 case nir_intrinsic_ssbo_atomic_add
:
5987 op32
= aco_opcode::buffer_atomic_add
;
5988 op64
= aco_opcode::buffer_atomic_add_x2
;
5990 case nir_intrinsic_ssbo_atomic_imin
:
5991 op32
= aco_opcode::buffer_atomic_smin
;
5992 op64
= aco_opcode::buffer_atomic_smin_x2
;
5994 case nir_intrinsic_ssbo_atomic_umin
:
5995 op32
= aco_opcode::buffer_atomic_umin
;
5996 op64
= aco_opcode::buffer_atomic_umin_x2
;
5998 case nir_intrinsic_ssbo_atomic_imax
:
5999 op32
= aco_opcode::buffer_atomic_smax
;
6000 op64
= aco_opcode::buffer_atomic_smax_x2
;
6002 case nir_intrinsic_ssbo_atomic_umax
:
6003 op32
= aco_opcode::buffer_atomic_umax
;
6004 op64
= aco_opcode::buffer_atomic_umax_x2
;
6006 case nir_intrinsic_ssbo_atomic_and
:
6007 op32
= aco_opcode::buffer_atomic_and
;
6008 op64
= aco_opcode::buffer_atomic_and_x2
;
6010 case nir_intrinsic_ssbo_atomic_or
:
6011 op32
= aco_opcode::buffer_atomic_or
;
6012 op64
= aco_opcode::buffer_atomic_or_x2
;
6014 case nir_intrinsic_ssbo_atomic_xor
:
6015 op32
= aco_opcode::buffer_atomic_xor
;
6016 op64
= aco_opcode::buffer_atomic_xor_x2
;
6018 case nir_intrinsic_ssbo_atomic_exchange
:
6019 op32
= aco_opcode::buffer_atomic_swap
;
6020 op64
= aco_opcode::buffer_atomic_swap_x2
;
6022 case nir_intrinsic_ssbo_atomic_comp_swap
:
6023 op32
= aco_opcode::buffer_atomic_cmpswap
;
6024 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6027 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6029 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6030 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6031 mubuf
->operands
[0] = Operand(rsrc
);
6032 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6033 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6034 mubuf
->operands
[3] = Operand(data
);
6035 if (return_previous
)
6036 mubuf
->definitions
[0] = Definition(dst
);
6038 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6039 mubuf
->glc
= return_previous
;
6040 mubuf
->dlc
= false; /* Not needed for atomics */
6041 mubuf
->disable_wqm
= true;
6042 mubuf
->barrier
= barrier_buffer
;
6043 ctx
->program
->needs_exact
= true;
6044 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6047 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6049 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6050 Builder
bld(ctx
->program
, ctx
->block
);
6051 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6052 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6055 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
6057 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6058 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6060 if (addr
.type() == RegType::vgpr
)
6061 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
6062 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
6065 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6067 Builder
bld(ctx
->program
, ctx
->block
);
6068 unsigned num_components
= instr
->num_components
;
6069 unsigned num_bytes
= num_components
* instr
->dest
.ssa
.bit_size
/ 8;
6071 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6072 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6074 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6075 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
6077 if (dst
.type() == RegType::vgpr
|| (glc
&& ctx
->options
->chip_class
< GFX8
)) {
6078 bool global
= ctx
->options
->chip_class
>= GFX9
;
6080 if (ctx
->options
->chip_class
>= GFX7
) {
6082 switch (num_bytes
) {
6084 op
= global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
6087 op
= global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
6090 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
6093 op
= global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
6096 unreachable("load_global not implemented for this size.");
6099 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
6100 flat
->operands
[0] = Operand(addr
);
6101 flat
->operands
[1] = Operand(s1
);
6104 flat
->barrier
= barrier_buffer
;
6106 if (dst
.type() == RegType::sgpr
) {
6107 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
6108 flat
->definitions
[0] = Definition(vec
);
6109 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6110 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
6112 flat
->definitions
[0] = Definition(dst
);
6113 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6115 emit_split_vector(ctx
, dst
, num_components
);
6117 assert(ctx
->options
->chip_class
== GFX6
);
6119 /* GFX6 doesn't support loading vec3, expand to vec4. */
6120 num_bytes
= num_bytes
== 12 ? 16 : num_bytes
;
6123 switch (num_bytes
) {
6125 op
= aco_opcode::buffer_load_dword
;
6128 op
= aco_opcode::buffer_load_dwordx2
;
6131 op
= aco_opcode::buffer_load_dwordx4
;
6134 unreachable("load_global not implemented for this size.");
6137 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6139 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
6140 mubuf
->operands
[0] = Operand(rsrc
);
6141 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6142 mubuf
->operands
[2] = Operand(0u);
6146 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6147 mubuf
->disable_wqm
= false;
6148 mubuf
->barrier
= barrier_buffer
;
6149 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
6152 if (dst
.size() == 3) {
6153 Temp vec
= bld
.tmp(v4
);
6154 instr
->definitions
[0] = Definition(vec
);
6155 bld
.insert(std::move(instr
));
6156 emit_split_vector(ctx
, vec
, 4);
6158 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 3, 1));
6159 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, vec
, 0, v1
));
6160 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, vec
, 1, v1
));
6161 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, vec
, 2, v1
));
6164 if (dst
.type() == RegType::sgpr
) {
6165 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
6166 instr
->definitions
[0] = Definition(vec
);
6167 bld
.insert(std::move(instr
));
6168 expand_vector(ctx
, vec
, dst
, num_components
, (1 << num_components
) - 1);
6169 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
6171 instr
->definitions
[0] = Definition(dst
);
6172 bld
.insert(std::move(instr
));
6173 emit_split_vector(ctx
, dst
, num_components
);
6177 switch (num_bytes
) {
6179 op
= aco_opcode::s_load_dword
;
6182 op
= aco_opcode::s_load_dwordx2
;
6186 op
= aco_opcode::s_load_dwordx4
;
6189 unreachable("load_global not implemented for this size.");
6191 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
6192 load
->operands
[0] = Operand(addr
);
6193 load
->operands
[1] = Operand(0u);
6194 load
->definitions
[0] = Definition(dst
);
6197 load
->barrier
= barrier_buffer
;
6198 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
6200 if (dst
.size() == 3) {
6202 Temp vec
= bld
.tmp(s4
);
6203 load
->definitions
[0] = Definition(vec
);
6204 ctx
->block
->instructions
.emplace_back(std::move(load
));
6205 emit_split_vector(ctx
, vec
, 4);
6207 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6208 emit_extract_vector(ctx
, vec
, 0, s1
),
6209 emit_extract_vector(ctx
, vec
, 1, s1
),
6210 emit_extract_vector(ctx
, vec
, 2, s1
));
6212 ctx
->block
->instructions
.emplace_back(std::move(load
));
6217 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6219 Builder
bld(ctx
->program
, ctx
->block
);
6220 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6222 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6223 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6225 if (ctx
->options
->chip_class
>= GFX7
)
6226 addr
= as_vgpr(ctx
, addr
);
6228 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6231 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
6232 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
6233 /* GFX6 doesn't support storing vec3, split it. */
6234 writemask
|= 1u << (start
+ 2);
6237 unsigned num_bytes
= count
* elem_size_bytes
;
6239 Temp write_data
= data
;
6240 if (count
!= instr
->num_components
) {
6241 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6242 for (int i
= 0; i
< count
; i
++)
6243 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, data
, start
+ i
, v1
));
6244 write_data
= bld
.tmp(RegType::vgpr
, count
);
6245 vec
->definitions
[0] = Definition(write_data
);
6246 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6249 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6250 unsigned offset
= start
* elem_size_bytes
;
6252 if (ctx
->options
->chip_class
>= GFX7
) {
6253 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6254 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6255 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6256 Temp carry
= bld
.tmp(bld
.lm
);
6257 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6259 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6260 Operand(offset
), addr0
);
6261 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6263 carry
).def(1).setHint(vcc
);
6265 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6270 bool global
= ctx
->options
->chip_class
>= GFX9
;
6272 switch (num_bytes
) {
6274 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6277 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6280 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6283 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6286 unreachable("store_global not implemented for this size.");
6289 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6290 flat
->operands
[0] = Operand(addr
);
6291 flat
->operands
[1] = Operand(s1
);
6292 flat
->operands
[2] = Operand(data
);
6295 flat
->offset
= offset
;
6296 flat
->disable_wqm
= true;
6297 flat
->barrier
= barrier_buffer
;
6298 ctx
->program
->needs_exact
= true;
6299 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6301 assert(ctx
->options
->chip_class
== GFX6
);
6304 switch (num_bytes
) {
6306 op
= aco_opcode::buffer_store_dword
;
6309 op
= aco_opcode::buffer_store_dwordx2
;
6312 op
= aco_opcode::buffer_store_dwordx4
;
6315 unreachable("store_global not implemented for this size.");
6318 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6320 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6321 mubuf
->operands
[0] = Operand(rsrc
);
6322 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6323 mubuf
->operands
[2] = Operand(0u);
6324 mubuf
->operands
[3] = Operand(write_data
);
6327 mubuf
->offset
= offset
;
6328 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6329 mubuf
->disable_wqm
= true;
6330 mubuf
->barrier
= barrier_buffer
;
6331 ctx
->program
->needs_exact
= true;
6332 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6337 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6339 /* return the previous value if dest is ever used */
6340 bool return_previous
= false;
6341 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6342 return_previous
= true;
6345 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6346 return_previous
= true;
6350 Builder
bld(ctx
->program
, ctx
->block
);
6351 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6352 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6354 if (ctx
->options
->chip_class
>= GFX7
)
6355 addr
= as_vgpr(ctx
, addr
);
6357 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6358 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6359 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6361 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6363 aco_opcode op32
, op64
;
6365 if (ctx
->options
->chip_class
>= GFX7
) {
6366 bool global
= ctx
->options
->chip_class
>= GFX9
;
6367 switch (instr
->intrinsic
) {
6368 case nir_intrinsic_global_atomic_add
:
6369 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6370 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6372 case nir_intrinsic_global_atomic_imin
:
6373 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6374 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6376 case nir_intrinsic_global_atomic_umin
:
6377 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6378 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6380 case nir_intrinsic_global_atomic_imax
:
6381 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6382 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6384 case nir_intrinsic_global_atomic_umax
:
6385 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6386 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6388 case nir_intrinsic_global_atomic_and
:
6389 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6390 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6392 case nir_intrinsic_global_atomic_or
:
6393 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6394 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6396 case nir_intrinsic_global_atomic_xor
:
6397 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6398 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6400 case nir_intrinsic_global_atomic_exchange
:
6401 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6402 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6404 case nir_intrinsic_global_atomic_comp_swap
:
6405 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6406 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6409 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6412 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6413 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6414 flat
->operands
[0] = Operand(addr
);
6415 flat
->operands
[1] = Operand(s1
);
6416 flat
->operands
[2] = Operand(data
);
6417 if (return_previous
)
6418 flat
->definitions
[0] = Definition(dst
);
6419 flat
->glc
= return_previous
;
6420 flat
->dlc
= false; /* Not needed for atomics */
6422 flat
->disable_wqm
= true;
6423 flat
->barrier
= barrier_buffer
;
6424 ctx
->program
->needs_exact
= true;
6425 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6427 assert(ctx
->options
->chip_class
== GFX6
);
6429 switch (instr
->intrinsic
) {
6430 case nir_intrinsic_global_atomic_add
:
6431 op32
= aco_opcode::buffer_atomic_add
;
6432 op64
= aco_opcode::buffer_atomic_add_x2
;
6434 case nir_intrinsic_global_atomic_imin
:
6435 op32
= aco_opcode::buffer_atomic_smin
;
6436 op64
= aco_opcode::buffer_atomic_smin_x2
;
6438 case nir_intrinsic_global_atomic_umin
:
6439 op32
= aco_opcode::buffer_atomic_umin
;
6440 op64
= aco_opcode::buffer_atomic_umin_x2
;
6442 case nir_intrinsic_global_atomic_imax
:
6443 op32
= aco_opcode::buffer_atomic_smax
;
6444 op64
= aco_opcode::buffer_atomic_smax_x2
;
6446 case nir_intrinsic_global_atomic_umax
:
6447 op32
= aco_opcode::buffer_atomic_umax
;
6448 op64
= aco_opcode::buffer_atomic_umax_x2
;
6450 case nir_intrinsic_global_atomic_and
:
6451 op32
= aco_opcode::buffer_atomic_and
;
6452 op64
= aco_opcode::buffer_atomic_and_x2
;
6454 case nir_intrinsic_global_atomic_or
:
6455 op32
= aco_opcode::buffer_atomic_or
;
6456 op64
= aco_opcode::buffer_atomic_or_x2
;
6458 case nir_intrinsic_global_atomic_xor
:
6459 op32
= aco_opcode::buffer_atomic_xor
;
6460 op64
= aco_opcode::buffer_atomic_xor_x2
;
6462 case nir_intrinsic_global_atomic_exchange
:
6463 op32
= aco_opcode::buffer_atomic_swap
;
6464 op64
= aco_opcode::buffer_atomic_swap_x2
;
6466 case nir_intrinsic_global_atomic_comp_swap
:
6467 op32
= aco_opcode::buffer_atomic_cmpswap
;
6468 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6471 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6474 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6476 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6478 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6479 mubuf
->operands
[0] = Operand(rsrc
);
6480 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6481 mubuf
->operands
[2] = Operand(0u);
6482 mubuf
->operands
[3] = Operand(data
);
6483 if (return_previous
)
6484 mubuf
->definitions
[0] = Definition(dst
);
6485 mubuf
->glc
= return_previous
;
6488 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6489 mubuf
->disable_wqm
= true;
6490 mubuf
->barrier
= barrier_buffer
;
6491 ctx
->program
->needs_exact
= true;
6492 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6496 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6497 Builder
bld(ctx
->program
, ctx
->block
);
6498 switch(instr
->intrinsic
) {
6499 case nir_intrinsic_group_memory_barrier
:
6500 case nir_intrinsic_memory_barrier
:
6501 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6503 case nir_intrinsic_memory_barrier_buffer
:
6504 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6506 case nir_intrinsic_memory_barrier_image
:
6507 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6509 case nir_intrinsic_memory_barrier_tcs_patch
:
6510 case nir_intrinsic_memory_barrier_shared
:
6511 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6514 unreachable("Unimplemented memory barrier intrinsic");
6519 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6521 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6522 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6523 assert(instr
->dest
.ssa
.bit_size
>= 32 && "Bitsize not supported in load_shared.");
6524 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6525 Builder
bld(ctx
->program
, ctx
->block
);
6527 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6528 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6529 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6532 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6534 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6535 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6536 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6537 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6538 assert(elem_size_bytes
>= 4 && "Only 32bit & 64bit store_shared currently supported.");
6540 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6541 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6544 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6546 unsigned offset
= nir_intrinsic_base(instr
);
6547 Operand m
= load_lds_size_m0(ctx
);
6548 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6549 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6551 unsigned num_operands
= 3;
6552 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6553 switch(instr
->intrinsic
) {
6554 case nir_intrinsic_shared_atomic_add
:
6555 op32
= aco_opcode::ds_add_u32
;
6556 op64
= aco_opcode::ds_add_u64
;
6557 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6558 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6560 case nir_intrinsic_shared_atomic_imin
:
6561 op32
= aco_opcode::ds_min_i32
;
6562 op64
= aco_opcode::ds_min_i64
;
6563 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6564 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6566 case nir_intrinsic_shared_atomic_umin
:
6567 op32
= aco_opcode::ds_min_u32
;
6568 op64
= aco_opcode::ds_min_u64
;
6569 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6570 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6572 case nir_intrinsic_shared_atomic_imax
:
6573 op32
= aco_opcode::ds_max_i32
;
6574 op64
= aco_opcode::ds_max_i64
;
6575 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6576 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6578 case nir_intrinsic_shared_atomic_umax
:
6579 op32
= aco_opcode::ds_max_u32
;
6580 op64
= aco_opcode::ds_max_u64
;
6581 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6582 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6584 case nir_intrinsic_shared_atomic_and
:
6585 op32
= aco_opcode::ds_and_b32
;
6586 op64
= aco_opcode::ds_and_b64
;
6587 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6588 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6590 case nir_intrinsic_shared_atomic_or
:
6591 op32
= aco_opcode::ds_or_b32
;
6592 op64
= aco_opcode::ds_or_b64
;
6593 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6594 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6596 case nir_intrinsic_shared_atomic_xor
:
6597 op32
= aco_opcode::ds_xor_b32
;
6598 op64
= aco_opcode::ds_xor_b64
;
6599 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6600 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6602 case nir_intrinsic_shared_atomic_exchange
:
6603 op32
= aco_opcode::ds_write_b32
;
6604 op64
= aco_opcode::ds_write_b64
;
6605 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6606 op64_rtn
= aco_opcode::ds_wrxchg2_rtn_b64
;
6608 case nir_intrinsic_shared_atomic_comp_swap
:
6609 op32
= aco_opcode::ds_cmpst_b32
;
6610 op64
= aco_opcode::ds_cmpst_b64
;
6611 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6612 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6616 unreachable("Unhandled shared atomic intrinsic");
6619 /* return the previous value if dest is ever used */
6620 bool return_previous
= false;
6621 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6622 return_previous
= true;
6625 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6626 return_previous
= true;
6631 if (data
.size() == 1) {
6632 assert(instr
->dest
.ssa
.bit_size
== 32);
6633 op
= return_previous
? op32_rtn
: op32
;
6635 assert(instr
->dest
.ssa
.bit_size
== 64);
6636 op
= return_previous
? op64_rtn
: op64
;
6639 if (offset
> 65535) {
6640 Builder
bld(ctx
->program
, ctx
->block
);
6641 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6645 aco_ptr
<DS_instruction
> ds
;
6646 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6647 ds
->operands
[0] = Operand(address
);
6648 ds
->operands
[1] = Operand(data
);
6649 if (num_operands
== 4)
6650 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6651 ds
->operands
[num_operands
- 1] = m
;
6652 ds
->offset0
= offset
;
6653 if (return_previous
)
6654 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6655 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6658 Temp
get_scratch_resource(isel_context
*ctx
)
6660 Builder
bld(ctx
->program
, ctx
->block
);
6661 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6662 if (ctx
->stage
!= compute_cs
)
6663 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6665 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6666 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6668 if (ctx
->program
->chip_class
>= GFX10
) {
6669 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6670 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6671 S_008F0C_RESOURCE_LEVEL(1);
6672 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6673 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6674 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6677 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6678 if (ctx
->program
->chip_class
<= GFX8
)
6679 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6681 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6684 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6685 assert(instr
->dest
.ssa
.bit_size
== 32 || instr
->dest
.ssa
.bit_size
== 64);
6686 Builder
bld(ctx
->program
, ctx
->block
);
6687 Temp rsrc
= get_scratch_resource(ctx
);
6688 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6689 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6692 switch (dst
.size()) {
6694 op
= aco_opcode::buffer_load_dword
;
6697 op
= aco_opcode::buffer_load_dwordx2
;
6700 op
= aco_opcode::buffer_load_dwordx3
;
6703 op
= aco_opcode::buffer_load_dwordx4
;
6707 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
6708 Temp lower
= bld
.mubuf(aco_opcode::buffer_load_dwordx4
,
6709 bld
.def(v4
), rsrc
, offset
,
6710 ctx
->program
->scratch_offset
, 0, true);
6711 Temp upper
= bld
.mubuf(dst
.size() == 6 ? aco_opcode::buffer_load_dwordx2
:
6712 aco_opcode::buffer_load_dwordx4
,
6713 dst
.size() == 6 ? bld
.def(v2
) : bld
.def(v4
),
6714 rsrc
, offset
, ctx
->program
->scratch_offset
, 16, true);
6715 emit_split_vector(ctx
, lower
, 2);
6716 elems
[0] = emit_extract_vector(ctx
, lower
, 0, v2
);
6717 elems
[1] = emit_extract_vector(ctx
, lower
, 1, v2
);
6718 if (dst
.size() == 8) {
6719 emit_split_vector(ctx
, upper
, 2);
6720 elems
[2] = emit_extract_vector(ctx
, upper
, 0, v2
);
6721 elems
[3] = emit_extract_vector(ctx
, upper
, 1, v2
);
6726 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
6727 Format::PSEUDO
, dst
.size() / 2, 1)};
6728 for (unsigned i
= 0; i
< dst
.size() / 2; i
++)
6729 vec
->operands
[i
] = Operand(elems
[i
]);
6730 vec
->definitions
[0] = Definition(dst
);
6731 bld
.insert(std::move(vec
));
6732 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
6736 unreachable("Wrong dst size for nir_intrinsic_load_scratch");
6739 bld
.mubuf(op
, Definition(dst
), rsrc
, offset
, ctx
->program
->scratch_offset
, 0, true);
6740 emit_split_vector(ctx
, dst
, instr
->num_components
);
6743 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6744 assert(instr
->src
[0].ssa
->bit_size
== 32 || instr
->src
[0].ssa
->bit_size
== 64);
6745 Builder
bld(ctx
->program
, ctx
->block
);
6746 Temp rsrc
= get_scratch_resource(ctx
);
6747 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6748 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6750 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6751 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6755 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
6756 int num_bytes
= count
* elem_size_bytes
;
6758 if (num_bytes
> 16) {
6759 assert(elem_size_bytes
== 8);
6760 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
6765 // TODO: check alignment of sub-dword stores
6766 // TODO: split 3 bytes. there is no store instruction for that
6769 if (count
!= instr
->num_components
) {
6770 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6771 for (int i
= 0; i
< count
; i
++) {
6772 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(RegType::vgpr
, elem_size_bytes
/ 4));
6773 vec
->operands
[i
] = Operand(elem
);
6775 write_data
= bld
.tmp(RegClass(RegType::vgpr
, count
* elem_size_bytes
/ 4));
6776 vec
->definitions
[0] = Definition(write_data
);
6777 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6783 switch (num_bytes
) {
6785 op
= aco_opcode::buffer_store_dword
;
6788 op
= aco_opcode::buffer_store_dwordx2
;
6791 op
= aco_opcode::buffer_store_dwordx3
;
6794 op
= aco_opcode::buffer_store_dwordx4
;
6797 unreachable("Invalid data size for nir_intrinsic_store_scratch.");
6800 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_data
, start
* elem_size_bytes
, true);
6804 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6805 uint8_t log2_ps_iter_samples
;
6806 if (ctx
->program
->info
->ps
.force_persample
) {
6807 log2_ps_iter_samples
=
6808 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6810 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6813 /* The bit pattern matches that used by fixed function fragment
6815 static const unsigned ps_iter_masks
[] = {
6816 0xffff, /* not used */
6822 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6824 Builder
bld(ctx
->program
, ctx
->block
);
6826 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6827 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6828 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6829 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6830 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6831 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6834 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6835 Builder
bld(ctx
->program
, ctx
->block
);
6837 unsigned stream
= nir_intrinsic_stream_id(instr
);
6838 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6839 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6840 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6843 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6845 unsigned num_components
=
6846 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6847 assert(num_components
);
6849 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6850 unsigned stream_offset
= 0;
6851 for (unsigned i
= 0; i
< stream
; i
++) {
6852 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6853 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6856 /* Limit on the stride field for <= GFX7. */
6857 assert(stride
< (1 << 14));
6859 Temp gsvs_dwords
[4];
6860 for (unsigned i
= 0; i
< 4; i
++)
6861 gsvs_dwords
[i
] = bld
.tmp(s1
);
6862 bld
.pseudo(aco_opcode::p_split_vector
,
6863 Definition(gsvs_dwords
[0]),
6864 Definition(gsvs_dwords
[1]),
6865 Definition(gsvs_dwords
[2]),
6866 Definition(gsvs_dwords
[3]),
6869 if (stream_offset
) {
6870 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6872 Temp carry
= bld
.tmp(s1
);
6873 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6874 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6877 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6878 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6880 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6881 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6883 unsigned offset
= 0;
6884 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6885 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6888 for (unsigned j
= 0; j
< 4; j
++) {
6889 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6892 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6893 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6894 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6895 if (const_offset
>= 4096u) {
6896 if (vaddr_offset
.isUndefined())
6897 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6899 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6900 const_offset
%= 4096u;
6903 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6904 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6905 mtbuf
->operands
[1] = vaddr_offset
;
6906 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6907 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6908 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6909 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6910 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6911 mtbuf
->offset
= const_offset
;
6914 mtbuf
->barrier
= barrier_gs_data
;
6915 mtbuf
->can_reorder
= true;
6916 bld
.insert(std::move(mtbuf
));
6919 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6922 /* outputs for the next vertex are undefined and keeping them around can
6923 * create invalid IR with control flow */
6924 ctx
->outputs
.mask
[i
] = 0;
6927 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6930 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6932 Builder
bld(ctx
->program
, ctx
->block
);
6934 if (cluster_size
== 1) {
6936 } if (op
== nir_op_iand
&& cluster_size
== 4) {
6937 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6938 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6939 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6940 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
6941 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
6942 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6943 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6944 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
6945 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
6946 //subgroupAnd(val) -> (exec & ~val) == 0
6947 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
6948 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
6949 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
6950 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
6951 //subgroupOr(val) -> (val & exec) != 0
6952 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
6953 return bool_to_vector_condition(ctx
, tmp
);
6954 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
6955 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6956 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6957 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
6958 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
6959 return bool_to_vector_condition(ctx
, tmp
);
6961 //subgroupClustered{And,Or,Xor}(val, n) ->
6962 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
6963 //cluster_offset = ~(n - 1) & lane_id
6964 //cluster_mask = ((1 << n) - 1)
6965 //subgroupClusteredAnd():
6966 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6967 //subgroupClusteredOr():
6968 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
6969 //subgroupClusteredXor():
6970 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6971 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
6972 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
6975 if (op
== nir_op_iand
)
6976 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6978 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6980 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
6982 if (ctx
->program
->chip_class
<= GFX7
)
6983 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
6984 else if (ctx
->program
->wave_size
== 64)
6985 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
6987 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
6988 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
6989 if (cluster_mask
!= 0xffffffff)
6990 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
6992 Definition cmp_def
= Definition();
6993 if (op
== nir_op_iand
) {
6994 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
6995 } else if (op
== nir_op_ior
) {
6996 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6997 } else if (op
== nir_op_ixor
) {
6998 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
6999 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
7000 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7002 cmp_def
.setHint(vcc
);
7003 return cmp_def
.getTemp();
7007 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7009 Builder
bld(ctx
->program
, ctx
->block
);
7011 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
7012 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
7013 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
7015 if (op
== nir_op_iand
)
7016 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7018 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7020 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
7021 Temp lo
= lohi
.def(0).getTemp();
7022 Temp hi
= lohi
.def(1).getTemp();
7023 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7025 Definition cmp_def
= Definition();
7026 if (op
== nir_op_iand
)
7027 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7028 else if (op
== nir_op_ior
)
7029 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7030 else if (op
== nir_op_ixor
)
7031 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7032 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7033 cmp_def
.setHint(vcc
);
7034 return cmp_def
.getTemp();
7037 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7039 Builder
bld(ctx
->program
, ctx
->block
);
7041 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7042 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7043 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7044 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7045 if (op
== nir_op_iand
)
7046 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7047 else if (op
== nir_op_ior
)
7048 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7049 else if (op
== nir_op_ixor
)
7050 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7056 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7058 Builder
bld(ctx
->program
, ctx
->block
);
7059 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7060 if (src
.regClass().type() == RegType::vgpr
) {
7061 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7062 } else if (src
.regClass() == s1
) {
7063 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7064 } else if (src
.regClass() == s2
) {
7065 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7067 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7068 nir_print_instr(&instr
->instr
, stderr
);
7069 fprintf(stderr
, "\n");
7073 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7075 Builder
bld(ctx
->program
, ctx
->block
);
7076 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7077 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7078 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7080 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7081 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7082 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7083 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7086 if (ctx
->program
->chip_class
>= GFX8
) {
7087 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7088 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7089 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7090 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7091 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7092 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7094 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7095 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7096 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7097 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7098 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7099 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7100 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7101 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7102 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7103 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7106 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7107 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7108 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7109 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7110 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7111 Temp wqm1
= bld
.tmp(v1
);
7112 emit_wqm(ctx
, tmp1
, wqm1
, true);
7113 Temp wqm2
= bld
.tmp(v1
);
7114 emit_wqm(ctx
, tmp2
, wqm2
, true);
7115 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7119 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7121 Builder
bld(ctx
->program
, ctx
->block
);
7122 switch(instr
->intrinsic
) {
7123 case nir_intrinsic_load_barycentric_sample
:
7124 case nir_intrinsic_load_barycentric_pixel
:
7125 case nir_intrinsic_load_barycentric_centroid
: {
7126 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7127 Temp bary
= Temp(0, s2
);
7129 case INTERP_MODE_SMOOTH
:
7130 case INTERP_MODE_NONE
:
7131 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7132 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7133 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7134 bary
= ctx
->persp_centroid
;
7135 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7136 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7138 case INTERP_MODE_NOPERSPECTIVE
:
7139 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7140 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7141 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7142 bary
= ctx
->linear_centroid
;
7143 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7144 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7149 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7150 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7151 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7152 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7153 Operand(p1
), Operand(p2
));
7154 emit_split_vector(ctx
, dst
, 2);
7157 case nir_intrinsic_load_barycentric_model
: {
7158 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7160 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7161 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7162 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7163 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7164 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7165 Operand(p1
), Operand(p2
), Operand(p3
));
7166 emit_split_vector(ctx
, dst
, 3);
7169 case nir_intrinsic_load_barycentric_at_sample
: {
7170 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7171 switch (ctx
->options
->key
.fs
.num_samples
) {
7172 case 2: sample_pos_offset
+= 1 << 3; break;
7173 case 4: sample_pos_offset
+= 3 << 3; break;
7174 case 8: sample_pos_offset
+= 7 << 3; break;
7178 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7179 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7180 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7181 if (addr
.type() == RegType::sgpr
) {
7184 sample_pos_offset
+= const_addr
->u32
<< 3;
7185 offset
= Operand(sample_pos_offset
);
7186 } else if (ctx
->options
->chip_class
>= GFX9
) {
7187 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7189 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7190 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7193 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7194 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7196 } else if (ctx
->options
->chip_class
>= GFX9
) {
7197 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7198 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7199 } else if (ctx
->options
->chip_class
>= GFX7
) {
7200 /* addr += private_segment_buffer + sample_pos_offset */
7201 Temp tmp0
= bld
.tmp(s1
);
7202 Temp tmp1
= bld
.tmp(s1
);
7203 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7204 Definition scc_tmp
= bld
.def(s1
, scc
);
7205 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7206 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7207 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7208 Temp pck0
= bld
.tmp(v1
);
7209 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7210 tmp1
= as_vgpr(ctx
, tmp1
);
7211 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7212 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7214 /* sample_pos = flat_load_dwordx2 addr */
7215 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7217 assert(ctx
->options
->chip_class
== GFX6
);
7219 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7220 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7221 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7223 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7224 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7226 sample_pos
= bld
.tmp(v2
);
7228 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7229 load
->definitions
[0] = Definition(sample_pos
);
7230 load
->operands
[0] = Operand(rsrc
);
7231 load
->operands
[1] = Operand(addr
);
7232 load
->operands
[2] = Operand(0u);
7233 load
->offset
= sample_pos_offset
;
7235 load
->addr64
= true;
7238 load
->disable_wqm
= false;
7239 load
->barrier
= barrier_none
;
7240 load
->can_reorder
= true;
7241 ctx
->block
->instructions
.emplace_back(std::move(load
));
7244 /* sample_pos -= 0.5 */
7245 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7246 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7247 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7248 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7249 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7251 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7254 case nir_intrinsic_load_barycentric_at_offset
: {
7255 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7256 RegClass rc
= RegClass(offset
.type(), 1);
7257 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7258 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7259 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7262 case nir_intrinsic_load_front_face
: {
7263 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7264 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7267 case nir_intrinsic_load_view_index
: {
7268 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7269 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7270 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7276 case nir_intrinsic_load_layer_id
: {
7277 unsigned idx
= nir_intrinsic_base(instr
);
7278 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7279 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7282 case nir_intrinsic_load_frag_coord
: {
7283 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7286 case nir_intrinsic_load_sample_pos
: {
7287 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7288 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7289 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7290 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7291 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7294 case nir_intrinsic_load_tess_coord
:
7295 visit_load_tess_coord(ctx
, instr
);
7297 case nir_intrinsic_load_interpolated_input
:
7298 visit_load_interpolated_input(ctx
, instr
);
7300 case nir_intrinsic_store_output
:
7301 visit_store_output(ctx
, instr
);
7303 case nir_intrinsic_load_input
:
7304 case nir_intrinsic_load_input_vertex
:
7305 visit_load_input(ctx
, instr
);
7307 case nir_intrinsic_load_output
:
7308 visit_load_output(ctx
, instr
);
7310 case nir_intrinsic_load_per_vertex_input
:
7311 visit_load_per_vertex_input(ctx
, instr
);
7313 case nir_intrinsic_load_per_vertex_output
:
7314 visit_load_per_vertex_output(ctx
, instr
);
7316 case nir_intrinsic_store_per_vertex_output
:
7317 visit_store_per_vertex_output(ctx
, instr
);
7319 case nir_intrinsic_load_ubo
:
7320 visit_load_ubo(ctx
, instr
);
7322 case nir_intrinsic_load_push_constant
:
7323 visit_load_push_constant(ctx
, instr
);
7325 case nir_intrinsic_load_constant
:
7326 visit_load_constant(ctx
, instr
);
7328 case nir_intrinsic_vulkan_resource_index
:
7329 visit_load_resource(ctx
, instr
);
7331 case nir_intrinsic_discard
:
7332 visit_discard(ctx
, instr
);
7334 case nir_intrinsic_discard_if
:
7335 visit_discard_if(ctx
, instr
);
7337 case nir_intrinsic_load_shared
:
7338 visit_load_shared(ctx
, instr
);
7340 case nir_intrinsic_store_shared
:
7341 visit_store_shared(ctx
, instr
);
7343 case nir_intrinsic_shared_atomic_add
:
7344 case nir_intrinsic_shared_atomic_imin
:
7345 case nir_intrinsic_shared_atomic_umin
:
7346 case nir_intrinsic_shared_atomic_imax
:
7347 case nir_intrinsic_shared_atomic_umax
:
7348 case nir_intrinsic_shared_atomic_and
:
7349 case nir_intrinsic_shared_atomic_or
:
7350 case nir_intrinsic_shared_atomic_xor
:
7351 case nir_intrinsic_shared_atomic_exchange
:
7352 case nir_intrinsic_shared_atomic_comp_swap
:
7353 visit_shared_atomic(ctx
, instr
);
7355 case nir_intrinsic_image_deref_load
:
7356 visit_image_load(ctx
, instr
);
7358 case nir_intrinsic_image_deref_store
:
7359 visit_image_store(ctx
, instr
);
7361 case nir_intrinsic_image_deref_atomic_add
:
7362 case nir_intrinsic_image_deref_atomic_umin
:
7363 case nir_intrinsic_image_deref_atomic_imin
:
7364 case nir_intrinsic_image_deref_atomic_umax
:
7365 case nir_intrinsic_image_deref_atomic_imax
:
7366 case nir_intrinsic_image_deref_atomic_and
:
7367 case nir_intrinsic_image_deref_atomic_or
:
7368 case nir_intrinsic_image_deref_atomic_xor
:
7369 case nir_intrinsic_image_deref_atomic_exchange
:
7370 case nir_intrinsic_image_deref_atomic_comp_swap
:
7371 visit_image_atomic(ctx
, instr
);
7373 case nir_intrinsic_image_deref_size
:
7374 visit_image_size(ctx
, instr
);
7376 case nir_intrinsic_load_ssbo
:
7377 visit_load_ssbo(ctx
, instr
);
7379 case nir_intrinsic_store_ssbo
:
7380 visit_store_ssbo(ctx
, instr
);
7382 case nir_intrinsic_load_global
:
7383 visit_load_global(ctx
, instr
);
7385 case nir_intrinsic_store_global
:
7386 visit_store_global(ctx
, instr
);
7388 case nir_intrinsic_global_atomic_add
:
7389 case nir_intrinsic_global_atomic_imin
:
7390 case nir_intrinsic_global_atomic_umin
:
7391 case nir_intrinsic_global_atomic_imax
:
7392 case nir_intrinsic_global_atomic_umax
:
7393 case nir_intrinsic_global_atomic_and
:
7394 case nir_intrinsic_global_atomic_or
:
7395 case nir_intrinsic_global_atomic_xor
:
7396 case nir_intrinsic_global_atomic_exchange
:
7397 case nir_intrinsic_global_atomic_comp_swap
:
7398 visit_global_atomic(ctx
, instr
);
7400 case nir_intrinsic_ssbo_atomic_add
:
7401 case nir_intrinsic_ssbo_atomic_imin
:
7402 case nir_intrinsic_ssbo_atomic_umin
:
7403 case nir_intrinsic_ssbo_atomic_imax
:
7404 case nir_intrinsic_ssbo_atomic_umax
:
7405 case nir_intrinsic_ssbo_atomic_and
:
7406 case nir_intrinsic_ssbo_atomic_or
:
7407 case nir_intrinsic_ssbo_atomic_xor
:
7408 case nir_intrinsic_ssbo_atomic_exchange
:
7409 case nir_intrinsic_ssbo_atomic_comp_swap
:
7410 visit_atomic_ssbo(ctx
, instr
);
7412 case nir_intrinsic_load_scratch
:
7413 visit_load_scratch(ctx
, instr
);
7415 case nir_intrinsic_store_scratch
:
7416 visit_store_scratch(ctx
, instr
);
7418 case nir_intrinsic_get_buffer_size
:
7419 visit_get_buffer_size(ctx
, instr
);
7421 case nir_intrinsic_control_barrier
: {
7422 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7423 /* GFX6 only (thanks to a hw bug workaround):
7424 * The real barrier instruction isn’t needed, because an entire patch
7425 * always fits into a single wave.
7430 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7431 bld
.sopp(aco_opcode::s_barrier
);
7435 case nir_intrinsic_memory_barrier_tcs_patch
:
7436 case nir_intrinsic_group_memory_barrier
:
7437 case nir_intrinsic_memory_barrier
:
7438 case nir_intrinsic_memory_barrier_buffer
:
7439 case nir_intrinsic_memory_barrier_image
:
7440 case nir_intrinsic_memory_barrier_shared
:
7441 emit_memory_barrier(ctx
, instr
);
7443 case nir_intrinsic_load_num_work_groups
: {
7444 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7445 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7446 emit_split_vector(ctx
, dst
, 3);
7449 case nir_intrinsic_load_local_invocation_id
: {
7450 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7451 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7452 emit_split_vector(ctx
, dst
, 3);
7455 case nir_intrinsic_load_work_group_id
: {
7456 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7457 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7458 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7459 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7460 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7461 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7462 emit_split_vector(ctx
, dst
, 3);
7465 case nir_intrinsic_load_local_invocation_index
: {
7466 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7468 /* The tg_size bits [6:11] contain the subgroup id,
7469 * we need this multiplied by the wave size, and then OR the thread id to it.
7471 if (ctx
->program
->wave_size
== 64) {
7472 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7473 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7474 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7475 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7477 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7478 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7479 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7480 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7484 case nir_intrinsic_load_subgroup_id
: {
7485 if (ctx
->stage
== compute_cs
) {
7486 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7487 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7489 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7493 case nir_intrinsic_load_subgroup_invocation
: {
7494 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7497 case nir_intrinsic_load_num_subgroups
: {
7498 if (ctx
->stage
== compute_cs
)
7499 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7500 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7502 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7505 case nir_intrinsic_ballot
: {
7506 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7507 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7508 Definition tmp
= bld
.def(dst
.regClass());
7509 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7510 if (instr
->src
[0].ssa
->bit_size
== 1) {
7511 assert(src
.regClass() == bld
.lm
);
7512 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7513 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7514 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7515 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7516 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7518 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7519 nir_print_instr(&instr
->instr
, stderr
);
7520 fprintf(stderr
, "\n");
7522 if (dst
.size() != bld
.lm
.size()) {
7523 /* Wave32 with ballot size set to 64 */
7524 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7526 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7529 case nir_intrinsic_shuffle
:
7530 case nir_intrinsic_read_invocation
: {
7531 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7532 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
]) {
7533 emit_uniform_subgroup(ctx
, instr
, src
);
7535 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7536 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !ctx
->divergent_vals
[instr
->src
[1].ssa
->index
])
7537 tid
= bld
.as_uniform(tid
);
7538 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7539 if (src
.regClass() == v1
) {
7540 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7541 } else if (src
.regClass() == v2
) {
7542 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7543 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7544 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7545 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7546 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7547 emit_split_vector(ctx
, dst
, 2);
7548 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7549 assert(src
.regClass() == bld
.lm
);
7550 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7551 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7552 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7553 assert(src
.regClass() == bld
.lm
);
7555 if (ctx
->program
->chip_class
<= GFX7
)
7556 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7557 else if (ctx
->program
->wave_size
== 64)
7558 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7560 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7561 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7562 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7563 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7565 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7566 nir_print_instr(&instr
->instr
, stderr
);
7567 fprintf(stderr
, "\n");
7572 case nir_intrinsic_load_sample_id
: {
7573 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7574 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7577 case nir_intrinsic_load_sample_mask_in
: {
7578 visit_load_sample_mask_in(ctx
, instr
);
7581 case nir_intrinsic_read_first_invocation
: {
7582 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7583 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7584 if (src
.regClass() == v1
) {
7586 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7588 } else if (src
.regClass() == v2
) {
7589 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7590 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7591 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7592 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7593 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7594 emit_split_vector(ctx
, dst
, 2);
7595 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7596 assert(src
.regClass() == bld
.lm
);
7597 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7598 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7599 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7600 } else if (src
.regClass() == s1
) {
7601 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7602 } else if (src
.regClass() == s2
) {
7603 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7605 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7606 nir_print_instr(&instr
->instr
, stderr
);
7607 fprintf(stderr
, "\n");
7611 case nir_intrinsic_vote_all
: {
7612 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7613 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7614 assert(src
.regClass() == bld
.lm
);
7615 assert(dst
.regClass() == bld
.lm
);
7617 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7618 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7619 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7622 case nir_intrinsic_vote_any
: {
7623 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7624 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7625 assert(src
.regClass() == bld
.lm
);
7626 assert(dst
.regClass() == bld
.lm
);
7628 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7629 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7632 case nir_intrinsic_reduce
:
7633 case nir_intrinsic_inclusive_scan
:
7634 case nir_intrinsic_exclusive_scan
: {
7635 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7636 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7637 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7638 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7639 nir_intrinsic_cluster_size(instr
) : 0;
7640 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7642 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
] && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7643 emit_uniform_subgroup(ctx
, instr
, src
);
7644 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7645 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7647 else if (op
== nir_op_iadd
)
7649 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7651 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7653 switch (instr
->intrinsic
) {
7654 case nir_intrinsic_reduce
:
7655 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7657 case nir_intrinsic_exclusive_scan
:
7658 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7660 case nir_intrinsic_inclusive_scan
:
7661 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7666 } else if (cluster_size
== 1) {
7667 bld
.copy(Definition(dst
), src
);
7669 src
= as_vgpr(ctx
, src
);
7673 #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
7688 unreachable("unknown reduction op");
7693 switch (instr
->intrinsic
) {
7694 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7695 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7696 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7698 unreachable("unknown reduce intrinsic");
7701 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7702 reduce
->operands
[0] = Operand(src
);
7703 // filled in by aco_reduce_assign.cpp, used internally as part of the
7705 assert(dst
.size() == 1 || dst
.size() == 2);
7706 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7707 reduce
->operands
[2] = Operand(v1
.as_linear());
7709 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7710 reduce
->definitions
[0] = Definition(tmp_dst
);
7711 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7712 reduce
->definitions
[2] = Definition();
7713 reduce
->definitions
[3] = Definition(scc
, s1
);
7714 reduce
->definitions
[4] = Definition();
7715 reduce
->reduce_op
= reduce_op
;
7716 reduce
->cluster_size
= cluster_size
;
7717 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7719 emit_wqm(ctx
, tmp_dst
, dst
);
7723 case nir_intrinsic_quad_broadcast
: {
7724 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7725 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7726 emit_uniform_subgroup(ctx
, instr
, src
);
7728 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7729 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7730 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7732 if (instr
->dest
.ssa
.bit_size
== 1) {
7733 assert(src
.regClass() == bld
.lm
);
7734 assert(dst
.regClass() == bld
.lm
);
7735 uint32_t half_mask
= 0x11111111u
<< lane
;
7736 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7737 Temp tmp
= bld
.tmp(bld
.lm
);
7738 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7739 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7740 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7741 emit_wqm(ctx
, tmp
, dst
);
7742 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7743 if (ctx
->program
->chip_class
>= GFX8
)
7744 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7746 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7747 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7748 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7749 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7750 if (ctx
->program
->chip_class
>= GFX8
) {
7751 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7752 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7754 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7755 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7757 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7758 emit_split_vector(ctx
, dst
, 2);
7760 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7761 nir_print_instr(&instr
->instr
, stderr
);
7762 fprintf(stderr
, "\n");
7767 case nir_intrinsic_quad_swap_horizontal
:
7768 case nir_intrinsic_quad_swap_vertical
:
7769 case nir_intrinsic_quad_swap_diagonal
:
7770 case nir_intrinsic_quad_swizzle_amd
: {
7771 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7772 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7773 emit_uniform_subgroup(ctx
, instr
, src
);
7776 uint16_t dpp_ctrl
= 0;
7777 switch (instr
->intrinsic
) {
7778 case nir_intrinsic_quad_swap_horizontal
:
7779 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7781 case nir_intrinsic_quad_swap_vertical
:
7782 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7784 case nir_intrinsic_quad_swap_diagonal
:
7785 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7787 case nir_intrinsic_quad_swizzle_amd
:
7788 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7793 if (ctx
->program
->chip_class
< GFX8
)
7794 dpp_ctrl
|= (1 << 15);
7796 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7797 if (instr
->dest
.ssa
.bit_size
== 1) {
7798 assert(src
.regClass() == bld
.lm
);
7799 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7800 if (ctx
->program
->chip_class
>= GFX8
)
7801 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7803 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7804 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7805 emit_wqm(ctx
, tmp
, dst
);
7806 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7808 if (ctx
->program
->chip_class
>= GFX8
)
7809 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7811 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7812 emit_wqm(ctx
, tmp
, dst
);
7813 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7814 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7815 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7816 if (ctx
->program
->chip_class
>= GFX8
) {
7817 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7818 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7820 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7821 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7823 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7824 emit_split_vector(ctx
, dst
, 2);
7826 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7827 nir_print_instr(&instr
->instr
, stderr
);
7828 fprintf(stderr
, "\n");
7832 case nir_intrinsic_masked_swizzle_amd
: {
7833 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7834 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7835 emit_uniform_subgroup(ctx
, instr
, src
);
7838 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7839 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7840 if (dst
.regClass() == v1
) {
7842 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
7844 } else if (dst
.regClass() == v2
) {
7845 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7846 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7847 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
7848 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
7849 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7850 emit_split_vector(ctx
, dst
, 2);
7852 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7853 nir_print_instr(&instr
->instr
, stderr
);
7854 fprintf(stderr
, "\n");
7858 case nir_intrinsic_write_invocation_amd
: {
7859 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7860 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7861 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7862 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7863 if (dst
.regClass() == v1
) {
7864 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7865 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7866 } else if (dst
.regClass() == v2
) {
7867 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7868 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7869 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7870 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7871 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7872 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7873 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7874 emit_split_vector(ctx
, dst
, 2);
7876 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7877 nir_print_instr(&instr
->instr
, stderr
);
7878 fprintf(stderr
, "\n");
7882 case nir_intrinsic_mbcnt_amd
: {
7883 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7884 RegClass rc
= RegClass(src
.type(), 1);
7885 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7886 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7887 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7888 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7889 emit_wqm(ctx
, wqm_tmp
, dst
);
7892 case nir_intrinsic_load_helper_invocation
: {
7893 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7894 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7895 ctx
->block
->kind
|= block_kind_needs_lowering
;
7896 ctx
->program
->needs_exact
= true;
7899 case nir_intrinsic_is_helper_invocation
: {
7900 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7901 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7902 ctx
->block
->kind
|= block_kind_needs_lowering
;
7903 ctx
->program
->needs_exact
= true;
7906 case nir_intrinsic_demote
:
7907 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7909 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7910 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7911 ctx
->block
->kind
|= block_kind_uses_demote
;
7912 ctx
->program
->needs_exact
= true;
7914 case nir_intrinsic_demote_if
: {
7915 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7916 assert(src
.regClass() == bld
.lm
);
7917 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7918 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
7920 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7921 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7922 ctx
->block
->kind
|= block_kind_uses_demote
;
7923 ctx
->program
->needs_exact
= true;
7926 case nir_intrinsic_first_invocation
: {
7927 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
7928 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7931 case nir_intrinsic_shader_clock
:
7932 bld
.smem(aco_opcode::s_memtime
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
7933 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
7935 case nir_intrinsic_load_vertex_id_zero_base
: {
7936 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7937 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
7940 case nir_intrinsic_load_first_vertex
: {
7941 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7942 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
7945 case nir_intrinsic_load_base_instance
: {
7946 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7947 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
7950 case nir_intrinsic_load_instance_id
: {
7951 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7952 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
7955 case nir_intrinsic_load_draw_id
: {
7956 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7957 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
7960 case nir_intrinsic_load_invocation_id
: {
7961 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7963 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
7964 if (ctx
->options
->chip_class
>= GFX10
)
7965 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7967 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7968 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7969 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
7970 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
7972 unreachable("Unsupported stage for load_invocation_id");
7977 case nir_intrinsic_load_primitive_id
: {
7978 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7980 switch (ctx
->shader
->info
.stage
) {
7981 case MESA_SHADER_GEOMETRY
:
7982 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
7984 case MESA_SHADER_TESS_CTRL
:
7985 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
7987 case MESA_SHADER_TESS_EVAL
:
7988 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
7991 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
7996 case nir_intrinsic_load_patch_vertices_in
: {
7997 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
7998 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8000 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8001 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8004 case nir_intrinsic_emit_vertex_with_counter
: {
8005 visit_emit_vertex_with_counter(ctx
, instr
);
8008 case nir_intrinsic_end_primitive_with_counter
: {
8009 unsigned stream
= nir_intrinsic_stream_id(instr
);
8010 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8013 case nir_intrinsic_set_vertex_count
: {
8014 /* unused, the HW keeps track of this for us */
8018 fprintf(stderr
, "Unimplemented intrinsic instr: ");
8019 nir_print_instr(&instr
->instr
, stderr
);
8020 fprintf(stderr
, "\n");
8028 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8029 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8030 enum glsl_base_type
*stype
)
8032 nir_deref_instr
*texture_deref_instr
= NULL
;
8033 nir_deref_instr
*sampler_deref_instr
= NULL
;
8036 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8037 switch (instr
->src
[i
].src_type
) {
8038 case nir_tex_src_texture_deref
:
8039 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8041 case nir_tex_src_sampler_deref
:
8042 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8044 case nir_tex_src_plane
:
8045 plane
= nir_src_as_int(instr
->src
[i
].src
);
8052 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8054 if (!sampler_deref_instr
)
8055 sampler_deref_instr
= texture_deref_instr
;
8058 assert(instr
->op
!= nir_texop_txf_ms
&&
8059 instr
->op
!= nir_texop_samples_identical
);
8060 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8061 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8062 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8063 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8064 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8065 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8067 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8070 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8072 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8073 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8074 Builder
bld(ctx
->program
, ctx
->block
);
8076 /* to avoid unnecessary moves, we split and recombine sampler and image */
8077 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8078 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8079 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8080 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8081 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8082 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8083 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8084 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8086 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8087 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8088 img
[0], img
[1], img
[2], img
[3],
8089 img
[4], img
[5], img
[6], img
[7]);
8090 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8091 samp
[0], samp
[1], samp
[2], samp
[3]);
8094 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8095 instr
->op
== nir_texop_samples_identical
))
8096 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8099 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8100 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8102 Builder
bld(ctx
->program
, ctx
->block
);
8104 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8105 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8106 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8108 Operand
neg_one(0xbf800000u
);
8109 Operand
one(0x3f800000u
);
8110 Operand
two(0x40000000u
);
8111 Operand
four(0x40800000u
);
8113 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8114 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8115 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8117 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8118 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8119 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8120 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8123 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8124 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8125 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8127 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8130 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8131 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8132 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8135 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8136 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8138 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8139 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8142 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8144 Builder
bld(ctx
->program
, ctx
->block
);
8145 Temp ma
, tc
, sc
, id
;
8148 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8150 // see comment in ac_prepare_cube_coords()
8151 if (ctx
->options
->chip_class
<= GFX8
)
8152 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8155 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8157 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8158 vop3a
->operands
[0] = Operand(ma
);
8159 vop3a
->abs
[0] = true;
8160 Temp invma
= bld
.tmp(v1
);
8161 vop3a
->definitions
[0] = Definition(invma
);
8162 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8164 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8166 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8168 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8170 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8172 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8175 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8176 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8178 for (unsigned i
= 0; i
< 2; i
++) {
8179 // see comment in ac_prepare_cube_coords()
8181 Temp deriv_sc
, deriv_tc
;
8182 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8183 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8185 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8187 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8188 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8189 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8190 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8191 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8192 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8193 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8196 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8197 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8201 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8208 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8210 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8212 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8213 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8216 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8217 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8218 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8222 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8224 Builder
bld(ctx
->program
, ctx
->block
);
8225 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8226 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false;
8227 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8228 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp();
8229 std::vector
<Temp
> coords
;
8230 std::vector
<Temp
> derivs
;
8231 nir_const_value
*sample_index_cv
= NULL
;
8232 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8233 enum glsl_base_type stype
;
8234 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8236 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8237 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8238 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8239 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8241 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8242 switch (instr
->src
[i
].src_type
) {
8243 case nir_tex_src_coord
: {
8244 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8245 for (unsigned i
= 0; i
< coord
.size(); i
++)
8246 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8249 case nir_tex_src_bias
:
8250 if (instr
->op
== nir_texop_txb
) {
8251 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8255 case nir_tex_src_lod
: {
8256 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8258 if (val
&& val
->f32
<= 0.0) {
8261 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8266 case nir_tex_src_comparator
:
8267 if (instr
->is_shadow
) {
8268 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8272 case nir_tex_src_offset
:
8273 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8274 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8277 case nir_tex_src_ddx
:
8278 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8281 case nir_tex_src_ddy
:
8282 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8285 case nir_tex_src_ms_index
:
8286 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8287 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8288 has_sample_index
= true;
8290 case nir_tex_src_texture_offset
:
8291 case nir_tex_src_sampler_offset
:
8297 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8298 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8300 if (instr
->op
== nir_texop_texture_samples
) {
8301 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8303 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8304 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8305 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8306 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8308 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8309 samples
, Operand(1u), bld
.scc(is_msaa
));
8313 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8314 aco_ptr
<Instruction
> tmp_instr
;
8315 Temp acc
, pack
= Temp();
8317 uint32_t pack_const
= 0;
8318 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8319 if (!const_offset
[i
])
8321 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8324 if (offset
.type() == RegType::sgpr
) {
8325 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8326 if (const_offset
[i
])
8329 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8330 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8333 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8336 if (pack
== Temp()) {
8339 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8343 if (pack_const
&& pack
!= Temp())
8344 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8346 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8347 if (const_offset
[i
])
8350 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8351 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8354 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8357 if (pack
== Temp()) {
8360 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8364 if (pack_const
&& pack
!= Temp())
8365 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8367 if (pack_const
&& pack
== Temp())
8368 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8369 else if (pack
== Temp())
8375 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8376 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8378 /* pack derivatives */
8379 if (has_ddx
|| has_ddy
) {
8380 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8381 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8382 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8383 derivs
= {ddy
, zero
, ddy
, zero
};
8385 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8386 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8387 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8388 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8393 if (instr
->coord_components
> 1 &&
8394 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8396 instr
->op
!= nir_texop_txf
)
8397 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8399 if (instr
->coord_components
> 2 &&
8400 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8401 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8402 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8403 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8405 instr
->op
!= nir_texop_txf
&&
8406 instr
->op
!= nir_texop_txf_ms
&&
8407 instr
->op
!= nir_texop_fragment_fetch
&&
8408 instr
->op
!= nir_texop_fragment_mask_fetch
)
8409 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8411 if (ctx
->options
->chip_class
== GFX9
&&
8412 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8413 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8414 assert(coords
.size() > 0 && coords
.size() < 3);
8416 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8417 Operand((uint32_t) 0) :
8418 Operand((uint32_t) 0x3f000000)));
8421 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8423 if (instr
->op
== nir_texop_samples_identical
)
8424 resource
= fmask_ptr
;
8426 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8427 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8428 instr
->op
!= nir_texop_txs
&&
8429 instr
->op
!= nir_texop_fragment_fetch
&&
8430 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8431 assert(has_sample_index
);
8432 Operand
op(sample_index
);
8433 if (sample_index_cv
)
8434 op
= Operand(sample_index_cv
->u32
);
8435 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8438 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8439 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8440 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8441 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8446 /* Build tex instruction */
8447 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8448 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8449 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8451 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8454 /* gather4 selects the component by dmask and always returns vec4 */
8455 if (instr
->op
== nir_texop_tg4
) {
8456 assert(instr
->dest
.ssa
.num_components
== 4);
8457 if (instr
->is_shadow
)
8460 dmask
= 1 << instr
->component
;
8461 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8462 tmp_dst
= bld
.tmp(v4
);
8463 } else if (instr
->op
== nir_texop_samples_identical
) {
8464 tmp_dst
= bld
.tmp(v1
);
8465 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8466 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8469 aco_ptr
<MIMG_instruction
> tex
;
8470 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8472 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8474 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8475 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8478 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8479 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8481 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8482 tex
->operands
[0] = Operand(resource
);
8483 tex
->operands
[1] = Operand(s4
); /* no sampler */
8484 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8485 if (ctx
->options
->chip_class
== GFX9
&&
8486 instr
->op
== nir_texop_txs
&&
8487 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8489 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8490 } else if (instr
->op
== nir_texop_query_levels
) {
8491 tex
->dmask
= 1 << 3;
8496 tex
->definitions
[0] = Definition(tmp_dst
);
8498 tex
->can_reorder
= true;
8499 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8502 /* divide 3rd value by 6 by multiplying with magic number */
8503 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8504 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8505 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8506 assert(instr
->dest
.ssa
.num_components
== 3);
8507 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8508 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8509 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8510 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8515 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8519 Temp tg4_compare_cube_wa64
= Temp();
8521 if (tg4_integer_workarounds
) {
8522 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8523 tex
->operands
[0] = Operand(resource
);
8524 tex
->operands
[1] = Operand(s4
); /* no sampler */
8525 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8529 Temp size
= bld
.tmp(v2
);
8530 tex
->definitions
[0] = Definition(size
);
8531 tex
->can_reorder
= true;
8532 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8533 emit_split_vector(ctx
, size
, size
.size());
8536 for (unsigned i
= 0; i
< 2; i
++) {
8537 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8538 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8539 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8540 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8543 Temp new_coords
[2] = {
8544 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8545 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8548 if (tg4_integer_cube_workaround
) {
8549 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8550 Temp desc
[resource
.size()];
8551 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8552 Format::PSEUDO
, 1, resource
.size())};
8553 split
->operands
[0] = Operand(resource
);
8554 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8555 desc
[i
] = bld
.tmp(s1
);
8556 split
->definitions
[i
] = Definition(desc
[i
]);
8558 ctx
->block
->instructions
.emplace_back(std::move(split
));
8560 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8561 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8562 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8565 if (stype
== GLSL_TYPE_UINT
) {
8566 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8567 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8568 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8569 bld
.scc(compare_cube_wa
));
8571 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8572 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8573 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8574 bld
.scc(compare_cube_wa
));
8576 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8577 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8579 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8581 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8582 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8583 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8585 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8586 Format::PSEUDO
, resource
.size(), 1)};
8587 for (unsigned i
= 0; i
< resource
.size(); i
++)
8588 vec
->operands
[i
] = Operand(desc
[i
]);
8589 resource
= bld
.tmp(resource
.regClass());
8590 vec
->definitions
[0] = Definition(resource
);
8591 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8593 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8594 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8595 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8596 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8598 coords
[0] = new_coords
[0];
8599 coords
[1] = new_coords
[1];
8602 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8603 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8605 assert(coords
.size() == 1);
8606 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8610 op
= aco_opcode::buffer_load_format_x
; break;
8612 op
= aco_opcode::buffer_load_format_xy
; break;
8614 op
= aco_opcode::buffer_load_format_xyz
; break;
8616 op
= aco_opcode::buffer_load_format_xyzw
; break;
8618 unreachable("Tex instruction loads more than 4 components.");
8621 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8622 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8625 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8627 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8628 mubuf
->operands
[0] = Operand(resource
);
8629 mubuf
->operands
[1] = Operand(coords
[0]);
8630 mubuf
->operands
[2] = Operand((uint32_t) 0);
8631 mubuf
->definitions
[0] = Definition(tmp_dst
);
8632 mubuf
->idxen
= true;
8633 mubuf
->can_reorder
= true;
8634 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8636 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8640 /* gather MIMG address components */
8641 std::vector
<Temp
> args
;
8643 args
.emplace_back(offset
);
8645 args
.emplace_back(bias
);
8647 args
.emplace_back(compare
);
8649 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8651 args
.insert(args
.end(), coords
.begin(), coords
.end());
8652 if (has_sample_index
)
8653 args
.emplace_back(sample_index
);
8655 args
.emplace_back(lod
);
8657 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8658 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8659 vec
->definitions
[0] = Definition(arg
);
8660 for (unsigned i
= 0; i
< args
.size(); i
++)
8661 vec
->operands
[i
] = Operand(args
[i
]);
8662 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8665 if (instr
->op
== nir_texop_txf
||
8666 instr
->op
== nir_texop_txf_ms
||
8667 instr
->op
== nir_texop_samples_identical
||
8668 instr
->op
== nir_texop_fragment_fetch
||
8669 instr
->op
== nir_texop_fragment_mask_fetch
) {
8670 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8671 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8672 tex
->operands
[0] = Operand(resource
);
8673 tex
->operands
[1] = Operand(s4
); /* no sampler */
8674 tex
->operands
[2] = Operand(arg
);
8679 tex
->definitions
[0] = Definition(tmp_dst
);
8680 tex
->can_reorder
= true;
8681 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8683 if (instr
->op
== nir_texop_samples_identical
) {
8684 assert(dmask
== 1 && dst
.regClass() == v1
);
8685 assert(dst
.id() != tmp_dst
.id());
8687 Temp tmp
= bld
.tmp(bld
.lm
);
8688 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8689 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8692 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8697 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8698 aco_opcode opcode
= aco_opcode::image_sample
;
8699 if (has_offset
) { /* image_sample_*_o */
8701 opcode
= aco_opcode::image_sample_c_o
;
8703 opcode
= aco_opcode::image_sample_c_d_o
;
8705 opcode
= aco_opcode::image_sample_c_b_o
;
8707 opcode
= aco_opcode::image_sample_c_lz_o
;
8709 opcode
= aco_opcode::image_sample_c_l_o
;
8711 opcode
= aco_opcode::image_sample_o
;
8713 opcode
= aco_opcode::image_sample_d_o
;
8715 opcode
= aco_opcode::image_sample_b_o
;
8717 opcode
= aco_opcode::image_sample_lz_o
;
8719 opcode
= aco_opcode::image_sample_l_o
;
8721 } else { /* no offset */
8723 opcode
= aco_opcode::image_sample_c
;
8725 opcode
= aco_opcode::image_sample_c_d
;
8727 opcode
= aco_opcode::image_sample_c_b
;
8729 opcode
= aco_opcode::image_sample_c_lz
;
8731 opcode
= aco_opcode::image_sample_c_l
;
8733 opcode
= aco_opcode::image_sample
;
8735 opcode
= aco_opcode::image_sample_d
;
8737 opcode
= aco_opcode::image_sample_b
;
8739 opcode
= aco_opcode::image_sample_lz
;
8741 opcode
= aco_opcode::image_sample_l
;
8745 if (instr
->op
== nir_texop_tg4
) {
8747 opcode
= aco_opcode::image_gather4_lz_o
;
8749 opcode
= aco_opcode::image_gather4_c_lz_o
;
8751 opcode
= aco_opcode::image_gather4_lz
;
8753 opcode
= aco_opcode::image_gather4_c_lz
;
8755 } else if (instr
->op
== nir_texop_lod
) {
8756 opcode
= aco_opcode::image_get_lod
;
8759 /* we don't need the bias, sample index, compare value or offset to be
8760 * computed in WQM but if the p_create_vector copies the coordinates, then it
8761 * needs to be in WQM */
8762 if (ctx
->stage
== fragment_fs
&&
8763 !has_derivs
&& !has_lod
&& !level_zero
&&
8764 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8765 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8766 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8768 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8769 tex
->operands
[0] = Operand(resource
);
8770 tex
->operands
[1] = Operand(sampler
);
8771 tex
->operands
[2] = Operand(arg
);
8775 tex
->definitions
[0] = Definition(tmp_dst
);
8776 tex
->can_reorder
= true;
8777 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8779 if (tg4_integer_cube_workaround
) {
8780 assert(tmp_dst
.id() != dst
.id());
8781 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8783 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8785 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8786 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8788 if (stype
== GLSL_TYPE_UINT
)
8789 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8791 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8792 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8794 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8795 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8796 val
[0], val
[1], val
[2], val
[3]);
8798 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8799 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8804 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
)
8806 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8807 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
8808 return Operand(tmp
.regClass());
8810 return Operand(tmp
);
8813 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8815 aco_ptr
<Pseudo_instruction
> phi
;
8816 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8817 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8819 bool logical
= !dst
.is_linear() || ctx
->divergent_vals
[instr
->dest
.ssa
.index
];
8820 logical
|= ctx
->block
->kind
& block_kind_merge
;
8821 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8823 /* we want a sorted list of sources, since the predecessor list is also sorted */
8824 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8825 nir_foreach_phi_src(src
, instr
)
8826 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8828 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8829 unsigned num_operands
= 0;
8830 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8831 unsigned num_defined
= 0;
8832 unsigned cur_pred_idx
= 0;
8833 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8834 if (cur_pred_idx
< preds
.size()) {
8835 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8836 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8837 unsigned skipped
= 0;
8838 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8840 if (cur_pred_idx
+ skipped
< preds
.size()) {
8841 for (unsigned i
= 0; i
< skipped
; i
++)
8842 operands
[num_operands
++] = Operand(dst
.regClass());
8843 cur_pred_idx
+= skipped
;
8848 /* Handle missing predecessors at the end. This shouldn't happen with loop
8849 * headers and we can't ignore these sources for loop header phis. */
8850 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8853 Operand op
= get_phi_operand(ctx
, src
.second
);
8854 operands
[num_operands
++] = op
;
8855 num_defined
+= !op
.isUndefined();
8857 /* handle block_kind_continue_or_break at loop exit blocks */
8858 while (cur_pred_idx
++ < preds
.size())
8859 operands
[num_operands
++] = Operand(dst
.regClass());
8861 /* If the loop ends with a break, still add a linear continue edge in case
8862 * that break is divergent or continue_or_break is used. We'll either remove
8863 * this operand later in visit_loop() if it's not necessary or replace the
8864 * undef with something correct. */
8865 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
8866 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
8867 nir_block
*last
= nir_loop_last_block(loop
);
8868 if (last
->successors
[0] != instr
->instr
.block
)
8869 operands
[num_operands
++] = Operand(RegClass());
8872 if (num_defined
== 0) {
8873 Builder
bld(ctx
->program
, ctx
->block
);
8874 if (dst
.regClass() == s1
) {
8875 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
8876 } else if (dst
.regClass() == v1
) {
8877 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
8879 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8880 for (unsigned i
= 0; i
< dst
.size(); i
++)
8881 vec
->operands
[i
] = Operand(0u);
8882 vec
->definitions
[0] = Definition(dst
);
8883 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8888 /* we can use a linear phi in some cases if one src is undef */
8889 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
8890 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
8892 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
8893 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
8894 assert(invert
->kind
& block_kind_invert
);
8896 unsigned then_block
= invert
->linear_preds
[0];
8898 Block
* insert_block
= NULL
;
8899 for (unsigned i
= 0; i
< num_operands
; i
++) {
8900 Operand op
= operands
[i
];
8901 if (op
.isUndefined())
8903 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
8904 phi
->operands
[0] = op
;
8907 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
8908 phi
->operands
[1] = Operand(dst
.regClass());
8909 phi
->definitions
[0] = Definition(dst
);
8910 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
8914 /* try to scalarize vector phis */
8915 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
8916 // TODO: scalarize linear phis on divergent ifs
8917 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
8918 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
8919 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
8920 Operand src
= operands
[i
];
8921 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
8922 can_scalarize
= false;
8924 if (can_scalarize
) {
8925 unsigned num_components
= instr
->dest
.ssa
.num_components
;
8926 assert(dst
.size() % num_components
== 0);
8927 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
8929 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
8930 for (unsigned k
= 0; k
< num_components
; k
++) {
8931 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8932 for (unsigned i
= 0; i
< num_operands
; i
++) {
8933 Operand src
= operands
[i
];
8934 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
8936 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
8937 phi
->definitions
[0] = Definition(phi_dst
);
8938 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
8939 new_vec
[k
] = phi_dst
;
8940 vec
->operands
[k
] = Operand(phi_dst
);
8942 vec
->definitions
[0] = Definition(dst
);
8943 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8944 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
8949 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8950 for (unsigned i
= 0; i
< num_operands
; i
++)
8951 phi
->operands
[i
] = operands
[i
];
8952 phi
->definitions
[0] = Definition(dst
);
8953 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
8957 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
8959 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
8961 assert(dst
.type() == RegType::sgpr
);
8963 if (dst
.size() == 1) {
8964 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
8966 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8967 for (unsigned i
= 0; i
< dst
.size(); i
++)
8968 vec
->operands
[i
] = Operand(0u);
8969 vec
->definitions
[0] = Definition(dst
);
8970 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8974 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
8976 Builder
bld(ctx
->program
, ctx
->block
);
8977 Block
*logical_target
;
8978 append_logical_end(ctx
->block
);
8979 unsigned idx
= ctx
->block
->index
;
8981 switch (instr
->type
) {
8982 case nir_jump_break
:
8983 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
8984 add_logical_edge(idx
, logical_target
);
8985 ctx
->block
->kind
|= block_kind_break
;
8987 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
8988 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
8989 /* uniform break - directly jump out of the loop */
8990 ctx
->block
->kind
|= block_kind_uniform
;
8991 ctx
->cf_info
.has_branch
= true;
8992 bld
.branch(aco_opcode::p_branch
);
8993 add_linear_edge(idx
, logical_target
);
8996 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
8997 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
8999 case nir_jump_continue
:
9000 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9001 add_logical_edge(idx
, logical_target
);
9002 ctx
->block
->kind
|= block_kind_continue
;
9004 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9005 /* for potential uniform breaks after this continue,
9006 we must ensure that they are handled correctly */
9007 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9008 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9009 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9011 /* uniform continue - directly jump to the loop header */
9012 ctx
->block
->kind
|= block_kind_uniform
;
9013 ctx
->cf_info
.has_branch
= true;
9014 bld
.branch(aco_opcode::p_branch
);
9015 add_linear_edge(idx
, logical_target
);
9020 fprintf(stderr
, "Unknown NIR jump instr: ");
9021 nir_print_instr(&instr
->instr
, stderr
);
9022 fprintf(stderr
, "\n");
9026 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9027 ctx
->cf_info
.exec_potentially_empty_break
= true;
9028 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9031 /* remove critical edges from linear CFG */
9032 bld
.branch(aco_opcode::p_branch
);
9033 Block
* break_block
= ctx
->program
->create_and_insert_block();
9034 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9035 break_block
->kind
|= block_kind_uniform
;
9036 add_linear_edge(idx
, break_block
);
9037 /* the loop_header pointer might be invalidated by this point */
9038 if (instr
->type
== nir_jump_continue
)
9039 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9040 add_linear_edge(break_block
->index
, logical_target
);
9041 bld
.reset(break_block
);
9042 bld
.branch(aco_opcode::p_branch
);
9044 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9045 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9046 add_linear_edge(idx
, continue_block
);
9047 append_logical_start(continue_block
);
9048 ctx
->block
= continue_block
;
9052 void visit_block(isel_context
*ctx
, nir_block
*block
)
9054 nir_foreach_instr(instr
, block
) {
9055 switch (instr
->type
) {
9056 case nir_instr_type_alu
:
9057 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9059 case nir_instr_type_load_const
:
9060 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9062 case nir_instr_type_intrinsic
:
9063 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9065 case nir_instr_type_tex
:
9066 visit_tex(ctx
, nir_instr_as_tex(instr
));
9068 case nir_instr_type_phi
:
9069 visit_phi(ctx
, nir_instr_as_phi(instr
));
9071 case nir_instr_type_ssa_undef
:
9072 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9074 case nir_instr_type_deref
:
9076 case nir_instr_type_jump
:
9077 visit_jump(ctx
, nir_instr_as_jump(instr
));
9080 fprintf(stderr
, "Unknown NIR instr type: ");
9081 nir_print_instr(instr
, stderr
);
9082 fprintf(stderr
, "\n");
9087 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9088 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9093 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9094 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9096 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9097 RegClass rc
= vals
[0].regClass();
9099 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9101 unsigned next_pred
= 1;
9103 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9104 Block
& block
= ctx
->program
->blocks
[idx
];
9105 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9106 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9110 if (block
.kind
& block_kind_continue
) {
9111 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9116 bool all_same
= true;
9117 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9118 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9122 val
= vals
[block
.linear_preds
[0] - first
];
9124 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9125 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9126 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9127 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9128 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9129 phi
->definitions
[0] = Definition(val
.getTemp());
9130 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9132 vals
[idx
- first
] = val
;
9135 return vals
[last
- first
];
9138 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9140 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9141 append_logical_end(ctx
->block
);
9142 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9143 Builder
bld(ctx
->program
, ctx
->block
);
9144 bld
.branch(aco_opcode::p_branch
);
9145 unsigned loop_preheader_idx
= ctx
->block
->index
;
9147 Block loop_exit
= Block();
9148 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9149 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9151 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9152 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9153 loop_header
->kind
|= block_kind_loop_header
;
9154 add_edge(loop_preheader_idx
, loop_header
);
9155 ctx
->block
= loop_header
;
9157 /* emit loop body */
9158 unsigned loop_header_idx
= loop_header
->index
;
9159 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9160 append_logical_start(ctx
->block
);
9161 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9163 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9164 if (!ctx
->cf_info
.has_branch
) {
9165 append_logical_end(ctx
->block
);
9166 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9167 /* Discards can result in code running with an empty exec mask.
9168 * This would result in divergent breaks not ever being taken. As a
9169 * workaround, break the loop when the loop mask is empty instead of
9170 * always continuing. */
9171 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9172 unsigned block_idx
= ctx
->block
->index
;
9174 /* create helper blocks to avoid critical edges */
9175 Block
*break_block
= ctx
->program
->create_and_insert_block();
9176 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9177 break_block
->kind
= block_kind_uniform
;
9178 bld
.reset(break_block
);
9179 bld
.branch(aco_opcode::p_branch
);
9180 add_linear_edge(block_idx
, break_block
);
9181 add_linear_edge(break_block
->index
, &loop_exit
);
9183 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9184 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9185 continue_block
->kind
= block_kind_uniform
;
9186 bld
.reset(continue_block
);
9187 bld
.branch(aco_opcode::p_branch
);
9188 add_linear_edge(block_idx
, continue_block
);
9189 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9191 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9192 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9193 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9195 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9196 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9197 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9199 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9202 bld
.reset(ctx
->block
);
9203 bld
.branch(aco_opcode::p_branch
);
9206 /* Fixup phis in loop header from unreachable blocks.
9207 * has_branch/has_divergent_branch also indicates if the loop ends with a
9208 * break/continue instruction, but we don't emit those if unreachable=true */
9210 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9211 bool linear
= ctx
->cf_info
.has_branch
;
9212 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9213 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9214 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9215 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9216 /* the last operand should be the one that needs to be removed */
9217 instr
->operands
.pop_back();
9218 } else if (!is_phi(instr
)) {
9224 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9225 * and the previous one shouldn't both happen at once because a break in the
9226 * merge block would get CSE'd */
9227 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9228 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9229 Operand vals
[num_vals
];
9230 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9231 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9232 if (ctx
->cf_info
.has_branch
)
9233 instr
->operands
.pop_back();
9235 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9236 } else if (!is_phi(instr
)) {
9242 ctx
->cf_info
.has_branch
= false;
9244 // TODO: if the loop has not a single exit, we must add one °°
9245 /* emit loop successor block */
9246 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9247 append_logical_start(ctx
->block
);
9250 // TODO: check if it is beneficial to not branch on continues
9251 /* trim linear phis in loop header */
9252 for (auto&& instr
: loop_entry
->instructions
) {
9253 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9254 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9255 new_phi
->definitions
[0] = instr
->definitions
[0];
9256 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9257 new_phi
->operands
[i
] = instr
->operands
[i
];
9258 /* check that the remaining operands are all the same */
9259 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9260 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9261 instr
.swap(new_phi
);
9262 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9271 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9275 append_logical_end(ctx
->block
);
9276 ctx
->block
->kind
|= block_kind_branch
;
9278 /* branch to linear then block */
9279 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9280 aco_ptr
<Pseudo_branch_instruction
> branch
;
9281 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9282 branch
->operands
[0] = Operand(cond
);
9283 ctx
->block
->instructions
.push_back(std::move(branch
));
9285 ic
->BB_if_idx
= ctx
->block
->index
;
9286 ic
->BB_invert
= Block();
9287 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9288 /* Invert blocks are intentionally not marked as top level because they
9289 * are not part of the logical cfg. */
9290 ic
->BB_invert
.kind
|= block_kind_invert
;
9291 ic
->BB_endif
= Block();
9292 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9293 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9295 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9296 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9297 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9298 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9299 ctx
->cf_info
.parent_if
.is_divergent
= true;
9301 /* divergent branches use cbranch_execz */
9302 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9303 ctx
->cf_info
.exec_potentially_empty_break
= false;
9304 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9306 /** emit logical then block */
9307 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9308 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9309 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9310 ctx
->block
= BB_then_logical
;
9311 append_logical_start(BB_then_logical
);
9314 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9316 Block
*BB_then_logical
= ctx
->block
;
9317 append_logical_end(BB_then_logical
);
9318 /* branch from logical then block to invert block */
9319 aco_ptr
<Pseudo_branch_instruction
> branch
;
9320 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9321 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9322 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9323 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9324 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9325 BB_then_logical
->kind
|= block_kind_uniform
;
9326 assert(!ctx
->cf_info
.has_branch
);
9327 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9328 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9330 /** emit linear then block */
9331 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9332 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9333 BB_then_linear
->kind
|= block_kind_uniform
;
9334 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9335 /* branch from linear then block to invert block */
9336 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9337 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9338 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9340 /** emit invert merge block */
9341 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9342 ic
->invert_idx
= ctx
->block
->index
;
9344 /* branch to linear else block (skip else) */
9345 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9346 branch
->operands
[0] = Operand(ic
->cond
);
9347 ctx
->block
->instructions
.push_back(std::move(branch
));
9349 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9350 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9351 ic
->exec_potentially_empty_break_depth_old
=
9352 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9353 /* divergent branches use cbranch_execz */
9354 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9355 ctx
->cf_info
.exec_potentially_empty_break
= false;
9356 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9358 /** emit logical else block */
9359 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9360 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9361 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9362 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9363 ctx
->block
= BB_else_logical
;
9364 append_logical_start(BB_else_logical
);
9367 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9369 Block
*BB_else_logical
= ctx
->block
;
9370 append_logical_end(BB_else_logical
);
9372 /* branch from logical else block to endif block */
9373 aco_ptr
<Pseudo_branch_instruction
> branch
;
9374 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9375 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9376 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9377 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9378 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9379 BB_else_logical
->kind
|= block_kind_uniform
;
9381 assert(!ctx
->cf_info
.has_branch
);
9382 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9385 /** emit linear else block */
9386 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9387 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9388 BB_else_linear
->kind
|= block_kind_uniform
;
9389 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9391 /* branch from linear else block to endif block */
9392 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9393 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9394 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9397 /** emit endif merge block */
9398 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9399 append_logical_start(ctx
->block
);
9402 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9403 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9404 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9405 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9406 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9407 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9408 !ctx
->cf_info
.parent_if
.is_divergent
) {
9409 ctx
->cf_info
.exec_potentially_empty_break
= false;
9410 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9412 /* uniform control flow never has an empty exec-mask */
9413 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9414 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9415 ctx
->cf_info
.exec_potentially_empty_break
= false;
9416 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9420 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9422 assert(cond
.regClass() == s1
);
9424 append_logical_end(ctx
->block
);
9425 ctx
->block
->kind
|= block_kind_uniform
;
9427 aco_ptr
<Pseudo_branch_instruction
> branch
;
9428 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9429 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9430 branch
->operands
[0] = Operand(cond
);
9431 branch
->operands
[0].setFixed(scc
);
9432 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9434 ic
->BB_if_idx
= ctx
->block
->index
;
9435 ic
->BB_endif
= Block();
9436 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9437 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9439 ctx
->cf_info
.has_branch
= false;
9440 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9442 /** emit then block */
9443 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9444 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9445 add_edge(ic
->BB_if_idx
, BB_then
);
9446 append_logical_start(BB_then
);
9447 ctx
->block
= BB_then
;
9450 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9452 Block
*BB_then
= ctx
->block
;
9454 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9455 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9457 if (!ic
->uniform_has_then_branch
) {
9458 append_logical_end(BB_then
);
9459 /* branch from then block to endif block */
9460 aco_ptr
<Pseudo_branch_instruction
> branch
;
9461 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9462 BB_then
->instructions
.emplace_back(std::move(branch
));
9463 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9464 if (!ic
->then_branch_divergent
)
9465 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9466 BB_then
->kind
|= block_kind_uniform
;
9469 ctx
->cf_info
.has_branch
= false;
9470 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9472 /** emit else block */
9473 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9474 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9475 add_edge(ic
->BB_if_idx
, BB_else
);
9476 append_logical_start(BB_else
);
9477 ctx
->block
= BB_else
;
9480 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9482 Block
*BB_else
= ctx
->block
;
9484 if (!ctx
->cf_info
.has_branch
) {
9485 append_logical_end(BB_else
);
9486 /* branch from then block to endif block */
9487 aco_ptr
<Pseudo_branch_instruction
> branch
;
9488 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9489 BB_else
->instructions
.emplace_back(std::move(branch
));
9490 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9491 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9492 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9493 BB_else
->kind
|= block_kind_uniform
;
9496 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9497 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9499 /** emit endif merge block */
9500 if (!ctx
->cf_info
.has_branch
) {
9501 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9502 append_logical_start(ctx
->block
);
9506 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9508 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9509 Builder
bld(ctx
->program
, ctx
->block
);
9510 aco_ptr
<Pseudo_branch_instruction
> branch
;
9513 if (!ctx
->divergent_vals
[if_stmt
->condition
.ssa
->index
]) { /* uniform condition */
9515 * Uniform conditionals are represented in the following way*) :
9517 * The linear and logical CFG:
9520 * BB_THEN (logical) BB_ELSE (logical)
9524 * *) Exceptions may be due to break and continue statements within loops
9525 * If a break/continue happens within uniform control flow, it branches
9526 * to the loop exit/entry block. Otherwise, it branches to the next
9530 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9531 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9532 cond
= bool_to_scalar_condition(ctx
, cond
);
9534 begin_uniform_if_then(ctx
, &ic
, cond
);
9535 visit_cf_list(ctx
, &if_stmt
->then_list
);
9537 begin_uniform_if_else(ctx
, &ic
);
9538 visit_cf_list(ctx
, &if_stmt
->else_list
);
9540 end_uniform_if(ctx
, &ic
);
9542 return !ctx
->cf_info
.has_branch
;
9543 } else { /* non-uniform condition */
9545 * To maintain a logical and linear CFG without critical edges,
9546 * non-uniform conditionals are represented in the following way*) :
9551 * BB_THEN (logical) BB_THEN (linear)
9553 * BB_INVERT (linear)
9555 * BB_ELSE (logical) BB_ELSE (linear)
9562 * BB_THEN (logical) BB_ELSE (logical)
9566 * *) Exceptions may be due to break and continue statements within loops
9569 begin_divergent_if_then(ctx
, &ic
, cond
);
9570 visit_cf_list(ctx
, &if_stmt
->then_list
);
9572 begin_divergent_if_else(ctx
, &ic
);
9573 visit_cf_list(ctx
, &if_stmt
->else_list
);
9575 end_divergent_if(ctx
, &ic
);
9581 static bool visit_cf_list(isel_context
*ctx
,
9582 struct exec_list
*list
)
9584 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9585 switch (node
->type
) {
9586 case nir_cf_node_block
:
9587 visit_block(ctx
, nir_cf_node_as_block(node
));
9589 case nir_cf_node_if
:
9590 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9593 case nir_cf_node_loop
:
9594 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9597 unreachable("unimplemented cf list type");
9603 static void create_null_export(isel_context
*ctx
)
9605 /* Some shader stages always need to have exports.
9606 * So when there is none, we need to add a null export.
9609 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9610 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9611 Builder
bld(ctx
->program
, ctx
->block
);
9612 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9613 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9616 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9618 assert(ctx
->stage
== vertex_vs
||
9619 ctx
->stage
== tess_eval_vs
||
9620 ctx
->stage
== gs_copy_vs
||
9621 ctx
->stage
== ngg_vertex_gs
||
9622 ctx
->stage
== ngg_tess_eval_gs
);
9624 int offset
= (ctx
->stage
& sw_tes
)
9625 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9626 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9627 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9628 if (!is_pos
&& !mask
)
9630 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9632 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9633 exp
->enabled_mask
= mask
;
9634 for (unsigned i
= 0; i
< 4; ++i
) {
9635 if (mask
& (1 << i
))
9636 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9638 exp
->operands
[i
] = Operand(v1
);
9640 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9641 * Setting valid_mask=1 prevents it and has no other effect.
9643 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9645 exp
->compressed
= false;
9647 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9649 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9650 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9655 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9657 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9658 exp
->enabled_mask
= 0;
9659 for (unsigned i
= 0; i
< 4; ++i
)
9660 exp
->operands
[i
] = Operand(v1
);
9661 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9662 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9663 exp
->enabled_mask
|= 0x1;
9665 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9666 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9667 exp
->enabled_mask
|= 0x4;
9669 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9670 if (ctx
->options
->chip_class
< GFX9
) {
9671 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9672 exp
->enabled_mask
|= 0x8;
9674 Builder
bld(ctx
->program
, ctx
->block
);
9676 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9677 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9678 if (exp
->operands
[2].isTemp())
9679 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9681 exp
->operands
[2] = Operand(out
);
9682 exp
->enabled_mask
|= 0x4;
9685 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9687 exp
->compressed
= false;
9688 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9689 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9692 static void create_export_phis(isel_context
*ctx
)
9694 /* Used when exports are needed, but the output temps are defined in a preceding block.
9695 * This function will set up phis in order to access the outputs in the next block.
9698 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9699 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9700 ctx
->block
->instructions
.pop_back();
9702 Builder
bld(ctx
->program
, ctx
->block
);
9704 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9705 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9706 for (unsigned i
= 0; i
< 4; ++i
) {
9707 if (!(mask
& (1 << i
)))
9710 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9711 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9712 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9716 bld
.insert(std::move(logical_start
));
9719 static void create_vs_exports(isel_context
*ctx
)
9721 assert(ctx
->stage
== vertex_vs
||
9722 ctx
->stage
== tess_eval_vs
||
9723 ctx
->stage
== gs_copy_vs
||
9724 ctx
->stage
== ngg_vertex_gs
||
9725 ctx
->stage
== ngg_tess_eval_gs
);
9727 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9728 ? &ctx
->program
->info
->tes
.outinfo
9729 : &ctx
->program
->info
->vs
.outinfo
;
9731 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9732 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9733 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9736 if (ctx
->options
->key
.has_multiview_view_index
) {
9737 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9738 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9741 /* the order these position exports are created is important */
9743 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9744 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9745 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9746 exported_pos
= true;
9748 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9749 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9750 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9751 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9753 if (ctx
->export_clip_dists
) {
9754 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9755 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9756 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9757 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9760 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9761 if (i
< VARYING_SLOT_VAR0
&&
9762 i
!= VARYING_SLOT_LAYER
&&
9763 i
!= VARYING_SLOT_PRIMITIVE_ID
)
9766 export_vs_varying(ctx
, i
, false, NULL
);
9770 create_null_export(ctx
);
9773 static bool export_fs_mrt_z(isel_context
*ctx
)
9775 Builder
bld(ctx
->program
, ctx
->block
);
9776 unsigned enabled_channels
= 0;
9780 for (unsigned i
= 0; i
< 4; ++i
) {
9781 values
[i
] = Operand(v1
);
9784 /* Both stencil and sample mask only need 16-bits. */
9785 if (!ctx
->program
->info
->ps
.writes_z
&&
9786 (ctx
->program
->info
->ps
.writes_stencil
||
9787 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9788 compr
= true; /* COMPR flag */
9790 if (ctx
->program
->info
->ps
.writes_stencil
) {
9791 /* Stencil should be in X[23:16]. */
9792 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9793 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9794 enabled_channels
|= 0x3;
9797 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9798 /* SampleMask should be in Y[15:0]. */
9799 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9800 enabled_channels
|= 0xc;
9803 if (ctx
->program
->info
->ps
.writes_z
) {
9804 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9805 enabled_channels
|= 0x1;
9808 if (ctx
->program
->info
->ps
.writes_stencil
) {
9809 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9810 enabled_channels
|= 0x2;
9813 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9814 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9815 enabled_channels
|= 0x4;
9819 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9820 * writemask component.
9822 if (ctx
->options
->chip_class
== GFX6
&&
9823 ctx
->options
->family
!= CHIP_OLAND
&&
9824 ctx
->options
->family
!= CHIP_HAINAN
) {
9825 enabled_channels
|= 0x1;
9828 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9829 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9834 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9836 Builder
bld(ctx
->program
, ctx
->block
);
9837 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9840 for (unsigned i
= 0; i
< 4; ++i
) {
9841 if (write_mask
& (1 << i
)) {
9842 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9844 values
[i
] = Operand(v1
);
9848 unsigned target
, col_format
;
9849 unsigned enabled_channels
= 0;
9850 aco_opcode compr_op
= (aco_opcode
)0;
9852 slot
-= FRAG_RESULT_DATA0
;
9853 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9854 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9856 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9857 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
9861 case V_028714_SPI_SHADER_ZERO
:
9862 enabled_channels
= 0; /* writemask */
9863 target
= V_008DFC_SQ_EXP_NULL
;
9866 case V_028714_SPI_SHADER_32_R
:
9867 enabled_channels
= 1;
9870 case V_028714_SPI_SHADER_32_GR
:
9871 enabled_channels
= 0x3;
9874 case V_028714_SPI_SHADER_32_AR
:
9875 if (ctx
->options
->chip_class
>= GFX10
) {
9876 /* Special case: on GFX10, the outputs are different for 32_AR */
9877 enabled_channels
= 0x3;
9878 values
[1] = values
[3];
9879 values
[3] = Operand(v1
);
9881 enabled_channels
= 0x9;
9885 case V_028714_SPI_SHADER_FP16_ABGR
:
9886 enabled_channels
= 0x5;
9887 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
9890 case V_028714_SPI_SHADER_UNORM16_ABGR
:
9891 enabled_channels
= 0x5;
9892 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
9895 case V_028714_SPI_SHADER_SNORM16_ABGR
:
9896 enabled_channels
= 0x5;
9897 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
9900 case V_028714_SPI_SHADER_UINT16_ABGR
: {
9901 enabled_channels
= 0x5;
9902 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
9903 if (is_int8
|| is_int10
) {
9905 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
9906 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9908 for (unsigned i
= 0; i
< 4; i
++) {
9909 if ((write_mask
>> i
) & 1) {
9910 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
9911 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
9919 case V_028714_SPI_SHADER_SINT16_ABGR
:
9920 enabled_channels
= 0x5;
9921 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
9922 if (is_int8
|| is_int10
) {
9924 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
9925 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
9926 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9927 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
9929 for (unsigned i
= 0; i
< 4; i
++) {
9930 if ((write_mask
>> i
) & 1) {
9931 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
9932 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
9934 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
9935 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
9942 case V_028714_SPI_SHADER_32_ABGR
:
9943 enabled_channels
= 0xF;
9950 if (target
== V_008DFC_SQ_EXP_NULL
)
9953 if ((bool) compr_op
) {
9954 for (int i
= 0; i
< 2; i
++) {
9955 /* check if at least one of the values to be compressed is enabled */
9956 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
9958 enabled_channels
|= enabled
<< (i
*2);
9959 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
9960 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
9961 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
9963 values
[i
] = Operand(v1
);
9966 values
[2] = Operand(v1
);
9967 values
[3] = Operand(v1
);
9969 for (int i
= 0; i
< 4; i
++)
9970 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
9973 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9974 enabled_channels
, target
, (bool) compr_op
);
9978 static void create_fs_exports(isel_context
*ctx
)
9980 bool exported
= false;
9982 /* Export depth, stencil and sample mask. */
9983 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
9984 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
9985 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
9986 exported
|= export_fs_mrt_z(ctx
);
9988 /* Export all color render targets. */
9989 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
9990 if (ctx
->outputs
.mask
[i
])
9991 exported
|= export_fs_mrt_color(ctx
, i
);
9994 create_null_export(ctx
);
9997 static void write_tcs_tess_factors(isel_context
*ctx
)
9999 unsigned outer_comps
;
10000 unsigned inner_comps
;
10002 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10019 Builder
bld(ctx
->program
, ctx
->block
);
10021 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10022 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
10023 bld
.sopp(aco_opcode::s_barrier
);
10025 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10026 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10028 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10029 if_context ic_invocation_id_is_zero
;
10030 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10031 bld
.reset(ctx
->block
);
10033 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10035 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10036 unsigned stride
= inner_comps
+ outer_comps
;
10037 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10041 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10043 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10045 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10046 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10047 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10049 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10050 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10052 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10053 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10054 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10055 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10058 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10059 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10060 Temp byte_offset
= bld
.v_mul_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10061 unsigned tf_const_offset
= 0;
10063 if (ctx
->program
->chip_class
<= GFX8
) {
10064 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10065 if_context ic_rel_patch_id_is_zero
;
10066 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10067 bld
.reset(ctx
->block
);
10069 /* Store the dynamic HS control word. */
10070 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10071 bld
.mubuf(aco_opcode::buffer_store_dword
,
10072 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10073 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
10074 /* disable_wqm */ false, /* glc */ true);
10075 tf_const_offset
+= 4;
10077 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10078 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10079 bld
.reset(ctx
->block
);
10082 assert(stride
== 2 || stride
== 4 || stride
== 6);
10083 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10084 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
10086 /* Store to offchip for TES to read - only if TES reads them */
10087 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10088 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10089 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10091 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10092 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
10094 if (likely(inner_comps
)) {
10095 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10096 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
10100 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10101 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10104 static void emit_stream_output(isel_context
*ctx
,
10105 Temp
const *so_buffers
,
10106 Temp
const *so_write_offset
,
10107 const struct radv_stream_output
*output
)
10109 unsigned num_comps
= util_bitcount(output
->component_mask
);
10110 unsigned writemask
= (1 << num_comps
) - 1;
10111 unsigned loc
= output
->location
;
10112 unsigned buf
= output
->buffer
;
10114 assert(num_comps
&& num_comps
<= 4);
10115 if (!num_comps
|| num_comps
> 4)
10118 unsigned start
= ffs(output
->component_mask
) - 1;
10121 bool all_undef
= true;
10122 assert(ctx
->stage
== vertex_vs
|| ctx
->stage
== gs_copy_vs
);
10123 for (unsigned i
= 0; i
< num_comps
; i
++) {
10124 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10125 all_undef
= all_undef
&& !out
[i
].id();
10130 while (writemask
) {
10132 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10133 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10134 /* GFX6 doesn't support storing vec3, split it. */
10135 writemask
|= 1u << (start
+ 2);
10139 unsigned offset
= output
->offset
+ start
* 4;
10141 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10142 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10143 for (int i
= 0; i
< count
; ++i
)
10144 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10145 vec
->definitions
[0] = Definition(write_data
);
10146 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10151 opcode
= aco_opcode::buffer_store_dword
;
10154 opcode
= aco_opcode::buffer_store_dwordx2
;
10157 opcode
= aco_opcode::buffer_store_dwordx3
;
10160 opcode
= aco_opcode::buffer_store_dwordx4
;
10163 unreachable("Unsupported dword count.");
10166 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10167 store
->operands
[0] = Operand(so_buffers
[buf
]);
10168 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10169 store
->operands
[2] = Operand((uint32_t) 0);
10170 store
->operands
[3] = Operand(write_data
);
10171 if (offset
> 4095) {
10172 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10173 Builder
bld(ctx
->program
, ctx
->block
);
10174 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10176 store
->offset
= offset
;
10178 store
->offen
= true;
10180 store
->dlc
= false;
10182 store
->can_reorder
= true;
10183 ctx
->block
->instructions
.emplace_back(std::move(store
));
10187 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10189 Builder
bld(ctx
->program
, ctx
->block
);
10191 Temp so_buffers
[4];
10192 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10193 for (unsigned i
= 0; i
< 4; i
++) {
10194 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10198 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10199 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10202 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10203 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10205 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10207 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10210 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10212 bld
.reset(ctx
->block
);
10214 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10216 Temp so_write_offset
[4];
10218 for (unsigned i
= 0; i
< 4; i
++) {
10219 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10224 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10225 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10226 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10227 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10229 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10231 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10232 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10233 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10234 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10238 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10239 struct radv_stream_output
*output
=
10240 &ctx
->program
->info
->so
.outputs
[i
];
10241 if (stream
!= output
->stream
)
10244 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10247 begin_divergent_if_else(ctx
, &ic
);
10248 end_divergent_if(ctx
, &ic
);
10251 } /* end namespace */
10253 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10255 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10256 Builder
bld(ctx
->program
, ctx
->block
);
10257 constexpr unsigned hs_idx
= 1u;
10258 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10259 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10260 Operand((8u << 16) | (hs_idx
* 8u)));
10261 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10263 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10265 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10266 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10267 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10268 ls_has_nonzero_hs_threads
);
10269 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10270 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10271 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10272 ls_has_nonzero_hs_threads
);
10273 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10274 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10275 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10276 ls_has_nonzero_hs_threads
);
10278 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10279 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10280 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10283 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10285 /* Split all arguments except for the first (ring_offsets) and the last
10286 * (exec) so that the dead channels don't stay live throughout the program.
10288 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10289 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10290 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10291 startpgm
->definitions
[i
].regClass().size());
10296 void handle_bc_optimize(isel_context
*ctx
)
10298 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10299 Builder
bld(ctx
->program
, ctx
->block
);
10300 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10301 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10302 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10303 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10304 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10305 if (uses_center
&& uses_centroid
) {
10306 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10307 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10309 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10311 for (unsigned i
= 0; i
< 2; i
++) {
10312 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10313 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10314 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10315 persp_centroid
, persp_center
, sel
);
10317 ctx
->persp_centroid
= bld
.tmp(v2
);
10318 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10319 Operand(new_coord
[0]), Operand(new_coord
[1]));
10320 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10323 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10325 for (unsigned i
= 0; i
< 2; i
++) {
10326 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10327 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10328 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10329 linear_centroid
, linear_center
, sel
);
10331 ctx
->linear_centroid
= bld
.tmp(v2
);
10332 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10333 Operand(new_coord
[0]), Operand(new_coord
[1]));
10334 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10339 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10341 Program
*program
= ctx
->program
;
10343 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10345 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10346 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10347 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10348 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10349 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10351 program
->next_fp_mode
.must_flush_denorms32
=
10352 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10353 program
->next_fp_mode
.must_flush_denorms16_64
=
10354 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10355 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10357 program
->next_fp_mode
.care_about_round32
=
10358 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10360 program
->next_fp_mode
.care_about_round16_64
=
10361 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10362 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10364 /* default to preserving fp16 and fp64 denorms, since it's free */
10365 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10366 program
->next_fp_mode
.denorm16_64
= 0;
10368 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10370 /* preserving fp32 denorms is expensive, so only do it if asked */
10371 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10372 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10374 program
->next_fp_mode
.denorm32
= 0;
10376 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10377 program
->next_fp_mode
.round32
= fp_round_tz
;
10379 program
->next_fp_mode
.round32
= fp_round_ne
;
10381 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10382 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10384 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10386 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10389 void cleanup_cfg(Program
*program
)
10391 /* create linear_succs/logical_succs */
10392 for (Block
& BB
: program
->blocks
) {
10393 for (unsigned idx
: BB
.linear_preds
)
10394 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10395 for (unsigned idx
: BB
.logical_preds
)
10396 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10400 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10402 Builder
bld(ctx
->program
, ctx
->block
);
10404 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10405 Temp count
= i
== 0
10406 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10407 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10408 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10410 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10413 if (ctx
->program
->wave_size
== 64) {
10414 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10415 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10416 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10418 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10419 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10425 bool ngg_early_prim_export(isel_context
*ctx
)
10427 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10431 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10433 Builder
bld(ctx
->program
, ctx
->block
);
10435 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10436 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10438 /* Get the id of the current wave within the threadgroup (workgroup) */
10439 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10440 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10442 /* Execute the following code only on the first wave (wave id 0),
10443 * use the SCC def to tell if the wave id is zero or not.
10445 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10447 begin_uniform_if_then(ctx
, &ic
, cond
);
10448 begin_uniform_if_else(ctx
, &ic
);
10449 bld
.reset(ctx
->block
);
10451 /* Number of vertices output by VS/TES */
10452 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10453 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10454 /* Number of primitives output by VS/TES */
10455 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10456 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10458 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10459 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10460 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10462 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10463 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10465 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10466 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10468 end_uniform_if(ctx
, &ic
);
10471 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10473 Builder
bld(ctx
->program
, ctx
->block
);
10475 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10476 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10479 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10482 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10483 assert(vtxindex
[i
].id());
10486 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10490 /* The initial edge flag is always false in tess eval shaders. */
10491 if (ctx
->stage
== ngg_vertex_gs
) {
10492 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10493 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10497 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10502 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10504 Builder
bld(ctx
->program
, ctx
->block
);
10505 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10507 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10508 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10509 false /* compressed */, true/* done */, false /* valid mask */);
10512 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10514 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10515 * These must always come before VS exports.
10517 * It is recommended to do these as early as possible. They can be at the beginning when
10518 * there is no SW GS and the shader doesn't write edge flags.
10522 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10523 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10525 Builder
bld(ctx
->program
, ctx
->block
);
10526 constexpr unsigned max_vertices_per_primitive
= 3;
10527 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10529 if (ctx
->stage
== ngg_vertex_gs
) {
10530 /* TODO: optimize for points & lines */
10531 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10532 if (ctx
->shader
->info
.tess
.point_mode
)
10533 num_vertices_per_primitive
= 1;
10534 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10535 num_vertices_per_primitive
= 2;
10537 unreachable("Unsupported NGG shader stage");
10540 Temp vtxindex
[max_vertices_per_primitive
];
10541 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10542 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10543 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10544 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10545 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10546 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10547 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10548 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10550 /* Export primitive data to the index buffer. */
10551 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10553 /* Export primitive ID. */
10554 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10555 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10556 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10557 Temp provoking_vtx_index
= vtxindex
[0];
10558 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10560 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10563 begin_divergent_if_else(ctx
, &ic
);
10564 end_divergent_if(ctx
, &ic
);
10567 void ngg_emit_nogs_output(isel_context
*ctx
)
10569 /* Emits NGG GS output, for stages that don't have SW GS. */
10572 Builder
bld(ctx
->program
, ctx
->block
);
10573 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10575 /* NGG streamout is currently disabled by default. */
10576 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10578 if (late_prim_export
) {
10579 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10580 create_export_phis(ctx
);
10581 /* Do what we need to do in the GS threads. */
10582 ngg_emit_nogs_gsthreads(ctx
);
10584 /* What comes next should be executed on ES threads. */
10585 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10586 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10587 bld
.reset(ctx
->block
);
10590 /* Export VS outputs */
10591 ctx
->block
->kind
|= block_kind_export_end
;
10592 create_vs_exports(ctx
);
10594 /* Export primitive ID */
10595 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10598 if (ctx
->stage
== ngg_vertex_gs
) {
10599 /* Wait for GS threads to store primitive ID in LDS. */
10600 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10601 bld
.sopp(aco_opcode::s_barrier
);
10603 /* Calculate LDS address where the GS threads stored the primitive ID. */
10604 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10605 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10606 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10607 Temp wave_id_mul
= bld
.v_mul_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10608 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10609 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10611 /* Load primitive ID from LDS. */
10612 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10613 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10614 /* TES: Just use the patch ID as the primitive ID. */
10615 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10617 unreachable("unsupported NGG shader stage.");
10620 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10621 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10623 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10626 if (late_prim_export
) {
10627 begin_divergent_if_else(ctx
, &ic
);
10628 end_divergent_if(ctx
, &ic
);
10629 bld
.reset(ctx
->block
);
10633 void select_program(Program
*program
,
10634 unsigned shader_count
,
10635 struct nir_shader
*const *shaders
,
10636 ac_shader_config
* config
,
10637 struct radv_shader_args
*args
)
10639 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10640 if_context ic_merged_wave_info
;
10641 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10643 for (unsigned i
= 0; i
< shader_count
; i
++) {
10644 nir_shader
*nir
= shaders
[i
];
10645 init_context(&ctx
, nir
);
10647 setup_fp_mode(&ctx
, nir
);
10650 /* needs to be after init_context() for FS */
10651 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10652 append_logical_start(ctx
.block
);
10654 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10655 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10657 split_arguments(&ctx
, startpgm
);
10661 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10663 if (ngg_early_prim_export(&ctx
))
10664 ngg_emit_nogs_gsthreads(&ctx
);
10667 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10668 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10669 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10670 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10671 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10672 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10673 ctx
.stage
== tess_eval_geometry_gs
));
10675 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10676 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10677 if (check_merged_wave_info
) {
10678 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10679 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10683 Builder
bld(ctx
.program
, ctx
.block
);
10685 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10686 bld
.sopp(aco_opcode::s_barrier
);
10688 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10689 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10691 } else if (ctx
.stage
== geometry_gs
)
10692 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10694 if (ctx
.stage
== fragment_fs
)
10695 handle_bc_optimize(&ctx
);
10697 visit_cf_list(&ctx
, &func
->body
);
10699 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10700 emit_streamout(&ctx
, 0);
10702 if (ctx
.stage
& hw_vs
) {
10703 create_vs_exports(&ctx
);
10704 ctx
.block
->kind
|= block_kind_export_end
;
10705 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10706 ngg_emit_nogs_output(&ctx
);
10707 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10708 Builder
bld(ctx
.program
, ctx
.block
);
10709 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10710 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10711 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10712 write_tcs_tess_factors(&ctx
);
10715 if (ctx
.stage
== fragment_fs
) {
10716 create_fs_exports(&ctx
);
10717 ctx
.block
->kind
|= block_kind_export_end
;
10720 if (endif_merged_wave_info
) {
10721 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10722 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10725 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10726 ngg_emit_nogs_output(&ctx
);
10728 ralloc_free(ctx
.divergent_vals
);
10730 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10731 /* Outputs of the previous stage are inputs to the next stage */
10732 ctx
.inputs
= ctx
.outputs
;
10733 ctx
.outputs
= shader_io_state();
10737 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10739 append_logical_end(ctx
.block
);
10740 ctx
.block
->kind
|= block_kind_uniform
;
10741 Builder
bld(ctx
.program
, ctx
.block
);
10742 if (ctx
.program
->wb_smem_l1_on_end
)
10743 bld
.smem(aco_opcode::s_dcache_wb
, false);
10744 bld
.sopp(aco_opcode::s_endpgm
);
10746 cleanup_cfg(program
);
10749 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10750 ac_shader_config
* config
,
10751 struct radv_shader_args
*args
)
10753 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10755 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
10756 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
10757 program
->next_fp_mode
.must_flush_denorms32
= false;
10758 program
->next_fp_mode
.must_flush_denorms16_64
= false;
10759 program
->next_fp_mode
.care_about_round32
= false;
10760 program
->next_fp_mode
.care_about_round16_64
= false;
10761 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10762 program
->next_fp_mode
.denorm32
= 0;
10763 program
->next_fp_mode
.round32
= fp_round_ne
;
10764 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10765 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10767 add_startpgm(&ctx
);
10768 append_logical_start(ctx
.block
);
10770 Builder
bld(ctx
.program
, ctx
.block
);
10772 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10774 Operand
stream_id(0u);
10775 if (args
->shader_info
->so
.num_outputs
)
10776 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10777 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10779 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10781 std::stack
<Block
> endif_blocks
;
10783 for (unsigned stream
= 0; stream
< 4; stream
++) {
10784 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10787 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10788 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10791 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10793 unsigned BB_if_idx
= ctx
.block
->index
;
10794 Block BB_endif
= Block();
10795 if (!stream_id
.isConstant()) {
10797 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10798 append_logical_end(ctx
.block
);
10799 ctx
.block
->kind
|= block_kind_uniform
;
10800 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
10802 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10804 ctx
.block
= ctx
.program
->create_and_insert_block();
10805 add_edge(BB_if_idx
, ctx
.block
);
10806 bld
.reset(ctx
.block
);
10807 append_logical_start(ctx
.block
);
10810 unsigned offset
= 0;
10811 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10812 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10815 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10816 unsigned length
= util_last_bit(output_usage_mask
);
10817 for (unsigned j
= 0; j
< length
; ++j
) {
10818 if (!(output_usage_mask
& (1 << j
)))
10821 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10822 Temp voffset
= vtx_offset
;
10823 if (const_offset
>= 4096u) {
10824 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10825 const_offset
%= 4096u;
10828 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10829 mubuf
->definitions
[0] = bld
.def(v1
);
10830 mubuf
->operands
[0] = Operand(gsvs_ring
);
10831 mubuf
->operands
[1] = Operand(voffset
);
10832 mubuf
->operands
[2] = Operand(0u);
10833 mubuf
->offen
= true;
10834 mubuf
->offset
= const_offset
;
10837 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
10838 mubuf
->barrier
= barrier_none
;
10839 mubuf
->can_reorder
= true;
10841 ctx
.outputs
.mask
[i
] |= 1 << j
;
10842 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
10844 bld
.insert(std::move(mubuf
));
10850 if (args
->shader_info
->so
.num_outputs
) {
10851 emit_streamout(&ctx
, stream
);
10852 bld
.reset(ctx
.block
);
10856 create_vs_exports(&ctx
);
10857 ctx
.block
->kind
|= block_kind_export_end
;
10860 if (!stream_id
.isConstant()) {
10861 append_logical_end(ctx
.block
);
10863 /* branch from then block to endif block */
10864 bld
.branch(aco_opcode::p_branch
);
10865 add_edge(ctx
.block
->index
, &BB_endif
);
10866 ctx
.block
->kind
|= block_kind_uniform
;
10868 /* emit else block */
10869 ctx
.block
= ctx
.program
->create_and_insert_block();
10870 add_edge(BB_if_idx
, ctx
.block
);
10871 bld
.reset(ctx
.block
);
10872 append_logical_start(ctx
.block
);
10874 endif_blocks
.push(std::move(BB_endif
));
10878 while (!endif_blocks
.empty()) {
10879 Block BB_endif
= std::move(endif_blocks
.top());
10880 endif_blocks
.pop();
10882 Block
*BB_else
= ctx
.block
;
10884 append_logical_end(BB_else
);
10885 /* branch from else block to endif block */
10886 bld
.branch(aco_opcode::p_branch
);
10887 add_edge(BB_else
->index
, &BB_endif
);
10888 BB_else
->kind
|= block_kind_uniform
;
10890 /** emit endif merge block */
10891 ctx
.block
= program
->insert_block(std::move(BB_endif
));
10892 bld
.reset(ctx
.block
);
10893 append_logical_start(ctx
.block
);
10896 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10898 append_logical_end(ctx
.block
);
10899 ctx
.block
->kind
|= block_kind_uniform
;
10900 bld
.sopp(aco_opcode::s_endpgm
);
10902 cleanup_cfg(program
);