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3 * Copyright © 2018 Google
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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
140 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
145 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
147 Builder
bld(ctx
->program
, ctx
->block
);
150 dst
= bld
.tmp(src
.regClass());
152 assert(src
.size() == dst
.size());
154 if (ctx
->stage
!= fragment_fs
) {
158 bld
.copy(Definition(dst
), src
);
162 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
163 ctx
->program
->needs_wqm
|= program_needs_wqm
;
167 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
169 if (index
.regClass() == s1
)
170 return bld
.readlane(bld
.def(s1
), data
, index
);
172 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
174 /* Currently not implemented on GFX6-7 */
175 assert(ctx
->options
->chip_class
>= GFX8
);
177 if (ctx
->options
->chip_class
<= GFX9
|| ctx
->program
->wave_size
== 32) {
178 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
181 /* GFX10, wave64 mode:
182 * The bpermute instruction is limited to half-wave operation, which means that it can't
183 * properly support subgroup shuffle like older generations (or wave32 mode), so we
186 if (!ctx
->has_gfx10_wave64_bpermute
) {
187 ctx
->has_gfx10_wave64_bpermute
= true;
188 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
189 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
192 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
193 Temp lane_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), lane_id
);
194 Temp index_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), index
);
195 Temp cmp
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
, vcc
), lane_is_hi
, index_is_hi
);
197 return bld
.reduction(aco_opcode::p_wave64_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
),
198 bld
.vcc(cmp
), Operand(v2
.as_linear()), index_x4
, data
, gfx10_wave64_bpermute
);
201 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
203 if (val
.type() == RegType::sgpr
) {
204 Builder
bld(ctx
->program
, ctx
->block
);
205 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
207 assert(val
.type() == RegType::vgpr
);
211 //assumes a != 0xffffffff
212 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
215 Builder
bld(ctx
->program
, ctx
->block
);
217 if (util_is_power_of_two_or_zero(b
)) {
218 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
222 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
224 assert(info
.multiplier
<= 0xffffffff);
226 bool pre_shift
= info
.pre_shift
!= 0;
227 bool increment
= info
.increment
!= 0;
228 bool multiply
= true;
229 bool post_shift
= info
.post_shift
!= 0;
231 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
232 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
236 Temp pre_shift_dst
= a
;
238 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
239 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
242 Temp increment_dst
= pre_shift_dst
;
244 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
245 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
248 Temp multiply_dst
= increment_dst
;
250 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
251 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
252 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
256 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
260 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
262 Builder
bld(ctx
->program
, ctx
->block
);
263 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
267 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
269 /* no need to extract the whole vector */
270 if (src
.regClass() == dst_rc
) {
275 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
276 Builder
bld(ctx
->program
, ctx
->block
);
277 auto it
= ctx
->allocated_vec
.find(src
.id());
278 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
279 if (it
->second
[idx
].regClass() == dst_rc
) {
280 return it
->second
[idx
];
282 assert(!dst_rc
.is_subdword());
283 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
284 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
288 if (dst_rc
.is_subdword())
289 src
= as_vgpr(ctx
, src
);
291 if (src
.bytes() == dst_rc
.bytes()) {
293 return bld
.copy(bld
.def(dst_rc
), src
);
295 Temp dst
= bld
.tmp(dst_rc
);
296 emit_extract_vector(ctx
, src
, idx
, dst
);
301 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
303 if (num_components
== 1)
305 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
307 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
308 split
->operands
[0] = Operand(vec_src
);
309 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
311 if (num_components
> vec_src
.size()) {
312 if (vec_src
.type() == RegType::sgpr
)
315 /* sub-dword split */
316 assert(vec_src
.type() == RegType::vgpr
);
317 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
319 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
321 for (unsigned i
= 0; i
< num_components
; i
++) {
322 elems
[i
] = {ctx
->program
->allocateId(), rc
};
323 split
->definitions
[i
] = Definition(elems
[i
]);
325 ctx
->block
->instructions
.emplace_back(std::move(split
));
326 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
329 /* This vector expansion uses a mask to determine which elements in the new vector
330 * come from the original vector. The other elements are undefined. */
331 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
333 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
338 Builder
bld(ctx
->program
, ctx
->block
);
339 if (num_components
== 1) {
340 if (dst
.type() == RegType::sgpr
)
341 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
343 bld
.copy(Definition(dst
), vec_src
);
347 unsigned component_size
= dst
.size() / num_components
;
348 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
350 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
351 vec
->definitions
[0] = Definition(dst
);
353 for (unsigned i
= 0; i
< num_components
; i
++) {
354 if (mask
& (1 << i
)) {
355 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
356 if (dst
.type() == RegType::sgpr
)
357 src
= bld
.as_uniform(src
);
358 vec
->operands
[i
] = Operand(src
);
360 vec
->operands
[i
] = Operand(0u);
362 elems
[i
] = vec
->operands
[i
].getTemp();
364 ctx
->block
->instructions
.emplace_back(std::move(vec
));
365 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
368 /* adjust misaligned small bit size loads */
369 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
371 Builder
bld(ctx
->program
, ctx
->block
);
373 Temp select
= Temp();
374 if (offset
.isConstant()) {
375 assert(offset
.constantValue() && offset
.constantValue() < 4);
376 shift
= Operand(offset
.constantValue() * 8);
378 /* bit_offset = 8 * (offset & 0x3) */
379 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
380 select
= bld
.tmp(s1
);
381 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
384 if (vec
.size() == 1) {
385 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
386 } else if (vec
.size() == 2) {
387 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
388 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
390 emit_split_vector(ctx
, dst
, 2);
392 emit_extract_vector(ctx
, tmp
, 0, dst
);
393 } else if (vec
.size() == 4) {
394 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
395 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
396 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
397 if (select
!= Temp())
398 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), select
);
399 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
400 Temp mid
= bld
.tmp(s1
);
401 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
402 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
403 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
404 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
405 emit_split_vector(ctx
, dst
, 2);
409 /* this function trims subdword vectors:
410 * if dst is vgpr - split the src and create a shrunk version according to the mask.
411 * if dst is sgpr - split the src, but move the original to sgpr. */
412 void trim_subdword_vector(isel_context
*ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
414 assert(vec_src
.type() == RegType::vgpr
);
415 emit_split_vector(ctx
, vec_src
, num_components
);
417 Builder
bld(ctx
->program
, ctx
->block
);
418 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
419 unsigned component_size
= vec_src
.bytes() / num_components
;
420 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
423 for (unsigned i
= 0; i
< num_components
; i
++) {
425 elems
[k
++] = emit_extract_vector(ctx
, vec_src
, i
, rc
);
428 if (dst
.type() == RegType::vgpr
) {
429 assert(dst
.bytes() == k
* component_size
);
430 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, k
, 1)};
431 for (unsigned i
= 0; i
< k
; i
++)
432 vec
->operands
[i
] = Operand(elems
[i
]);
433 vec
->definitions
[0] = Definition(dst
);
434 bld
.insert(std::move(vec
));
436 // TODO: alignbyte if mask doesn't start with 1?
438 assert(dst
.size() == vec_src
.size());
439 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
441 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
444 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
446 Builder
bld(ctx
->program
, ctx
->block
);
448 dst
= bld
.tmp(bld
.lm
);
450 assert(val
.regClass() == s1
);
451 assert(dst
.regClass() == bld
.lm
);
453 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
456 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
458 Builder
bld(ctx
->program
, ctx
->block
);
462 assert(val
.regClass() == bld
.lm
);
463 assert(dst
.regClass() == s1
);
465 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
466 Temp tmp
= bld
.tmp(s1
);
467 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
468 return emit_wqm(ctx
, tmp
, dst
);
471 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
473 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
474 return get_ssa_temp(ctx
, src
.src
.ssa
);
476 if (src
.src
.ssa
->num_components
== size
) {
477 bool identity_swizzle
= true;
478 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
479 if (src
.swizzle
[i
] != i
)
480 identity_swizzle
= false;
482 if (identity_swizzle
)
483 return get_ssa_temp(ctx
, src
.src
.ssa
);
486 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
487 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
488 assert(elem_size
> 0);
489 assert(vec
.bytes() % elem_size
== 0);
491 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
492 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
494 unsigned swizzle
= src
.swizzle
[0];
495 if (vec
.size() > 1) {
496 assert(src
.src
.ssa
->bit_size
== 16);
497 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
498 swizzle
= swizzle
& 1;
503 Temp dst
{ctx
->program
->allocateId(), s1
};
504 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 1)};
505 bfe
->operands
[0] = Operand(vec
);
506 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
507 bfe
->definitions
[0] = Definition(dst
);
508 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
512 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
514 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
517 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
518 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
519 for (unsigned i
= 0; i
< size
; ++i
) {
520 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
521 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
523 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
524 vec_instr
->definitions
[0] = Definition(dst
);
525 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
526 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
531 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
535 Builder
bld(ctx
->program
, ctx
->block
);
536 if (ptr
.type() == RegType::vgpr
)
537 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
538 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
539 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
542 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
544 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
545 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
546 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
547 sop2
->definitions
[0] = Definition(dst
);
549 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
550 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
553 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
554 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
556 Builder
bld(ctx
->program
, ctx
->block
);
557 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
558 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
559 if (src1
.type() == RegType::sgpr
) {
560 if (commutative
&& src0
.type() == RegType::vgpr
) {
564 } else if (src0
.type() == RegType::vgpr
&&
565 op
!= aco_opcode::v_madmk_f32
&&
566 op
!= aco_opcode::v_madak_f32
&&
567 op
!= aco_opcode::v_madmk_f16
&&
568 op
!= aco_opcode::v_madak_f16
) {
569 /* If the instruction is not commutative, we emit a VOP3A instruction */
570 bld
.vop2_e64(op
, Definition(dst
), src0
, src1
);
573 src1
= bld
.copy(bld
.def(RegType::vgpr
, src1
.size()), src1
); //TODO: as_vgpr
577 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
578 assert(dst
.size() == 1);
579 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
580 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
582 bld
.vop2(op
, Definition(dst
), src0
, src1
);
586 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
587 bool flush_denorms
= false)
589 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
590 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
591 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
593 /* ensure that the instruction has at most 1 sgpr operand
594 * The optimizer will inline constants for us */
595 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
596 src0
= as_vgpr(ctx
, src0
);
597 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
598 src1
= as_vgpr(ctx
, src1
);
599 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
600 src2
= as_vgpr(ctx
, src2
);
602 Builder
bld(ctx
->program
, ctx
->block
);
603 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
604 assert(dst
.size() == 1);
605 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
606 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
608 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
612 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
614 Builder
bld(ctx
->program
, ctx
->block
);
615 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
618 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
620 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
621 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
622 assert(src0
.size() == src1
.size());
624 aco_ptr
<Instruction
> vopc
;
625 if (src1
.type() == RegType::sgpr
) {
626 if (src0
.type() == RegType::vgpr
) {
627 /* to swap the operands, we might also have to change the opcode */
629 case aco_opcode::v_cmp_lt_f32
:
630 op
= aco_opcode::v_cmp_gt_f32
;
632 case aco_opcode::v_cmp_ge_f32
:
633 op
= aco_opcode::v_cmp_le_f32
;
635 case aco_opcode::v_cmp_lt_i32
:
636 op
= aco_opcode::v_cmp_gt_i32
;
638 case aco_opcode::v_cmp_ge_i32
:
639 op
= aco_opcode::v_cmp_le_i32
;
641 case aco_opcode::v_cmp_lt_u32
:
642 op
= aco_opcode::v_cmp_gt_u32
;
644 case aco_opcode::v_cmp_ge_u32
:
645 op
= aco_opcode::v_cmp_le_u32
;
647 case aco_opcode::v_cmp_lt_f64
:
648 op
= aco_opcode::v_cmp_gt_f64
;
650 case aco_opcode::v_cmp_ge_f64
:
651 op
= aco_opcode::v_cmp_le_f64
;
653 case aco_opcode::v_cmp_lt_i64
:
654 op
= aco_opcode::v_cmp_gt_i64
;
656 case aco_opcode::v_cmp_ge_i64
:
657 op
= aco_opcode::v_cmp_le_i64
;
659 case aco_opcode::v_cmp_lt_u64
:
660 op
= aco_opcode::v_cmp_gt_u64
;
662 case aco_opcode::v_cmp_ge_u64
:
663 op
= aco_opcode::v_cmp_le_u64
;
665 default: /* eq and ne are commutative */
672 src1
= as_vgpr(ctx
, src1
);
676 Builder
bld(ctx
->program
, ctx
->block
);
677 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
680 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
682 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
683 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
684 Builder
bld(ctx
->program
, ctx
->block
);
686 assert(dst
.regClass() == bld
.lm
);
687 assert(src0
.type() == RegType::sgpr
);
688 assert(src1
.type() == RegType::sgpr
);
689 assert(src0
.regClass() == src1
.regClass());
691 /* Emit the SALU comparison instruction */
692 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
693 /* Turn the result into a per-lane bool */
694 bool_to_vector_condition(ctx
, cmp
, dst
);
697 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
698 aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
700 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: s32_op
;
701 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: v32_op
;
702 bool divergent_vals
= ctx
->divergent_vals
[instr
->dest
.dest
.ssa
.index
];
703 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
705 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
706 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
707 aco_opcode op
= use_valu
? v_op
: s_op
;
708 assert(op
!= aco_opcode::num_opcodes
);
709 assert(dst
.regClass() == ctx
->program
->lane_mask
);
712 emit_vopc_instruction(ctx
, instr
, op
, dst
);
714 emit_sopc_instruction(ctx
, instr
, op
, dst
);
717 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
719 Builder
bld(ctx
->program
, ctx
->block
);
720 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
721 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
723 assert(dst
.regClass() == bld
.lm
);
724 assert(src0
.regClass() == bld
.lm
);
725 assert(src1
.regClass() == bld
.lm
);
727 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
730 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
732 Builder
bld(ctx
->program
, ctx
->block
);
733 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
734 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
735 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
737 assert(cond
.regClass() == bld
.lm
);
739 if (dst
.type() == RegType::vgpr
) {
740 aco_ptr
<Instruction
> bcsel
;
741 if (dst
.size() == 1) {
742 then
= as_vgpr(ctx
, then
);
743 els
= as_vgpr(ctx
, els
);
745 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
746 } else if (dst
.size() == 2) {
747 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
748 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
749 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
750 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
752 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
753 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
755 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
757 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
758 nir_print_instr(&instr
->instr
, stderr
);
759 fprintf(stderr
, "\n");
764 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
765 assert(dst
.regClass() == bld
.lm
);
766 assert(then
.regClass() == bld
.lm
);
767 assert(els
.regClass() == bld
.lm
);
770 if (!ctx
->divergent_vals
[instr
->src
[0].src
.ssa
->index
]) { /* uniform condition and values in sgpr */
771 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
772 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
773 assert(dst
.size() == then
.size());
774 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
775 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
777 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
778 nir_print_instr(&instr
->instr
, stderr
);
779 fprintf(stderr
, "\n");
784 /* divergent boolean bcsel
785 * this implements bcsel on bools: dst = s0 ? s1 : s2
786 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
787 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
789 if (cond
.id() != then
.id())
790 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
792 if (cond
.id() == els
.id())
793 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
795 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
796 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
799 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
800 aco_opcode op
, uint32_t undo
)
802 /* multiply by 16777216 to handle denormals */
803 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
804 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
805 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
806 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
807 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
809 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
811 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
814 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
816 if (ctx
->block
->fp_mode
.denorm32
== 0) {
817 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
821 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
824 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
826 if (ctx
->block
->fp_mode
.denorm32
== 0) {
827 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
831 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
834 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
836 if (ctx
->block
->fp_mode
.denorm32
== 0) {
837 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
841 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
844 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
846 if (ctx
->block
->fp_mode
.denorm32
== 0) {
847 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
851 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
854 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
856 if (ctx
->options
->chip_class
>= GFX7
)
857 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
859 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
860 /* TODO: create more efficient code! */
861 if (val
.type() == RegType::sgpr
)
862 val
= as_vgpr(ctx
, val
);
864 /* Split the input value. */
865 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
866 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
868 /* Extract the exponent and compute the unbiased value. */
869 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, bld
.def(v1
), val
);
871 /* Extract the fractional part. */
872 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
873 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
875 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
876 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
878 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
879 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
880 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
881 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
882 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
884 /* Get the sign bit. */
885 Temp sign
= bld
.vop2(aco_opcode::v_ashr_i32
, bld
.def(v1
), Operand(31u), val_hi
);
887 /* Decide the operation to apply depending on the unbiased exponent. */
888 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
889 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
890 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
891 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
892 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
893 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
895 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
898 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
900 if (ctx
->options
->chip_class
>= GFX7
)
901 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
903 /* GFX6 doesn't support V_FLOOR_F64, lower it. */
904 Temp src0
= as_vgpr(ctx
, val
);
906 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
907 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
909 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
910 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
911 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
913 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
914 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
915 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
916 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
918 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
919 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
921 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
923 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
924 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
926 return add
->definitions
[0].getTemp();
929 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
931 if (!instr
->dest
.dest
.is_ssa
) {
932 fprintf(stderr
, "nir alu dst not in ssa: ");
933 nir_print_instr(&instr
->instr
, stderr
);
934 fprintf(stderr
, "\n");
937 Builder
bld(ctx
->program
, ctx
->block
);
938 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
943 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
944 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
945 for (unsigned i
= 0; i
< num
; ++i
)
946 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
948 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
949 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
950 for (unsigned i
= 0; i
< num
; ++i
)
951 vec
->operands
[i
] = Operand
{elems
[i
]};
952 vec
->definitions
[0] = Definition(dst
);
953 ctx
->block
->instructions
.emplace_back(std::move(vec
));
954 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
956 // TODO: that is a bit suboptimal..
957 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
958 for (unsigned i
= 0; i
< num
- 1; ++i
)
959 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
960 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
961 for (unsigned i
= 0; i
< num
; ++i
) {
962 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
964 elems
[bit
/ 32] = elems
[i
];
966 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
967 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
968 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
972 bld
.copy(Definition(dst
), elems
[0]);
974 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
979 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
980 aco_ptr
<Instruction
> mov
;
981 if (dst
.type() == RegType::sgpr
) {
982 if (src
.type() == RegType::vgpr
)
983 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
984 else if (src
.regClass() == s1
)
985 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
986 else if (src
.regClass() == s2
)
987 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
989 unreachable("wrong src register class for nir_op_imov");
990 } else if (dst
.regClass() == v1
) {
991 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
992 } else if (dst
.regClass() == v2
) {
993 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
995 nir_print_instr(&instr
->instr
, stderr
);
996 unreachable("Should have been lowered to scalar.");
1001 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1002 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1003 assert(src
.regClass() == bld
.lm
);
1004 assert(dst
.regClass() == bld
.lm
);
1005 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1006 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1007 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1008 } else if (dst
.regClass() == v1
) {
1009 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1010 } else if (dst
.type() == RegType::sgpr
) {
1011 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1012 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1014 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1015 nir_print_instr(&instr
->instr
, stderr
);
1016 fprintf(stderr
, "\n");
1021 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1022 if (dst
.regClass() == v1
) {
1023 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1024 } else if (dst
.regClass() == s1
) {
1025 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1026 } else if (dst
.size() == 2) {
1027 Temp src0
= bld
.tmp(dst
.type(), 1);
1028 Temp src1
= bld
.tmp(dst
.type(), 1);
1029 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1031 if (dst
.regClass() == s2
) {
1032 Temp carry
= bld
.tmp(s1
);
1033 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1034 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1035 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1037 Temp lower
= bld
.tmp(v1
);
1038 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1039 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1040 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1043 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1044 nir_print_instr(&instr
->instr
, stderr
);
1045 fprintf(stderr
, "\n");
1050 if (dst
.regClass() == s1
) {
1051 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1052 } else if (dst
.regClass() == v1
) {
1053 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1054 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1056 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1057 nir_print_instr(&instr
->instr
, stderr
);
1058 fprintf(stderr
, "\n");
1062 case nir_op_isign
: {
1063 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1064 if (dst
.regClass() == s1
) {
1065 Temp tmp
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
1066 Temp gtz
= bld
.sopc(aco_opcode::s_cmp_gt_i32
, bld
.def(s1
, scc
), src
, Operand(0u));
1067 bld
.sop2(aco_opcode::s_add_i32
, Definition(dst
), bld
.def(s1
, scc
), gtz
, tmp
);
1068 } else if (dst
.regClass() == s2
) {
1069 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1071 if (ctx
->program
->chip_class
>= GFX8
)
1072 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1074 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1075 /* SCC gets zero-extended to 64 bit */
1076 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1077 } else if (dst
.regClass() == v1
) {
1078 Temp tmp
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
1079 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1080 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(1u), tmp
, gtz
);
1081 } else if (dst
.regClass() == v2
) {
1082 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1083 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1084 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1085 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1086 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1087 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1089 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1090 nir_print_instr(&instr
->instr
, stderr
);
1091 fprintf(stderr
, "\n");
1096 if (dst
.regClass() == v1
) {
1097 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1098 } else if (dst
.regClass() == s1
) {
1099 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1101 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1102 nir_print_instr(&instr
->instr
, stderr
);
1103 fprintf(stderr
, "\n");
1108 if (dst
.regClass() == v1
) {
1109 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1110 } else if (dst
.regClass() == s1
) {
1111 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1113 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1114 nir_print_instr(&instr
->instr
, stderr
);
1115 fprintf(stderr
, "\n");
1120 if (dst
.regClass() == v1
) {
1121 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1122 } else if (dst
.regClass() == s1
) {
1123 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1125 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1126 nir_print_instr(&instr
->instr
, stderr
);
1127 fprintf(stderr
, "\n");
1132 if (dst
.regClass() == v1
) {
1133 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1134 } else if (dst
.regClass() == s1
) {
1135 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1137 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1138 nir_print_instr(&instr
->instr
, stderr
);
1139 fprintf(stderr
, "\n");
1144 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1145 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1146 } else if (dst
.regClass() == v1
) {
1147 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1148 } else if (dst
.regClass() == s1
) {
1149 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1150 } else if (dst
.regClass() == s2
) {
1151 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1153 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1154 nir_print_instr(&instr
->instr
, stderr
);
1155 fprintf(stderr
, "\n");
1160 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1161 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1162 } else if (dst
.regClass() == v1
) {
1163 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1164 } else if (dst
.regClass() == s1
) {
1165 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1166 } else if (dst
.regClass() == s2
) {
1167 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1169 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1170 nir_print_instr(&instr
->instr
, stderr
);
1171 fprintf(stderr
, "\n");
1176 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1177 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1178 } else if (dst
.regClass() == v1
) {
1179 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1180 } else if (dst
.regClass() == s1
) {
1181 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1182 } else if (dst
.regClass() == s2
) {
1183 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1185 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1186 nir_print_instr(&instr
->instr
, stderr
);
1187 fprintf(stderr
, "\n");
1192 if (dst
.regClass() == v1
) {
1193 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1194 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1195 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1196 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1197 } else if (dst
.regClass() == v2
) {
1198 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1199 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1200 } else if (dst
.regClass() == s2
) {
1201 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1202 } else if (dst
.regClass() == s1
) {
1203 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1205 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1206 nir_print_instr(&instr
->instr
, stderr
);
1207 fprintf(stderr
, "\n");
1212 if (dst
.regClass() == v1
) {
1213 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1214 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1215 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1216 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1217 } else if (dst
.regClass() == v2
) {
1218 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1219 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1220 } else if (dst
.regClass() == s1
) {
1221 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1222 } else if (dst
.regClass() == s2
) {
1223 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1225 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1226 nir_print_instr(&instr
->instr
, stderr
);
1227 fprintf(stderr
, "\n");
1232 if (dst
.regClass() == v1
) {
1233 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1234 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1235 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1236 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1237 } else if (dst
.regClass() == v2
) {
1238 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1239 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1240 } else if (dst
.regClass() == s1
) {
1241 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1242 } else if (dst
.regClass() == s2
) {
1243 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1245 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1246 nir_print_instr(&instr
->instr
, stderr
);
1247 fprintf(stderr
, "\n");
1251 case nir_op_find_lsb
: {
1252 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1253 if (src
.regClass() == s1
) {
1254 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1255 } else if (src
.regClass() == v1
) {
1256 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1257 } else if (src
.regClass() == s2
) {
1258 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1260 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1261 nir_print_instr(&instr
->instr
, stderr
);
1262 fprintf(stderr
, "\n");
1266 case nir_op_ufind_msb
:
1267 case nir_op_ifind_msb
: {
1268 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1269 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1270 aco_opcode op
= src
.regClass() == s2
?
1271 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1272 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1273 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1275 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1276 Operand(src
.size() * 32u - 1u), msb_rev
);
1277 Temp msb
= sub
.def(0).getTemp();
1278 Temp carry
= sub
.def(1).getTemp();
1280 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1281 } else if (src
.regClass() == v1
) {
1282 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1283 Temp msb_rev
= bld
.tmp(v1
);
1284 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1285 Temp msb
= bld
.tmp(v1
);
1286 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1287 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1289 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1290 nir_print_instr(&instr
->instr
, stderr
);
1291 fprintf(stderr
, "\n");
1295 case nir_op_bitfield_reverse
: {
1296 if (dst
.regClass() == s1
) {
1297 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1298 } else if (dst
.regClass() == v1
) {
1299 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1301 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1302 nir_print_instr(&instr
->instr
, stderr
);
1303 fprintf(stderr
, "\n");
1308 if (dst
.regClass() == s1
) {
1309 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1313 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1314 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1315 if (dst
.regClass() == v1
) {
1316 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1320 assert(src0
.size() == 2 && src1
.size() == 2);
1321 Temp src00
= bld
.tmp(src0
.type(), 1);
1322 Temp src01
= bld
.tmp(dst
.type(), 1);
1323 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1324 Temp src10
= bld
.tmp(src1
.type(), 1);
1325 Temp src11
= bld
.tmp(dst
.type(), 1);
1326 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1328 if (dst
.regClass() == s2
) {
1329 Temp carry
= bld
.tmp(s1
);
1330 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1331 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1332 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1333 } else if (dst
.regClass() == v2
) {
1334 Temp dst0
= bld
.tmp(v1
);
1335 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1336 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1337 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1339 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1340 nir_print_instr(&instr
->instr
, stderr
);
1341 fprintf(stderr
, "\n");
1345 case nir_op_uadd_sat
: {
1346 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1347 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1348 if (dst
.regClass() == s1
) {
1349 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1350 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1352 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1353 } else if (dst
.regClass() == v1
) {
1354 if (ctx
->options
->chip_class
>= GFX9
) {
1355 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1356 add
->operands
[0] = Operand(src0
);
1357 add
->operands
[1] = Operand(src1
);
1358 add
->definitions
[0] = Definition(dst
);
1360 ctx
->block
->instructions
.emplace_back(std::move(add
));
1362 if (src1
.regClass() != v1
)
1363 std::swap(src0
, src1
);
1364 assert(src1
.regClass() == v1
);
1365 Temp tmp
= bld
.tmp(v1
);
1366 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1367 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1370 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1371 nir_print_instr(&instr
->instr
, stderr
);
1372 fprintf(stderr
, "\n");
1376 case nir_op_uadd_carry
: {
1377 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1378 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1379 if (dst
.regClass() == s1
) {
1380 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1383 if (dst
.regClass() == v1
) {
1384 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1385 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1389 Temp src00
= bld
.tmp(src0
.type(), 1);
1390 Temp src01
= bld
.tmp(dst
.type(), 1);
1391 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1392 Temp src10
= bld
.tmp(src1
.type(), 1);
1393 Temp src11
= bld
.tmp(dst
.type(), 1);
1394 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1395 if (dst
.regClass() == s2
) {
1396 Temp carry
= bld
.tmp(s1
);
1397 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1398 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1399 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1400 } else if (dst
.regClass() == v2
) {
1401 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1402 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1403 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1404 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1406 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1407 nir_print_instr(&instr
->instr
, stderr
);
1408 fprintf(stderr
, "\n");
1413 if (dst
.regClass() == s1
) {
1414 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1418 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1419 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1420 if (dst
.regClass() == v1
) {
1421 bld
.vsub32(Definition(dst
), src0
, src1
);
1425 Temp src00
= bld
.tmp(src0
.type(), 1);
1426 Temp src01
= bld
.tmp(dst
.type(), 1);
1427 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1428 Temp src10
= bld
.tmp(src1
.type(), 1);
1429 Temp src11
= bld
.tmp(dst
.type(), 1);
1430 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1431 if (dst
.regClass() == s2
) {
1432 Temp carry
= bld
.tmp(s1
);
1433 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1434 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1435 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1436 } else if (dst
.regClass() == v2
) {
1437 Temp lower
= bld
.tmp(v1
);
1438 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1439 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1440 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1442 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1443 nir_print_instr(&instr
->instr
, stderr
);
1444 fprintf(stderr
, "\n");
1448 case nir_op_usub_borrow
: {
1449 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1450 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1451 if (dst
.regClass() == s1
) {
1452 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1454 } else if (dst
.regClass() == v1
) {
1455 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1456 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1460 Temp src00
= bld
.tmp(src0
.type(), 1);
1461 Temp src01
= bld
.tmp(dst
.type(), 1);
1462 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1463 Temp src10
= bld
.tmp(src1
.type(), 1);
1464 Temp src11
= bld
.tmp(dst
.type(), 1);
1465 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1466 if (dst
.regClass() == s2
) {
1467 Temp borrow
= bld
.tmp(s1
);
1468 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1469 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1470 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1471 } else if (dst
.regClass() == v2
) {
1472 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1473 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1474 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1475 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1477 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1478 nir_print_instr(&instr
->instr
, stderr
);
1479 fprintf(stderr
, "\n");
1484 if (dst
.regClass() == v1
) {
1485 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1486 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1487 } else if (dst
.regClass() == s1
) {
1488 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1490 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1491 nir_print_instr(&instr
->instr
, stderr
);
1492 fprintf(stderr
, "\n");
1496 case nir_op_umul_high
: {
1497 if (dst
.regClass() == v1
) {
1498 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1499 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1500 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1501 } else if (dst
.regClass() == s1
) {
1502 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1503 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1504 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1506 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1507 nir_print_instr(&instr
->instr
, stderr
);
1508 fprintf(stderr
, "\n");
1512 case nir_op_imul_high
: {
1513 if (dst
.regClass() == v1
) {
1514 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1515 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1516 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1517 } else if (dst
.regClass() == s1
) {
1518 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1519 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1520 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1522 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1523 nir_print_instr(&instr
->instr
, stderr
);
1524 fprintf(stderr
, "\n");
1529 if (dst
.size() == 1) {
1530 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1531 } else if (dst
.size() == 2) {
1532 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]),
1533 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1535 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1536 nir_print_instr(&instr
->instr
, stderr
);
1537 fprintf(stderr
, "\n");
1542 if (dst
.size() == 1) {
1543 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1544 } else if (dst
.size() == 2) {
1545 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]),
1546 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1548 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1549 nir_print_instr(&instr
->instr
, stderr
);
1550 fprintf(stderr
, "\n");
1555 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1556 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1557 if (dst
.size() == 1) {
1558 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1559 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1561 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1562 } else if (dst
.size() == 2) {
1563 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1564 get_alu_src(ctx
, instr
->src
[0]),
1565 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1566 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1569 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1570 nir_print_instr(&instr
->instr
, stderr
);
1571 fprintf(stderr
, "\n");
1576 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1577 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1578 if (dst
.regClass() == v2b
) {
1579 // TODO: check fp_mode.must_flush_denorms16_64
1580 Temp tmp
= bld
.tmp(v1
);
1581 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, tmp
, true);
1582 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1583 } else if (dst
.regClass() == v1
) {
1584 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1585 } else if (dst
.regClass() == v2
) {
1586 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1587 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1588 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1590 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1593 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1594 nir_print_instr(&instr
->instr
, stderr
);
1595 fprintf(stderr
, "\n");
1600 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1601 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1602 if (dst
.regClass() == v2b
) {
1603 // TODO: check fp_mode.must_flush_denorms16_64
1604 Temp tmp
= bld
.tmp(v1
);
1605 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, tmp
, true);
1606 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1607 } else if (dst
.regClass() == v1
) {
1608 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1609 } else if (dst
.regClass() == v2
) {
1610 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1611 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1612 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1614 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1617 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1618 nir_print_instr(&instr
->instr
, stderr
);
1619 fprintf(stderr
, "\n");
1623 case nir_op_fmax3
: {
1624 if (dst
.size() == 1) {
1625 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1627 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1628 nir_print_instr(&instr
->instr
, stderr
);
1629 fprintf(stderr
, "\n");
1633 case nir_op_fmin3
: {
1634 if (dst
.size() == 1) {
1635 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1637 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1638 nir_print_instr(&instr
->instr
, stderr
);
1639 fprintf(stderr
, "\n");
1643 case nir_op_fmed3
: {
1644 if (dst
.size() == 1) {
1645 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1647 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1648 nir_print_instr(&instr
->instr
, stderr
);
1649 fprintf(stderr
, "\n");
1653 case nir_op_umax3
: {
1654 if (dst
.size() == 1) {
1655 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1657 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1658 nir_print_instr(&instr
->instr
, stderr
);
1659 fprintf(stderr
, "\n");
1663 case nir_op_umin3
: {
1664 if (dst
.size() == 1) {
1665 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1667 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1668 nir_print_instr(&instr
->instr
, stderr
);
1669 fprintf(stderr
, "\n");
1673 case nir_op_umed3
: {
1674 if (dst
.size() == 1) {
1675 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1677 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1678 nir_print_instr(&instr
->instr
, stderr
);
1679 fprintf(stderr
, "\n");
1683 case nir_op_imax3
: {
1684 if (dst
.size() == 1) {
1685 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1687 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1688 nir_print_instr(&instr
->instr
, stderr
);
1689 fprintf(stderr
, "\n");
1693 case nir_op_imin3
: {
1694 if (dst
.size() == 1) {
1695 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1697 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1698 nir_print_instr(&instr
->instr
, stderr
);
1699 fprintf(stderr
, "\n");
1703 case nir_op_imed3
: {
1704 if (dst
.size() == 1) {
1705 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1707 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1708 nir_print_instr(&instr
->instr
, stderr
);
1709 fprintf(stderr
, "\n");
1713 case nir_op_cube_face_coord
: {
1714 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1715 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1716 emit_extract_vector(ctx
, in
, 1, v1
),
1717 emit_extract_vector(ctx
, in
, 2, v1
) };
1718 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1719 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1720 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1721 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1722 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1723 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1724 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1727 case nir_op_cube_face_index
: {
1728 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1729 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1730 emit_extract_vector(ctx
, in
, 1, v1
),
1731 emit_extract_vector(ctx
, in
, 2, v1
) };
1732 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1735 case nir_op_bcsel
: {
1736 emit_bcsel(ctx
, instr
, dst
);
1740 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1741 if (dst
.regClass() == v2b
) {
1742 Temp tmp
= bld
.vop1(aco_opcode::v_rsq_f16
, bld
.def(v1
), src
);
1743 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1744 } else if (dst
.regClass() == v1
) {
1745 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1746 } else if (dst
.regClass() == v2
) {
1747 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1749 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1750 nir_print_instr(&instr
->instr
, stderr
);
1751 fprintf(stderr
, "\n");
1756 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1757 if (dst
.regClass() == v2b
) {
1758 Temp tmp
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1759 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1760 } else if (dst
.regClass() == v1
) {
1761 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1762 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1763 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1764 } else if (dst
.regClass() == v2
) {
1765 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1766 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1767 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1768 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1769 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1770 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1772 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1773 nir_print_instr(&instr
->instr
, stderr
);
1774 fprintf(stderr
, "\n");
1779 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1780 if (dst
.regClass() == v2b
) {
1781 Temp tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1782 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1783 } else if (dst
.regClass() == v1
) {
1784 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1785 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1786 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1787 } else if (dst
.regClass() == v2
) {
1788 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1789 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1790 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1791 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1792 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1793 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1795 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1796 nir_print_instr(&instr
->instr
, stderr
);
1797 fprintf(stderr
, "\n");
1802 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1803 if (dst
.size() == 1) {
1804 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1805 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1806 // TODO: confirm that this holds under any circumstances
1807 } else if (dst
.size() == 2) {
1808 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1809 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1812 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1813 nir_print_instr(&instr
->instr
, stderr
);
1814 fprintf(stderr
, "\n");
1818 case nir_op_flog2
: {
1819 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1820 if (dst
.regClass() == v2b
) {
1821 Temp tmp
= bld
.vop1(aco_opcode::v_log_f16
, bld
.def(v1
), src
);
1822 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1823 } else if (dst
.regClass() == v1
) {
1824 emit_log2(ctx
, bld
, Definition(dst
), src
);
1826 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1827 nir_print_instr(&instr
->instr
, stderr
);
1828 fprintf(stderr
, "\n");
1833 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1834 if (dst
.regClass() == v2b
) {
1835 Temp tmp
= bld
.vop1(aco_opcode::v_rcp_f16
, bld
.def(v1
), src
);
1836 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1837 } else if (dst
.regClass() == v1
) {
1838 emit_rcp(ctx
, bld
, Definition(dst
), src
);
1839 } else if (dst
.regClass() == v2
) {
1840 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1842 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1843 nir_print_instr(&instr
->instr
, stderr
);
1844 fprintf(stderr
, "\n");
1848 case nir_op_fexp2
: {
1849 if (dst
.regClass() == v2b
) {
1850 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1851 Temp tmp
= bld
.vop1(aco_opcode::v_exp_f16
, bld
.def(v1
), src
);
1852 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1853 } else if (dst
.regClass() == v1
) {
1854 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1856 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1857 nir_print_instr(&instr
->instr
, stderr
);
1858 fprintf(stderr
, "\n");
1862 case nir_op_fsqrt
: {
1863 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1864 if (dst
.regClass() == v2b
) {
1865 Temp tmp
= bld
.vop1(aco_opcode::v_sqrt_f16
, bld
.def(v1
), src
);
1866 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1867 } else if (dst
.regClass() == v1
) {
1868 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
1869 } else if (dst
.regClass() == v2
) {
1870 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1872 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1873 nir_print_instr(&instr
->instr
, stderr
);
1874 fprintf(stderr
, "\n");
1878 case nir_op_ffract
: {
1879 if (dst
.regClass() == v2b
) {
1880 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1881 Temp tmp
= bld
.vop1(aco_opcode::v_fract_f16
, bld
.def(v1
), src
);
1882 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1883 } else if (dst
.regClass() == v1
) {
1884 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1885 } else if (dst
.regClass() == v2
) {
1886 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1888 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1889 nir_print_instr(&instr
->instr
, stderr
);
1890 fprintf(stderr
, "\n");
1894 case nir_op_ffloor
: {
1895 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1896 if (dst
.regClass() == v2b
) {
1897 Temp tmp
= bld
.vop1(aco_opcode::v_floor_f16
, bld
.def(v1
), src
);
1898 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1899 } else if (dst
.regClass() == v1
) {
1900 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
1901 } else if (dst
.regClass() == v2
) {
1902 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
1904 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1905 nir_print_instr(&instr
->instr
, stderr
);
1906 fprintf(stderr
, "\n");
1910 case nir_op_fceil
: {
1911 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1912 if (dst
.regClass() == v2b
) {
1913 Temp tmp
= bld
.vop1(aco_opcode::v_ceil_f16
, bld
.def(v1
), src0
);
1914 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1915 } else if (dst
.regClass() == v1
) {
1916 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
1917 } else if (dst
.regClass() == v2
) {
1918 if (ctx
->options
->chip_class
>= GFX7
) {
1919 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
1921 /* GFX6 doesn't support V_CEIL_F64, lower it. */
1922 /* trunc = trunc(src0)
1923 * if (src0 > 0.0 && src0 != trunc)
1926 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
1927 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
1928 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
1929 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
1930 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
1931 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
1932 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
1935 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1936 nir_print_instr(&instr
->instr
, stderr
);
1937 fprintf(stderr
, "\n");
1941 case nir_op_ftrunc
: {
1942 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1943 if (dst
.regClass() == v2b
) {
1944 Temp tmp
= bld
.vop1(aco_opcode::v_trunc_f16
, bld
.def(v1
), src
);
1945 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1946 } else if (dst
.regClass() == v1
) {
1947 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
1948 } else if (dst
.regClass() == v2
) {
1949 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
1951 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1952 nir_print_instr(&instr
->instr
, stderr
);
1953 fprintf(stderr
, "\n");
1957 case nir_op_fround_even
: {
1958 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1959 if (dst
.regClass() == v2b
) {
1960 Temp tmp
= bld
.vop1(aco_opcode::v_rndne_f16
, bld
.def(v1
), src0
);
1961 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1962 } else if (dst
.regClass() == v1
) {
1963 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
1964 } else if (dst
.regClass() == v2
) {
1965 if (ctx
->options
->chip_class
>= GFX7
) {
1966 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
1968 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
1969 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
1970 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
1972 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
1973 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
1974 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
1975 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
1976 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
1977 tmp
= sub
->definitions
[0].getTemp();
1979 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
1980 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
1981 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
1982 Temp cond
= vop3
->definitions
[0].getTemp();
1984 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
1985 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
1986 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
1987 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
1989 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1992 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1993 nir_print_instr(&instr
->instr
, stderr
);
1994 fprintf(stderr
, "\n");
2000 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2001 aco_ptr
<Instruction
> norm
;
2002 if (dst
.size() == 1) {
2003 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2004 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, as_vgpr(ctx
, src
));
2006 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2007 if (ctx
->options
->chip_class
< GFX9
)
2008 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2010 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2011 bld
.vop1(opcode
, Definition(dst
), tmp
);
2013 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2014 nir_print_instr(&instr
->instr
, stderr
);
2015 fprintf(stderr
, "\n");
2019 case nir_op_ldexp
: {
2020 if (dst
.size() == 1) {
2021 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
),
2022 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0])),
2023 get_alu_src(ctx
, instr
->src
[1]));
2024 } else if (dst
.size() == 2) {
2025 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
),
2026 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0])),
2027 get_alu_src(ctx
, instr
->src
[1]));
2029 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2030 nir_print_instr(&instr
->instr
, stderr
);
2031 fprintf(stderr
, "\n");
2035 case nir_op_frexp_sig
: {
2036 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2037 if (dst
.regClass() == v2b
) {
2038 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_mant_f16
, bld
.def(v1
), src
);
2039 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2040 } else if (dst
.regClass() == v1
) {
2041 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2042 } else if (dst
.regClass() == v2
) {
2043 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2045 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2046 nir_print_instr(&instr
->instr
, stderr
);
2047 fprintf(stderr
, "\n");
2051 case nir_op_frexp_exp
: {
2052 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2053 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2054 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2055 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), tmp
, Operand(0u));
2056 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2057 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2058 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2059 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2061 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2062 nir_print_instr(&instr
->instr
, stderr
);
2063 fprintf(stderr
, "\n");
2067 case nir_op_fsign
: {
2068 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2069 if (dst
.size() == 1) {
2070 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2071 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2072 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2073 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2074 } else if (dst
.size() == 2) {
2075 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2076 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2077 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2079 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2080 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2081 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2083 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2085 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2086 nir_print_instr(&instr
->instr
, stderr
);
2087 fprintf(stderr
, "\n");
2092 case nir_op_f2f16_rtne
: {
2093 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2094 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2095 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2096 src
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2097 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2100 case nir_op_f2f16_rtz
: {
2101 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2102 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2103 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2104 src
= bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, bld
.def(v1
), src
, Operand(0u));
2105 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2108 case nir_op_f2f32
: {
2109 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2110 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2111 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2112 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2114 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2115 nir_print_instr(&instr
->instr
, stderr
);
2116 fprintf(stderr
, "\n");
2120 case nir_op_f2f64
: {
2121 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2122 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2123 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2124 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2127 case nir_op_i2f32
: {
2128 assert(dst
.size() == 1);
2129 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_i32
, dst
);
2132 case nir_op_i2f64
: {
2133 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2134 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_i32
, dst
);
2135 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2136 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2137 RegClass rc
= RegClass(src
.type(), 1);
2138 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2139 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2140 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2141 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2142 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2143 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2146 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2147 nir_print_instr(&instr
->instr
, stderr
);
2148 fprintf(stderr
, "\n");
2152 case nir_op_u2f32
: {
2153 assert(dst
.size() == 1);
2154 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_u32
, dst
);
2157 case nir_op_u2f64
: {
2158 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2159 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_u32
, dst
);
2160 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2161 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2162 RegClass rc
= RegClass(src
.type(), 1);
2163 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2164 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2165 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2166 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2167 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2168 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2170 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2171 nir_print_instr(&instr
->instr
, stderr
);
2172 fprintf(stderr
, "\n");
2176 case nir_op_f2i16
: {
2177 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2178 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2179 src
= bld
.vop1(aco_opcode::v_cvt_i16_f16
, bld
.def(v1
), src
);
2180 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2181 src
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
);
2183 src
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
);
2185 if (dst
.type() == RegType::vgpr
)
2186 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2188 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2191 case nir_op_f2u16
: {
2192 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2193 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2194 src
= bld
.vop1(aco_opcode::v_cvt_u16_f16
, bld
.def(v1
), src
);
2195 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2196 src
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
);
2198 src
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
);
2200 if (dst
.type() == RegType::vgpr
)
2201 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2203 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2206 case nir_op_f2i32
: {
2207 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2208 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2209 if (dst
.type() == RegType::vgpr
)
2210 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), src
);
2212 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2213 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
));
2215 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2216 if (dst
.type() == RegType::vgpr
)
2217 bld
.vop1(aco_opcode::v_cvt_i32_f64
, Definition(dst
), src
);
2219 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2220 bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
));
2223 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2224 nir_print_instr(&instr
->instr
, stderr
);
2225 fprintf(stderr
, "\n");
2229 case nir_op_f2u32
: {
2230 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2231 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2232 if (dst
.type() == RegType::vgpr
)
2233 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), src
);
2235 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2236 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
));
2238 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2239 if (dst
.type() == RegType::vgpr
)
2240 bld
.vop1(aco_opcode::v_cvt_u32_f64
, Definition(dst
), src
);
2242 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2243 bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
));
2246 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2247 nir_print_instr(&instr
->instr
, stderr
);
2248 fprintf(stderr
, "\n");
2252 case nir_op_f2i64
: {
2253 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2254 if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::vgpr
) {
2255 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2256 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2257 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2258 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2259 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2260 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2261 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2262 Temp new_exponent
= bld
.tmp(v1
);
2263 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2264 if (ctx
->program
->chip_class
>= GFX8
)
2265 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2267 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2268 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2269 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2270 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2271 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2272 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2273 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2274 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2275 Temp new_lower
= bld
.tmp(v1
);
2276 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2277 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2278 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2280 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::sgpr
) {
2281 if (src
.type() == RegType::vgpr
)
2282 src
= bld
.as_uniform(src
);
2283 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2284 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2285 exponent
= bld
.sop2(aco_opcode::s_max_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2286 exponent
= bld
.sop2(aco_opcode::s_min_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2287 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2288 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2289 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2290 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2291 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2292 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2293 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2294 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2295 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2296 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2297 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2298 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2299 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2300 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2301 Temp borrow
= bld
.tmp(s1
);
2302 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2303 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2304 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2306 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2307 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2308 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2309 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2310 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2311 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2312 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2313 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2314 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2315 if (dst
.type() == RegType::sgpr
) {
2316 lower
= bld
.as_uniform(lower
);
2317 upper
= bld
.as_uniform(upper
);
2319 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2322 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2323 nir_print_instr(&instr
->instr
, stderr
);
2324 fprintf(stderr
, "\n");
2328 case nir_op_f2u64
: {
2329 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2330 if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::vgpr
) {
2331 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2332 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2333 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2334 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2335 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2336 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2337 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2338 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2339 Temp new_exponent
= bld
.tmp(v1
);
2340 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2341 if (ctx
->program
->chip_class
>= GFX8
)
2342 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2344 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2345 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2346 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2347 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2348 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2349 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2350 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2351 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2353 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::sgpr
) {
2354 if (src
.type() == RegType::vgpr
)
2355 src
= bld
.as_uniform(src
);
2356 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2357 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2358 exponent
= bld
.sop2(aco_opcode::s_max_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2359 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2360 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2361 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2362 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2363 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2364 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2365 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2366 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2367 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2368 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2369 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2370 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2371 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2372 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2373 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2375 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2376 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2377 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2378 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2379 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2380 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2381 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2382 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2383 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2384 if (dst
.type() == RegType::sgpr
) {
2385 lower
= bld
.as_uniform(lower
);
2386 upper
= bld
.as_uniform(upper
);
2388 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2391 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2392 nir_print_instr(&instr
->instr
, stderr
);
2393 fprintf(stderr
, "\n");
2397 case nir_op_b2f32
: {
2398 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2399 assert(src
.regClass() == bld
.lm
);
2401 if (dst
.regClass() == s1
) {
2402 src
= bool_to_scalar_condition(ctx
, src
);
2403 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2404 } else if (dst
.regClass() == v1
) {
2405 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2407 unreachable("Wrong destination register class for nir_op_b2f32.");
2411 case nir_op_b2f64
: {
2412 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2413 assert(src
.regClass() == bld
.lm
);
2415 if (dst
.regClass() == s2
) {
2416 src
= bool_to_scalar_condition(ctx
, src
);
2417 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2418 } else if (dst
.regClass() == v2
) {
2419 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2420 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2421 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2423 unreachable("Wrong destination register class for nir_op_b2f64.");
2429 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2430 /* we can actually just say dst = src */
2431 if (src
.regClass() == s1
)
2432 bld
.copy(Definition(dst
), src
);
2434 emit_extract_vector(ctx
, src
, 0, dst
);
2437 case nir_op_i2i16
: {
2438 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2439 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2440 if (dst
.regClass() == s1
) {
2441 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(dst
), Operand(src
));
2443 assert(src
.regClass() == v1b
);
2444 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2445 sdwa
->operands
[0] = Operand(src
);
2446 sdwa
->definitions
[0] = Definition(dst
);
2447 sdwa
->sel
[0] = sdwa_sbyte
;
2448 sdwa
->dst_sel
= sdwa_sword
;
2449 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2452 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2453 /* we can actually just say dst = src */
2454 if (src
.regClass() == s1
)
2455 bld
.copy(Definition(dst
), src
);
2457 emit_extract_vector(ctx
, src
, 0, dst
);
2461 case nir_op_u2u16
: {
2462 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2463 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2464 if (dst
.regClass() == s1
)
2465 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFu
), src
);
2467 assert(src
.regClass() == v1b
);
2468 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2469 sdwa
->operands
[0] = Operand(src
);
2470 sdwa
->definitions
[0] = Definition(dst
);
2471 sdwa
->sel
[0] = sdwa_ubyte
;
2472 sdwa
->dst_sel
= sdwa_uword
;
2473 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2476 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2477 /* we can actually just say dst = src */
2478 if (src
.regClass() == s1
)
2479 bld
.copy(Definition(dst
), src
);
2481 emit_extract_vector(ctx
, src
, 0, dst
);
2485 case nir_op_i2i32
: {
2486 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2487 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2488 if (dst
.regClass() == s1
) {
2489 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(dst
), Operand(src
));
2491 assert(src
.regClass() == v1b
);
2492 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2493 sdwa
->operands
[0] = Operand(src
);
2494 sdwa
->definitions
[0] = Definition(dst
);
2495 sdwa
->sel
[0] = sdwa_sbyte
;
2496 sdwa
->dst_sel
= sdwa_sdword
;
2497 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2499 } else if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2500 if (dst
.regClass() == s1
) {
2501 bld
.sop1(aco_opcode::s_sext_i32_i16
, Definition(dst
), Operand(src
));
2503 assert(src
.regClass() == v2b
);
2504 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2505 sdwa
->operands
[0] = Operand(src
);
2506 sdwa
->definitions
[0] = Definition(dst
);
2507 sdwa
->sel
[0] = sdwa_sword
;
2508 sdwa
->dst_sel
= sdwa_udword
;
2509 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2511 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2512 /* we can actually just say dst = src, as it would map the lower register */
2513 emit_extract_vector(ctx
, src
, 0, dst
);
2515 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2516 nir_print_instr(&instr
->instr
, stderr
);
2517 fprintf(stderr
, "\n");
2521 case nir_op_u2u32
: {
2522 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2523 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2524 if (dst
.regClass() == s1
)
2525 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFu
), src
);
2527 assert(src
.regClass() == v1b
);
2528 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2529 sdwa
->operands
[0] = Operand(src
);
2530 sdwa
->definitions
[0] = Definition(dst
);
2531 sdwa
->sel
[0] = sdwa_ubyte
;
2532 sdwa
->dst_sel
= sdwa_udword
;
2533 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2535 } else if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2536 if (dst
.regClass() == s1
) {
2537 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFFFu
), src
);
2539 assert(src
.regClass() == v2b
);
2540 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2541 sdwa
->operands
[0] = Operand(src
);
2542 sdwa
->definitions
[0] = Definition(dst
);
2543 sdwa
->sel
[0] = sdwa_uword
;
2544 sdwa
->dst_sel
= sdwa_udword
;
2545 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2547 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2548 /* we can actually just say dst = src, as it would map the lower register */
2549 emit_extract_vector(ctx
, src
, 0, dst
);
2551 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2552 nir_print_instr(&instr
->instr
, stderr
);
2553 fprintf(stderr
, "\n");
2557 case nir_op_i2i64
: {
2558 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2559 if (src
.regClass() == s1
) {
2560 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2561 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, high
);
2562 } else if (src
.regClass() == v1
) {
2563 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2564 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, high
);
2566 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2567 nir_print_instr(&instr
->instr
, stderr
);
2568 fprintf(stderr
, "\n");
2572 case nir_op_u2u64
: {
2573 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2574 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2575 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, Operand(0u));
2577 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2578 nir_print_instr(&instr
->instr
, stderr
);
2579 fprintf(stderr
, "\n");
2584 case nir_op_b2i32
: {
2585 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2586 assert(src
.regClass() == bld
.lm
);
2588 if (dst
.regClass() == s1
) {
2589 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2590 bool_to_scalar_condition(ctx
, src
, dst
);
2591 } else if (dst
.regClass() == v1
) {
2592 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2594 unreachable("Invalid register class for b2i32");
2600 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2601 assert(dst
.regClass() == bld
.lm
);
2603 if (src
.type() == RegType::vgpr
) {
2604 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2605 assert(dst
.regClass() == bld
.lm
);
2606 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2607 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2609 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2611 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2612 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2614 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2615 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2617 bool_to_vector_condition(ctx
, tmp
, dst
);
2621 case nir_op_pack_64_2x32_split
: {
2622 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2623 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2625 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2628 case nir_op_unpack_64_2x32_split_x
:
2629 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2631 case nir_op_unpack_64_2x32_split_y
:
2632 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2634 case nir_op_unpack_32_2x16_split_x
:
2635 if (dst
.type() == RegType::vgpr
) {
2636 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2638 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2641 case nir_op_unpack_32_2x16_split_y
:
2642 if (dst
.type() == RegType::vgpr
) {
2643 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2645 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2648 case nir_op_pack_32_2x16_split
: {
2649 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2650 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2651 if (dst
.regClass() == v1
) {
2652 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2654 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2655 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2656 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2660 case nir_op_pack_half_2x16
: {
2661 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2663 if (dst
.regClass() == v1
) {
2664 Temp src0
= bld
.tmp(v1
);
2665 Temp src1
= bld
.tmp(v1
);
2666 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2667 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2668 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2670 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2671 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2672 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2674 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2675 nir_print_instr(&instr
->instr
, stderr
);
2676 fprintf(stderr
, "\n");
2680 case nir_op_unpack_half_2x16_split_x
: {
2681 if (dst
.regClass() == v1
) {
2682 Builder
bld(ctx
->program
, ctx
->block
);
2683 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2685 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2686 nir_print_instr(&instr
->instr
, stderr
);
2687 fprintf(stderr
, "\n");
2691 case nir_op_unpack_half_2x16_split_y
: {
2692 if (dst
.regClass() == v1
) {
2693 Builder
bld(ctx
->program
, ctx
->block
);
2694 /* TODO: use SDWA here */
2695 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2696 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2698 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2699 nir_print_instr(&instr
->instr
, stderr
);
2700 fprintf(stderr
, "\n");
2704 case nir_op_fquantize2f16
: {
2705 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2706 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2709 if (ctx
->program
->chip_class
>= GFX8
) {
2710 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2711 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2712 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2714 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2715 * so compare the result and flush to 0 if it's smaller.
2717 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2718 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2719 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2720 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2721 cmp_res
= vop3
->definitions
[0].getTemp();
2724 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2725 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2726 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2728 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2733 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2734 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2736 if (dst
.regClass() == s1
) {
2737 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2738 } else if (dst
.regClass() == v1
) {
2739 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2741 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2742 nir_print_instr(&instr
->instr
, stderr
);
2743 fprintf(stderr
, "\n");
2747 case nir_op_bitfield_select
: {
2748 /* (mask & insert) | (~mask & base) */
2749 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2750 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2751 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2753 /* dst = (insert & bitmask) | (base & ~bitmask) */
2754 if (dst
.regClass() == s1
) {
2755 aco_ptr
<Instruction
> sop2
;
2756 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2757 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2759 if (const_insert
&& const_bitmask
) {
2760 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2762 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2763 lhs
= Operand(insert
);
2767 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2768 if (const_base
&& const_bitmask
) {
2769 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2771 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2772 rhs
= Operand(base
);
2775 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2777 } else if (dst
.regClass() == v1
) {
2778 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2779 base
= as_vgpr(ctx
, base
);
2780 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2781 insert
= as_vgpr(ctx
, insert
);
2783 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2786 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2787 nir_print_instr(&instr
->instr
, stderr
);
2788 fprintf(stderr
, "\n");
2794 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2795 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2796 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2798 if (dst
.type() == RegType::sgpr
) {
2800 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2801 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2802 if (const_offset
&& const_bits
) {
2803 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2804 extract
= Operand(const_extract
);
2808 width
= Operand(const_bits
->u32
<< 16);
2810 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2812 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2816 if (dst
.regClass() == s1
) {
2817 if (instr
->op
== nir_op_ubfe
)
2818 opcode
= aco_opcode::s_bfe_u32
;
2820 opcode
= aco_opcode::s_bfe_i32
;
2821 } else if (dst
.regClass() == s2
) {
2822 if (instr
->op
== nir_op_ubfe
)
2823 opcode
= aco_opcode::s_bfe_u64
;
2825 opcode
= aco_opcode::s_bfe_i64
;
2827 unreachable("Unsupported BFE bit size");
2830 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2834 if (dst
.regClass() == v1
) {
2835 if (instr
->op
== nir_op_ubfe
)
2836 opcode
= aco_opcode::v_bfe_u32
;
2838 opcode
= aco_opcode::v_bfe_i32
;
2840 unreachable("Unsupported BFE bit size");
2843 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2847 case nir_op_bit_count
: {
2848 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2849 if (src
.regClass() == s1
) {
2850 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2851 } else if (src
.regClass() == v1
) {
2852 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2853 } else if (src
.regClass() == v2
) {
2854 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2855 emit_extract_vector(ctx
, src
, 1, v1
),
2856 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2857 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2858 } else if (src
.regClass() == s2
) {
2859 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2861 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2862 nir_print_instr(&instr
->instr
, stderr
);
2863 fprintf(stderr
, "\n");
2868 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2872 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2876 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2880 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2884 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2888 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2892 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2893 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2895 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2896 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2900 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2901 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2903 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2904 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2908 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2912 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2917 case nir_op_fddx_fine
:
2918 case nir_op_fddy_fine
:
2919 case nir_op_fddx_coarse
:
2920 case nir_op_fddy_coarse
: {
2921 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2922 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2923 if (instr
->op
== nir_op_fddx_fine
) {
2924 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2925 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2926 } else if (instr
->op
== nir_op_fddy_fine
) {
2927 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2928 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2930 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2931 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2932 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2934 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2938 if (ctx
->program
->chip_class
>= GFX8
) {
2939 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2940 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2942 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
2943 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
2944 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
2946 emit_wqm(ctx
, tmp
, dst
, true);
2950 fprintf(stderr
, "Unknown NIR ALU instr: ");
2951 nir_print_instr(&instr
->instr
, stderr
);
2952 fprintf(stderr
, "\n");
2956 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
2958 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
2960 // TODO: we really want to have the resulting type as this would allow for 64bit literals
2961 // which get truncated the lsb if double and msb if int
2962 // for now, we only use s_mov_b64 with 64bit inline constants
2963 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
2964 assert(dst
.type() == RegType::sgpr
);
2966 Builder
bld(ctx
->program
, ctx
->block
);
2968 if (instr
->def
.bit_size
== 1) {
2969 assert(dst
.regClass() == bld
.lm
);
2970 int val
= instr
->value
[0].b
? -1 : 0;
2971 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
2972 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
2973 } else if (dst
.size() == 1) {
2974 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
2976 assert(dst
.size() != 1);
2977 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
2978 if (instr
->def
.bit_size
== 64)
2979 for (unsigned i
= 0; i
< dst
.size(); i
++)
2980 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
2982 for (unsigned i
= 0; i
< dst
.size(); i
++)
2983 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
2985 vec
->definitions
[0] = Definition(dst
);
2986 ctx
->block
->instructions
.emplace_back(std::move(vec
));
2990 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
2992 uint32_t new_mask
= 0;
2993 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
2994 if (mask
& (1u << i
))
2995 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
2999 Operand
load_lds_size_m0(isel_context
*ctx
)
3001 /* TODO: m0 does not need to be initialized on GFX9+ */
3002 Builder
bld(ctx
->program
, ctx
->block
);
3003 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3006 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3007 Temp address
, unsigned base_offset
, unsigned align
)
3009 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
3011 Builder
bld(ctx
->program
, ctx
->block
);
3013 Operand m
= load_lds_size_m0(ctx
);
3015 unsigned num_components
= dst
.size() * 4u / elem_size_bytes
;
3016 unsigned bytes_read
= 0;
3017 unsigned result_size
= 0;
3018 unsigned total_bytes
= num_components
* elem_size_bytes
;
3019 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> result
;
3020 bool large_ds_read
= ctx
->options
->chip_class
>= GFX7
;
3021 bool usable_read2
= ctx
->options
->chip_class
>= GFX7
;
3023 while (bytes_read
< total_bytes
) {
3024 unsigned todo
= total_bytes
- bytes_read
;
3025 bool aligned8
= bytes_read
% 8 == 0 && align
% 8 == 0;
3026 bool aligned16
= bytes_read
% 16 == 0 && align
% 16 == 0;
3028 aco_opcode op
= aco_opcode::last_opcode
;
3030 if (todo
>= 16 && aligned16
&& large_ds_read
) {
3031 op
= aco_opcode::ds_read_b128
;
3033 } else if (todo
>= 16 && aligned8
&& usable_read2
) {
3034 op
= aco_opcode::ds_read2_b64
;
3037 } else if (todo
>= 12 && aligned16
&& large_ds_read
) {
3038 op
= aco_opcode::ds_read_b96
;
3040 } else if (todo
>= 8 && aligned8
) {
3041 op
= aco_opcode::ds_read_b64
;
3043 } else if (todo
>= 8 && usable_read2
) {
3044 op
= aco_opcode::ds_read2_b32
;
3047 } else if (todo
>= 4) {
3048 op
= aco_opcode::ds_read_b32
;
3053 assert(todo
% elem_size_bytes
== 0);
3054 unsigned num_elements
= todo
/ elem_size_bytes
;
3055 unsigned offset
= base_offset
+ bytes_read
;
3056 unsigned max_offset
= read2
? 1019 : 65535;
3058 Temp address_offset
= address
;
3059 if (offset
> max_offset
) {
3060 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3061 offset
= bytes_read
;
3063 assert(offset
<= max_offset
); /* bytes_read shouldn't be large enough for this to happen */
3066 if (num_components
== 1 && dst
.type() == RegType::vgpr
)
3069 res
= bld
.tmp(RegClass(RegType::vgpr
, todo
/ 4));
3072 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
/ (todo
/ 2), (offset
/ (todo
/ 2)) + 1);
3074 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
);
3076 if (num_components
== 1) {
3077 assert(todo
== total_bytes
);
3078 if (dst
.type() == RegType::sgpr
)
3079 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), res
);
3083 if (dst
.type() == RegType::sgpr
) {
3084 Temp new_res
= bld
.tmp(RegType::sgpr
, res
.size());
3085 expand_vector(ctx
, res
, new_res
, res
.size(), (1 << res
.size()) - 1);
3089 if (num_elements
== 1) {
3090 result
[result_size
++] = res
;
3092 assert(res
!= dst
&& res
.size() % num_elements
== 0);
3093 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_elements
)};
3094 split
->operands
[0] = Operand(res
);
3095 for (unsigned i
= 0; i
< num_elements
; i
++)
3096 split
->definitions
[i
] = Definition(result
[result_size
++] = bld
.tmp(res
.type(), elem_size_bytes
/ 4));
3097 ctx
->block
->instructions
.emplace_back(std::move(split
));
3103 assert(result_size
== num_components
&& result_size
> 1);
3104 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, result_size
, 1)};
3105 for (unsigned i
= 0; i
< result_size
; i
++)
3106 vec
->operands
[i
] = Operand(result
[i
]);
3107 vec
->definitions
[0] = Definition(dst
);
3108 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3109 ctx
->allocated_vec
.emplace(dst
.id(), result
);
3114 Temp
extract_subvector(isel_context
*ctx
, Temp data
, unsigned start
, unsigned size
, RegType type
)
3116 if (start
== 0 && size
== data
.size())
3117 return type
== RegType::vgpr
? as_vgpr(ctx
, data
) : data
;
3119 unsigned size_hint
= 1;
3120 auto it
= ctx
->allocated_vec
.find(data
.id());
3121 if (it
!= ctx
->allocated_vec
.end())
3122 size_hint
= it
->second
[0].size();
3123 if (size
% size_hint
|| start
% size_hint
)
3130 for (unsigned i
= 0; i
< size
; i
++)
3131 elems
[i
] = emit_extract_vector(ctx
, data
, start
+ i
, RegClass(type
, size_hint
));
3134 return type
== RegType::vgpr
? as_vgpr(ctx
, elems
[0]) : elems
[0];
3136 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
3137 for (unsigned i
= 0; i
< size
; i
++)
3138 vec
->operands
[i
] = Operand(elems
[i
]);
3139 Temp res
= {ctx
->program
->allocateId(), RegClass(type
, size
* size_hint
)};
3140 vec
->definitions
[0] = Definition(res
);
3141 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3145 void ds_write_helper(isel_context
*ctx
, Operand m
, Temp address
, Temp data
, unsigned data_start
, unsigned total_size
, unsigned offset0
, unsigned offset1
, unsigned align
)
3147 Builder
bld(ctx
->program
, ctx
->block
);
3148 unsigned bytes_written
= 0;
3149 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3150 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3152 while (bytes_written
< total_size
* 4) {
3153 unsigned todo
= total_size
* 4 - bytes_written
;
3154 bool aligned8
= bytes_written
% 8 == 0 && align
% 8 == 0;
3155 bool aligned16
= bytes_written
% 16 == 0 && align
% 16 == 0;
3157 aco_opcode op
= aco_opcode::last_opcode
;
3158 bool write2
= false;
3160 if (todo
>= 16 && aligned16
&& large_ds_write
) {
3161 op
= aco_opcode::ds_write_b128
;
3163 } else if (todo
>= 16 && aligned8
&& usable_write2
) {
3164 op
= aco_opcode::ds_write2_b64
;
3167 } else if (todo
>= 12 && aligned16
&& large_ds_write
) {
3168 op
= aco_opcode::ds_write_b96
;
3170 } else if (todo
>= 8 && aligned8
) {
3171 op
= aco_opcode::ds_write_b64
;
3173 } else if (todo
>= 8 && usable_write2
) {
3174 op
= aco_opcode::ds_write2_b32
;
3177 } else if (todo
>= 4) {
3178 op
= aco_opcode::ds_write_b32
;
3184 unsigned offset
= offset0
+ offset1
+ bytes_written
;
3185 unsigned max_offset
= write2
? 1020 : 65535;
3186 Temp address_offset
= address
;
3187 if (offset
> max_offset
) {
3188 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(offset0
), address_offset
);
3189 offset
= offset1
+ bytes_written
;
3191 assert(offset
<= max_offset
); /* offset1 shouldn't be large enough for this to happen */
3194 Temp val0
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
/ 2, RegType::vgpr
);
3195 Temp val1
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2) + 1, size
/ 2, RegType::vgpr
);
3196 bld
.ds(op
, address_offset
, val0
, val1
, m
, offset
/ size
/ 2, (offset
/ size
/ 2) + 1);
3198 Temp val
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
, RegType::vgpr
);
3199 bld
.ds(op
, address_offset
, val
, m
, offset
);
3202 bytes_written
+= size
* 4;
3206 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3207 Temp address
, unsigned base_offset
, unsigned align
)
3209 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
3210 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3212 Operand m
= load_lds_size_m0(ctx
);
3214 /* we need at most two stores, assuming that the writemask is at most 4 bits wide */
3215 assert(wrmask
<= 0x0f);
3216 int start
[2], count
[2];
3217 u_bit_scan_consecutive_range(&wrmask
, &start
[0], &count
[0]);
3218 u_bit_scan_consecutive_range(&wrmask
, &start
[1], &count
[1]);
3219 assert(wrmask
== 0);
3221 /* one combined store is sufficient */
3222 if (count
[0] == count
[1] && (align
% elem_size_bytes
) == 0 && (base_offset
% elem_size_bytes
) == 0) {
3223 Builder
bld(ctx
->program
, ctx
->block
);
3225 Temp address_offset
= address
;
3226 if ((base_offset
/ elem_size_bytes
) + start
[1] > 255) {
3227 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3231 assert(count
[0] == 1);
3232 RegClass
xtract_rc(RegType::vgpr
, elem_size_bytes
/ 4);
3234 Temp val0
= emit_extract_vector(ctx
, data
, start
[0], xtract_rc
);
3235 Temp val1
= emit_extract_vector(ctx
, data
, start
[1], xtract_rc
);
3236 aco_opcode op
= elem_size_bytes
== 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3237 base_offset
= base_offset
/ elem_size_bytes
;
3238 bld
.ds(op
, address_offset
, val0
, val1
, m
,
3239 base_offset
+ start
[0], base_offset
+ start
[1]);
3243 for (unsigned i
= 0; i
< 2; i
++) {
3247 unsigned elem_size_words
= elem_size_bytes
/ 4;
3248 ds_write_helper(ctx
, m
, address
, data
, start
[i
] * elem_size_words
, count
[i
] * elem_size_words
,
3249 base_offset
, start
[i
] * elem_size_bytes
, align
);
3254 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3256 unsigned align
= 16;
3258 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3264 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3265 unsigned split_cnt
= 0u, Temp dst
= Temp())
3267 Builder
bld(ctx
->program
, ctx
->block
);
3268 unsigned dword_size
= elem_size_bytes
/ 4;
3271 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3273 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3274 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3275 instr
->definitions
[0] = Definition(dst
);
3277 for (unsigned i
= 0; i
< cnt
; ++i
) {
3279 assert(arr
[i
].size() == dword_size
);
3280 allocated_vec
[i
] = arr
[i
];
3281 instr
->operands
[i
] = Operand(arr
[i
]);
3283 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3284 allocated_vec
[i
] = zero
;
3285 instr
->operands
[i
] = Operand(zero
);
3289 bld
.insert(std::move(instr
));
3292 emit_split_vector(ctx
, dst
, split_cnt
);
3294 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3299 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3301 if (const_offset
>= 4096) {
3302 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3303 const_offset
%= 4096u;
3306 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3307 else if (unlikely(voffset
.regClass() == s1
))
3308 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3309 else if (likely(voffset
.regClass() == v1
))
3310 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3312 unreachable("Unsupported register class of voffset");
3315 return const_offset
;
3318 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3319 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3322 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3323 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3325 Builder
bld(ctx
->program
, ctx
->block
);
3326 aco_opcode op
= (aco_opcode
) ((unsigned) aco_opcode::buffer_store_dword
+ vdata
.size() - 1);
3327 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3329 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3330 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3331 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3332 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3333 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3335 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3338 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3339 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3340 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3342 Builder
bld(ctx
->program
, ctx
->block
);
3343 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3346 if (elem_size_bytes
== 8) {
3347 elem_size_bytes
= 4;
3348 write_mask
= widen_mask(write_mask
, 2);
3351 while (write_mask
) {
3354 u_bit_scan_consecutive_range(&write_mask
, &start
, &count
);
3359 unsigned sub_count
= allow_combining
? MIN2(count
, 4) : 1;
3360 unsigned const_offset
= (unsigned) start
* elem_size_bytes
+ base_const_offset
;
3362 /* GFX6 doesn't have buffer_store_dwordx3, so make sure not to emit that here either. */
3363 if (unlikely(ctx
->program
->chip_class
== GFX6
&& sub_count
== 3))
3366 Temp elem
= extract_subvector(ctx
, src
, start
, sub_count
, RegType::vgpr
);
3367 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, elem
, const_offset
, reorder
, slc
);
3377 Temp
emit_single_mubuf_load(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
,
3378 unsigned const_offset
, unsigned size_dwords
, bool allow_reorder
= true)
3380 assert(size_dwords
!= 3 || ctx
->program
->chip_class
!= GFX6
);
3381 assert(size_dwords
>= 1 && size_dwords
<= 4);
3383 Builder
bld(ctx
->program
, ctx
->block
);
3384 Temp vdata
= bld
.tmp(RegClass(RegType::vgpr
, size_dwords
));
3385 aco_opcode op
= (aco_opcode
) ((unsigned) aco_opcode::buffer_load_dword
+ size_dwords
- 1);
3386 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3388 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3389 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3390 Builder::Result r
= bld
.mubuf(op
, Definition(vdata
), Operand(descriptor
), voffset_op
, soffset_op
, const_offset
,
3391 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3392 /* disable_wqm */ false, /* glc */ true,
3393 /* dlc*/ ctx
->program
->chip_class
>= GFX10
, /* slc */ false);
3395 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3400 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3401 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3402 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3404 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3405 assert((num_components
* elem_size_bytes
/ 4) == dst
.size());
3406 assert(!!stride
!= allow_combining
);
3408 Builder
bld(ctx
->program
, ctx
->block
);
3409 unsigned split_cnt
= num_components
;
3411 if (elem_size_bytes
== 8) {
3412 elem_size_bytes
= 4;
3413 num_components
*= 2;
3417 stride
= elem_size_bytes
;
3419 unsigned load_size
= 1;
3420 if (allow_combining
) {
3421 if ((num_components
% 4) == 0)
3423 else if ((num_components
% 3) == 0 && ctx
->program
->chip_class
!= GFX6
)
3425 else if ((num_components
% 2) == 0)
3429 unsigned num_loads
= num_components
/ load_size
;
3430 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
3432 for (unsigned i
= 0; i
< num_loads
; ++i
) {
3433 unsigned const_offset
= i
* stride
* load_size
+ base_const_offset
;
3434 elems
[i
] = emit_single_mubuf_load(ctx
, descriptor
, voffset
, soffset
, const_offset
, load_size
, allow_reorder
);
3437 create_vec_from_array(ctx
, elems
.data(), num_loads
, RegType::vgpr
, load_size
* 4u, split_cnt
, dst
);
3440 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
3442 Builder
bld(ctx
->program
, ctx
->block
);
3443 Temp offset
= base_offset
.first
;
3444 unsigned const_offset
= base_offset
.second
;
3446 if (!nir_src_is_const(*off_src
)) {
3447 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
3450 /* Calculate indirect offset with stride */
3451 if (likely(indirect_offset_arg
.regClass() == v1
))
3452 with_stride
= bld
.v_mul_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
3453 else if (indirect_offset_arg
.regClass() == s1
)
3454 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
3456 unreachable("Unsupported register class of indirect offset");
3458 /* Add to the supplied base offset */
3459 if (offset
.id() == 0)
3460 offset
= with_stride
;
3461 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
3462 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
3463 else if (offset
.size() == 1 && with_stride
.size() == 1)
3464 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
3466 unreachable("Unsupported register class of indirect offset");
3468 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
3469 const_offset
+= const_offset_arg
* stride
;
3472 return std::make_pair(offset
, const_offset
);
3475 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
3477 Builder
bld(ctx
->program
, ctx
->block
);
3480 if (off1
.first
.id() && off2
.first
.id()) {
3481 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
3482 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
3483 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
3484 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
3486 unreachable("Unsupported register class of indirect offset");
3488 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
3491 return std::make_pair(offset
, off1
.second
+ off2
.second
);
3494 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
3496 Builder
bld(ctx
->program
, ctx
->block
);
3497 unsigned const_offset
= offs
.second
* multiplier
;
3499 if (!offs
.first
.id())
3500 return std::make_pair(offs
.first
, const_offset
);
3502 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
3503 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
3504 : bld
.v_mul_imm(bld
.def(v1
), offs
.first
, multiplier
);
3506 return std::make_pair(offset
, const_offset
);
3509 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
3511 Builder
bld(ctx
->program
, ctx
->block
);
3513 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
3514 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
3515 /* component is in bytes */
3516 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
3518 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
3519 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3520 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
3523 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
3525 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
3528 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
3530 Builder
bld(ctx
->program
, ctx
->block
);
3532 switch (ctx
->shader
->info
.stage
) {
3533 case MESA_SHADER_TESS_CTRL
:
3534 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
3535 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
3536 case MESA_SHADER_TESS_EVAL
:
3537 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
3539 unreachable("Unsupported stage in get_tess_rel_patch_id");
3543 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3545 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3546 Builder
bld(ctx
->program
, ctx
->block
);
3548 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
3549 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
3551 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
3553 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3554 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
3556 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3557 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
3558 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
3560 return offset_mul(ctx
, offs
, 4u);
3563 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
3565 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3566 Builder
bld(ctx
->program
, ctx
->block
);
3568 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
3569 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
3570 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
3571 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
3572 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
3573 uint32_t output_patch_stride
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
3575 std::pair
<Temp
, unsigned> offs
= instr
3576 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
3577 : std::make_pair(Temp(), 0u);
3579 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3580 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
3585 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3586 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
3588 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
3589 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
3591 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
3592 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
3598 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3600 Builder
bld(ctx
->program
, ctx
->block
);
3602 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
3603 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
3605 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
3607 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3608 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
3609 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
3611 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3612 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
3617 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
3619 Builder
bld(ctx
->program
, ctx
->block
);
3621 unsigned num_tcs_outputs
= ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
3622 ? util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
)
3623 : ctx
->args
->options
->key
.tes
.tcs_num_outputs
;
3625 unsigned output_vertex_size
= num_tcs_outputs
* 16;
3626 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
3627 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
3628 unsigned attr_stride
= ctx
->tcs_num_patches
;
3630 std::pair
<Temp
, unsigned> offs
= instr
3631 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
3632 : std::make_pair(Temp(), 0u);
3634 if (const_base_offset
)
3635 offs
.second
+= const_base_offset
* attr_stride
;
3637 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3638 Temp patch_off
= bld
.v_mul_imm(bld
.def(v1
), rel_patch_id
, 16u);
3639 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
3644 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
3646 unsigned off
= nir_intrinsic_base(instr
) * 4u;
3647 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3649 if (!nir_src_is_const(*off_src
)) {
3655 off
+= nir_src_as_uint(*off_src
) * 16u;
3658 unsigned slot
= u_bit_scan64(&mask
) + (per_vertex
? 0 : VARYING_SLOT_PATCH0
);
3659 if (off
== shader_io_get_unique_index((gl_varying_slot
) slot
) * 16u)
3666 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3668 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3669 unsigned component
= nir_intrinsic_component(instr
);
3670 unsigned idx
= nir_intrinsic_base(instr
) + component
;
3672 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
3673 if (off_instr
->type
!= nir_instr_type_load_const
)
3676 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3677 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
3679 if (instr
->src
[0].ssa
->bit_size
== 64)
3680 write_mask
= widen_mask(write_mask
, 2);
3682 for (unsigned i
= 0; i
< 8; ++i
) {
3683 if (write_mask
& (1 << i
)) {
3684 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
3685 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, v1
);
3693 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
3695 /* Only TCS per-vertex inputs are supported by this function.
3696 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
3698 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
3701 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3702 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3703 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
3704 bool can_use_temps
= nir_src_is_const(*off_src
) &&
3705 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
3706 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
3711 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
3712 Temp
*src
= &ctx
->inputs
.temps
[idx
];
3713 Temp vec
= create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u);
3714 assert(vec
.size() == dst
.size());
3716 Builder
bld(ctx
->program
, ctx
->block
);
3717 bld
.copy(Definition(dst
), vec
);
3721 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3723 Builder
bld(ctx
->program
, ctx
->block
);
3725 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
3726 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3727 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3728 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
3730 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
3731 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
3732 bool indirect_write
;
3733 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
3734 if (temp_only_input
&& !indirect_write
)
3738 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
3739 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
3740 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
3741 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
3742 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
3746 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
3747 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
3748 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
3749 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
3750 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
3751 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
3752 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
3753 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
3754 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
3755 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
3756 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
3757 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
3758 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
3760 unsigned num_tcs_inputs
= util_last_bit64(ctx
->args
->shader_info
->vs
.ls_outputs_written
);
3761 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
3762 lds_base
= bld
.v_mul_imm(bld
.def(v1
), vertex_idx
, num_tcs_inputs
* 16u);
3764 unreachable("Invalid LS or ES stage");
3767 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
3768 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
3769 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
3773 bool should_write_tcs_patch_output_to_vmem(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3775 unsigned off
= nir_intrinsic_base(instr
) * 4u;
3776 return off
!= ctx
->tcs_tess_lvl_out_loc
&&
3777 off
!= ctx
->tcs_tess_lvl_in_loc
;
3780 bool should_write_tcs_output_to_lds(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3782 /* When none of the appropriate outputs are read, we are OK to never write to LDS */
3783 if (per_vertex
? ctx
->shader
->info
.outputs_read
== 0U : ctx
->shader
->info
.patch_outputs_read
== 0u)
3786 uint64_t mask
= per_vertex
3787 ? ctx
->shader
->info
.outputs_read
3788 : ctx
->shader
->info
.patch_outputs_read
;
3789 bool indirect_write
;
3790 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
3791 return indirect_write
|| output_read
;
3794 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3796 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
3797 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3799 Builder
bld(ctx
->program
, ctx
->block
);
3801 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3802 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
3803 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3805 /* Only write to VMEM if the output is per-vertex or it's per-patch non tess factor */
3806 bool write_to_vmem
= per_vertex
|| should_write_tcs_patch_output_to_vmem(ctx
, instr
);
3807 /* Only write to LDS if the output is read by the shader, or it's per-patch tess factor */
3808 bool write_to_lds
= !write_to_vmem
|| should_write_tcs_output_to_lds(ctx
, instr
, per_vertex
);
3810 if (write_to_vmem
) {
3811 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
3812 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
3813 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
3815 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
3816 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
3817 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
3821 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
3822 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
3823 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
3827 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3829 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
3830 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3832 Builder
bld(ctx
->program
, ctx
->block
);
3834 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3835 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
3836 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
3837 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
3839 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
3842 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3844 if (ctx
->stage
== vertex_vs
||
3845 ctx
->stage
== tess_eval_vs
||
3846 ctx
->stage
== fragment_fs
||
3847 ctx
->stage
== ngg_vertex_gs
||
3848 ctx
->stage
== ngg_tess_eval_gs
||
3849 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
3850 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
3851 if (!stored_to_temps
) {
3852 fprintf(stderr
, "Unimplemented output offset instruction:\n");
3853 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
3854 fprintf(stderr
, "\n");
3857 } else if (ctx
->stage
== vertex_es
||
3858 ctx
->stage
== vertex_ls
||
3859 ctx
->stage
== tess_eval_es
||
3860 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
3861 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
3862 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
3863 visit_store_ls_or_es_output(ctx
, instr
);
3864 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
3865 visit_store_tcs_output(ctx
, instr
, false);
3867 unreachable("Shader stage not implemented");
3871 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3873 visit_load_tcs_output(ctx
, instr
, false);
3876 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
3878 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
3879 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
3881 Builder
bld(ctx
->program
, ctx
->block
);
3882 Builder::Result interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
, bld
.m0(prim_mask
), idx
, component
);
3883 if (ctx
->program
->has_16bank_lds
)
3884 interp_p1
.instr
->operands
[0].setLateKill(true);
3885 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
3888 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
3890 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
3891 for (unsigned i
= 0; i
< num_components
; i
++)
3892 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
3893 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
3894 assert(num_components
== 4);
3895 Builder
bld(ctx
->program
, ctx
->block
);
3896 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
3899 for (Operand
& op
: vec
->operands
)
3900 op
= op
.isUndefined() ? Operand(0u) : op
;
3902 vec
->definitions
[0] = Definition(dst
);
3903 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3904 emit_split_vector(ctx
, dst
, num_components
);
3908 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3910 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3911 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3912 unsigned idx
= nir_intrinsic_base(instr
);
3913 unsigned component
= nir_intrinsic_component(instr
);
3914 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
3916 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
3918 assert(offset
->u32
== 0);
3920 /* the lower 15bit of the prim_mask contain the offset into LDS
3921 * while the upper bits contain the number of prims */
3922 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
3923 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
3924 Builder
bld(ctx
->program
, ctx
->block
);
3925 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
3926 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
3927 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
3928 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
3929 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
3932 if (instr
->dest
.ssa
.num_components
== 1) {
3933 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
3935 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
3936 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
3938 Temp tmp
= {ctx
->program
->allocateId(), v1
};
3939 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
3940 vec
->operands
[i
] = Operand(tmp
);
3942 vec
->definitions
[0] = Definition(dst
);
3943 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3947 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
3948 unsigned offset
, unsigned stride
, unsigned channels
)
3950 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
3951 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
3953 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
3954 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
3957 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
3958 unsigned offset
, unsigned stride
, unsigned *channels
)
3960 if (!vtx_info
->chan_byte_size
) {
3961 *channels
= vtx_info
->num_channels
;
3962 return vtx_info
->chan_format
;
3965 unsigned num_channels
= *channels
;
3966 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
3967 unsigned new_channels
= num_channels
+ 1;
3968 /* first, assume more loads is worse and try using a larger data format */
3969 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
3971 /* don't make the attribute potentially out-of-bounds */
3972 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
3976 if (new_channels
== 5) {
3977 /* then try decreasing load size (at the cost of more loads) */
3978 new_channels
= *channels
;
3979 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
3983 if (new_channels
< *channels
)
3984 *channels
= new_channels
;
3985 num_channels
= new_channels
;
3988 switch (vtx_info
->chan_format
) {
3989 case V_008F0C_BUF_DATA_FORMAT_8
:
3990 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
3991 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
3992 case V_008F0C_BUF_DATA_FORMAT_16
:
3993 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
3994 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
3995 case V_008F0C_BUF_DATA_FORMAT_32
:
3996 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
3997 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
3999 unreachable("shouldn't reach here");
4000 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4003 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4004 * so we may need to fix it up. */
4005 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4007 Builder
bld(ctx
->program
, ctx
->block
);
4009 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4010 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4012 /* For the integer-like cases, do a natural sign extension.
4014 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4015 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4018 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4019 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4021 /* Convert back to the right type. */
4022 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4023 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4024 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4025 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4026 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4027 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4033 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4035 Builder
bld(ctx
->program
, ctx
->block
);
4036 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4037 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4039 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4040 if (off_instr
->type
!= nir_instr_type_load_const
) {
4041 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4042 nir_print_instr(off_instr
, stderr
);
4043 fprintf(stderr
, "\n");
4045 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4047 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4049 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4050 unsigned component
= nir_intrinsic_component(instr
);
4051 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4052 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4053 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4054 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4056 unsigned dfmt
= attrib_format
& 0xf;
4057 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4058 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4060 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4061 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4062 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4063 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4065 num_channels
= MAX2(num_channels
, 3);
4067 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4068 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4071 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4072 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4073 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4075 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4077 Temp divided
= bld
.tmp(v1
);
4078 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4079 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4081 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4084 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4087 index
= bld
.vadd32(bld
.def(v1
),
4088 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4089 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4092 Temp channels
[num_channels
];
4093 unsigned channel_start
= 0;
4094 bool direct_fetch
= false;
4096 /* skip unused channels at the start */
4097 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4098 channel_start
= ffs(mask
) - 1;
4099 for (unsigned i
= 0; i
< channel_start
; i
++)
4100 channels
[i
] = Temp(0, s1
);
4101 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4102 num_channels
= 3 - (ffs(mask
) - 1);
4106 while (channel_start
< num_channels
) {
4107 unsigned fetch_size
= num_channels
- channel_start
;
4108 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4109 bool expanded
= false;
4111 /* use MUBUF when possible to avoid possible alignment issues */
4112 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4113 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4114 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4115 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4116 vtx_info
->chan_byte_size
== 4;
4117 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4119 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_size
);
4121 if (fetch_size
== 3 && ctx
->options
->chip_class
== GFX6
) {
4122 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4128 Temp fetch_index
= index
;
4129 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4130 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4131 fetch_offset
= fetch_offset
% attrib_stride
;
4134 Operand
soffset(0u);
4135 if (fetch_offset
>= 4096) {
4136 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4137 fetch_offset
%= 4096;
4141 switch (fetch_size
) {
4143 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4146 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4149 assert(ctx
->options
->chip_class
>= GFX7
||
4150 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4151 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4154 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4157 unreachable("Unimplemented load_input vector size");
4161 if (channel_start
== 0 && fetch_size
== dst
.size() && !post_shuffle
&&
4162 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4163 num_channels
<= 3)) {
4164 direct_fetch
= true;
4167 fetch_dst
= bld
.tmp(RegType::vgpr
, fetch_size
);
4171 Instruction
*mubuf
= bld
.mubuf(opcode
,
4172 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4173 fetch_offset
, false, true).instr
;
4174 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4176 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4177 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4178 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4179 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4182 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4184 if (fetch_size
== 1) {
4185 channels
[channel_start
] = fetch_dst
;
4187 for (unsigned i
= 0; i
< MIN2(fetch_size
, num_channels
- channel_start
); i
++)
4188 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
, v1
);
4191 channel_start
+= fetch_size
;
4194 if (!direct_fetch
) {
4195 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4196 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4198 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4199 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4200 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4202 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4203 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4204 unsigned num_temp
= 0;
4205 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4206 unsigned idx
= i
+ component
;
4207 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4208 Temp channel
= channels
[swizzle
[idx
]];
4209 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4210 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4211 vec
->operands
[i
] = Operand(channel
);
4215 } else if (is_float
&& idx
== 3) {
4216 vec
->operands
[i
] = Operand(0x3f800000u
);
4217 } else if (!is_float
&& idx
== 3) {
4218 vec
->operands
[i
] = Operand(1u);
4220 vec
->operands
[i
] = Operand(0u);
4223 vec
->definitions
[0] = Definition(dst
);
4224 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4225 emit_split_vector(ctx
, dst
, dst
.size());
4227 if (num_temp
== dst
.size())
4228 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4230 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4231 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4232 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4233 if (off_instr
->type
!= nir_instr_type_load_const
||
4234 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4235 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4236 nir_print_instr(off_instr
, stderr
);
4237 fprintf(stderr
, "\n");
4240 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4241 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4243 assert(offset
->u32
== 0);
4245 /* the lower 15bit of the prim_mask contain the offset into LDS
4246 * while the upper bits contain the number of prims */
4247 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4248 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4249 Builder
bld(ctx
->program
, ctx
->block
);
4250 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4251 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4252 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4253 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4254 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4257 unsigned idx
= nir_intrinsic_base(instr
);
4258 unsigned component
= nir_intrinsic_component(instr
);
4259 unsigned vertex_id
= 2; /* P0 */
4261 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4262 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4263 switch (src0
->u32
) {
4265 vertex_id
= 2; /* P0 */
4268 vertex_id
= 0; /* P10 */
4271 vertex_id
= 1; /* P20 */
4274 unreachable("invalid vertex index");
4278 if (dst
.size() == 1) {
4279 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4281 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4282 for (unsigned i
= 0; i
< dst
.size(); i
++)
4283 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4284 vec
->definitions
[0] = Definition(dst
);
4285 bld
.insert(std::move(vec
));
4288 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4289 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4290 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4291 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4292 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4294 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4296 unreachable("Shader stage not implemented");
4300 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4302 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4304 Builder
bld(ctx
->program
, ctx
->block
);
4305 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4308 if (!nir_src_is_const(*vertex_src
)) {
4309 /* better code could be created, but this case probably doesn't happen
4310 * much in practice */
4311 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4312 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4315 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4316 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4318 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4320 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4323 if (vertex_offset
.id()) {
4324 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4325 Operand(i
), indirect_vertex
);
4326 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4328 vertex_offset
= elem
;
4332 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4333 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4335 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4336 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4337 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4338 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4339 Operand((vertex
% 2u) * 16u), Operand(16u));
4341 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4344 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4345 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4346 return offset_mul(ctx
, offs
, 4u);
4349 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4351 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4353 Builder
bld(ctx
->program
, ctx
->block
);
4354 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4355 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4357 if (ctx
->stage
== geometry_gs
) {
4358 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4359 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4360 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4361 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4362 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4363 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4364 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4366 unreachable("Unsupported GS stage.");
4370 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4372 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4374 Builder
bld(ctx
->program
, ctx
->block
);
4375 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4377 if (load_input_from_temps(ctx
, instr
, dst
))
4380 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4381 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4382 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4384 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4387 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4389 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4391 Builder
bld(ctx
->program
, ctx
->block
);
4393 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4394 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4395 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4397 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4398 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
4400 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
4403 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4405 switch (ctx
->shader
->info
.stage
) {
4406 case MESA_SHADER_GEOMETRY
:
4407 visit_load_gs_per_vertex_input(ctx
, instr
);
4409 case MESA_SHADER_TESS_CTRL
:
4410 visit_load_tcs_per_vertex_input(ctx
, instr
);
4412 case MESA_SHADER_TESS_EVAL
:
4413 visit_load_tes_per_vertex_input(ctx
, instr
);
4416 unreachable("Unimplemented shader stage");
4420 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4422 visit_load_tcs_output(ctx
, instr
, true);
4425 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4427 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4428 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4430 visit_store_tcs_output(ctx
, instr
, true);
4433 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4435 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4437 Builder
bld(ctx
->program
, ctx
->block
);
4438 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4440 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
4441 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
4444 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
4445 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
4446 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
4447 tes_w
= Operand(tmp
);
4450 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
4451 emit_split_vector(ctx
, tess_coord
, 3);
4454 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
4456 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
4457 Builder
bld(ctx
->program
, ctx
->block
);
4458 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
4459 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
4460 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
4463 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
4467 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4469 Builder
bld(ctx
->program
, ctx
->block
);
4470 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4471 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
])
4472 index
= bld
.as_uniform(index
);
4473 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
4474 unsigned binding
= nir_intrinsic_binding(instr
);
4477 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
4478 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
4479 unsigned offset
= layout
->binding
[binding
].offset
;
4481 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
4482 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
4483 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
4484 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
4485 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
4488 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
4489 stride
= layout
->binding
[binding
].size
;
4492 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
4493 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
4495 if (nir_const_index
) {
4496 const_index
= const_index
* stride
;
4497 } else if (index
.type() == RegType::vgpr
) {
4498 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
4499 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
4501 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
4505 if (nir_const_index
) {
4506 const_index
= const_index
+ offset
;
4507 } else if (index
.type() == RegType::vgpr
) {
4508 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
4510 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
4514 if (nir_const_index
&& const_index
== 0) {
4516 } else if (index
.type() == RegType::vgpr
) {
4517 index
= bld
.vadd32(bld
.def(v1
),
4518 nir_const_index
? Operand(const_index
) : Operand(index
),
4521 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
4522 nir_const_index
? Operand(const_index
) : Operand(index
),
4526 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
4529 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
4530 Temp dst
, Temp rsrc
, Temp offset
, int byte_align
,
4531 bool glc
=false, bool readonly
=true)
4533 Builder
bld(ctx
->program
, ctx
->block
);
4534 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
4535 unsigned num_bytes
= num_components
* component_size
;
4538 if (dst
.type() == RegType::vgpr
|| ((ctx
->options
->chip_class
< GFX8
|| component_size
< 4) && !readonly
)) {
4539 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
4540 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
4541 unsigned const_offset
= 0;
4543 /* for small bit sizes add buffer for unaligned loads */
4546 num_bytes
+= byte_align
== -1 ? 4 - component_size
: byte_align
;
4551 Temp lower
= Temp();
4552 if (num_bytes
> 16) {
4553 assert(num_components
== 3 || num_components
== 4);
4554 op
= aco_opcode::buffer_load_dwordx4
;
4555 lower
= bld
.tmp(v4
);
4556 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
4557 mubuf
->definitions
[0] = Definition(lower
);
4558 mubuf
->operands
[0] = Operand(rsrc
);
4559 mubuf
->operands
[1] = vaddr
;
4560 mubuf
->operands
[2] = soffset
;
4561 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
4564 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4565 mubuf
->can_reorder
= readonly
;
4566 bld
.insert(std::move(mubuf
));
4567 emit_split_vector(ctx
, lower
, 2);
4570 } else if (num_bytes
== 12 && ctx
->options
->chip_class
== GFX6
) {
4571 /* GFX6 doesn't support loading vec3, expand to vec4. */
4575 switch (num_bytes
) {
4577 op
= aco_opcode::buffer_load_ubyte
;
4580 op
= aco_opcode::buffer_load_ushort
;
4584 op
= aco_opcode::buffer_load_dword
;
4590 op
= aco_opcode::buffer_load_dwordx2
;
4594 assert(ctx
->options
->chip_class
> GFX6
);
4595 op
= aco_opcode::buffer_load_dwordx3
;
4598 op
= aco_opcode::buffer_load_dwordx4
;
4601 unreachable("Load SSBO not implemented for this size.");
4603 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
4604 mubuf
->operands
[0] = Operand(rsrc
);
4605 mubuf
->operands
[1] = vaddr
;
4606 mubuf
->operands
[2] = soffset
;
4607 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
4610 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4611 mubuf
->can_reorder
= readonly
;
4612 mubuf
->offset
= const_offset
;
4613 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
4615 if (component_size
< 4) {
4616 Temp vec
= num_bytes
<= 4 ? bld
.tmp(v1
) : num_bytes
<= 8 ? bld
.tmp(v2
) : bld
.tmp(v3
);
4617 instr
->definitions
[0] = Definition(vec
);
4618 bld
.insert(std::move(instr
));
4620 if (byte_align
== -1 || (byte_align
&& dst
.type() == RegType::sgpr
)) {
4621 Operand align
= byte_align
== -1 ? Operand(offset
) : Operand((uint32_t)byte_align
);
4622 Temp tmp
[3] = {vec
, vec
, vec
};
4624 if (vec
.size() == 3) {
4625 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
4626 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
4627 } else if (vec
.size() == 2) {
4628 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
4629 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
4631 for (unsigned i
= 0; i
< dst
.size(); i
++)
4632 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], align
);
4635 if (dst
.size() == 2)
4636 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
4641 if (dst
.type() == RegType::vgpr
&& num_components
== 1) {
4642 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), vec
, Operand(byte_align
/ component_size
));
4644 trim_subdword_vector(ctx
, vec
, dst
, 4 * vec
.size() / component_size
, ((1 << num_components
) - 1) << byte_align
/ component_size
);
4649 } else if (dst
.size() > 4) {
4650 assert(lower
!= Temp());
4651 Temp upper
= bld
.tmp(RegType::vgpr
, dst
.size() - lower
.size());
4652 instr
->definitions
[0] = Definition(upper
);
4653 bld
.insert(std::move(instr
));
4654 if (dst
.size() == 8)
4655 emit_split_vector(ctx
, upper
, 2);
4656 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size() / 2, 1));
4657 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, lower
, 0, v2
));
4658 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, lower
, 1, v2
));
4659 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, upper
, 0, v2
));
4660 if (dst
.size() == 8)
4661 instr
->operands
[3] = Operand(emit_extract_vector(ctx
, upper
, 1, v2
));
4662 } else if (dst
.size() == 3 && ctx
->options
->chip_class
== GFX6
) {
4663 Temp vec
= bld
.tmp(v4
);
4664 instr
->definitions
[0] = Definition(vec
);
4665 bld
.insert(std::move(instr
));
4666 emit_split_vector(ctx
, vec
, 4);
4668 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 3, 1));
4669 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, vec
, 0, v1
));
4670 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, vec
, 1, v1
));
4671 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, vec
, 2, v1
));
4674 if (dst
.type() == RegType::sgpr
) {
4675 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
4676 instr
->definitions
[0] = Definition(vec
);
4677 bld
.insert(std::move(instr
));
4678 expand_vector(ctx
, vec
, dst
, num_components
, (1 << num_components
) - 1);
4680 instr
->definitions
[0] = Definition(dst
);
4681 bld
.insert(std::move(instr
));
4682 emit_split_vector(ctx
, dst
, num_components
);
4685 /* for small bit sizes add buffer for unaligned loads */
4687 num_bytes
+= byte_align
== -1 ? 4 - component_size
: byte_align
;
4689 switch (num_bytes
) {
4694 op
= aco_opcode::s_buffer_load_dword
;
4700 op
= aco_opcode::s_buffer_load_dwordx2
;
4705 op
= aco_opcode::s_buffer_load_dwordx4
;
4709 op
= aco_opcode::s_buffer_load_dwordx8
;
4712 unreachable("Load SSBO not implemented for this size.");
4714 offset
= bld
.as_uniform(offset
);
4715 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
4716 load
->operands
[0] = Operand(rsrc
);
4717 load
->operands
[1] = Operand(offset
);
4718 assert(load
->operands
[1].getTemp().type() == RegType::sgpr
);
4719 load
->definitions
[0] = Definition(dst
);
4722 load
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4723 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
4724 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
4726 /* adjust misaligned small bit size loads */
4728 Temp vec
= num_bytes
<= 4 ? bld
.tmp(s1
) : num_bytes
<= 8 ? bld
.tmp(s2
) : bld
.tmp(s4
);
4729 load
->definitions
[0] = Definition(vec
);
4730 bld
.insert(std::move(load
));
4731 Operand byte_offset
= byte_align
> 0 ? Operand(uint32_t(byte_align
)) : Operand(offset
);
4732 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
4735 } else if (dst
.size() == 3) {
4736 Temp vec
= bld
.tmp(s4
);
4737 load
->definitions
[0] = Definition(vec
);
4738 bld
.insert(std::move(load
));
4739 emit_split_vector(ctx
, vec
, 4);
4741 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4742 emit_extract_vector(ctx
, vec
, 0, s1
),
4743 emit_extract_vector(ctx
, vec
, 1, s1
),
4744 emit_extract_vector(ctx
, vec
, 2, s1
));
4745 } else if (dst
.size() == 6) {
4746 Temp vec
= bld
.tmp(s8
);
4747 load
->definitions
[0] = Definition(vec
);
4748 bld
.insert(std::move(load
));
4749 emit_split_vector(ctx
, vec
, 4);
4751 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4752 emit_extract_vector(ctx
, vec
, 0, s2
),
4753 emit_extract_vector(ctx
, vec
, 1, s2
),
4754 emit_extract_vector(ctx
, vec
, 2, s2
));
4756 bld
.insert(std::move(load
));
4758 emit_split_vector(ctx
, dst
, num_components
);
4762 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4764 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4765 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4767 Builder
bld(ctx
->program
, ctx
->block
);
4769 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
4770 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
4771 unsigned binding
= nir_intrinsic_binding(idx_instr
);
4772 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
4774 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
4775 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
4776 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
4777 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
4778 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
4779 if (ctx
->options
->chip_class
>= GFX10
) {
4780 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
4781 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
4782 S_008F0C_RESOURCE_LEVEL(1);
4784 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
4785 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
4787 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
4788 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
4789 Operand(0xFFFFFFFFu
),
4790 Operand(desc_type
));
4791 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
4792 rsrc
, upper_dwords
);
4794 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
4795 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
4797 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
4800 unsigned align_mul
= nir_intrinsic_align_mul(instr
);
4801 unsigned align_offset
= nir_intrinsic_align_offset(instr
);
4802 byte_align
= align_mul
% 4 == 0 ? align_offset
: -1;
4804 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), byte_align
);
4807 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4809 Builder
bld(ctx
->program
, ctx
->block
);
4810 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4811 unsigned offset
= nir_intrinsic_base(instr
);
4812 unsigned count
= instr
->dest
.ssa
.num_components
;
4813 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
4815 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
4816 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
4817 start
-= ctx
->args
->ac
.base_inline_push_consts
;
4818 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
4819 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4820 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
4821 for (unsigned i
= 0; i
< count
; ++i
) {
4822 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
4823 vec
->operands
[i
] = Operand
{elems
[i
]};
4825 vec
->definitions
[0] = Definition(dst
);
4826 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4827 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4832 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
4833 if (offset
!= 0) // TODO check if index != 0 as well
4834 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
4835 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
4838 bool aligned
= true;
4840 if (instr
->dest
.ssa
.bit_size
== 8) {
4841 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
4842 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
4844 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
4845 } else if (instr
->dest
.ssa
.bit_size
== 16) {
4846 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
4848 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
4853 switch (vec
.size()) {
4855 op
= aco_opcode::s_load_dword
;
4858 op
= aco_opcode::s_load_dwordx2
;
4864 op
= aco_opcode::s_load_dwordx4
;
4870 op
= aco_opcode::s_load_dwordx8
;
4873 unreachable("unimplemented or forbidden load_push_constant.");
4876 bld
.smem(op
, Definition(vec
), ptr
, index
);
4879 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
4880 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
4885 emit_split_vector(ctx
, vec
, 4);
4886 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
4887 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4888 emit_extract_vector(ctx
, vec
, 0, rc
),
4889 emit_extract_vector(ctx
, vec
, 1, rc
),
4890 emit_extract_vector(ctx
, vec
, 2, rc
));
4893 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
4896 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4898 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4900 Builder
bld(ctx
->program
, ctx
->block
);
4902 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
4903 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
4904 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
4905 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
4906 if (ctx
->options
->chip_class
>= GFX10
) {
4907 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
4908 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
4909 S_008F0C_RESOURCE_LEVEL(1);
4911 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
4912 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
4915 unsigned base
= nir_intrinsic_base(instr
);
4916 unsigned range
= nir_intrinsic_range(instr
);
4918 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4919 if (base
&& offset
.type() == RegType::sgpr
)
4920 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
4921 else if (base
&& offset
.type() == RegType::vgpr
)
4922 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
4924 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
4925 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
4926 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
4927 Operand(desc_type
));
4928 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
4929 // TODO: get alignment information for subdword constants
4930 unsigned byte_align
= size
< 4 ? -1 : 0;
4931 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, byte_align
);
4934 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4936 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
4937 ctx
->cf_info
.exec_potentially_empty_discard
= true;
4939 ctx
->program
->needs_exact
= true;
4941 // TODO: optimize uniform conditions
4942 Builder
bld(ctx
->program
, ctx
->block
);
4943 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4944 assert(src
.regClass() == bld
.lm
);
4945 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
4946 bld
.pseudo(aco_opcode::p_discard_if
, src
);
4947 ctx
->block
->kind
|= block_kind_uses_discard_if
;
4951 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
4953 Builder
bld(ctx
->program
, ctx
->block
);
4955 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
4956 ctx
->cf_info
.exec_potentially_empty_discard
= true;
4958 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
4959 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
4961 if (ctx
->block
->loop_nest_depth
&&
4962 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
4963 /* we handle discards the same way as jump instructions */
4964 append_logical_end(ctx
->block
);
4966 /* in loops, discard behaves like break */
4967 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
4968 ctx
->block
->kind
|= block_kind_discard
;
4971 /* uniform discard - loop ends here */
4972 assert(nir_instr_is_last(&instr
->instr
));
4973 ctx
->block
->kind
|= block_kind_uniform
;
4974 ctx
->cf_info
.has_branch
= true;
4975 bld
.branch(aco_opcode::p_branch
);
4976 add_linear_edge(ctx
->block
->index
, linear_target
);
4980 /* we add a break right behind the discard() instructions */
4981 ctx
->block
->kind
|= block_kind_break
;
4982 unsigned idx
= ctx
->block
->index
;
4984 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
4985 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
4987 /* remove critical edges from linear CFG */
4988 bld
.branch(aco_opcode::p_branch
);
4989 Block
* break_block
= ctx
->program
->create_and_insert_block();
4990 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
4991 break_block
->kind
|= block_kind_uniform
;
4992 add_linear_edge(idx
, break_block
);
4993 add_linear_edge(break_block
->index
, linear_target
);
4994 bld
.reset(break_block
);
4995 bld
.branch(aco_opcode::p_branch
);
4997 Block
* continue_block
= ctx
->program
->create_and_insert_block();
4998 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
4999 add_linear_edge(idx
, continue_block
);
5000 append_logical_start(continue_block
);
5001 ctx
->block
= continue_block
;
5006 /* it can currently happen that NIR doesn't remove the unreachable code */
5007 if (!nir_instr_is_last(&instr
->instr
)) {
5008 ctx
->program
->needs_exact
= true;
5009 /* save exec somewhere temporarily so that it doesn't get
5010 * overwritten before the discard from outer exec masks */
5011 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5012 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5013 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5017 /* This condition is incorrect for uniformly branched discards in a loop
5018 * predicated by a divergent condition, but the above code catches that case
5019 * and the discard would end up turning into a discard_if.
5029 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5030 /* program just ends here */
5031 ctx
->block
->kind
|= block_kind_uniform
;
5032 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5033 0 /* enabled mask */, 9 /* dest */,
5034 false /* compressed */, true/* done */, true /* valid mask */);
5035 bld
.sopp(aco_opcode::s_endpgm
);
5036 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5038 ctx
->block
->kind
|= block_kind_discard
;
5039 /* branch and linear edge is added by visit_if() */
5043 enum aco_descriptor_type
{
5054 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5055 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5057 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5058 return dim
== ac_image_cube
||
5059 dim
== ac_image_1darray
||
5060 dim
== ac_image_2darray
||
5061 dim
== ac_image_2darraymsaa
;
5064 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5065 enum aco_descriptor_type desc_type
,
5066 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5068 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5069 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5070 if (it != ctx->tex_desc.end())
5073 Temp index
= Temp();
5074 bool index_set
= false;
5075 unsigned constant_index
= 0;
5076 unsigned descriptor_set
;
5077 unsigned base_index
;
5078 Builder
bld(ctx
->program
, ctx
->block
);
5081 assert(tex_instr
&& !image
);
5083 base_index
= tex_instr
->sampler_index
;
5085 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5086 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5090 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5091 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5093 constant_index
+= array_size
* const_value
->u32
;
5095 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5096 if (indirect
.type() == RegType::vgpr
)
5097 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5099 if (array_size
!= 1)
5100 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5106 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5110 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5112 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5113 base_index
= deref_instr
->var
->data
.binding
;
5116 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5117 list
= convert_pointer_to_64_bit(ctx
, list
);
5119 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5120 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5121 unsigned offset
= binding
->offset
;
5122 unsigned stride
= binding
->size
;
5126 assert(base_index
< layout
->binding_count
);
5128 switch (desc_type
) {
5129 case ACO_DESC_IMAGE
:
5131 opcode
= aco_opcode::s_load_dwordx8
;
5133 case ACO_DESC_FMASK
:
5135 opcode
= aco_opcode::s_load_dwordx8
;
5138 case ACO_DESC_SAMPLER
:
5140 opcode
= aco_opcode::s_load_dwordx4
;
5141 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5142 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5144 case ACO_DESC_BUFFER
:
5146 opcode
= aco_opcode::s_load_dwordx4
;
5148 case ACO_DESC_PLANE_0
:
5149 case ACO_DESC_PLANE_1
:
5151 opcode
= aco_opcode::s_load_dwordx8
;
5152 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5154 case ACO_DESC_PLANE_2
:
5156 opcode
= aco_opcode::s_load_dwordx4
;
5160 unreachable("invalid desc_type\n");
5163 offset
+= constant_index
* stride
;
5165 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5166 (!index_set
|| binding
->immutable_samplers_equal
)) {
5167 if (binding
->immutable_samplers_equal
)
5170 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5171 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5172 Operand(samplers
[constant_index
* 4 + 0]),
5173 Operand(samplers
[constant_index
* 4 + 1]),
5174 Operand(samplers
[constant_index
* 4 + 2]),
5175 Operand(samplers
[constant_index
* 4 + 3]));
5180 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5182 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5183 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5186 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5188 if (desc_type
== ACO_DESC_PLANE_2
) {
5190 for (unsigned i
= 0; i
< 8; i
++)
5191 components
[i
] = bld
.tmp(s1
);
5192 bld
.pseudo(aco_opcode::p_split_vector
,
5193 Definition(components
[0]),
5194 Definition(components
[1]),
5195 Definition(components
[2]),
5196 Definition(components
[3]),
5199 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5200 bld
.pseudo(aco_opcode::p_split_vector
,
5201 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5202 Definition(components
[4]),
5203 Definition(components
[5]),
5204 Definition(components
[6]),
5205 Definition(components
[7]),
5208 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5209 components
[0], components
[1], components
[2], components
[3],
5210 components
[4], components
[5], components
[6], components
[7]);
5216 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5219 case GLSL_SAMPLER_DIM_BUF
:
5221 case GLSL_SAMPLER_DIM_1D
:
5222 return array
? 2 : 1;
5223 case GLSL_SAMPLER_DIM_2D
:
5224 return array
? 3 : 2;
5225 case GLSL_SAMPLER_DIM_MS
:
5226 return array
? 4 : 3;
5227 case GLSL_SAMPLER_DIM_3D
:
5228 case GLSL_SAMPLER_DIM_CUBE
:
5230 case GLSL_SAMPLER_DIM_RECT
:
5231 case GLSL_SAMPLER_DIM_SUBPASS
:
5233 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5242 /* Adjust the sample index according to FMASK.
5244 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5245 * which is the identity mapping. Each nibble says which physical sample
5246 * should be fetched to get that sample.
5248 * For example, 0x11111100 means there are only 2 samples stored and
5249 * the second sample covers 3/4 of the pixel. When reading samples 0
5250 * and 1, return physical sample 0 (determined by the first two 0s
5251 * in FMASK), otherwise return physical sample 1.
5253 * The sample index should be adjusted as follows:
5254 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5256 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5258 Builder
bld(ctx
->program
, ctx
->block
);
5259 Temp fmask
= bld
.tmp(v1
);
5260 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5261 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5264 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5265 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5266 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5267 load
->operands
[0] = Operand(fmask_desc_ptr
);
5268 load
->operands
[1] = Operand(s4
); /* no sampler */
5269 load
->operands
[2] = Operand(coord
);
5270 load
->definitions
[0] = Definition(fmask
);
5277 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5278 ctx
->block
->instructions
.emplace_back(std::move(load
));
5280 Operand sample_index4
;
5281 if (sample_index
.isConstant() && sample_index
.constantValue() < 16) {
5282 sample_index4
= Operand(sample_index
.constantValue() << 2);
5283 } else if (sample_index
.regClass() == s1
) {
5284 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5286 assert(sample_index
.regClass() == v1
);
5287 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5291 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5292 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5293 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5294 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5296 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5298 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5299 * resource descriptor is 0 (invalid),
5301 Temp compare
= bld
.tmp(bld
.lm
);
5302 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5303 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5305 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5307 /* Replace the MSAA sample index. */
5308 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5311 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5314 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5315 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5316 bool is_array
= glsl_sampler_type_is_array(type
);
5317 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5318 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5319 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5320 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5321 int count
= image_type_to_components_count(dim
, is_array
);
5322 std::vector
<Temp
> coords(count
);
5323 Builder
bld(ctx
->program
, ctx
->block
);
5327 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5328 /* get sample index */
5329 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5330 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5331 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5332 std::vector
<Temp
> fmask_load_address
;
5333 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5334 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5336 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5337 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5339 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5344 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5345 coords
.resize(coords
.size() + 1);
5346 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5348 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5350 for (int i
= 0; i
< count
; i
++)
5351 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5354 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5355 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5356 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5357 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5360 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5363 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5364 for (unsigned i
= 0; i
< coords
.size(); i
++)
5365 vec
->operands
[i
] = Operand(coords
[i
]);
5366 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5367 vec
->definitions
[0] = Definition(res
);
5368 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5373 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5375 Builder
bld(ctx
->program
, ctx
->block
);
5376 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5377 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5378 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5379 bool is_array
= glsl_sampler_type_is_array(type
);
5380 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5382 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5383 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5384 unsigned num_channels
= util_last_bit(mask
);
5385 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5386 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5389 switch (num_channels
) {
5391 opcode
= aco_opcode::buffer_load_format_x
;
5394 opcode
= aco_opcode::buffer_load_format_xy
;
5397 opcode
= aco_opcode::buffer_load_format_xyz
;
5400 opcode
= aco_opcode::buffer_load_format_xyzw
;
5403 unreachable(">4 channel buffer image load");
5405 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5406 load
->operands
[0] = Operand(rsrc
);
5407 load
->operands
[1] = Operand(vindex
);
5408 load
->operands
[2] = Operand((uint32_t) 0);
5410 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5413 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5414 load
->definitions
[0] = Definition(tmp
);
5416 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5417 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5418 load
->barrier
= barrier_image
;
5419 ctx
->block
->instructions
.emplace_back(std::move(load
));
5421 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5425 Temp coords
= get_image_coords(ctx
, instr
, type
);
5426 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5428 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5429 unsigned num_components
= util_bitcount(dmask
);
5431 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5434 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5436 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5437 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5439 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5440 load
->operands
[0] = Operand(resource
);
5441 load
->operands
[1] = Operand(s4
); /* no sampler */
5442 load
->operands
[2] = Operand(coords
);
5443 load
->definitions
[0] = Definition(tmp
);
5444 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5445 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5446 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5447 load
->dmask
= dmask
;
5449 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5450 load
->barrier
= barrier_image
;
5451 ctx
->block
->instructions
.emplace_back(std::move(load
));
5453 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5457 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5459 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5460 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5461 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5462 bool is_array
= glsl_sampler_type_is_array(type
);
5463 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5465 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5467 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5468 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5469 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5471 switch (data
.size()) {
5473 opcode
= aco_opcode::buffer_store_format_x
;
5476 opcode
= aco_opcode::buffer_store_format_xy
;
5479 opcode
= aco_opcode::buffer_store_format_xyz
;
5482 opcode
= aco_opcode::buffer_store_format_xyzw
;
5485 unreachable(">4 channel buffer image store");
5487 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5488 store
->operands
[0] = Operand(rsrc
);
5489 store
->operands
[1] = Operand(vindex
);
5490 store
->operands
[2] = Operand((uint32_t) 0);
5491 store
->operands
[3] = Operand(data
);
5492 store
->idxen
= true;
5495 store
->disable_wqm
= true;
5496 store
->barrier
= barrier_image
;
5497 ctx
->program
->needs_exact
= true;
5498 ctx
->block
->instructions
.emplace_back(std::move(store
));
5502 assert(data
.type() == RegType::vgpr
);
5503 Temp coords
= get_image_coords(ctx
, instr
, type
);
5504 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5506 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5507 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5509 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5510 store
->operands
[0] = Operand(resource
);
5511 store
->operands
[1] = Operand(data
);
5512 store
->operands
[2] = Operand(coords
);
5515 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5516 store
->dmask
= (1 << data
.size()) - 1;
5518 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5519 store
->disable_wqm
= true;
5520 store
->barrier
= barrier_image
;
5521 ctx
->program
->needs_exact
= true;
5522 ctx
->block
->instructions
.emplace_back(std::move(store
));
5526 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5528 /* return the previous value if dest is ever used */
5529 bool return_previous
= false;
5530 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5531 return_previous
= true;
5534 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5535 return_previous
= true;
5539 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5540 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5541 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5542 bool is_array
= glsl_sampler_type_is_array(type
);
5543 Builder
bld(ctx
->program
, ctx
->block
);
5545 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5546 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5548 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5549 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5551 aco_opcode buf_op
, image_op
;
5552 switch (instr
->intrinsic
) {
5553 case nir_intrinsic_image_deref_atomic_add
:
5554 buf_op
= aco_opcode::buffer_atomic_add
;
5555 image_op
= aco_opcode::image_atomic_add
;
5557 case nir_intrinsic_image_deref_atomic_umin
:
5558 buf_op
= aco_opcode::buffer_atomic_umin
;
5559 image_op
= aco_opcode::image_atomic_umin
;
5561 case nir_intrinsic_image_deref_atomic_imin
:
5562 buf_op
= aco_opcode::buffer_atomic_smin
;
5563 image_op
= aco_opcode::image_atomic_smin
;
5565 case nir_intrinsic_image_deref_atomic_umax
:
5566 buf_op
= aco_opcode::buffer_atomic_umax
;
5567 image_op
= aco_opcode::image_atomic_umax
;
5569 case nir_intrinsic_image_deref_atomic_imax
:
5570 buf_op
= aco_opcode::buffer_atomic_smax
;
5571 image_op
= aco_opcode::image_atomic_smax
;
5573 case nir_intrinsic_image_deref_atomic_and
:
5574 buf_op
= aco_opcode::buffer_atomic_and
;
5575 image_op
= aco_opcode::image_atomic_and
;
5577 case nir_intrinsic_image_deref_atomic_or
:
5578 buf_op
= aco_opcode::buffer_atomic_or
;
5579 image_op
= aco_opcode::image_atomic_or
;
5581 case nir_intrinsic_image_deref_atomic_xor
:
5582 buf_op
= aco_opcode::buffer_atomic_xor
;
5583 image_op
= aco_opcode::image_atomic_xor
;
5585 case nir_intrinsic_image_deref_atomic_exchange
:
5586 buf_op
= aco_opcode::buffer_atomic_swap
;
5587 image_op
= aco_opcode::image_atomic_swap
;
5589 case nir_intrinsic_image_deref_atomic_comp_swap
:
5590 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5591 image_op
= aco_opcode::image_atomic_cmpswap
;
5594 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5597 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5599 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5600 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5601 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5602 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5603 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5604 mubuf
->operands
[0] = Operand(resource
);
5605 mubuf
->operands
[1] = Operand(vindex
);
5606 mubuf
->operands
[2] = Operand((uint32_t)0);
5607 mubuf
->operands
[3] = Operand(data
);
5608 if (return_previous
)
5609 mubuf
->definitions
[0] = Definition(dst
);
5611 mubuf
->idxen
= true;
5612 mubuf
->glc
= return_previous
;
5613 mubuf
->dlc
= false; /* Not needed for atomics */
5614 mubuf
->disable_wqm
= true;
5615 mubuf
->barrier
= barrier_image
;
5616 ctx
->program
->needs_exact
= true;
5617 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5621 Temp coords
= get_image_coords(ctx
, instr
, type
);
5622 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5623 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
5624 mimg
->operands
[0] = Operand(resource
);
5625 mimg
->operands
[1] = Operand(data
);
5626 mimg
->operands
[2] = Operand(coords
);
5627 if (return_previous
)
5628 mimg
->definitions
[0] = Definition(dst
);
5629 mimg
->glc
= return_previous
;
5630 mimg
->dlc
= false; /* Not needed for atomics */
5631 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5632 mimg
->dmask
= (1 << data
.size()) - 1;
5634 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5635 mimg
->disable_wqm
= true;
5636 mimg
->barrier
= barrier_image
;
5637 ctx
->program
->needs_exact
= true;
5638 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5642 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
5644 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
5645 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
5646 Builder
bld(ctx
->program
, ctx
->block
);
5648 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
5650 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
5651 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
5653 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
5654 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
5656 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
5657 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
5659 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
5660 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
5661 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
5662 if (dst
.type() == RegType::vgpr
)
5663 bld
.copy(Definition(dst
), shr_dst
);
5665 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
5667 emit_extract_vector(ctx
, desc
, 2, dst
);
5671 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5673 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5674 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5675 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5676 bool is_array
= glsl_sampler_type_is_array(type
);
5677 Builder
bld(ctx
->program
, ctx
->block
);
5679 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
5680 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
5681 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
5685 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
5688 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
5690 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5692 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
5693 mimg
->operands
[0] = Operand(resource
);
5694 mimg
->operands
[1] = Operand(s4
); /* no sampler */
5695 mimg
->operands
[2] = Operand(lod
);
5696 uint8_t& dmask
= mimg
->dmask
;
5697 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5698 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
5699 mimg
->da
= glsl_sampler_type_is_array(type
);
5700 mimg
->can_reorder
= true;
5701 Definition
& def
= mimg
->definitions
[0];
5702 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5704 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
5705 glsl_sampler_type_is_array(type
)) {
5707 assert(instr
->dest
.ssa
.num_components
== 3);
5708 Temp tmp
= {ctx
->program
->allocateId(), v3
};
5709 def
= Definition(tmp
);
5710 emit_split_vector(ctx
, tmp
, 3);
5712 /* divide 3rd value by 6 by multiplying with magic number */
5713 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
5714 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
5716 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5717 emit_extract_vector(ctx
, tmp
, 0, v1
),
5718 emit_extract_vector(ctx
, tmp
, 1, v1
),
5721 } else if (ctx
->options
->chip_class
== GFX9
&&
5722 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
5723 glsl_sampler_type_is_array(type
)) {
5724 assert(instr
->dest
.ssa
.num_components
== 2);
5725 def
= Definition(dst
);
5728 def
= Definition(dst
);
5731 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5734 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5736 Builder
bld(ctx
->program
, ctx
->block
);
5737 unsigned num_components
= instr
->num_components
;
5739 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5740 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5741 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5743 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5744 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5747 unsigned align_mul
= nir_intrinsic_align_mul(instr
);
5748 unsigned align_offset
= nir_intrinsic_align_offset(instr
);
5749 byte_align
= align_mul
% 4 == 0 ? align_offset
: -1;
5751 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), byte_align
, glc
, false);
5754 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5756 Builder
bld(ctx
->program
, ctx
->block
);
5757 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5758 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
5759 unsigned writemask
= nir_intrinsic_write_mask(instr
);
5760 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5762 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
5763 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5765 bool smem
= !ctx
->divergent_vals
[instr
->src
[2].ssa
->index
] &&
5766 ctx
->options
->chip_class
>= GFX8
&&
5767 elem_size_bytes
>= 4;
5769 offset
= bld
.as_uniform(offset
);
5770 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
5774 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
5775 if (count
== 3 && (smem
|| ctx
->options
->chip_class
== GFX6
)) {
5776 /* GFX6 doesn't support storing vec3, split it. */
5777 writemask
|= 1u << (start
+ 2);
5780 int num_bytes
= count
* elem_size_bytes
;
5782 /* dword or larger stores have to be dword-aligned */
5783 if (elem_size_bytes
< 4 && num_bytes
> 2) {
5784 // TODO: improve alignment check of sub-dword stores
5785 unsigned count_new
= 2 / elem_size_bytes
;
5786 writemask
|= ((1 << (count
- count_new
)) - 1) << (start
+ count_new
);
5791 if (num_bytes
> 16) {
5792 assert(elem_size_bytes
== 8);
5793 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
5799 if (elem_size_bytes
< 4) {
5800 if (data
.type() == RegType::sgpr
) {
5801 data
= as_vgpr(ctx
, data
);
5802 emit_split_vector(ctx
, data
, 4 * data
.size() / elem_size_bytes
);
5804 RegClass rc
= RegClass(RegType::vgpr
, elem_size_bytes
).as_subdword();
5805 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5806 for (int i
= 0; i
< count
; i
++)
5807 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, data
, start
+ i
, rc
));
5808 write_data
= bld
.tmp(RegClass(RegType::vgpr
, num_bytes
).as_subdword());
5809 vec
->definitions
[0] = Definition(write_data
);
5810 bld
.insert(std::move(vec
));
5811 } else if (count
!= instr
->num_components
) {
5812 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5813 for (int i
= 0; i
< count
; i
++) {
5814 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(data
.type(), elem_size_bytes
/ 4));
5815 vec
->operands
[i
] = Operand(smem_nonfs
? bld
.as_uniform(elem
) : elem
);
5817 write_data
= bld
.tmp(!smem
? RegType::vgpr
: smem_nonfs
? RegType::sgpr
: data
.type(), count
* elem_size_bytes
/ 4);
5818 vec
->definitions
[0] = Definition(write_data
);
5819 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5820 } else if (!smem
&& data
.type() != RegType::vgpr
) {
5821 assert(num_bytes
% 4 == 0);
5822 write_data
= bld
.copy(bld
.def(RegType::vgpr
, num_bytes
/ 4), data
);
5823 } else if (smem_nonfs
&& data
.type() == RegType::vgpr
) {
5824 assert(num_bytes
% 4 == 0);
5825 write_data
= bld
.as_uniform(data
);
5830 aco_opcode vmem_op
, smem_op
= aco_opcode::last_opcode
;
5831 switch (num_bytes
) {
5833 vmem_op
= aco_opcode::buffer_store_byte
;
5836 vmem_op
= aco_opcode::buffer_store_short
;
5839 vmem_op
= aco_opcode::buffer_store_dword
;
5840 smem_op
= aco_opcode::s_buffer_store_dword
;
5843 vmem_op
= aco_opcode::buffer_store_dwordx2
;
5844 smem_op
= aco_opcode::s_buffer_store_dwordx2
;
5847 vmem_op
= aco_opcode::buffer_store_dwordx3
;
5848 assert(!smem
&& ctx
->options
->chip_class
> GFX6
);
5851 vmem_op
= aco_opcode::buffer_store_dwordx4
;
5852 smem_op
= aco_opcode::s_buffer_store_dwordx4
;
5855 unreachable("Store SSBO not implemented for this size.");
5857 if (ctx
->stage
== fragment_fs
)
5858 smem_op
= aco_opcode::p_fs_buffer_store_smem
;
5861 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(smem_op
, Format::SMEM
, 3, 0)};
5862 store
->operands
[0] = Operand(rsrc
);
5864 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5865 offset
, Operand(start
* elem_size_bytes
));
5866 store
->operands
[1] = Operand(off
);
5868 store
->operands
[1] = Operand(offset
);
5870 if (smem_op
!= aco_opcode::p_fs_buffer_store_smem
)
5871 store
->operands
[1].setFixed(m0
);
5872 store
->operands
[2] = Operand(write_data
);
5873 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
5875 store
->disable_wqm
= true;
5876 store
->barrier
= barrier_buffer
;
5877 ctx
->block
->instructions
.emplace_back(std::move(store
));
5878 ctx
->program
->wb_smem_l1_on_end
= true;
5879 if (smem_op
== aco_opcode::p_fs_buffer_store_smem
) {
5880 ctx
->block
->kind
|= block_kind_needs_lowering
;
5881 ctx
->program
->needs_exact
= true;
5884 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(vmem_op
, Format::MUBUF
, 4, 0)};
5885 store
->operands
[0] = Operand(rsrc
);
5886 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
5887 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
5888 store
->operands
[3] = Operand(write_data
);
5889 store
->offset
= start
* elem_size_bytes
;
5890 store
->offen
= (offset
.type() == RegType::vgpr
);
5891 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
5893 store
->disable_wqm
= true;
5894 store
->barrier
= barrier_buffer
;
5895 ctx
->program
->needs_exact
= true;
5896 ctx
->block
->instructions
.emplace_back(std::move(store
));
5901 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5903 /* return the previous value if dest is ever used */
5904 bool return_previous
= false;
5905 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5906 return_previous
= true;
5909 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5910 return_previous
= true;
5914 Builder
bld(ctx
->program
, ctx
->block
);
5915 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
5917 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
5918 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
5919 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
5921 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5922 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5923 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5925 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5927 aco_opcode op32
, op64
;
5928 switch (instr
->intrinsic
) {
5929 case nir_intrinsic_ssbo_atomic_add
:
5930 op32
= aco_opcode::buffer_atomic_add
;
5931 op64
= aco_opcode::buffer_atomic_add_x2
;
5933 case nir_intrinsic_ssbo_atomic_imin
:
5934 op32
= aco_opcode::buffer_atomic_smin
;
5935 op64
= aco_opcode::buffer_atomic_smin_x2
;
5937 case nir_intrinsic_ssbo_atomic_umin
:
5938 op32
= aco_opcode::buffer_atomic_umin
;
5939 op64
= aco_opcode::buffer_atomic_umin_x2
;
5941 case nir_intrinsic_ssbo_atomic_imax
:
5942 op32
= aco_opcode::buffer_atomic_smax
;
5943 op64
= aco_opcode::buffer_atomic_smax_x2
;
5945 case nir_intrinsic_ssbo_atomic_umax
:
5946 op32
= aco_opcode::buffer_atomic_umax
;
5947 op64
= aco_opcode::buffer_atomic_umax_x2
;
5949 case nir_intrinsic_ssbo_atomic_and
:
5950 op32
= aco_opcode::buffer_atomic_and
;
5951 op64
= aco_opcode::buffer_atomic_and_x2
;
5953 case nir_intrinsic_ssbo_atomic_or
:
5954 op32
= aco_opcode::buffer_atomic_or
;
5955 op64
= aco_opcode::buffer_atomic_or_x2
;
5957 case nir_intrinsic_ssbo_atomic_xor
:
5958 op32
= aco_opcode::buffer_atomic_xor
;
5959 op64
= aco_opcode::buffer_atomic_xor_x2
;
5961 case nir_intrinsic_ssbo_atomic_exchange
:
5962 op32
= aco_opcode::buffer_atomic_swap
;
5963 op64
= aco_opcode::buffer_atomic_swap_x2
;
5965 case nir_intrinsic_ssbo_atomic_comp_swap
:
5966 op32
= aco_opcode::buffer_atomic_cmpswap
;
5967 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
5970 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
5972 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
5973 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5974 mubuf
->operands
[0] = Operand(rsrc
);
5975 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
5976 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
5977 mubuf
->operands
[3] = Operand(data
);
5978 if (return_previous
)
5979 mubuf
->definitions
[0] = Definition(dst
);
5981 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
5982 mubuf
->glc
= return_previous
;
5983 mubuf
->dlc
= false; /* Not needed for atomics */
5984 mubuf
->disable_wqm
= true;
5985 mubuf
->barrier
= barrier_buffer
;
5986 ctx
->program
->needs_exact
= true;
5987 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5990 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
5992 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5993 Builder
bld(ctx
->program
, ctx
->block
);
5994 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
5995 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
5998 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
6000 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6001 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6003 if (addr
.type() == RegType::vgpr
)
6004 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
6005 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
6008 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6010 Builder
bld(ctx
->program
, ctx
->block
);
6011 unsigned num_components
= instr
->num_components
;
6012 unsigned num_bytes
= num_components
* instr
->dest
.ssa
.bit_size
/ 8;
6014 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6015 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6017 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6018 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
6020 if (dst
.type() == RegType::vgpr
|| (glc
&& ctx
->options
->chip_class
< GFX8
)) {
6021 bool global
= ctx
->options
->chip_class
>= GFX9
;
6023 if (ctx
->options
->chip_class
>= GFX7
) {
6025 switch (num_bytes
) {
6027 op
= global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
6030 op
= global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
6033 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
6036 op
= global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
6039 unreachable("load_global not implemented for this size.");
6042 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
6043 flat
->operands
[0] = Operand(addr
);
6044 flat
->operands
[1] = Operand(s1
);
6047 flat
->barrier
= barrier_buffer
;
6049 if (dst
.type() == RegType::sgpr
) {
6050 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
6051 flat
->definitions
[0] = Definition(vec
);
6052 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6053 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
6055 flat
->definitions
[0] = Definition(dst
);
6056 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6058 emit_split_vector(ctx
, dst
, num_components
);
6060 assert(ctx
->options
->chip_class
== GFX6
);
6062 /* GFX6 doesn't support loading vec3, expand to vec4. */
6063 num_bytes
= num_bytes
== 12 ? 16 : num_bytes
;
6066 switch (num_bytes
) {
6068 op
= aco_opcode::buffer_load_dword
;
6071 op
= aco_opcode::buffer_load_dwordx2
;
6074 op
= aco_opcode::buffer_load_dwordx4
;
6077 unreachable("load_global not implemented for this size.");
6080 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6082 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
6083 mubuf
->operands
[0] = Operand(rsrc
);
6084 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6085 mubuf
->operands
[2] = Operand(0u);
6089 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6090 mubuf
->disable_wqm
= false;
6091 mubuf
->barrier
= barrier_buffer
;
6092 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
6095 if (dst
.size() == 3) {
6096 Temp vec
= bld
.tmp(v4
);
6097 instr
->definitions
[0] = Definition(vec
);
6098 bld
.insert(std::move(instr
));
6099 emit_split_vector(ctx
, vec
, 4);
6101 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 3, 1));
6102 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, vec
, 0, v1
));
6103 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, vec
, 1, v1
));
6104 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, vec
, 2, v1
));
6107 if (dst
.type() == RegType::sgpr
) {
6108 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
6109 instr
->definitions
[0] = Definition(vec
);
6110 bld
.insert(std::move(instr
));
6111 expand_vector(ctx
, vec
, dst
, num_components
, (1 << num_components
) - 1);
6112 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
6114 instr
->definitions
[0] = Definition(dst
);
6115 bld
.insert(std::move(instr
));
6116 emit_split_vector(ctx
, dst
, num_components
);
6120 switch (num_bytes
) {
6122 op
= aco_opcode::s_load_dword
;
6125 op
= aco_opcode::s_load_dwordx2
;
6129 op
= aco_opcode::s_load_dwordx4
;
6132 unreachable("load_global not implemented for this size.");
6134 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
6135 load
->operands
[0] = Operand(addr
);
6136 load
->operands
[1] = Operand(0u);
6137 load
->definitions
[0] = Definition(dst
);
6140 load
->barrier
= barrier_buffer
;
6141 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
6143 if (dst
.size() == 3) {
6145 Temp vec
= bld
.tmp(s4
);
6146 load
->definitions
[0] = Definition(vec
);
6147 ctx
->block
->instructions
.emplace_back(std::move(load
));
6148 emit_split_vector(ctx
, vec
, 4);
6150 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6151 emit_extract_vector(ctx
, vec
, 0, s1
),
6152 emit_extract_vector(ctx
, vec
, 1, s1
),
6153 emit_extract_vector(ctx
, vec
, 2, s1
));
6155 ctx
->block
->instructions
.emplace_back(std::move(load
));
6160 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6162 Builder
bld(ctx
->program
, ctx
->block
);
6163 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6165 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6166 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6168 if (ctx
->options
->chip_class
>= GFX7
)
6169 addr
= as_vgpr(ctx
, addr
);
6171 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6174 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
6175 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
6176 /* GFX6 doesn't support storing vec3, split it. */
6177 writemask
|= 1u << (start
+ 2);
6180 unsigned num_bytes
= count
* elem_size_bytes
;
6182 Temp write_data
= data
;
6183 if (count
!= instr
->num_components
) {
6184 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6185 for (int i
= 0; i
< count
; i
++)
6186 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, data
, start
+ i
, v1
));
6187 write_data
= bld
.tmp(RegType::vgpr
, count
);
6188 vec
->definitions
[0] = Definition(write_data
);
6189 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6192 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6193 unsigned offset
= start
* elem_size_bytes
;
6195 if (ctx
->options
->chip_class
>= GFX7
) {
6196 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6197 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6198 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6199 Temp carry
= bld
.tmp(bld
.lm
);
6200 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6202 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6203 Operand(offset
), addr0
);
6204 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6206 carry
).def(1).setHint(vcc
);
6208 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6213 bool global
= ctx
->options
->chip_class
>= GFX9
;
6215 switch (num_bytes
) {
6217 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6220 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6223 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6226 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6229 unreachable("store_global not implemented for this size.");
6232 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6233 flat
->operands
[0] = Operand(addr
);
6234 flat
->operands
[1] = Operand(s1
);
6235 flat
->operands
[2] = Operand(data
);
6238 flat
->offset
= offset
;
6239 flat
->disable_wqm
= true;
6240 flat
->barrier
= barrier_buffer
;
6241 ctx
->program
->needs_exact
= true;
6242 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6244 assert(ctx
->options
->chip_class
== GFX6
);
6247 switch (num_bytes
) {
6249 op
= aco_opcode::buffer_store_dword
;
6252 op
= aco_opcode::buffer_store_dwordx2
;
6255 op
= aco_opcode::buffer_store_dwordx4
;
6258 unreachable("store_global not implemented for this size.");
6261 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6263 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6264 mubuf
->operands
[0] = Operand(rsrc
);
6265 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6266 mubuf
->operands
[2] = Operand(0u);
6267 mubuf
->operands
[3] = Operand(write_data
);
6270 mubuf
->offset
= offset
;
6271 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6272 mubuf
->disable_wqm
= true;
6273 mubuf
->barrier
= barrier_buffer
;
6274 ctx
->program
->needs_exact
= true;
6275 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6280 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6282 /* return the previous value if dest is ever used */
6283 bool return_previous
= false;
6284 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6285 return_previous
= true;
6288 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6289 return_previous
= true;
6293 Builder
bld(ctx
->program
, ctx
->block
);
6294 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6295 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6297 if (ctx
->options
->chip_class
>= GFX7
)
6298 addr
= as_vgpr(ctx
, addr
);
6300 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6301 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6302 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6304 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6306 aco_opcode op32
, op64
;
6308 if (ctx
->options
->chip_class
>= GFX7
) {
6309 bool global
= ctx
->options
->chip_class
>= GFX9
;
6310 switch (instr
->intrinsic
) {
6311 case nir_intrinsic_global_atomic_add
:
6312 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6313 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6315 case nir_intrinsic_global_atomic_imin
:
6316 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6317 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6319 case nir_intrinsic_global_atomic_umin
:
6320 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6321 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6323 case nir_intrinsic_global_atomic_imax
:
6324 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6325 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6327 case nir_intrinsic_global_atomic_umax
:
6328 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6329 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6331 case nir_intrinsic_global_atomic_and
:
6332 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6333 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6335 case nir_intrinsic_global_atomic_or
:
6336 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6337 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6339 case nir_intrinsic_global_atomic_xor
:
6340 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6341 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6343 case nir_intrinsic_global_atomic_exchange
:
6344 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6345 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6347 case nir_intrinsic_global_atomic_comp_swap
:
6348 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6349 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6352 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6355 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6356 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6357 flat
->operands
[0] = Operand(addr
);
6358 flat
->operands
[1] = Operand(s1
);
6359 flat
->operands
[2] = Operand(data
);
6360 if (return_previous
)
6361 flat
->definitions
[0] = Definition(dst
);
6362 flat
->glc
= return_previous
;
6363 flat
->dlc
= false; /* Not needed for atomics */
6365 flat
->disable_wqm
= true;
6366 flat
->barrier
= barrier_buffer
;
6367 ctx
->program
->needs_exact
= true;
6368 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6370 assert(ctx
->options
->chip_class
== GFX6
);
6372 switch (instr
->intrinsic
) {
6373 case nir_intrinsic_global_atomic_add
:
6374 op32
= aco_opcode::buffer_atomic_add
;
6375 op64
= aco_opcode::buffer_atomic_add_x2
;
6377 case nir_intrinsic_global_atomic_imin
:
6378 op32
= aco_opcode::buffer_atomic_smin
;
6379 op64
= aco_opcode::buffer_atomic_smin_x2
;
6381 case nir_intrinsic_global_atomic_umin
:
6382 op32
= aco_opcode::buffer_atomic_umin
;
6383 op64
= aco_opcode::buffer_atomic_umin_x2
;
6385 case nir_intrinsic_global_atomic_imax
:
6386 op32
= aco_opcode::buffer_atomic_smax
;
6387 op64
= aco_opcode::buffer_atomic_smax_x2
;
6389 case nir_intrinsic_global_atomic_umax
:
6390 op32
= aco_opcode::buffer_atomic_umax
;
6391 op64
= aco_opcode::buffer_atomic_umax_x2
;
6393 case nir_intrinsic_global_atomic_and
:
6394 op32
= aco_opcode::buffer_atomic_and
;
6395 op64
= aco_opcode::buffer_atomic_and_x2
;
6397 case nir_intrinsic_global_atomic_or
:
6398 op32
= aco_opcode::buffer_atomic_or
;
6399 op64
= aco_opcode::buffer_atomic_or_x2
;
6401 case nir_intrinsic_global_atomic_xor
:
6402 op32
= aco_opcode::buffer_atomic_xor
;
6403 op64
= aco_opcode::buffer_atomic_xor_x2
;
6405 case nir_intrinsic_global_atomic_exchange
:
6406 op32
= aco_opcode::buffer_atomic_swap
;
6407 op64
= aco_opcode::buffer_atomic_swap_x2
;
6409 case nir_intrinsic_global_atomic_comp_swap
:
6410 op32
= aco_opcode::buffer_atomic_cmpswap
;
6411 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6414 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6417 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6419 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6421 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6422 mubuf
->operands
[0] = Operand(rsrc
);
6423 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6424 mubuf
->operands
[2] = Operand(0u);
6425 mubuf
->operands
[3] = Operand(data
);
6426 if (return_previous
)
6427 mubuf
->definitions
[0] = Definition(dst
);
6428 mubuf
->glc
= return_previous
;
6431 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6432 mubuf
->disable_wqm
= true;
6433 mubuf
->barrier
= barrier_buffer
;
6434 ctx
->program
->needs_exact
= true;
6435 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6439 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6440 Builder
bld(ctx
->program
, ctx
->block
);
6441 switch(instr
->intrinsic
) {
6442 case nir_intrinsic_group_memory_barrier
:
6443 case nir_intrinsic_memory_barrier
:
6444 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6446 case nir_intrinsic_memory_barrier_buffer
:
6447 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6449 case nir_intrinsic_memory_barrier_image
:
6450 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6452 case nir_intrinsic_memory_barrier_tcs_patch
:
6453 case nir_intrinsic_memory_barrier_shared
:
6454 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6457 unreachable("Unimplemented memory barrier intrinsic");
6462 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6464 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6465 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6466 assert(instr
->dest
.ssa
.bit_size
>= 32 && "Bitsize not supported in load_shared.");
6467 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6468 Builder
bld(ctx
->program
, ctx
->block
);
6470 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6471 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6472 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6475 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6477 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6478 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6479 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6480 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6481 assert(elem_size_bytes
>= 4 && "Only 32bit & 64bit store_shared currently supported.");
6483 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6484 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6487 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6489 unsigned offset
= nir_intrinsic_base(instr
);
6490 Operand m
= load_lds_size_m0(ctx
);
6491 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6492 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6494 unsigned num_operands
= 3;
6495 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6496 switch(instr
->intrinsic
) {
6497 case nir_intrinsic_shared_atomic_add
:
6498 op32
= aco_opcode::ds_add_u32
;
6499 op64
= aco_opcode::ds_add_u64
;
6500 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6501 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6503 case nir_intrinsic_shared_atomic_imin
:
6504 op32
= aco_opcode::ds_min_i32
;
6505 op64
= aco_opcode::ds_min_i64
;
6506 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6507 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6509 case nir_intrinsic_shared_atomic_umin
:
6510 op32
= aco_opcode::ds_min_u32
;
6511 op64
= aco_opcode::ds_min_u64
;
6512 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6513 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6515 case nir_intrinsic_shared_atomic_imax
:
6516 op32
= aco_opcode::ds_max_i32
;
6517 op64
= aco_opcode::ds_max_i64
;
6518 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6519 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6521 case nir_intrinsic_shared_atomic_umax
:
6522 op32
= aco_opcode::ds_max_u32
;
6523 op64
= aco_opcode::ds_max_u64
;
6524 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6525 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6527 case nir_intrinsic_shared_atomic_and
:
6528 op32
= aco_opcode::ds_and_b32
;
6529 op64
= aco_opcode::ds_and_b64
;
6530 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6531 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6533 case nir_intrinsic_shared_atomic_or
:
6534 op32
= aco_opcode::ds_or_b32
;
6535 op64
= aco_opcode::ds_or_b64
;
6536 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6537 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6539 case nir_intrinsic_shared_atomic_xor
:
6540 op32
= aco_opcode::ds_xor_b32
;
6541 op64
= aco_opcode::ds_xor_b64
;
6542 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6543 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6545 case nir_intrinsic_shared_atomic_exchange
:
6546 op32
= aco_opcode::ds_write_b32
;
6547 op64
= aco_opcode::ds_write_b64
;
6548 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6549 op64_rtn
= aco_opcode::ds_wrxchg2_rtn_b64
;
6551 case nir_intrinsic_shared_atomic_comp_swap
:
6552 op32
= aco_opcode::ds_cmpst_b32
;
6553 op64
= aco_opcode::ds_cmpst_b64
;
6554 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6555 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6559 unreachable("Unhandled shared atomic intrinsic");
6562 /* return the previous value if dest is ever used */
6563 bool return_previous
= false;
6564 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6565 return_previous
= true;
6568 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6569 return_previous
= true;
6574 if (data
.size() == 1) {
6575 assert(instr
->dest
.ssa
.bit_size
== 32);
6576 op
= return_previous
? op32_rtn
: op32
;
6578 assert(instr
->dest
.ssa
.bit_size
== 64);
6579 op
= return_previous
? op64_rtn
: op64
;
6582 if (offset
> 65535) {
6583 Builder
bld(ctx
->program
, ctx
->block
);
6584 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6588 aco_ptr
<DS_instruction
> ds
;
6589 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6590 ds
->operands
[0] = Operand(address
);
6591 ds
->operands
[1] = Operand(data
);
6592 if (num_operands
== 4)
6593 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6594 ds
->operands
[num_operands
- 1] = m
;
6595 ds
->offset0
= offset
;
6596 if (return_previous
)
6597 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6598 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6601 Temp
get_scratch_resource(isel_context
*ctx
)
6603 Builder
bld(ctx
->program
, ctx
->block
);
6604 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6605 if (ctx
->stage
!= compute_cs
)
6606 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6608 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6609 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6611 if (ctx
->program
->chip_class
>= GFX10
) {
6612 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6613 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6614 S_008F0C_RESOURCE_LEVEL(1);
6615 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6616 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6617 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6620 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6621 if (ctx
->program
->chip_class
<= GFX8
)
6622 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6624 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6627 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6628 assert(instr
->dest
.ssa
.bit_size
== 32 || instr
->dest
.ssa
.bit_size
== 64);
6629 Builder
bld(ctx
->program
, ctx
->block
);
6630 Temp rsrc
= get_scratch_resource(ctx
);
6631 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6632 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6635 switch (dst
.size()) {
6637 op
= aco_opcode::buffer_load_dword
;
6640 op
= aco_opcode::buffer_load_dwordx2
;
6643 op
= aco_opcode::buffer_load_dwordx3
;
6646 op
= aco_opcode::buffer_load_dwordx4
;
6650 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
6651 Temp lower
= bld
.mubuf(aco_opcode::buffer_load_dwordx4
,
6652 bld
.def(v4
), rsrc
, offset
,
6653 ctx
->program
->scratch_offset
, 0, true);
6654 Temp upper
= bld
.mubuf(dst
.size() == 6 ? aco_opcode::buffer_load_dwordx2
:
6655 aco_opcode::buffer_load_dwordx4
,
6656 dst
.size() == 6 ? bld
.def(v2
) : bld
.def(v4
),
6657 rsrc
, offset
, ctx
->program
->scratch_offset
, 16, true);
6658 emit_split_vector(ctx
, lower
, 2);
6659 elems
[0] = emit_extract_vector(ctx
, lower
, 0, v2
);
6660 elems
[1] = emit_extract_vector(ctx
, lower
, 1, v2
);
6661 if (dst
.size() == 8) {
6662 emit_split_vector(ctx
, upper
, 2);
6663 elems
[2] = emit_extract_vector(ctx
, upper
, 0, v2
);
6664 elems
[3] = emit_extract_vector(ctx
, upper
, 1, v2
);
6669 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
6670 Format::PSEUDO
, dst
.size() / 2, 1)};
6671 for (unsigned i
= 0; i
< dst
.size() / 2; i
++)
6672 vec
->operands
[i
] = Operand(elems
[i
]);
6673 vec
->definitions
[0] = Definition(dst
);
6674 bld
.insert(std::move(vec
));
6675 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
6679 unreachable("Wrong dst size for nir_intrinsic_load_scratch");
6682 bld
.mubuf(op
, Definition(dst
), rsrc
, offset
, ctx
->program
->scratch_offset
, 0, true);
6683 emit_split_vector(ctx
, dst
, instr
->num_components
);
6686 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6687 assert(instr
->src
[0].ssa
->bit_size
== 32 || instr
->src
[0].ssa
->bit_size
== 64);
6688 Builder
bld(ctx
->program
, ctx
->block
);
6689 Temp rsrc
= get_scratch_resource(ctx
);
6690 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6691 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6693 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6694 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6698 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
6699 int num_bytes
= count
* elem_size_bytes
;
6701 if (num_bytes
> 16) {
6702 assert(elem_size_bytes
== 8);
6703 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
6708 // TODO: check alignment of sub-dword stores
6709 // TODO: split 3 bytes. there is no store instruction for that
6712 if (count
!= instr
->num_components
) {
6713 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6714 for (int i
= 0; i
< count
; i
++) {
6715 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(RegType::vgpr
, elem_size_bytes
/ 4));
6716 vec
->operands
[i
] = Operand(elem
);
6718 write_data
= bld
.tmp(RegClass(RegType::vgpr
, count
* elem_size_bytes
/ 4));
6719 vec
->definitions
[0] = Definition(write_data
);
6720 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6726 switch (num_bytes
) {
6728 op
= aco_opcode::buffer_store_dword
;
6731 op
= aco_opcode::buffer_store_dwordx2
;
6734 op
= aco_opcode::buffer_store_dwordx3
;
6737 op
= aco_opcode::buffer_store_dwordx4
;
6740 unreachable("Invalid data size for nir_intrinsic_store_scratch.");
6743 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_data
, start
* elem_size_bytes
, true);
6747 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6748 uint8_t log2_ps_iter_samples
;
6749 if (ctx
->program
->info
->ps
.force_persample
) {
6750 log2_ps_iter_samples
=
6751 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6753 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6756 /* The bit pattern matches that used by fixed function fragment
6758 static const unsigned ps_iter_masks
[] = {
6759 0xffff, /* not used */
6765 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6767 Builder
bld(ctx
->program
, ctx
->block
);
6769 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6770 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6771 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6772 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6773 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6774 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6777 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6778 Builder
bld(ctx
->program
, ctx
->block
);
6780 unsigned stream
= nir_intrinsic_stream_id(instr
);
6781 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6782 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6783 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6786 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6788 unsigned num_components
=
6789 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6790 assert(num_components
);
6792 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6793 unsigned stream_offset
= 0;
6794 for (unsigned i
= 0; i
< stream
; i
++) {
6795 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6796 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6799 /* Limit on the stride field for <= GFX7. */
6800 assert(stride
< (1 << 14));
6802 Temp gsvs_dwords
[4];
6803 for (unsigned i
= 0; i
< 4; i
++)
6804 gsvs_dwords
[i
] = bld
.tmp(s1
);
6805 bld
.pseudo(aco_opcode::p_split_vector
,
6806 Definition(gsvs_dwords
[0]),
6807 Definition(gsvs_dwords
[1]),
6808 Definition(gsvs_dwords
[2]),
6809 Definition(gsvs_dwords
[3]),
6812 if (stream_offset
) {
6813 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6815 Temp carry
= bld
.tmp(s1
);
6816 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6817 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6820 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6821 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6823 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6824 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6826 unsigned offset
= 0;
6827 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6828 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6831 for (unsigned j
= 0; j
< 4; j
++) {
6832 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6835 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6836 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6837 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6838 if (const_offset
>= 4096u) {
6839 if (vaddr_offset
.isUndefined())
6840 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6842 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6843 const_offset
%= 4096u;
6846 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6847 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6848 mtbuf
->operands
[1] = vaddr_offset
;
6849 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6850 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6851 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6852 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6853 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6854 mtbuf
->offset
= const_offset
;
6857 mtbuf
->barrier
= barrier_gs_data
;
6858 mtbuf
->can_reorder
= true;
6859 bld
.insert(std::move(mtbuf
));
6862 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6865 /* outputs for the next vertex are undefined and keeping them around can
6866 * create invalid IR with control flow */
6867 ctx
->outputs
.mask
[i
] = 0;
6870 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6873 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6875 Builder
bld(ctx
->program
, ctx
->block
);
6877 if (cluster_size
== 1) {
6879 } if (op
== nir_op_iand
&& cluster_size
== 4) {
6880 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6881 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6882 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6883 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
6884 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
6885 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6886 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6887 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
6888 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
6889 //subgroupAnd(val) -> (exec & ~val) == 0
6890 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
6891 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
6892 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
6893 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
6894 //subgroupOr(val) -> (val & exec) != 0
6895 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
6896 return bool_to_vector_condition(ctx
, tmp
);
6897 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
6898 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6899 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6900 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
6901 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
6902 return bool_to_vector_condition(ctx
, tmp
);
6904 //subgroupClustered{And,Or,Xor}(val, n) ->
6905 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
6906 //cluster_offset = ~(n - 1) & lane_id
6907 //cluster_mask = ((1 << n) - 1)
6908 //subgroupClusteredAnd():
6909 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6910 //subgroupClusteredOr():
6911 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
6912 //subgroupClusteredXor():
6913 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6914 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
6915 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
6918 if (op
== nir_op_iand
)
6919 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6921 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6923 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
6925 if (ctx
->program
->chip_class
<= GFX7
)
6926 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
6927 else if (ctx
->program
->wave_size
== 64)
6928 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
6930 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
6931 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
6932 if (cluster_mask
!= 0xffffffff)
6933 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
6935 Definition cmp_def
= Definition();
6936 if (op
== nir_op_iand
) {
6937 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
6938 } else if (op
== nir_op_ior
) {
6939 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6940 } else if (op
== nir_op_ixor
) {
6941 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
6942 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
6943 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6945 cmp_def
.setHint(vcc
);
6946 return cmp_def
.getTemp();
6950 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
6952 Builder
bld(ctx
->program
, ctx
->block
);
6954 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
6955 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
6956 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
6958 if (op
== nir_op_iand
)
6959 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6961 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6963 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
6964 Temp lo
= lohi
.def(0).getTemp();
6965 Temp hi
= lohi
.def(1).getTemp();
6966 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
6968 Definition cmp_def
= Definition();
6969 if (op
== nir_op_iand
)
6970 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
6971 else if (op
== nir_op_ior
)
6972 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
6973 else if (op
== nir_op_ixor
)
6974 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
6975 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
6976 cmp_def
.setHint(vcc
);
6977 return cmp_def
.getTemp();
6980 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
6982 Builder
bld(ctx
->program
, ctx
->block
);
6984 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
6985 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
6986 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
6987 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
6988 if (op
== nir_op_iand
)
6989 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
6990 else if (op
== nir_op_ior
)
6991 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
6992 else if (op
== nir_op_ixor
)
6993 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
6999 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7001 Builder
bld(ctx
->program
, ctx
->block
);
7002 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7003 if (src
.regClass().type() == RegType::vgpr
) {
7004 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7005 } else if (src
.regClass() == s1
) {
7006 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7007 } else if (src
.regClass() == s2
) {
7008 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7010 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7011 nir_print_instr(&instr
->instr
, stderr
);
7012 fprintf(stderr
, "\n");
7016 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7018 Builder
bld(ctx
->program
, ctx
->block
);
7019 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7020 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7021 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7023 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7024 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7025 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7026 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7029 if (ctx
->program
->chip_class
>= GFX8
) {
7030 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7031 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7032 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7033 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7034 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7035 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7037 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7038 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7039 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7040 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7041 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7042 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7043 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7044 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7045 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7046 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7049 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7050 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7051 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7052 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7053 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7054 Temp wqm1
= bld
.tmp(v1
);
7055 emit_wqm(ctx
, tmp1
, wqm1
, true);
7056 Temp wqm2
= bld
.tmp(v1
);
7057 emit_wqm(ctx
, tmp2
, wqm2
, true);
7058 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7062 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7064 Builder
bld(ctx
->program
, ctx
->block
);
7065 switch(instr
->intrinsic
) {
7066 case nir_intrinsic_load_barycentric_sample
:
7067 case nir_intrinsic_load_barycentric_pixel
:
7068 case nir_intrinsic_load_barycentric_centroid
: {
7069 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7070 Temp bary
= Temp(0, s2
);
7072 case INTERP_MODE_SMOOTH
:
7073 case INTERP_MODE_NONE
:
7074 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7075 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7076 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7077 bary
= ctx
->persp_centroid
;
7078 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7079 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7081 case INTERP_MODE_NOPERSPECTIVE
:
7082 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7083 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7084 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7085 bary
= ctx
->linear_centroid
;
7086 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7087 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7092 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7093 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7094 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7095 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7096 Operand(p1
), Operand(p2
));
7097 emit_split_vector(ctx
, dst
, 2);
7100 case nir_intrinsic_load_barycentric_model
: {
7101 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7103 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7104 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7105 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7106 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7107 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7108 Operand(p1
), Operand(p2
), Operand(p3
));
7109 emit_split_vector(ctx
, dst
, 3);
7112 case nir_intrinsic_load_barycentric_at_sample
: {
7113 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7114 switch (ctx
->options
->key
.fs
.num_samples
) {
7115 case 2: sample_pos_offset
+= 1 << 3; break;
7116 case 4: sample_pos_offset
+= 3 << 3; break;
7117 case 8: sample_pos_offset
+= 7 << 3; break;
7121 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7122 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7123 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7124 if (addr
.type() == RegType::sgpr
) {
7127 sample_pos_offset
+= const_addr
->u32
<< 3;
7128 offset
= Operand(sample_pos_offset
);
7129 } else if (ctx
->options
->chip_class
>= GFX9
) {
7130 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7132 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7133 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7136 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7137 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7139 } else if (ctx
->options
->chip_class
>= GFX9
) {
7140 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7141 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7142 } else if (ctx
->options
->chip_class
>= GFX7
) {
7143 /* addr += private_segment_buffer + sample_pos_offset */
7144 Temp tmp0
= bld
.tmp(s1
);
7145 Temp tmp1
= bld
.tmp(s1
);
7146 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7147 Definition scc_tmp
= bld
.def(s1
, scc
);
7148 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7149 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7150 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7151 Temp pck0
= bld
.tmp(v1
);
7152 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7153 tmp1
= as_vgpr(ctx
, tmp1
);
7154 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7155 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7157 /* sample_pos = flat_load_dwordx2 addr */
7158 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7160 assert(ctx
->options
->chip_class
== GFX6
);
7162 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7163 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7164 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7166 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7167 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7169 sample_pos
= bld
.tmp(v2
);
7171 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7172 load
->definitions
[0] = Definition(sample_pos
);
7173 load
->operands
[0] = Operand(rsrc
);
7174 load
->operands
[1] = Operand(addr
);
7175 load
->operands
[2] = Operand(0u);
7176 load
->offset
= sample_pos_offset
;
7178 load
->addr64
= true;
7181 load
->disable_wqm
= false;
7182 load
->barrier
= barrier_none
;
7183 load
->can_reorder
= true;
7184 ctx
->block
->instructions
.emplace_back(std::move(load
));
7187 /* sample_pos -= 0.5 */
7188 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7189 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7190 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7191 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7192 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7194 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7197 case nir_intrinsic_load_barycentric_at_offset
: {
7198 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7199 RegClass rc
= RegClass(offset
.type(), 1);
7200 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7201 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7202 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7205 case nir_intrinsic_load_front_face
: {
7206 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7207 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7210 case nir_intrinsic_load_view_index
: {
7211 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7212 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7213 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7219 case nir_intrinsic_load_layer_id
: {
7220 unsigned idx
= nir_intrinsic_base(instr
);
7221 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7222 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7225 case nir_intrinsic_load_frag_coord
: {
7226 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7229 case nir_intrinsic_load_sample_pos
: {
7230 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7231 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7232 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7233 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7234 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7237 case nir_intrinsic_load_tess_coord
:
7238 visit_load_tess_coord(ctx
, instr
);
7240 case nir_intrinsic_load_interpolated_input
:
7241 visit_load_interpolated_input(ctx
, instr
);
7243 case nir_intrinsic_store_output
:
7244 visit_store_output(ctx
, instr
);
7246 case nir_intrinsic_load_input
:
7247 case nir_intrinsic_load_input_vertex
:
7248 visit_load_input(ctx
, instr
);
7250 case nir_intrinsic_load_output
:
7251 visit_load_output(ctx
, instr
);
7253 case nir_intrinsic_load_per_vertex_input
:
7254 visit_load_per_vertex_input(ctx
, instr
);
7256 case nir_intrinsic_load_per_vertex_output
:
7257 visit_load_per_vertex_output(ctx
, instr
);
7259 case nir_intrinsic_store_per_vertex_output
:
7260 visit_store_per_vertex_output(ctx
, instr
);
7262 case nir_intrinsic_load_ubo
:
7263 visit_load_ubo(ctx
, instr
);
7265 case nir_intrinsic_load_push_constant
:
7266 visit_load_push_constant(ctx
, instr
);
7268 case nir_intrinsic_load_constant
:
7269 visit_load_constant(ctx
, instr
);
7271 case nir_intrinsic_vulkan_resource_index
:
7272 visit_load_resource(ctx
, instr
);
7274 case nir_intrinsic_discard
:
7275 visit_discard(ctx
, instr
);
7277 case nir_intrinsic_discard_if
:
7278 visit_discard_if(ctx
, instr
);
7280 case nir_intrinsic_load_shared
:
7281 visit_load_shared(ctx
, instr
);
7283 case nir_intrinsic_store_shared
:
7284 visit_store_shared(ctx
, instr
);
7286 case nir_intrinsic_shared_atomic_add
:
7287 case nir_intrinsic_shared_atomic_imin
:
7288 case nir_intrinsic_shared_atomic_umin
:
7289 case nir_intrinsic_shared_atomic_imax
:
7290 case nir_intrinsic_shared_atomic_umax
:
7291 case nir_intrinsic_shared_atomic_and
:
7292 case nir_intrinsic_shared_atomic_or
:
7293 case nir_intrinsic_shared_atomic_xor
:
7294 case nir_intrinsic_shared_atomic_exchange
:
7295 case nir_intrinsic_shared_atomic_comp_swap
:
7296 visit_shared_atomic(ctx
, instr
);
7298 case nir_intrinsic_image_deref_load
:
7299 visit_image_load(ctx
, instr
);
7301 case nir_intrinsic_image_deref_store
:
7302 visit_image_store(ctx
, instr
);
7304 case nir_intrinsic_image_deref_atomic_add
:
7305 case nir_intrinsic_image_deref_atomic_umin
:
7306 case nir_intrinsic_image_deref_atomic_imin
:
7307 case nir_intrinsic_image_deref_atomic_umax
:
7308 case nir_intrinsic_image_deref_atomic_imax
:
7309 case nir_intrinsic_image_deref_atomic_and
:
7310 case nir_intrinsic_image_deref_atomic_or
:
7311 case nir_intrinsic_image_deref_atomic_xor
:
7312 case nir_intrinsic_image_deref_atomic_exchange
:
7313 case nir_intrinsic_image_deref_atomic_comp_swap
:
7314 visit_image_atomic(ctx
, instr
);
7316 case nir_intrinsic_image_deref_size
:
7317 visit_image_size(ctx
, instr
);
7319 case nir_intrinsic_load_ssbo
:
7320 visit_load_ssbo(ctx
, instr
);
7322 case nir_intrinsic_store_ssbo
:
7323 visit_store_ssbo(ctx
, instr
);
7325 case nir_intrinsic_load_global
:
7326 visit_load_global(ctx
, instr
);
7328 case nir_intrinsic_store_global
:
7329 visit_store_global(ctx
, instr
);
7331 case nir_intrinsic_global_atomic_add
:
7332 case nir_intrinsic_global_atomic_imin
:
7333 case nir_intrinsic_global_atomic_umin
:
7334 case nir_intrinsic_global_atomic_imax
:
7335 case nir_intrinsic_global_atomic_umax
:
7336 case nir_intrinsic_global_atomic_and
:
7337 case nir_intrinsic_global_atomic_or
:
7338 case nir_intrinsic_global_atomic_xor
:
7339 case nir_intrinsic_global_atomic_exchange
:
7340 case nir_intrinsic_global_atomic_comp_swap
:
7341 visit_global_atomic(ctx
, instr
);
7343 case nir_intrinsic_ssbo_atomic_add
:
7344 case nir_intrinsic_ssbo_atomic_imin
:
7345 case nir_intrinsic_ssbo_atomic_umin
:
7346 case nir_intrinsic_ssbo_atomic_imax
:
7347 case nir_intrinsic_ssbo_atomic_umax
:
7348 case nir_intrinsic_ssbo_atomic_and
:
7349 case nir_intrinsic_ssbo_atomic_or
:
7350 case nir_intrinsic_ssbo_atomic_xor
:
7351 case nir_intrinsic_ssbo_atomic_exchange
:
7352 case nir_intrinsic_ssbo_atomic_comp_swap
:
7353 visit_atomic_ssbo(ctx
, instr
);
7355 case nir_intrinsic_load_scratch
:
7356 visit_load_scratch(ctx
, instr
);
7358 case nir_intrinsic_store_scratch
:
7359 visit_store_scratch(ctx
, instr
);
7361 case nir_intrinsic_get_buffer_size
:
7362 visit_get_buffer_size(ctx
, instr
);
7364 case nir_intrinsic_control_barrier
: {
7365 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7366 /* GFX6 only (thanks to a hw bug workaround):
7367 * The real barrier instruction isn’t needed, because an entire patch
7368 * always fits into a single wave.
7373 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7374 bld
.sopp(aco_opcode::s_barrier
);
7378 case nir_intrinsic_memory_barrier_tcs_patch
:
7379 case nir_intrinsic_group_memory_barrier
:
7380 case nir_intrinsic_memory_barrier
:
7381 case nir_intrinsic_memory_barrier_buffer
:
7382 case nir_intrinsic_memory_barrier_image
:
7383 case nir_intrinsic_memory_barrier_shared
:
7384 emit_memory_barrier(ctx
, instr
);
7386 case nir_intrinsic_load_num_work_groups
: {
7387 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7388 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7389 emit_split_vector(ctx
, dst
, 3);
7392 case nir_intrinsic_load_local_invocation_id
: {
7393 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7394 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7395 emit_split_vector(ctx
, dst
, 3);
7398 case nir_intrinsic_load_work_group_id
: {
7399 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7400 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7401 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7402 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7403 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7404 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7405 emit_split_vector(ctx
, dst
, 3);
7408 case nir_intrinsic_load_local_invocation_index
: {
7409 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7411 /* The tg_size bits [6:11] contain the subgroup id,
7412 * we need this multiplied by the wave size, and then OR the thread id to it.
7414 if (ctx
->program
->wave_size
== 64) {
7415 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7416 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7417 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7418 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7420 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7421 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7422 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7423 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7427 case nir_intrinsic_load_subgroup_id
: {
7428 if (ctx
->stage
== compute_cs
) {
7429 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7430 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7432 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7436 case nir_intrinsic_load_subgroup_invocation
: {
7437 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7440 case nir_intrinsic_load_num_subgroups
: {
7441 if (ctx
->stage
== compute_cs
)
7442 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7443 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7445 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7448 case nir_intrinsic_ballot
: {
7449 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7450 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7451 Definition tmp
= bld
.def(dst
.regClass());
7452 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7453 if (instr
->src
[0].ssa
->bit_size
== 1) {
7454 assert(src
.regClass() == bld
.lm
);
7455 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7456 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7457 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7458 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7459 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7461 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7462 nir_print_instr(&instr
->instr
, stderr
);
7463 fprintf(stderr
, "\n");
7465 if (dst
.size() != bld
.lm
.size()) {
7466 /* Wave32 with ballot size set to 64 */
7467 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7469 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7472 case nir_intrinsic_shuffle
:
7473 case nir_intrinsic_read_invocation
: {
7474 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7475 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
]) {
7476 emit_uniform_subgroup(ctx
, instr
, src
);
7478 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7479 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !ctx
->divergent_vals
[instr
->src
[1].ssa
->index
])
7480 tid
= bld
.as_uniform(tid
);
7481 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7482 if (src
.regClass() == v1
) {
7483 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7484 } else if (src
.regClass() == v2
) {
7485 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7486 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7487 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7488 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7489 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7490 emit_split_vector(ctx
, dst
, 2);
7491 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7492 assert(src
.regClass() == bld
.lm
);
7493 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7494 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7495 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7496 assert(src
.regClass() == bld
.lm
);
7498 if (ctx
->program
->chip_class
<= GFX7
)
7499 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7500 else if (ctx
->program
->wave_size
== 64)
7501 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7503 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7504 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7505 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7506 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7508 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7509 nir_print_instr(&instr
->instr
, stderr
);
7510 fprintf(stderr
, "\n");
7515 case nir_intrinsic_load_sample_id
: {
7516 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7517 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7520 case nir_intrinsic_load_sample_mask_in
: {
7521 visit_load_sample_mask_in(ctx
, instr
);
7524 case nir_intrinsic_read_first_invocation
: {
7525 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7526 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7527 if (src
.regClass() == v1
) {
7529 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7531 } else if (src
.regClass() == v2
) {
7532 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7533 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7534 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7535 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7536 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7537 emit_split_vector(ctx
, dst
, 2);
7538 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7539 assert(src
.regClass() == bld
.lm
);
7540 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7541 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7542 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7543 } else if (src
.regClass() == s1
) {
7544 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7545 } else if (src
.regClass() == s2
) {
7546 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7548 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7549 nir_print_instr(&instr
->instr
, stderr
);
7550 fprintf(stderr
, "\n");
7554 case nir_intrinsic_vote_all
: {
7555 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7556 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7557 assert(src
.regClass() == bld
.lm
);
7558 assert(dst
.regClass() == bld
.lm
);
7560 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7561 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7562 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7565 case nir_intrinsic_vote_any
: {
7566 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7567 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7568 assert(src
.regClass() == bld
.lm
);
7569 assert(dst
.regClass() == bld
.lm
);
7571 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7572 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7575 case nir_intrinsic_reduce
:
7576 case nir_intrinsic_inclusive_scan
:
7577 case nir_intrinsic_exclusive_scan
: {
7578 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7579 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7580 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7581 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7582 nir_intrinsic_cluster_size(instr
) : 0;
7583 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7585 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
] && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7586 emit_uniform_subgroup(ctx
, instr
, src
);
7587 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7588 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7590 else if (op
== nir_op_iadd
)
7592 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7594 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7596 switch (instr
->intrinsic
) {
7597 case nir_intrinsic_reduce
:
7598 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7600 case nir_intrinsic_exclusive_scan
:
7601 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7603 case nir_intrinsic_inclusive_scan
:
7604 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7609 } else if (cluster_size
== 1) {
7610 bld
.copy(Definition(dst
), src
);
7612 src
= as_vgpr(ctx
, src
);
7616 #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
7631 unreachable("unknown reduction op");
7636 switch (instr
->intrinsic
) {
7637 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7638 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7639 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7641 unreachable("unknown reduce intrinsic");
7644 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7645 reduce
->operands
[0] = Operand(src
);
7646 // filled in by aco_reduce_assign.cpp, used internally as part of the
7648 assert(dst
.size() == 1 || dst
.size() == 2);
7649 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7650 reduce
->operands
[2] = Operand(v1
.as_linear());
7652 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7653 reduce
->definitions
[0] = Definition(tmp_dst
);
7654 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7655 reduce
->definitions
[2] = Definition();
7656 reduce
->definitions
[3] = Definition(scc
, s1
);
7657 reduce
->definitions
[4] = Definition();
7658 reduce
->reduce_op
= reduce_op
;
7659 reduce
->cluster_size
= cluster_size
;
7660 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7662 emit_wqm(ctx
, tmp_dst
, dst
);
7666 case nir_intrinsic_quad_broadcast
: {
7667 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7668 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7669 emit_uniform_subgroup(ctx
, instr
, src
);
7671 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7672 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7673 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7675 if (instr
->dest
.ssa
.bit_size
== 1) {
7676 assert(src
.regClass() == bld
.lm
);
7677 assert(dst
.regClass() == bld
.lm
);
7678 uint32_t half_mask
= 0x11111111u
<< lane
;
7679 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7680 Temp tmp
= bld
.tmp(bld
.lm
);
7681 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7682 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7683 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7684 emit_wqm(ctx
, tmp
, dst
);
7685 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7686 if (ctx
->program
->chip_class
>= GFX8
)
7687 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7689 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7690 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7691 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7692 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7693 if (ctx
->program
->chip_class
>= GFX8
) {
7694 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7695 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7697 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7698 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7700 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7701 emit_split_vector(ctx
, dst
, 2);
7703 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7704 nir_print_instr(&instr
->instr
, stderr
);
7705 fprintf(stderr
, "\n");
7710 case nir_intrinsic_quad_swap_horizontal
:
7711 case nir_intrinsic_quad_swap_vertical
:
7712 case nir_intrinsic_quad_swap_diagonal
:
7713 case nir_intrinsic_quad_swizzle_amd
: {
7714 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7715 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7716 emit_uniform_subgroup(ctx
, instr
, src
);
7719 uint16_t dpp_ctrl
= 0;
7720 switch (instr
->intrinsic
) {
7721 case nir_intrinsic_quad_swap_horizontal
:
7722 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7724 case nir_intrinsic_quad_swap_vertical
:
7725 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7727 case nir_intrinsic_quad_swap_diagonal
:
7728 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7730 case nir_intrinsic_quad_swizzle_amd
:
7731 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7736 if (ctx
->program
->chip_class
< GFX8
)
7737 dpp_ctrl
|= (1 << 15);
7739 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7740 if (instr
->dest
.ssa
.bit_size
== 1) {
7741 assert(src
.regClass() == bld
.lm
);
7742 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7743 if (ctx
->program
->chip_class
>= GFX8
)
7744 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7746 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7747 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7748 emit_wqm(ctx
, tmp
, dst
);
7749 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7751 if (ctx
->program
->chip_class
>= GFX8
)
7752 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7754 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7755 emit_wqm(ctx
, tmp
, dst
);
7756 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7757 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7758 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7759 if (ctx
->program
->chip_class
>= GFX8
) {
7760 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7761 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7763 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7764 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7766 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7767 emit_split_vector(ctx
, dst
, 2);
7769 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7770 nir_print_instr(&instr
->instr
, stderr
);
7771 fprintf(stderr
, "\n");
7775 case nir_intrinsic_masked_swizzle_amd
: {
7776 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7777 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7778 emit_uniform_subgroup(ctx
, instr
, src
);
7781 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7782 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7783 if (dst
.regClass() == v1
) {
7785 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
7787 } else if (dst
.regClass() == v2
) {
7788 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7789 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7790 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
7791 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
7792 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7793 emit_split_vector(ctx
, dst
, 2);
7795 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7796 nir_print_instr(&instr
->instr
, stderr
);
7797 fprintf(stderr
, "\n");
7801 case nir_intrinsic_write_invocation_amd
: {
7802 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7803 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7804 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7805 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7806 if (dst
.regClass() == v1
) {
7807 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7808 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7809 } else if (dst
.regClass() == v2
) {
7810 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7811 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7812 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7813 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7814 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7815 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7816 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7817 emit_split_vector(ctx
, dst
, 2);
7819 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7820 nir_print_instr(&instr
->instr
, stderr
);
7821 fprintf(stderr
, "\n");
7825 case nir_intrinsic_mbcnt_amd
: {
7826 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7827 RegClass rc
= RegClass(src
.type(), 1);
7828 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7829 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7830 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7831 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7832 emit_wqm(ctx
, wqm_tmp
, dst
);
7835 case nir_intrinsic_load_helper_invocation
: {
7836 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7837 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7838 ctx
->block
->kind
|= block_kind_needs_lowering
;
7839 ctx
->program
->needs_exact
= true;
7842 case nir_intrinsic_is_helper_invocation
: {
7843 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7844 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7845 ctx
->block
->kind
|= block_kind_needs_lowering
;
7846 ctx
->program
->needs_exact
= true;
7849 case nir_intrinsic_demote
:
7850 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7852 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7853 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7854 ctx
->block
->kind
|= block_kind_uses_demote
;
7855 ctx
->program
->needs_exact
= true;
7857 case nir_intrinsic_demote_if
: {
7858 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7859 assert(src
.regClass() == bld
.lm
);
7860 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7861 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
7863 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7864 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7865 ctx
->block
->kind
|= block_kind_uses_demote
;
7866 ctx
->program
->needs_exact
= true;
7869 case nir_intrinsic_first_invocation
: {
7870 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
7871 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7874 case nir_intrinsic_shader_clock
:
7875 bld
.smem(aco_opcode::s_memtime
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
7876 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
7878 case nir_intrinsic_load_vertex_id_zero_base
: {
7879 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7880 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
7883 case nir_intrinsic_load_first_vertex
: {
7884 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7885 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
7888 case nir_intrinsic_load_base_instance
: {
7889 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7890 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
7893 case nir_intrinsic_load_instance_id
: {
7894 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7895 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
7898 case nir_intrinsic_load_draw_id
: {
7899 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7900 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
7903 case nir_intrinsic_load_invocation_id
: {
7904 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7906 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
7907 if (ctx
->options
->chip_class
>= GFX10
)
7908 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7910 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7911 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7912 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
7913 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
7915 unreachable("Unsupported stage for load_invocation_id");
7920 case nir_intrinsic_load_primitive_id
: {
7921 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7923 switch (ctx
->shader
->info
.stage
) {
7924 case MESA_SHADER_GEOMETRY
:
7925 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
7927 case MESA_SHADER_TESS_CTRL
:
7928 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
7930 case MESA_SHADER_TESS_EVAL
:
7931 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
7934 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
7939 case nir_intrinsic_load_patch_vertices_in
: {
7940 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
7941 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
7943 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7944 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
7947 case nir_intrinsic_emit_vertex_with_counter
: {
7948 visit_emit_vertex_with_counter(ctx
, instr
);
7951 case nir_intrinsic_end_primitive_with_counter
: {
7952 unsigned stream
= nir_intrinsic_stream_id(instr
);
7953 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
7956 case nir_intrinsic_set_vertex_count
: {
7957 /* unused, the HW keeps track of this for us */
7961 fprintf(stderr
, "Unimplemented intrinsic instr: ");
7962 nir_print_instr(&instr
->instr
, stderr
);
7963 fprintf(stderr
, "\n");
7971 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
7972 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
7973 enum glsl_base_type
*stype
)
7975 nir_deref_instr
*texture_deref_instr
= NULL
;
7976 nir_deref_instr
*sampler_deref_instr
= NULL
;
7979 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
7980 switch (instr
->src
[i
].src_type
) {
7981 case nir_tex_src_texture_deref
:
7982 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
7984 case nir_tex_src_sampler_deref
:
7985 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
7987 case nir_tex_src_plane
:
7988 plane
= nir_src_as_int(instr
->src
[i
].src
);
7995 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
7997 if (!sampler_deref_instr
)
7998 sampler_deref_instr
= texture_deref_instr
;
8001 assert(instr
->op
!= nir_texop_txf_ms
&&
8002 instr
->op
!= nir_texop_samples_identical
);
8003 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8004 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8005 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8006 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8007 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8008 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8010 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8013 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8015 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8016 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8017 Builder
bld(ctx
->program
, ctx
->block
);
8019 /* to avoid unnecessary moves, we split and recombine sampler and image */
8020 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8021 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8022 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8023 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8024 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8025 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8026 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8027 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8029 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8030 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8031 img
[0], img
[1], img
[2], img
[3],
8032 img
[4], img
[5], img
[6], img
[7]);
8033 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8034 samp
[0], samp
[1], samp
[2], samp
[3]);
8037 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8038 instr
->op
== nir_texop_samples_identical
))
8039 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8042 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8043 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8045 Builder
bld(ctx
->program
, ctx
->block
);
8047 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8048 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8049 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8051 Operand
neg_one(0xbf800000u
);
8052 Operand
one(0x3f800000u
);
8053 Operand
two(0x40000000u
);
8054 Operand
four(0x40800000u
);
8056 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8057 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8058 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8060 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8061 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8062 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8063 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8066 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8067 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8068 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8070 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8073 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8074 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8075 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8078 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8079 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8081 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8082 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8085 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8087 Builder
bld(ctx
->program
, ctx
->block
);
8088 Temp ma
, tc
, sc
, id
;
8091 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8093 // see comment in ac_prepare_cube_coords()
8094 if (ctx
->options
->chip_class
<= GFX8
)
8095 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8098 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8100 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8101 vop3a
->operands
[0] = Operand(ma
);
8102 vop3a
->abs
[0] = true;
8103 Temp invma
= bld
.tmp(v1
);
8104 vop3a
->definitions
[0] = Definition(invma
);
8105 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8107 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8109 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8111 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8113 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8115 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8118 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8119 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8121 for (unsigned i
= 0; i
< 2; i
++) {
8122 // see comment in ac_prepare_cube_coords()
8124 Temp deriv_sc
, deriv_tc
;
8125 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8126 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8128 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8130 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8131 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8132 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8133 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8134 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8135 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8136 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8139 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8140 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8144 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8151 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8153 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8155 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8156 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8159 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8160 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8161 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8165 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8167 Builder
bld(ctx
->program
, ctx
->block
);
8168 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8169 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false;
8170 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8171 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp();
8172 std::vector
<Temp
> coords
;
8173 std::vector
<Temp
> derivs
;
8174 nir_const_value
*sample_index_cv
= NULL
;
8175 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8176 enum glsl_base_type stype
;
8177 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8179 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8180 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8181 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8182 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8184 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8185 switch (instr
->src
[i
].src_type
) {
8186 case nir_tex_src_coord
: {
8187 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8188 for (unsigned i
= 0; i
< coord
.size(); i
++)
8189 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8192 case nir_tex_src_bias
:
8193 if (instr
->op
== nir_texop_txb
) {
8194 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8198 case nir_tex_src_lod
: {
8199 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8201 if (val
&& val
->f32
<= 0.0) {
8204 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8209 case nir_tex_src_comparator
:
8210 if (instr
->is_shadow
) {
8211 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8215 case nir_tex_src_offset
:
8216 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8217 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8220 case nir_tex_src_ddx
:
8221 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8224 case nir_tex_src_ddy
:
8225 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8228 case nir_tex_src_ms_index
:
8229 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8230 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8231 has_sample_index
= true;
8233 case nir_tex_src_texture_offset
:
8234 case nir_tex_src_sampler_offset
:
8240 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8241 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8243 if (instr
->op
== nir_texop_texture_samples
) {
8244 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8246 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8247 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8248 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8249 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8251 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8252 samples
, Operand(1u), bld
.scc(is_msaa
));
8256 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8257 aco_ptr
<Instruction
> tmp_instr
;
8258 Temp acc
, pack
= Temp();
8260 uint32_t pack_const
= 0;
8261 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8262 if (!const_offset
[i
])
8264 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8267 if (offset
.type() == RegType::sgpr
) {
8268 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8269 if (const_offset
[i
])
8272 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8273 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8276 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8279 if (pack
== Temp()) {
8282 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8286 if (pack_const
&& pack
!= Temp())
8287 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8289 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8290 if (const_offset
[i
])
8293 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8294 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8297 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8300 if (pack
== Temp()) {
8303 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8307 if (pack_const
&& pack
!= Temp())
8308 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8310 if (pack_const
&& pack
== Temp())
8311 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8312 else if (pack
== Temp())
8318 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8319 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8321 /* pack derivatives */
8322 if (has_ddx
|| has_ddy
) {
8323 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8324 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8325 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8326 derivs
= {ddy
, zero
, ddy
, zero
};
8328 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8329 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8330 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8331 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8336 if (instr
->coord_components
> 1 &&
8337 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8339 instr
->op
!= nir_texop_txf
)
8340 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8342 if (instr
->coord_components
> 2 &&
8343 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8344 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8345 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8346 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8348 instr
->op
!= nir_texop_txf
&&
8349 instr
->op
!= nir_texop_txf_ms
&&
8350 instr
->op
!= nir_texop_fragment_fetch
&&
8351 instr
->op
!= nir_texop_fragment_mask_fetch
)
8352 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8354 if (ctx
->options
->chip_class
== GFX9
&&
8355 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8356 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8357 assert(coords
.size() > 0 && coords
.size() < 3);
8359 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8360 Operand((uint32_t) 0) :
8361 Operand((uint32_t) 0x3f000000)));
8364 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8366 if (instr
->op
== nir_texop_samples_identical
)
8367 resource
= fmask_ptr
;
8369 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8370 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8371 instr
->op
!= nir_texop_txs
&&
8372 instr
->op
!= nir_texop_fragment_fetch
&&
8373 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8374 assert(has_sample_index
);
8375 Operand
op(sample_index
);
8376 if (sample_index_cv
)
8377 op
= Operand(sample_index_cv
->u32
);
8378 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8381 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8382 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8383 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8384 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8389 /* Build tex instruction */
8390 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8391 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8392 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8394 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8397 /* gather4 selects the component by dmask and always returns vec4 */
8398 if (instr
->op
== nir_texop_tg4
) {
8399 assert(instr
->dest
.ssa
.num_components
== 4);
8400 if (instr
->is_shadow
)
8403 dmask
= 1 << instr
->component
;
8404 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8405 tmp_dst
= bld
.tmp(v4
);
8406 } else if (instr
->op
== nir_texop_samples_identical
) {
8407 tmp_dst
= bld
.tmp(v1
);
8408 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8409 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8412 aco_ptr
<MIMG_instruction
> tex
;
8413 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8415 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8417 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8418 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8421 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8422 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8424 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8425 tex
->operands
[0] = Operand(resource
);
8426 tex
->operands
[1] = Operand(s4
); /* no sampler */
8427 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8428 if (ctx
->options
->chip_class
== GFX9
&&
8429 instr
->op
== nir_texop_txs
&&
8430 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8432 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8433 } else if (instr
->op
== nir_texop_query_levels
) {
8434 tex
->dmask
= 1 << 3;
8439 tex
->definitions
[0] = Definition(tmp_dst
);
8441 tex
->can_reorder
= true;
8442 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8445 /* divide 3rd value by 6 by multiplying with magic number */
8446 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8447 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8448 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8449 assert(instr
->dest
.ssa
.num_components
== 3);
8450 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8451 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8452 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8453 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8458 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8462 Temp tg4_compare_cube_wa64
= Temp();
8464 if (tg4_integer_workarounds
) {
8465 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8466 tex
->operands
[0] = Operand(resource
);
8467 tex
->operands
[1] = Operand(s4
); /* no sampler */
8468 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8472 Temp size
= bld
.tmp(v2
);
8473 tex
->definitions
[0] = Definition(size
);
8474 tex
->can_reorder
= true;
8475 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8476 emit_split_vector(ctx
, size
, size
.size());
8479 for (unsigned i
= 0; i
< 2; i
++) {
8480 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8481 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8482 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8483 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8486 Temp new_coords
[2] = {
8487 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8488 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8491 if (tg4_integer_cube_workaround
) {
8492 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8493 Temp desc
[resource
.size()];
8494 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8495 Format::PSEUDO
, 1, resource
.size())};
8496 split
->operands
[0] = Operand(resource
);
8497 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8498 desc
[i
] = bld
.tmp(s1
);
8499 split
->definitions
[i
] = Definition(desc
[i
]);
8501 ctx
->block
->instructions
.emplace_back(std::move(split
));
8503 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8504 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8505 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8508 if (stype
== GLSL_TYPE_UINT
) {
8509 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8510 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8511 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8512 bld
.scc(compare_cube_wa
));
8514 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8515 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8516 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8517 bld
.scc(compare_cube_wa
));
8519 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8520 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8522 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8524 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8525 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8526 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8528 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8529 Format::PSEUDO
, resource
.size(), 1)};
8530 for (unsigned i
= 0; i
< resource
.size(); i
++)
8531 vec
->operands
[i
] = Operand(desc
[i
]);
8532 resource
= bld
.tmp(resource
.regClass());
8533 vec
->definitions
[0] = Definition(resource
);
8534 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8536 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8537 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8538 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8539 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8541 coords
[0] = new_coords
[0];
8542 coords
[1] = new_coords
[1];
8545 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8546 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8548 assert(coords
.size() == 1);
8549 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8553 op
= aco_opcode::buffer_load_format_x
; break;
8555 op
= aco_opcode::buffer_load_format_xy
; break;
8557 op
= aco_opcode::buffer_load_format_xyz
; break;
8559 op
= aco_opcode::buffer_load_format_xyzw
; break;
8561 unreachable("Tex instruction loads more than 4 components.");
8564 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8565 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8568 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8570 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8571 mubuf
->operands
[0] = Operand(resource
);
8572 mubuf
->operands
[1] = Operand(coords
[0]);
8573 mubuf
->operands
[2] = Operand((uint32_t) 0);
8574 mubuf
->definitions
[0] = Definition(tmp_dst
);
8575 mubuf
->idxen
= true;
8576 mubuf
->can_reorder
= true;
8577 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8579 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8583 /* gather MIMG address components */
8584 std::vector
<Temp
> args
;
8586 args
.emplace_back(offset
);
8588 args
.emplace_back(bias
);
8590 args
.emplace_back(compare
);
8592 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8594 args
.insert(args
.end(), coords
.begin(), coords
.end());
8595 if (has_sample_index
)
8596 args
.emplace_back(sample_index
);
8598 args
.emplace_back(lod
);
8600 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8601 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8602 vec
->definitions
[0] = Definition(arg
);
8603 for (unsigned i
= 0; i
< args
.size(); i
++)
8604 vec
->operands
[i
] = Operand(args
[i
]);
8605 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8608 if (instr
->op
== nir_texop_txf
||
8609 instr
->op
== nir_texop_txf_ms
||
8610 instr
->op
== nir_texop_samples_identical
||
8611 instr
->op
== nir_texop_fragment_fetch
||
8612 instr
->op
== nir_texop_fragment_mask_fetch
) {
8613 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8614 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8615 tex
->operands
[0] = Operand(resource
);
8616 tex
->operands
[1] = Operand(s4
); /* no sampler */
8617 tex
->operands
[2] = Operand(arg
);
8622 tex
->definitions
[0] = Definition(tmp_dst
);
8623 tex
->can_reorder
= true;
8624 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8626 if (instr
->op
== nir_texop_samples_identical
) {
8627 assert(dmask
== 1 && dst
.regClass() == v1
);
8628 assert(dst
.id() != tmp_dst
.id());
8630 Temp tmp
= bld
.tmp(bld
.lm
);
8631 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8632 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8635 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8640 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8641 aco_opcode opcode
= aco_opcode::image_sample
;
8642 if (has_offset
) { /* image_sample_*_o */
8644 opcode
= aco_opcode::image_sample_c_o
;
8646 opcode
= aco_opcode::image_sample_c_d_o
;
8648 opcode
= aco_opcode::image_sample_c_b_o
;
8650 opcode
= aco_opcode::image_sample_c_lz_o
;
8652 opcode
= aco_opcode::image_sample_c_l_o
;
8654 opcode
= aco_opcode::image_sample_o
;
8656 opcode
= aco_opcode::image_sample_d_o
;
8658 opcode
= aco_opcode::image_sample_b_o
;
8660 opcode
= aco_opcode::image_sample_lz_o
;
8662 opcode
= aco_opcode::image_sample_l_o
;
8664 } else { /* no offset */
8666 opcode
= aco_opcode::image_sample_c
;
8668 opcode
= aco_opcode::image_sample_c_d
;
8670 opcode
= aco_opcode::image_sample_c_b
;
8672 opcode
= aco_opcode::image_sample_c_lz
;
8674 opcode
= aco_opcode::image_sample_c_l
;
8676 opcode
= aco_opcode::image_sample
;
8678 opcode
= aco_opcode::image_sample_d
;
8680 opcode
= aco_opcode::image_sample_b
;
8682 opcode
= aco_opcode::image_sample_lz
;
8684 opcode
= aco_opcode::image_sample_l
;
8688 if (instr
->op
== nir_texop_tg4
) {
8690 opcode
= aco_opcode::image_gather4_lz_o
;
8692 opcode
= aco_opcode::image_gather4_c_lz_o
;
8694 opcode
= aco_opcode::image_gather4_lz
;
8696 opcode
= aco_opcode::image_gather4_c_lz
;
8698 } else if (instr
->op
== nir_texop_lod
) {
8699 opcode
= aco_opcode::image_get_lod
;
8702 /* we don't need the bias, sample index, compare value or offset to be
8703 * computed in WQM but if the p_create_vector copies the coordinates, then it
8704 * needs to be in WQM */
8705 if (ctx
->stage
== fragment_fs
&&
8706 !has_derivs
&& !has_lod
&& !level_zero
&&
8707 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8708 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8709 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8711 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8712 tex
->operands
[0] = Operand(resource
);
8713 tex
->operands
[1] = Operand(sampler
);
8714 tex
->operands
[2] = Operand(arg
);
8718 tex
->definitions
[0] = Definition(tmp_dst
);
8719 tex
->can_reorder
= true;
8720 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8722 if (tg4_integer_cube_workaround
) {
8723 assert(tmp_dst
.id() != dst
.id());
8724 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8726 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8728 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8729 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8731 if (stype
== GLSL_TYPE_UINT
)
8732 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8734 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8735 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8737 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8738 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8739 val
[0], val
[1], val
[2], val
[3]);
8741 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8742 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8747 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
)
8749 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8750 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
8751 return Operand(tmp
.regClass());
8753 return Operand(tmp
);
8756 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8758 aco_ptr
<Pseudo_instruction
> phi
;
8759 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8760 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8762 bool logical
= !dst
.is_linear() || ctx
->divergent_vals
[instr
->dest
.ssa
.index
];
8763 logical
|= ctx
->block
->kind
& block_kind_merge
;
8764 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8766 /* we want a sorted list of sources, since the predecessor list is also sorted */
8767 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8768 nir_foreach_phi_src(src
, instr
)
8769 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8771 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8772 unsigned num_operands
= 0;
8773 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8774 unsigned num_defined
= 0;
8775 unsigned cur_pred_idx
= 0;
8776 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8777 if (cur_pred_idx
< preds
.size()) {
8778 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8779 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8780 unsigned skipped
= 0;
8781 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8783 if (cur_pred_idx
+ skipped
< preds
.size()) {
8784 for (unsigned i
= 0; i
< skipped
; i
++)
8785 operands
[num_operands
++] = Operand(dst
.regClass());
8786 cur_pred_idx
+= skipped
;
8791 /* Handle missing predecessors at the end. This shouldn't happen with loop
8792 * headers and we can't ignore these sources for loop header phis. */
8793 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8796 Operand op
= get_phi_operand(ctx
, src
.second
);
8797 operands
[num_operands
++] = op
;
8798 num_defined
+= !op
.isUndefined();
8800 /* handle block_kind_continue_or_break at loop exit blocks */
8801 while (cur_pred_idx
++ < preds
.size())
8802 operands
[num_operands
++] = Operand(dst
.regClass());
8804 /* If the loop ends with a break, still add a linear continue edge in case
8805 * that break is divergent or continue_or_break is used. We'll either remove
8806 * this operand later in visit_loop() if it's not necessary or replace the
8807 * undef with something correct. */
8808 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
8809 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
8810 nir_block
*last
= nir_loop_last_block(loop
);
8811 if (last
->successors
[0] != instr
->instr
.block
)
8812 operands
[num_operands
++] = Operand(RegClass());
8815 if (num_defined
== 0) {
8816 Builder
bld(ctx
->program
, ctx
->block
);
8817 if (dst
.regClass() == s1
) {
8818 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
8819 } else if (dst
.regClass() == v1
) {
8820 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
8822 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8823 for (unsigned i
= 0; i
< dst
.size(); i
++)
8824 vec
->operands
[i
] = Operand(0u);
8825 vec
->definitions
[0] = Definition(dst
);
8826 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8831 /* we can use a linear phi in some cases if one src is undef */
8832 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
8833 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
8835 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
8836 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
8837 assert(invert
->kind
& block_kind_invert
);
8839 unsigned then_block
= invert
->linear_preds
[0];
8841 Block
* insert_block
= NULL
;
8842 for (unsigned i
= 0; i
< num_operands
; i
++) {
8843 Operand op
= operands
[i
];
8844 if (op
.isUndefined())
8846 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
8847 phi
->operands
[0] = op
;
8850 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
8851 phi
->operands
[1] = Operand(dst
.regClass());
8852 phi
->definitions
[0] = Definition(dst
);
8853 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
8857 /* try to scalarize vector phis */
8858 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
8859 // TODO: scalarize linear phis on divergent ifs
8860 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
8861 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
8862 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
8863 Operand src
= operands
[i
];
8864 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
8865 can_scalarize
= false;
8867 if (can_scalarize
) {
8868 unsigned num_components
= instr
->dest
.ssa
.num_components
;
8869 assert(dst
.size() % num_components
== 0);
8870 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
8872 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
8873 for (unsigned k
= 0; k
< num_components
; k
++) {
8874 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8875 for (unsigned i
= 0; i
< num_operands
; i
++) {
8876 Operand src
= operands
[i
];
8877 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
8879 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
8880 phi
->definitions
[0] = Definition(phi_dst
);
8881 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
8882 new_vec
[k
] = phi_dst
;
8883 vec
->operands
[k
] = Operand(phi_dst
);
8885 vec
->definitions
[0] = Definition(dst
);
8886 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8887 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
8892 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8893 for (unsigned i
= 0; i
< num_operands
; i
++)
8894 phi
->operands
[i
] = operands
[i
];
8895 phi
->definitions
[0] = Definition(dst
);
8896 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
8900 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
8902 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
8904 assert(dst
.type() == RegType::sgpr
);
8906 if (dst
.size() == 1) {
8907 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
8909 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8910 for (unsigned i
= 0; i
< dst
.size(); i
++)
8911 vec
->operands
[i
] = Operand(0u);
8912 vec
->definitions
[0] = Definition(dst
);
8913 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8917 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
8919 Builder
bld(ctx
->program
, ctx
->block
);
8920 Block
*logical_target
;
8921 append_logical_end(ctx
->block
);
8922 unsigned idx
= ctx
->block
->index
;
8924 switch (instr
->type
) {
8925 case nir_jump_break
:
8926 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
8927 add_logical_edge(idx
, logical_target
);
8928 ctx
->block
->kind
|= block_kind_break
;
8930 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
8931 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
8932 /* uniform break - directly jump out of the loop */
8933 ctx
->block
->kind
|= block_kind_uniform
;
8934 ctx
->cf_info
.has_branch
= true;
8935 bld
.branch(aco_opcode::p_branch
);
8936 add_linear_edge(idx
, logical_target
);
8939 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
8940 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
8942 case nir_jump_continue
:
8943 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
8944 add_logical_edge(idx
, logical_target
);
8945 ctx
->block
->kind
|= block_kind_continue
;
8947 if (ctx
->cf_info
.parent_if
.is_divergent
) {
8948 /* for potential uniform breaks after this continue,
8949 we must ensure that they are handled correctly */
8950 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
8951 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
8952 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
8954 /* uniform continue - directly jump to the loop header */
8955 ctx
->block
->kind
|= block_kind_uniform
;
8956 ctx
->cf_info
.has_branch
= true;
8957 bld
.branch(aco_opcode::p_branch
);
8958 add_linear_edge(idx
, logical_target
);
8963 fprintf(stderr
, "Unknown NIR jump instr: ");
8964 nir_print_instr(&instr
->instr
, stderr
);
8965 fprintf(stderr
, "\n");
8969 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
8970 ctx
->cf_info
.exec_potentially_empty_break
= true;
8971 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
8974 /* remove critical edges from linear CFG */
8975 bld
.branch(aco_opcode::p_branch
);
8976 Block
* break_block
= ctx
->program
->create_and_insert_block();
8977 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
8978 break_block
->kind
|= block_kind_uniform
;
8979 add_linear_edge(idx
, break_block
);
8980 /* the loop_header pointer might be invalidated by this point */
8981 if (instr
->type
== nir_jump_continue
)
8982 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
8983 add_linear_edge(break_block
->index
, logical_target
);
8984 bld
.reset(break_block
);
8985 bld
.branch(aco_opcode::p_branch
);
8987 Block
* continue_block
= ctx
->program
->create_and_insert_block();
8988 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
8989 add_linear_edge(idx
, continue_block
);
8990 append_logical_start(continue_block
);
8991 ctx
->block
= continue_block
;
8995 void visit_block(isel_context
*ctx
, nir_block
*block
)
8997 nir_foreach_instr(instr
, block
) {
8998 switch (instr
->type
) {
8999 case nir_instr_type_alu
:
9000 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9002 case nir_instr_type_load_const
:
9003 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9005 case nir_instr_type_intrinsic
:
9006 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9008 case nir_instr_type_tex
:
9009 visit_tex(ctx
, nir_instr_as_tex(instr
));
9011 case nir_instr_type_phi
:
9012 visit_phi(ctx
, nir_instr_as_phi(instr
));
9014 case nir_instr_type_ssa_undef
:
9015 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9017 case nir_instr_type_deref
:
9019 case nir_instr_type_jump
:
9020 visit_jump(ctx
, nir_instr_as_jump(instr
));
9023 fprintf(stderr
, "Unknown NIR instr type: ");
9024 nir_print_instr(instr
, stderr
);
9025 fprintf(stderr
, "\n");
9030 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9031 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9036 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9037 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9039 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9040 RegClass rc
= vals
[0].regClass();
9042 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9044 unsigned next_pred
= 1;
9046 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9047 Block
& block
= ctx
->program
->blocks
[idx
];
9048 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9049 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9053 if (block
.kind
& block_kind_continue
) {
9054 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9059 bool all_same
= true;
9060 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9061 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9065 val
= vals
[block
.linear_preds
[0] - first
];
9067 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9068 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9069 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9070 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9071 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9072 phi
->definitions
[0] = Definition(val
.getTemp());
9073 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9075 vals
[idx
- first
] = val
;
9078 return vals
[last
- first
];
9081 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9083 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9084 append_logical_end(ctx
->block
);
9085 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9086 Builder
bld(ctx
->program
, ctx
->block
);
9087 bld
.branch(aco_opcode::p_branch
);
9088 unsigned loop_preheader_idx
= ctx
->block
->index
;
9090 Block loop_exit
= Block();
9091 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9092 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9094 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9095 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9096 loop_header
->kind
|= block_kind_loop_header
;
9097 add_edge(loop_preheader_idx
, loop_header
);
9098 ctx
->block
= loop_header
;
9100 /* emit loop body */
9101 unsigned loop_header_idx
= loop_header
->index
;
9102 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9103 append_logical_start(ctx
->block
);
9104 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9106 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9107 if (!ctx
->cf_info
.has_branch
) {
9108 append_logical_end(ctx
->block
);
9109 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9110 /* Discards can result in code running with an empty exec mask.
9111 * This would result in divergent breaks not ever being taken. As a
9112 * workaround, break the loop when the loop mask is empty instead of
9113 * always continuing. */
9114 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9115 unsigned block_idx
= ctx
->block
->index
;
9117 /* create helper blocks to avoid critical edges */
9118 Block
*break_block
= ctx
->program
->create_and_insert_block();
9119 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9120 break_block
->kind
= block_kind_uniform
;
9121 bld
.reset(break_block
);
9122 bld
.branch(aco_opcode::p_branch
);
9123 add_linear_edge(block_idx
, break_block
);
9124 add_linear_edge(break_block
->index
, &loop_exit
);
9126 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9127 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9128 continue_block
->kind
= block_kind_uniform
;
9129 bld
.reset(continue_block
);
9130 bld
.branch(aco_opcode::p_branch
);
9131 add_linear_edge(block_idx
, continue_block
);
9132 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9134 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9135 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9136 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9138 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9139 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9140 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9142 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9145 bld
.reset(ctx
->block
);
9146 bld
.branch(aco_opcode::p_branch
);
9149 /* Fixup phis in loop header from unreachable blocks.
9150 * has_branch/has_divergent_branch also indicates if the loop ends with a
9151 * break/continue instruction, but we don't emit those if unreachable=true */
9153 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9154 bool linear
= ctx
->cf_info
.has_branch
;
9155 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9156 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9157 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9158 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9159 /* the last operand should be the one that needs to be removed */
9160 instr
->operands
.pop_back();
9161 } else if (!is_phi(instr
)) {
9167 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9168 * and the previous one shouldn't both happen at once because a break in the
9169 * merge block would get CSE'd */
9170 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9171 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9172 Operand vals
[num_vals
];
9173 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9174 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9175 if (ctx
->cf_info
.has_branch
)
9176 instr
->operands
.pop_back();
9178 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9179 } else if (!is_phi(instr
)) {
9185 ctx
->cf_info
.has_branch
= false;
9187 // TODO: if the loop has not a single exit, we must add one °°
9188 /* emit loop successor block */
9189 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9190 append_logical_start(ctx
->block
);
9193 // TODO: check if it is beneficial to not branch on continues
9194 /* trim linear phis in loop header */
9195 for (auto&& instr
: loop_entry
->instructions
) {
9196 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9197 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9198 new_phi
->definitions
[0] = instr
->definitions
[0];
9199 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9200 new_phi
->operands
[i
] = instr
->operands
[i
];
9201 /* check that the remaining operands are all the same */
9202 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9203 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9204 instr
.swap(new_phi
);
9205 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9214 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9218 append_logical_end(ctx
->block
);
9219 ctx
->block
->kind
|= block_kind_branch
;
9221 /* branch to linear then block */
9222 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9223 aco_ptr
<Pseudo_branch_instruction
> branch
;
9224 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9225 branch
->operands
[0] = Operand(cond
);
9226 ctx
->block
->instructions
.push_back(std::move(branch
));
9228 ic
->BB_if_idx
= ctx
->block
->index
;
9229 ic
->BB_invert
= Block();
9230 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9231 /* Invert blocks are intentionally not marked as top level because they
9232 * are not part of the logical cfg. */
9233 ic
->BB_invert
.kind
|= block_kind_invert
;
9234 ic
->BB_endif
= Block();
9235 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9236 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9238 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9239 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9240 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9241 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9242 ctx
->cf_info
.parent_if
.is_divergent
= true;
9244 /* divergent branches use cbranch_execz */
9245 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9246 ctx
->cf_info
.exec_potentially_empty_break
= false;
9247 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9249 /** emit logical then block */
9250 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9251 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9252 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9253 ctx
->block
= BB_then_logical
;
9254 append_logical_start(BB_then_logical
);
9257 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9259 Block
*BB_then_logical
= ctx
->block
;
9260 append_logical_end(BB_then_logical
);
9261 /* branch from logical then block to invert block */
9262 aco_ptr
<Pseudo_branch_instruction
> branch
;
9263 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9264 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9265 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9266 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9267 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9268 BB_then_logical
->kind
|= block_kind_uniform
;
9269 assert(!ctx
->cf_info
.has_branch
);
9270 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9271 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9273 /** emit linear then block */
9274 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9275 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9276 BB_then_linear
->kind
|= block_kind_uniform
;
9277 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9278 /* branch from linear then block to invert block */
9279 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9280 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9281 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9283 /** emit invert merge block */
9284 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9285 ic
->invert_idx
= ctx
->block
->index
;
9287 /* branch to linear else block (skip else) */
9288 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9289 branch
->operands
[0] = Operand(ic
->cond
);
9290 ctx
->block
->instructions
.push_back(std::move(branch
));
9292 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9293 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9294 ic
->exec_potentially_empty_break_depth_old
=
9295 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9296 /* divergent branches use cbranch_execz */
9297 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9298 ctx
->cf_info
.exec_potentially_empty_break
= false;
9299 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9301 /** emit logical else block */
9302 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9303 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9304 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9305 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9306 ctx
->block
= BB_else_logical
;
9307 append_logical_start(BB_else_logical
);
9310 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9312 Block
*BB_else_logical
= ctx
->block
;
9313 append_logical_end(BB_else_logical
);
9315 /* branch from logical else block to endif block */
9316 aco_ptr
<Pseudo_branch_instruction
> branch
;
9317 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9318 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9319 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9320 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9321 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9322 BB_else_logical
->kind
|= block_kind_uniform
;
9324 assert(!ctx
->cf_info
.has_branch
);
9325 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9328 /** emit linear else block */
9329 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9330 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9331 BB_else_linear
->kind
|= block_kind_uniform
;
9332 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9334 /* branch from linear else block to endif block */
9335 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9336 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9337 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9340 /** emit endif merge block */
9341 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9342 append_logical_start(ctx
->block
);
9345 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9346 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9347 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9348 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9349 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9350 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9351 !ctx
->cf_info
.parent_if
.is_divergent
) {
9352 ctx
->cf_info
.exec_potentially_empty_break
= false;
9353 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9355 /* uniform control flow never has an empty exec-mask */
9356 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9357 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9358 ctx
->cf_info
.exec_potentially_empty_break
= false;
9359 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9363 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9365 assert(cond
.regClass() == s1
);
9367 append_logical_end(ctx
->block
);
9368 ctx
->block
->kind
|= block_kind_uniform
;
9370 aco_ptr
<Pseudo_branch_instruction
> branch
;
9371 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9372 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9373 branch
->operands
[0] = Operand(cond
);
9374 branch
->operands
[0].setFixed(scc
);
9375 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9377 ic
->BB_if_idx
= ctx
->block
->index
;
9378 ic
->BB_endif
= Block();
9379 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9380 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9382 ctx
->cf_info
.has_branch
= false;
9383 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9385 /** emit then block */
9386 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9387 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9388 add_edge(ic
->BB_if_idx
, BB_then
);
9389 append_logical_start(BB_then
);
9390 ctx
->block
= BB_then
;
9393 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9395 Block
*BB_then
= ctx
->block
;
9397 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9398 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9400 if (!ic
->uniform_has_then_branch
) {
9401 append_logical_end(BB_then
);
9402 /* branch from then block to endif block */
9403 aco_ptr
<Pseudo_branch_instruction
> branch
;
9404 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9405 BB_then
->instructions
.emplace_back(std::move(branch
));
9406 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9407 if (!ic
->then_branch_divergent
)
9408 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9409 BB_then
->kind
|= block_kind_uniform
;
9412 ctx
->cf_info
.has_branch
= false;
9413 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9415 /** emit else block */
9416 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9417 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9418 add_edge(ic
->BB_if_idx
, BB_else
);
9419 append_logical_start(BB_else
);
9420 ctx
->block
= BB_else
;
9423 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9425 Block
*BB_else
= ctx
->block
;
9427 if (!ctx
->cf_info
.has_branch
) {
9428 append_logical_end(BB_else
);
9429 /* branch from then block to endif block */
9430 aco_ptr
<Pseudo_branch_instruction
> branch
;
9431 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9432 BB_else
->instructions
.emplace_back(std::move(branch
));
9433 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9434 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9435 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9436 BB_else
->kind
|= block_kind_uniform
;
9439 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9440 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9442 /** emit endif merge block */
9443 if (!ctx
->cf_info
.has_branch
) {
9444 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9445 append_logical_start(ctx
->block
);
9449 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9451 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9452 Builder
bld(ctx
->program
, ctx
->block
);
9453 aco_ptr
<Pseudo_branch_instruction
> branch
;
9456 if (!ctx
->divergent_vals
[if_stmt
->condition
.ssa
->index
]) { /* uniform condition */
9458 * Uniform conditionals are represented in the following way*) :
9460 * The linear and logical CFG:
9463 * BB_THEN (logical) BB_ELSE (logical)
9467 * *) Exceptions may be due to break and continue statements within loops
9468 * If a break/continue happens within uniform control flow, it branches
9469 * to the loop exit/entry block. Otherwise, it branches to the next
9473 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9474 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9475 cond
= bool_to_scalar_condition(ctx
, cond
);
9477 begin_uniform_if_then(ctx
, &ic
, cond
);
9478 visit_cf_list(ctx
, &if_stmt
->then_list
);
9480 begin_uniform_if_else(ctx
, &ic
);
9481 visit_cf_list(ctx
, &if_stmt
->else_list
);
9483 end_uniform_if(ctx
, &ic
);
9485 return !ctx
->cf_info
.has_branch
;
9486 } else { /* non-uniform condition */
9488 * To maintain a logical and linear CFG without critical edges,
9489 * non-uniform conditionals are represented in the following way*) :
9494 * BB_THEN (logical) BB_THEN (linear)
9496 * BB_INVERT (linear)
9498 * BB_ELSE (logical) BB_ELSE (linear)
9505 * BB_THEN (logical) BB_ELSE (logical)
9509 * *) Exceptions may be due to break and continue statements within loops
9512 begin_divergent_if_then(ctx
, &ic
, cond
);
9513 visit_cf_list(ctx
, &if_stmt
->then_list
);
9515 begin_divergent_if_else(ctx
, &ic
);
9516 visit_cf_list(ctx
, &if_stmt
->else_list
);
9518 end_divergent_if(ctx
, &ic
);
9524 static bool visit_cf_list(isel_context
*ctx
,
9525 struct exec_list
*list
)
9527 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9528 switch (node
->type
) {
9529 case nir_cf_node_block
:
9530 visit_block(ctx
, nir_cf_node_as_block(node
));
9532 case nir_cf_node_if
:
9533 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9536 case nir_cf_node_loop
:
9537 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9540 unreachable("unimplemented cf list type");
9546 static void create_null_export(isel_context
*ctx
)
9548 /* Some shader stages always need to have exports.
9549 * So when there is none, we need to add a null export.
9552 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9553 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9554 Builder
bld(ctx
->program
, ctx
->block
);
9555 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9556 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9559 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9561 assert(ctx
->stage
== vertex_vs
||
9562 ctx
->stage
== tess_eval_vs
||
9563 ctx
->stage
== gs_copy_vs
||
9564 ctx
->stage
== ngg_vertex_gs
||
9565 ctx
->stage
== ngg_tess_eval_gs
);
9567 int offset
= (ctx
->stage
& sw_tes
)
9568 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9569 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9570 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9571 if (!is_pos
&& !mask
)
9573 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9575 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9576 exp
->enabled_mask
= mask
;
9577 for (unsigned i
= 0; i
< 4; ++i
) {
9578 if (mask
& (1 << i
))
9579 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9581 exp
->operands
[i
] = Operand(v1
);
9583 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9584 * Setting valid_mask=1 prevents it and has no other effect.
9586 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9588 exp
->compressed
= false;
9590 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9592 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9593 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9598 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9600 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9601 exp
->enabled_mask
= 0;
9602 for (unsigned i
= 0; i
< 4; ++i
)
9603 exp
->operands
[i
] = Operand(v1
);
9604 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9605 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9606 exp
->enabled_mask
|= 0x1;
9608 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9609 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9610 exp
->enabled_mask
|= 0x4;
9612 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9613 if (ctx
->options
->chip_class
< GFX9
) {
9614 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9615 exp
->enabled_mask
|= 0x8;
9617 Builder
bld(ctx
->program
, ctx
->block
);
9619 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9620 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9621 if (exp
->operands
[2].isTemp())
9622 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9624 exp
->operands
[2] = Operand(out
);
9625 exp
->enabled_mask
|= 0x4;
9628 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9630 exp
->compressed
= false;
9631 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9632 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9635 static void create_export_phis(isel_context
*ctx
)
9637 /* Used when exports are needed, but the output temps are defined in a preceding block.
9638 * This function will set up phis in order to access the outputs in the next block.
9641 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9642 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9643 ctx
->block
->instructions
.pop_back();
9645 Builder
bld(ctx
->program
, ctx
->block
);
9647 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9648 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9649 for (unsigned i
= 0; i
< 4; ++i
) {
9650 if (!(mask
& (1 << i
)))
9653 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9654 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9655 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9659 bld
.insert(std::move(logical_start
));
9662 static void create_vs_exports(isel_context
*ctx
)
9664 assert(ctx
->stage
== vertex_vs
||
9665 ctx
->stage
== tess_eval_vs
||
9666 ctx
->stage
== gs_copy_vs
||
9667 ctx
->stage
== ngg_vertex_gs
||
9668 ctx
->stage
== ngg_tess_eval_gs
);
9670 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9671 ? &ctx
->program
->info
->tes
.outinfo
9672 : &ctx
->program
->info
->vs
.outinfo
;
9674 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9675 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9676 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9679 if (ctx
->options
->key
.has_multiview_view_index
) {
9680 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9681 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9684 /* the order these position exports are created is important */
9686 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9687 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9688 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9689 exported_pos
= true;
9691 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9692 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9693 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9694 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9696 if (ctx
->export_clip_dists
) {
9697 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9698 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9699 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9700 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9703 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9704 if (i
< VARYING_SLOT_VAR0
&&
9705 i
!= VARYING_SLOT_LAYER
&&
9706 i
!= VARYING_SLOT_PRIMITIVE_ID
)
9709 export_vs_varying(ctx
, i
, false, NULL
);
9713 create_null_export(ctx
);
9716 static bool export_fs_mrt_z(isel_context
*ctx
)
9718 Builder
bld(ctx
->program
, ctx
->block
);
9719 unsigned enabled_channels
= 0;
9723 for (unsigned i
= 0; i
< 4; ++i
) {
9724 values
[i
] = Operand(v1
);
9727 /* Both stencil and sample mask only need 16-bits. */
9728 if (!ctx
->program
->info
->ps
.writes_z
&&
9729 (ctx
->program
->info
->ps
.writes_stencil
||
9730 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9731 compr
= true; /* COMPR flag */
9733 if (ctx
->program
->info
->ps
.writes_stencil
) {
9734 /* Stencil should be in X[23:16]. */
9735 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9736 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9737 enabled_channels
|= 0x3;
9740 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9741 /* SampleMask should be in Y[15:0]. */
9742 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9743 enabled_channels
|= 0xc;
9746 if (ctx
->program
->info
->ps
.writes_z
) {
9747 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9748 enabled_channels
|= 0x1;
9751 if (ctx
->program
->info
->ps
.writes_stencil
) {
9752 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9753 enabled_channels
|= 0x2;
9756 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9757 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9758 enabled_channels
|= 0x4;
9762 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9763 * writemask component.
9765 if (ctx
->options
->chip_class
== GFX6
&&
9766 ctx
->options
->family
!= CHIP_OLAND
&&
9767 ctx
->options
->family
!= CHIP_HAINAN
) {
9768 enabled_channels
|= 0x1;
9771 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9772 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9777 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9779 Builder
bld(ctx
->program
, ctx
->block
);
9780 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9783 for (unsigned i
= 0; i
< 4; ++i
) {
9784 if (write_mask
& (1 << i
)) {
9785 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9787 values
[i
] = Operand(v1
);
9791 unsigned target
, col_format
;
9792 unsigned enabled_channels
= 0;
9793 aco_opcode compr_op
= (aco_opcode
)0;
9795 slot
-= FRAG_RESULT_DATA0
;
9796 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9797 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9799 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9800 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
9804 case V_028714_SPI_SHADER_ZERO
:
9805 enabled_channels
= 0; /* writemask */
9806 target
= V_008DFC_SQ_EXP_NULL
;
9809 case V_028714_SPI_SHADER_32_R
:
9810 enabled_channels
= 1;
9813 case V_028714_SPI_SHADER_32_GR
:
9814 enabled_channels
= 0x3;
9817 case V_028714_SPI_SHADER_32_AR
:
9818 if (ctx
->options
->chip_class
>= GFX10
) {
9819 /* Special case: on GFX10, the outputs are different for 32_AR */
9820 enabled_channels
= 0x3;
9821 values
[1] = values
[3];
9822 values
[3] = Operand(v1
);
9824 enabled_channels
= 0x9;
9828 case V_028714_SPI_SHADER_FP16_ABGR
:
9829 enabled_channels
= 0x5;
9830 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
9833 case V_028714_SPI_SHADER_UNORM16_ABGR
:
9834 enabled_channels
= 0x5;
9835 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
9838 case V_028714_SPI_SHADER_SNORM16_ABGR
:
9839 enabled_channels
= 0x5;
9840 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
9843 case V_028714_SPI_SHADER_UINT16_ABGR
: {
9844 enabled_channels
= 0x5;
9845 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
9846 if (is_int8
|| is_int10
) {
9848 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
9849 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9851 for (unsigned i
= 0; i
< 4; i
++) {
9852 if ((write_mask
>> i
) & 1) {
9853 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
9854 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
9862 case V_028714_SPI_SHADER_SINT16_ABGR
:
9863 enabled_channels
= 0x5;
9864 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
9865 if (is_int8
|| is_int10
) {
9867 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
9868 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
9869 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9870 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
9872 for (unsigned i
= 0; i
< 4; i
++) {
9873 if ((write_mask
>> i
) & 1) {
9874 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
9875 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
9877 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
9878 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
9885 case V_028714_SPI_SHADER_32_ABGR
:
9886 enabled_channels
= 0xF;
9893 if (target
== V_008DFC_SQ_EXP_NULL
)
9896 if ((bool) compr_op
) {
9897 for (int i
= 0; i
< 2; i
++) {
9898 /* check if at least one of the values to be compressed is enabled */
9899 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
9901 enabled_channels
|= enabled
<< (i
*2);
9902 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
9903 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
9904 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
9906 values
[i
] = Operand(v1
);
9909 values
[2] = Operand(v1
);
9910 values
[3] = Operand(v1
);
9912 for (int i
= 0; i
< 4; i
++)
9913 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
9916 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9917 enabled_channels
, target
, (bool) compr_op
);
9921 static void create_fs_exports(isel_context
*ctx
)
9923 bool exported
= false;
9925 /* Export depth, stencil and sample mask. */
9926 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
9927 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
9928 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
9929 exported
|= export_fs_mrt_z(ctx
);
9931 /* Export all color render targets. */
9932 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
9933 if (ctx
->outputs
.mask
[i
])
9934 exported
|= export_fs_mrt_color(ctx
, i
);
9937 create_null_export(ctx
);
9940 static void write_tcs_tess_factors(isel_context
*ctx
)
9942 unsigned outer_comps
;
9943 unsigned inner_comps
;
9945 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
9962 Builder
bld(ctx
->program
, ctx
->block
);
9964 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
9965 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
9966 bld
.sopp(aco_opcode::s_barrier
);
9968 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
9969 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
9971 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
9972 if_context ic_invocation_id_is_zero
;
9973 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
9974 bld
.reset(ctx
->block
);
9976 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
9978 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
9979 unsigned stride
= inner_comps
+ outer_comps
;
9980 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
9984 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
9986 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
9988 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
9989 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
9990 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
9992 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
9993 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
9995 for (unsigned i
= 0; i
< outer_comps
; ++i
)
9996 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
9997 for (unsigned i
= 0; i
< inner_comps
; ++i
)
9998 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10001 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10002 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10003 Temp byte_offset
= bld
.v_mul_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10004 unsigned tf_const_offset
= 0;
10006 if (ctx
->program
->chip_class
<= GFX8
) {
10007 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10008 if_context ic_rel_patch_id_is_zero
;
10009 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10010 bld
.reset(ctx
->block
);
10012 /* Store the dynamic HS control word. */
10013 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10014 bld
.mubuf(aco_opcode::buffer_store_dword
,
10015 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10016 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
10017 /* disable_wqm */ false, /* glc */ true);
10018 tf_const_offset
+= 4;
10020 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10021 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10022 bld
.reset(ctx
->block
);
10025 assert(stride
== 2 || stride
== 4 || stride
== 6);
10026 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10027 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
10029 /* Store to offchip for TES to read - only if TES reads them */
10030 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10031 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10032 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10034 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10035 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
10037 if (likely(inner_comps
)) {
10038 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10039 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
10043 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10044 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10047 static void emit_stream_output(isel_context
*ctx
,
10048 Temp
const *so_buffers
,
10049 Temp
const *so_write_offset
,
10050 const struct radv_stream_output
*output
)
10052 unsigned num_comps
= util_bitcount(output
->component_mask
);
10053 unsigned writemask
= (1 << num_comps
) - 1;
10054 unsigned loc
= output
->location
;
10055 unsigned buf
= output
->buffer
;
10057 assert(num_comps
&& num_comps
<= 4);
10058 if (!num_comps
|| num_comps
> 4)
10061 unsigned start
= ffs(output
->component_mask
) - 1;
10064 bool all_undef
= true;
10065 assert(ctx
->stage
== vertex_vs
|| ctx
->stage
== gs_copy_vs
);
10066 for (unsigned i
= 0; i
< num_comps
; i
++) {
10067 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10068 all_undef
= all_undef
&& !out
[i
].id();
10073 while (writemask
) {
10075 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10076 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10077 /* GFX6 doesn't support storing vec3, split it. */
10078 writemask
|= 1u << (start
+ 2);
10082 unsigned offset
= output
->offset
+ start
* 4;
10084 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10085 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10086 for (int i
= 0; i
< count
; ++i
)
10087 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10088 vec
->definitions
[0] = Definition(write_data
);
10089 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10094 opcode
= aco_opcode::buffer_store_dword
;
10097 opcode
= aco_opcode::buffer_store_dwordx2
;
10100 opcode
= aco_opcode::buffer_store_dwordx3
;
10103 opcode
= aco_opcode::buffer_store_dwordx4
;
10106 unreachable("Unsupported dword count.");
10109 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10110 store
->operands
[0] = Operand(so_buffers
[buf
]);
10111 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10112 store
->operands
[2] = Operand((uint32_t) 0);
10113 store
->operands
[3] = Operand(write_data
);
10114 if (offset
> 4095) {
10115 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10116 Builder
bld(ctx
->program
, ctx
->block
);
10117 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10119 store
->offset
= offset
;
10121 store
->offen
= true;
10123 store
->dlc
= false;
10125 store
->can_reorder
= true;
10126 ctx
->block
->instructions
.emplace_back(std::move(store
));
10130 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10132 Builder
bld(ctx
->program
, ctx
->block
);
10134 Temp so_buffers
[4];
10135 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10136 for (unsigned i
= 0; i
< 4; i
++) {
10137 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10141 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10142 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10145 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10146 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10148 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10150 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10153 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10155 bld
.reset(ctx
->block
);
10157 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10159 Temp so_write_offset
[4];
10161 for (unsigned i
= 0; i
< 4; i
++) {
10162 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10167 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10168 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10169 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10170 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10172 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10174 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10175 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10176 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10177 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10181 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10182 struct radv_stream_output
*output
=
10183 &ctx
->program
->info
->so
.outputs
[i
];
10184 if (stream
!= output
->stream
)
10187 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10190 begin_divergent_if_else(ctx
, &ic
);
10191 end_divergent_if(ctx
, &ic
);
10194 } /* end namespace */
10196 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10198 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10199 Builder
bld(ctx
->program
, ctx
->block
);
10200 constexpr unsigned hs_idx
= 1u;
10201 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10202 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10203 Operand((8u << 16) | (hs_idx
* 8u)));
10204 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10206 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10208 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10209 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10210 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10211 ls_has_nonzero_hs_threads
);
10212 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10213 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10214 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10215 ls_has_nonzero_hs_threads
);
10216 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10217 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10218 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10219 ls_has_nonzero_hs_threads
);
10221 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10222 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10223 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10226 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10228 /* Split all arguments except for the first (ring_offsets) and the last
10229 * (exec) so that the dead channels don't stay live throughout the program.
10231 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10232 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10233 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10234 startpgm
->definitions
[i
].regClass().size());
10239 void handle_bc_optimize(isel_context
*ctx
)
10241 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10242 Builder
bld(ctx
->program
, ctx
->block
);
10243 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10244 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10245 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10246 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10247 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10248 if (uses_center
&& uses_centroid
) {
10249 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10250 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10252 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10254 for (unsigned i
= 0; i
< 2; i
++) {
10255 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10256 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10257 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10258 persp_centroid
, persp_center
, sel
);
10260 ctx
->persp_centroid
= bld
.tmp(v2
);
10261 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10262 Operand(new_coord
[0]), Operand(new_coord
[1]));
10263 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10266 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10268 for (unsigned i
= 0; i
< 2; i
++) {
10269 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10270 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10271 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10272 linear_centroid
, linear_center
, sel
);
10274 ctx
->linear_centroid
= bld
.tmp(v2
);
10275 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10276 Operand(new_coord
[0]), Operand(new_coord
[1]));
10277 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10282 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10284 Program
*program
= ctx
->program
;
10286 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10288 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10289 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10290 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10291 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10292 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10294 program
->next_fp_mode
.must_flush_denorms32
=
10295 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10296 program
->next_fp_mode
.must_flush_denorms16_64
=
10297 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10298 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10300 program
->next_fp_mode
.care_about_round32
=
10301 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10303 program
->next_fp_mode
.care_about_round16_64
=
10304 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10305 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10307 /* default to preserving fp16 and fp64 denorms, since it's free */
10308 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10309 program
->next_fp_mode
.denorm16_64
= 0;
10311 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10313 /* preserving fp32 denorms is expensive, so only do it if asked */
10314 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10315 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10317 program
->next_fp_mode
.denorm32
= 0;
10319 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10320 program
->next_fp_mode
.round32
= fp_round_tz
;
10322 program
->next_fp_mode
.round32
= fp_round_ne
;
10324 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10325 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10327 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10329 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10332 void cleanup_cfg(Program
*program
)
10334 /* create linear_succs/logical_succs */
10335 for (Block
& BB
: program
->blocks
) {
10336 for (unsigned idx
: BB
.linear_preds
)
10337 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10338 for (unsigned idx
: BB
.logical_preds
)
10339 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10343 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10345 Builder
bld(ctx
->program
, ctx
->block
);
10347 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10348 Temp count
= i
== 0
10349 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10350 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10351 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10353 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10356 if (ctx
->program
->wave_size
== 64) {
10357 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10358 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10359 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10361 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10362 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10368 bool ngg_early_prim_export(isel_context
*ctx
)
10370 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10374 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10376 Builder
bld(ctx
->program
, ctx
->block
);
10378 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10379 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10381 /* Get the id of the current wave within the threadgroup (workgroup) */
10382 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10383 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10385 /* Execute the following code only on the first wave (wave id 0),
10386 * use the SCC def to tell if the wave id is zero or not.
10388 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10390 begin_uniform_if_then(ctx
, &ic
, cond
);
10391 begin_uniform_if_else(ctx
, &ic
);
10392 bld
.reset(ctx
->block
);
10394 /* Number of vertices output by VS/TES */
10395 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10396 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10397 /* Number of primitives output by VS/TES */
10398 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10399 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10401 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10402 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10403 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10405 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10406 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10408 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10409 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10411 end_uniform_if(ctx
, &ic
);
10414 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10416 Builder
bld(ctx
->program
, ctx
->block
);
10418 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10419 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10422 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10425 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10426 assert(vtxindex
[i
].id());
10429 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10433 /* The initial edge flag is always false in tess eval shaders. */
10434 if (ctx
->stage
== ngg_vertex_gs
) {
10435 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10436 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10440 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10445 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10447 Builder
bld(ctx
->program
, ctx
->block
);
10448 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10450 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10451 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10452 false /* compressed */, true/* done */, false /* valid mask */);
10455 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10457 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10458 * These must always come before VS exports.
10460 * It is recommended to do these as early as possible. They can be at the beginning when
10461 * there is no SW GS and the shader doesn't write edge flags.
10465 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10466 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10468 Builder
bld(ctx
->program
, ctx
->block
);
10469 constexpr unsigned max_vertices_per_primitive
= 3;
10470 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10472 if (ctx
->stage
== ngg_vertex_gs
) {
10473 /* TODO: optimize for points & lines */
10474 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10475 if (ctx
->shader
->info
.tess
.point_mode
)
10476 num_vertices_per_primitive
= 1;
10477 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10478 num_vertices_per_primitive
= 2;
10480 unreachable("Unsupported NGG shader stage");
10483 Temp vtxindex
[max_vertices_per_primitive
];
10484 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10485 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10486 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10487 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10488 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10489 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10490 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10491 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10493 /* Export primitive data to the index buffer. */
10494 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10496 /* Export primitive ID. */
10497 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10498 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10499 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10500 Temp provoking_vtx_index
= vtxindex
[0];
10501 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10503 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10506 begin_divergent_if_else(ctx
, &ic
);
10507 end_divergent_if(ctx
, &ic
);
10510 void ngg_emit_nogs_output(isel_context
*ctx
)
10512 /* Emits NGG GS output, for stages that don't have SW GS. */
10515 Builder
bld(ctx
->program
, ctx
->block
);
10516 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10518 /* NGG streamout is currently disabled by default. */
10519 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10521 if (late_prim_export
) {
10522 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10523 create_export_phis(ctx
);
10524 /* Do what we need to do in the GS threads. */
10525 ngg_emit_nogs_gsthreads(ctx
);
10527 /* What comes next should be executed on ES threads. */
10528 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10529 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10530 bld
.reset(ctx
->block
);
10533 /* Export VS outputs */
10534 ctx
->block
->kind
|= block_kind_export_end
;
10535 create_vs_exports(ctx
);
10537 /* Export primitive ID */
10538 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10541 if (ctx
->stage
== ngg_vertex_gs
) {
10542 /* Wait for GS threads to store primitive ID in LDS. */
10543 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10544 bld
.sopp(aco_opcode::s_barrier
);
10546 /* Calculate LDS address where the GS threads stored the primitive ID. */
10547 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10548 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10549 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10550 Temp wave_id_mul
= bld
.v_mul_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10551 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10552 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10554 /* Load primitive ID from LDS. */
10555 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10556 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10557 /* TES: Just use the patch ID as the primitive ID. */
10558 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10560 unreachable("unsupported NGG shader stage.");
10563 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10564 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10566 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10569 if (late_prim_export
) {
10570 begin_divergent_if_else(ctx
, &ic
);
10571 end_divergent_if(ctx
, &ic
);
10572 bld
.reset(ctx
->block
);
10576 void select_program(Program
*program
,
10577 unsigned shader_count
,
10578 struct nir_shader
*const *shaders
,
10579 ac_shader_config
* config
,
10580 struct radv_shader_args
*args
)
10582 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10583 if_context ic_merged_wave_info
;
10584 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10586 for (unsigned i
= 0; i
< shader_count
; i
++) {
10587 nir_shader
*nir
= shaders
[i
];
10588 init_context(&ctx
, nir
);
10590 setup_fp_mode(&ctx
, nir
);
10593 /* needs to be after init_context() for FS */
10594 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10595 append_logical_start(ctx
.block
);
10597 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10598 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10600 split_arguments(&ctx
, startpgm
);
10604 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10606 if (ngg_early_prim_export(&ctx
))
10607 ngg_emit_nogs_gsthreads(&ctx
);
10610 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10611 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10612 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10613 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10614 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10615 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10616 ctx
.stage
== tess_eval_geometry_gs
));
10618 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10619 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10620 if (check_merged_wave_info
) {
10621 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10622 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10626 Builder
bld(ctx
.program
, ctx
.block
);
10628 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10629 bld
.sopp(aco_opcode::s_barrier
);
10631 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10632 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10634 } else if (ctx
.stage
== geometry_gs
)
10635 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10637 if (ctx
.stage
== fragment_fs
)
10638 handle_bc_optimize(&ctx
);
10640 visit_cf_list(&ctx
, &func
->body
);
10642 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10643 emit_streamout(&ctx
, 0);
10645 if (ctx
.stage
& hw_vs
) {
10646 create_vs_exports(&ctx
);
10647 ctx
.block
->kind
|= block_kind_export_end
;
10648 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10649 ngg_emit_nogs_output(&ctx
);
10650 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10651 Builder
bld(ctx
.program
, ctx
.block
);
10652 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10653 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10654 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10655 write_tcs_tess_factors(&ctx
);
10658 if (ctx
.stage
== fragment_fs
) {
10659 create_fs_exports(&ctx
);
10660 ctx
.block
->kind
|= block_kind_export_end
;
10663 if (endif_merged_wave_info
) {
10664 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10665 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10668 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10669 ngg_emit_nogs_output(&ctx
);
10671 ralloc_free(ctx
.divergent_vals
);
10673 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10674 /* Outputs of the previous stage are inputs to the next stage */
10675 ctx
.inputs
= ctx
.outputs
;
10676 ctx
.outputs
= shader_io_state();
10680 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10682 append_logical_end(ctx
.block
);
10683 ctx
.block
->kind
|= block_kind_uniform
;
10684 Builder
bld(ctx
.program
, ctx
.block
);
10685 if (ctx
.program
->wb_smem_l1_on_end
)
10686 bld
.smem(aco_opcode::s_dcache_wb
, false);
10687 bld
.sopp(aco_opcode::s_endpgm
);
10689 cleanup_cfg(program
);
10692 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10693 ac_shader_config
* config
,
10694 struct radv_shader_args
*args
)
10696 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10698 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
10699 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
10700 program
->next_fp_mode
.must_flush_denorms32
= false;
10701 program
->next_fp_mode
.must_flush_denorms16_64
= false;
10702 program
->next_fp_mode
.care_about_round32
= false;
10703 program
->next_fp_mode
.care_about_round16_64
= false;
10704 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10705 program
->next_fp_mode
.denorm32
= 0;
10706 program
->next_fp_mode
.round32
= fp_round_ne
;
10707 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10708 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10710 add_startpgm(&ctx
);
10711 append_logical_start(ctx
.block
);
10713 Builder
bld(ctx
.program
, ctx
.block
);
10715 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10717 Operand
stream_id(0u);
10718 if (args
->shader_info
->so
.num_outputs
)
10719 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10720 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10722 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10724 std::stack
<Block
> endif_blocks
;
10726 for (unsigned stream
= 0; stream
< 4; stream
++) {
10727 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10730 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10731 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10734 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10736 unsigned BB_if_idx
= ctx
.block
->index
;
10737 Block BB_endif
= Block();
10738 if (!stream_id
.isConstant()) {
10740 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10741 append_logical_end(ctx
.block
);
10742 ctx
.block
->kind
|= block_kind_uniform
;
10743 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
10745 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10747 ctx
.block
= ctx
.program
->create_and_insert_block();
10748 add_edge(BB_if_idx
, ctx
.block
);
10749 bld
.reset(ctx
.block
);
10750 append_logical_start(ctx
.block
);
10753 unsigned offset
= 0;
10754 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10755 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10758 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10759 unsigned length
= util_last_bit(output_usage_mask
);
10760 for (unsigned j
= 0; j
< length
; ++j
) {
10761 if (!(output_usage_mask
& (1 << j
)))
10764 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10765 Temp voffset
= vtx_offset
;
10766 if (const_offset
>= 4096u) {
10767 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10768 const_offset
%= 4096u;
10771 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10772 mubuf
->definitions
[0] = bld
.def(v1
);
10773 mubuf
->operands
[0] = Operand(gsvs_ring
);
10774 mubuf
->operands
[1] = Operand(voffset
);
10775 mubuf
->operands
[2] = Operand(0u);
10776 mubuf
->offen
= true;
10777 mubuf
->offset
= const_offset
;
10780 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
10781 mubuf
->barrier
= barrier_none
;
10782 mubuf
->can_reorder
= true;
10784 ctx
.outputs
.mask
[i
] |= 1 << j
;
10785 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
10787 bld
.insert(std::move(mubuf
));
10793 if (args
->shader_info
->so
.num_outputs
) {
10794 emit_streamout(&ctx
, stream
);
10795 bld
.reset(ctx
.block
);
10799 create_vs_exports(&ctx
);
10800 ctx
.block
->kind
|= block_kind_export_end
;
10803 if (!stream_id
.isConstant()) {
10804 append_logical_end(ctx
.block
);
10806 /* branch from then block to endif block */
10807 bld
.branch(aco_opcode::p_branch
);
10808 add_edge(ctx
.block
->index
, &BB_endif
);
10809 ctx
.block
->kind
|= block_kind_uniform
;
10811 /* emit else block */
10812 ctx
.block
= ctx
.program
->create_and_insert_block();
10813 add_edge(BB_if_idx
, ctx
.block
);
10814 bld
.reset(ctx
.block
);
10815 append_logical_start(ctx
.block
);
10817 endif_blocks
.push(std::move(BB_endif
));
10821 while (!endif_blocks
.empty()) {
10822 Block BB_endif
= std::move(endif_blocks
.top());
10823 endif_blocks
.pop();
10825 Block
*BB_else
= ctx
.block
;
10827 append_logical_end(BB_else
);
10828 /* branch from else block to endif block */
10829 bld
.branch(aco_opcode::p_branch
);
10830 add_edge(BB_else
->index
, &BB_endif
);
10831 BB_else
->kind
|= block_kind_uniform
;
10833 /** emit endif merge block */
10834 ctx
.block
= program
->insert_block(std::move(BB_endif
));
10835 bld
.reset(ctx
.block
);
10836 append_logical_start(ctx
.block
);
10839 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10841 append_logical_end(ctx
.block
);
10842 ctx
.block
->kind
|= block_kind_uniform
;
10843 bld
.sopp(aco_opcode::s_endpgm
);
10845 cleanup_cfg(program
);