src/amd/compiler/aco_instruction_selection.cpp

   1 /*
   2  * Copyright © 2018 Valve Corporation
   3  * Copyright © 2018 Google
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <algorithm>
  27 #include <array>
  28 #include <stack>
  29 #include <map>
  30
  31 #include "ac_shader_util.h"
  32 #include "aco_ir.h"
  33 #include "aco_builder.h"
  34 #include "aco_interface.h"
  35 #include "aco_instruction_selection_setup.cpp"
  36 #include "util/fast_idiv_by_const.h"
  37
  38 namespace aco {
  39 namespace {
  40
  41 class loop_info_RAII {
  42    isel_context* ctx;
  43    unsigned header_idx_old;
  44    Block* exit_old;
  45    bool divergent_cont_old;
  46    bool divergent_branch_old;
  47    bool divergent_if_old;
  48
  49 public:
  50    loop_info_RAII(isel_context* ctx, unsigned loop_header_idx, Block* loop_exit)
  51       : ctx(ctx),
  52         header_idx_old(ctx->cf_info.parent_loop.header_idx), exit_old(ctx->cf_info.parent_loop.exit),
  53         divergent_cont_old(ctx->cf_info.parent_loop.has_divergent_continue),
  54         divergent_branch_old(ctx->cf_info.parent_loop.has_divergent_branch),
  55         divergent_if_old(ctx->cf_info.parent_if.is_divergent)
  56    {
  57       ctx->cf_info.parent_loop.header_idx = loop_header_idx;
  58       ctx->cf_info.parent_loop.exit = loop_exit;
  59       ctx->cf_info.parent_loop.has_divergent_continue = false;
  60       ctx->cf_info.parent_loop.has_divergent_branch = false;
  61       ctx->cf_info.parent_if.is_divergent = false;
  62       ctx->cf_info.loop_nest_depth = ctx->cf_info.loop_nest_depth + 1;
  63    }
  64
  65    ~loop_info_RAII()
  66    {
  67       ctx->cf_info.parent_loop.header_idx = header_idx_old;
  68       ctx->cf_info.parent_loop.exit = exit_old;
  69       ctx->cf_info.parent_loop.has_divergent_continue = divergent_cont_old;
  70       ctx->cf_info.parent_loop.has_divergent_branch = divergent_branch_old;
  71       ctx->cf_info.parent_if.is_divergent = divergent_if_old;
  72       ctx->cf_info.loop_nest_depth = ctx->cf_info.loop_nest_depth - 1;
  73       if (!ctx->cf_info.loop_nest_depth && !ctx->cf_info.parent_if.is_divergent)
  74          ctx->cf_info.exec_potentially_empty_discard = false;
  75    }
  76 };
  77
  78 struct if_context {
  79    Temp cond;
  80
  81    bool divergent_old;
  82    bool exec_potentially_empty_discard_old;
  83    bool exec_potentially_empty_break_old;
  84    uint16_t exec_potentially_empty_break_depth_old;
  85
  86    unsigned BB_if_idx;
  87    unsigned invert_idx;
  88    bool then_branch_divergent;
  89    Block BB_invert;
  90    Block BB_endif;
  91 };
  92
  93 static void visit_cf_list(struct isel_context *ctx,
  94                           struct exec_list *list);
  95
  96 static void add_logical_edge(unsigned pred_idx, Block *succ)
  97 {
  98    succ->logical_preds.emplace_back(pred_idx);
  99 }
 100
 101
 102 static void add_linear_edge(unsigned pred_idx, Block *succ)
 103 {
 104    succ->linear_preds.emplace_back(pred_idx);
 105 }
 106
 107 static void add_edge(unsigned pred_idx, Block *succ)
 108 {
 109    add_logical_edge(pred_idx, succ);
 110    add_linear_edge(pred_idx, succ);
 111 }
 112
 113 static void append_logical_start(Block *b)
 114 {
 115    Builder(NULL, b).pseudo(aco_opcode::p_logical_start);
 116 }
 117
 118 static void append_logical_end(Block *b)
 119 {
 120    Builder(NULL, b).pseudo(aco_opcode::p_logical_end);
 121 }
 122
 123 Temp get_ssa_temp(struct isel_context *ctx, nir_ssa_def *def)
 124 {
 125    assert(ctx->allocated[def->index].id());
 126    return ctx->allocated[def->index];
 127 }
 128
 129 Temp emit_mbcnt(isel_context *ctx, Definition dst,
 130                 Operand mask_lo = Operand((uint32_t) -1), Operand mask_hi = Operand((uint32_t) -1))
 131 {
 132    Builder bld(ctx->program, ctx->block);
 133    Definition lo_def = ctx->program->wave_size == 32 ? dst : bld.def(v1);
 134    Temp thread_id_lo = bld.vop3(aco_opcode::v_mbcnt_lo_u32_b32, lo_def, mask_lo, Operand(0u));
 135
 136    if (ctx->program->wave_size == 32) {
 137       return thread_id_lo;
 138    } else {
 139       Temp thread_id_hi = bld.vop3(aco_opcode::v_mbcnt_hi_u32_b32, dst, mask_hi, thread_id_lo);
 140       return thread_id_hi;
 141    }
 142 }
 143
 144 Temp emit_wqm(isel_context *ctx, Temp src, Temp dst=Temp(0, s1), bool program_needs_wqm = false)
 145 {
 146    Builder bld(ctx->program, ctx->block);
 147
 148    if (!dst.id())
 149       dst = bld.tmp(src.regClass());
 150
 151    assert(src.size() == dst.size());
 152
 153    if (ctx->stage != fragment_fs) {
 154       if (!dst.id())
 155          return src;
 156
 157       bld.copy(Definition(dst), src);
 158       return dst;
 159    }
 160
 161    bld.pseudo(aco_opcode::p_wqm, Definition(dst), src);
 162    ctx->program->needs_wqm |= program_needs_wqm;
 163    return dst;
 164 }
 165
 166 static Temp emit_bpermute(isel_context *ctx, Builder &bld, Temp index, Temp data)
 167 {
 168    if (index.regClass() == s1)
 169       return bld.readlane(bld.def(s1), data, index);
 170
 171    Temp index_x4 = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), index);
 172
 173    /* Currently not implemented on GFX6-7 */
 174    assert(ctx->options->chip_class >= GFX8);
 175
 176    if (ctx->options->chip_class <= GFX9 || ctx->program->wave_size == 32) {
 177       return bld.ds(aco_opcode::ds_bpermute_b32, bld.def(v1), index_x4, data);
 178    }
 179
 180    /* GFX10, wave64 mode:
 181     * The bpermute instruction is limited to half-wave operation, which means that it can't
 182     * properly support subgroup shuffle like older generations (or wave32 mode), so we
 183     * emulate it here.
 184     */
 185    if (!ctx->has_gfx10_wave64_bpermute) {
 186       ctx->has_gfx10_wave64_bpermute = true;
 187       ctx->program->config->num_shared_vgprs = 8; /* Shared VGPRs are allocated in groups of 8 */
 188       ctx->program->vgpr_limit -= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
 189    }
 190
 191    Temp lane_id = emit_mbcnt(ctx, bld.def(v1));
 192    Temp lane_is_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x20u), lane_id);
 193    Temp index_is_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x20u), index);
 194    Temp cmp = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm, vcc), lane_is_hi, index_is_hi);
 195
 196    return bld.reduction(aco_opcode::p_wave64_bpermute, bld.def(v1), bld.def(s2), bld.def(s1, scc),
 197                         bld.vcc(cmp), Operand(v2.as_linear()), index_x4, data, gfx10_wave64_bpermute);
 198 }
 199
 200 Temp as_vgpr(isel_context *ctx, Temp val)
 201 {
 202    if (val.type() == RegType::sgpr) {
 203       Builder bld(ctx->program, ctx->block);
 204       return bld.copy(bld.def(RegType::vgpr, val.size()), val);
 205    }
 206    assert(val.type() == RegType::vgpr);
 207    return val;
 208 }
 209
 210 //assumes a != 0xffffffff
 211 void emit_v_div_u32(isel_context *ctx, Temp dst, Temp a, uint32_t b)
 212 {
 213    assert(b != 0);
 214    Builder bld(ctx->program, ctx->block);
 215
 216    if (util_is_power_of_two_or_zero(b)) {
 217       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(dst), Operand((uint32_t)util_logbase2(b)), a);
 218       return;
 219    }
 220
 221    util_fast_udiv_info info = util_compute_fast_udiv_info(b, 32, 32);
 222
 223    assert(info.multiplier <= 0xffffffff);
 224
 225    bool pre_shift = info.pre_shift != 0;
 226    bool increment = info.increment != 0;
 227    bool multiply = true;
 228    bool post_shift = info.post_shift != 0;
 229
 230    if (!pre_shift && !increment && !multiply && !post_shift) {
 231       bld.vop1(aco_opcode::v_mov_b32, Definition(dst), a);
 232       return;
 233    }
 234
 235    Temp pre_shift_dst = a;
 236    if (pre_shift) {
 237       pre_shift_dst = (increment || multiply || post_shift) ? bld.tmp(v1) : dst;
 238       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(pre_shift_dst), Operand((uint32_t)info.pre_shift), a);
 239    }
 240
 241    Temp increment_dst = pre_shift_dst;
 242    if (increment) {
 243       increment_dst = (post_shift || multiply) ? bld.tmp(v1) : dst;
 244       bld.vadd32(Definition(increment_dst), Operand((uint32_t) info.increment), pre_shift_dst);
 245    }
 246
 247    Temp multiply_dst = increment_dst;
 248    if (multiply) {
 249       multiply_dst = post_shift ? bld.tmp(v1) : dst;
 250       bld.vop3(aco_opcode::v_mul_hi_u32, Definition(multiply_dst), increment_dst,
 251                bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand((uint32_t)info.multiplier)));
 252    }
 253
 254    if (post_shift) {
 255       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(dst), Operand((uint32_t)info.post_shift), multiply_dst);
 256    }
 257 }
 258
 259 void emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, Temp dst)
 260 {
 261    Builder bld(ctx->program, ctx->block);
 262    bld.pseudo(aco_opcode::p_extract_vector, Definition(dst), src, Operand(idx));
 263 }
 264
 265
 266 Temp emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, RegClass dst_rc)
 267 {
 268    /* no need to extract the whole vector */
 269    if (src.regClass() == dst_rc) {
 270       assert(idx == 0);
 271       return src;
 272    }
 273    assert(src.size() > idx);
 274    Builder bld(ctx->program, ctx->block);
 275    auto it = ctx->allocated_vec.find(src.id());
 276    /* the size check needs to be early because elements other than 0 may be garbage */
 277    if (it != ctx->allocated_vec.end() && it->second[0].size() == dst_rc.size()) {
 278       if (it->second[idx].regClass() == dst_rc) {
 279          return it->second[idx];
 280       } else {
 281          assert(dst_rc.size() == it->second[idx].regClass().size());
 282          assert(dst_rc.type() == RegType::vgpr && it->second[idx].type() == RegType::sgpr);
 283          return bld.copy(bld.def(dst_rc), it->second[idx]);
 284       }
 285    }
 286
 287    if (src.size() == dst_rc.size()) {
 288       assert(idx == 0);
 289       return bld.copy(bld.def(dst_rc), src);
 290    } else {
 291       Temp dst = bld.tmp(dst_rc);
 292       emit_extract_vector(ctx, src, idx, dst);
 293       return dst;
 294    }
 295 }
 296
 297 void emit_split_vector(isel_context* ctx, Temp vec_src, unsigned num_components)
 298 {
 299    if (num_components == 1)
 300       return;
 301    if (ctx->allocated_vec.find(vec_src.id()) != ctx->allocated_vec.end())
 302       return;
 303    aco_ptr<Pseudo_instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector, Format::PSEUDO, 1, num_components)};
 304    split->operands[0] = Operand(vec_src);
 305    std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 306    for (unsigned i = 0; i < num_components; i++) {
 307       elems[i] = {ctx->program->allocateId(), RegClass(vec_src.type(), vec_src.size() / num_components)};
 308       split->definitions[i] = Definition(elems[i]);
 309    }
 310    ctx->block->instructions.emplace_back(std::move(split));
 311    ctx->allocated_vec.emplace(vec_src.id(), elems);
 312 }
 313
 314 /* This vector expansion uses a mask to determine which elements in the new vector
 315  * come from the original vector. The other elements are undefined. */
 316 void expand_vector(isel_context* ctx, Temp vec_src, Temp dst, unsigned num_components, unsigned mask)
 317 {
 318    emit_split_vector(ctx, vec_src, util_bitcount(mask));
 319
 320    if (vec_src == dst)
 321       return;
 322
 323    Builder bld(ctx->program, ctx->block);
 324    if (num_components == 1) {
 325       if (dst.type() == RegType::sgpr)
 326          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec_src);
 327       else
 328          bld.copy(Definition(dst), vec_src);
 329       return;
 330    }
 331
 332    unsigned component_size = dst.size() / num_components;
 333    std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 334
 335    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1)};
 336    vec->definitions[0] = Definition(dst);
 337    unsigned k = 0;
 338    for (unsigned i = 0; i < num_components; i++) {
 339       if (mask & (1 << i)) {
 340          Temp src = emit_extract_vector(ctx, vec_src, k++, RegClass(vec_src.type(), component_size));
 341          if (dst.type() == RegType::sgpr)
 342             src = bld.as_uniform(src);
 343          vec->operands[i] = Operand(src);
 344       } else {
 345          vec->operands[i] = Operand(0u);
 346       }
 347       elems[i] = vec->operands[i].getTemp();
 348    }
 349    ctx->block->instructions.emplace_back(std::move(vec));
 350    ctx->allocated_vec.emplace(dst.id(), elems);
 351 }
 352
 353 Temp bool_to_vector_condition(isel_context *ctx, Temp val, Temp dst = Temp(0, s2))
 354 {
 355    Builder bld(ctx->program, ctx->block);
 356    if (!dst.id())
 357       dst = bld.tmp(bld.lm);
 358
 359    assert(val.regClass() == s1);
 360    assert(dst.regClass() == bld.lm);
 361
 362    return bld.sop2(Builder::s_cselect, Definition(dst), Operand((uint32_t) -1), Operand(0u), bld.scc(val));
 363 }
 364
 365 Temp bool_to_scalar_condition(isel_context *ctx, Temp val, Temp dst = Temp(0, s1))
 366 {
 367    Builder bld(ctx->program, ctx->block);
 368    if (!dst.id())
 369       dst = bld.tmp(s1);
 370
 371    assert(val.regClass() == bld.lm);
 372    assert(dst.regClass() == s1);
 373
 374    /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
 375    Temp tmp = bld.tmp(s1);
 376    bld.sop2(Builder::s_and, bld.def(bld.lm), bld.scc(Definition(tmp)), val, Operand(exec, bld.lm));
 377    return emit_wqm(ctx, tmp, dst);
 378 }
 379
 380 Temp get_alu_src(struct isel_context *ctx, nir_alu_src src, unsigned size=1)
 381 {
 382    if (src.src.ssa->num_components == 1 && src.swizzle[0] == 0 && size == 1)
 383       return get_ssa_temp(ctx, src.src.ssa);
 384
 385    if (src.src.ssa->num_components == size) {
 386       bool identity_swizzle = true;
 387       for (unsigned i = 0; identity_swizzle && i < size; i++) {
 388          if (src.swizzle[i] != i)
 389             identity_swizzle = false;
 390       }
 391       if (identity_swizzle)
 392          return get_ssa_temp(ctx, src.src.ssa);
 393    }
 394
 395    Temp vec = get_ssa_temp(ctx, src.src.ssa);
 396    unsigned elem_size = vec.size() / src.src.ssa->num_components;
 397    assert(elem_size > 0); /* TODO: 8 and 16-bit vectors not supported */
 398    assert(vec.size() % elem_size == 0);
 399
 400    RegClass elem_rc = RegClass(vec.type(), elem_size);
 401    if (size == 1) {
 402       return emit_extract_vector(ctx, vec, src.swizzle[0], elem_rc);
 403    } else {
 404       assert(size <= 4);
 405       std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 406       aco_ptr<Pseudo_instruction> vec_instr{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, size, 1)};
 407       for (unsigned i = 0; i < size; ++i) {
 408          elems[i] = emit_extract_vector(ctx, vec, src.swizzle[i], elem_rc);
 409          vec_instr->operands[i] = Operand{elems[i]};
 410       }
 411       Temp dst{ctx->program->allocateId(), RegClass(vec.type(), elem_size * size)};
 412       vec_instr->definitions[0] = Definition(dst);
 413       ctx->block->instructions.emplace_back(std::move(vec_instr));
 414       ctx->allocated_vec.emplace(dst.id(), elems);
 415       return dst;
 416    }
 417 }
 418
 419 Temp convert_pointer_to_64_bit(isel_context *ctx, Temp ptr)
 420 {
 421    if (ptr.size() == 2)
 422       return ptr;
 423    Builder bld(ctx->program, ctx->block);
 424    if (ptr.type() == RegType::vgpr)
 425       ptr = bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), ptr);
 426    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s2),
 427                      ptr, Operand((unsigned)ctx->options->address32_hi));
 428 }
 429
 430 void emit_sop2_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst, bool writes_scc)
 431 {
 432    aco_ptr<SOP2_instruction> sop2{create_instruction<SOP2_instruction>(op, Format::SOP2, 2, writes_scc ? 2 : 1)};
 433    sop2->operands[0] = Operand(get_alu_src(ctx, instr->src[0]));
 434    sop2->operands[1] = Operand(get_alu_src(ctx, instr->src[1]));
 435    sop2->definitions[0] = Definition(dst);
 436    if (writes_scc)
 437       sop2->definitions[1] = Definition(ctx->program->allocateId(), scc, s1);
 438    ctx->block->instructions.emplace_back(std::move(sop2));
 439 }
 440
 441 void emit_vop2_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst,
 442                            bool commutative, bool swap_srcs=false, bool flush_denorms = false)
 443 {
 444    Builder bld(ctx->program, ctx->block);
 445    Temp src0 = get_alu_src(ctx, instr->src[swap_srcs ? 1 : 0]);
 446    Temp src1 = get_alu_src(ctx, instr->src[swap_srcs ? 0 : 1]);
 447    if (src1.type() == RegType::sgpr) {
 448       if (commutative && src0.type() == RegType::vgpr) {
 449          Temp t = src0;
 450          src0 = src1;
 451          src1 = t;
 452       } else if (src0.type() == RegType::vgpr &&
 453                  op != aco_opcode::v_madmk_f32 &&
 454                  op != aco_opcode::v_madak_f32 &&
 455                  op != aco_opcode::v_madmk_f16 &&
 456                  op != aco_opcode::v_madak_f16) {
 457          /* If the instruction is not commutative, we emit a VOP3A instruction */
 458          bld.vop2_e64(op, Definition(dst), src0, src1);
 459          return;
 460       } else {
 461          src1 = bld.copy(bld.def(RegType::vgpr, src1.size()), src1); //TODO: as_vgpr
 462       }
 463    }
 464
 465    if (flush_denorms && ctx->program->chip_class < GFX9) {
 466       assert(dst.size() == 1);
 467       Temp tmp = bld.vop2(op, bld.def(v1), src0, src1);
 468       bld.vop2(aco_opcode::v_mul_f32, Definition(dst), Operand(0x3f800000u), tmp);
 469    } else {
 470       bld.vop2(op, Definition(dst), src0, src1);
 471    }
 472 }
 473
 474 void emit_vop3a_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst,
 475                             bool flush_denorms = false)
 476 {
 477    Temp src0 = get_alu_src(ctx, instr->src[0]);
 478    Temp src1 = get_alu_src(ctx, instr->src[1]);
 479    Temp src2 = get_alu_src(ctx, instr->src[2]);
 480
 481    /* ensure that the instruction has at most 1 sgpr operand
 482     * The optimizer will inline constants for us */
 483    if (src0.type() == RegType::sgpr && src1.type() == RegType::sgpr)
 484       src0 = as_vgpr(ctx, src0);
 485    if (src1.type() == RegType::sgpr && src2.type() == RegType::sgpr)
 486       src1 = as_vgpr(ctx, src1);
 487    if (src2.type() == RegType::sgpr && src0.type() == RegType::sgpr)
 488       src2 = as_vgpr(ctx, src2);
 489
 490    Builder bld(ctx->program, ctx->block);
 491    if (flush_denorms && ctx->program->chip_class < GFX9) {
 492       assert(dst.size() == 1);
 493       Temp tmp = bld.vop3(op, Definition(dst), src0, src1, src2);
 494       bld.vop2(aco_opcode::v_mul_f32, Definition(dst), Operand(0x3f800000u), tmp);
 495    } else {
 496       bld.vop3(op, Definition(dst), src0, src1, src2);
 497    }
 498 }
 499
 500 void emit_vop1_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 501 {
 502    Builder bld(ctx->program, ctx->block);
 503    bld.vop1(op, Definition(dst), get_alu_src(ctx, instr->src[0]));
 504 }
 505
 506 void emit_vopc_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 507 {
 508    Temp src0 = get_alu_src(ctx, instr->src[0]);
 509    Temp src1 = get_alu_src(ctx, instr->src[1]);
 510    assert(src0.size() == src1.size());
 511
 512    aco_ptr<Instruction> vopc;
 513    if (src1.type() == RegType::sgpr) {
 514       if (src0.type() == RegType::vgpr) {
 515          /* to swap the operands, we might also have to change the opcode */
 516          switch (op) {
 517             case aco_opcode::v_cmp_lt_f32:
 518                op = aco_opcode::v_cmp_gt_f32;
 519                break;
 520             case aco_opcode::v_cmp_ge_f32:
 521                op = aco_opcode::v_cmp_le_f32;
 522                break;
 523             case aco_opcode::v_cmp_lt_i32:
 524                op = aco_opcode::v_cmp_gt_i32;
 525                break;
 526             case aco_opcode::v_cmp_ge_i32:
 527                op = aco_opcode::v_cmp_le_i32;
 528                break;
 529             case aco_opcode::v_cmp_lt_u32:
 530                op = aco_opcode::v_cmp_gt_u32;
 531                break;
 532             case aco_opcode::v_cmp_ge_u32:
 533                op = aco_opcode::v_cmp_le_u32;
 534                break;
 535             case aco_opcode::v_cmp_lt_f64:
 536                op = aco_opcode::v_cmp_gt_f64;
 537                break;
 538             case aco_opcode::v_cmp_ge_f64:
 539                op = aco_opcode::v_cmp_le_f64;
 540                break;
 541             case aco_opcode::v_cmp_lt_i64:
 542                op = aco_opcode::v_cmp_gt_i64;
 543                break;
 544             case aco_opcode::v_cmp_ge_i64:
 545                op = aco_opcode::v_cmp_le_i64;
 546                break;
 547             case aco_opcode::v_cmp_lt_u64:
 548                op = aco_opcode::v_cmp_gt_u64;
 549                break;
 550             case aco_opcode::v_cmp_ge_u64:
 551                op = aco_opcode::v_cmp_le_u64;
 552                break;
 553             default: /* eq and ne are commutative */
 554                break;
 555          }
 556          Temp t = src0;
 557          src0 = src1;
 558          src1 = t;
 559       } else {
 560          src1 = as_vgpr(ctx, src1);
 561       }
 562    }
 563
 564    Builder bld(ctx->program, ctx->block);
 565    bld.vopc(op, bld.hint_vcc(Definition(dst)), src0, src1);
 566 }
 567
 568 void emit_sopc_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 569 {
 570    Temp src0 = get_alu_src(ctx, instr->src[0]);
 571    Temp src1 = get_alu_src(ctx, instr->src[1]);
 572    Builder bld(ctx->program, ctx->block);
 573
 574    assert(dst.regClass() == bld.lm);
 575    assert(src0.type() == RegType::sgpr);
 576    assert(src1.type() == RegType::sgpr);
 577    assert(src0.regClass() == src1.regClass());
 578
 579    /* Emit the SALU comparison instruction */
 580    Temp cmp = bld.sopc(op, bld.scc(bld.def(s1)), src0, src1);
 581    /* Turn the result into a per-lane bool */
 582    bool_to_vector_condition(ctx, cmp, dst);
 583 }
 584
 585 void emit_comparison(isel_context *ctx, nir_alu_instr *instr, Temp dst,
 586                      aco_opcode v32_op, aco_opcode v64_op, aco_opcode s32_op = aco_opcode::num_opcodes, aco_opcode s64_op = aco_opcode::num_opcodes)
 587 {
 588    aco_opcode s_op = instr->src[0].src.ssa->bit_size == 64 ? s64_op : s32_op;
 589    aco_opcode v_op = instr->src[0].src.ssa->bit_size == 64 ? v64_op : v32_op;
 590    bool divergent_vals = ctx->divergent_vals[instr->dest.dest.ssa.index];
 591    bool use_valu = s_op == aco_opcode::num_opcodes ||
 592                    divergent_vals ||
 593                    ctx->allocated[instr->src[0].src.ssa->index].type() == RegType::vgpr ||
 594                    ctx->allocated[instr->src[1].src.ssa->index].type() == RegType::vgpr;
 595    aco_opcode op = use_valu ? v_op : s_op;
 596    assert(op != aco_opcode::num_opcodes);
 597    assert(dst.regClass() == ctx->program->lane_mask);
 598
 599    if (use_valu)
 600       emit_vopc_instruction(ctx, instr, op, dst);
 601    else
 602       emit_sopc_instruction(ctx, instr, op, dst);
 603 }
 604
 605 void emit_boolean_logic(isel_context *ctx, nir_alu_instr *instr, Builder::WaveSpecificOpcode op, Temp dst)
 606 {
 607    Builder bld(ctx->program, ctx->block);
 608    Temp src0 = get_alu_src(ctx, instr->src[0]);
 609    Temp src1 = get_alu_src(ctx, instr->src[1]);
 610
 611    assert(dst.regClass() == bld.lm);
 612    assert(src0.regClass() == bld.lm);
 613    assert(src1.regClass() == bld.lm);
 614
 615    bld.sop2(op, Definition(dst), bld.def(s1, scc), src0, src1);
 616 }
 617
 618 void emit_bcsel(isel_context *ctx, nir_alu_instr *instr, Temp dst)
 619 {
 620    Builder bld(ctx->program, ctx->block);
 621    Temp cond = get_alu_src(ctx, instr->src[0]);
 622    Temp then = get_alu_src(ctx, instr->src[1]);
 623    Temp els = get_alu_src(ctx, instr->src[2]);
 624
 625    assert(cond.regClass() == bld.lm);
 626
 627    if (dst.type() == RegType::vgpr) {
 628       aco_ptr<Instruction> bcsel;
 629       if (dst.size() == 1) {
 630          then = as_vgpr(ctx, then);
 631          els = as_vgpr(ctx, els);
 632
 633          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), els, then, cond);
 634       } else if (dst.size() == 2) {
 635          Temp then_lo = bld.tmp(v1), then_hi = bld.tmp(v1);
 636          bld.pseudo(aco_opcode::p_split_vector, Definition(then_lo), Definition(then_hi), then);
 637          Temp else_lo = bld.tmp(v1), else_hi = bld.tmp(v1);
 638          bld.pseudo(aco_opcode::p_split_vector, Definition(else_lo), Definition(else_hi), els);
 639
 640          Temp dst0 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_lo, then_lo, cond);
 641          Temp dst1 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_hi, then_hi, cond);
 642
 643          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
 644       } else {
 645          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 646          nir_print_instr(&instr->instr, stderr);
 647          fprintf(stderr, "\n");
 648       }
 649       return;
 650    }
 651
 652    if (instr->dest.dest.ssa.bit_size == 1) {
 653       assert(dst.regClass() == bld.lm);
 654       assert(then.regClass() == bld.lm);
 655       assert(els.regClass() == bld.lm);
 656    }
 657
 658    if (!ctx->divergent_vals[instr->src[0].src.ssa->index]) { /* uniform condition and values in sgpr */
 659       if (dst.regClass() == s1 || dst.regClass() == s2) {
 660          assert((then.regClass() == s1 || then.regClass() == s2) && els.regClass() == then.regClass());
 661          assert(dst.size() == then.size());
 662          aco_opcode op = dst.regClass() == s1 ? aco_opcode::s_cselect_b32 : aco_opcode::s_cselect_b64;
 663          bld.sop2(op, Definition(dst), then, els, bld.scc(bool_to_scalar_condition(ctx, cond)));
 664       } else {
 665          fprintf(stderr, "Unimplemented uniform bcsel bit size: ");
 666          nir_print_instr(&instr->instr, stderr);
 667          fprintf(stderr, "\n");
 668       }
 669       return;
 670    }
 671
 672    /* divergent boolean bcsel
 673     * this implements bcsel on bools: dst = s0 ? s1 : s2
 674     * are going to be: dst = (s0 & s1) | (~s0 & s2) */
 675    assert(instr->dest.dest.ssa.bit_size == 1);
 676
 677    if (cond.id() != then.id())
 678       then = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), cond, then);
 679
 680    if (cond.id() == els.id())
 681       bld.sop1(Builder::s_mov, Definition(dst), then);
 682    else
 683       bld.sop2(Builder::s_or, Definition(dst), bld.def(s1, scc), then,
 684                bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), els, cond));
 685 }
 686
 687 void emit_scaled_op(isel_context *ctx, Builder& bld, Definition dst, Temp val,
 688                     aco_opcode op, uint32_t undo)
 689 {
 690    /* multiply by 16777216 to handle denormals */
 691    Temp is_denormal = bld.vopc(aco_opcode::v_cmp_class_f32, bld.hint_vcc(bld.def(bld.lm)),
 692                                as_vgpr(ctx, val), bld.copy(bld.def(v1), Operand((1u << 7) | (1u << 4))));
 693    Temp scaled = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x4b800000u), val);
 694    scaled = bld.vop1(op, bld.def(v1), scaled);
 695    scaled = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(undo), scaled);
 696
 697    Temp not_scaled = bld.vop1(op, bld.def(v1), val);
 698
 699    bld.vop2(aco_opcode::v_cndmask_b32, dst, not_scaled, scaled, is_denormal);
 700 }
 701
 702 void emit_rcp(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 703 {
 704    if (ctx->block->fp_mode.denorm32 == 0) {
 705       bld.vop1(aco_opcode::v_rcp_f32, dst, val);
 706       return;
 707    }
 708
 709    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_rcp_f32, 0x4b800000u);
 710 }
 711
 712 void emit_rsq(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 713 {
 714    if (ctx->block->fp_mode.denorm32 == 0) {
 715       bld.vop1(aco_opcode::v_rsq_f32, dst, val);
 716       return;
 717    }
 718
 719    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_rsq_f32, 0x45800000u);
 720 }
 721
 722 void emit_sqrt(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 723 {
 724    if (ctx->block->fp_mode.denorm32 == 0) {
 725       bld.vop1(aco_opcode::v_sqrt_f32, dst, val);
 726       return;
 727    }
 728
 729    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_sqrt_f32, 0x39800000u);
 730 }
 731
 732 void emit_log2(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 733 {
 734    if (ctx->block->fp_mode.denorm32 == 0) {
 735       bld.vop1(aco_opcode::v_log_f32, dst, val);
 736       return;
 737    }
 738
 739    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_log_f32, 0xc1c00000u);
 740 }
 741
 742 Temp emit_trunc_f64(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 743 {
 744    if (ctx->options->chip_class >= GFX7)
 745       return bld.vop1(aco_opcode::v_trunc_f64, Definition(dst), val);
 746
 747    /* GFX6 doesn't support V_TRUNC_F64, lower it. */
 748    /* TODO: create more efficient code! */
 749    if (val.type() == RegType::sgpr)
 750       val = as_vgpr(ctx, val);
 751
 752    /* Split the input value. */
 753    Temp val_lo = bld.tmp(v1), val_hi = bld.tmp(v1);
 754    bld.pseudo(aco_opcode::p_split_vector, Definition(val_lo), Definition(val_hi), val);
 755
 756    /* Extract the exponent and compute the unbiased value. */
 757    Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f64, bld.def(v1), val);
 758
 759    /* Extract the fractional part. */
 760    Temp fract_mask = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(-1u), Operand(0x000fffffu));
 761    fract_mask = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), fract_mask, exponent);
 762
 763    Temp fract_mask_lo = bld.tmp(v1), fract_mask_hi = bld.tmp(v1);
 764    bld.pseudo(aco_opcode::p_split_vector, Definition(fract_mask_lo), Definition(fract_mask_hi), fract_mask);
 765
 766    Temp fract_lo = bld.tmp(v1), fract_hi = bld.tmp(v1);
 767    Temp tmp = bld.vop1(aco_opcode::v_not_b32, bld.def(v1), fract_mask_lo);
 768    fract_lo = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), val_lo, tmp);
 769    tmp = bld.vop1(aco_opcode::v_not_b32, bld.def(v1), fract_mask_hi);
 770    fract_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), val_hi, tmp);
 771
 772    /* Get the sign bit. */
 773    Temp sign = bld.vop2(aco_opcode::v_ashr_i32, bld.def(v1), Operand(31u), val_hi);
 774
 775    /* Decide the operation to apply depending on the unbiased exponent. */
 776    Temp exp_lt0 = bld.vopc_e64(aco_opcode::v_cmp_lt_i32, bld.hint_vcc(bld.def(bld.lm)), exponent, Operand(0u));
 777    Temp dst_lo = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), fract_lo, bld.copy(bld.def(v1), Operand(0u)), exp_lt0);
 778    Temp dst_hi = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), fract_hi, sign, exp_lt0);
 779    Temp exp_gt51 = bld.vopc_e64(aco_opcode::v_cmp_gt_i32, bld.def(s2), exponent, Operand(51u));
 780    dst_lo = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), dst_lo, val_lo, exp_gt51);
 781    dst_hi = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), dst_hi, val_hi, exp_gt51);
 782
 783    return bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst_lo, dst_hi);
 784 }
 785
 786 Temp emit_floor_f64(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 787 {
 788    if (ctx->options->chip_class >= GFX7)
 789       return bld.vop1(aco_opcode::v_floor_f64, Definition(dst), val);
 790
 791    /* GFX6 doesn't support V_FLOOR_F64, lower it. */
 792    Temp src0 = as_vgpr(ctx, val);
 793
 794    Temp mask = bld.copy(bld.def(s1), Operand(3u)); /* isnan */
 795    Temp min_val = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(-1u), Operand(0x3fefffffu));
 796
 797    Temp isnan = bld.vopc_e64(aco_opcode::v_cmp_class_f64, bld.hint_vcc(bld.def(bld.lm)), src0, mask);
 798    Temp fract = bld.vop1(aco_opcode::v_fract_f64, bld.def(v2), src0);
 799    Temp min = bld.vop3(aco_opcode::v_min_f64, bld.def(v2), fract, min_val);
 800
 801    Temp then_lo = bld.tmp(v1), then_hi = bld.tmp(v1);
 802    bld.pseudo(aco_opcode::p_split_vector, Definition(then_lo), Definition(then_hi), src0);
 803    Temp else_lo = bld.tmp(v1), else_hi = bld.tmp(v1);
 804    bld.pseudo(aco_opcode::p_split_vector, Definition(else_lo), Definition(else_hi), min);
 805
 806    Temp dst0 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_lo, then_lo, isnan);
 807    Temp dst1 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_hi, then_hi, isnan);
 808
 809    Temp v = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), dst0, dst1);
 810
 811    Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst), src0, v);
 812    static_cast<VOP3A_instruction*>(add)->neg[1] = true;
 813
 814    return add->definitions[0].getTemp();
 815 }
 816
 817 void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
 818 {
 819    if (!instr->dest.dest.is_ssa) {
 820       fprintf(stderr, "nir alu dst not in ssa: ");
 821       nir_print_instr(&instr->instr, stderr);
 822       fprintf(stderr, "\n");
 823       abort();
 824    }
 825    Builder bld(ctx->program, ctx->block);
 826    Temp dst = get_ssa_temp(ctx, &instr->dest.dest.ssa);
 827    switch(instr->op) {
 828    case nir_op_vec2:
 829    case nir_op_vec3:
 830    case nir_op_vec4: {
 831       std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 832       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.dest.ssa.num_components, 1)};
 833       for (unsigned i = 0; i < instr->dest.dest.ssa.num_components; ++i) {
 834          elems[i] = get_alu_src(ctx, instr->src[i]);
 835          vec->operands[i] = Operand{elems[i]};
 836       }
 837       vec->definitions[0] = Definition(dst);
 838       ctx->block->instructions.emplace_back(std::move(vec));
 839       ctx->allocated_vec.emplace(dst.id(), elems);
 840       break;
 841    }
 842    case nir_op_mov: {
 843       Temp src = get_alu_src(ctx, instr->src[0]);
 844       aco_ptr<Instruction> mov;
 845       if (dst.type() == RegType::sgpr) {
 846          if (src.type() == RegType::vgpr)
 847             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), src);
 848          else if (src.regClass() == s1)
 849             bld.sop1(aco_opcode::s_mov_b32, Definition(dst), src);
 850          else if (src.regClass() == s2)
 851             bld.sop1(aco_opcode::s_mov_b64, Definition(dst), src);
 852          else
 853             unreachable("wrong src register class for nir_op_imov");
 854       } else if (dst.regClass() == v1) {
 855          bld.vop1(aco_opcode::v_mov_b32, Definition(dst), src);
 856       } else if (dst.regClass() == v2) {
 857          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src);
 858       } else {
 859          nir_print_instr(&instr->instr, stderr);
 860          unreachable("Should have been lowered to scalar.");
 861       }
 862       break;
 863    }
 864    case nir_op_inot: {
 865       Temp src = get_alu_src(ctx, instr->src[0]);
 866       if (instr->dest.dest.ssa.bit_size == 1) {
 867          assert(src.regClass() == bld.lm);
 868          assert(dst.regClass() == bld.lm);
 869          /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
 870          Temp tmp = bld.sop1(Builder::s_not, bld.def(bld.lm), bld.def(s1, scc), src);
 871          bld.sop2(Builder::s_and, Definition(dst), bld.def(s1, scc), tmp, Operand(exec, bld.lm));
 872       } else if (dst.regClass() == v1) {
 873          emit_vop1_instruction(ctx, instr, aco_opcode::v_not_b32, dst);
 874       } else if (dst.type() == RegType::sgpr) {
 875          aco_opcode opcode = dst.size() == 1 ? aco_opcode::s_not_b32 : aco_opcode::s_not_b64;
 876          bld.sop1(opcode, Definition(dst), bld.def(s1, scc), src);
 877       } else {
 878          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 879          nir_print_instr(&instr->instr, stderr);
 880          fprintf(stderr, "\n");
 881       }
 882       break;
 883    }
 884    case nir_op_ineg: {
 885       Temp src = get_alu_src(ctx, instr->src[0]);
 886       if (dst.regClass() == v1) {
 887          bld.vsub32(Definition(dst), Operand(0u), Operand(src));
 888       } else if (dst.regClass() == s1) {
 889          bld.sop2(aco_opcode::s_mul_i32, Definition(dst), Operand((uint32_t) -1), src);
 890       } else if (dst.size() == 2) {
 891          Temp src0 = bld.tmp(dst.type(), 1);
 892          Temp src1 = bld.tmp(dst.type(), 1);
 893          bld.pseudo(aco_opcode::p_split_vector, Definition(src0), Definition(src1), src);
 894
 895          if (dst.regClass() == s2) {
 896             Temp carry = bld.tmp(s1);
 897             Temp dst0 = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(carry)), Operand(0u), src0);
 898             Temp dst1 = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), src1, carry);
 899             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
 900          } else {
 901             Temp lower = bld.tmp(v1);
 902             Temp borrow = bld.vsub32(Definition(lower), Operand(0u), src0, true).def(1).getTemp();
 903             Temp upper = bld.vsub32(bld.def(v1), Operand(0u), src1, false, borrow);
 904             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
 905          }
 906       } else {
 907          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 908          nir_print_instr(&instr->instr, stderr);
 909          fprintf(stderr, "\n");
 910       }
 911       break;
 912    }
 913    case nir_op_iabs: {
 914       if (dst.regClass() == s1) {
 915          bld.sop1(aco_opcode::s_abs_i32, Definition(dst), bld.def(s1, scc), get_alu_src(ctx, instr->src[0]));
 916       } else if (dst.regClass() == v1) {
 917          Temp src = get_alu_src(ctx, instr->src[0]);
 918          bld.vop2(aco_opcode::v_max_i32, Definition(dst), src, bld.vsub32(bld.def(v1), Operand(0u), src));
 919       } else {
 920          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 921          nir_print_instr(&instr->instr, stderr);
 922          fprintf(stderr, "\n");
 923       }
 924       break;
 925    }
 926    case nir_op_isign: {
 927       Temp src = get_alu_src(ctx, instr->src[0]);
 928       if (dst.regClass() == s1) {
 929          Temp tmp = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
 930          Temp gtz = bld.sopc(aco_opcode::s_cmp_gt_i32, bld.def(s1, scc), src, Operand(0u));
 931          bld.sop2(aco_opcode::s_add_i32, Definition(dst), bld.def(s1, scc), gtz, tmp);
 932       } else if (dst.regClass() == s2) {
 933          Temp neg = bld.sop2(aco_opcode::s_ashr_i64, bld.def(s2), bld.def(s1, scc), src, Operand(63u));
 934          Temp neqz;
 935          if (ctx->program->chip_class >= GFX8)
 936             neqz = bld.sopc(aco_opcode::s_cmp_lg_u64, bld.def(s1, scc), src, Operand(0u));
 937          else
 938             neqz = bld.sop2(aco_opcode::s_or_b64, bld.def(s2), bld.def(s1, scc), src, Operand(0u)).def(1).getTemp();
 939          /* SCC gets zero-extended to 64 bit */
 940          bld.sop2(aco_opcode::s_or_b64, Definition(dst), bld.def(s1, scc), neg, bld.scc(neqz));
 941       } else if (dst.regClass() == v1) {
 942          Temp tmp = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
 943          Temp gtz = bld.vopc(aco_opcode::v_cmp_ge_i32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
 944          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(1u), tmp, gtz);
 945       } else if (dst.regClass() == v2) {
 946          Temp upper = emit_extract_vector(ctx, src, 1, v1);
 947          Temp neg = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), upper);
 948          Temp gtz = bld.vopc(aco_opcode::v_cmp_ge_i64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
 949          Temp lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(1u), neg, gtz);
 950          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), neg, gtz);
 951          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
 952       } else {
 953          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 954          nir_print_instr(&instr->instr, stderr);
 955          fprintf(stderr, "\n");
 956       }
 957       break;
 958    }
 959    case nir_op_imax: {
 960       if (dst.regClass() == v1) {
 961          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_i32, dst, true);
 962       } else if (dst.regClass() == s1) {
 963          emit_sop2_instruction(ctx, instr, aco_opcode::s_max_i32, dst, true);
 964       } else {
 965          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 966          nir_print_instr(&instr->instr, stderr);
 967          fprintf(stderr, "\n");
 968       }
 969       break;
 970    }
 971    case nir_op_umax: {
 972       if (dst.regClass() == v1) {
 973          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_u32, dst, true);
 974       } else if (dst.regClass() == s1) {
 975          emit_sop2_instruction(ctx, instr, aco_opcode::s_max_u32, dst, true);
 976       } else {
 977          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 978          nir_print_instr(&instr->instr, stderr);
 979          fprintf(stderr, "\n");
 980       }
 981       break;
 982    }
 983    case nir_op_imin: {
 984       if (dst.regClass() == v1) {
 985          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_i32, dst, true);
 986       } else if (dst.regClass() == s1) {
 987          emit_sop2_instruction(ctx, instr, aco_opcode::s_min_i32, dst, true);
 988       } else {
 989          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 990          nir_print_instr(&instr->instr, stderr);
 991          fprintf(stderr, "\n");
 992       }
 993       break;
 994    }
 995    case nir_op_umin: {
 996       if (dst.regClass() == v1) {
 997          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_u32, dst, true);
 998       } else if (dst.regClass() == s1) {
 999          emit_sop2_instruction(ctx, instr, aco_opcode::s_min_u32, dst, true);
1000       } else {
1001          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1002          nir_print_instr(&instr->instr, stderr);
1003          fprintf(stderr, "\n");
1004       }
1005       break;
1006    }
1007    case nir_op_ior: {
1008       if (instr->dest.dest.ssa.bit_size == 1) {
1009          emit_boolean_logic(ctx, instr, Builder::s_or, dst);
1010       } else if (dst.regClass() == v1) {
1011          emit_vop2_instruction(ctx, instr, aco_opcode::v_or_b32, dst, true);
1012       } else if (dst.regClass() == s1) {
1013          emit_sop2_instruction(ctx, instr, aco_opcode::s_or_b32, dst, true);
1014       } else if (dst.regClass() == s2) {
1015          emit_sop2_instruction(ctx, instr, aco_opcode::s_or_b64, dst, true);
1016       } else {
1017          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1018          nir_print_instr(&instr->instr, stderr);
1019          fprintf(stderr, "\n");
1020       }
1021       break;
1022    }
1023    case nir_op_iand: {
1024       if (instr->dest.dest.ssa.bit_size == 1) {
1025          emit_boolean_logic(ctx, instr, Builder::s_and, dst);
1026       } else if (dst.regClass() == v1) {
1027          emit_vop2_instruction(ctx, instr, aco_opcode::v_and_b32, dst, true);
1028       } else if (dst.regClass() == s1) {
1029          emit_sop2_instruction(ctx, instr, aco_opcode::s_and_b32, dst, true);
1030       } else if (dst.regClass() == s2) {
1031          emit_sop2_instruction(ctx, instr, aco_opcode::s_and_b64, dst, true);
1032       } else {
1033          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1034          nir_print_instr(&instr->instr, stderr);
1035          fprintf(stderr, "\n");
1036       }
1037       break;
1038    }
1039    case nir_op_ixor: {
1040       if (instr->dest.dest.ssa.bit_size == 1) {
1041          emit_boolean_logic(ctx, instr, Builder::s_xor, dst);
1042       } else if (dst.regClass() == v1) {
1043          emit_vop2_instruction(ctx, instr, aco_opcode::v_xor_b32, dst, true);
1044       } else if (dst.regClass() == s1) {
1045          emit_sop2_instruction(ctx, instr, aco_opcode::s_xor_b32, dst, true);
1046       } else if (dst.regClass() == s2) {
1047          emit_sop2_instruction(ctx, instr, aco_opcode::s_xor_b64, dst, true);
1048       } else {
1049          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1050          nir_print_instr(&instr->instr, stderr);
1051          fprintf(stderr, "\n");
1052       }
1053       break;
1054    }
1055    case nir_op_ushr: {
1056       if (dst.regClass() == v1) {
1057          emit_vop2_instruction(ctx, instr, aco_opcode::v_lshrrev_b32, dst, false, true);
1058       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
1059          bld.vop3(aco_opcode::v_lshrrev_b64, Definition(dst),
1060                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
1061       } else if (dst.regClass() == v2) {
1062          bld.vop3(aco_opcode::v_lshr_b64, Definition(dst),
1063                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1064       } else if (dst.regClass() == s2) {
1065          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshr_b64, dst, true);
1066       } else if (dst.regClass() == s1) {
1067          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshr_b32, dst, true);
1068       } else {
1069          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1070          nir_print_instr(&instr->instr, stderr);
1071          fprintf(stderr, "\n");
1072       }
1073       break;
1074    }
1075    case nir_op_ishl: {
1076       if (dst.regClass() == v1) {
1077          emit_vop2_instruction(ctx, instr, aco_opcode::v_lshlrev_b32, dst, false, true);
1078       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
1079          bld.vop3(aco_opcode::v_lshlrev_b64, Definition(dst),
1080                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
1081       } else if (dst.regClass() == v2) {
1082          bld.vop3(aco_opcode::v_lshl_b64, Definition(dst),
1083                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1084       } else if (dst.regClass() == s1) {
1085          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshl_b32, dst, true);
1086       } else if (dst.regClass() == s2) {
1087          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshl_b64, dst, true);
1088       } else {
1089          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1090          nir_print_instr(&instr->instr, stderr);
1091          fprintf(stderr, "\n");
1092       }
1093       break;
1094    }
1095    case nir_op_ishr: {
1096       if (dst.regClass() == v1) {
1097          emit_vop2_instruction(ctx, instr, aco_opcode::v_ashrrev_i32, dst, false, true);
1098       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
1099          bld.vop3(aco_opcode::v_ashrrev_i64, Definition(dst),
1100                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
1101       } else if (dst.regClass() == v2) {
1102          bld.vop3(aco_opcode::v_ashr_i64, Definition(dst),
1103                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1104       } else if (dst.regClass() == s1) {
1105          emit_sop2_instruction(ctx, instr, aco_opcode::s_ashr_i32, dst, true);
1106       } else if (dst.regClass() == s2) {
1107          emit_sop2_instruction(ctx, instr, aco_opcode::s_ashr_i64, dst, true);
1108       } else {
1109          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1110          nir_print_instr(&instr->instr, stderr);
1111          fprintf(stderr, "\n");
1112       }
1113       break;
1114    }
1115    case nir_op_find_lsb: {
1116       Temp src = get_alu_src(ctx, instr->src[0]);
1117       if (src.regClass() == s1) {
1118          bld.sop1(aco_opcode::s_ff1_i32_b32, Definition(dst), src);
1119       } else if (src.regClass() == v1) {
1120          emit_vop1_instruction(ctx, instr, aco_opcode::v_ffbl_b32, dst);
1121       } else if (src.regClass() == s2) {
1122          bld.sop1(aco_opcode::s_ff1_i32_b64, Definition(dst), src);
1123       } else {
1124          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1125          nir_print_instr(&instr->instr, stderr);
1126          fprintf(stderr, "\n");
1127       }
1128       break;
1129    }
1130    case nir_op_ufind_msb:
1131    case nir_op_ifind_msb: {
1132       Temp src = get_alu_src(ctx, instr->src[0]);
1133       if (src.regClass() == s1 || src.regClass() == s2) {
1134          aco_opcode op = src.regClass() == s2 ?
1135                          (instr->op == nir_op_ufind_msb ? aco_opcode::s_flbit_i32_b64 : aco_opcode::s_flbit_i32_i64) :
1136                          (instr->op == nir_op_ufind_msb ? aco_opcode::s_flbit_i32_b32 : aco_opcode::s_flbit_i32);
1137          Temp msb_rev = bld.sop1(op, bld.def(s1), src);
1138
1139          Builder::Result sub = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc),
1140                                         Operand(src.size() * 32u - 1u), msb_rev);
1141          Temp msb = sub.def(0).getTemp();
1142          Temp carry = sub.def(1).getTemp();
1143
1144          bld.sop2(aco_opcode::s_cselect_b32, Definition(dst), Operand((uint32_t)-1), msb, bld.scc(carry));
1145       } else if (src.regClass() == v1) {
1146          aco_opcode op = instr->op == nir_op_ufind_msb ? aco_opcode::v_ffbh_u32 : aco_opcode::v_ffbh_i32;
1147          Temp msb_rev = bld.tmp(v1);
1148          emit_vop1_instruction(ctx, instr, op, msb_rev);
1149          Temp msb = bld.tmp(v1);
1150          Temp carry = bld.vsub32(Definition(msb), Operand(31u), Operand(msb_rev), true).def(1).getTemp();
1151          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), msb, Operand((uint32_t)-1), carry);
1152       } else {
1153          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1154          nir_print_instr(&instr->instr, stderr);
1155          fprintf(stderr, "\n");
1156       }
1157       break;
1158    }
1159    case nir_op_bitfield_reverse: {
1160       if (dst.regClass() == s1) {
1161          bld.sop1(aco_opcode::s_brev_b32, Definition(dst), get_alu_src(ctx, instr->src[0]));
1162       } else if (dst.regClass() == v1) {
1163          bld.vop1(aco_opcode::v_bfrev_b32, Definition(dst), get_alu_src(ctx, instr->src[0]));
1164       } else {
1165          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1166          nir_print_instr(&instr->instr, stderr);
1167          fprintf(stderr, "\n");
1168       }
1169       break;
1170    }
1171    case nir_op_iadd: {
1172       if (dst.regClass() == s1) {
1173          emit_sop2_instruction(ctx, instr, aco_opcode::s_add_u32, dst, true);
1174          break;
1175       }
1176
1177       Temp src0 = get_alu_src(ctx, instr->src[0]);
1178       Temp src1 = get_alu_src(ctx, instr->src[1]);
1179       if (dst.regClass() == v1) {
1180          bld.vadd32(Definition(dst), Operand(src0), Operand(src1));
1181          break;
1182       }
1183
1184       assert(src0.size() == 2 && src1.size() == 2);
1185       Temp src00 = bld.tmp(src0.type(), 1);
1186       Temp src01 = bld.tmp(dst.type(), 1);
1187       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1188       Temp src10 = bld.tmp(src1.type(), 1);
1189       Temp src11 = bld.tmp(dst.type(), 1);
1190       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1191
1192       if (dst.regClass() == s2) {
1193          Temp carry = bld.tmp(s1);
1194          Temp dst0 = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1195          Temp dst1 = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), src01, src11, bld.scc(carry));
1196          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1197       } else if (dst.regClass() == v2) {
1198          Temp dst0 = bld.tmp(v1);
1199          Temp carry = bld.vadd32(Definition(dst0), src00, src10, true).def(1).getTemp();
1200          Temp dst1 = bld.vadd32(bld.def(v1), src01, src11, false, carry);
1201          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1202       } else {
1203          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1204          nir_print_instr(&instr->instr, stderr);
1205          fprintf(stderr, "\n");
1206       }
1207       break;
1208    }
1209    case nir_op_uadd_sat: {
1210       Temp src0 = get_alu_src(ctx, instr->src[0]);
1211       Temp src1 = get_alu_src(ctx, instr->src[1]);
1212       if (dst.regClass() == s1) {
1213          Temp tmp = bld.tmp(s1), carry = bld.tmp(s1);
1214          bld.sop2(aco_opcode::s_add_u32, Definition(tmp), bld.scc(Definition(carry)),
1215                   src0, src1);
1216          bld.sop2(aco_opcode::s_cselect_b32, Definition(dst), Operand((uint32_t) -1), tmp, bld.scc(carry));
1217       } else if (dst.regClass() == v1) {
1218          if (ctx->options->chip_class >= GFX9) {
1219             aco_ptr<VOP3A_instruction> add{create_instruction<VOP3A_instruction>(aco_opcode::v_add_u32, asVOP3(Format::VOP2), 2, 1)};
1220             add->operands[0] = Operand(src0);
1221             add->operands[1] = Operand(src1);
1222             add->definitions[0] = Definition(dst);
1223             add->clamp = 1;
1224             ctx->block->instructions.emplace_back(std::move(add));
1225          } else {
1226             if (src1.regClass() != v1)
1227                std::swap(src0, src1);
1228             assert(src1.regClass() == v1);
1229             Temp tmp = bld.tmp(v1);
1230             Temp carry = bld.vadd32(Definition(tmp), src0, src1, true).def(1).getTemp();
1231             bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), tmp, Operand((uint32_t) -1), carry);
1232          }
1233       } else {
1234          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1235          nir_print_instr(&instr->instr, stderr);
1236          fprintf(stderr, "\n");
1237       }
1238       break;
1239    }
1240    case nir_op_uadd_carry: {
1241       Temp src0 = get_alu_src(ctx, instr->src[0]);
1242       Temp src1 = get_alu_src(ctx, instr->src[1]);
1243       if (dst.regClass() == s1) {
1244          bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(dst)), src0, src1);
1245          break;
1246       }
1247       if (dst.regClass() == v1) {
1248          Temp carry = bld.vadd32(bld.def(v1), src0, src1, true).def(1).getTemp();
1249          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), carry);
1250          break;
1251       }
1252
1253       Temp src00 = bld.tmp(src0.type(), 1);
1254       Temp src01 = bld.tmp(dst.type(), 1);
1255       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1256       Temp src10 = bld.tmp(src1.type(), 1);
1257       Temp src11 = bld.tmp(dst.type(), 1);
1258       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1259       if (dst.regClass() == s2) {
1260          Temp carry = bld.tmp(s1);
1261          bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1262          carry = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.scc(bld.def(s1)), src01, src11, bld.scc(carry)).def(1).getTemp();
1263          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), carry, Operand(0u));
1264       } else if (dst.regClass() == v2) {
1265          Temp carry = bld.vadd32(bld.def(v1), src00, src10, true).def(1).getTemp();
1266          carry = bld.vadd32(bld.def(v1), src01, src11, true, carry).def(1).getTemp();
1267          carry = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand(1u), carry);
1268          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), carry, Operand(0u));
1269       } else {
1270          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1271          nir_print_instr(&instr->instr, stderr);
1272          fprintf(stderr, "\n");
1273       }
1274       break;
1275    }
1276    case nir_op_isub: {
1277       if (dst.regClass() == s1) {
1278          emit_sop2_instruction(ctx, instr, aco_opcode::s_sub_i32, dst, true);
1279          break;
1280       }
1281
1282       Temp src0 = get_alu_src(ctx, instr->src[0]);
1283       Temp src1 = get_alu_src(ctx, instr->src[1]);
1284       if (dst.regClass() == v1) {
1285          bld.vsub32(Definition(dst), src0, src1);
1286          break;
1287       }
1288
1289       Temp src00 = bld.tmp(src0.type(), 1);
1290       Temp src01 = bld.tmp(dst.type(), 1);
1291       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1292       Temp src10 = bld.tmp(src1.type(), 1);
1293       Temp src11 = bld.tmp(dst.type(), 1);
1294       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1295       if (dst.regClass() == s2) {
1296          Temp carry = bld.tmp(s1);
1297          Temp dst0 = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1298          Temp dst1 = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), src01, src11, carry);
1299          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1300       } else if (dst.regClass() == v2) {
1301          Temp lower = bld.tmp(v1);
1302          Temp borrow = bld.vsub32(Definition(lower), src00, src10, true).def(1).getTemp();
1303          Temp upper = bld.vsub32(bld.def(v1), src01, src11, false, borrow);
1304          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1305       } else {
1306          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1307          nir_print_instr(&instr->instr, stderr);
1308          fprintf(stderr, "\n");
1309       }
1310       break;
1311    }
1312    case nir_op_usub_borrow: {
1313       Temp src0 = get_alu_src(ctx, instr->src[0]);
1314       Temp src1 = get_alu_src(ctx, instr->src[1]);
1315       if (dst.regClass() == s1) {
1316          bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(dst)), src0, src1);
1317          break;
1318       } else if (dst.regClass() == v1) {
1319          Temp borrow = bld.vsub32(bld.def(v1), src0, src1, true).def(1).getTemp();
1320          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), borrow);
1321          break;
1322       }
1323
1324       Temp src00 = bld.tmp(src0.type(), 1);
1325       Temp src01 = bld.tmp(dst.type(), 1);
1326       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1327       Temp src10 = bld.tmp(src1.type(), 1);
1328       Temp src11 = bld.tmp(dst.type(), 1);
1329       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1330       if (dst.regClass() == s2) {
1331          Temp borrow = bld.tmp(s1);
1332          bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(borrow)), src00, src10);
1333          borrow = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.scc(bld.def(s1)), src01, src11, bld.scc(borrow)).def(1).getTemp();
1334          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), borrow, Operand(0u));
1335       } else if (dst.regClass() == v2) {
1336          Temp borrow = bld.vsub32(bld.def(v1), src00, src10, true).def(1).getTemp();
1337          borrow = bld.vsub32(bld.def(v1), src01, src11, true, Operand(borrow)).def(1).getTemp();
1338          borrow = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand(1u), borrow);
1339          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), borrow, Operand(0u));
1340       } else {
1341          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1342          nir_print_instr(&instr->instr, stderr);
1343          fprintf(stderr, "\n");
1344       }
1345       break;
1346    }
1347    case nir_op_imul: {
1348       if (dst.regClass() == v1) {
1349          bld.vop3(aco_opcode::v_mul_lo_u32, Definition(dst),
1350                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1351       } else if (dst.regClass() == s1) {
1352          emit_sop2_instruction(ctx, instr, aco_opcode::s_mul_i32, dst, false);
1353       } else {
1354          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1355          nir_print_instr(&instr->instr, stderr);
1356          fprintf(stderr, "\n");
1357       }
1358       break;
1359    }
1360    case nir_op_umul_high: {
1361       if (dst.regClass() == v1) {
1362          bld.vop3(aco_opcode::v_mul_hi_u32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1363       } else if (dst.regClass() == s1 && ctx->options->chip_class >= GFX9) {
1364          bld.sop2(aco_opcode::s_mul_hi_u32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1365       } else if (dst.regClass() == s1) {
1366          Temp tmp = bld.vop3(aco_opcode::v_mul_hi_u32, bld.def(v1), get_alu_src(ctx, instr->src[0]),
1367                              as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1368          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), tmp);
1369       } else {
1370          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1371          nir_print_instr(&instr->instr, stderr);
1372          fprintf(stderr, "\n");
1373       }
1374       break;
1375    }
1376    case nir_op_imul_high: {
1377       if (dst.regClass() == v1) {
1378          bld.vop3(aco_opcode::v_mul_hi_i32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1379       } else if (dst.regClass() == s1 && ctx->options->chip_class >= GFX9) {
1380          bld.sop2(aco_opcode::s_mul_hi_i32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1381       } else if (dst.regClass() == s1) {
1382          Temp tmp = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), get_alu_src(ctx, instr->src[0]),
1383                              as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1384          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), tmp);
1385       } else {
1386          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1387          nir_print_instr(&instr->instr, stderr);
1388          fprintf(stderr, "\n");
1389       }
1390       break;
1391    }
1392    case nir_op_fmul: {
1393       if (dst.size() == 1) {
1394          emit_vop2_instruction(ctx, instr, aco_opcode::v_mul_f32, dst, true);
1395       } else if (dst.size() == 2) {
1396          bld.vop3(aco_opcode::v_mul_f64, Definition(dst), get_alu_src(ctx, instr->src[0]),
1397                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1398       } else {
1399          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1400          nir_print_instr(&instr->instr, stderr);
1401          fprintf(stderr, "\n");
1402       }
1403       break;
1404    }
1405    case nir_op_fadd: {
1406       if (dst.size() == 1) {
1407          emit_vop2_instruction(ctx, instr, aco_opcode::v_add_f32, dst, true);
1408       } else if (dst.size() == 2) {
1409          bld.vop3(aco_opcode::v_add_f64, Definition(dst), get_alu_src(ctx, instr->src[0]),
1410                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1411       } else {
1412          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1413          nir_print_instr(&instr->instr, stderr);
1414          fprintf(stderr, "\n");
1415       }
1416       break;
1417    }
1418    case nir_op_fsub: {
1419       Temp src0 = get_alu_src(ctx, instr->src[0]);
1420       Temp src1 = get_alu_src(ctx, instr->src[1]);
1421       if (dst.size() == 1) {
1422          if (src1.type() == RegType::vgpr || src0.type() != RegType::vgpr)
1423             emit_vop2_instruction(ctx, instr, aco_opcode::v_sub_f32, dst, false);
1424          else
1425             emit_vop2_instruction(ctx, instr, aco_opcode::v_subrev_f32, dst, true);
1426       } else if (dst.size() == 2) {
1427          Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst),
1428                                      get_alu_src(ctx, instr->src[0]),
1429                                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1430          VOP3A_instruction* sub = static_cast<VOP3A_instruction*>(add);
1431          sub->neg[1] = true;
1432       } else {
1433          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1434          nir_print_instr(&instr->instr, stderr);
1435          fprintf(stderr, "\n");
1436       }
1437       break;
1438    }
1439    case nir_op_fmax: {
1440       if (dst.size() == 1) {
1441          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_f32, dst, true, false, ctx->block->fp_mode.must_flush_denorms32);
1442       } else if (dst.size() == 2) {
1443          if (ctx->block->fp_mode.must_flush_denorms16_64 && ctx->program->chip_class < GFX9) {
1444             Temp tmp = bld.vop3(aco_opcode::v_max_f64, bld.def(v2),
1445                                 get_alu_src(ctx, instr->src[0]),
1446                                 as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1447             bld.vop3(aco_opcode::v_mul_f64, Definition(dst), Operand(0x3FF0000000000000lu), tmp);
1448          } else {
1449             bld.vop3(aco_opcode::v_max_f64, Definition(dst),
1450                      get_alu_src(ctx, instr->src[0]),
1451                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1452          }
1453       } else {
1454          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1455          nir_print_instr(&instr->instr, stderr);
1456          fprintf(stderr, "\n");
1457       }
1458       break;
1459    }
1460    case nir_op_fmin: {
1461       if (dst.size() == 1) {
1462          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_f32, dst, true, false, ctx->block->fp_mode.must_flush_denorms32);
1463       } else if (dst.size() == 2) {
1464          if (ctx->block->fp_mode.must_flush_denorms16_64 && ctx->program->chip_class < GFX9) {
1465             Temp tmp = bld.vop3(aco_opcode::v_min_f64, bld.def(v2),
1466                                 get_alu_src(ctx, instr->src[0]),
1467                                 as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1468             bld.vop3(aco_opcode::v_mul_f64, Definition(dst), Operand(0x3FF0000000000000lu), tmp);
1469          } else {
1470             bld.vop3(aco_opcode::v_min_f64, Definition(dst),
1471                      get_alu_src(ctx, instr->src[0]),
1472                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1473          }
1474       } else {
1475          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1476          nir_print_instr(&instr->instr, stderr);
1477          fprintf(stderr, "\n");
1478       }
1479       break;
1480    }
1481    case nir_op_fmax3: {
1482       if (dst.size() == 1) {
1483          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_f32, dst, ctx->block->fp_mode.must_flush_denorms32);
1484       } else {
1485          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1486          nir_print_instr(&instr->instr, stderr);
1487          fprintf(stderr, "\n");
1488       }
1489       break;
1490    }
1491    case nir_op_fmin3: {
1492       if (dst.size() == 1) {
1493          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_f32, dst, ctx->block->fp_mode.must_flush_denorms32);
1494       } else {
1495          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1496          nir_print_instr(&instr->instr, stderr);
1497          fprintf(stderr, "\n");
1498       }
1499       break;
1500    }
1501    case nir_op_fmed3: {
1502       if (dst.size() == 1) {
1503          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_f32, dst, ctx->block->fp_mode.must_flush_denorms32);
1504       } else {
1505          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1506          nir_print_instr(&instr->instr, stderr);
1507          fprintf(stderr, "\n");
1508       }
1509       break;
1510    }
1511    case nir_op_umax3: {
1512       if (dst.size() == 1) {
1513          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_u32, dst);
1514       } else {
1515          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1516          nir_print_instr(&instr->instr, stderr);
1517          fprintf(stderr, "\n");
1518       }
1519       break;
1520    }
1521    case nir_op_umin3: {
1522       if (dst.size() == 1) {
1523          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_u32, dst);
1524       } else {
1525          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1526          nir_print_instr(&instr->instr, stderr);
1527          fprintf(stderr, "\n");
1528       }
1529       break;
1530    }
1531    case nir_op_umed3: {
1532       if (dst.size() == 1) {
1533          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_u32, dst);
1534       } else {
1535          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1536          nir_print_instr(&instr->instr, stderr);
1537          fprintf(stderr, "\n");
1538       }
1539       break;
1540    }
1541    case nir_op_imax3: {
1542       if (dst.size() == 1) {
1543          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_i32, dst);
1544       } else {
1545          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1546          nir_print_instr(&instr->instr, stderr);
1547          fprintf(stderr, "\n");
1548       }
1549       break;
1550    }
1551    case nir_op_imin3: {
1552       if (dst.size() == 1) {
1553          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_i32, dst);
1554       } else {
1555          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1556          nir_print_instr(&instr->instr, stderr);
1557          fprintf(stderr, "\n");
1558       }
1559       break;
1560    }
1561    case nir_op_imed3: {
1562       if (dst.size() == 1) {
1563          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_i32, dst);
1564       } else {
1565          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1566          nir_print_instr(&instr->instr, stderr);
1567          fprintf(stderr, "\n");
1568       }
1569       break;
1570    }
1571    case nir_op_cube_face_coord: {
1572       Temp in = get_alu_src(ctx, instr->src[0], 3);
1573       Temp src[3] = { emit_extract_vector(ctx, in, 0, v1),
1574                       emit_extract_vector(ctx, in, 1, v1),
1575                       emit_extract_vector(ctx, in, 2, v1) };
1576       Temp ma = bld.vop3(aco_opcode::v_cubema_f32, bld.def(v1), src[0], src[1], src[2]);
1577       ma = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), ma);
1578       Temp sc = bld.vop3(aco_opcode::v_cubesc_f32, bld.def(v1), src[0], src[1], src[2]);
1579       Temp tc = bld.vop3(aco_opcode::v_cubetc_f32, bld.def(v1), src[0], src[1], src[2]);
1580       sc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), sc, ma, Operand(0x3f000000u/*0.5*/));
1581       tc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), tc, ma, Operand(0x3f000000u/*0.5*/));
1582       bld.pseudo(aco_opcode::p_create_vector, Definition(dst), sc, tc);
1583       break;
1584    }
1585    case nir_op_cube_face_index: {
1586       Temp in = get_alu_src(ctx, instr->src[0], 3);
1587       Temp src[3] = { emit_extract_vector(ctx, in, 0, v1),
1588                       emit_extract_vector(ctx, in, 1, v1),
1589                       emit_extract_vector(ctx, in, 2, v1) };
1590       bld.vop3(aco_opcode::v_cubeid_f32, Definition(dst), src[0], src[1], src[2]);
1591       break;
1592    }
1593    case nir_op_bcsel: {
1594       emit_bcsel(ctx, instr, dst);
1595       break;
1596    }
1597    case nir_op_frsq: {
1598       if (dst.size() == 1) {
1599          emit_rsq(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1600       } else if (dst.size() == 2) {
1601          emit_vop1_instruction(ctx, instr, aco_opcode::v_rsq_f64, dst);
1602       } else {
1603          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1604          nir_print_instr(&instr->instr, stderr);
1605          fprintf(stderr, "\n");
1606       }
1607       break;
1608    }
1609    case nir_op_fneg: {
1610       Temp src = get_alu_src(ctx, instr->src[0]);
1611       if (dst.size() == 1) {
1612          if (ctx->block->fp_mode.must_flush_denorms32)
1613             src = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x3f800000u), as_vgpr(ctx, src));
1614          bld.vop2(aco_opcode::v_xor_b32, Definition(dst), Operand(0x80000000u), as_vgpr(ctx, src));
1615       } else if (dst.size() == 2) {
1616          if (ctx->block->fp_mode.must_flush_denorms16_64)
1617             src = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), Operand(0x3FF0000000000000lu), as_vgpr(ctx, src));
1618          Temp upper = bld.tmp(v1), lower = bld.tmp(v1);
1619          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1620          upper = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), Operand(0x80000000u), upper);
1621          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1622       } else {
1623          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1624          nir_print_instr(&instr->instr, stderr);
1625          fprintf(stderr, "\n");
1626       }
1627       break;
1628    }
1629    case nir_op_fabs: {
1630       Temp src = get_alu_src(ctx, instr->src[0]);
1631       if (dst.size() == 1) {
1632          if (ctx->block->fp_mode.must_flush_denorms32)
1633             src = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x3f800000u), as_vgpr(ctx, src));
1634          bld.vop2(aco_opcode::v_and_b32, Definition(dst), Operand(0x7FFFFFFFu), as_vgpr(ctx, src));
1635       } else if (dst.size() == 2) {
1636          if (ctx->block->fp_mode.must_flush_denorms16_64)
1637             src = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), Operand(0x3FF0000000000000lu), as_vgpr(ctx, src));
1638          Temp upper = bld.tmp(v1), lower = bld.tmp(v1);
1639          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1640          upper = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7FFFFFFFu), upper);
1641          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1642       } else {
1643          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1644          nir_print_instr(&instr->instr, stderr);
1645          fprintf(stderr, "\n");
1646       }
1647       break;
1648    }
1649    case nir_op_fsat: {
1650       Temp src = get_alu_src(ctx, instr->src[0]);
1651       if (dst.size() == 1) {
1652          bld.vop3(aco_opcode::v_med3_f32, Definition(dst), Operand(0u), Operand(0x3f800000u), src);
1653          /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1654          // TODO: confirm that this holds under any circumstances
1655       } else if (dst.size() == 2) {
1656          Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst), src, Operand(0u));
1657          VOP3A_instruction* vop3 = static_cast<VOP3A_instruction*>(add);
1658          vop3->clamp = true;
1659       } else {
1660          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1661          nir_print_instr(&instr->instr, stderr);
1662          fprintf(stderr, "\n");
1663       }
1664       break;
1665    }
1666    case nir_op_flog2: {
1667       if (dst.size() == 1) {
1668          emit_log2(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1669       } else {
1670          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1671          nir_print_instr(&instr->instr, stderr);
1672          fprintf(stderr, "\n");
1673       }
1674       break;
1675    }
1676    case nir_op_frcp: {
1677       if (dst.size() == 1) {
1678          emit_rcp(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1679       } else if (dst.size() == 2) {
1680          emit_vop1_instruction(ctx, instr, aco_opcode::v_rcp_f64, dst);
1681       } else {
1682          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1683          nir_print_instr(&instr->instr, stderr);
1684          fprintf(stderr, "\n");
1685       }
1686       break;
1687    }
1688    case nir_op_fexp2: {
1689       if (dst.size() == 1) {
1690          emit_vop1_instruction(ctx, instr, aco_opcode::v_exp_f32, dst);
1691       } else {
1692          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1693          nir_print_instr(&instr->instr, stderr);
1694          fprintf(stderr, "\n");
1695       }
1696       break;
1697    }
1698    case nir_op_fsqrt: {
1699       if (dst.size() == 1) {
1700          emit_sqrt(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1701       } else if (dst.size() == 2) {
1702          emit_vop1_instruction(ctx, instr, aco_opcode::v_sqrt_f64, dst);
1703       } else {
1704          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1705          nir_print_instr(&instr->instr, stderr);
1706          fprintf(stderr, "\n");
1707       }
1708       break;
1709    }
1710    case nir_op_ffract: {
1711       if (dst.size() == 1) {
1712          emit_vop1_instruction(ctx, instr, aco_opcode::v_fract_f32, dst);
1713       } else if (dst.size() == 2) {
1714          emit_vop1_instruction(ctx, instr, aco_opcode::v_fract_f64, dst);
1715       } else {
1716          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1717          nir_print_instr(&instr->instr, stderr);
1718          fprintf(stderr, "\n");
1719       }
1720       break;
1721    }
1722    case nir_op_ffloor: {
1723       if (dst.size() == 1) {
1724          emit_vop1_instruction(ctx, instr, aco_opcode::v_floor_f32, dst);
1725       } else if (dst.size() == 2) {
1726          emit_floor_f64(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1727       } else {
1728          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1729          nir_print_instr(&instr->instr, stderr);
1730          fprintf(stderr, "\n");
1731       }
1732       break;
1733    }
1734    case nir_op_fceil: {
1735       if (dst.size() == 1) {
1736          emit_vop1_instruction(ctx, instr, aco_opcode::v_ceil_f32, dst);
1737       } else if (dst.size() == 2) {
1738          if (ctx->options->chip_class >= GFX7) {
1739             emit_vop1_instruction(ctx, instr, aco_opcode::v_ceil_f64, dst);
1740          } else {
1741             /* GFX6 doesn't support V_CEIL_F64, lower it. */
1742             Temp src0 = get_alu_src(ctx, instr->src[0]);
1743
1744             /* trunc = trunc(src0)
1745              * if (src0 > 0.0 && src0 != trunc)
1746              *    trunc += 1.0
1747              */
1748             Temp trunc = emit_trunc_f64(ctx, bld, bld.def(v2), src0);
1749             Temp tmp0 = bld.vopc_e64(aco_opcode::v_cmp_gt_f64, bld.def(bld.lm), src0, Operand(0u));
1750             Temp tmp1 = bld.vopc(aco_opcode::v_cmp_lg_f64, bld.hint_vcc(bld.def(bld.lm)), src0, trunc);
1751             Temp cond = bld.sop2(aco_opcode::s_and_b64, bld.hint_vcc(bld.def(s2)), bld.def(s1, scc), tmp0, tmp1);
1752             Temp add = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), bld.copy(bld.def(v1), Operand(0u)), bld.copy(bld.def(v1), Operand(0x3ff00000u)), cond);
1753             add = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), bld.copy(bld.def(v1), Operand(0u)), add);
1754             bld.vop3(aco_opcode::v_add_f64, Definition(dst), trunc, add);
1755          }
1756       } else {
1757          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1758          nir_print_instr(&instr->instr, stderr);
1759          fprintf(stderr, "\n");
1760       }
1761       break;
1762    }
1763    case nir_op_ftrunc: {
1764       if (dst.size() == 1) {
1765          emit_vop1_instruction(ctx, instr, aco_opcode::v_trunc_f32, dst);
1766       } else if (dst.size() == 2) {
1767          emit_trunc_f64(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1768       } else {
1769          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1770          nir_print_instr(&instr->instr, stderr);
1771          fprintf(stderr, "\n");
1772       }
1773       break;
1774    }
1775    case nir_op_fround_even: {
1776       if (dst.size() == 1) {
1777          emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f32, dst);
1778       } else if (dst.size() == 2) {
1779          if (ctx->options->chip_class >= GFX7) {
1780             emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f64, dst);
1781          } else {
1782             /* GFX6 doesn't support V_RNDNE_F64, lower it. */
1783             Temp src0 = get_alu_src(ctx, instr->src[0]);
1784
1785             Temp src0_lo = bld.tmp(v1), src0_hi = bld.tmp(v1);
1786             bld.pseudo(aco_opcode::p_split_vector, Definition(src0_lo), Definition(src0_hi), src0);
1787
1788             Temp bitmask = bld.sop1(aco_opcode::s_brev_b32, bld.def(s1), bld.copy(bld.def(s1), Operand(-2u)));
1789             Temp bfi = bld.vop3(aco_opcode::v_bfi_b32, bld.def(v1), bitmask, bld.copy(bld.def(v1), Operand(0x43300000u)), as_vgpr(ctx, src0_hi));
1790             Temp tmp = bld.vop3(aco_opcode::v_add_f64, bld.def(v2), src0, bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), bfi));
1791             Instruction *sub = bld.vop3(aco_opcode::v_add_f64, bld.def(v2), tmp, bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), bfi));
1792             static_cast<VOP3A_instruction*>(sub)->neg[1] = true;
1793             tmp = sub->definitions[0].getTemp();
1794
1795             Temp v = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(-1u), Operand(0x432fffffu));
1796             Instruction* vop3 = bld.vopc_e64(aco_opcode::v_cmp_gt_f64, bld.hint_vcc(bld.def(bld.lm)), src0, v);
1797             static_cast<VOP3A_instruction*>(vop3)->abs[0] = true;
1798             Temp cond = vop3->definitions[0].getTemp();
1799
1800             Temp tmp_lo = bld.tmp(v1), tmp_hi = bld.tmp(v1);
1801             bld.pseudo(aco_opcode::p_split_vector, Definition(tmp_lo), Definition(tmp_hi), tmp);
1802             Temp dst0 = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), tmp_lo, as_vgpr(ctx, src0_lo), cond);
1803             Temp dst1 = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), tmp_hi, as_vgpr(ctx, src0_hi), cond);
1804
1805             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1806          }
1807       } else {
1808          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1809          nir_print_instr(&instr->instr, stderr);
1810          fprintf(stderr, "\n");
1811       }
1812       break;
1813    }
1814    case nir_op_fsin:
1815    case nir_op_fcos: {
1816       Temp src = get_alu_src(ctx, instr->src[0]);
1817       aco_ptr<Instruction> norm;
1818       if (dst.size() == 1) {
1819          Temp half_pi = bld.copy(bld.def(s1), Operand(0x3e22f983u));
1820          Temp tmp = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), half_pi, as_vgpr(ctx, src));
1821
1822          /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
1823          if (ctx->options->chip_class < GFX9)
1824             tmp = bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), tmp);
1825
1826          aco_opcode opcode = instr->op == nir_op_fsin ? aco_opcode::v_sin_f32 : aco_opcode::v_cos_f32;
1827          bld.vop1(opcode, Definition(dst), tmp);
1828       } else {
1829          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1830          nir_print_instr(&instr->instr, stderr);
1831          fprintf(stderr, "\n");
1832       }
1833       break;
1834    }
1835    case nir_op_ldexp: {
1836       if (dst.size() == 1) {
1837          bld.vop3(aco_opcode::v_ldexp_f32, Definition(dst),
1838                   as_vgpr(ctx, get_alu_src(ctx, instr->src[0])),
1839                   get_alu_src(ctx, instr->src[1]));
1840       } else if (dst.size() == 2) {
1841          bld.vop3(aco_opcode::v_ldexp_f64, Definition(dst),
1842                   as_vgpr(ctx, get_alu_src(ctx, instr->src[0])),
1843                   get_alu_src(ctx, instr->src[1]));
1844       } else {
1845          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1846          nir_print_instr(&instr->instr, stderr);
1847          fprintf(stderr, "\n");
1848       }
1849       break;
1850    }
1851    case nir_op_frexp_sig: {
1852       if (dst.size() == 1) {
1853          bld.vop1(aco_opcode::v_frexp_mant_f32, Definition(dst),
1854                   get_alu_src(ctx, instr->src[0]));
1855       } else if (dst.size() == 2) {
1856          bld.vop1(aco_opcode::v_frexp_mant_f64, Definition(dst),
1857                   get_alu_src(ctx, instr->src[0]));
1858       } else {
1859          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1860          nir_print_instr(&instr->instr, stderr);
1861          fprintf(stderr, "\n");
1862       }
1863       break;
1864    }
1865    case nir_op_frexp_exp: {
1866       if (instr->src[0].src.ssa->bit_size == 32) {
1867          bld.vop1(aco_opcode::v_frexp_exp_i32_f32, Definition(dst),
1868                   get_alu_src(ctx, instr->src[0]));
1869       } else if (instr->src[0].src.ssa->bit_size == 64) {
1870          bld.vop1(aco_opcode::v_frexp_exp_i32_f64, Definition(dst),
1871                   get_alu_src(ctx, instr->src[0]));
1872       } else {
1873          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1874          nir_print_instr(&instr->instr, stderr);
1875          fprintf(stderr, "\n");
1876       }
1877       break;
1878    }
1879    case nir_op_fsign: {
1880       Temp src = as_vgpr(ctx, get_alu_src(ctx, instr->src[0]));
1881       if (dst.size() == 1) {
1882          Temp cond = bld.vopc(aco_opcode::v_cmp_nlt_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1883          src = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0x3f800000u), src, cond);
1884          cond = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1885          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0xbf800000u), src, cond);
1886       } else if (dst.size() == 2) {
1887          Temp cond = bld.vopc(aco_opcode::v_cmp_nlt_f64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1888          Temp tmp = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0x3FF00000u));
1889          Temp upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), tmp, emit_extract_vector(ctx, src, 1, v1), cond);
1890
1891          cond = bld.vopc(aco_opcode::v_cmp_le_f64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1892          tmp = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0xBFF00000u));
1893          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), tmp, upper, cond);
1894
1895          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), Operand(0u), upper);
1896       } else {
1897          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1898          nir_print_instr(&instr->instr, stderr);
1899          fprintf(stderr, "\n");
1900       }
1901       break;
1902    }
1903    case nir_op_f2f32: {
1904       if (instr->src[0].src.ssa->bit_size == 64) {
1905          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_f64, dst);
1906       } else {
1907          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1908          nir_print_instr(&instr->instr, stderr);
1909          fprintf(stderr, "\n");
1910       }
1911       break;
1912    }
1913    case nir_op_f2f64: {
1914       if (instr->src[0].src.ssa->bit_size == 32) {
1915          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_f32, dst);
1916       } else {
1917          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1918          nir_print_instr(&instr->instr, stderr);
1919          fprintf(stderr, "\n");
1920       }
1921       break;
1922    }
1923    case nir_op_i2f32: {
1924       assert(dst.size() == 1);
1925       emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_i32, dst);
1926       break;
1927    }
1928    case nir_op_i2f64: {
1929       if (instr->src[0].src.ssa->bit_size == 32) {
1930          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_i32, dst);
1931       } else if (instr->src[0].src.ssa->bit_size == 64) {
1932          Temp src = get_alu_src(ctx, instr->src[0]);
1933          RegClass rc = RegClass(src.type(), 1);
1934          Temp lower = bld.tmp(rc), upper = bld.tmp(rc);
1935          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1936          lower = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), lower);
1937          upper = bld.vop1(aco_opcode::v_cvt_f64_i32, bld.def(v2), upper);
1938          upper = bld.vop3(aco_opcode::v_ldexp_f64, bld.def(v2), upper, Operand(32u));
1939          bld.vop3(aco_opcode::v_add_f64, Definition(dst), lower, upper);
1940
1941       } else {
1942          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1943          nir_print_instr(&instr->instr, stderr);
1944          fprintf(stderr, "\n");
1945       }
1946       break;
1947    }
1948    case nir_op_u2f32: {
1949       assert(dst.size() == 1);
1950       emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_u32, dst);
1951       break;
1952    }
1953    case nir_op_u2f64: {
1954       if (instr->src[0].src.ssa->bit_size == 32) {
1955          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_u32, dst);
1956       } else if (instr->src[0].src.ssa->bit_size == 64) {
1957          Temp src = get_alu_src(ctx, instr->src[0]);
1958          RegClass rc = RegClass(src.type(), 1);
1959          Temp lower = bld.tmp(rc), upper = bld.tmp(rc);
1960          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1961          lower = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), lower);
1962          upper = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), upper);
1963          upper = bld.vop3(aco_opcode::v_ldexp_f64, bld.def(v2), upper, Operand(32u));
1964          bld.vop3(aco_opcode::v_add_f64, Definition(dst), lower, upper);
1965       } else {
1966          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1967          nir_print_instr(&instr->instr, stderr);
1968          fprintf(stderr, "\n");
1969       }
1970       break;
1971    }
1972    case nir_op_f2i32: {
1973       Temp src = get_alu_src(ctx, instr->src[0]);
1974       if (instr->src[0].src.ssa->bit_size == 32) {
1975          if (dst.type() == RegType::vgpr)
1976             bld.vop1(aco_opcode::v_cvt_i32_f32, Definition(dst), src);
1977          else
1978             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1979                        bld.vop1(aco_opcode::v_cvt_i32_f32, bld.def(v1), src));
1980
1981       } else if (instr->src[0].src.ssa->bit_size == 64) {
1982          if (dst.type() == RegType::vgpr)
1983             bld.vop1(aco_opcode::v_cvt_i32_f64, Definition(dst), src);
1984          else
1985             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1986                        bld.vop1(aco_opcode::v_cvt_i32_f64, bld.def(v1), src));
1987
1988       } else {
1989          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1990          nir_print_instr(&instr->instr, stderr);
1991          fprintf(stderr, "\n");
1992       }
1993       break;
1994    }
1995    case nir_op_f2u32: {
1996       Temp src = get_alu_src(ctx, instr->src[0]);
1997       if (instr->src[0].src.ssa->bit_size == 32) {
1998          if (dst.type() == RegType::vgpr)
1999             bld.vop1(aco_opcode::v_cvt_u32_f32, Definition(dst), src);
2000          else
2001             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
2002                        bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), src));
2003
2004       } else if (instr->src[0].src.ssa->bit_size == 64) {
2005          if (dst.type() == RegType::vgpr)
2006             bld.vop1(aco_opcode::v_cvt_u32_f64, Definition(dst), src);
2007          else
2008             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
2009                        bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), src));
2010
2011       } else {
2012          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2013          nir_print_instr(&instr->instr, stderr);
2014          fprintf(stderr, "\n");
2015       }
2016       break;
2017    }
2018    case nir_op_f2i64: {
2019       Temp src = get_alu_src(ctx, instr->src[0]);
2020       if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::vgpr) {
2021          Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f32, bld.def(v1), src);
2022          exponent = bld.vop3(aco_opcode::v_med3_i32, bld.def(v1), Operand(0x0u), exponent, Operand(64u));
2023          Temp mantissa = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffu), src);
2024          Temp sign = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
2025          mantissa = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(0x800000u), mantissa);
2026          mantissa = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(7u), mantissa);
2027          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), mantissa);
2028          Temp new_exponent = bld.tmp(v1);
2029          Temp borrow = bld.vsub32(Definition(new_exponent), Operand(63u), exponent, true).def(1).getTemp();
2030          if (ctx->program->chip_class >= GFX8)
2031             mantissa = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), new_exponent, mantissa);
2032          else
2033             mantissa = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), mantissa, new_exponent);
2034          Temp saturate = bld.vop1(aco_opcode::v_bfrev_b32, bld.def(v1), Operand(0xfffffffeu));
2035          Temp lower = bld.tmp(v1), upper = bld.tmp(v1);
2036          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2037          lower = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), lower, Operand(0xffffffffu), borrow);
2038          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), upper, saturate, borrow);
2039          lower = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), sign, lower);
2040          upper = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), sign, upper);
2041          Temp new_lower = bld.tmp(v1);
2042          borrow = bld.vsub32(Definition(new_lower), lower, sign, true).def(1).getTemp();
2043          Temp new_upper = bld.vsub32(bld.def(v1), upper, sign, false, borrow);
2044          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), new_lower, new_upper);
2045
2046       } else if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::sgpr) {
2047          if (src.type() == RegType::vgpr)
2048             src = bld.as_uniform(src);
2049          Temp exponent = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), src, Operand(0x80017u));
2050          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(126u));
2051          exponent = bld.sop2(aco_opcode::s_max_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), exponent);
2052          exponent = bld.sop2(aco_opcode::s_min_u32, bld.def(s1), bld.def(s1, scc), Operand(64u), exponent);
2053          Temp mantissa = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0x7fffffu), src);
2054          Temp sign = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
2055          mantissa = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(0x800000u), mantissa);
2056          mantissa = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), mantissa, Operand(7u));
2057          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), mantissa);
2058          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), Operand(63u), exponent);
2059          mantissa = bld.sop2(aco_opcode::s_lshr_b64, bld.def(s2), bld.def(s1, scc), mantissa, exponent);
2060          Temp cond = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), exponent, Operand(0xffffffffu)); // exp >= 64
2061          Temp saturate = bld.sop1(aco_opcode::s_brev_b64, bld.def(s2), Operand(0xfffffffeu));
2062          mantissa = bld.sop2(aco_opcode::s_cselect_b64, bld.def(s2), saturate, mantissa, cond);
2063          Temp lower = bld.tmp(s1), upper = bld.tmp(s1);
2064          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2065          lower = bld.sop2(aco_opcode::s_xor_b32, bld.def(s1), bld.def(s1, scc), sign, lower);
2066          upper = bld.sop2(aco_opcode::s_xor_b32, bld.def(s1), bld.def(s1, scc), sign, upper);
2067          Temp borrow = bld.tmp(s1);
2068          lower = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(borrow)), lower, sign);
2069          upper = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), upper, sign, borrow);
2070          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2071
2072       } else if (instr->src[0].src.ssa->bit_size == 64) {
2073          Temp vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0x3df00000u));
2074          Temp trunc = emit_trunc_f64(ctx, bld, bld.def(v2), src);
2075          Temp mul = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), trunc, vec);
2076          vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0xc1f00000u));
2077          Temp floor = emit_floor_f64(ctx, bld, bld.def(v2), mul);
2078          Temp fma = bld.vop3(aco_opcode::v_fma_f64, bld.def(v2), floor, vec, trunc);
2079          Temp lower = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), fma);
2080          Temp upper = bld.vop1(aco_opcode::v_cvt_i32_f64, bld.def(v1), floor);
2081          if (dst.type() == RegType::sgpr) {
2082             lower = bld.as_uniform(lower);
2083             upper = bld.as_uniform(upper);
2084          }
2085          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2086
2087       } else {
2088          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2089          nir_print_instr(&instr->instr, stderr);
2090          fprintf(stderr, "\n");
2091       }
2092       break;
2093    }
2094    case nir_op_f2u64: {
2095       Temp src = get_alu_src(ctx, instr->src[0]);
2096       if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::vgpr) {
2097          Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f32, bld.def(v1), src);
2098          Temp exponent_in_range = bld.vopc(aco_opcode::v_cmp_ge_i32, bld.hint_vcc(bld.def(bld.lm)), Operand(64u), exponent);
2099          exponent = bld.vop2(aco_opcode::v_max_i32, bld.def(v1), Operand(0x0u), exponent);
2100          Temp mantissa = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffu), src);
2101          mantissa = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(0x800000u), mantissa);
2102          Temp exponent_small = bld.vsub32(bld.def(v1), Operand(24u), exponent);
2103          Temp small = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), exponent_small, mantissa);
2104          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), mantissa);
2105          Temp new_exponent = bld.tmp(v1);
2106          Temp cond_small = bld.vsub32(Definition(new_exponent), exponent, Operand(24u), true).def(1).getTemp();
2107          if (ctx->program->chip_class >= GFX8)
2108             mantissa = bld.vop3(aco_opcode::v_lshlrev_b64, bld.def(v2), new_exponent, mantissa);
2109          else
2110             mantissa = bld.vop3(aco_opcode::v_lshl_b64, bld.def(v2), mantissa, new_exponent);
2111          Temp lower = bld.tmp(v1), upper = bld.tmp(v1);
2112          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2113          lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), lower, small, cond_small);
2114          upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), upper, Operand(0u), cond_small);
2115          lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xffffffffu), lower, exponent_in_range);
2116          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xffffffffu), upper, exponent_in_range);
2117          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2118
2119       } else if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::sgpr) {
2120          if (src.type() == RegType::vgpr)
2121             src = bld.as_uniform(src);
2122          Temp exponent = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), src, Operand(0x80017u));
2123          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(126u));
2124          exponent = bld.sop2(aco_opcode::s_max_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), exponent);
2125          Temp mantissa = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0x7fffffu), src);
2126          mantissa = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(0x800000u), mantissa);
2127          Temp exponent_small = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), Operand(24u), exponent);
2128          Temp small = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), mantissa, exponent_small);
2129          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), mantissa);
2130          Temp exponent_large = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(24u));
2131          mantissa = bld.sop2(aco_opcode::s_lshl_b64, bld.def(s2), bld.def(s1, scc), mantissa, exponent_large);
2132          Temp cond = bld.sopc(aco_opcode::s_cmp_ge_i32, bld.def(s1, scc), Operand(64u), exponent);
2133          mantissa = bld.sop2(aco_opcode::s_cselect_b64, bld.def(s2), mantissa, Operand(0xffffffffu), cond);
2134          Temp lower = bld.tmp(s1), upper = bld.tmp(s1);
2135          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2136          Temp cond_small = bld.sopc(aco_opcode::s_cmp_le_i32, bld.def(s1, scc), exponent, Operand(24u));
2137          lower = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), small, lower, cond_small);
2138          upper = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), Operand(0u), upper, cond_small);
2139          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2140
2141       } else if (instr->src[0].src.ssa->bit_size == 64) {
2142          Temp vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0x3df00000u));
2143          Temp trunc = emit_trunc_f64(ctx, bld, bld.def(v2), src);
2144          Temp mul = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), trunc, vec);
2145          vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0xc1f00000u));
2146          Temp floor = emit_floor_f64(ctx, bld, bld.def(v2), mul);
2147          Temp fma = bld.vop3(aco_opcode::v_fma_f64, bld.def(v2), floor, vec, trunc);
2148          Temp lower = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), fma);
2149          Temp upper = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), floor);
2150          if (dst.type() == RegType::sgpr) {
2151             lower = bld.as_uniform(lower);
2152             upper = bld.as_uniform(upper);
2153          }
2154          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2155
2156       } else {
2157          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2158          nir_print_instr(&instr->instr, stderr);
2159          fprintf(stderr, "\n");
2160       }
2161       break;
2162    }
2163    case nir_op_b2f32: {
2164       Temp src = get_alu_src(ctx, instr->src[0]);
2165       assert(src.regClass() == bld.lm);
2166
2167       if (dst.regClass() == s1) {
2168          src = bool_to_scalar_condition(ctx, src);
2169          bld.sop2(aco_opcode::s_mul_i32, Definition(dst), Operand(0x3f800000u), src);
2170       } else if (dst.regClass() == v1) {
2171          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(0x3f800000u), src);
2172       } else {
2173          unreachable("Wrong destination register class for nir_op_b2f32.");
2174       }
2175       break;
2176    }
2177    case nir_op_b2f64: {
2178       Temp src = get_alu_src(ctx, instr->src[0]);
2179       assert(src.regClass() == bld.lm);
2180
2181       if (dst.regClass() == s2) {
2182          src = bool_to_scalar_condition(ctx, src);
2183          bld.sop2(aco_opcode::s_cselect_b64, Definition(dst), Operand(0x3f800000u), Operand(0u), bld.scc(src));
2184       } else if (dst.regClass() == v2) {
2185          Temp one = bld.vop1(aco_opcode::v_mov_b32, bld.def(v2), Operand(0x3FF00000u));
2186          Temp upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), one, src);
2187          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), Operand(0u), upper);
2188       } else {
2189          unreachable("Wrong destination register class for nir_op_b2f64.");
2190       }
2191       break;
2192    }
2193    case nir_op_i2i32: {
2194       Temp src = get_alu_src(ctx, instr->src[0]);
2195       if (instr->src[0].src.ssa->bit_size == 64) {
2196          /* we can actually just say dst = src, as it would map the lower register */
2197          emit_extract_vector(ctx, src, 0, dst);
2198       } else {
2199          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2200          nir_print_instr(&instr->instr, stderr);
2201          fprintf(stderr, "\n");
2202       }
2203       break;
2204    }
2205    case nir_op_u2u32: {
2206       Temp src = get_alu_src(ctx, instr->src[0]);
2207       if (instr->src[0].src.ssa->bit_size == 16) {
2208          if (dst.regClass() == s1) {
2209             bld.sop2(aco_opcode::s_and_b32, Definition(dst), bld.def(s1, scc), Operand(0xFFFFu), src);
2210          } else {
2211             // TODO: do better with SDWA
2212             bld.vop2(aco_opcode::v_and_b32, Definition(dst), Operand(0xFFFFu), src);
2213          }
2214       } else if (instr->src[0].src.ssa->bit_size == 64) {
2215          /* we can actually just say dst = src, as it would map the lower register */
2216          emit_extract_vector(ctx, src, 0, dst);
2217       } else {
2218          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2219          nir_print_instr(&instr->instr, stderr);
2220          fprintf(stderr, "\n");
2221       }
2222       break;
2223    }
2224    case nir_op_i2i64: {
2225       Temp src = get_alu_src(ctx, instr->src[0]);
2226       if (src.regClass() == s1) {
2227          Temp high = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
2228          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, high);
2229       } else if (src.regClass() == v1) {
2230          Temp high = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
2231          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, high);
2232       } else {
2233          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2234          nir_print_instr(&instr->instr, stderr);
2235          fprintf(stderr, "\n");
2236       }
2237       break;
2238    }
2239    case nir_op_u2u64: {
2240       Temp src = get_alu_src(ctx, instr->src[0]);
2241       if (instr->src[0].src.ssa->bit_size == 32) {
2242          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, Operand(0u));
2243       } else {
2244          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2245          nir_print_instr(&instr->instr, stderr);
2246          fprintf(stderr, "\n");
2247       }
2248       break;
2249    }
2250    case nir_op_b2i32: {
2251       Temp src = get_alu_src(ctx, instr->src[0]);
2252       assert(src.regClass() == bld.lm);
2253
2254       if (dst.regClass() == s1) {
2255          // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2256          bool_to_scalar_condition(ctx, src, dst);
2257       } else if (dst.regClass() == v1) {
2258          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), src);
2259       } else {
2260          unreachable("Invalid register class for b2i32");
2261       }
2262       break;
2263    }
2264    case nir_op_i2b1: {
2265       Temp src = get_alu_src(ctx, instr->src[0]);
2266       assert(dst.regClass() == bld.lm);
2267
2268       if (src.type() == RegType::vgpr) {
2269          assert(src.regClass() == v1 || src.regClass() == v2);
2270          assert(dst.regClass() == bld.lm);
2271          bld.vopc(src.size() == 2 ? aco_opcode::v_cmp_lg_u64 : aco_opcode::v_cmp_lg_u32,
2272                   Definition(dst), Operand(0u), src).def(0).setHint(vcc);
2273       } else {
2274          assert(src.regClass() == s1 || src.regClass() == s2);
2275          Temp tmp;
2276          if (src.regClass() == s2 && ctx->program->chip_class <= GFX7) {
2277             tmp = bld.sop2(aco_opcode::s_or_b64, bld.def(s2), bld.def(s1, scc), Operand(0u), src).def(1).getTemp();
2278          } else {
2279             tmp = bld.sopc(src.size() == 2 ? aco_opcode::s_cmp_lg_u64 : aco_opcode::s_cmp_lg_u32,
2280                            bld.scc(bld.def(s1)), Operand(0u), src);
2281          }
2282          bool_to_vector_condition(ctx, tmp, dst);
2283       }
2284       break;
2285    }
2286    case nir_op_pack_64_2x32_split: {
2287       Temp src0 = get_alu_src(ctx, instr->src[0]);
2288       Temp src1 = get_alu_src(ctx, instr->src[1]);
2289
2290       bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src0, src1);
2291       break;
2292    }
2293    case nir_op_unpack_64_2x32_split_x:
2294       bld.pseudo(aco_opcode::p_split_vector, Definition(dst), bld.def(dst.regClass()), get_alu_src(ctx, instr->src[0]));
2295       break;
2296    case nir_op_unpack_64_2x32_split_y:
2297       bld.pseudo(aco_opcode::p_split_vector, bld.def(dst.regClass()), Definition(dst), get_alu_src(ctx, instr->src[0]));
2298       break;
2299    case nir_op_pack_half_2x16: {
2300       Temp src = get_alu_src(ctx, instr->src[0], 2);
2301
2302       if (dst.regClass() == v1) {
2303          Temp src0 = bld.tmp(v1);
2304          Temp src1 = bld.tmp(v1);
2305          bld.pseudo(aco_opcode::p_split_vector, Definition(src0), Definition(src1), src);
2306          if (!ctx->block->fp_mode.care_about_round32 || ctx->block->fp_mode.round32 == fp_round_tz)
2307             bld.vop3(aco_opcode::v_cvt_pkrtz_f16_f32, Definition(dst), src0, src1);
2308          else
2309             bld.vop3(aco_opcode::v_cvt_pk_u16_u32, Definition(dst),
2310                      bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src0),
2311                      bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src1));
2312       } else {
2313          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2314          nir_print_instr(&instr->instr, stderr);
2315          fprintf(stderr, "\n");
2316       }
2317       break;
2318    }
2319    case nir_op_unpack_half_2x16_split_x: {
2320       if (dst.regClass() == v1) {
2321          Builder bld(ctx->program, ctx->block);
2322          bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst), get_alu_src(ctx, instr->src[0]));
2323       } else {
2324          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2325          nir_print_instr(&instr->instr, stderr);
2326          fprintf(stderr, "\n");
2327       }
2328       break;
2329    }
2330    case nir_op_unpack_half_2x16_split_y: {
2331       if (dst.regClass() == v1) {
2332          Builder bld(ctx->program, ctx->block);
2333          /* TODO: use SDWA here */
2334          bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst),
2335                   bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(16u), as_vgpr(ctx, get_alu_src(ctx, instr->src[0]))));
2336       } else {
2337          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2338          nir_print_instr(&instr->instr, stderr);
2339          fprintf(stderr, "\n");
2340       }
2341       break;
2342    }
2343    case nir_op_fquantize2f16: {
2344       Temp src = get_alu_src(ctx, instr->src[0]);
2345       Temp f16 = bld.vop1(aco_opcode::v_cvt_f16_f32, bld.def(v1), src);
2346       Temp f32, cmp_res;
2347
2348       if (ctx->program->chip_class >= GFX8) {
2349          Temp mask = bld.copy(bld.def(s1), Operand(0x36Fu)); /* value is NOT negative/positive denormal value */
2350          cmp_res = bld.vopc_e64(aco_opcode::v_cmp_class_f16, bld.hint_vcc(bld.def(bld.lm)), f16, mask);
2351          f32 = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), f16);
2352       } else {
2353          /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2354           * so compare the result and flush to 0 if it's smaller.
2355           */
2356          f32 = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), f16);
2357          Temp smallest = bld.copy(bld.def(s1), Operand(0x38800000u));
2358          Instruction* vop3 = bld.vopc_e64(aco_opcode::v_cmp_nlt_f32, bld.hint_vcc(bld.def(bld.lm)), f32, smallest);
2359          static_cast<VOP3A_instruction*>(vop3)->abs[0] = true;
2360          cmp_res = vop3->definitions[0].getTemp();
2361       }
2362
2363       if (ctx->block->fp_mode.preserve_signed_zero_inf_nan32 || ctx->program->chip_class < GFX8) {
2364          Temp copysign_0 = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0u), as_vgpr(ctx, src));
2365          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), copysign_0, f32, cmp_res);
2366       } else {
2367          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), f32, cmp_res);
2368       }
2369       break;
2370    }
2371    case nir_op_bfm: {
2372       Temp bits = get_alu_src(ctx, instr->src[0]);
2373       Temp offset = get_alu_src(ctx, instr->src[1]);
2374
2375       if (dst.regClass() == s1) {
2376          bld.sop2(aco_opcode::s_bfm_b32, Definition(dst), bits, offset);
2377       } else if (dst.regClass() == v1) {
2378          bld.vop3(aco_opcode::v_bfm_b32, Definition(dst), bits, offset);
2379       } else {
2380          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2381          nir_print_instr(&instr->instr, stderr);
2382          fprintf(stderr, "\n");
2383       }
2384       break;
2385    }
2386    case nir_op_bitfield_select: {
2387       /* (mask & insert) | (~mask & base) */
2388       Temp bitmask = get_alu_src(ctx, instr->src[0]);
2389       Temp insert = get_alu_src(ctx, instr->src[1]);
2390       Temp base = get_alu_src(ctx, instr->src[2]);
2391
2392       /* dst = (insert & bitmask) | (base & ~bitmask) */
2393       if (dst.regClass() == s1) {
2394          aco_ptr<Instruction> sop2;
2395          nir_const_value* const_bitmask = nir_src_as_const_value(instr->src[0].src);
2396          nir_const_value* const_insert = nir_src_as_const_value(instr->src[1].src);
2397          Operand lhs;
2398          if (const_insert && const_bitmask) {
2399             lhs = Operand(const_insert->u32 & const_bitmask->u32);
2400          } else {
2401             insert = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), insert, bitmask);
2402             lhs = Operand(insert);
2403          }
2404
2405          Operand rhs;
2406          nir_const_value* const_base = nir_src_as_const_value(instr->src[2].src);
2407          if (const_base && const_bitmask) {
2408             rhs = Operand(const_base->u32 & ~const_bitmask->u32);
2409          } else {
2410             base = bld.sop2(aco_opcode::s_andn2_b32, bld.def(s1), bld.def(s1, scc), base, bitmask);
2411             rhs = Operand(base);
2412          }
2413
2414          bld.sop2(aco_opcode::s_or_b32, Definition(dst), bld.def(s1, scc), rhs, lhs);
2415
2416       } else if (dst.regClass() == v1) {
2417          if (base.type() == RegType::sgpr && (bitmask.type() == RegType::sgpr || (insert.type() == RegType::sgpr)))
2418             base = as_vgpr(ctx, base);
2419          if (insert.type() == RegType::sgpr && bitmask.type() == RegType::sgpr)
2420             insert = as_vgpr(ctx, insert);
2421
2422          bld.vop3(aco_opcode::v_bfi_b32, Definition(dst), bitmask, insert, base);
2423
2424       } else {
2425          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2426          nir_print_instr(&instr->instr, stderr);
2427          fprintf(stderr, "\n");
2428       }
2429       break;
2430    }
2431    case nir_op_ubfe:
2432    case nir_op_ibfe: {
2433       Temp base = get_alu_src(ctx, instr->src[0]);
2434       Temp offset = get_alu_src(ctx, instr->src[1]);
2435       Temp bits = get_alu_src(ctx, instr->src[2]);
2436
2437       if (dst.type() == RegType::sgpr) {
2438          Operand extract;
2439          nir_const_value* const_offset = nir_src_as_const_value(instr->src[1].src);
2440          nir_const_value* const_bits = nir_src_as_const_value(instr->src[2].src);
2441          if (const_offset && const_bits) {
2442             uint32_t const_extract = (const_bits->u32 << 16) | const_offset->u32;
2443             extract = Operand(const_extract);
2444          } else {
2445             Operand width;
2446             if (const_bits) {
2447                width = Operand(const_bits->u32 << 16);
2448             } else {
2449                width = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), bits, Operand(16u));
2450             }
2451             extract = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), offset, width);
2452          }
2453
2454          aco_opcode opcode;
2455          if (dst.regClass() == s1) {
2456             if (instr->op == nir_op_ubfe)
2457                opcode = aco_opcode::s_bfe_u32;
2458             else
2459                opcode = aco_opcode::s_bfe_i32;
2460          } else if (dst.regClass() == s2) {
2461             if (instr->op == nir_op_ubfe)
2462                opcode = aco_opcode::s_bfe_u64;
2463             else
2464                opcode = aco_opcode::s_bfe_i64;
2465          } else {
2466             unreachable("Unsupported BFE bit size");
2467          }
2468
2469          bld.sop2(opcode, Definition(dst), bld.def(s1, scc), base, extract);
2470
2471       } else {
2472          aco_opcode opcode;
2473          if (dst.regClass() == v1) {
2474             if (instr->op == nir_op_ubfe)
2475                opcode = aco_opcode::v_bfe_u32;
2476             else
2477                opcode = aco_opcode::v_bfe_i32;
2478          } else {
2479             unreachable("Unsupported BFE bit size");
2480          }
2481
2482          emit_vop3a_instruction(ctx, instr, opcode, dst);
2483       }
2484       break;
2485    }
2486    case nir_op_bit_count: {
2487       Temp src = get_alu_src(ctx, instr->src[0]);
2488       if (src.regClass() == s1) {
2489          bld.sop1(aco_opcode::s_bcnt1_i32_b32, Definition(dst), bld.def(s1, scc), src);
2490       } else if (src.regClass() == v1) {
2491          bld.vop3(aco_opcode::v_bcnt_u32_b32, Definition(dst), src, Operand(0u));
2492       } else if (src.regClass() == v2) {
2493          bld.vop3(aco_opcode::v_bcnt_u32_b32, Definition(dst),
2494                   emit_extract_vector(ctx, src, 1, v1),
2495                   bld.vop3(aco_opcode::v_bcnt_u32_b32, bld.def(v1),
2496                            emit_extract_vector(ctx, src, 0, v1), Operand(0u)));
2497       } else if (src.regClass() == s2) {
2498          bld.sop1(aco_opcode::s_bcnt1_i32_b64, Definition(dst), bld.def(s1, scc), src);
2499       } else {
2500          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2501          nir_print_instr(&instr->instr, stderr);
2502          fprintf(stderr, "\n");
2503       }
2504       break;
2505    }
2506    case nir_op_flt: {
2507       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_f32, aco_opcode::v_cmp_lt_f64);
2508       break;
2509    }
2510    case nir_op_fge: {
2511       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_f32, aco_opcode::v_cmp_ge_f64);
2512       break;
2513    }
2514    case nir_op_feq: {
2515       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_eq_f32, aco_opcode::v_cmp_eq_f64);
2516       break;
2517    }
2518    case nir_op_fne: {
2519       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_neq_f32, aco_opcode::v_cmp_neq_f64);
2520       break;
2521    }
2522    case nir_op_ilt: {
2523       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_i32, aco_opcode::v_cmp_lt_i64, aco_opcode::s_cmp_lt_i32);
2524       break;
2525    }
2526    case nir_op_ige: {
2527       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_i32, aco_opcode::v_cmp_ge_i64, aco_opcode::s_cmp_ge_i32);
2528       break;
2529    }
2530    case nir_op_ieq: {
2531       if (instr->src[0].src.ssa->bit_size == 1)
2532          emit_boolean_logic(ctx, instr, Builder::s_xnor, dst);
2533       else
2534          emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_eq_i32, aco_opcode::v_cmp_eq_i64, aco_opcode::s_cmp_eq_i32,
2535                          ctx->program->chip_class >= GFX8 ? aco_opcode::s_cmp_eq_u64 : aco_opcode::num_opcodes);
2536       break;
2537    }
2538    case nir_op_ine: {
2539       if (instr->src[0].src.ssa->bit_size == 1)
2540          emit_boolean_logic(ctx, instr, Builder::s_xor, dst);
2541       else
2542          emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lg_i32, aco_opcode::v_cmp_lg_i64, aco_opcode::s_cmp_lg_i32,
2543                          ctx->program->chip_class >= GFX8 ? aco_opcode::s_cmp_lg_u64 : aco_opcode::num_opcodes);
2544       break;
2545    }
2546    case nir_op_ult: {
2547       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_u32, aco_opcode::v_cmp_lt_u64, aco_opcode::s_cmp_lt_u32);
2548       break;
2549    }
2550    case nir_op_uge: {
2551       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_u32, aco_opcode::v_cmp_ge_u64, aco_opcode::s_cmp_ge_u32);
2552       break;
2553    }
2554    case nir_op_fddx:
2555    case nir_op_fddy:
2556    case nir_op_fddx_fine:
2557    case nir_op_fddy_fine:
2558    case nir_op_fddx_coarse:
2559    case nir_op_fddy_coarse: {
2560       Temp src = get_alu_src(ctx, instr->src[0]);
2561       uint16_t dpp_ctrl1, dpp_ctrl2;
2562       if (instr->op == nir_op_fddx_fine) {
2563          dpp_ctrl1 = dpp_quad_perm(0, 0, 2, 2);
2564          dpp_ctrl2 = dpp_quad_perm(1, 1, 3, 3);
2565       } else if (instr->op == nir_op_fddy_fine) {
2566          dpp_ctrl1 = dpp_quad_perm(0, 1, 0, 1);
2567          dpp_ctrl2 = dpp_quad_perm(2, 3, 2, 3);
2568       } else {
2569          dpp_ctrl1 = dpp_quad_perm(0, 0, 0, 0);
2570          if (instr->op == nir_op_fddx || instr->op == nir_op_fddx_coarse)
2571             dpp_ctrl2 = dpp_quad_perm(1, 1, 1, 1);
2572          else
2573             dpp_ctrl2 = dpp_quad_perm(2, 2, 2, 2);
2574       }
2575
2576       Temp tmp;
2577       if (ctx->program->chip_class >= GFX8) {
2578          Temp tl = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl1);
2579          tmp = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), src, tl, dpp_ctrl2);
2580       } else {
2581          Temp tl = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl1);
2582          Temp tr = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl2);
2583          tmp = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), tr, tl);
2584       }
2585       emit_wqm(ctx, tmp, dst, true);
2586       break;
2587    }
2588    default:
2589       fprintf(stderr, "Unknown NIR ALU instr: ");
2590       nir_print_instr(&instr->instr, stderr);
2591       fprintf(stderr, "\n");
2592    }
2593 }
2594
2595 void visit_load_const(isel_context *ctx, nir_load_const_instr *instr)
2596 {
2597    Temp dst = get_ssa_temp(ctx, &instr->def);
2598
2599    // TODO: we really want to have the resulting type as this would allow for 64bit literals
2600    // which get truncated the lsb if double and msb if int
2601    // for now, we only use s_mov_b64 with 64bit inline constants
2602    assert(instr->def.num_components == 1 && "Vector load_const should be lowered to scalar.");
2603    assert(dst.type() == RegType::sgpr);
2604
2605    Builder bld(ctx->program, ctx->block);
2606
2607    if (instr->def.bit_size == 1) {
2608       assert(dst.regClass() == bld.lm);
2609       int val = instr->value[0].b ? -1 : 0;
2610       Operand op = bld.lm.size() == 1 ? Operand((uint32_t) val) : Operand((uint64_t) val);
2611       bld.sop1(Builder::s_mov, Definition(dst), op);
2612    } else if (dst.size() == 1) {
2613       bld.copy(Definition(dst), Operand(instr->value[0].u32));
2614    } else {
2615       assert(dst.size() != 1);
2616       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
2617       if (instr->def.bit_size == 64)
2618          for (unsigned i = 0; i < dst.size(); i++)
2619             vec->operands[i] = Operand{(uint32_t)(instr->value[0].u64 >> i * 32)};
2620       else {
2621          for (unsigned i = 0; i < dst.size(); i++)
2622             vec->operands[i] = Operand{instr->value[i].u32};
2623       }
2624       vec->definitions[0] = Definition(dst);
2625       ctx->block->instructions.emplace_back(std::move(vec));
2626    }
2627 }
2628
2629 uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2630 {
2631    uint32_t new_mask = 0;
2632    for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2633       if (mask & (1u << i))
2634          new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2635    return new_mask;
2636 }
2637
2638 Operand load_lds_size_m0(isel_context *ctx)
2639 {
2640    /* TODO: m0 does not need to be initialized on GFX9+ */
2641    Builder bld(ctx->program, ctx->block);
2642    return bld.m0((Temp)bld.sopk(aco_opcode::s_movk_i32, bld.def(s1, m0), 0xffff));
2643 }
2644
2645 Temp load_lds(isel_context *ctx, unsigned elem_size_bytes, Temp dst,
2646               Temp address, unsigned base_offset, unsigned align)
2647 {
2648    assert(util_is_power_of_two_nonzero(align) && align >= 4);
2649
2650    Builder bld(ctx->program, ctx->block);
2651
2652    Operand m = load_lds_size_m0(ctx);
2653
2654    unsigned num_components = dst.size() * 4u / elem_size_bytes;
2655    unsigned bytes_read = 0;
2656    unsigned result_size = 0;
2657    unsigned total_bytes = num_components * elem_size_bytes;
2658    std::array<Temp, NIR_MAX_VEC_COMPONENTS> result;
2659    bool large_ds_read = ctx->options->chip_class >= GFX7;
2660    bool usable_read2 = ctx->options->chip_class >= GFX7;
2661
2662    while (bytes_read < total_bytes) {
2663       unsigned todo = total_bytes - bytes_read;
2664       bool aligned8 = bytes_read % 8 == 0 && align % 8 == 0;
2665       bool aligned16 = bytes_read % 16 == 0 && align % 16 == 0;
2666
2667       aco_opcode op = aco_opcode::last_opcode;
2668       bool read2 = false;
2669       if (todo >= 16 && aligned16 && large_ds_read) {
2670          op = aco_opcode::ds_read_b128;
2671          todo = 16;
2672       } else if (todo >= 16 && aligned8 && usable_read2) {
2673          op = aco_opcode::ds_read2_b64;
2674          read2 = true;
2675          todo = 16;
2676       } else if (todo >= 12 && aligned16 && large_ds_read) {
2677          op = aco_opcode::ds_read_b96;
2678          todo = 12;
2679       } else if (todo >= 8 && aligned8) {
2680          op = aco_opcode::ds_read_b64;
2681          todo = 8;
2682       } else if (todo >= 8 && usable_read2) {
2683          op = aco_opcode::ds_read2_b32;
2684          read2 = true;
2685          todo = 8;
2686       } else if (todo >= 4) {
2687          op = aco_opcode::ds_read_b32;
2688          todo = 4;
2689       } else {
2690          assert(false);
2691       }
2692       assert(todo % elem_size_bytes == 0);
2693       unsigned num_elements = todo / elem_size_bytes;
2694       unsigned offset = base_offset + bytes_read;
2695       unsigned max_offset = read2 ? 1019 : 65535;
2696
2697       Temp address_offset = address;
2698       if (offset > max_offset) {
2699          address_offset = bld.vadd32(bld.def(v1), Operand(base_offset), address_offset);
2700          offset = bytes_read;
2701       }
2702       assert(offset <= max_offset); /* bytes_read shouldn't be large enough for this to happen */
2703
2704       Temp res;
2705       if (num_components == 1 && dst.type() == RegType::vgpr)
2706          res = dst;
2707       else
2708          res = bld.tmp(RegClass(RegType::vgpr, todo / 4));
2709
2710       if (read2)
2711          res = bld.ds(op, Definition(res), address_offset, m, offset / (todo / 2), (offset / (todo / 2)) + 1);
2712       else
2713          res = bld.ds(op, Definition(res), address_offset, m, offset);
2714
2715       if (num_components == 1) {
2716          assert(todo == total_bytes);
2717          if (dst.type() == RegType::sgpr)
2718             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), res);
2719          return dst;
2720       }
2721
2722       if (dst.type() == RegType::sgpr) {
2723          Temp new_res = bld.tmp(RegType::sgpr, res.size());
2724          expand_vector(ctx, res, new_res, res.size(), (1 << res.size()) - 1);
2725          res = new_res;
2726       }
2727
2728       if (num_elements == 1) {
2729          result[result_size++] = res;
2730       } else {
2731          assert(res != dst && res.size() % num_elements == 0);
2732          aco_ptr<Pseudo_instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector, Format::PSEUDO, 1, num_elements)};
2733          split->operands[0] = Operand(res);
2734          for (unsigned i = 0; i < num_elements; i++)
2735             split->definitions[i] = Definition(result[result_size++] = bld.tmp(res.type(), elem_size_bytes / 4));
2736          ctx->block->instructions.emplace_back(std::move(split));
2737       }
2738
2739       bytes_read += todo;
2740    }
2741
2742    assert(result_size == num_components && result_size > 1);
2743    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, result_size, 1)};
2744    for (unsigned i = 0; i < result_size; i++)
2745       vec->operands[i] = Operand(result[i]);
2746    vec->definitions[0] = Definition(dst);
2747    ctx->block->instructions.emplace_back(std::move(vec));
2748    ctx->allocated_vec.emplace(dst.id(), result);
2749
2750    return dst;
2751 }
2752
2753 Temp extract_subvector(isel_context *ctx, Temp data, unsigned start, unsigned size, RegType type)
2754 {
2755    if (start == 0 && size == data.size())
2756       return type == RegType::vgpr ? as_vgpr(ctx, data) : data;
2757
2758    unsigned size_hint = 1;
2759    auto it = ctx->allocated_vec.find(data.id());
2760    if (it != ctx->allocated_vec.end())
2761       size_hint = it->second[0].size();
2762    if (size % size_hint || start % size_hint)
2763       size_hint = 1;
2764
2765    start /= size_hint;
2766    size /= size_hint;
2767
2768    Temp elems[size];
2769    for (unsigned i = 0; i < size; i++)
2770       elems[i] = emit_extract_vector(ctx, data, start + i, RegClass(type, size_hint));
2771
2772    if (size == 1)
2773       return type == RegType::vgpr ? as_vgpr(ctx, elems[0]) : elems[0];
2774
2775    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, size, 1)};
2776    for (unsigned i = 0; i < size; i++)
2777       vec->operands[i] = Operand(elems[i]);
2778    Temp res = {ctx->program->allocateId(), RegClass(type, size * size_hint)};
2779    vec->definitions[0] = Definition(res);
2780    ctx->block->instructions.emplace_back(std::move(vec));
2781    return res;
2782 }
2783
2784 void ds_write_helper(isel_context *ctx, Operand m, Temp address, Temp data, unsigned data_start, unsigned total_size, unsigned offset0, unsigned offset1, unsigned align)
2785 {
2786    Builder bld(ctx->program, ctx->block);
2787    unsigned bytes_written = 0;
2788    bool large_ds_write = ctx->options->chip_class >= GFX7;
2789    bool usable_write2 = ctx->options->chip_class >= GFX7;
2790
2791    while (bytes_written < total_size * 4) {
2792       unsigned todo = total_size * 4 - bytes_written;
2793       bool aligned8 = bytes_written % 8 == 0 && align % 8 == 0;
2794       bool aligned16 = bytes_written % 16 == 0 && align % 16 == 0;
2795
2796       aco_opcode op = aco_opcode::last_opcode;
2797       bool write2 = false;
2798       unsigned size = 0;
2799       if (todo >= 16 && aligned16 && large_ds_write) {
2800          op = aco_opcode::ds_write_b128;
2801          size = 4;
2802       } else if (todo >= 16 && aligned8 && usable_write2) {
2803          op = aco_opcode::ds_write2_b64;
2804          write2 = true;
2805          size = 4;
2806       } else if (todo >= 12 && aligned16 && large_ds_write) {
2807          op = aco_opcode::ds_write_b96;
2808          size = 3;
2809       } else if (todo >= 8 && aligned8) {
2810          op = aco_opcode::ds_write_b64;
2811          size = 2;
2812       } else if (todo >= 8 && usable_write2) {
2813          op = aco_opcode::ds_write2_b32;
2814          write2 = true;
2815          size = 2;
2816       } else if (todo >= 4) {
2817          op = aco_opcode::ds_write_b32;
2818          size = 1;
2819       } else {
2820          assert(false);
2821       }
2822
2823       unsigned offset = offset0 + offset1 + bytes_written;
2824       unsigned max_offset = write2 ? 1020 : 65535;
2825       Temp address_offset = address;
2826       if (offset > max_offset) {
2827          address_offset = bld.vadd32(bld.def(v1), Operand(offset0), address_offset);
2828          offset = offset1 + bytes_written;
2829       }
2830       assert(offset <= max_offset); /* offset1 shouldn't be large enough for this to happen */
2831
2832       if (write2) {
2833          Temp val0 = extract_subvector(ctx, data, data_start + (bytes_written >> 2), size / 2, RegType::vgpr);
2834          Temp val1 = extract_subvector(ctx, data, data_start + (bytes_written >> 2) + 1, size / 2, RegType::vgpr);
2835          bld.ds(op, address_offset, val0, val1, m, offset / size / 2, (offset / size / 2) + 1);
2836       } else {
2837          Temp val = extract_subvector(ctx, data, data_start + (bytes_written >> 2), size, RegType::vgpr);
2838          bld.ds(op, address_offset, val, m, offset);
2839       }
2840
2841       bytes_written += size * 4;
2842    }
2843 }
2844
2845 void store_lds(isel_context *ctx, unsigned elem_size_bytes, Temp data, uint32_t wrmask,
2846                Temp address, unsigned base_offset, unsigned align)
2847 {
2848    assert(util_is_power_of_two_nonzero(align) && align >= 4);
2849    assert(elem_size_bytes == 4 || elem_size_bytes == 8);
2850
2851    Operand m = load_lds_size_m0(ctx);
2852
2853    /* we need at most two stores, assuming that the writemask is at most 4 bits wide */
2854    assert(wrmask <= 0x0f);
2855    int start[2], count[2];
2856    u_bit_scan_consecutive_range(&wrmask, &start[0], &count[0]);
2857    u_bit_scan_consecutive_range(&wrmask, &start[1], &count[1]);
2858    assert(wrmask == 0);
2859
2860    /* one combined store is sufficient */
2861    if (count[0] == count[1] && (align % elem_size_bytes) == 0 && (base_offset % elem_size_bytes) == 0) {
2862       Builder bld(ctx->program, ctx->block);
2863
2864       Temp address_offset = address;
2865       if ((base_offset / elem_size_bytes) + start[1] > 255) {
2866          address_offset = bld.vadd32(bld.def(v1), Operand(base_offset), address_offset);
2867          base_offset = 0;
2868       }
2869
2870       assert(count[0] == 1);
2871       RegClass xtract_rc(RegType::vgpr, elem_size_bytes / 4);
2872
2873       Temp val0 = emit_extract_vector(ctx, data, start[0], xtract_rc);
2874       Temp val1 = emit_extract_vector(ctx, data, start[1], xtract_rc);
2875       aco_opcode op = elem_size_bytes == 4 ? aco_opcode::ds_write2_b32 : aco_opcode::ds_write2_b64;
2876       base_offset = base_offset / elem_size_bytes;
2877       bld.ds(op, address_offset, val0, val1, m,
2878              base_offset + start[0], base_offset + start[1]);
2879       return;
2880    }
2881
2882    for (unsigned i = 0; i < 2; i++) {
2883       if (count[i] == 0)
2884          continue;
2885
2886       unsigned elem_size_words = elem_size_bytes / 4;
2887       ds_write_helper(ctx, m, address, data, start[i] * elem_size_words, count[i] * elem_size_words,
2888                       base_offset, start[i] * elem_size_bytes, align);
2889    }
2890    return;
2891 }
2892
2893 unsigned calculate_lds_alignment(isel_context *ctx, unsigned const_offset)
2894 {
2895    unsigned align = 16;
2896    if (const_offset)
2897       align = std::min(align, 1u << (ffs(const_offset) - 1));
2898
2899    return align;
2900 }
2901
2902
2903 Temp create_vec_from_array(isel_context *ctx, Temp arr[], unsigned cnt, RegType reg_type, unsigned split_cnt = 0u, Temp dst = Temp())
2904 {
2905    Builder bld(ctx->program, ctx->block);
2906
2907    if (!dst.id())
2908       dst = bld.tmp(RegClass(reg_type, cnt * arr[0].size()));
2909
2910    std::array<Temp, NIR_MAX_VEC_COMPONENTS> allocated_vec;
2911    aco_ptr<Pseudo_instruction> instr {create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, cnt, 1)};
2912    instr->definitions[0] = Definition(dst);
2913
2914    for (unsigned i = 0; i < cnt; ++i) {
2915       assert(arr[i].size() == arr[0].size());
2916       allocated_vec[i] = arr[i];
2917       instr->operands[i] = Operand(arr[i]);
2918    }
2919
2920    bld.insert(std::move(instr));
2921
2922    if (split_cnt)
2923       emit_split_vector(ctx, dst, split_cnt);
2924    else
2925       ctx->allocated_vec.emplace(dst.id(), allocated_vec); /* emit_split_vector already does this */
2926
2927    return dst;
2928 }
2929
2930 inline unsigned resolve_excess_vmem_const_offset(Builder &bld, Temp &voffset, unsigned const_offset)
2931 {
2932    if (const_offset >= 4096) {
2933       unsigned excess_const_offset = const_offset / 4096u * 4096u;
2934       const_offset %= 4096u;
2935
2936       if (!voffset.id())
2937          voffset = bld.copy(bld.def(v1), Operand(excess_const_offset));
2938       else if (unlikely(voffset.regClass() == s1))
2939          voffset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), Operand(excess_const_offset), Operand(voffset));
2940       else if (likely(voffset.regClass() == v1))
2941          voffset = bld.vadd32(bld.def(v1), Operand(voffset), Operand(excess_const_offset));
2942       else
2943          unreachable("Unsupported register class of voffset");
2944    }
2945
2946    return const_offset;
2947 }
2948
2949 void emit_single_mubuf_store(isel_context *ctx, Temp descriptor, Temp voffset, Temp soffset, Temp vdata,
2950                              unsigned const_offset = 0u, bool allow_reorder = true, bool slc = false)
2951 {
2952    assert(vdata.id());
2953    assert(vdata.size() != 3 || ctx->program->chip_class != GFX6);
2954    assert(vdata.size() >= 1 && vdata.size() <= 4);
2955
2956    Builder bld(ctx->program, ctx->block);
2957    aco_opcode op = (aco_opcode) ((unsigned) aco_opcode::buffer_store_dword + vdata.size() - 1);
2958    const_offset = resolve_excess_vmem_const_offset(bld, voffset, const_offset);
2959
2960    Operand voffset_op = voffset.id() ? Operand(as_vgpr(ctx, voffset)) : Operand(v1);
2961    Operand soffset_op = soffset.id() ? Operand(soffset) : Operand(0u);
2962    Builder::Result r = bld.mubuf(op, Operand(descriptor), voffset_op, soffset_op, Operand(vdata), const_offset,
2963                                  /* offen */ !voffset_op.isUndefined(), /* idxen*/ false, /* addr64 */ false,
2964                                  /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc);
2965
2966    static_cast<MUBUF_instruction *>(r.instr)->can_reorder = allow_reorder;
2967 }
2968
2969 void store_vmem_mubuf(isel_context *ctx, Temp src, Temp descriptor, Temp voffset, Temp soffset,
2970                                    unsigned base_const_offset, unsigned elem_size_bytes, unsigned write_mask,
2971                                    bool allow_combining = true, bool reorder = true, bool slc = false)
2972 {
2973    Builder bld(ctx->program, ctx->block);
2974    assert(elem_size_bytes == 4 || elem_size_bytes == 8);
2975    assert(write_mask);
2976
2977    if (elem_size_bytes == 8) {
2978       elem_size_bytes = 4;
2979       write_mask = widen_mask(write_mask, 2);
2980    }
2981
2982    while (write_mask) {
2983       int start = 0;
2984       int count = 0;
2985       u_bit_scan_consecutive_range(&write_mask, &start, &count);
2986       assert(count > 0);
2987       assert(start >= 0);
2988
2989       while (count > 0) {
2990          unsigned sub_count = allow_combining ? MIN2(count, 4) : 1;
2991          unsigned const_offset = (unsigned) start * elem_size_bytes + base_const_offset;
2992
2993          /* GFX6 doesn't have buffer_store_dwordx3, so make sure not to emit that here either. */
2994          if (unlikely(ctx->program->chip_class == GFX6 && sub_count == 3))
2995             sub_count = 2;
2996
2997          Temp elem = extract_subvector(ctx, src, start, sub_count, RegType::vgpr);
2998          emit_single_mubuf_store(ctx, descriptor, voffset, soffset, elem, const_offset, reorder, slc);
2999
3000          count -= sub_count;
3001          start += sub_count;
3002       }
3003
3004       assert(count == 0);
3005    }
3006 }
3007
3008 Temp emit_single_mubuf_load(isel_context *ctx, Temp descriptor, Temp voffset, Temp soffset,
3009                             unsigned const_offset, unsigned size_dwords, bool allow_reorder = true)
3010 {
3011    assert(size_dwords != 3 || ctx->program->chip_class != GFX6);
3012    assert(size_dwords >= 1 && size_dwords <= 4);
3013
3014    Builder bld(ctx->program, ctx->block);
3015    Temp vdata = bld.tmp(RegClass(RegType::vgpr, size_dwords));
3016    aco_opcode op = (aco_opcode) ((unsigned) aco_opcode::buffer_load_dword + size_dwords - 1);
3017    const_offset = resolve_excess_vmem_const_offset(bld, voffset, const_offset);
3018
3019    Operand voffset_op = voffset.id() ? Operand(as_vgpr(ctx, voffset)) : Operand(v1);
3020    Operand soffset_op = soffset.id() ? Operand(soffset) : Operand(0u);
3021    Builder::Result r = bld.mubuf(op, Definition(vdata), Operand(descriptor), voffset_op, soffset_op, const_offset,
3022                                  /* offen */ !voffset_op.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3023                                  /* disable_wqm */ false, /* glc */ true,
3024                                  /* dlc*/ ctx->program->chip_class >= GFX10, /* slc */ false);
3025
3026    static_cast<MUBUF_instruction *>(r.instr)->can_reorder = allow_reorder;
3027
3028    return vdata;
3029 }
3030
3031 void load_vmem_mubuf(isel_context *ctx, Temp dst, Temp descriptor, Temp voffset, Temp soffset,
3032                      unsigned base_const_offset, unsigned elem_size_bytes, unsigned num_components,
3033                      unsigned stride = 0u, bool allow_combining = true, bool allow_reorder = true)
3034 {
3035    assert(elem_size_bytes == 4 || elem_size_bytes == 8);
3036    assert((num_components * elem_size_bytes / 4) == dst.size());
3037    assert(!!stride != allow_combining);
3038
3039    Builder bld(ctx->program, ctx->block);
3040    unsigned split_cnt = num_components;
3041
3042    if (elem_size_bytes == 8) {
3043       elem_size_bytes = 4;
3044       num_components *= 2;
3045    }
3046
3047    if (!stride)
3048       stride = elem_size_bytes;
3049
3050    unsigned load_size = 1;
3051    if (allow_combining) {
3052       if ((num_components % 4) == 0)
3053          load_size = 4;
3054       else if ((num_components % 3) == 0 && ctx->program->chip_class != GFX6)
3055          load_size = 3;
3056       else if ((num_components % 2) == 0)
3057          load_size = 2;
3058    }
3059
3060    unsigned num_loads = num_components / load_size;
3061    std::array<Temp, NIR_MAX_VEC_COMPONENTS> elems;
3062
3063    for (unsigned i = 0; i < num_loads; ++i) {
3064       unsigned const_offset = i * stride * load_size + base_const_offset;
3065       elems[i] = emit_single_mubuf_load(ctx, descriptor, voffset, soffset, const_offset, load_size, allow_reorder);
3066    }
3067
3068    create_vec_from_array(ctx, elems.data(), num_loads, RegType::vgpr, split_cnt, dst);
3069 }
3070
3071 std::pair<Temp, unsigned> offset_add_from_nir(isel_context *ctx, const std::pair<Temp, unsigned> &base_offset, nir_src *off_src, unsigned stride = 1u)
3072 {
3073    Builder bld(ctx->program, ctx->block);
3074    Temp offset = base_offset.first;
3075    unsigned const_offset = base_offset.second;
3076
3077    if (!nir_src_is_const(*off_src)) {
3078       Temp indirect_offset_arg = get_ssa_temp(ctx, off_src->ssa);
3079       Temp with_stride;
3080
3081       /* Calculate indirect offset with stride */
3082       if (likely(indirect_offset_arg.regClass() == v1))
3083          with_stride = bld.v_mul_imm(bld.def(v1), indirect_offset_arg, stride);
3084       else if (indirect_offset_arg.regClass() == s1)
3085          with_stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), indirect_offset_arg);
3086       else
3087          unreachable("Unsupported register class of indirect offset");
3088
3089       /* Add to the supplied base offset */
3090       if (offset.id() == 0)
3091          offset = with_stride;
3092       else if (unlikely(offset.regClass() == s1 && with_stride.regClass() == s1))
3093          offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), with_stride, offset);
3094       else if (offset.size() == 1 && with_stride.size() == 1)
3095          offset = bld.vadd32(bld.def(v1), with_stride, offset);
3096       else
3097          unreachable("Unsupported register class of indirect offset");
3098    } else {
3099       unsigned const_offset_arg = nir_src_as_uint(*off_src);
3100       const_offset += const_offset_arg * stride;
3101    }
3102
3103    return std::make_pair(offset, const_offset);
3104 }
3105
3106 std::pair<Temp, unsigned> offset_add(isel_context *ctx, const std::pair<Temp, unsigned> &off1, const std::pair<Temp, unsigned> &off2)
3107 {
3108    Builder bld(ctx->program, ctx->block);
3109    Temp offset;
3110
3111    if (off1.first.id() && off2.first.id()) {
3112       if (unlikely(off1.first.regClass() == s1 && off2.first.regClass() == s1))
3113          offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), off1.first, off2.first);
3114       else if (off1.first.size() == 1 && off2.first.size() == 1)
3115          offset = bld.vadd32(bld.def(v1), off1.first, off2.first);
3116       else
3117          unreachable("Unsupported register class of indirect offset");
3118    } else {
3119       offset = off1.first.id() ? off1.first : off2.first;
3120    }
3121
3122    return std::make_pair(offset, off1.second + off2.second);
3123 }
3124
3125 std::pair<Temp, unsigned> offset_mul(isel_context *ctx, const std::pair<Temp, unsigned> &offs, unsigned multiplier)
3126 {
3127    Builder bld(ctx->program, ctx->block);
3128    unsigned const_offset = offs.second * multiplier;
3129
3130    if (!offs.first.id())
3131       return std::make_pair(offs.first, const_offset);
3132
3133    Temp offset = unlikely(offs.first.regClass() == s1)
3134                  ? bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(multiplier), offs.first)
3135                  : bld.v_mul_imm(bld.def(v1), offs.first, multiplier);
3136
3137    return std::make_pair(offset, const_offset);
3138 }
3139
3140 std::pair<Temp, unsigned> get_intrinsic_io_basic_offset(isel_context *ctx, nir_intrinsic_instr *instr, unsigned base_stride, unsigned component_stride)
3141 {
3142    Builder bld(ctx->program, ctx->block);
3143
3144    /* base is the driver_location, which is already multiplied by 4, so is in dwords */
3145    unsigned const_offset = nir_intrinsic_base(instr) * base_stride;
3146    /* component is in bytes */
3147    const_offset += nir_intrinsic_component(instr) * component_stride;
3148
3149    /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
3150    nir_src *off_src = nir_get_io_offset_src(instr);
3151    return offset_add_from_nir(ctx, std::make_pair(Temp(), const_offset), off_src, 4u * base_stride);
3152 }
3153
3154 std::pair<Temp, unsigned> get_intrinsic_io_basic_offset(isel_context *ctx, nir_intrinsic_instr *instr, unsigned stride = 1u)
3155 {
3156    return get_intrinsic_io_basic_offset(ctx, instr, stride, stride);
3157 }
3158
3159 Temp get_tess_rel_patch_id(isel_context *ctx)
3160 {
3161    Builder bld(ctx->program, ctx->block);
3162
3163    switch (ctx->shader->info.stage) {
3164    case MESA_SHADER_TESS_CTRL:
3165       return bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0xffu),
3166                       get_arg(ctx, ctx->args->ac.tcs_rel_ids));
3167    case MESA_SHADER_TESS_EVAL:
3168       return get_arg(ctx, ctx->args->tes_rel_patch_id);
3169    default:
3170       unreachable("Unsupported stage in get_tess_rel_patch_id");
3171    }
3172 }
3173
3174 std::pair<Temp, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context *ctx, nir_intrinsic_instr *instr)
3175 {
3176    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
3177    Builder bld(ctx->program, ctx->block);
3178
3179    uint32_t tcs_in_patch_stride = ctx->args->options->key.tcs.input_vertices * ctx->tcs_num_inputs * 4;
3180    uint32_t tcs_in_vertex_stride = ctx->tcs_num_inputs * 4;
3181
3182    std::pair<Temp, unsigned> offs = get_intrinsic_io_basic_offset(ctx, instr);
3183
3184    nir_src *vertex_index_src = nir_get_io_vertex_index_src(instr);
3185    offs = offset_add_from_nir(ctx, offs, vertex_index_src, tcs_in_vertex_stride);
3186
3187    Temp rel_patch_id = get_tess_rel_patch_id(ctx);
3188    Temp tcs_in_current_patch_offset = bld.v_mul24_imm(bld.def(v1), rel_patch_id, tcs_in_patch_stride);
3189    offs = offset_add(ctx, offs, std::make_pair(tcs_in_current_patch_offset, 0));
3190
3191    return offset_mul(ctx, offs, 4u);
3192 }
3193
3194 std::pair<Temp, unsigned> get_tcs_output_lds_offset(isel_context *ctx, nir_intrinsic_instr *instr = nullptr, bool per_vertex = false)
3195 {
3196    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
3197    Builder bld(ctx->program, ctx->block);
3198
3199    uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * ctx->tcs_num_inputs * 16;
3200    uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
3201    uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->args->shader_info->tcs.patch_outputs_written);
3202    uint32_t output_vertex_size = num_tcs_outputs * 16;
3203    uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
3204    uint32_t output_patch_stride = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
3205
3206    std::pair<Temp, unsigned> offs = instr
3207                                     ? get_intrinsic_io_basic_offset(ctx, instr, 4u)
3208                                     : std::make_pair(Temp(), 0u);
3209
3210    Temp rel_patch_id = get_tess_rel_patch_id(ctx);
3211    Temp patch_off = bld.v_mul24_imm(bld.def(v1), rel_patch_id, output_patch_stride);
3212
3213    if (per_vertex) {
3214       assert(instr);
3215
3216       nir_src *vertex_index_src = nir_get_io_vertex_index_src(instr);
3217       offs = offset_add_from_nir(ctx, offs, vertex_index_src, output_vertex_size);
3218
3219       uint32_t output_patch0_offset = (input_patch_size * ctx->tcs_num_patches);
3220       offs = offset_add(ctx, offs, std::make_pair(patch_off, output_patch0_offset));
3221    } else {
3222       uint32_t output_patch0_patch_data_offset = (input_patch_size * ctx->tcs_num_patches + pervertex_output_patch_size);
3223       offs = offset_add(ctx, offs, std::make_pair(patch_off, output_patch0_patch_data_offset));
3224    }
3225
3226    return offs;
3227 }
3228
3229 std::pair<Temp, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context *ctx, nir_intrinsic_instr *instr)
3230 {
3231    Builder bld(ctx->program, ctx->block);
3232
3233    unsigned vertices_per_patch = ctx->shader->info.tess.tcs_vertices_out;
3234    unsigned attr_stride = vertices_per_patch * ctx->tcs_num_patches;
3235
3236    std::pair<Temp, unsigned> offs = get_intrinsic_io_basic_offset(ctx, instr, attr_stride * 4u, 4u);
3237
3238    Temp rel_patch_id = get_tess_rel_patch_id(ctx);
3239    Temp patch_off = bld.v_mul24_imm(bld.def(v1), rel_patch_id, vertices_per_patch * 16u);
3240    offs = offset_add(ctx, offs, std::make_pair(patch_off, 0u));
3241
3242    nir_src *vertex_index_src = nir_get_io_vertex_index_src(instr);
3243    offs = offset_add_from_nir(ctx, offs, vertex_index_src, 16u);
3244
3245    return offs;
3246 }
3247
3248 std::pair<Temp, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context *ctx, nir_intrinsic_instr *instr = nullptr, unsigned const_base_offset = 0u)
3249 {
3250    Builder bld(ctx->program, ctx->block);
3251
3252    unsigned num_tcs_outputs = ctx->shader->info.stage == MESA_SHADER_TESS_CTRL
3253                               ? util_last_bit64(ctx->args->shader_info->tcs.outputs_written)
3254                               : ctx->args->options->key.tes.tcs_num_outputs;
3255
3256    unsigned output_vertex_size = num_tcs_outputs * 16;
3257    unsigned per_vertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
3258    unsigned per_patch_data_offset = per_vertex_output_patch_size * ctx->tcs_num_patches;
3259    unsigned attr_stride = ctx->tcs_num_patches;
3260
3261    std::pair<Temp, unsigned> offs = instr
3262                                     ? get_intrinsic_io_basic_offset(ctx, instr, attr_stride * 4u, 4u)
3263                                     : std::make_pair(Temp(), 0u);
3264
3265    if (const_base_offset)
3266       offs.second += const_base_offset * attr_stride;
3267
3268    Temp rel_patch_id = get_tess_rel_patch_id(ctx);
3269    Temp patch_off = bld.v_mul_imm(bld.def(v1), rel_patch_id, 16u);
3270    offs = offset_add(ctx, offs, std::make_pair(patch_off, per_patch_data_offset));
3271
3272    return offs;
3273 }
3274
3275 void visit_store_ls_or_es_output(isel_context *ctx, nir_intrinsic_instr *instr)
3276 {
3277    Builder bld(ctx->program, ctx->block);
3278
3279    std::pair<Temp, unsigned> offs = get_intrinsic_io_basic_offset(ctx, instr, 4u);
3280    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
3281    unsigned write_mask = nir_intrinsic_write_mask(instr);
3282    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8u;
3283
3284    if (ctx->stage == vertex_es || ctx->stage == tess_eval_es) {
3285       /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
3286       Temp esgs_ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_ESGS_VS * 16u));
3287       Temp es2gs_offset = get_arg(ctx, ctx->args->es2gs_offset);
3288       store_vmem_mubuf(ctx, src, esgs_ring, offs.first, es2gs_offset, offs.second, elem_size_bytes, write_mask, false, true, true);
3289    } else {
3290       Temp lds_base;
3291
3292       if (ctx->stage == vertex_geometry_gs || ctx->stage == tess_eval_geometry_gs) {
3293          /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
3294          unsigned itemsize = ctx->stage == vertex_geometry_gs
3295                              ? ctx->program->info->vs.es_info.esgs_itemsize
3296                              : ctx->program->info->tes.es_info.esgs_itemsize;
3297          Temp thread_id = emit_mbcnt(ctx, bld.def(v1));
3298          Temp wave_idx = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), get_arg(ctx, ctx->args->merged_wave_info), Operand(4u << 16 | 24));
3299          Temp vertex_idx = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), thread_id,
3300                                bld.v_mul24_imm(bld.def(v1), as_vgpr(ctx, wave_idx), ctx->program->wave_size));
3301          lds_base = bld.v_mul24_imm(bld.def(v1), vertex_idx, itemsize);
3302       } else if (ctx->stage == vertex_ls || ctx->stage == vertex_tess_control_hs) {
3303          /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
3304           * GFX9+: LS is merged into HS, but still uses the same LDS layout.
3305           */
3306          unsigned num_tcs_inputs = util_last_bit64(ctx->args->shader_info->vs.ls_outputs_written);
3307          Temp vertex_idx = get_arg(ctx, ctx->args->rel_auto_id);
3308          lds_base = bld.v_mul_imm(bld.def(v1), vertex_idx, num_tcs_inputs * 16u);
3309       } else {
3310          unreachable("Invalid LS or ES stage");
3311       }
3312
3313       offs = offset_add(ctx, offs, std::make_pair(lds_base, 0u));
3314       unsigned lds_align = calculate_lds_alignment(ctx, offs.second);
3315       store_lds(ctx, elem_size_bytes, src, write_mask, offs.first, offs.second, lds_align);
3316    }
3317 }
3318
3319 void visit_store_tcs_output(isel_context *ctx, nir_intrinsic_instr *instr, bool per_vertex)
3320 {
3321    assert(ctx->stage == tess_control_hs || ctx->stage == vertex_tess_control_hs);
3322    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
3323
3324    Builder bld(ctx->program, ctx->block);
3325
3326    Temp store_val = get_ssa_temp(ctx, instr->src[0].ssa);
3327    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
3328    unsigned write_mask = nir_intrinsic_write_mask(instr);
3329
3330    /* TODO: Only write to VMEM if the output is per-vertex or it's per-patch non tess factor */
3331    bool write_to_vmem = true;
3332    /* TODO: Only write to LDS if the output is read by the shader, or it's per-patch tess factor */
3333    bool write_to_lds = true;
3334
3335    if (write_to_vmem) {
3336       std::pair<Temp, unsigned> vmem_offs = per_vertex
3337                                             ? get_tcs_per_vertex_output_vmem_offset(ctx, instr)
3338                                             : get_tcs_per_patch_output_vmem_offset(ctx, instr);
3339
3340       Temp hs_ring_tess_offchip = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_HS_TESS_OFFCHIP * 16u));
3341       Temp oc_lds = get_arg(ctx, ctx->args->oc_lds);
3342       store_vmem_mubuf(ctx, store_val, hs_ring_tess_offchip, vmem_offs.first, oc_lds, vmem_offs.second, elem_size_bytes, write_mask, false, false);
3343    }
3344
3345    if (write_to_lds) {
3346       std::pair<Temp, unsigned> lds_offs = get_tcs_output_lds_offset(ctx, instr, per_vertex);
3347       unsigned lds_align = calculate_lds_alignment(ctx, lds_offs.second);
3348       store_lds(ctx, elem_size_bytes, store_val, write_mask, lds_offs.first, lds_offs.second, lds_align);
3349    }
3350 }
3351
3352 void visit_load_tcs_output(isel_context *ctx, nir_intrinsic_instr *instr, bool per_vertex)
3353 {
3354    assert(ctx->stage == tess_control_hs || ctx->stage == vertex_tess_control_hs);
3355    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
3356
3357    Builder bld(ctx->program, ctx->block);
3358
3359    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3360    std::pair<Temp, unsigned> lds_offs = get_tcs_output_lds_offset(ctx, instr, per_vertex);
3361    unsigned lds_align = calculate_lds_alignment(ctx, lds_offs.second);
3362    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
3363
3364    load_lds(ctx, elem_size_bytes, dst, lds_offs.first, lds_offs.second, lds_align);
3365 }
3366
3367 void visit_store_output(isel_context *ctx, nir_intrinsic_instr *instr)
3368 {
3369    if (ctx->stage == vertex_vs ||
3370        ctx->stage == tess_eval_vs ||
3371        ctx->stage == fragment_fs ||
3372        ctx->shader->info.stage == MESA_SHADER_GEOMETRY) {
3373       unsigned write_mask = nir_intrinsic_write_mask(instr);
3374       unsigned component = nir_intrinsic_component(instr);
3375       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
3376       unsigned idx = nir_intrinsic_base(instr) + component;
3377
3378       nir_instr *off_instr = instr->src[1].ssa->parent_instr;
3379       if (off_instr->type != nir_instr_type_load_const) {
3380          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
3381          nir_print_instr(off_instr, stderr);
3382          fprintf(stderr, "\n");
3383       }
3384       idx += nir_instr_as_load_const(off_instr)->value[0].u32 * 4u;
3385
3386       if (instr->src[0].ssa->bit_size == 64)
3387          write_mask = widen_mask(write_mask, 2);
3388
3389       for (unsigned i = 0; i < 8; ++i) {
3390          if (write_mask & (1 << i)) {
3391             ctx->outputs.mask[idx / 4u] |= 1 << (idx % 4u);
3392             ctx->outputs.outputs[idx / 4u][idx % 4u] = emit_extract_vector(ctx, src, i, v1);
3393          }
3394          idx++;
3395       }
3396    } else if (ctx->stage == vertex_es ||
3397               ctx->stage == vertex_ls ||
3398               ctx->stage == tess_eval_es ||
3399               (ctx->stage == vertex_tess_control_hs && ctx->shader->info.stage == MESA_SHADER_VERTEX) ||
3400               (ctx->stage == vertex_geometry_gs && ctx->shader->info.stage == MESA_SHADER_VERTEX) ||
3401               (ctx->stage == tess_eval_geometry_gs && ctx->shader->info.stage == MESA_SHADER_TESS_EVAL)) {
3402       visit_store_ls_or_es_output(ctx, instr);
3403    } else if (ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) {
3404       visit_store_tcs_output(ctx, instr, false);
3405    } else {
3406       unreachable("Shader stage not implemented");
3407    }
3408 }
3409
3410 void visit_load_output(isel_context *ctx, nir_intrinsic_instr *instr)
3411 {
3412    visit_load_tcs_output(ctx, instr, false);
3413 }
3414
3415 void emit_interp_instr(isel_context *ctx, unsigned idx, unsigned component, Temp src, Temp dst, Temp prim_mask)
3416 {
3417    Temp coord1 = emit_extract_vector(ctx, src, 0, v1);
3418    Temp coord2 = emit_extract_vector(ctx, src, 1, v1);
3419
3420    Builder bld(ctx->program, ctx->block);
3421    Temp tmp = bld.vintrp(aco_opcode::v_interp_p1_f32, bld.def(v1), coord1, bld.m0(prim_mask), idx, component);
3422    bld.vintrp(aco_opcode::v_interp_p2_f32, Definition(dst), coord2, bld.m0(prim_mask), tmp, idx, component);
3423 }
3424
3425 void emit_load_frag_coord(isel_context *ctx, Temp dst, unsigned num_components)
3426 {
3427    aco_ptr<Pseudo_instruction> vec(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1));
3428    for (unsigned i = 0; i < num_components; i++)
3429       vec->operands[i] = Operand(get_arg(ctx, ctx->args->ac.frag_pos[i]));
3430    if (G_0286CC_POS_W_FLOAT_ENA(ctx->program->config->spi_ps_input_ena)) {
3431       assert(num_components == 4);
3432       Builder bld(ctx->program, ctx->block);
3433       vec->operands[3] = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), get_arg(ctx, ctx->args->ac.frag_pos[3]));
3434    }
3435
3436    for (Operand& op : vec->operands)
3437       op = op.isUndefined() ? Operand(0u) : op;
3438
3439    vec->definitions[0] = Definition(dst);
3440    ctx->block->instructions.emplace_back(std::move(vec));
3441    emit_split_vector(ctx, dst, num_components);
3442    return;
3443 }
3444
3445 void visit_load_interpolated_input(isel_context *ctx, nir_intrinsic_instr *instr)
3446 {
3447    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3448    Temp coords = get_ssa_temp(ctx, instr->src[0].ssa);
3449    unsigned idx = nir_intrinsic_base(instr);
3450    unsigned component = nir_intrinsic_component(instr);
3451    Temp prim_mask = get_arg(ctx, ctx->args->ac.prim_mask);
3452
3453    nir_const_value* offset = nir_src_as_const_value(instr->src[1]);
3454    if (offset) {
3455       assert(offset->u32 == 0);
3456    } else {
3457       /* the lower 15bit of the prim_mask contain the offset into LDS
3458        * while the upper bits contain the number of prims */
3459       Temp offset_src = get_ssa_temp(ctx, instr->src[1].ssa);
3460       assert(offset_src.regClass() == s1 && "TODO: divergent offsets...");
3461       Builder bld(ctx->program, ctx->block);
3462       Temp stride = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), prim_mask, Operand(16u));
3463       stride = bld.sop1(aco_opcode::s_bcnt1_i32_b32, bld.def(s1), bld.def(s1, scc), stride);
3464       stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, Operand(48u));
3465       offset_src = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, offset_src);
3466       prim_mask = bld.sop2(aco_opcode::s_add_i32, bld.def(s1, m0), bld.def(s1, scc), offset_src, prim_mask);
3467    }
3468
3469    if (instr->dest.ssa.num_components == 1) {
3470       emit_interp_instr(ctx, idx, component, coords, dst, prim_mask);
3471    } else {
3472       aco_ptr<Pseudo_instruction> vec(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.ssa.num_components, 1));
3473       for (unsigned i = 0; i < instr->dest.ssa.num_components; i++)
3474       {
3475          Temp tmp = {ctx->program->allocateId(), v1};
3476          emit_interp_instr(ctx, idx, component+i, coords, tmp, prim_mask);
3477          vec->operands[i] = Operand(tmp);
3478       }
3479       vec->definitions[0] = Definition(dst);
3480       ctx->block->instructions.emplace_back(std::move(vec));
3481    }
3482 }
3483
3484 bool check_vertex_fetch_size(isel_context *ctx, const ac_data_format_info *vtx_info,
3485                              unsigned offset, unsigned stride, unsigned channels)
3486 {
3487    unsigned vertex_byte_size = vtx_info->chan_byte_size * channels;
3488    if (vtx_info->chan_byte_size != 4 && channels == 3)
3489       return false;
3490    return (ctx->options->chip_class != GFX6 && ctx->options->chip_class != GFX10) ||
3491           (offset % vertex_byte_size == 0 && stride % vertex_byte_size == 0);
3492 }
3493
3494 uint8_t get_fetch_data_format(isel_context *ctx, const ac_data_format_info *vtx_info,
3495                               unsigned offset, unsigned stride, unsigned *channels)
3496 {
3497    if (!vtx_info->chan_byte_size) {
3498       *channels = vtx_info->num_channels;
3499       return vtx_info->chan_format;
3500    }
3501
3502    unsigned num_channels = *channels;
3503    if (!check_vertex_fetch_size(ctx, vtx_info, offset, stride, *channels)) {
3504       unsigned new_channels = num_channels + 1;
3505       /* first, assume more loads is worse and try using a larger data format */
3506       while (new_channels <= 4 && !check_vertex_fetch_size(ctx, vtx_info, offset, stride, new_channels)) {
3507          new_channels++;
3508          /* don't make the attribute potentially out-of-bounds */
3509          if (offset + new_channels * vtx_info->chan_byte_size > stride)
3510             new_channels = 5;
3511       }
3512
3513       if (new_channels == 5) {
3514          /* then try decreasing load size (at the cost of more loads) */
3515          new_channels = *channels;
3516          while (new_channels > 1 && !check_vertex_fetch_size(ctx, vtx_info, offset, stride, new_channels))
3517             new_channels--;
3518       }
3519
3520       if (new_channels < *channels)
3521          *channels = new_channels;
3522       num_channels = new_channels;
3523    }
3524
3525    switch (vtx_info->chan_format) {
3526    case V_008F0C_BUF_DATA_FORMAT_8:
3527       return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8, V_008F0C_BUF_DATA_FORMAT_8_8,
3528                          V_008F0C_BUF_DATA_FORMAT_INVALID, V_008F0C_BUF_DATA_FORMAT_8_8_8_8}[num_channels - 1];
3529    case V_008F0C_BUF_DATA_FORMAT_16:
3530       return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16, V_008F0C_BUF_DATA_FORMAT_16_16,
3531                          V_008F0C_BUF_DATA_FORMAT_INVALID, V_008F0C_BUF_DATA_FORMAT_16_16_16_16}[num_channels - 1];
3532    case V_008F0C_BUF_DATA_FORMAT_32:
3533       return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32, V_008F0C_BUF_DATA_FORMAT_32_32,
3534                          V_008F0C_BUF_DATA_FORMAT_32_32_32, V_008F0C_BUF_DATA_FORMAT_32_32_32_32}[num_channels - 1];
3535    }
3536    unreachable("shouldn't reach here");
3537    return V_008F0C_BUF_DATA_FORMAT_INVALID;
3538 }
3539
3540 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
3541  * so we may need to fix it up. */
3542 Temp adjust_vertex_fetch_alpha(isel_context *ctx, unsigned adjustment, Temp alpha)
3543 {
3544    Builder bld(ctx->program, ctx->block);
3545
3546    if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
3547       alpha = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), alpha);
3548
3549    /* For the integer-like cases, do a natural sign extension.
3550     *
3551     * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
3552     * and happen to contain 0, 1, 2, 3 as the two LSBs of the
3553     * exponent.
3554     */
3555    alpha = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(adjustment == RADV_ALPHA_ADJUST_SNORM ? 7u : 30u), alpha);
3556    alpha = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(30u), alpha);
3557
3558    /* Convert back to the right type. */
3559    if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
3560       alpha = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), alpha);
3561       Temp clamp = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0xbf800000u), alpha);
3562       alpha = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xbf800000u), alpha, clamp);
3563    } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
3564       alpha = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), alpha);
3565    }
3566
3567    return alpha;
3568 }
3569
3570 void visit_load_input(isel_context *ctx, nir_intrinsic_instr *instr)
3571 {
3572    Builder bld(ctx->program, ctx->block);
3573    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3574    if (ctx->shader->info.stage == MESA_SHADER_VERTEX) {
3575
3576       nir_instr *off_instr = instr->src[0].ssa->parent_instr;
3577       if (off_instr->type != nir_instr_type_load_const) {
3578          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
3579          nir_print_instr(off_instr, stderr);
3580          fprintf(stderr, "\n");
3581       }
3582       uint32_t offset = nir_instr_as_load_const(off_instr)->value[0].u32;
3583
3584       Temp vertex_buffers = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->vertex_buffers));
3585
3586       unsigned location = nir_intrinsic_base(instr) / 4 - VERT_ATTRIB_GENERIC0 + offset;
3587       unsigned component = nir_intrinsic_component(instr);
3588       unsigned attrib_binding = ctx->options->key.vs.vertex_attribute_bindings[location];
3589       uint32_t attrib_offset = ctx->options->key.vs.vertex_attribute_offsets[location];
3590       uint32_t attrib_stride = ctx->options->key.vs.vertex_attribute_strides[location];
3591       unsigned attrib_format = ctx->options->key.vs.vertex_attribute_formats[location];
3592
3593       unsigned dfmt = attrib_format & 0xf;
3594       unsigned nfmt = (attrib_format >> 4) & 0x7;
3595       const struct ac_data_format_info *vtx_info = ac_get_data_format_info(dfmt);
3596
3597       unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa) << component;
3598       unsigned num_channels = MIN2(util_last_bit(mask), vtx_info->num_channels);
3599       unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> (location * 2)) & 3;
3600       bool post_shuffle = ctx->options->key.vs.post_shuffle & (1 << location);
3601       if (post_shuffle)
3602          num_channels = MAX2(num_channels, 3);
3603
3604       Operand off = bld.copy(bld.def(s1), Operand(attrib_binding * 16u));
3605       Temp list = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), vertex_buffers, off);
3606
3607       Temp index;
3608       if (ctx->options->key.vs.instance_rate_inputs & (1u << location)) {
3609          uint32_t divisor = ctx->options->key.vs.instance_rate_divisors[location];
3610          Temp start_instance = get_arg(ctx, ctx->args->ac.start_instance);
3611          if (divisor) {
3612             Temp instance_id = get_arg(ctx, ctx->args->ac.instance_id);
3613             if (divisor != 1) {
3614                Temp divided = bld.tmp(v1);
3615                emit_v_div_u32(ctx, divided, as_vgpr(ctx, instance_id), divisor);
3616                index = bld.vadd32(bld.def(v1), start_instance, divided);
3617             } else {
3618                index = bld.vadd32(bld.def(v1), start_instance, instance_id);
3619             }
3620          } else {
3621             index = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), start_instance);
3622          }
3623       } else {
3624          index = bld.vadd32(bld.def(v1),
3625                             get_arg(ctx, ctx->args->ac.base_vertex),
3626                             get_arg(ctx, ctx->args->ac.vertex_id));
3627       }
3628
3629       Temp channels[num_channels];
3630       unsigned channel_start = 0;
3631       bool direct_fetch = false;
3632
3633       /* skip unused channels at the start */
3634       if (vtx_info->chan_byte_size && !post_shuffle) {
3635          channel_start = ffs(mask) - 1;
3636          for (unsigned i = 0; i < channel_start; i++)
3637             channels[i] = Temp(0, s1);
3638       } else if (vtx_info->chan_byte_size && post_shuffle && !(mask & 0x8)) {
3639          num_channels = 3 - (ffs(mask) - 1);
3640       }
3641
3642       /* load channels */
3643       while (channel_start < num_channels) {
3644          unsigned fetch_size = num_channels - channel_start;
3645          unsigned fetch_offset = attrib_offset + channel_start * vtx_info->chan_byte_size;
3646          bool expanded = false;
3647
3648          /* use MUBUF when possible to avoid possible alignment issues */
3649          /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
3650          bool use_mubuf = (nfmt == V_008F0C_BUF_NUM_FORMAT_FLOAT ||
3651                            nfmt == V_008F0C_BUF_NUM_FORMAT_UINT ||
3652                            nfmt == V_008F0C_BUF_NUM_FORMAT_SINT) &&
3653                           vtx_info->chan_byte_size == 4;
3654          unsigned fetch_dfmt = V_008F0C_BUF_DATA_FORMAT_INVALID;
3655          if (!use_mubuf) {
3656             fetch_dfmt = get_fetch_data_format(ctx, vtx_info, fetch_offset, attrib_stride, &fetch_size);
3657          } else {
3658             if (fetch_size == 3 && ctx->options->chip_class == GFX6) {
3659                /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
3660                fetch_size = 4;
3661                expanded = true;
3662             }
3663          }
3664
3665          Temp fetch_index = index;
3666          if (attrib_stride != 0 && fetch_offset > attrib_stride) {
3667             fetch_index = bld.vadd32(bld.def(v1), Operand(fetch_offset / attrib_stride), fetch_index);
3668             fetch_offset = fetch_offset % attrib_stride;
3669          }
3670
3671          Operand soffset(0u);
3672          if (fetch_offset >= 4096) {
3673             soffset = bld.copy(bld.def(s1), Operand(fetch_offset / 4096 * 4096));
3674             fetch_offset %= 4096;
3675          }
3676
3677          aco_opcode opcode;
3678          switch (fetch_size) {
3679          case 1:
3680             opcode = use_mubuf ? aco_opcode::buffer_load_dword : aco_opcode::tbuffer_load_format_x;
3681             break;
3682          case 2:
3683             opcode = use_mubuf ? aco_opcode::buffer_load_dwordx2 : aco_opcode::tbuffer_load_format_xy;
3684             break;
3685          case 3:
3686             assert(ctx->options->chip_class >= GFX7 ||
3687                    (!use_mubuf && ctx->options->chip_class == GFX6));
3688             opcode = use_mubuf ? aco_opcode::buffer_load_dwordx3 : aco_opcode::tbuffer_load_format_xyz;
3689             break;
3690          case 4:
3691             opcode = use_mubuf ? aco_opcode::buffer_load_dwordx4 : aco_opcode::tbuffer_load_format_xyzw;
3692             break;
3693          default:
3694             unreachable("Unimplemented load_input vector size");
3695          }
3696
3697          Temp fetch_dst;
3698          if (channel_start == 0 && fetch_size == dst.size() && !post_shuffle &&
3699              !expanded && (alpha_adjust == RADV_ALPHA_ADJUST_NONE ||
3700                            num_channels <= 3)) {
3701             direct_fetch = true;
3702             fetch_dst = dst;
3703          } else {
3704             fetch_dst = bld.tmp(RegType::vgpr, fetch_size);
3705          }
3706
3707          if (use_mubuf) {
3708             Instruction *mubuf = bld.mubuf(opcode,
3709                                            Definition(fetch_dst), list, fetch_index, soffset,
3710                                            fetch_offset, false, true).instr;
3711             static_cast<MUBUF_instruction*>(mubuf)->can_reorder = true;
3712          } else {
3713             Instruction *mtbuf = bld.mtbuf(opcode,
3714                                            Definition(fetch_dst), list, fetch_index, soffset,
3715                                            fetch_dfmt, nfmt, fetch_offset, false, true).instr;
3716             static_cast<MTBUF_instruction*>(mtbuf)->can_reorder = true;
3717          }
3718
3719          emit_split_vector(ctx, fetch_dst, fetch_dst.size());
3720
3721          if (fetch_size == 1) {
3722             channels[channel_start] = fetch_dst;
3723          } else {
3724             for (unsigned i = 0; i < MIN2(fetch_size, num_channels - channel_start); i++)
3725                channels[channel_start + i] = emit_extract_vector(ctx, fetch_dst, i, v1);
3726          }
3727
3728          channel_start += fetch_size;
3729       }
3730
3731       if (!direct_fetch) {
3732          bool is_float = nfmt != V_008F0C_BUF_NUM_FORMAT_UINT &&
3733                          nfmt != V_008F0C_BUF_NUM_FORMAT_SINT;
3734
3735          static const unsigned swizzle_normal[4] = {0, 1, 2, 3};
3736          static const unsigned swizzle_post_shuffle[4] = {2, 1, 0, 3};
3737          const unsigned *swizzle = post_shuffle ? swizzle_post_shuffle : swizzle_normal;
3738
3739          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
3740          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
3741          unsigned num_temp = 0;
3742          for (unsigned i = 0; i < dst.size(); i++) {
3743             unsigned idx = i + component;
3744             if (swizzle[idx] < num_channels && channels[swizzle[idx]].id()) {
3745                Temp channel = channels[swizzle[idx]];
3746                if (idx == 3 && alpha_adjust != RADV_ALPHA_ADJUST_NONE)
3747                   channel = adjust_vertex_fetch_alpha(ctx, alpha_adjust, channel);
3748                vec->operands[i] = Operand(channel);
3749
3750                num_temp++;
3751                elems[i] = channel;
3752             } else if (is_float && idx == 3) {
3753                vec->operands[i] = Operand(0x3f800000u);
3754             } else if (!is_float && idx == 3) {
3755                vec->operands[i] = Operand(1u);
3756             } else {
3757                vec->operands[i] = Operand(0u);
3758             }
3759          }
3760          vec->definitions[0] = Definition(dst);
3761          ctx->block->instructions.emplace_back(std::move(vec));
3762          emit_split_vector(ctx, dst, dst.size());
3763
3764          if (num_temp == dst.size())
3765             ctx->allocated_vec.emplace(dst.id(), elems);
3766       }
3767    } else if (ctx->shader->info.stage == MESA_SHADER_FRAGMENT) {
3768       unsigned offset_idx = instr->intrinsic == nir_intrinsic_load_input ? 0 : 1;
3769       nir_instr *off_instr = instr->src[offset_idx].ssa->parent_instr;
3770       if (off_instr->type != nir_instr_type_load_const ||
3771           nir_instr_as_load_const(off_instr)->value[0].u32 != 0) {
3772          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
3773          nir_print_instr(off_instr, stderr);
3774          fprintf(stderr, "\n");
3775       }
3776
3777       Temp prim_mask = get_arg(ctx, ctx->args->ac.prim_mask);
3778       nir_const_value* offset = nir_src_as_const_value(instr->src[offset_idx]);
3779       if (offset) {
3780          assert(offset->u32 == 0);
3781       } else {
3782          /* the lower 15bit of the prim_mask contain the offset into LDS
3783           * while the upper bits contain the number of prims */
3784          Temp offset_src = get_ssa_temp(ctx, instr->src[offset_idx].ssa);
3785          assert(offset_src.regClass() == s1 && "TODO: divergent offsets...");
3786          Builder bld(ctx->program, ctx->block);
3787          Temp stride = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), prim_mask, Operand(16u));
3788          stride = bld.sop1(aco_opcode::s_bcnt1_i32_b32, bld.def(s1), bld.def(s1, scc), stride);
3789          stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, Operand(48u));
3790          offset_src = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, offset_src);
3791          prim_mask = bld.sop2(aco_opcode::s_add_i32, bld.def(s1, m0), bld.def(s1, scc), offset_src, prim_mask);
3792       }
3793
3794       unsigned idx = nir_intrinsic_base(instr);
3795       unsigned component = nir_intrinsic_component(instr);
3796       unsigned vertex_id = 2; /* P0 */
3797
3798       if (instr->intrinsic == nir_intrinsic_load_input_vertex) {
3799          nir_const_value* src0 = nir_src_as_const_value(instr->src[0]);
3800          switch (src0->u32) {
3801          case 0:
3802             vertex_id = 2; /* P0 */
3803             break;
3804          case 1:
3805             vertex_id = 0; /* P10 */
3806             break;
3807          case 2:
3808             vertex_id = 1; /* P20 */
3809             break;
3810          default:
3811             unreachable("invalid vertex index");
3812          }
3813       }
3814
3815       if (dst.size() == 1) {
3816          bld.vintrp(aco_opcode::v_interp_mov_f32, Definition(dst), Operand(vertex_id), bld.m0(prim_mask), idx, component);
3817       } else {
3818          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
3819          for (unsigned i = 0; i < dst.size(); i++)
3820             vec->operands[i] = bld.vintrp(aco_opcode::v_interp_mov_f32, bld.def(v1), Operand(vertex_id), bld.m0(prim_mask), idx, component + i);
3821          vec->definitions[0] = Definition(dst);
3822          bld.insert(std::move(vec));
3823       }
3824
3825    } else if (ctx->shader->info.stage == MESA_SHADER_TESS_EVAL) {
3826       Temp ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_HS_TESS_OFFCHIP * 16u));
3827       Temp soffset = get_arg(ctx, ctx->args->oc_lds);
3828       std::pair<Temp, unsigned> offs = get_tcs_per_patch_output_vmem_offset(ctx, instr);
3829       unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8u;
3830
3831       load_vmem_mubuf(ctx, dst, ring, offs.first, soffset, offs.second, elem_size_bytes, instr->dest.ssa.num_components);
3832    } else {
3833       unreachable("Shader stage not implemented");
3834    }
3835 }
3836
3837 std::pair<Temp, unsigned> get_gs_per_vertex_input_offset(isel_context *ctx, nir_intrinsic_instr *instr, unsigned base_stride = 1u)
3838 {
3839    assert(ctx->shader->info.stage == MESA_SHADER_GEOMETRY);
3840
3841    Builder bld(ctx->program, ctx->block);
3842    nir_src *vertex_src = nir_get_io_vertex_index_src(instr);
3843    Temp vertex_offset;
3844
3845    if (!nir_src_is_const(*vertex_src)) {
3846       /* better code could be created, but this case probably doesn't happen
3847        * much in practice */
3848       Temp indirect_vertex = as_vgpr(ctx, get_ssa_temp(ctx, vertex_src->ssa));
3849       for (unsigned i = 0; i < ctx->shader->info.gs.vertices_in; i++) {
3850          Temp elem;
3851
3852          if (ctx->stage == vertex_geometry_gs || ctx->stage == tess_eval_geometry_gs) {
3853             elem = get_arg(ctx, ctx->args->gs_vtx_offset[i / 2u * 2u]);
3854             if (i % 2u)
3855                elem = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(16u), elem);
3856          } else {
3857             elem = get_arg(ctx, ctx->args->gs_vtx_offset[i]);
3858          }
3859
3860          if (vertex_offset.id()) {
3861             Temp cond = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.hint_vcc(bld.def(bld.lm)),
3862                                  Operand(i), indirect_vertex);
3863             vertex_offset = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), vertex_offset, elem, cond);
3864          } else {
3865             vertex_offset = elem;
3866          }
3867       }
3868
3869       if (ctx->stage == vertex_geometry_gs || ctx->stage == tess_eval_geometry_gs)
3870          vertex_offset = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0xffffu), vertex_offset);
3871    } else {
3872       unsigned vertex = nir_src_as_uint(*vertex_src);
3873       if (ctx->stage == vertex_geometry_gs || ctx->stage == tess_eval_geometry_gs)
3874          vertex_offset = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1),
3875                                   get_arg(ctx, ctx->args->gs_vtx_offset[vertex / 2u * 2u]),
3876                                   Operand((vertex % 2u) * 16u), Operand(16u));
3877       else
3878          vertex_offset = get_arg(ctx, ctx->args->gs_vtx_offset[vertex]);
3879    }
3880
3881    std::pair<Temp, unsigned> offs = get_intrinsic_io_basic_offset(ctx, instr, base_stride);
3882    offs = offset_add(ctx, offs, std::make_pair(vertex_offset, 0u));
3883    return offset_mul(ctx, offs, 4u);
3884 }
3885
3886 void visit_load_gs_per_vertex_input(isel_context *ctx, nir_intrinsic_instr *instr)
3887 {
3888    assert(ctx->shader->info.stage == MESA_SHADER_GEOMETRY);
3889
3890    Builder bld(ctx->program, ctx->block);
3891    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3892    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
3893
3894    if (ctx->stage == geometry_gs) {
3895       std::pair<Temp, unsigned> offs = get_gs_per_vertex_input_offset(ctx, instr, ctx->program->wave_size);
3896       Temp ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_ESGS_GS * 16u));
3897       load_vmem_mubuf(ctx, dst, ring, offs.first, Temp(), offs.second, elem_size_bytes, instr->dest.ssa.num_components, 4u * ctx->program->wave_size, false, true);
3898    } else if (ctx->stage == vertex_geometry_gs || ctx->stage == tess_eval_geometry_gs) {
3899       std::pair<Temp, unsigned> offs = get_gs_per_vertex_input_offset(ctx, instr);
3900       unsigned lds_align = calculate_lds_alignment(ctx, offs.second);
3901       load_lds(ctx, elem_size_bytes, dst, offs.first, offs.second, lds_align);
3902    } else {
3903       unreachable("Unsupported GS stage.");
3904    }
3905 }
3906
3907 void visit_load_tcs_per_vertex_input(isel_context *ctx, nir_intrinsic_instr *instr)
3908 {
3909    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
3910
3911    Builder bld(ctx->program, ctx->block);
3912    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3913    std::pair<Temp, unsigned> offs = get_tcs_per_vertex_input_lds_offset(ctx, instr);
3914    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
3915    unsigned lds_align = calculate_lds_alignment(ctx, offs.second);
3916
3917    load_lds(ctx, elem_size_bytes, dst, offs.first, offs.second, lds_align);
3918 }
3919
3920 void visit_load_tes_per_vertex_input(isel_context *ctx, nir_intrinsic_instr *instr)
3921 {
3922    assert(ctx->shader->info.stage == MESA_SHADER_TESS_EVAL);
3923
3924    Builder bld(ctx->program, ctx->block);
3925
3926    Temp ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_HS_TESS_OFFCHIP * 16u));
3927    Temp oc_lds = get_arg(ctx, ctx->args->oc_lds);
3928    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3929
3930    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
3931    std::pair<Temp, unsigned> offs = get_tcs_per_vertex_output_vmem_offset(ctx, instr);
3932
3933    load_vmem_mubuf(ctx, dst, ring, offs.first, oc_lds, offs.second, elem_size_bytes, instr->dest.ssa.num_components, 0u, true, true);
3934 }
3935
3936 void visit_load_per_vertex_input(isel_context *ctx, nir_intrinsic_instr *instr)
3937 {
3938    switch (ctx->shader->info.stage) {
3939    case MESA_SHADER_GEOMETRY:
3940       visit_load_gs_per_vertex_input(ctx, instr);
3941       break;
3942    case MESA_SHADER_TESS_CTRL:
3943       visit_load_tcs_per_vertex_input(ctx, instr);
3944       break;
3945    case MESA_SHADER_TESS_EVAL:
3946       visit_load_tes_per_vertex_input(ctx, instr);
3947       break;
3948    default:
3949       unreachable("Unimplemented shader stage");
3950    }
3951 }
3952
3953 void visit_load_per_vertex_output(isel_context *ctx, nir_intrinsic_instr *instr)
3954 {
3955    visit_load_tcs_output(ctx, instr, true);
3956 }
3957
3958 void visit_store_per_vertex_output(isel_context *ctx, nir_intrinsic_instr *instr)
3959 {
3960    assert(ctx->stage == tess_control_hs || ctx->stage == vertex_tess_control_hs);
3961    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
3962
3963    visit_store_tcs_output(ctx, instr, true);
3964 }
3965
3966 void visit_load_tess_coord(isel_context *ctx, nir_intrinsic_instr *instr)
3967 {
3968    assert(ctx->shader->info.stage == MESA_SHADER_TESS_EVAL);
3969
3970    Builder bld(ctx->program, ctx->block);
3971    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3972
3973    Operand tes_u(get_arg(ctx, ctx->args->tes_u));
3974    Operand tes_v(get_arg(ctx, ctx->args->tes_v));
3975    Operand tes_w(0u);
3976
3977    if (ctx->shader->info.tess.primitive_mode == GL_TRIANGLES) {
3978       Temp tmp = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), tes_u, tes_v);
3979       tmp = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), Operand(0x3f800000u /* 1.0f */), tmp);
3980       tes_w = Operand(tmp);
3981    }
3982
3983    Temp tess_coord = bld.pseudo(aco_opcode::p_create_vector, Definition(dst), tes_u, tes_v, tes_w);
3984    emit_split_vector(ctx, tess_coord, 3);
3985 }
3986
3987 Temp load_desc_ptr(isel_context *ctx, unsigned desc_set)
3988 {
3989    if (ctx->program->info->need_indirect_descriptor_sets) {
3990       Builder bld(ctx->program, ctx->block);
3991       Temp ptr64 = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->descriptor_sets[0]));
3992       Operand off = bld.copy(bld.def(s1), Operand(desc_set << 2));
3993       return bld.smem(aco_opcode::s_load_dword, bld.def(s1), ptr64, off);//, false, false, false);
3994    }
3995
3996    return get_arg(ctx, ctx->args->descriptor_sets[desc_set]);
3997 }
3998
3999
4000 void visit_load_resource(isel_context *ctx, nir_intrinsic_instr *instr)
4001 {
4002    Builder bld(ctx->program, ctx->block);
4003    Temp index = get_ssa_temp(ctx, instr->src[0].ssa);
4004    if (!ctx->divergent_vals[instr->dest.ssa.index])
4005       index = bld.as_uniform(index);
4006    unsigned desc_set = nir_intrinsic_desc_set(instr);
4007    unsigned binding = nir_intrinsic_binding(instr);
4008
4009    Temp desc_ptr;
4010    radv_pipeline_layout *pipeline_layout = ctx->options->layout;
4011    radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
4012    unsigned offset = layout->binding[binding].offset;
4013    unsigned stride;
4014    if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
4015        layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
4016       unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start + layout->binding[binding].dynamic_offset_offset;
4017       desc_ptr = get_arg(ctx, ctx->args->ac.push_constants);
4018       offset = pipeline_layout->push_constant_size + 16 * idx;
4019       stride = 16;
4020    } else {
4021       desc_ptr = load_desc_ptr(ctx, desc_set);
4022       stride = layout->binding[binding].size;
4023    }
4024
4025    nir_const_value* nir_const_index = nir_src_as_const_value(instr->src[0]);
4026    unsigned const_index = nir_const_index ? nir_const_index->u32 : 0;
4027    if (stride != 1) {
4028       if (nir_const_index) {
4029          const_index = const_index * stride;
4030       } else if (index.type() == RegType::vgpr) {
4031          bool index24bit = layout->binding[binding].array_size <= 0x1000000;
4032          index = bld.v_mul_imm(bld.def(v1), index, stride, index24bit);
4033       } else {
4034          index = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), Operand(index));
4035       }
4036    }
4037    if (offset) {
4038       if (nir_const_index) {
4039          const_index = const_index + offset;
4040       } else if (index.type() == RegType::vgpr) {
4041          index = bld.vadd32(bld.def(v1), Operand(offset), index);
4042       } else {
4043          index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset), Operand(index));
4044       }
4045    }
4046
4047    if (nir_const_index && const_index == 0) {
4048       index = desc_ptr;
4049    } else if (index.type() == RegType::vgpr) {
4050       index = bld.vadd32(bld.def(v1),
4051                          nir_const_index ? Operand(const_index) : Operand(index),
4052                          Operand(desc_ptr));
4053    } else {
4054       index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
4055                        nir_const_index ? Operand(const_index) : Operand(index),
4056                        Operand(desc_ptr));
4057    }
4058
4059    bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), index);
4060 }
4061
4062 void load_buffer(isel_context *ctx, unsigned num_components, Temp dst,
4063                  Temp rsrc, Temp offset, bool glc=false, bool readonly=true)
4064 {
4065    Builder bld(ctx->program, ctx->block);
4066
4067    unsigned num_bytes = dst.size() * 4;
4068    bool dlc = glc && ctx->options->chip_class >= GFX10;
4069
4070    aco_opcode op;
4071    if (dst.type() == RegType::vgpr || (ctx->options->chip_class < GFX8 && !readonly)) {
4072       Operand vaddr = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
4073       Operand soffset = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
4074       unsigned const_offset = 0;
4075
4076       Temp lower = Temp();
4077       if (num_bytes > 16) {
4078          assert(num_components == 3 || num_components == 4);
4079          op = aco_opcode::buffer_load_dwordx4;
4080          lower = bld.tmp(v4);
4081          aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
4082          mubuf->definitions[0] = Definition(lower);
4083          mubuf->operands[0] = Operand(rsrc);
4084          mubuf->operands[1] = vaddr;
4085          mubuf->operands[2] = soffset;
4086          mubuf->offen = (offset.type() == RegType::vgpr);
4087          mubuf->glc = glc;
4088          mubuf->dlc = dlc;
4089          mubuf->barrier = readonly ? barrier_none : barrier_buffer;
4090          mubuf->can_reorder = readonly;
4091          bld.insert(std::move(mubuf));
4092          emit_split_vector(ctx, lower, 2);
4093          num_bytes -= 16;
4094          const_offset = 16;
4095       } else if (num_bytes == 12 && ctx->options->chip_class == GFX6) {
4096          /* GFX6 doesn't support loading vec3, expand to vec4. */
4097          num_bytes = 16;
4098       }
4099
4100       switch (num_bytes) {
4101          case 4:
4102             op = aco_opcode::buffer_load_dword;
4103             break;
4104          case 8:
4105             op = aco_opcode::buffer_load_dwordx2;
4106             break;
4107          case 12:
4108             assert(ctx->options->chip_class > GFX6);
4109             op = aco_opcode::buffer_load_dwordx3;
4110             break;
4111          case 16:
4112             op = aco_opcode::buffer_load_dwordx4;
4113             break;
4114          default:
4115             unreachable("Load SSBO not implemented for this size.");
4116       }
4117       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
4118       mubuf->operands[0] = Operand(rsrc);
4119       mubuf->operands[1] = vaddr;
4120       mubuf->operands[2] = soffset;
4121       mubuf->offen = (offset.type() == RegType::vgpr);
4122       mubuf->glc = glc;
4123       mubuf->dlc = dlc;
4124       mubuf->barrier = readonly ? barrier_none : barrier_buffer;
4125       mubuf->can_reorder = readonly;
4126       mubuf->offset = const_offset;
4127       aco_ptr<Instruction> instr = std::move(mubuf);
4128
4129       if (dst.size() > 4) {
4130          assert(lower != Temp());
4131          Temp upper = bld.tmp(RegType::vgpr, dst.size() - lower.size());
4132          instr->definitions[0] = Definition(upper);
4133          bld.insert(std::move(instr));
4134          if (dst.size() == 8)
4135             emit_split_vector(ctx, upper, 2);
4136          instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size() / 2, 1));
4137          instr->operands[0] = Operand(emit_extract_vector(ctx, lower, 0, v2));
4138          instr->operands[1] = Operand(emit_extract_vector(ctx, lower, 1, v2));
4139          instr->operands[2] = Operand(emit_extract_vector(ctx, upper, 0, v2));
4140          if (dst.size() == 8)
4141             instr->operands[3] = Operand(emit_extract_vector(ctx, upper, 1, v2));
4142       } else if (dst.size() == 3 && ctx->options->chip_class == GFX6) {
4143          Temp vec = bld.tmp(v4);
4144          instr->definitions[0] = Definition(vec);
4145          bld.insert(std::move(instr));
4146          emit_split_vector(ctx, vec, 4);
4147
4148          instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, 3, 1));
4149          instr->operands[0] = Operand(emit_extract_vector(ctx, vec, 0, v1));
4150          instr->operands[1] = Operand(emit_extract_vector(ctx, vec, 1, v1));
4151          instr->operands[2] = Operand(emit_extract_vector(ctx, vec, 2, v1));
4152       }
4153
4154       if (dst.type() == RegType::sgpr) {
4155          Temp vec = bld.tmp(RegType::vgpr, dst.size());
4156          instr->definitions[0] = Definition(vec);
4157          bld.insert(std::move(instr));
4158          expand_vector(ctx, vec, dst, num_components, (1 << num_components) - 1);
4159       } else {
4160          instr->definitions[0] = Definition(dst);
4161          bld.insert(std::move(instr));
4162          emit_split_vector(ctx, dst, num_components);
4163       }
4164    } else {
4165       switch (num_bytes) {
4166          case 4:
4167             op = aco_opcode::s_buffer_load_dword;
4168             break;
4169          case 8:
4170             op = aco_opcode::s_buffer_load_dwordx2;
4171             break;
4172          case 12:
4173          case 16:
4174             op = aco_opcode::s_buffer_load_dwordx4;
4175             break;
4176          case 24:
4177          case 32:
4178             op = aco_opcode::s_buffer_load_dwordx8;
4179             break;
4180          default:
4181             unreachable("Load SSBO not implemented for this size.");
4182       }
4183       aco_ptr<SMEM_instruction> load{create_instruction<SMEM_instruction>(op, Format::SMEM, 2, 1)};
4184       load->operands[0] = Operand(rsrc);
4185       load->operands[1] = Operand(bld.as_uniform(offset));
4186       assert(load->operands[1].getTemp().type() == RegType::sgpr);
4187       load->definitions[0] = Definition(dst);
4188       load->glc = glc;
4189       load->dlc = dlc;
4190       load->barrier = readonly ? barrier_none : barrier_buffer;
4191       load->can_reorder = false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
4192       assert(ctx->options->chip_class >= GFX8 || !glc);
4193
4194       /* trim vector */
4195       if (dst.size() == 3) {
4196          Temp vec = bld.tmp(s4);
4197          load->definitions[0] = Definition(vec);
4198          bld.insert(std::move(load));
4199          emit_split_vector(ctx, vec, 4);
4200
4201          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4202                     emit_extract_vector(ctx, vec, 0, s1),
4203                     emit_extract_vector(ctx, vec, 1, s1),
4204                     emit_extract_vector(ctx, vec, 2, s1));
4205       } else if (dst.size() == 6) {
4206          Temp vec = bld.tmp(s8);
4207          load->definitions[0] = Definition(vec);
4208          bld.insert(std::move(load));
4209          emit_split_vector(ctx, vec, 4);
4210
4211          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4212                     emit_extract_vector(ctx, vec, 0, s2),
4213                     emit_extract_vector(ctx, vec, 1, s2),
4214                     emit_extract_vector(ctx, vec, 2, s2));
4215       } else {
4216          bld.insert(std::move(load));
4217       }
4218       emit_split_vector(ctx, dst, num_components);
4219    }
4220 }
4221
4222 void visit_load_ubo(isel_context *ctx, nir_intrinsic_instr *instr)
4223 {
4224    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4225    Temp rsrc = get_ssa_temp(ctx, instr->src[0].ssa);
4226
4227    Builder bld(ctx->program, ctx->block);
4228
4229    nir_intrinsic_instr* idx_instr = nir_instr_as_intrinsic(instr->src[0].ssa->parent_instr);
4230    unsigned desc_set = nir_intrinsic_desc_set(idx_instr);
4231    unsigned binding = nir_intrinsic_binding(idx_instr);
4232    radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
4233
4234    if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
4235       uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
4236                            S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
4237                            S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
4238                            S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
4239       if (ctx->options->chip_class >= GFX10) {
4240          desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
4241                       S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
4242                       S_008F0C_RESOURCE_LEVEL(1);
4243       } else {
4244          desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
4245                       S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
4246       }
4247       Temp upper_dwords = bld.pseudo(aco_opcode::p_create_vector, bld.def(s3),
4248                                      Operand(S_008F04_BASE_ADDRESS_HI(ctx->options->address32_hi)),
4249                                      Operand(0xFFFFFFFFu),
4250                                      Operand(desc_type));
4251       rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
4252                         rsrc, upper_dwords);
4253    } else {
4254       rsrc = convert_pointer_to_64_bit(ctx, rsrc);
4255       rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
4256    }
4257
4258    load_buffer(ctx, instr->num_components, dst, rsrc, get_ssa_temp(ctx, instr->src[1].ssa));
4259 }
4260
4261 void visit_load_push_constant(isel_context *ctx, nir_intrinsic_instr *instr)
4262 {
4263    Builder bld(ctx->program, ctx->block);
4264    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4265
4266    unsigned offset = nir_intrinsic_base(instr);
4267    nir_const_value *index_cv = nir_src_as_const_value(instr->src[0]);
4268    if (index_cv && instr->dest.ssa.bit_size == 32) {
4269
4270       unsigned count = instr->dest.ssa.num_components;
4271       unsigned start = (offset + index_cv->u32) / 4u;
4272       start -= ctx->args->ac.base_inline_push_consts;
4273       if (start + count <= ctx->args->ac.num_inline_push_consts) {
4274          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
4275          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
4276          for (unsigned i = 0; i < count; ++i) {
4277             elems[i] = get_arg(ctx, ctx->args->ac.inline_push_consts[start + i]);
4278             vec->operands[i] = Operand{elems[i]};
4279          }
4280          vec->definitions[0] = Definition(dst);
4281          ctx->block->instructions.emplace_back(std::move(vec));
4282          ctx->allocated_vec.emplace(dst.id(), elems);
4283          return;
4284       }
4285    }
4286
4287    Temp index = bld.as_uniform(get_ssa_temp(ctx, instr->src[0].ssa));
4288    if (offset != 0) // TODO check if index != 0 as well
4289       index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset), index);
4290    Temp ptr = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->ac.push_constants));
4291    Temp vec = dst;
4292    bool trim = false;
4293    aco_opcode op;
4294
4295    switch (dst.size()) {
4296    case 1:
4297       op = aco_opcode::s_load_dword;
4298       break;
4299    case 2:
4300       op = aco_opcode::s_load_dwordx2;
4301       break;
4302    case 3:
4303       vec = bld.tmp(s4);
4304       trim = true;
4305    case 4:
4306       op = aco_opcode::s_load_dwordx4;
4307       break;
4308    case 6:
4309       vec = bld.tmp(s8);
4310       trim = true;
4311    case 8:
4312       op = aco_opcode::s_load_dwordx8;
4313       break;
4314    default:
4315       unreachable("unimplemented or forbidden load_push_constant.");
4316    }
4317
4318    bld.smem(op, Definition(vec), ptr, index);
4319
4320    if (trim) {
4321       emit_split_vector(ctx, vec, 4);
4322       RegClass rc = dst.size() == 3 ? s1 : s2;
4323       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4324                  emit_extract_vector(ctx, vec, 0, rc),
4325                  emit_extract_vector(ctx, vec, 1, rc),
4326                  emit_extract_vector(ctx, vec, 2, rc));
4327
4328    }
4329    emit_split_vector(ctx, dst, instr->dest.ssa.num_components);
4330 }
4331
4332 void visit_load_constant(isel_context *ctx, nir_intrinsic_instr *instr)
4333 {
4334    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4335
4336    Builder bld(ctx->program, ctx->block);
4337
4338    uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
4339                         S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
4340                         S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
4341                         S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
4342    if (ctx->options->chip_class >= GFX10) {
4343       desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
4344                    S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
4345                    S_008F0C_RESOURCE_LEVEL(1);
4346    } else {
4347       desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
4348                    S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
4349    }
4350
4351    unsigned base = nir_intrinsic_base(instr);
4352    unsigned range = nir_intrinsic_range(instr);
4353
4354    Temp offset = get_ssa_temp(ctx, instr->src[0].ssa);
4355    if (base && offset.type() == RegType::sgpr)
4356       offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), offset, Operand(base));
4357    else if (base && offset.type() == RegType::vgpr)
4358       offset = bld.vadd32(bld.def(v1), Operand(base), offset);
4359
4360    Temp rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
4361                           bld.sop1(aco_opcode::p_constaddr, bld.def(s2), bld.def(s1, scc), Operand(ctx->constant_data_offset)),
4362                           Operand(MIN2(base + range, ctx->shader->constant_data_size)),
4363                           Operand(desc_type));
4364
4365    load_buffer(ctx, instr->num_components, dst, rsrc, offset);
4366 }
4367
4368 void visit_discard_if(isel_context *ctx, nir_intrinsic_instr *instr)
4369 {
4370    if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
4371       ctx->cf_info.exec_potentially_empty_discard = true;
4372
4373    ctx->program->needs_exact = true;
4374
4375    // TODO: optimize uniform conditions
4376    Builder bld(ctx->program, ctx->block);
4377    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
4378    assert(src.regClass() == bld.lm);
4379    src = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
4380    bld.pseudo(aco_opcode::p_discard_if, src);
4381    ctx->block->kind |= block_kind_uses_discard_if;
4382    return;
4383 }
4384
4385 void visit_discard(isel_context* ctx, nir_intrinsic_instr *instr)
4386 {
4387    Builder bld(ctx->program, ctx->block);
4388
4389    if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
4390       ctx->cf_info.exec_potentially_empty_discard = true;
4391
4392    bool divergent = ctx->cf_info.parent_if.is_divergent ||
4393                     ctx->cf_info.parent_loop.has_divergent_continue;
4394
4395    if (ctx->block->loop_nest_depth &&
4396        ((nir_instr_is_last(&instr->instr) && !divergent) || divergent)) {
4397       /* we handle discards the same way as jump instructions */
4398       append_logical_end(ctx->block);
4399
4400       /* in loops, discard behaves like break */
4401       Block *linear_target = ctx->cf_info.parent_loop.exit;
4402       ctx->block->kind |= block_kind_discard;
4403
4404       if (!divergent) {
4405          /* uniform discard - loop ends here */
4406          assert(nir_instr_is_last(&instr->instr));
4407          ctx->block->kind |= block_kind_uniform;
4408          ctx->cf_info.has_branch = true;
4409          bld.branch(aco_opcode::p_branch);
4410          add_linear_edge(ctx->block->index, linear_target);
4411          return;
4412       }
4413
4414       /* we add a break right behind the discard() instructions */
4415       ctx->block->kind |= block_kind_break;
4416       unsigned idx = ctx->block->index;
4417
4418       /* remove critical edges from linear CFG */
4419       bld.branch(aco_opcode::p_branch);
4420       Block* break_block = ctx->program->create_and_insert_block();
4421       break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
4422       break_block->kind |= block_kind_uniform;
4423       add_linear_edge(idx, break_block);
4424       add_linear_edge(break_block->index, linear_target);
4425       bld.reset(break_block);
4426       bld.branch(aco_opcode::p_branch);
4427
4428       Block* continue_block = ctx->program->create_and_insert_block();
4429       continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
4430       add_linear_edge(idx, continue_block);
4431       append_logical_start(continue_block);
4432       ctx->block = continue_block;
4433
4434       return;
4435    }
4436
4437    /* it can currently happen that NIR doesn't remove the unreachable code */
4438    if (!nir_instr_is_last(&instr->instr)) {
4439       ctx->program->needs_exact = true;
4440       /* save exec somewhere temporarily so that it doesn't get
4441        * overwritten before the discard from outer exec masks */
4442       Temp cond = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), Operand(0xFFFFFFFF), Operand(exec, bld.lm));
4443       bld.pseudo(aco_opcode::p_discard_if, cond);
4444       ctx->block->kind |= block_kind_uses_discard_if;
4445       return;
4446    }
4447
4448    /* This condition is incorrect for uniformly branched discards in a loop
4449     * predicated by a divergent condition, but the above code catches that case
4450     * and the discard would end up turning into a discard_if.
4451     * For example:
4452     * if (divergent) {
4453     *    while (...) {
4454     *       if (uniform) {
4455     *          discard;
4456     *       }
4457     *    }
4458     * }
4459     */
4460    if (!ctx->cf_info.parent_if.is_divergent) {
4461       /* program just ends here */
4462       ctx->block->kind |= block_kind_uniform;
4463       bld.exp(aco_opcode::exp, Operand(v1), Operand(v1), Operand(v1), Operand(v1),
4464               0 /* enabled mask */, 9 /* dest */,
4465               false /* compressed */, true/* done */, true /* valid mask */);
4466       bld.sopp(aco_opcode::s_endpgm);
4467       // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
4468    } else {
4469       ctx->block->kind |= block_kind_discard;
4470       /* branch and linear edge is added by visit_if() */
4471    }
4472 }
4473
4474 enum aco_descriptor_type {
4475    ACO_DESC_IMAGE,
4476    ACO_DESC_FMASK,
4477    ACO_DESC_SAMPLER,
4478    ACO_DESC_BUFFER,
4479    ACO_DESC_PLANE_0,
4480    ACO_DESC_PLANE_1,
4481    ACO_DESC_PLANE_2,
4482 };
4483
4484 static bool
4485 should_declare_array(isel_context *ctx, enum glsl_sampler_dim sampler_dim, bool is_array) {
4486    if (sampler_dim == GLSL_SAMPLER_DIM_BUF)
4487       return false;
4488    ac_image_dim dim = ac_get_sampler_dim(ctx->options->chip_class, sampler_dim, is_array);
4489    return dim == ac_image_cube ||
4490           dim == ac_image_1darray ||
4491           dim == ac_image_2darray ||
4492           dim == ac_image_2darraymsaa;
4493 }
4494
4495 Temp get_sampler_desc(isel_context *ctx, nir_deref_instr *deref_instr,
4496                       enum aco_descriptor_type desc_type,
4497                       const nir_tex_instr *tex_instr, bool image, bool write)
4498 {
4499 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
4500    std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
4501    if (it != ctx->tex_desc.end())
4502       return it->second;
4503 */
4504    Temp index = Temp();
4505    bool index_set = false;
4506    unsigned constant_index = 0;
4507    unsigned descriptor_set;
4508    unsigned base_index;
4509    Builder bld(ctx->program, ctx->block);
4510
4511    if (!deref_instr) {
4512       assert(tex_instr && !image);
4513       descriptor_set = 0;
4514       base_index = tex_instr->sampler_index;
4515    } else {
4516       while(deref_instr->deref_type != nir_deref_type_var) {
4517          unsigned array_size = glsl_get_aoa_size(deref_instr->type);
4518          if (!array_size)
4519             array_size = 1;
4520
4521          assert(deref_instr->deref_type == nir_deref_type_array);
4522          nir_const_value *const_value = nir_src_as_const_value(deref_instr->arr.index);
4523          if (const_value) {
4524             constant_index += array_size * const_value->u32;
4525          } else {
4526             Temp indirect = get_ssa_temp(ctx, deref_instr->arr.index.ssa);
4527             if (indirect.type() == RegType::vgpr)
4528                indirect = bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), indirect);
4529
4530             if (array_size != 1)
4531                indirect = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(array_size), indirect);
4532
4533             if (!index_set) {
4534                index = indirect;
4535                index_set = true;
4536             } else {
4537                index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), index, indirect);
4538             }
4539          }
4540
4541          deref_instr = nir_src_as_deref(deref_instr->parent);
4542       }
4543       descriptor_set = deref_instr->var->data.descriptor_set;
4544       base_index = deref_instr->var->data.binding;
4545    }
4546
4547    Temp list = load_desc_ptr(ctx, descriptor_set);
4548    list = convert_pointer_to_64_bit(ctx, list);
4549
4550    struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4551    struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4552    unsigned offset = binding->offset;
4553    unsigned stride = binding->size;
4554    aco_opcode opcode;
4555    RegClass type;
4556
4557    assert(base_index < layout->binding_count);
4558
4559    switch (desc_type) {
4560    case ACO_DESC_IMAGE:
4561       type = s8;
4562       opcode = aco_opcode::s_load_dwordx8;
4563       break;
4564    case ACO_DESC_FMASK:
4565       type = s8;
4566       opcode = aco_opcode::s_load_dwordx8;
4567       offset += 32;
4568       break;
4569    case ACO_DESC_SAMPLER:
4570       type = s4;
4571       opcode = aco_opcode::s_load_dwordx4;
4572       if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4573          offset += radv_combined_image_descriptor_sampler_offset(binding);
4574       break;
4575    case ACO_DESC_BUFFER:
4576       type = s4;
4577       opcode = aco_opcode::s_load_dwordx4;
4578       break;
4579    case ACO_DESC_PLANE_0:
4580    case ACO_DESC_PLANE_1:
4581       type = s8;
4582       opcode = aco_opcode::s_load_dwordx8;
4583       offset += 32 * (desc_type - ACO_DESC_PLANE_0);
4584       break;
4585    case ACO_DESC_PLANE_2:
4586       type = s4;
4587       opcode = aco_opcode::s_load_dwordx4;
4588       offset += 64;
4589       break;
4590    default:
4591       unreachable("invalid desc_type\n");
4592    }
4593
4594    offset += constant_index * stride;
4595
4596    if (desc_type == ACO_DESC_SAMPLER && binding->immutable_samplers_offset &&
4597       (!index_set || binding->immutable_samplers_equal)) {
4598       if (binding->immutable_samplers_equal)
4599          constant_index = 0;
4600
4601       const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4602       return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
4603                         Operand(samplers[constant_index * 4 + 0]),
4604                         Operand(samplers[constant_index * 4 + 1]),
4605                         Operand(samplers[constant_index * 4 + 2]),
4606                         Operand(samplers[constant_index * 4 + 3]));
4607    }
4608
4609    Operand off;
4610    if (!index_set) {
4611       off = bld.copy(bld.def(s1), Operand(offset));
4612    } else {
4613       off = Operand((Temp)bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset),
4614                                    bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), index)));
4615    }
4616
4617    Temp res = bld.smem(opcode, bld.def(type), list, off);
4618
4619    if (desc_type == ACO_DESC_PLANE_2) {
4620       Temp components[8];
4621       for (unsigned i = 0; i < 8; i++)
4622          components[i] = bld.tmp(s1);
4623       bld.pseudo(aco_opcode::p_split_vector,
4624                  Definition(components[0]),
4625                  Definition(components[1]),
4626                  Definition(components[2]),
4627                  Definition(components[3]),
4628                  res);
4629
4630       Temp desc2 = get_sampler_desc(ctx, deref_instr, ACO_DESC_PLANE_1, tex_instr, image, write);
4631       bld.pseudo(aco_opcode::p_split_vector,
4632                  bld.def(s1), bld.def(s1), bld.def(s1), bld.def(s1),
4633                  Definition(components[4]),
4634                  Definition(components[5]),
4635                  Definition(components[6]),
4636                  Definition(components[7]),
4637                  desc2);
4638
4639       res = bld.pseudo(aco_opcode::p_create_vector, bld.def(s8),
4640                        components[0], components[1], components[2], components[3],
4641                        components[4], components[5], components[6], components[7]);
4642    }
4643
4644    return res;
4645 }
4646
4647 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
4648 {
4649    switch (dim) {
4650    case GLSL_SAMPLER_DIM_BUF:
4651       return 1;
4652    case GLSL_SAMPLER_DIM_1D:
4653       return array ? 2 : 1;
4654    case GLSL_SAMPLER_DIM_2D:
4655       return array ? 3 : 2;
4656    case GLSL_SAMPLER_DIM_MS:
4657       return array ? 4 : 3;
4658    case GLSL_SAMPLER_DIM_3D:
4659    case GLSL_SAMPLER_DIM_CUBE:
4660       return 3;
4661    case GLSL_SAMPLER_DIM_RECT:
4662    case GLSL_SAMPLER_DIM_SUBPASS:
4663       return 2;
4664    case GLSL_SAMPLER_DIM_SUBPASS_MS:
4665       return 3;
4666    default:
4667       break;
4668    }
4669    return 0;
4670 }
4671
4672
4673 /* Adjust the sample index according to FMASK.
4674  *
4675  * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4676  * which is the identity mapping. Each nibble says which physical sample
4677  * should be fetched to get that sample.
4678  *
4679  * For example, 0x11111100 means there are only 2 samples stored and
4680  * the second sample covers 3/4 of the pixel. When reading samples 0
4681  * and 1, return physical sample 0 (determined by the first two 0s
4682  * in FMASK), otherwise return physical sample 1.
4683  *
4684  * The sample index should be adjusted as follows:
4685  *   sample_index = (fmask >> (sample_index * 4)) & 0xF;
4686  */
4687 static Temp adjust_sample_index_using_fmask(isel_context *ctx, bool da, std::vector<Temp>& coords, Operand sample_index, Temp fmask_desc_ptr)
4688 {
4689    Builder bld(ctx->program, ctx->block);
4690    Temp fmask = bld.tmp(v1);
4691    unsigned dim = ctx->options->chip_class >= GFX10
4692                   ? ac_get_sampler_dim(ctx->options->chip_class, GLSL_SAMPLER_DIM_2D, da)
4693                   : 0;
4694
4695    Temp coord = da ? bld.pseudo(aco_opcode::p_create_vector, bld.def(v3), coords[0], coords[1], coords[2]) :
4696                      bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), coords[0], coords[1]);
4697    aco_ptr<MIMG_instruction> load{create_instruction<MIMG_instruction>(aco_opcode::image_load, Format::MIMG, 3, 1)};
4698    load->operands[0] = Operand(fmask_desc_ptr);
4699    load->operands[1] = Operand(s4); /* no sampler */
4700    load->operands[2] = Operand(coord);
4701    load->definitions[0] = Definition(fmask);
4702    load->glc = false;
4703    load->dlc = false;
4704    load->dmask = 0x1;
4705    load->unrm = true;
4706    load->da = da;
4707    load->dim = dim;
4708    load->can_reorder = true; /* fmask images shouldn't be modified */
4709    ctx->block->instructions.emplace_back(std::move(load));
4710
4711    Operand sample_index4;
4712    if (sample_index.isConstant() && sample_index.constantValue() < 16) {
4713       sample_index4 = Operand(sample_index.constantValue() << 2);
4714    } else if (sample_index.regClass() == s1) {
4715       sample_index4 = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), sample_index, Operand(2u));
4716    } else {
4717       assert(sample_index.regClass() == v1);
4718       sample_index4 = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), sample_index);
4719    }
4720
4721    Temp final_sample;
4722    if (sample_index4.isConstant() && sample_index4.constantValue() == 0)
4723       final_sample = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(15u), fmask);
4724    else if (sample_index4.isConstant() && sample_index4.constantValue() == 28)
4725       final_sample = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(28u), fmask);
4726    else
4727       final_sample = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1), fmask, sample_index4, Operand(4u));
4728
4729    /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4730     * resource descriptor is 0 (invalid),
4731     */
4732    Temp compare = bld.tmp(bld.lm);
4733    bld.vopc_e64(aco_opcode::v_cmp_lg_u32, Definition(compare),
4734                 Operand(0u), emit_extract_vector(ctx, fmask_desc_ptr, 1, s1)).def(0).setHint(vcc);
4735
4736    Temp sample_index_v = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), sample_index);
4737
4738    /* Replace the MSAA sample index. */
4739    return bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), sample_index_v, final_sample, compare);
4740 }
4741
4742 static Temp get_image_coords(isel_context *ctx, const nir_intrinsic_instr *instr, const struct glsl_type *type)
4743 {
4744
4745    Temp src0 = get_ssa_temp(ctx, instr->src[1].ssa);
4746    enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4747    bool is_array = glsl_sampler_type_is_array(type);
4748    ASSERTED bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS || dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
4749    assert(!add_frag_pos && "Input attachments should be lowered.");
4750    bool is_ms = (dim == GLSL_SAMPLER_DIM_MS || dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
4751    bool gfx9_1d = ctx->options->chip_class == GFX9 && dim == GLSL_SAMPLER_DIM_1D;
4752    int count = image_type_to_components_count(dim, is_array);
4753    std::vector<Temp> coords(count);
4754    Builder bld(ctx->program, ctx->block);
4755
4756    if (is_ms) {
4757       count--;
4758       Temp src2 = get_ssa_temp(ctx, instr->src[2].ssa);
4759       /* get sample index */
4760       if (instr->intrinsic == nir_intrinsic_image_deref_load) {
4761          nir_const_value *sample_cv = nir_src_as_const_value(instr->src[2]);
4762          Operand sample_index = sample_cv ? Operand(sample_cv->u32) : Operand(emit_extract_vector(ctx, src2, 0, v1));
4763          std::vector<Temp> fmask_load_address;
4764          for (unsigned i = 0; i < (is_array ? 3 : 2); i++)
4765             fmask_load_address.emplace_back(emit_extract_vector(ctx, src0, i, v1));
4766
4767          Temp fmask_desc_ptr = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_FMASK, nullptr, false, false);
4768          coords[count] = adjust_sample_index_using_fmask(ctx, is_array, fmask_load_address, sample_index, fmask_desc_ptr);
4769       } else {
4770          coords[count] = emit_extract_vector(ctx, src2, 0, v1);
4771       }
4772    }
4773
4774    if (gfx9_1d) {
4775       coords[0] = emit_extract_vector(ctx, src0, 0, v1);
4776       coords.resize(coords.size() + 1);
4777       coords[1] = bld.copy(bld.def(v1), Operand(0u));
4778       if (is_array)
4779          coords[2] = emit_extract_vector(ctx, src0, 1, v1);
4780    } else {
4781       for (int i = 0; i < count; i++)
4782          coords[i] = emit_extract_vector(ctx, src0, i, v1);
4783    }
4784
4785    if (instr->intrinsic == nir_intrinsic_image_deref_load ||
4786        instr->intrinsic == nir_intrinsic_image_deref_store) {
4787       int lod_index = instr->intrinsic == nir_intrinsic_image_deref_load ? 3 : 4;
4788       bool level_zero = nir_src_is_const(instr->src[lod_index]) && nir_src_as_uint(instr->src[lod_index]) == 0;
4789
4790       if (!level_zero)
4791          coords.emplace_back(get_ssa_temp(ctx, instr->src[lod_index].ssa));
4792    }
4793
4794    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, coords.size(), 1)};
4795    for (unsigned i = 0; i < coords.size(); i++)
4796       vec->operands[i] = Operand(coords[i]);
4797    Temp res = {ctx->program->allocateId(), RegClass(RegType::vgpr, coords.size())};
4798    vec->definitions[0] = Definition(res);
4799    ctx->block->instructions.emplace_back(std::move(vec));
4800    return res;
4801 }
4802
4803
4804 void visit_image_load(isel_context *ctx, nir_intrinsic_instr *instr)
4805 {
4806    Builder bld(ctx->program, ctx->block);
4807    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4808    const struct glsl_type *type = glsl_without_array(var->type);
4809    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4810    bool is_array = glsl_sampler_type_is_array(type);
4811    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4812
4813    if (dim == GLSL_SAMPLER_DIM_BUF) {
4814       unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
4815       unsigned num_channels = util_last_bit(mask);
4816       Temp rsrc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4817       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4818
4819       aco_opcode opcode;
4820       switch (num_channels) {
4821       case 1:
4822          opcode = aco_opcode::buffer_load_format_x;
4823          break;
4824       case 2:
4825          opcode = aco_opcode::buffer_load_format_xy;
4826          break;
4827       case 3:
4828          opcode = aco_opcode::buffer_load_format_xyz;
4829          break;
4830       case 4:
4831          opcode = aco_opcode::buffer_load_format_xyzw;
4832          break;
4833       default:
4834          unreachable(">4 channel buffer image load");
4835       }
4836       aco_ptr<MUBUF_instruction> load{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 3, 1)};
4837       load->operands[0] = Operand(rsrc);
4838       load->operands[1] = Operand(vindex);
4839       load->operands[2] = Operand((uint32_t) 0);
4840       Temp tmp;
4841       if (num_channels == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
4842          tmp = dst;
4843       else
4844          tmp = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_channels)};
4845       load->definitions[0] = Definition(tmp);
4846       load->idxen = true;
4847       load->glc = var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT);
4848       load->dlc = load->glc && ctx->options->chip_class >= GFX10;
4849       load->barrier = barrier_image;
4850       ctx->block->instructions.emplace_back(std::move(load));
4851
4852       expand_vector(ctx, tmp, dst, instr->dest.ssa.num_components, (1 << num_channels) - 1);
4853       return;
4854    }
4855
4856    Temp coords = get_image_coords(ctx, instr, type);
4857    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
4858
4859    unsigned dmask = nir_ssa_def_components_read(&instr->dest.ssa);
4860    unsigned num_components = util_bitcount(dmask);
4861    Temp tmp;
4862    if (num_components == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
4863       tmp = dst;
4864    else
4865       tmp = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_components)};
4866
4867    bool level_zero = nir_src_is_const(instr->src[3]) && nir_src_as_uint(instr->src[3]) == 0;
4868    aco_opcode opcode = level_zero ? aco_opcode::image_load : aco_opcode::image_load_mip;
4869
4870    aco_ptr<MIMG_instruction> load{create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 1)};
4871    load->operands[0] = Operand(resource);
4872    load->operands[1] = Operand(s4); /* no sampler */
4873    load->operands[2] = Operand(coords);
4874    load->definitions[0] = Definition(tmp);
4875    load->glc = var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT) ? 1 : 0;
4876    load->dlc = load->glc && ctx->options->chip_class >= GFX10;
4877    load->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4878    load->dmask = dmask;
4879    load->unrm = true;
4880    load->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
4881    load->barrier = barrier_image;
4882    ctx->block->instructions.emplace_back(std::move(load));
4883
4884    expand_vector(ctx, tmp, dst, instr->dest.ssa.num_components, dmask);
4885    return;
4886 }
4887
4888 void visit_image_store(isel_context *ctx, nir_intrinsic_instr *instr)
4889 {
4890    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4891    const struct glsl_type *type = glsl_without_array(var->type);
4892    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4893    bool is_array = glsl_sampler_type_is_array(type);
4894    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[3].ssa));
4895
4896    bool glc = ctx->options->chip_class == GFX6 || var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE) ? 1 : 0;
4897
4898    if (dim == GLSL_SAMPLER_DIM_BUF) {
4899       Temp rsrc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4900       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4901       aco_opcode opcode;
4902       switch (data.size()) {
4903       case 1:
4904          opcode = aco_opcode::buffer_store_format_x;
4905          break;
4906       case 2:
4907          opcode = aco_opcode::buffer_store_format_xy;
4908          break;
4909       case 3:
4910          opcode = aco_opcode::buffer_store_format_xyz;
4911          break;
4912       case 4:
4913          opcode = aco_opcode::buffer_store_format_xyzw;
4914          break;
4915       default:
4916          unreachable(">4 channel buffer image store");
4917       }
4918       aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 4, 0)};
4919       store->operands[0] = Operand(rsrc);
4920       store->operands[1] = Operand(vindex);
4921       store->operands[2] = Operand((uint32_t) 0);
4922       store->operands[3] = Operand(data);
4923       store->idxen = true;
4924       store->glc = glc;
4925       store->dlc = false;
4926       store->disable_wqm = true;
4927       store->barrier = barrier_image;
4928       ctx->program->needs_exact = true;
4929       ctx->block->instructions.emplace_back(std::move(store));
4930       return;
4931    }
4932
4933    assert(data.type() == RegType::vgpr);
4934    Temp coords = get_image_coords(ctx, instr, type);
4935    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
4936
4937    bool level_zero = nir_src_is_const(instr->src[4]) && nir_src_as_uint(instr->src[4]) == 0;
4938    aco_opcode opcode = level_zero ? aco_opcode::image_store : aco_opcode::image_store_mip;
4939
4940    aco_ptr<MIMG_instruction> store{create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 0)};
4941    store->operands[0] = Operand(resource);
4942    store->operands[1] = Operand(data);
4943    store->operands[2] = Operand(coords);
4944    store->glc = glc;
4945    store->dlc = false;
4946    store->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4947    store->dmask = (1 << data.size()) - 1;
4948    store->unrm = true;
4949    store->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
4950    store->disable_wqm = true;
4951    store->barrier = barrier_image;
4952    ctx->program->needs_exact = true;
4953    ctx->block->instructions.emplace_back(std::move(store));
4954    return;
4955 }
4956
4957 void visit_image_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
4958 {
4959    /* return the previous value if dest is ever used */
4960    bool return_previous = false;
4961    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
4962       return_previous = true;
4963       break;
4964    }
4965    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
4966       return_previous = true;
4967       break;
4968    }
4969
4970    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4971    const struct glsl_type *type = glsl_without_array(var->type);
4972    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4973    bool is_array = glsl_sampler_type_is_array(type);
4974    Builder bld(ctx->program, ctx->block);
4975
4976    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[3].ssa));
4977    assert(data.size() == 1 && "64bit ssbo atomics not yet implemented.");
4978
4979    if (instr->intrinsic == nir_intrinsic_image_deref_atomic_comp_swap)
4980       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), get_ssa_temp(ctx, instr->src[4].ssa), data);
4981
4982    aco_opcode buf_op, image_op;
4983    switch (instr->intrinsic) {
4984       case nir_intrinsic_image_deref_atomic_add:
4985          buf_op = aco_opcode::buffer_atomic_add;
4986          image_op = aco_opcode::image_atomic_add;
4987          break;
4988       case nir_intrinsic_image_deref_atomic_umin:
4989          buf_op = aco_opcode::buffer_atomic_umin;
4990          image_op = aco_opcode::image_atomic_umin;
4991          break;
4992       case nir_intrinsic_image_deref_atomic_imin:
4993          buf_op = aco_opcode::buffer_atomic_smin;
4994          image_op = aco_opcode::image_atomic_smin;
4995          break;
4996       case nir_intrinsic_image_deref_atomic_umax:
4997          buf_op = aco_opcode::buffer_atomic_umax;
4998          image_op = aco_opcode::image_atomic_umax;
4999          break;
5000       case nir_intrinsic_image_deref_atomic_imax:
5001          buf_op = aco_opcode::buffer_atomic_smax;
5002          image_op = aco_opcode::image_atomic_smax;
5003          break;
5004       case nir_intrinsic_image_deref_atomic_and:
5005          buf_op = aco_opcode::buffer_atomic_and;
5006          image_op = aco_opcode::image_atomic_and;
5007          break;
5008       case nir_intrinsic_image_deref_atomic_or:
5009          buf_op = aco_opcode::buffer_atomic_or;
5010          image_op = aco_opcode::image_atomic_or;
5011          break;
5012       case nir_intrinsic_image_deref_atomic_xor:
5013          buf_op = aco_opcode::buffer_atomic_xor;
5014          image_op = aco_opcode::image_atomic_xor;
5015          break;
5016       case nir_intrinsic_image_deref_atomic_exchange:
5017          buf_op = aco_opcode::buffer_atomic_swap;
5018          image_op = aco_opcode::image_atomic_swap;
5019          break;
5020       case nir_intrinsic_image_deref_atomic_comp_swap:
5021          buf_op = aco_opcode::buffer_atomic_cmpswap;
5022          image_op = aco_opcode::image_atomic_cmpswap;
5023          break;
5024       default:
5025          unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5026    }
5027
5028    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5029
5030    if (dim == GLSL_SAMPLER_DIM_BUF) {
5031       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
5032       Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
5033       //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5034       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(buf_op, Format::MUBUF, 4, return_previous ? 1 : 0)};
5035       mubuf->operands[0] = Operand(resource);
5036       mubuf->operands[1] = Operand(vindex);
5037       mubuf->operands[2] = Operand((uint32_t)0);
5038       mubuf->operands[3] = Operand(data);
5039       if (return_previous)
5040          mubuf->definitions[0] = Definition(dst);
5041       mubuf->offset = 0;
5042       mubuf->idxen = true;
5043       mubuf->glc = return_previous;
5044       mubuf->dlc = false; /* Not needed for atomics */
5045       mubuf->disable_wqm = true;
5046       mubuf->barrier = barrier_image;
5047       ctx->program->needs_exact = true;
5048       ctx->block->instructions.emplace_back(std::move(mubuf));
5049       return;
5050    }
5051
5052    Temp coords = get_image_coords(ctx, instr, type);
5053    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
5054    aco_ptr<MIMG_instruction> mimg{create_instruction<MIMG_instruction>(image_op, Format::MIMG, 3, return_previous ? 1 : 0)};
5055    mimg->operands[0] = Operand(resource);
5056    mimg->operands[1] = Operand(data);
5057    mimg->operands[2] = Operand(coords);
5058    if (return_previous)
5059       mimg->definitions[0] = Definition(dst);
5060    mimg->glc = return_previous;
5061    mimg->dlc = false; /* Not needed for atomics */
5062    mimg->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
5063    mimg->dmask = (1 << data.size()) - 1;
5064    mimg->unrm = true;
5065    mimg->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
5066    mimg->disable_wqm = true;
5067    mimg->barrier = barrier_image;
5068    ctx->program->needs_exact = true;
5069    ctx->block->instructions.emplace_back(std::move(mimg));
5070    return;
5071 }
5072
5073 void get_buffer_size(isel_context *ctx, Temp desc, Temp dst, bool in_elements)
5074 {
5075    if (in_elements && ctx->options->chip_class == GFX8) {
5076       /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
5077       Builder bld(ctx->program, ctx->block);
5078
5079       Temp size = emit_extract_vector(ctx, desc, 2, s1);
5080
5081       Temp size_div3 = bld.vop3(aco_opcode::v_mul_hi_u32, bld.def(v1), bld.copy(bld.def(v1), Operand(0xaaaaaaabu)), size);
5082       size_div3 = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.as_uniform(size_div3), Operand(1u));
5083
5084       Temp stride = emit_extract_vector(ctx, desc, 1, s1);
5085       stride = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), stride, Operand((5u << 16) | 16u));
5086
5087       Temp is12 = bld.sopc(aco_opcode::s_cmp_eq_i32, bld.def(s1, scc), stride, Operand(12u));
5088       size = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), size_div3, size, bld.scc(is12));
5089
5090       Temp shr_dst = dst.type() == RegType::vgpr ? bld.tmp(s1) : dst;
5091       bld.sop2(aco_opcode::s_lshr_b32, Definition(shr_dst), bld.def(s1, scc),
5092                size, bld.sop1(aco_opcode::s_ff1_i32_b32, bld.def(s1), stride));
5093       if (dst.type() == RegType::vgpr)
5094          bld.copy(Definition(dst), shr_dst);
5095
5096       /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
5097    } else {
5098       emit_extract_vector(ctx, desc, 2, dst);
5099    }
5100 }
5101
5102 void visit_image_size(isel_context *ctx, nir_intrinsic_instr *instr)
5103 {
5104    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
5105    const struct glsl_type *type = glsl_without_array(var->type);
5106    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
5107    bool is_array = glsl_sampler_type_is_array(type);
5108    Builder bld(ctx->program, ctx->block);
5109
5110    if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
5111       Temp desc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, NULL, true, false);
5112       return get_buffer_size(ctx, desc, get_ssa_temp(ctx, &instr->dest.ssa), true);
5113    }
5114
5115    /* LOD */
5116    Temp lod = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
5117
5118    /* Resource */
5119    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, NULL, true, false);
5120
5121    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5122
5123    aco_ptr<MIMG_instruction> mimg{create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 3, 1)};
5124    mimg->operands[0] = Operand(resource);
5125    mimg->operands[1] = Operand(s4); /* no sampler */
5126    mimg->operands[2] = Operand(lod);
5127    uint8_t& dmask = mimg->dmask;
5128    mimg->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
5129    mimg->dmask = (1 << instr->dest.ssa.num_components) - 1;
5130    mimg->da = glsl_sampler_type_is_array(type);
5131    mimg->can_reorder = true;
5132    Definition& def = mimg->definitions[0];
5133    ctx->block->instructions.emplace_back(std::move(mimg));
5134
5135    if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
5136        glsl_sampler_type_is_array(type)) {
5137
5138       assert(instr->dest.ssa.num_components == 3);
5139       Temp tmp = {ctx->program->allocateId(), v3};
5140       def = Definition(tmp);
5141       emit_split_vector(ctx, tmp, 3);
5142
5143       /* divide 3rd value by 6 by multiplying with magic number */
5144       Temp c = bld.copy(bld.def(s1), Operand((uint32_t) 0x2AAAAAAB));
5145       Temp by_6 = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), emit_extract_vector(ctx, tmp, 2, v1), c);
5146
5147       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
5148                  emit_extract_vector(ctx, tmp, 0, v1),
5149                  emit_extract_vector(ctx, tmp, 1, v1),
5150                  by_6);
5151
5152    } else if (ctx->options->chip_class == GFX9 &&
5153               glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
5154               glsl_sampler_type_is_array(type)) {
5155       assert(instr->dest.ssa.num_components == 2);
5156       def = Definition(dst);
5157       dmask = 0x5;
5158    } else {
5159       def = Definition(dst);
5160    }
5161
5162    emit_split_vector(ctx, dst, instr->dest.ssa.num_components);
5163 }
5164
5165 void visit_load_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
5166 {
5167    Builder bld(ctx->program, ctx->block);
5168    unsigned num_components = instr->num_components;
5169
5170    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5171    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5172    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
5173
5174    bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT);
5175    load_buffer(ctx, num_components, dst, rsrc, get_ssa_temp(ctx, instr->src[1].ssa), glc, false);
5176 }
5177
5178 void visit_store_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
5179 {
5180    Builder bld(ctx->program, ctx->block);
5181    Temp data = get_ssa_temp(ctx, instr->src[0].ssa);
5182    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
5183    unsigned writemask = nir_intrinsic_write_mask(instr);
5184    Temp offset = get_ssa_temp(ctx, instr->src[2].ssa);
5185
5186    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5187    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
5188
5189    bool smem = !ctx->divergent_vals[instr->src[2].ssa->index] &&
5190                ctx->options->chip_class >= GFX8;
5191    if (smem)
5192       offset = bld.as_uniform(offset);
5193    bool smem_nonfs = smem && ctx->stage != fragment_fs;
5194
5195    while (writemask) {
5196       int start, count;
5197       u_bit_scan_consecutive_range(&writemask, &start, &count);
5198       if (count == 3 && (smem || ctx->options->chip_class == GFX6)) {
5199          /* GFX6 doesn't support storing vec3, split it. */
5200          writemask |= 1u << (start + 2);
5201          count = 2;
5202       }
5203       int num_bytes = count * elem_size_bytes;
5204
5205       if (num_bytes > 16) {
5206          assert(elem_size_bytes == 8);
5207          writemask |= (((count - 2) << 1) - 1) << (start + 2);
5208          count = 2;
5209          num_bytes = 16;
5210       }
5211
5212       // TODO: check alignment of sub-dword stores
5213       // TODO: split 3 bytes. there is no store instruction for that
5214
5215       Temp write_data;
5216       if (count != instr->num_components) {
5217          emit_split_vector(ctx, data, instr->num_components);
5218          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
5219          for (int i = 0; i < count; i++) {
5220             Temp elem = emit_extract_vector(ctx, data, start + i, RegClass(data.type(), elem_size_bytes / 4));
5221             vec->operands[i] = Operand(smem_nonfs ? bld.as_uniform(elem) : elem);
5222          }
5223          write_data = bld.tmp(!smem ? RegType::vgpr : smem_nonfs ? RegType::sgpr : data.type(), count * elem_size_bytes / 4);
5224          vec->definitions[0] = Definition(write_data);
5225          ctx->block->instructions.emplace_back(std::move(vec));
5226       } else if (!smem && data.type() != RegType::vgpr) {
5227          assert(num_bytes % 4 == 0);
5228          write_data = bld.copy(bld.def(RegType::vgpr, num_bytes / 4), data);
5229       } else if (smem_nonfs && data.type() == RegType::vgpr) {
5230          assert(num_bytes % 4 == 0);
5231          write_data = bld.as_uniform(data);
5232       } else {
5233          write_data = data;
5234       }
5235
5236       aco_opcode vmem_op, smem_op;
5237       switch (num_bytes) {
5238          case 4:
5239             vmem_op = aco_opcode::buffer_store_dword;
5240             smem_op = aco_opcode::s_buffer_store_dword;
5241             break;
5242          case 8:
5243             vmem_op = aco_opcode::buffer_store_dwordx2;
5244             smem_op = aco_opcode::s_buffer_store_dwordx2;
5245             break;
5246          case 12:
5247             vmem_op = aco_opcode::buffer_store_dwordx3;
5248             smem_op = aco_opcode::last_opcode;
5249             assert(!smem && ctx->options->chip_class > GFX6);
5250             break;
5251          case 16:
5252             vmem_op = aco_opcode::buffer_store_dwordx4;
5253             smem_op = aco_opcode::s_buffer_store_dwordx4;
5254             break;
5255          default:
5256             unreachable("Store SSBO not implemented for this size.");
5257       }
5258       if (ctx->stage == fragment_fs)
5259          smem_op = aco_opcode::p_fs_buffer_store_smem;
5260
5261       if (smem) {
5262          aco_ptr<SMEM_instruction> store{create_instruction<SMEM_instruction>(smem_op, Format::SMEM, 3, 0)};
5263          store->operands[0] = Operand(rsrc);
5264          if (start) {
5265             Temp off = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
5266                                 offset, Operand(start * elem_size_bytes));
5267             store->operands[1] = Operand(off);
5268          } else {
5269             store->operands[1] = Operand(offset);
5270          }
5271          if (smem_op != aco_opcode::p_fs_buffer_store_smem)
5272             store->operands[1].setFixed(m0);
5273          store->operands[2] = Operand(write_data);
5274          store->glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
5275          store->dlc = false;
5276          store->disable_wqm = true;
5277          store->barrier = barrier_buffer;
5278          ctx->block->instructions.emplace_back(std::move(store));
5279          ctx->program->wb_smem_l1_on_end = true;
5280          if (smem_op == aco_opcode::p_fs_buffer_store_smem) {
5281             ctx->block->kind |= block_kind_needs_lowering;
5282             ctx->program->needs_exact = true;
5283          }
5284       } else {
5285          aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(vmem_op, Format::MUBUF, 4, 0)};
5286          store->operands[0] = Operand(rsrc);
5287          store->operands[1] = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
5288          store->operands[2] = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
5289          store->operands[3] = Operand(write_data);
5290          store->offset = start * elem_size_bytes;
5291          store->offen = (offset.type() == RegType::vgpr);
5292          store->glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
5293          store->dlc = false;
5294          store->disable_wqm = true;
5295          store->barrier = barrier_buffer;
5296          ctx->program->needs_exact = true;
5297          ctx->block->instructions.emplace_back(std::move(store));
5298       }
5299    }
5300 }
5301
5302 void visit_atomic_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
5303 {
5304    /* return the previous value if dest is ever used */
5305    bool return_previous = false;
5306    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
5307       return_previous = true;
5308       break;
5309    }
5310    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
5311       return_previous = true;
5312       break;
5313    }
5314
5315    Builder bld(ctx->program, ctx->block);
5316    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[2].ssa));
5317
5318    if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap)
5319       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(RegType::vgpr, data.size() * 2),
5320                         get_ssa_temp(ctx, instr->src[3].ssa), data);
5321
5322    Temp offset = get_ssa_temp(ctx, instr->src[1].ssa);
5323    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5324    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
5325
5326    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5327
5328    aco_opcode op32, op64;
5329    switch (instr->intrinsic) {
5330       case nir_intrinsic_ssbo_atomic_add:
5331          op32 = aco_opcode::buffer_atomic_add;
5332          op64 = aco_opcode::buffer_atomic_add_x2;
5333          break;
5334       case nir_intrinsic_ssbo_atomic_imin:
5335          op32 = aco_opcode::buffer_atomic_smin;
5336          op64 = aco_opcode::buffer_atomic_smin_x2;
5337          break;
5338       case nir_intrinsic_ssbo_atomic_umin:
5339          op32 = aco_opcode::buffer_atomic_umin;
5340          op64 = aco_opcode::buffer_atomic_umin_x2;
5341          break;
5342       case nir_intrinsic_ssbo_atomic_imax:
5343          op32 = aco_opcode::buffer_atomic_smax;
5344          op64 = aco_opcode::buffer_atomic_smax_x2;
5345          break;
5346       case nir_intrinsic_ssbo_atomic_umax:
5347          op32 = aco_opcode::buffer_atomic_umax;
5348          op64 = aco_opcode::buffer_atomic_umax_x2;
5349          break;
5350       case nir_intrinsic_ssbo_atomic_and:
5351          op32 = aco_opcode::buffer_atomic_and;
5352          op64 = aco_opcode::buffer_atomic_and_x2;
5353          break;
5354       case nir_intrinsic_ssbo_atomic_or:
5355          op32 = aco_opcode::buffer_atomic_or;
5356          op64 = aco_opcode::buffer_atomic_or_x2;
5357          break;
5358       case nir_intrinsic_ssbo_atomic_xor:
5359          op32 = aco_opcode::buffer_atomic_xor;
5360          op64 = aco_opcode::buffer_atomic_xor_x2;
5361          break;
5362       case nir_intrinsic_ssbo_atomic_exchange:
5363          op32 = aco_opcode::buffer_atomic_swap;
5364          op64 = aco_opcode::buffer_atomic_swap_x2;
5365          break;
5366       case nir_intrinsic_ssbo_atomic_comp_swap:
5367          op32 = aco_opcode::buffer_atomic_cmpswap;
5368          op64 = aco_opcode::buffer_atomic_cmpswap_x2;
5369          break;
5370       default:
5371          unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
5372    }
5373    aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
5374    aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, return_previous ? 1 : 0)};
5375    mubuf->operands[0] = Operand(rsrc);
5376    mubuf->operands[1] = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
5377    mubuf->operands[2] = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
5378    mubuf->operands[3] = Operand(data);
5379    if (return_previous)
5380       mubuf->definitions[0] = Definition(dst);
5381    mubuf->offset = 0;
5382    mubuf->offen = (offset.type() == RegType::vgpr);
5383    mubuf->glc = return_previous;
5384    mubuf->dlc = false; /* Not needed for atomics */
5385    mubuf->disable_wqm = true;
5386    mubuf->barrier = barrier_buffer;
5387    ctx->program->needs_exact = true;
5388    ctx->block->instructions.emplace_back(std::move(mubuf));
5389 }
5390
5391 void visit_get_buffer_size(isel_context *ctx, nir_intrinsic_instr *instr) {
5392
5393    Temp index = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5394    Builder bld(ctx->program, ctx->block);
5395    Temp desc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), index, Operand(0u));
5396    get_buffer_size(ctx, desc, get_ssa_temp(ctx, &instr->dest.ssa), false);
5397 }
5398
5399 Temp get_gfx6_global_rsrc(Builder& bld, Temp addr)
5400 {
5401    uint32_t rsrc_conf = S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5402                         S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
5403
5404    if (addr.type() == RegType::vgpr)
5405       return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf));
5406    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), addr, Operand(-1u), Operand(rsrc_conf));
5407 }
5408
5409 void visit_load_global(isel_context *ctx, nir_intrinsic_instr *instr)
5410 {
5411    Builder bld(ctx->program, ctx->block);
5412    unsigned num_components = instr->num_components;
5413    unsigned num_bytes = num_components * instr->dest.ssa.bit_size / 8;
5414
5415    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5416    Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
5417
5418    bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT);
5419    bool dlc = glc && ctx->options->chip_class >= GFX10;
5420    aco_opcode op;
5421    if (dst.type() == RegType::vgpr || (glc && ctx->options->chip_class < GFX8)) {
5422       bool global = ctx->options->chip_class >= GFX9;
5423
5424       if (ctx->options->chip_class >= GFX7) {
5425          aco_opcode op;
5426          switch (num_bytes) {
5427          case 4:
5428             op = global ? aco_opcode::global_load_dword : aco_opcode::flat_load_dword;
5429             break;
5430          case 8:
5431             op = global ? aco_opcode::global_load_dwordx2 : aco_opcode::flat_load_dwordx2;
5432             break;
5433          case 12:
5434             op = global ? aco_opcode::global_load_dwordx3 : aco_opcode::flat_load_dwordx3;
5435             break;
5436          case 16:
5437             op = global ? aco_opcode::global_load_dwordx4 : aco_opcode::flat_load_dwordx4;
5438             break;
5439          default:
5440             unreachable("load_global not implemented for this size.");
5441          }
5442
5443          aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 2, 1)};
5444          flat->operands[0] = Operand(addr);
5445          flat->operands[1] = Operand(s1);
5446          flat->glc = glc;
5447          flat->dlc = dlc;
5448          flat->barrier = barrier_buffer;
5449
5450          if (dst.type() == RegType::sgpr) {
5451             Temp vec = bld.tmp(RegType::vgpr, dst.size());
5452             flat->definitions[0] = Definition(vec);
5453             ctx->block->instructions.emplace_back(std::move(flat));
5454             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec);
5455          } else {
5456             flat->definitions[0] = Definition(dst);
5457             ctx->block->instructions.emplace_back(std::move(flat));
5458          }
5459          emit_split_vector(ctx, dst, num_components);
5460       } else {
5461          assert(ctx->options->chip_class == GFX6);
5462
5463          /* GFX6 doesn't support loading vec3, expand to vec4. */
5464          num_bytes = num_bytes == 12 ? 16 : num_bytes;
5465
5466          aco_opcode op;
5467          switch (num_bytes) {
5468          case 4:
5469             op = aco_opcode::buffer_load_dword;
5470             break;
5471          case 8:
5472             op = aco_opcode::buffer_load_dwordx2;
5473             break;
5474          case 16:
5475             op = aco_opcode::buffer_load_dwordx4;
5476             break;
5477          default:
5478             unreachable("load_global not implemented for this size.");
5479          }
5480
5481          Temp rsrc = get_gfx6_global_rsrc(bld, addr);
5482
5483          aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
5484          mubuf->operands[0] = Operand(rsrc);
5485          mubuf->operands[1] = addr.type() == RegType::vgpr ? Operand(addr) : Operand(v1);
5486          mubuf->operands[2] = Operand(0u);
5487          mubuf->glc = glc;
5488          mubuf->dlc = false;
5489          mubuf->offset = 0;
5490          mubuf->addr64 = addr.type() == RegType::vgpr;
5491          mubuf->disable_wqm = false;
5492          mubuf->barrier = barrier_buffer;
5493          aco_ptr<Instruction> instr = std::move(mubuf);
5494
5495          /* expand vector */
5496          if (dst.size() == 3) {
5497             Temp vec = bld.tmp(v4);
5498             instr->definitions[0] = Definition(vec);
5499             bld.insert(std::move(instr));
5500             emit_split_vector(ctx, vec, 4);
5501
5502             instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, 3, 1));
5503             instr->operands[0] = Operand(emit_extract_vector(ctx, vec, 0, v1));
5504             instr->operands[1] = Operand(emit_extract_vector(ctx, vec, 1, v1));
5505             instr->operands[2] = Operand(emit_extract_vector(ctx, vec, 2, v1));
5506          }
5507
5508          if (dst.type() == RegType::sgpr) {
5509             Temp vec = bld.tmp(RegType::vgpr, dst.size());
5510             instr->definitions[0] = Definition(vec);
5511             bld.insert(std::move(instr));
5512             expand_vector(ctx, vec, dst, num_components, (1 << num_components) - 1);
5513             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec);
5514          } else {
5515             instr->definitions[0] = Definition(dst);
5516             bld.insert(std::move(instr));
5517             emit_split_vector(ctx, dst, num_components);
5518          }
5519       }
5520    } else {
5521       switch (num_bytes) {
5522          case 4:
5523             op = aco_opcode::s_load_dword;
5524             break;
5525          case 8:
5526             op = aco_opcode::s_load_dwordx2;
5527             break;
5528          case 12:
5529          case 16:
5530             op = aco_opcode::s_load_dwordx4;
5531             break;
5532          default:
5533             unreachable("load_global not implemented for this size.");
5534       }
5535       aco_ptr<SMEM_instruction> load{create_instruction<SMEM_instruction>(op, Format::SMEM, 2, 1)};
5536       load->operands[0] = Operand(addr);
5537       load->operands[1] = Operand(0u);
5538       load->definitions[0] = Definition(dst);
5539       load->glc = glc;
5540       load->dlc = dlc;
5541       load->barrier = barrier_buffer;
5542       assert(ctx->options->chip_class >= GFX8 || !glc);
5543
5544       if (dst.size() == 3) {
5545          /* trim vector */
5546          Temp vec = bld.tmp(s4);
5547          load->definitions[0] = Definition(vec);
5548          ctx->block->instructions.emplace_back(std::move(load));
5549          emit_split_vector(ctx, vec, 4);
5550
5551          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
5552                     emit_extract_vector(ctx, vec, 0, s1),
5553                     emit_extract_vector(ctx, vec, 1, s1),
5554                     emit_extract_vector(ctx, vec, 2, s1));
5555       } else {
5556          ctx->block->instructions.emplace_back(std::move(load));
5557       }
5558    }
5559 }
5560
5561 void visit_store_global(isel_context *ctx, nir_intrinsic_instr *instr)
5562 {
5563    Builder bld(ctx->program, ctx->block);
5564    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
5565
5566    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5567    Temp addr = get_ssa_temp(ctx, instr->src[1].ssa);
5568
5569    if (ctx->options->chip_class >= GFX7)
5570       addr = as_vgpr(ctx, addr);
5571
5572    unsigned writemask = nir_intrinsic_write_mask(instr);
5573    while (writemask) {
5574       int start, count;
5575       u_bit_scan_consecutive_range(&writemask, &start, &count);
5576       if (count == 3 && ctx->options->chip_class == GFX6) {
5577          /* GFX6 doesn't support storing vec3, split it. */
5578          writemask |= 1u << (start + 2);
5579          count = 2;
5580       }
5581       unsigned num_bytes = count * elem_size_bytes;
5582
5583       Temp write_data = data;
5584       if (count != instr->num_components) {
5585          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
5586          for (int i = 0; i < count; i++)
5587             vec->operands[i] = Operand(emit_extract_vector(ctx, data, start + i, v1));
5588          write_data = bld.tmp(RegType::vgpr, count);
5589          vec->definitions[0] = Definition(write_data);
5590          ctx->block->instructions.emplace_back(std::move(vec));
5591       }
5592
5593       bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
5594       unsigned offset = start * elem_size_bytes;
5595
5596       if (ctx->options->chip_class >= GFX7) {
5597          if (offset > 0 && ctx->options->chip_class < GFX9) {
5598             Temp addr0 = bld.tmp(v1), addr1 = bld.tmp(v1);
5599             Temp new_addr0 = bld.tmp(v1), new_addr1 = bld.tmp(v1);
5600             Temp carry = bld.tmp(bld.lm);
5601             bld.pseudo(aco_opcode::p_split_vector, Definition(addr0), Definition(addr1), addr);
5602
5603             bld.vop2(aco_opcode::v_add_co_u32, Definition(new_addr0), bld.hint_vcc(Definition(carry)),
5604                      Operand(offset), addr0);
5605             bld.vop2(aco_opcode::v_addc_co_u32, Definition(new_addr1), bld.def(bld.lm),
5606                      Operand(0u), addr1,
5607                      carry).def(1).setHint(vcc);
5608
5609             addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), new_addr0, new_addr1);
5610
5611             offset = 0;
5612          }
5613
5614          bool global = ctx->options->chip_class >= GFX9;
5615          aco_opcode op;
5616          switch (num_bytes) {
5617          case 4:
5618             op = global ? aco_opcode::global_store_dword : aco_opcode::flat_store_dword;
5619             break;
5620          case 8:
5621             op = global ? aco_opcode::global_store_dwordx2 : aco_opcode::flat_store_dwordx2;
5622             break;
5623          case 12:
5624             op = global ? aco_opcode::global_store_dwordx3 : aco_opcode::flat_store_dwordx3;
5625             break;
5626          case 16:
5627             op = global ? aco_opcode::global_store_dwordx4 : aco_opcode::flat_store_dwordx4;
5628             break;
5629          default:
5630             unreachable("store_global not implemented for this size.");
5631          }
5632
5633          aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 3, 0)};
5634          flat->operands[0] = Operand(addr);
5635          flat->operands[1] = Operand(s1);
5636          flat->operands[2] = Operand(data);
5637          flat->glc = glc;
5638          flat->dlc = false;
5639          flat->offset = offset;
5640          flat->disable_wqm = true;
5641          flat->barrier = barrier_buffer;
5642          ctx->program->needs_exact = true;
5643          ctx->block->instructions.emplace_back(std::move(flat));
5644       } else {
5645          assert(ctx->options->chip_class == GFX6);
5646
5647          aco_opcode op;
5648          switch (num_bytes) {
5649          case 4:
5650             op = aco_opcode::buffer_store_dword;
5651             break;
5652          case 8:
5653             op = aco_opcode::buffer_store_dwordx2;
5654             break;
5655          case 16:
5656             op = aco_opcode::buffer_store_dwordx4;
5657             break;
5658          default:
5659             unreachable("store_global not implemented for this size.");
5660          }
5661
5662          Temp rsrc = get_gfx6_global_rsrc(bld, addr);
5663
5664          aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, 0)};
5665          mubuf->operands[0] = Operand(rsrc);
5666          mubuf->operands[1] = addr.type() == RegType::vgpr ? Operand(addr) : Operand(v1);
5667          mubuf->operands[2] = Operand(0u);
5668          mubuf->operands[3] = Operand(write_data);
5669          mubuf->glc = glc;
5670          mubuf->dlc = false;
5671          mubuf->offset = offset;
5672          mubuf->addr64 = addr.type() == RegType::vgpr;
5673          mubuf->disable_wqm = true;
5674          mubuf->barrier = barrier_buffer;
5675          ctx->program->needs_exact = true;
5676          ctx->block->instructions.emplace_back(std::move(mubuf));
5677       }
5678    }
5679 }
5680
5681 void visit_global_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
5682 {
5683    /* return the previous value if dest is ever used */
5684    bool return_previous = false;
5685    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
5686       return_previous = true;
5687       break;
5688    }
5689    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
5690       return_previous = true;
5691       break;
5692    }
5693
5694    Builder bld(ctx->program, ctx->block);
5695    Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
5696    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5697
5698    if (ctx->options->chip_class >= GFX7)
5699       addr = as_vgpr(ctx, addr);
5700
5701    if (instr->intrinsic == nir_intrinsic_global_atomic_comp_swap)
5702       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(RegType::vgpr, data.size() * 2),
5703                         get_ssa_temp(ctx, instr->src[2].ssa), data);
5704
5705    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5706
5707    aco_opcode op32, op64;
5708
5709    if (ctx->options->chip_class >= GFX7) {
5710       bool global = ctx->options->chip_class >= GFX9;
5711       switch (instr->intrinsic) {
5712          case nir_intrinsic_global_atomic_add:
5713             op32 = global ? aco_opcode::global_atomic_add : aco_opcode::flat_atomic_add;
5714             op64 = global ? aco_opcode::global_atomic_add_x2 : aco_opcode::flat_atomic_add_x2;
5715             break;
5716          case nir_intrinsic_global_atomic_imin:
5717             op32 = global ? aco_opcode::global_atomic_smin : aco_opcode::flat_atomic_smin;
5718             op64 = global ? aco_opcode::global_atomic_smin_x2 : aco_opcode::flat_atomic_smin_x2;
5719             break;
5720          case nir_intrinsic_global_atomic_umin:
5721             op32 = global ? aco_opcode::global_atomic_umin : aco_opcode::flat_atomic_umin;
5722             op64 = global ? aco_opcode::global_atomic_umin_x2 : aco_opcode::flat_atomic_umin_x2;
5723             break;
5724          case nir_intrinsic_global_atomic_imax:
5725             op32 = global ? aco_opcode::global_atomic_smax : aco_opcode::flat_atomic_smax;
5726             op64 = global ? aco_opcode::global_atomic_smax_x2 : aco_opcode::flat_atomic_smax_x2;
5727             break;
5728          case nir_intrinsic_global_atomic_umax:
5729             op32 = global ? aco_opcode::global_atomic_umax : aco_opcode::flat_atomic_umax;
5730             op64 = global ? aco_opcode::global_atomic_umax_x2 : aco_opcode::flat_atomic_umax_x2;
5731             break;
5732          case nir_intrinsic_global_atomic_and:
5733             op32 = global ? aco_opcode::global_atomic_and : aco_opcode::flat_atomic_and;
5734             op64 = global ? aco_opcode::global_atomic_and_x2 : aco_opcode::flat_atomic_and_x2;
5735             break;
5736          case nir_intrinsic_global_atomic_or:
5737             op32 = global ? aco_opcode::global_atomic_or : aco_opcode::flat_atomic_or;
5738             op64 = global ? aco_opcode::global_atomic_or_x2 : aco_opcode::flat_atomic_or_x2;
5739             break;
5740          case nir_intrinsic_global_atomic_xor:
5741             op32 = global ? aco_opcode::global_atomic_xor : aco_opcode::flat_atomic_xor;
5742             op64 = global ? aco_opcode::global_atomic_xor_x2 : aco_opcode::flat_atomic_xor_x2;
5743             break;
5744          case nir_intrinsic_global_atomic_exchange:
5745             op32 = global ? aco_opcode::global_atomic_swap : aco_opcode::flat_atomic_swap;
5746             op64 = global ? aco_opcode::global_atomic_swap_x2 : aco_opcode::flat_atomic_swap_x2;
5747             break;
5748          case nir_intrinsic_global_atomic_comp_swap:
5749             op32 = global ? aco_opcode::global_atomic_cmpswap : aco_opcode::flat_atomic_cmpswap;
5750             op64 = global ? aco_opcode::global_atomic_cmpswap_x2 : aco_opcode::flat_atomic_cmpswap_x2;
5751             break;
5752          default:
5753             unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
5754       }
5755
5756       aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
5757       aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 3, return_previous ? 1 : 0)};
5758       flat->operands[0] = Operand(addr);
5759       flat->operands[1] = Operand(s1);
5760       flat->operands[2] = Operand(data);
5761       if (return_previous)
5762          flat->definitions[0] = Definition(dst);
5763       flat->glc = return_previous;
5764       flat->dlc = false; /* Not needed for atomics */
5765       flat->offset = 0;
5766       flat->disable_wqm = true;
5767       flat->barrier = barrier_buffer;
5768       ctx->program->needs_exact = true;
5769       ctx->block->instructions.emplace_back(std::move(flat));
5770    } else {
5771       assert(ctx->options->chip_class == GFX6);
5772
5773       switch (instr->intrinsic) {
5774          case nir_intrinsic_global_atomic_add:
5775             op32 = aco_opcode::buffer_atomic_add;
5776             op64 = aco_opcode::buffer_atomic_add_x2;
5777             break;
5778          case nir_intrinsic_global_atomic_imin:
5779             op32 = aco_opcode::buffer_atomic_smin;
5780             op64 = aco_opcode::buffer_atomic_smin_x2;
5781             break;
5782          case nir_intrinsic_global_atomic_umin:
5783             op32 = aco_opcode::buffer_atomic_umin;
5784             op64 = aco_opcode::buffer_atomic_umin_x2;
5785             break;
5786          case nir_intrinsic_global_atomic_imax:
5787             op32 = aco_opcode::buffer_atomic_smax;
5788             op64 = aco_opcode::buffer_atomic_smax_x2;
5789             break;
5790          case nir_intrinsic_global_atomic_umax:
5791             op32 = aco_opcode::buffer_atomic_umax;
5792             op64 = aco_opcode::buffer_atomic_umax_x2;
5793             break;
5794          case nir_intrinsic_global_atomic_and:
5795             op32 = aco_opcode::buffer_atomic_and;
5796             op64 = aco_opcode::buffer_atomic_and_x2;
5797             break;
5798          case nir_intrinsic_global_atomic_or:
5799             op32 = aco_opcode::buffer_atomic_or;
5800             op64 = aco_opcode::buffer_atomic_or_x2;
5801             break;
5802          case nir_intrinsic_global_atomic_xor:
5803             op32 = aco_opcode::buffer_atomic_xor;
5804             op64 = aco_opcode::buffer_atomic_xor_x2;
5805             break;
5806          case nir_intrinsic_global_atomic_exchange:
5807             op32 = aco_opcode::buffer_atomic_swap;
5808             op64 = aco_opcode::buffer_atomic_swap_x2;
5809             break;
5810          case nir_intrinsic_global_atomic_comp_swap:
5811             op32 = aco_opcode::buffer_atomic_cmpswap;
5812             op64 = aco_opcode::buffer_atomic_cmpswap_x2;
5813             break;
5814          default:
5815             unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
5816       }
5817
5818       Temp rsrc = get_gfx6_global_rsrc(bld, addr);
5819
5820       aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
5821
5822       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, return_previous ? 1 : 0)};
5823       mubuf->operands[0] = Operand(rsrc);
5824       mubuf->operands[1] = addr.type() == RegType::vgpr ? Operand(addr) : Operand(v1);
5825       mubuf->operands[2] = Operand(0u);
5826       mubuf->operands[3] = Operand(data);
5827       if (return_previous)
5828          mubuf->definitions[0] = Definition(dst);
5829       mubuf->glc = return_previous;
5830       mubuf->dlc = false;
5831       mubuf->offset = 0;
5832       mubuf->addr64 = addr.type() == RegType::vgpr;
5833       mubuf->disable_wqm = true;
5834       mubuf->barrier = barrier_buffer;
5835       ctx->program->needs_exact = true;
5836       ctx->block->instructions.emplace_back(std::move(mubuf));
5837    }
5838 }
5839
5840 void emit_memory_barrier(isel_context *ctx, nir_intrinsic_instr *instr) {
5841    Builder bld(ctx->program, ctx->block);
5842    switch(instr->intrinsic) {
5843       case nir_intrinsic_group_memory_barrier:
5844       case nir_intrinsic_memory_barrier:
5845          bld.barrier(aco_opcode::p_memory_barrier_common);
5846          break;
5847       case nir_intrinsic_memory_barrier_buffer:
5848          bld.barrier(aco_opcode::p_memory_barrier_buffer);
5849          break;
5850       case nir_intrinsic_memory_barrier_image:
5851          bld.barrier(aco_opcode::p_memory_barrier_image);
5852          break;
5853       case nir_intrinsic_memory_barrier_tcs_patch:
5854       case nir_intrinsic_memory_barrier_shared:
5855          bld.barrier(aco_opcode::p_memory_barrier_shared);
5856          break;
5857       default:
5858          unreachable("Unimplemented memory barrier intrinsic");
5859          break;
5860    }
5861 }
5862
5863 void visit_load_shared(isel_context *ctx, nir_intrinsic_instr *instr)
5864 {
5865    // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
5866    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5867    assert(instr->dest.ssa.bit_size >= 32 && "Bitsize not supported in load_shared.");
5868    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5869    Builder bld(ctx->program, ctx->block);
5870
5871    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
5872    unsigned align = nir_intrinsic_align_mul(instr) ? nir_intrinsic_align(instr) : elem_size_bytes;
5873    load_lds(ctx, elem_size_bytes, dst, address, nir_intrinsic_base(instr), align);
5874 }
5875
5876 void visit_store_shared(isel_context *ctx, nir_intrinsic_instr *instr)
5877 {
5878    unsigned writemask = nir_intrinsic_write_mask(instr);
5879    Temp data = get_ssa_temp(ctx, instr->src[0].ssa);
5880    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5881    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
5882    assert(elem_size_bytes >= 4 && "Only 32bit & 64bit store_shared currently supported.");
5883
5884    unsigned align = nir_intrinsic_align_mul(instr) ? nir_intrinsic_align(instr) : elem_size_bytes;
5885    store_lds(ctx, elem_size_bytes, data, writemask, address, nir_intrinsic_base(instr), align);
5886 }
5887
5888 void visit_shared_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
5889 {
5890    unsigned offset = nir_intrinsic_base(instr);
5891    Operand m = load_lds_size_m0(ctx);
5892    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5893    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5894
5895    unsigned num_operands = 3;
5896    aco_opcode op32, op64, op32_rtn, op64_rtn;
5897    switch(instr->intrinsic) {
5898       case nir_intrinsic_shared_atomic_add:
5899          op32 = aco_opcode::ds_add_u32;
5900          op64 = aco_opcode::ds_add_u64;
5901          op32_rtn = aco_opcode::ds_add_rtn_u32;
5902          op64_rtn = aco_opcode::ds_add_rtn_u64;
5903          break;
5904       case nir_intrinsic_shared_atomic_imin:
5905          op32 = aco_opcode::ds_min_i32;
5906          op64 = aco_opcode::ds_min_i64;
5907          op32_rtn = aco_opcode::ds_min_rtn_i32;
5908          op64_rtn = aco_opcode::ds_min_rtn_i64;
5909          break;
5910       case nir_intrinsic_shared_atomic_umin:
5911          op32 = aco_opcode::ds_min_u32;
5912          op64 = aco_opcode::ds_min_u64;
5913          op32_rtn = aco_opcode::ds_min_rtn_u32;
5914          op64_rtn = aco_opcode::ds_min_rtn_u64;
5915          break;
5916       case nir_intrinsic_shared_atomic_imax:
5917          op32 = aco_opcode::ds_max_i32;
5918          op64 = aco_opcode::ds_max_i64;
5919          op32_rtn = aco_opcode::ds_max_rtn_i32;
5920          op64_rtn = aco_opcode::ds_max_rtn_i64;
5921          break;
5922       case nir_intrinsic_shared_atomic_umax:
5923          op32 = aco_opcode::ds_max_u32;
5924          op64 = aco_opcode::ds_max_u64;
5925          op32_rtn = aco_opcode::ds_max_rtn_u32;
5926          op64_rtn = aco_opcode::ds_max_rtn_u64;
5927          break;
5928       case nir_intrinsic_shared_atomic_and:
5929          op32 = aco_opcode::ds_and_b32;
5930          op64 = aco_opcode::ds_and_b64;
5931          op32_rtn = aco_opcode::ds_and_rtn_b32;
5932          op64_rtn = aco_opcode::ds_and_rtn_b64;
5933          break;
5934       case nir_intrinsic_shared_atomic_or:
5935          op32 = aco_opcode::ds_or_b32;
5936          op64 = aco_opcode::ds_or_b64;
5937          op32_rtn = aco_opcode::ds_or_rtn_b32;
5938          op64_rtn = aco_opcode::ds_or_rtn_b64;
5939          break;
5940       case nir_intrinsic_shared_atomic_xor:
5941          op32 = aco_opcode::ds_xor_b32;
5942          op64 = aco_opcode::ds_xor_b64;
5943          op32_rtn = aco_opcode::ds_xor_rtn_b32;
5944          op64_rtn = aco_opcode::ds_xor_rtn_b64;
5945          break;
5946       case nir_intrinsic_shared_atomic_exchange:
5947          op32 = aco_opcode::ds_write_b32;
5948          op64 = aco_opcode::ds_write_b64;
5949          op32_rtn = aco_opcode::ds_wrxchg_rtn_b32;
5950          op64_rtn = aco_opcode::ds_wrxchg2_rtn_b64;
5951          break;
5952       case nir_intrinsic_shared_atomic_comp_swap:
5953          op32 = aco_opcode::ds_cmpst_b32;
5954          op64 = aco_opcode::ds_cmpst_b64;
5955          op32_rtn = aco_opcode::ds_cmpst_rtn_b32;
5956          op64_rtn = aco_opcode::ds_cmpst_rtn_b64;
5957          num_operands = 4;
5958          break;
5959       default:
5960          unreachable("Unhandled shared atomic intrinsic");
5961    }
5962
5963    /* return the previous value if dest is ever used */
5964    bool return_previous = false;
5965    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
5966       return_previous = true;
5967       break;
5968    }
5969    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
5970       return_previous = true;
5971       break;
5972    }
5973
5974    aco_opcode op;
5975    if (data.size() == 1) {
5976       assert(instr->dest.ssa.bit_size == 32);
5977       op = return_previous ? op32_rtn : op32;
5978    } else {
5979       assert(instr->dest.ssa.bit_size == 64);
5980       op = return_previous ? op64_rtn : op64;
5981    }
5982
5983    if (offset > 65535) {
5984       Builder bld(ctx->program, ctx->block);
5985       address = bld.vadd32(bld.def(v1), Operand(offset), address);
5986       offset = 0;
5987    }
5988
5989    aco_ptr<DS_instruction> ds;
5990    ds.reset(create_instruction<DS_instruction>(op, Format::DS, num_operands, return_previous ? 1 : 0));
5991    ds->operands[0] = Operand(address);
5992    ds->operands[1] = Operand(data);
5993    if (num_operands == 4)
5994       ds->operands[2] = Operand(get_ssa_temp(ctx, instr->src[2].ssa));
5995    ds->operands[num_operands - 1] = m;
5996    ds->offset0 = offset;
5997    if (return_previous)
5998       ds->definitions[0] = Definition(get_ssa_temp(ctx, &instr->dest.ssa));
5999    ctx->block->instructions.emplace_back(std::move(ds));
6000 }
6001
6002 Temp get_scratch_resource(isel_context *ctx)
6003 {
6004    Builder bld(ctx->program, ctx->block);
6005    Temp scratch_addr = ctx->program->private_segment_buffer;
6006    if (ctx->stage != compute_cs)
6007       scratch_addr = bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), scratch_addr, Operand(0u));
6008
6009    uint32_t rsrc_conf = S_008F0C_ADD_TID_ENABLE(1) |
6010                         S_008F0C_INDEX_STRIDE(ctx->program->wave_size == 64 ? 3 : 2);;
6011
6012    if (ctx->program->chip_class >= GFX10) {
6013       rsrc_conf |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
6014                    S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
6015                    S_008F0C_RESOURCE_LEVEL(1);
6016    } else if (ctx->program->chip_class <= GFX7) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6017       rsrc_conf |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
6018                    S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
6019    }
6020
6021    /* older generations need element size = 16 bytes. element size removed in GFX9 */
6022    if (ctx->program->chip_class <= GFX8)
6023       rsrc_conf |= S_008F0C_ELEMENT_SIZE(3);
6024
6025    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), scratch_addr, Operand(-1u), Operand(rsrc_conf));
6026 }
6027
6028 void visit_load_scratch(isel_context *ctx, nir_intrinsic_instr *instr) {
6029    assert(instr->dest.ssa.bit_size == 32 || instr->dest.ssa.bit_size == 64);
6030    Builder bld(ctx->program, ctx->block);
6031    Temp rsrc = get_scratch_resource(ctx);
6032    Temp offset = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
6033    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6034
6035    aco_opcode op;
6036    switch (dst.size()) {
6037       case 1:
6038          op = aco_opcode::buffer_load_dword;
6039          break;
6040       case 2:
6041          op = aco_opcode::buffer_load_dwordx2;
6042          break;
6043       case 3:
6044          op = aco_opcode::buffer_load_dwordx3;
6045          break;
6046       case 4:
6047          op = aco_opcode::buffer_load_dwordx4;
6048          break;
6049       case 6:
6050       case 8: {
6051          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
6052          Temp lower = bld.mubuf(aco_opcode::buffer_load_dwordx4,
6053                                 bld.def(v4), rsrc, offset,
6054                                 ctx->program->scratch_offset, 0, true);
6055          Temp upper = bld.mubuf(dst.size() == 6 ? aco_opcode::buffer_load_dwordx2 :
6056                                                   aco_opcode::buffer_load_dwordx4,
6057                                 dst.size() == 6 ? bld.def(v2) : bld.def(v4),
6058                                 rsrc, offset, ctx->program->scratch_offset, 16, true);
6059          emit_split_vector(ctx, lower, 2);
6060          elems[0] = emit_extract_vector(ctx, lower, 0, v2);
6061          elems[1] = emit_extract_vector(ctx, lower, 1, v2);
6062          if (dst.size() == 8) {
6063             emit_split_vector(ctx, upper, 2);
6064             elems[2] = emit_extract_vector(ctx, upper, 0, v2);
6065             elems[3] = emit_extract_vector(ctx, upper, 1, v2);
6066          } else {
6067             elems[2] = upper;
6068          }
6069
6070          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector,
6071                                                                          Format::PSEUDO, dst.size() / 2, 1)};
6072          for (unsigned i = 0; i < dst.size() / 2; i++)
6073             vec->operands[i] = Operand(elems[i]);
6074          vec->definitions[0] = Definition(dst);
6075          bld.insert(std::move(vec));
6076          ctx->allocated_vec.emplace(dst.id(), elems);
6077          return;
6078       }
6079       default:
6080          unreachable("Wrong dst size for nir_intrinsic_load_scratch");
6081    }
6082
6083    bld.mubuf(op, Definition(dst), rsrc, offset, ctx->program->scratch_offset, 0, true);
6084    emit_split_vector(ctx, dst, instr->num_components);
6085 }
6086
6087 void visit_store_scratch(isel_context *ctx, nir_intrinsic_instr *instr) {
6088    assert(instr->src[0].ssa->bit_size == 32 || instr->src[0].ssa->bit_size == 64);
6089    Builder bld(ctx->program, ctx->block);
6090    Temp rsrc = get_scratch_resource(ctx);
6091    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
6092    Temp offset = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
6093
6094    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
6095    unsigned writemask = nir_intrinsic_write_mask(instr);
6096
6097    while (writemask) {
6098       int start, count;
6099       u_bit_scan_consecutive_range(&writemask, &start, &count);
6100       int num_bytes = count * elem_size_bytes;
6101
6102       if (num_bytes > 16) {
6103          assert(elem_size_bytes == 8);
6104          writemask |= (((count - 2) << 1) - 1) << (start + 2);
6105          count = 2;
6106          num_bytes = 16;
6107       }
6108
6109       // TODO: check alignment of sub-dword stores
6110       // TODO: split 3 bytes. there is no store instruction for that
6111
6112       Temp write_data;
6113       if (count != instr->num_components) {
6114          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
6115          for (int i = 0; i < count; i++) {
6116             Temp elem = emit_extract_vector(ctx, data, start + i, RegClass(RegType::vgpr, elem_size_bytes / 4));
6117             vec->operands[i] = Operand(elem);
6118          }
6119          write_data = bld.tmp(RegClass(RegType::vgpr, count * elem_size_bytes / 4));
6120          vec->definitions[0] = Definition(write_data);
6121          ctx->block->instructions.emplace_back(std::move(vec));
6122       } else {
6123          write_data = data;
6124       }
6125
6126       aco_opcode op;
6127       switch (num_bytes) {
6128          case 4:
6129             op = aco_opcode::buffer_store_dword;
6130             break;
6131          case 8:
6132             op = aco_opcode::buffer_store_dwordx2;
6133             break;
6134          case 12:
6135             op = aco_opcode::buffer_store_dwordx3;
6136             break;
6137          case 16:
6138             op = aco_opcode::buffer_store_dwordx4;
6139             break;
6140          default:
6141             unreachable("Invalid data size for nir_intrinsic_store_scratch.");
6142       }
6143
6144       bld.mubuf(op, rsrc, offset, ctx->program->scratch_offset, write_data, start * elem_size_bytes, true);
6145    }
6146 }
6147
6148 void visit_load_sample_mask_in(isel_context *ctx, nir_intrinsic_instr *instr) {
6149    uint8_t log2_ps_iter_samples;
6150    if (ctx->program->info->ps.force_persample) {
6151       log2_ps_iter_samples =
6152          util_logbase2(ctx->options->key.fs.num_samples);
6153    } else {
6154       log2_ps_iter_samples = ctx->options->key.fs.log2_ps_iter_samples;
6155    }
6156
6157    /* The bit pattern matches that used by fixed function fragment
6158     * processing. */
6159    static const unsigned ps_iter_masks[] = {
6160       0xffff, /* not used */
6161       0x5555,
6162       0x1111,
6163       0x0101,
6164       0x0001,
6165    };
6166    assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
6167
6168    Builder bld(ctx->program, ctx->block);
6169
6170    Temp sample_id = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1),
6171                              get_arg(ctx, ctx->args->ac.ancillary), Operand(8u), Operand(4u));
6172    Temp ps_iter_mask = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(ps_iter_masks[log2_ps_iter_samples]));
6173    Temp mask = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), sample_id, ps_iter_mask);
6174    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6175    bld.vop2(aco_opcode::v_and_b32, Definition(dst), mask, get_arg(ctx, ctx->args->ac.sample_coverage));
6176 }
6177
6178 void visit_emit_vertex_with_counter(isel_context *ctx, nir_intrinsic_instr *instr) {
6179    Builder bld(ctx->program, ctx->block);
6180
6181    unsigned stream = nir_intrinsic_stream_id(instr);
6182    Temp next_vertex = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
6183    next_vertex = bld.v_mul_imm(bld.def(v1), next_vertex, 4u);
6184    nir_const_value *next_vertex_cv = nir_src_as_const_value(instr->src[0]);
6185
6186    /* get GSVS ring */
6187    Temp gsvs_ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_GSVS_GS * 16u));
6188
6189    unsigned num_components =
6190       ctx->program->info->gs.num_stream_output_components[stream];
6191    assert(num_components);
6192
6193    unsigned stride = 4u * num_components * ctx->shader->info.gs.vertices_out;
6194    unsigned stream_offset = 0;
6195    for (unsigned i = 0; i < stream; i++) {
6196       unsigned prev_stride = 4u * ctx->program->info->gs.num_stream_output_components[i] * ctx->shader->info.gs.vertices_out;
6197       stream_offset += prev_stride * ctx->program->wave_size;
6198    }
6199
6200    /* Limit on the stride field for <= GFX7. */
6201    assert(stride < (1 << 14));
6202
6203    Temp gsvs_dwords[4];
6204    for (unsigned i = 0; i < 4; i++)
6205       gsvs_dwords[i] = bld.tmp(s1);
6206    bld.pseudo(aco_opcode::p_split_vector,
6207               Definition(gsvs_dwords[0]),
6208               Definition(gsvs_dwords[1]),
6209               Definition(gsvs_dwords[2]),
6210               Definition(gsvs_dwords[3]),
6211               gsvs_ring);
6212
6213    if (stream_offset) {
6214       Temp stream_offset_tmp = bld.copy(bld.def(s1), Operand(stream_offset));
6215
6216       Temp carry = bld.tmp(s1);
6217       gsvs_dwords[0] = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), gsvs_dwords[0], stream_offset_tmp);
6218       gsvs_dwords[1] = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), gsvs_dwords[1], Operand(0u), bld.scc(carry));
6219    }
6220
6221    gsvs_dwords[1] = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), gsvs_dwords[1], Operand(S_008F04_STRIDE(stride)));
6222    gsvs_dwords[2] = bld.copy(bld.def(s1), Operand((uint32_t)ctx->program->wave_size));
6223
6224    gsvs_ring = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
6225                           gsvs_dwords[0], gsvs_dwords[1], gsvs_dwords[2], gsvs_dwords[3]);
6226
6227    unsigned offset = 0;
6228    for (unsigned i = 0; i <= VARYING_SLOT_VAR31; i++) {
6229       if (ctx->program->info->gs.output_streams[i] != stream)
6230          continue;
6231
6232       for (unsigned j = 0; j < 4; j++) {
6233          if (!(ctx->program->info->gs.output_usage_mask[i] & (1 << j)))
6234             continue;
6235
6236          if (ctx->outputs.mask[i] & (1 << j)) {
6237             Operand vaddr_offset = next_vertex_cv ? Operand(v1) : Operand(next_vertex);
6238             unsigned const_offset = (offset + (next_vertex_cv ? next_vertex_cv->u32 : 0u)) * 4u;
6239             if (const_offset >= 4096u) {
6240                if (vaddr_offset.isUndefined())
6241                   vaddr_offset = bld.copy(bld.def(v1), Operand(const_offset / 4096u * 4096u));
6242                else
6243                   vaddr_offset = bld.vadd32(bld.def(v1), Operand(const_offset / 4096u * 4096u), vaddr_offset);
6244                const_offset %= 4096u;
6245             }
6246
6247             aco_ptr<MTBUF_instruction> mtbuf{create_instruction<MTBUF_instruction>(aco_opcode::tbuffer_store_format_x, Format::MTBUF, 4, 0)};
6248             mtbuf->operands[0] = Operand(gsvs_ring);
6249             mtbuf->operands[1] = vaddr_offset;
6250             mtbuf->operands[2] = Operand(get_arg(ctx, ctx->args->gs2vs_offset));
6251             mtbuf->operands[3] = Operand(ctx->outputs.outputs[i][j]);
6252             mtbuf->offen = !vaddr_offset.isUndefined();
6253             mtbuf->dfmt = V_008F0C_BUF_DATA_FORMAT_32;
6254             mtbuf->nfmt = V_008F0C_BUF_NUM_FORMAT_UINT;
6255             mtbuf->offset = const_offset;
6256             mtbuf->glc = true;
6257             mtbuf->slc = true;
6258             mtbuf->barrier = barrier_gs_data;
6259             mtbuf->can_reorder = true;
6260             bld.insert(std::move(mtbuf));
6261          }
6262
6263          offset += ctx->shader->info.gs.vertices_out;
6264       }
6265
6266       /* outputs for the next vertex are undefined and keeping them around can
6267        * create invalid IR with control flow */
6268       ctx->outputs.mask[i] = 0;
6269    }
6270
6271    bld.sopp(aco_opcode::s_sendmsg, bld.m0(ctx->gs_wave_id), -1, sendmsg_gs(false, true, stream));
6272 }
6273
6274 Temp emit_boolean_reduce(isel_context *ctx, nir_op op, unsigned cluster_size, Temp src)
6275 {
6276    Builder bld(ctx->program, ctx->block);
6277
6278    if (cluster_size == 1) {
6279       return src;
6280    } if (op == nir_op_iand && cluster_size == 4) {
6281       //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6282       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src);
6283       return bld.sop1(Builder::s_not, bld.def(bld.lm), bld.def(s1, scc),
6284                       bld.sop1(Builder::s_wqm, bld.def(bld.lm), bld.def(s1, scc), tmp));
6285    } else if (op == nir_op_ior && cluster_size == 4) {
6286       //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6287       return bld.sop1(Builder::s_wqm, bld.def(bld.lm), bld.def(s1, scc),
6288                       bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm)));
6289    } else if (op == nir_op_iand && cluster_size == ctx->program->wave_size) {
6290       //subgroupAnd(val) -> (exec & ~val) == 0
6291       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src).def(1).getTemp();
6292       Temp cond = bool_to_vector_condition(ctx, emit_wqm(ctx, tmp));
6293       return bld.sop1(Builder::s_not, bld.def(bld.lm), bld.def(s1, scc), cond);
6294    } else if (op == nir_op_ior && cluster_size == ctx->program->wave_size) {
6295       //subgroupOr(val) -> (val & exec) != 0
6296       Temp tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm)).def(1).getTemp();
6297       return bool_to_vector_condition(ctx, tmp);
6298    } else if (op == nir_op_ixor && cluster_size == ctx->program->wave_size) {
6299       //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6300       Temp tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
6301       tmp = bld.sop1(Builder::s_bcnt1_i32, bld.def(s1), bld.def(s1, scc), tmp);
6302       tmp = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), tmp, Operand(1u)).def(1).getTemp();
6303       return bool_to_vector_condition(ctx, tmp);
6304    } else {
6305       //subgroupClustered{And,Or,Xor}(val, n) ->
6306       //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ;  just v_mbcnt_lo_u32_b32 on wave32
6307       //cluster_offset = ~(n - 1) & lane_id
6308       //cluster_mask = ((1 << n) - 1)
6309       //subgroupClusteredAnd():
6310       //   return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6311       //subgroupClusteredOr():
6312       //   return ((val & exec) >> cluster_offset) & cluster_mask != 0
6313       //subgroupClusteredXor():
6314       //   return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6315       Temp lane_id = emit_mbcnt(ctx, bld.def(v1));
6316       Temp cluster_offset = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(~uint32_t(cluster_size - 1)), lane_id);
6317
6318       Temp tmp;
6319       if (op == nir_op_iand)
6320          tmp = bld.sop2(Builder::s_orn2, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
6321       else
6322          tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
6323
6324       uint32_t cluster_mask = cluster_size == 32 ? -1 : (1u << cluster_size) - 1u;
6325
6326       if (ctx->program->chip_class <= GFX7)
6327          tmp = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), tmp, cluster_offset);
6328       else if (ctx->program->wave_size == 64)
6329          tmp = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), cluster_offset, tmp);
6330       else
6331          tmp = bld.vop2_e64(aco_opcode::v_lshrrev_b32, bld.def(v1), cluster_offset, tmp);
6332       tmp = emit_extract_vector(ctx, tmp, 0, v1);
6333       if (cluster_mask != 0xffffffff)
6334          tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(cluster_mask), tmp);
6335
6336       Definition cmp_def = Definition();
6337       if (op == nir_op_iand) {
6338          cmp_def = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm), Operand(cluster_mask), tmp).def(0);
6339       } else if (op == nir_op_ior) {
6340          cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp).def(0);
6341       } else if (op == nir_op_ixor) {
6342          tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u),
6343                         bld.vop3(aco_opcode::v_bcnt_u32_b32, bld.def(v1), tmp, Operand(0u)));
6344          cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp).def(0);
6345       }
6346       cmp_def.setHint(vcc);
6347       return cmp_def.getTemp();
6348    }
6349 }
6350
6351 Temp emit_boolean_exclusive_scan(isel_context *ctx, nir_op op, Temp src)
6352 {
6353    Builder bld(ctx->program, ctx->block);
6354
6355    //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
6356    //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
6357    //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
6358    Temp tmp;
6359    if (op == nir_op_iand)
6360       tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src);
6361    else
6362       tmp = bld.sop2(Builder::s_and, bld.def(s2), bld.def(s1, scc), src, Operand(exec, bld.lm));
6363
6364    Builder::Result lohi = bld.pseudo(aco_opcode::p_split_vector, bld.def(s1), bld.def(s1), tmp);
6365    Temp lo = lohi.def(0).getTemp();
6366    Temp hi = lohi.def(1).getTemp();
6367    Temp mbcnt = emit_mbcnt(ctx, bld.def(v1), Operand(lo), Operand(hi));
6368
6369    Definition cmp_def = Definition();
6370    if (op == nir_op_iand)
6371       cmp_def = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm), Operand(0u), mbcnt).def(0);
6372    else if (op == nir_op_ior)
6373       cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), mbcnt).def(0);
6374    else if (op == nir_op_ixor)
6375       cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u),
6376                          bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u), mbcnt)).def(0);
6377    cmp_def.setHint(vcc);
6378    return cmp_def.getTemp();
6379 }
6380
6381 Temp emit_boolean_inclusive_scan(isel_context *ctx, nir_op op, Temp src)
6382 {
6383    Builder bld(ctx->program, ctx->block);
6384
6385    //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
6386    //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
6387    //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
6388    Temp tmp = emit_boolean_exclusive_scan(ctx, op, src);
6389    if (op == nir_op_iand)
6390       return bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
6391    else if (op == nir_op_ior)
6392       return bld.sop2(Builder::s_or, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
6393    else if (op == nir_op_ixor)
6394       return bld.sop2(Builder::s_xor, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
6395
6396    assert(false);
6397    return Temp();
6398 }
6399
6400 void emit_uniform_subgroup(isel_context *ctx, nir_intrinsic_instr *instr, Temp src)
6401 {
6402    Builder bld(ctx->program, ctx->block);
6403    Definition dst(get_ssa_temp(ctx, &instr->dest.ssa));
6404    if (src.regClass().type() == RegType::vgpr) {
6405       bld.pseudo(aco_opcode::p_as_uniform, dst, src);
6406    } else if (src.regClass() == s1) {
6407       bld.sop1(aco_opcode::s_mov_b32, dst, src);
6408    } else if (src.regClass() == s2) {
6409       bld.sop1(aco_opcode::s_mov_b64, dst, src);
6410    } else {
6411       fprintf(stderr, "Unimplemented NIR instr bit size: ");
6412       nir_print_instr(&instr->instr, stderr);
6413       fprintf(stderr, "\n");
6414    }
6415 }
6416
6417 void emit_interp_center(isel_context *ctx, Temp dst, Temp pos1, Temp pos2)
6418 {
6419    Builder bld(ctx->program, ctx->block);
6420    Temp persp_center = get_arg(ctx, ctx->args->ac.persp_center);
6421    Temp p1 = emit_extract_vector(ctx, persp_center, 0, v1);
6422    Temp p2 = emit_extract_vector(ctx, persp_center, 1, v1);
6423
6424    Temp ddx_1, ddx_2, ddy_1, ddy_2;
6425    uint32_t dpp_ctrl0 = dpp_quad_perm(0, 0, 0, 0);
6426    uint32_t dpp_ctrl1 = dpp_quad_perm(1, 1, 1, 1);
6427    uint32_t dpp_ctrl2 = dpp_quad_perm(2, 2, 2, 2);
6428
6429    /* Build DD X/Y */
6430    if (ctx->program->chip_class >= GFX8) {
6431       Temp tl_1 = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), p1, dpp_ctrl0);
6432       ddx_1 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p1, tl_1, dpp_ctrl1);
6433       ddy_1 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p1, tl_1, dpp_ctrl2);
6434       Temp tl_2 = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), p2, dpp_ctrl0);
6435       ddx_2 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p2, tl_2, dpp_ctrl1);
6436       ddy_2 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p2, tl_2, dpp_ctrl2);
6437    } else {
6438       Temp tl_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl0);
6439       ddx_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl1);
6440       ddx_1 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddx_1, tl_1);
6441       ddx_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl2);
6442       ddx_2 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddx_2, tl_1);
6443       Temp tl_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl0);
6444       ddy_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl1);
6445       ddy_1 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddy_1, tl_2);
6446       ddy_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl2);
6447       ddy_2 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddy_2, tl_2);
6448    }
6449
6450    /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
6451    Temp tmp1 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddx_1, pos1, p1);
6452    Temp tmp2 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddx_2, pos1, p2);
6453    tmp1 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddy_1, pos2, tmp1);
6454    tmp2 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddy_2, pos2, tmp2);
6455    Temp wqm1 = bld.tmp(v1);
6456    emit_wqm(ctx, tmp1, wqm1, true);
6457    Temp wqm2 = bld.tmp(v1);
6458    emit_wqm(ctx, tmp2, wqm2, true);
6459    bld.pseudo(aco_opcode::p_create_vector, Definition(dst), wqm1, wqm2);
6460    return;
6461 }
6462
6463 void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr)
6464 {
6465    Builder bld(ctx->program, ctx->block);
6466    switch(instr->intrinsic) {
6467    case nir_intrinsic_load_barycentric_sample:
6468    case nir_intrinsic_load_barycentric_pixel:
6469    case nir_intrinsic_load_barycentric_centroid: {
6470       glsl_interp_mode mode = (glsl_interp_mode)nir_intrinsic_interp_mode(instr);
6471       Temp bary = Temp(0, s2);
6472       switch (mode) {
6473       case INTERP_MODE_SMOOTH:
6474       case INTERP_MODE_NONE:
6475          if (instr->intrinsic == nir_intrinsic_load_barycentric_pixel)
6476             bary = get_arg(ctx, ctx->args->ac.persp_center);
6477          else if (instr->intrinsic == nir_intrinsic_load_barycentric_centroid)
6478             bary = ctx->persp_centroid;
6479          else if (instr->intrinsic == nir_intrinsic_load_barycentric_sample)
6480             bary = get_arg(ctx, ctx->args->ac.persp_sample);
6481          break;
6482       case INTERP_MODE_NOPERSPECTIVE:
6483          if (instr->intrinsic == nir_intrinsic_load_barycentric_pixel)
6484             bary = get_arg(ctx, ctx->args->ac.linear_center);
6485          else if (instr->intrinsic == nir_intrinsic_load_barycentric_centroid)
6486             bary = ctx->linear_centroid;
6487          else if (instr->intrinsic == nir_intrinsic_load_barycentric_sample)
6488             bary = get_arg(ctx, ctx->args->ac.linear_sample);
6489          break;
6490       default:
6491          break;
6492       }
6493       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6494       Temp p1 = emit_extract_vector(ctx, bary, 0, v1);
6495       Temp p2 = emit_extract_vector(ctx, bary, 1, v1);
6496       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
6497                  Operand(p1), Operand(p2));
6498       emit_split_vector(ctx, dst, 2);
6499       break;
6500    }
6501    case nir_intrinsic_load_barycentric_model: {
6502       Temp model = get_arg(ctx, ctx->args->ac.pull_model);
6503
6504       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6505       Temp p1 = emit_extract_vector(ctx, model, 0, v1);
6506       Temp p2 = emit_extract_vector(ctx, model, 1, v1);
6507       Temp p3 = emit_extract_vector(ctx, model, 2, v1);
6508       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
6509                  Operand(p1), Operand(p2), Operand(p3));
6510       emit_split_vector(ctx, dst, 3);
6511       break;
6512    }
6513    case nir_intrinsic_load_barycentric_at_sample: {
6514       uint32_t sample_pos_offset = RING_PS_SAMPLE_POSITIONS * 16;
6515       switch (ctx->options->key.fs.num_samples) {
6516          case 2: sample_pos_offset += 1 << 3; break;
6517          case 4: sample_pos_offset += 3 << 3; break;
6518          case 8: sample_pos_offset += 7 << 3; break;
6519          default: break;
6520       }
6521       Temp sample_pos;
6522       Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
6523       nir_const_value* const_addr = nir_src_as_const_value(instr->src[0]);
6524       Temp private_segment_buffer = ctx->program->private_segment_buffer;
6525       if (addr.type() == RegType::sgpr) {
6526          Operand offset;
6527          if (const_addr) {
6528             sample_pos_offset += const_addr->u32 << 3;
6529             offset = Operand(sample_pos_offset);
6530          } else if (ctx->options->chip_class >= GFX9) {
6531             offset = bld.sop2(aco_opcode::s_lshl3_add_u32, bld.def(s1), bld.def(s1, scc), addr, Operand(sample_pos_offset));
6532          } else {
6533             offset = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), addr, Operand(3u));
6534             offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), addr, Operand(sample_pos_offset));
6535          }
6536
6537          Operand off = bld.copy(bld.def(s1), Operand(offset));
6538          sample_pos = bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), private_segment_buffer, off);
6539
6540       } else if (ctx->options->chip_class >= GFX9) {
6541          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
6542          sample_pos = bld.global(aco_opcode::global_load_dwordx2, bld.def(v2), addr, private_segment_buffer, sample_pos_offset);
6543       } else if (ctx->options->chip_class >= GFX7) {
6544          /* addr += private_segment_buffer + sample_pos_offset */
6545          Temp tmp0 = bld.tmp(s1);
6546          Temp tmp1 = bld.tmp(s1);
6547          bld.pseudo(aco_opcode::p_split_vector, Definition(tmp0), Definition(tmp1), private_segment_buffer);
6548          Definition scc_tmp = bld.def(s1, scc);
6549          tmp0 = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), scc_tmp, tmp0, Operand(sample_pos_offset));
6550          tmp1 = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), tmp1, Operand(0u), bld.scc(scc_tmp.getTemp()));
6551          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
6552          Temp pck0 = bld.tmp(v1);
6553          Temp carry = bld.vadd32(Definition(pck0), tmp0, addr, true).def(1).getTemp();
6554          tmp1 = as_vgpr(ctx, tmp1);
6555          Temp pck1 = bld.vop2_e64(aco_opcode::v_addc_co_u32, bld.def(v1), bld.hint_vcc(bld.def(bld.lm)), tmp1, Operand(0u), carry);
6556          addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), pck0, pck1);
6557
6558          /* sample_pos = flat_load_dwordx2 addr */
6559          sample_pos = bld.flat(aco_opcode::flat_load_dwordx2, bld.def(v2), addr, Operand(s1));
6560       } else {
6561          assert(ctx->options->chip_class == GFX6);
6562
6563          uint32_t rsrc_conf = S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
6564                               S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
6565          Temp rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), private_segment_buffer, Operand(0u), Operand(rsrc_conf));
6566
6567          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
6568          addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), addr, Operand(0u));
6569
6570          sample_pos = bld.tmp(v2);
6571
6572          aco_ptr<MUBUF_instruction> load{create_instruction<MUBUF_instruction>(aco_opcode::buffer_load_dwordx2, Format::MUBUF, 3, 1)};
6573          load->definitions[0] = Definition(sample_pos);
6574          load->operands[0] = Operand(rsrc);
6575          load->operands[1] = Operand(addr);
6576          load->operands[2] = Operand(0u);
6577          load->offset = sample_pos_offset;
6578          load->offen = 0;
6579          load->addr64 = true;
6580          load->glc = false;
6581          load->dlc = false;
6582          load->disable_wqm = false;
6583          load->barrier = barrier_none;
6584          load->can_reorder = true;
6585          ctx->block->instructions.emplace_back(std::move(load));
6586       }
6587
6588       /* sample_pos -= 0.5 */
6589       Temp pos1 = bld.tmp(RegClass(sample_pos.type(), 1));
6590       Temp pos2 = bld.tmp(RegClass(sample_pos.type(), 1));
6591       bld.pseudo(aco_opcode::p_split_vector, Definition(pos1), Definition(pos2), sample_pos);
6592       pos1 = bld.vop2_e64(aco_opcode::v_sub_f32, bld.def(v1), pos1, Operand(0x3f000000u));
6593       pos2 = bld.vop2_e64(aco_opcode::v_sub_f32, bld.def(v1), pos2, Operand(0x3f000000u));
6594
6595       emit_interp_center(ctx, get_ssa_temp(ctx, &instr->dest.ssa), pos1, pos2);
6596       break;
6597    }
6598    case nir_intrinsic_load_barycentric_at_offset: {
6599       Temp offset = get_ssa_temp(ctx, instr->src[0].ssa);
6600       RegClass rc = RegClass(offset.type(), 1);
6601       Temp pos1 = bld.tmp(rc), pos2 = bld.tmp(rc);
6602       bld.pseudo(aco_opcode::p_split_vector, Definition(pos1), Definition(pos2), offset);
6603       emit_interp_center(ctx, get_ssa_temp(ctx, &instr->dest.ssa), pos1, pos2);
6604       break;
6605    }
6606    case nir_intrinsic_load_front_face: {
6607       bld.vopc(aco_opcode::v_cmp_lg_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6608                Operand(0u), get_arg(ctx, ctx->args->ac.front_face)).def(0).setHint(vcc);
6609       break;
6610    }
6611    case nir_intrinsic_load_view_index: {
6612       if (ctx->stage & (sw_vs | sw_gs | sw_tcs | sw_tes)) {
6613          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6614          bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.view_index)));
6615          break;
6616       }
6617
6618       /* fallthrough */
6619    }
6620    case nir_intrinsic_load_layer_id: {
6621       unsigned idx = nir_intrinsic_base(instr);
6622       bld.vintrp(aco_opcode::v_interp_mov_f32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6623                  Operand(2u), bld.m0(get_arg(ctx, ctx->args->ac.prim_mask)), idx, 0);
6624       break;
6625    }
6626    case nir_intrinsic_load_frag_coord: {
6627       emit_load_frag_coord(ctx, get_ssa_temp(ctx, &instr->dest.ssa), 4);
6628       break;
6629    }
6630    case nir_intrinsic_load_sample_pos: {
6631       Temp posx = get_arg(ctx, ctx->args->ac.frag_pos[0]);
6632       Temp posy = get_arg(ctx, ctx->args->ac.frag_pos[1]);
6633       bld.pseudo(aco_opcode::p_create_vector, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6634                  posx.id() ? bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), posx) : Operand(0u),
6635                  posy.id() ? bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), posy) : Operand(0u));
6636       break;
6637    }
6638    case nir_intrinsic_load_tess_coord:
6639       visit_load_tess_coord(ctx, instr);
6640       break;
6641    case nir_intrinsic_load_interpolated_input:
6642       visit_load_interpolated_input(ctx, instr);
6643       break;
6644    case nir_intrinsic_store_output:
6645       visit_store_output(ctx, instr);
6646       break;
6647    case nir_intrinsic_load_input:
6648    case nir_intrinsic_load_input_vertex:
6649       visit_load_input(ctx, instr);
6650       break;
6651    case nir_intrinsic_load_output:
6652       visit_load_output(ctx, instr);
6653       break;
6654    case nir_intrinsic_load_per_vertex_input:
6655       visit_load_per_vertex_input(ctx, instr);
6656       break;
6657    case nir_intrinsic_load_per_vertex_output:
6658       visit_load_per_vertex_output(ctx, instr);
6659       break;
6660    case nir_intrinsic_store_per_vertex_output:
6661       visit_store_per_vertex_output(ctx, instr);
6662       break;
6663    case nir_intrinsic_load_ubo:
6664       visit_load_ubo(ctx, instr);
6665       break;
6666    case nir_intrinsic_load_push_constant:
6667       visit_load_push_constant(ctx, instr);
6668       break;
6669    case nir_intrinsic_load_constant:
6670       visit_load_constant(ctx, instr);
6671       break;
6672    case nir_intrinsic_vulkan_resource_index:
6673       visit_load_resource(ctx, instr);
6674       break;
6675    case nir_intrinsic_discard:
6676       visit_discard(ctx, instr);
6677       break;
6678    case nir_intrinsic_discard_if:
6679       visit_discard_if(ctx, instr);
6680       break;
6681    case nir_intrinsic_load_shared:
6682       visit_load_shared(ctx, instr);
6683       break;
6684    case nir_intrinsic_store_shared:
6685       visit_store_shared(ctx, instr);
6686       break;
6687    case nir_intrinsic_shared_atomic_add:
6688    case nir_intrinsic_shared_atomic_imin:
6689    case nir_intrinsic_shared_atomic_umin:
6690    case nir_intrinsic_shared_atomic_imax:
6691    case nir_intrinsic_shared_atomic_umax:
6692    case nir_intrinsic_shared_atomic_and:
6693    case nir_intrinsic_shared_atomic_or:
6694    case nir_intrinsic_shared_atomic_xor:
6695    case nir_intrinsic_shared_atomic_exchange:
6696    case nir_intrinsic_shared_atomic_comp_swap:
6697       visit_shared_atomic(ctx, instr);
6698       break;
6699    case nir_intrinsic_image_deref_load:
6700       visit_image_load(ctx, instr);
6701       break;
6702    case nir_intrinsic_image_deref_store:
6703       visit_image_store(ctx, instr);
6704       break;
6705    case nir_intrinsic_image_deref_atomic_add:
6706    case nir_intrinsic_image_deref_atomic_umin:
6707    case nir_intrinsic_image_deref_atomic_imin:
6708    case nir_intrinsic_image_deref_atomic_umax:
6709    case nir_intrinsic_image_deref_atomic_imax:
6710    case nir_intrinsic_image_deref_atomic_and:
6711    case nir_intrinsic_image_deref_atomic_or:
6712    case nir_intrinsic_image_deref_atomic_xor:
6713    case nir_intrinsic_image_deref_atomic_exchange:
6714    case nir_intrinsic_image_deref_atomic_comp_swap:
6715       visit_image_atomic(ctx, instr);
6716       break;
6717    case nir_intrinsic_image_deref_size:
6718       visit_image_size(ctx, instr);
6719       break;
6720    case nir_intrinsic_load_ssbo:
6721       visit_load_ssbo(ctx, instr);
6722       break;
6723    case nir_intrinsic_store_ssbo:
6724       visit_store_ssbo(ctx, instr);
6725       break;
6726    case nir_intrinsic_load_global:
6727       visit_load_global(ctx, instr);
6728       break;
6729    case nir_intrinsic_store_global:
6730       visit_store_global(ctx, instr);
6731       break;
6732    case nir_intrinsic_global_atomic_add:
6733    case nir_intrinsic_global_atomic_imin:
6734    case nir_intrinsic_global_atomic_umin:
6735    case nir_intrinsic_global_atomic_imax:
6736    case nir_intrinsic_global_atomic_umax:
6737    case nir_intrinsic_global_atomic_and:
6738    case nir_intrinsic_global_atomic_or:
6739    case nir_intrinsic_global_atomic_xor:
6740    case nir_intrinsic_global_atomic_exchange:
6741    case nir_intrinsic_global_atomic_comp_swap:
6742       visit_global_atomic(ctx, instr);
6743       break;
6744    case nir_intrinsic_ssbo_atomic_add:
6745    case nir_intrinsic_ssbo_atomic_imin:
6746    case nir_intrinsic_ssbo_atomic_umin:
6747    case nir_intrinsic_ssbo_atomic_imax:
6748    case nir_intrinsic_ssbo_atomic_umax:
6749    case nir_intrinsic_ssbo_atomic_and:
6750    case nir_intrinsic_ssbo_atomic_or:
6751    case nir_intrinsic_ssbo_atomic_xor:
6752    case nir_intrinsic_ssbo_atomic_exchange:
6753    case nir_intrinsic_ssbo_atomic_comp_swap:
6754       visit_atomic_ssbo(ctx, instr);
6755       break;
6756    case nir_intrinsic_load_scratch:
6757       visit_load_scratch(ctx, instr);
6758       break;
6759    case nir_intrinsic_store_scratch:
6760       visit_store_scratch(ctx, instr);
6761       break;
6762    case nir_intrinsic_get_buffer_size:
6763       visit_get_buffer_size(ctx, instr);
6764       break;
6765    case nir_intrinsic_control_barrier: {
6766       if (ctx->program->chip_class == GFX6 && ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) {
6767          /* GFX6 only (thanks to a hw bug workaround):
6768           * The real barrier instruction isn’t needed, because an entire patch
6769           * always fits into a single wave.
6770           */
6771          break;
6772       }
6773
6774       if (ctx->shader->info.stage == MESA_SHADER_COMPUTE) {
6775          unsigned* bsize = ctx->program->info->cs.block_size;
6776          unsigned workgroup_size = bsize[0] * bsize[1] * bsize[2];
6777          if (workgroup_size > ctx->program->wave_size)
6778             bld.sopp(aco_opcode::s_barrier);
6779       } else if (ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) {
6780          /* For each patch provided during rendering, n TCS shader invocations will be processed,
6781           * where n is the number of vertices in the output patch.
6782           */
6783          unsigned workgroup_size = ctx->tcs_num_patches * ctx->shader->info.tess.tcs_vertices_out;
6784          if (workgroup_size > ctx->program->wave_size)
6785             bld.sopp(aco_opcode::s_barrier);
6786       } else {
6787          /* We don't know the workgroup size, so always emit the s_barrier. */
6788          bld.sopp(aco_opcode::s_barrier);
6789       }
6790
6791       break;
6792    }
6793    case nir_intrinsic_memory_barrier_tcs_patch:
6794    case nir_intrinsic_group_memory_barrier:
6795    case nir_intrinsic_memory_barrier:
6796    case nir_intrinsic_memory_barrier_buffer:
6797    case nir_intrinsic_memory_barrier_image:
6798    case nir_intrinsic_memory_barrier_shared:
6799       emit_memory_barrier(ctx, instr);
6800       break;
6801    case nir_intrinsic_load_num_work_groups: {
6802       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6803       bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.num_work_groups)));
6804       emit_split_vector(ctx, dst, 3);
6805       break;
6806    }
6807    case nir_intrinsic_load_local_invocation_id: {
6808       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6809       bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.local_invocation_ids)));
6810       emit_split_vector(ctx, dst, 3);
6811       break;
6812    }
6813    case nir_intrinsic_load_work_group_id: {
6814       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6815       struct ac_arg *args = ctx->args->ac.workgroup_ids;
6816       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
6817                  args[0].used ? Operand(get_arg(ctx, args[0])) : Operand(0u),
6818                  args[1].used ? Operand(get_arg(ctx, args[1])) : Operand(0u),
6819                  args[2].used ? Operand(get_arg(ctx, args[2])) : Operand(0u));
6820       emit_split_vector(ctx, dst, 3);
6821       break;
6822    }
6823    case nir_intrinsic_load_local_invocation_index: {
6824       Temp id = emit_mbcnt(ctx, bld.def(v1));
6825
6826       /* The tg_size bits [6:11] contain the subgroup id,
6827        * we need this multiplied by the wave size, and then OR the thread id to it.
6828        */
6829       if (ctx->program->wave_size == 64) {
6830          /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
6831          Temp tg_num = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0xfc0u),
6832                                 get_arg(ctx, ctx->args->ac.tg_size));
6833          bld.vop2(aco_opcode::v_or_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), tg_num, id);
6834       } else {
6835          /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR  */
6836          Temp tg_num = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
6837                                 get_arg(ctx, ctx->args->ac.tg_size), Operand(0x6u | (0x6u << 16)));
6838          bld.vop3(aco_opcode::v_lshl_or_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), tg_num, Operand(0x5u), id);
6839       }
6840       break;
6841    }
6842    case nir_intrinsic_load_subgroup_id: {
6843       if (ctx->stage == compute_cs) {
6844          bld.sop2(aco_opcode::s_bfe_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), bld.def(s1, scc),
6845                   get_arg(ctx, ctx->args->ac.tg_size), Operand(0x6u | (0x6u << 16)));
6846       } else {
6847          bld.sop1(aco_opcode::s_mov_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand(0x0u));
6848       }
6849       break;
6850    }
6851    case nir_intrinsic_load_subgroup_invocation: {
6852       emit_mbcnt(ctx, Definition(get_ssa_temp(ctx, &instr->dest.ssa)));
6853       break;
6854    }
6855    case nir_intrinsic_load_num_subgroups: {
6856       if (ctx->stage == compute_cs)
6857          bld.sop2(aco_opcode::s_and_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), bld.def(s1, scc), Operand(0x3fu),
6858                   get_arg(ctx, ctx->args->ac.tg_size));
6859       else
6860          bld.sop1(aco_opcode::s_mov_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand(0x1u));
6861       break;
6862    }
6863    case nir_intrinsic_ballot: {
6864       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6865       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6866       Definition tmp = bld.def(dst.regClass());
6867       Definition lanemask_tmp = dst.size() == bld.lm.size() ? tmp : bld.def(src.regClass());
6868       if (instr->src[0].ssa->bit_size == 1) {
6869          assert(src.regClass() == bld.lm);
6870          bld.sop2(Builder::s_and, lanemask_tmp, bld.def(s1, scc), Operand(exec, bld.lm), src);
6871       } else if (instr->src[0].ssa->bit_size == 32 && src.regClass() == v1) {
6872          bld.vopc(aco_opcode::v_cmp_lg_u32, lanemask_tmp, Operand(0u), src);
6873       } else if (instr->src[0].ssa->bit_size == 64 && src.regClass() == v2) {
6874          bld.vopc(aco_opcode::v_cmp_lg_u64, lanemask_tmp, Operand(0u), src);
6875       } else {
6876          fprintf(stderr, "Unimplemented NIR instr bit size: ");
6877          nir_print_instr(&instr->instr, stderr);
6878          fprintf(stderr, "\n");
6879       }
6880       if (dst.size() != bld.lm.size()) {
6881          /* Wave32 with ballot size set to 64 */
6882          bld.pseudo(aco_opcode::p_create_vector, Definition(tmp), lanemask_tmp.getTemp(), Operand(0u));
6883       }
6884       emit_wqm(ctx, tmp.getTemp(), dst);
6885       break;
6886    }
6887    case nir_intrinsic_shuffle:
6888    case nir_intrinsic_read_invocation: {
6889       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6890       if (!ctx->divergent_vals[instr->src[0].ssa->index]) {
6891          emit_uniform_subgroup(ctx, instr, src);
6892       } else {
6893          Temp tid = get_ssa_temp(ctx, instr->src[1].ssa);
6894          if (instr->intrinsic == nir_intrinsic_read_invocation || !ctx->divergent_vals[instr->src[1].ssa->index])
6895             tid = bld.as_uniform(tid);
6896          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6897          if (src.regClass() == v1) {
6898             emit_wqm(ctx, emit_bpermute(ctx, bld, tid, src), dst);
6899          } else if (src.regClass() == v2) {
6900             Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6901             bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6902             lo = emit_wqm(ctx, emit_bpermute(ctx, bld, tid, lo));
6903             hi = emit_wqm(ctx, emit_bpermute(ctx, bld, tid, hi));
6904             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6905             emit_split_vector(ctx, dst, 2);
6906          } else if (instr->dest.ssa.bit_size == 1 && tid.regClass() == s1) {
6907             assert(src.regClass() == bld.lm);
6908             Temp tmp = bld.sopc(Builder::s_bitcmp1, bld.def(s1, scc), src, tid);
6909             bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
6910          } else if (instr->dest.ssa.bit_size == 1 && tid.regClass() == v1) {
6911             assert(src.regClass() == bld.lm);
6912             Temp tmp;
6913             if (ctx->program->chip_class <= GFX7)
6914                tmp = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), src, tid);
6915             else if (ctx->program->wave_size == 64)
6916                tmp = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), tid, src);
6917             else
6918                tmp = bld.vop2_e64(aco_opcode::v_lshrrev_b32, bld.def(v1), tid, src);
6919             tmp = emit_extract_vector(ctx, tmp, 0, v1);
6920             tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u), tmp);
6921             emit_wqm(ctx, bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp), dst);
6922          } else {
6923             fprintf(stderr, "Unimplemented NIR instr bit size: ");
6924             nir_print_instr(&instr->instr, stderr);
6925             fprintf(stderr, "\n");
6926          }
6927       }
6928       break;
6929    }
6930    case nir_intrinsic_load_sample_id: {
6931       bld.vop3(aco_opcode::v_bfe_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6932                get_arg(ctx, ctx->args->ac.ancillary), Operand(8u), Operand(4u));
6933       break;
6934    }
6935    case nir_intrinsic_load_sample_mask_in: {
6936       visit_load_sample_mask_in(ctx, instr);
6937       break;
6938    }
6939    case nir_intrinsic_read_first_invocation: {
6940       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6941       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6942       if (src.regClass() == v1) {
6943          emit_wqm(ctx,
6944                   bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), src),
6945                   dst);
6946       } else if (src.regClass() == v2) {
6947          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6948          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6949          lo = emit_wqm(ctx, bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), lo));
6950          hi = emit_wqm(ctx, bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), hi));
6951          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6952          emit_split_vector(ctx, dst, 2);
6953       } else if (instr->dest.ssa.bit_size == 1) {
6954          assert(src.regClass() == bld.lm);
6955          Temp tmp = bld.sopc(Builder::s_bitcmp1, bld.def(s1, scc), src,
6956                              bld.sop1(Builder::s_ff1_i32, bld.def(s1), Operand(exec, bld.lm)));
6957          bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
6958       } else if (src.regClass() == s1) {
6959          bld.sop1(aco_opcode::s_mov_b32, Definition(dst), src);
6960       } else if (src.regClass() == s2) {
6961          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src);
6962       } else {
6963          fprintf(stderr, "Unimplemented NIR instr bit size: ");
6964          nir_print_instr(&instr->instr, stderr);
6965          fprintf(stderr, "\n");
6966       }
6967       break;
6968    }
6969    case nir_intrinsic_vote_all: {
6970       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6971       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6972       assert(src.regClass() == bld.lm);
6973       assert(dst.regClass() == bld.lm);
6974
6975       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src).def(1).getTemp();
6976       Temp cond = bool_to_vector_condition(ctx, emit_wqm(ctx, tmp));
6977       bld.sop1(Builder::s_not, Definition(dst), bld.def(s1, scc), cond);
6978       break;
6979    }
6980    case nir_intrinsic_vote_any: {
6981       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6982       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6983       assert(src.regClass() == bld.lm);
6984       assert(dst.regClass() == bld.lm);
6985
6986       Temp tmp = bool_to_scalar_condition(ctx, src);
6987       bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
6988       break;
6989    }
6990    case nir_intrinsic_reduce:
6991    case nir_intrinsic_inclusive_scan:
6992    case nir_intrinsic_exclusive_scan: {
6993       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6994       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6995       nir_op op = (nir_op) nir_intrinsic_reduction_op(instr);
6996       unsigned cluster_size = instr->intrinsic == nir_intrinsic_reduce ?
6997          nir_intrinsic_cluster_size(instr) : 0;
6998       cluster_size = util_next_power_of_two(MIN2(cluster_size ? cluster_size : ctx->program->wave_size, ctx->program->wave_size));
6999
7000       if (!ctx->divergent_vals[instr->src[0].ssa->index] && (op == nir_op_ior || op == nir_op_iand)) {
7001          emit_uniform_subgroup(ctx, instr, src);
7002       } else if (instr->dest.ssa.bit_size == 1) {
7003          if (op == nir_op_imul || op == nir_op_umin || op == nir_op_imin)
7004             op = nir_op_iand;
7005          else if (op == nir_op_iadd)
7006             op = nir_op_ixor;
7007          else if (op == nir_op_umax || op == nir_op_imax)
7008             op = nir_op_ior;
7009          assert(op == nir_op_iand || op == nir_op_ior || op == nir_op_ixor);
7010
7011          switch (instr->intrinsic) {
7012          case nir_intrinsic_reduce:
7013             emit_wqm(ctx, emit_boolean_reduce(ctx, op, cluster_size, src), dst);
7014             break;
7015          case nir_intrinsic_exclusive_scan:
7016             emit_wqm(ctx, emit_boolean_exclusive_scan(ctx, op, src), dst);
7017             break;
7018          case nir_intrinsic_inclusive_scan:
7019             emit_wqm(ctx, emit_boolean_inclusive_scan(ctx, op, src), dst);
7020             break;
7021          default:
7022             assert(false);
7023          }
7024       } else if (cluster_size == 1) {
7025          bld.copy(Definition(dst), src);
7026       } else {
7027          src = as_vgpr(ctx, src);
7028
7029          ReduceOp reduce_op;
7030          switch (op) {
7031          #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
7032             CASE(iadd)
7033             CASE(imul)
7034             CASE(fadd)
7035             CASE(fmul)
7036             CASE(imin)
7037             CASE(umin)
7038             CASE(fmin)
7039             CASE(imax)
7040             CASE(umax)
7041             CASE(fmax)
7042             CASE(iand)
7043             CASE(ior)
7044             CASE(ixor)
7045             default:
7046                unreachable("unknown reduction op");
7047          #undef CASE
7048          }
7049
7050          aco_opcode aco_op;
7051          switch (instr->intrinsic) {
7052             case nir_intrinsic_reduce: aco_op = aco_opcode::p_reduce; break;
7053             case nir_intrinsic_inclusive_scan: aco_op = aco_opcode::p_inclusive_scan; break;
7054             case nir_intrinsic_exclusive_scan: aco_op = aco_opcode::p_exclusive_scan; break;
7055             default:
7056                unreachable("unknown reduce intrinsic");
7057          }
7058
7059          aco_ptr<Pseudo_reduction_instruction> reduce{create_instruction<Pseudo_reduction_instruction>(aco_op, Format::PSEUDO_REDUCTION, 3, 5)};
7060          reduce->operands[0] = Operand(src);
7061          // filled in by aco_reduce_assign.cpp, used internally as part of the
7062          // reduce sequence
7063          assert(dst.size() == 1 || dst.size() == 2);
7064          reduce->operands[1] = Operand(RegClass(RegType::vgpr, dst.size()).as_linear());
7065          reduce->operands[2] = Operand(v1.as_linear());
7066
7067          Temp tmp_dst = bld.tmp(dst.regClass());
7068          reduce->definitions[0] = Definition(tmp_dst);
7069          reduce->definitions[1] = bld.def(ctx->program->lane_mask); // used internally
7070          reduce->definitions[2] = Definition();
7071          reduce->definitions[3] = Definition(scc, s1);
7072          reduce->definitions[4] = Definition();
7073          reduce->reduce_op = reduce_op;
7074          reduce->cluster_size = cluster_size;
7075          ctx->block->instructions.emplace_back(std::move(reduce));
7076
7077          emit_wqm(ctx, tmp_dst, dst);
7078       }
7079       break;
7080    }
7081    case nir_intrinsic_quad_broadcast: {
7082       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7083       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
7084          emit_uniform_subgroup(ctx, instr, src);
7085       } else {
7086          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7087          unsigned lane = nir_src_as_const_value(instr->src[1])->u32;
7088          uint32_t dpp_ctrl = dpp_quad_perm(lane, lane, lane, lane);
7089
7090          if (instr->dest.ssa.bit_size == 1) {
7091             assert(src.regClass() == bld.lm);
7092             assert(dst.regClass() == bld.lm);
7093             uint32_t half_mask = 0x11111111u << lane;
7094             Temp mask_tmp = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(half_mask), Operand(half_mask));
7095             Temp tmp = bld.tmp(bld.lm);
7096             bld.sop1(Builder::s_wqm, Definition(tmp),
7097                      bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), mask_tmp,
7098                               bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm))));
7099             emit_wqm(ctx, tmp, dst);
7100          } else if (instr->dest.ssa.bit_size == 32) {
7101             if (ctx->program->chip_class >= GFX8)
7102                emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl), dst);
7103             else
7104                emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl), dst);
7105          } else if (instr->dest.ssa.bit_size == 64) {
7106             Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
7107             bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
7108             if (ctx->program->chip_class >= GFX8) {
7109                lo = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), lo, dpp_ctrl));
7110                hi = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), hi, dpp_ctrl));
7111             } else {
7112                lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, (1 << 15) | dpp_ctrl));
7113                hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, (1 << 15) | dpp_ctrl));
7114             }
7115             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
7116             emit_split_vector(ctx, dst, 2);
7117          } else {
7118             fprintf(stderr, "Unimplemented NIR instr bit size: ");
7119             nir_print_instr(&instr->instr, stderr);
7120             fprintf(stderr, "\n");
7121          }
7122       }
7123       break;
7124    }
7125    case nir_intrinsic_quad_swap_horizontal:
7126    case nir_intrinsic_quad_swap_vertical:
7127    case nir_intrinsic_quad_swap_diagonal:
7128    case nir_intrinsic_quad_swizzle_amd: {
7129       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7130       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
7131          emit_uniform_subgroup(ctx, instr, src);
7132          break;
7133       }
7134       uint16_t dpp_ctrl = 0;
7135       switch (instr->intrinsic) {
7136       case nir_intrinsic_quad_swap_horizontal:
7137          dpp_ctrl = dpp_quad_perm(1, 0, 3, 2);
7138          break;
7139       case nir_intrinsic_quad_swap_vertical:
7140          dpp_ctrl = dpp_quad_perm(2, 3, 0, 1);
7141          break;
7142       case nir_intrinsic_quad_swap_diagonal:
7143          dpp_ctrl = dpp_quad_perm(3, 2, 1, 0);
7144          break;
7145       case nir_intrinsic_quad_swizzle_amd:
7146          dpp_ctrl = nir_intrinsic_swizzle_mask(instr);
7147          break;
7148       default:
7149          break;
7150       }
7151       if (ctx->program->chip_class < GFX8)
7152          dpp_ctrl |= (1 << 15);
7153
7154       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7155       if (instr->dest.ssa.bit_size == 1) {
7156          assert(src.regClass() == bld.lm);
7157          src = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand((uint32_t)-1), src);
7158          if (ctx->program->chip_class >= GFX8)
7159             src = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl);
7160          else
7161             src = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, dpp_ctrl);
7162          Temp tmp = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), src);
7163          emit_wqm(ctx, tmp, dst);
7164       } else if (instr->dest.ssa.bit_size == 32) {
7165          Temp tmp;
7166          if (ctx->program->chip_class >= GFX8)
7167             tmp = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl);
7168          else
7169             tmp = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, dpp_ctrl);
7170          emit_wqm(ctx, tmp, dst);
7171       } else if (instr->dest.ssa.bit_size == 64) {
7172          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
7173          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
7174          if (ctx->program->chip_class >= GFX8) {
7175             lo = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), lo, dpp_ctrl));
7176             hi = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), hi, dpp_ctrl));
7177          } else {
7178             lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, dpp_ctrl));
7179             hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, dpp_ctrl));
7180          }
7181          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
7182          emit_split_vector(ctx, dst, 2);
7183       } else {
7184          fprintf(stderr, "Unimplemented NIR instr bit size: ");
7185          nir_print_instr(&instr->instr, stderr);
7186          fprintf(stderr, "\n");
7187       }
7188       break;
7189    }
7190    case nir_intrinsic_masked_swizzle_amd: {
7191       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7192       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
7193          emit_uniform_subgroup(ctx, instr, src);
7194          break;
7195       }
7196       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7197       uint32_t mask = nir_intrinsic_swizzle_mask(instr);
7198       if (dst.regClass() == v1) {
7199          emit_wqm(ctx,
7200                   bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, mask, 0, false),
7201                   dst);
7202       } else if (dst.regClass() == v2) {
7203          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
7204          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
7205          lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, mask, 0, false));
7206          hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, mask, 0, false));
7207          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
7208          emit_split_vector(ctx, dst, 2);
7209       } else {
7210          fprintf(stderr, "Unimplemented NIR instr bit size: ");
7211          nir_print_instr(&instr->instr, stderr);
7212          fprintf(stderr, "\n");
7213       }
7214       break;
7215    }
7216    case nir_intrinsic_write_invocation_amd: {
7217       Temp src = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
7218       Temp val = bld.as_uniform(get_ssa_temp(ctx, instr->src[1].ssa));
7219       Temp lane = bld.as_uniform(get_ssa_temp(ctx, instr->src[2].ssa));
7220       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7221       if (dst.regClass() == v1) {
7222          /* src2 is ignored for writelane. RA assigns the same reg for dst */
7223          emit_wqm(ctx, bld.writelane(bld.def(v1), val, lane, src), dst);
7224       } else if (dst.regClass() == v2) {
7225          Temp src_lo = bld.tmp(v1), src_hi = bld.tmp(v1);
7226          Temp val_lo = bld.tmp(s1), val_hi = bld.tmp(s1);
7227          bld.pseudo(aco_opcode::p_split_vector, Definition(src_lo), Definition(src_hi), src);
7228          bld.pseudo(aco_opcode::p_split_vector, Definition(val_lo), Definition(val_hi), val);
7229          Temp lo = emit_wqm(ctx, bld.writelane(bld.def(v1), val_lo, lane, src_hi));
7230          Temp hi = emit_wqm(ctx, bld.writelane(bld.def(v1), val_hi, lane, src_hi));
7231          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
7232          emit_split_vector(ctx, dst, 2);
7233       } else {
7234          fprintf(stderr, "Unimplemented NIR instr bit size: ");
7235          nir_print_instr(&instr->instr, stderr);
7236          fprintf(stderr, "\n");
7237       }
7238       break;
7239    }
7240    case nir_intrinsic_mbcnt_amd: {
7241       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7242       RegClass rc = RegClass(src.type(), 1);
7243       Temp mask_lo = bld.tmp(rc), mask_hi = bld.tmp(rc);
7244       bld.pseudo(aco_opcode::p_split_vector, Definition(mask_lo), Definition(mask_hi), src);
7245       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7246       Temp wqm_tmp = emit_mbcnt(ctx, bld.def(v1), Operand(mask_lo), Operand(mask_hi));
7247       emit_wqm(ctx, wqm_tmp, dst);
7248       break;
7249    }
7250    case nir_intrinsic_load_helper_invocation: {
7251       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7252       bld.pseudo(aco_opcode::p_load_helper, Definition(dst));
7253       ctx->block->kind |= block_kind_needs_lowering;
7254       ctx->program->needs_exact = true;
7255       break;
7256    }
7257    case nir_intrinsic_is_helper_invocation: {
7258       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7259       bld.pseudo(aco_opcode::p_is_helper, Definition(dst));
7260       ctx->block->kind |= block_kind_needs_lowering;
7261       ctx->program->needs_exact = true;
7262       break;
7263    }
7264    case nir_intrinsic_demote:
7265       bld.pseudo(aco_opcode::p_demote_to_helper, Operand(-1u));
7266
7267       if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
7268          ctx->cf_info.exec_potentially_empty_discard = true;
7269       ctx->block->kind |= block_kind_uses_demote;
7270       ctx->program->needs_exact = true;
7271       break;
7272    case nir_intrinsic_demote_if: {
7273       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7274       assert(src.regClass() == bld.lm);
7275       Temp cond = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
7276       bld.pseudo(aco_opcode::p_demote_to_helper, cond);
7277
7278       if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
7279          ctx->cf_info.exec_potentially_empty_discard = true;
7280       ctx->block->kind |= block_kind_uses_demote;
7281       ctx->program->needs_exact = true;
7282       break;
7283    }
7284    case nir_intrinsic_first_invocation: {
7285       emit_wqm(ctx, bld.sop1(Builder::s_ff1_i32, bld.def(s1), Operand(exec, bld.lm)),
7286                get_ssa_temp(ctx, &instr->dest.ssa));
7287       break;
7288    }
7289    case nir_intrinsic_shader_clock:
7290       bld.smem(aco_opcode::s_memtime, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), false);
7291       emit_split_vector(ctx, get_ssa_temp(ctx, &instr->dest.ssa), 2);
7292       break;
7293    case nir_intrinsic_load_vertex_id_zero_base: {
7294       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7295       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.vertex_id));
7296       break;
7297    }
7298    case nir_intrinsic_load_first_vertex: {
7299       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7300       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.base_vertex));
7301       break;
7302    }
7303    case nir_intrinsic_load_base_instance: {
7304       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7305       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.start_instance));
7306       break;
7307    }
7308    case nir_intrinsic_load_instance_id: {
7309       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7310       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.instance_id));
7311       break;
7312    }
7313    case nir_intrinsic_load_draw_id: {
7314       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7315       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.draw_id));
7316       break;
7317    }
7318    case nir_intrinsic_load_invocation_id: {
7319       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7320
7321       if (ctx->shader->info.stage == MESA_SHADER_GEOMETRY) {
7322          if (ctx->options->chip_class >= GFX10)
7323             bld.vop2_e64(aco_opcode::v_and_b32, Definition(dst), Operand(127u), get_arg(ctx, ctx->args->ac.gs_invocation_id));
7324          else
7325             bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.gs_invocation_id));
7326       } else if (ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) {
7327          bld.vop3(aco_opcode::v_bfe_u32, Definition(dst),
7328                   get_arg(ctx, ctx->args->ac.tcs_rel_ids), Operand(8u), Operand(5u));
7329       } else {
7330          unreachable("Unsupported stage for load_invocation_id");
7331       }
7332
7333       break;
7334    }
7335    case nir_intrinsic_load_primitive_id: {
7336       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7337
7338       switch (ctx->shader->info.stage) {
7339       case MESA_SHADER_GEOMETRY:
7340          bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.gs_prim_id));
7341          break;
7342       case MESA_SHADER_TESS_CTRL:
7343          bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.tcs_patch_id));
7344          break;
7345       case MESA_SHADER_TESS_EVAL:
7346          bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.tes_patch_id));
7347          break;
7348       default:
7349          unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
7350       }
7351
7352       break;
7353    }
7354    case nir_intrinsic_load_patch_vertices_in: {
7355       assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL ||
7356              ctx->shader->info.stage == MESA_SHADER_TESS_EVAL);
7357
7358       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7359       bld.copy(Definition(dst), Operand(ctx->args->options->key.tcs.input_vertices));
7360       break;
7361    }
7362    case nir_intrinsic_emit_vertex_with_counter: {
7363       visit_emit_vertex_with_counter(ctx, instr);
7364       break;
7365    }
7366    case nir_intrinsic_end_primitive_with_counter: {
7367       unsigned stream = nir_intrinsic_stream_id(instr);
7368       bld.sopp(aco_opcode::s_sendmsg, bld.m0(ctx->gs_wave_id), -1, sendmsg_gs(true, false, stream));
7369       break;
7370    }
7371    case nir_intrinsic_set_vertex_count: {
7372       /* unused, the HW keeps track of this for us */
7373       break;
7374    }
7375    default:
7376       fprintf(stderr, "Unimplemented intrinsic instr: ");
7377       nir_print_instr(&instr->instr, stderr);
7378       fprintf(stderr, "\n");
7379       abort();
7380
7381       break;
7382    }
7383 }
7384
7385
7386 void tex_fetch_ptrs(isel_context *ctx, nir_tex_instr *instr,
7387                     Temp *res_ptr, Temp *samp_ptr, Temp *fmask_ptr,
7388                     enum glsl_base_type *stype)
7389 {
7390    nir_deref_instr *texture_deref_instr = NULL;
7391    nir_deref_instr *sampler_deref_instr = NULL;
7392    int plane = -1;
7393
7394    for (unsigned i = 0; i < instr->num_srcs; i++) {
7395       switch (instr->src[i].src_type) {
7396       case nir_tex_src_texture_deref:
7397          texture_deref_instr = nir_src_as_deref(instr->src[i].src);
7398          break;
7399       case nir_tex_src_sampler_deref:
7400          sampler_deref_instr = nir_src_as_deref(instr->src[i].src);
7401          break;
7402       case nir_tex_src_plane:
7403          plane = nir_src_as_int(instr->src[i].src);
7404          break;
7405       default:
7406          break;
7407       }
7408    }
7409
7410    *stype = glsl_get_sampler_result_type(texture_deref_instr->type);
7411
7412    if (!sampler_deref_instr)
7413       sampler_deref_instr = texture_deref_instr;
7414
7415    if (plane >= 0) {
7416       assert(instr->op != nir_texop_txf_ms &&
7417              instr->op != nir_texop_samples_identical);
7418       assert(instr->sampler_dim  != GLSL_SAMPLER_DIM_BUF);
7419       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, (aco_descriptor_type)(ACO_DESC_PLANE_0 + plane), instr, false, false);
7420    } else if (instr->sampler_dim  == GLSL_SAMPLER_DIM_BUF) {
7421       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_BUFFER, instr, false, false);
7422    } else if (instr->op == nir_texop_fragment_mask_fetch) {
7423       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_FMASK, instr, false, false);
7424    } else {
7425       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_IMAGE, instr, false, false);
7426    }
7427    if (samp_ptr) {
7428       *samp_ptr = get_sampler_desc(ctx, sampler_deref_instr, ACO_DESC_SAMPLER, instr, false, false);
7429
7430       if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT && ctx->options->chip_class < GFX8) {
7431          /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
7432          Builder bld(ctx->program, ctx->block);
7433
7434          /* to avoid unnecessary moves, we split and recombine sampler and image */
7435          Temp img[8] = {bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1),
7436                         bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1)};
7437          Temp samp[4] = {bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1)};
7438          bld.pseudo(aco_opcode::p_split_vector, Definition(img[0]), Definition(img[1]),
7439                     Definition(img[2]), Definition(img[3]), Definition(img[4]),
7440                     Definition(img[5]), Definition(img[6]), Definition(img[7]), *res_ptr);
7441          bld.pseudo(aco_opcode::p_split_vector, Definition(samp[0]), Definition(samp[1]),
7442                     Definition(samp[2]), Definition(samp[3]), *samp_ptr);
7443
7444          samp[0] = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), samp[0], img[7]);
7445          *res_ptr = bld.pseudo(aco_opcode::p_create_vector, bld.def(s8),
7446                                img[0], img[1], img[2], img[3],
7447                                img[4], img[5], img[6], img[7]);
7448          *samp_ptr = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
7449                                 samp[0], samp[1], samp[2], samp[3]);
7450       }
7451    }
7452    if (fmask_ptr && (instr->op == nir_texop_txf_ms ||
7453                      instr->op == nir_texop_samples_identical))
7454       *fmask_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_FMASK, instr, false, false);
7455 }
7456
7457 void build_cube_select(isel_context *ctx, Temp ma, Temp id, Temp deriv,
7458                        Temp *out_ma, Temp *out_sc, Temp *out_tc)
7459 {
7460    Builder bld(ctx->program, ctx->block);
7461
7462    Temp deriv_x = emit_extract_vector(ctx, deriv, 0, v1);
7463    Temp deriv_y = emit_extract_vector(ctx, deriv, 1, v1);
7464    Temp deriv_z = emit_extract_vector(ctx, deriv, 2, v1);
7465
7466    Operand neg_one(0xbf800000u);
7467    Operand one(0x3f800000u);
7468    Operand two(0x40000000u);
7469    Operand four(0x40800000u);
7470
7471    Temp is_ma_positive = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), ma);
7472    Temp sgn_ma = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), neg_one, one, is_ma_positive);
7473    Temp neg_sgn_ma = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), Operand(0u), sgn_ma);
7474
7475    Temp is_ma_z = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), four, id);
7476    Temp is_ma_y = bld.vopc(aco_opcode::v_cmp_le_f32, bld.def(bld.lm), two, id);
7477    is_ma_y = bld.sop2(Builder::s_andn2, bld.hint_vcc(bld.def(bld.lm)), is_ma_y, is_ma_z);
7478    Temp is_not_ma_x = bld.sop2(aco_opcode::s_or_b64, bld.hint_vcc(bld.def(bld.lm)), bld.def(s1, scc), is_ma_z, is_ma_y);
7479
7480    // select sc
7481    Temp tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_z, deriv_x, is_not_ma_x);
7482    Temp sgn = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1),
7483                        bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), neg_sgn_ma, sgn_ma, is_ma_z),
7484                        one, is_ma_y);
7485    *out_sc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tmp, sgn);
7486
7487    // select tc
7488    tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_y, deriv_z, is_ma_y);
7489    sgn = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), neg_one, sgn_ma, is_ma_y);
7490    *out_tc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tmp, sgn);
7491
7492    // select ma
7493    tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
7494                   bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_x, deriv_y, is_ma_y),
7495                   deriv_z, is_ma_z);
7496    tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffffu), tmp);
7497    *out_ma = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), two, tmp);
7498 }
7499
7500 void prepare_cube_coords(isel_context *ctx, std::vector<Temp>& coords, Temp* ddx, Temp* ddy, bool is_deriv, bool is_array)
7501 {
7502    Builder bld(ctx->program, ctx->block);
7503    Temp ma, tc, sc, id;
7504
7505    if (is_array) {
7506       coords[3] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coords[3]);
7507
7508       // see comment in ac_prepare_cube_coords()
7509       if (ctx->options->chip_class <= GFX8)
7510          coords[3] = bld.vop2(aco_opcode::v_max_f32, bld.def(v1), Operand(0u), coords[3]);
7511    }
7512
7513    ma = bld.vop3(aco_opcode::v_cubema_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7514
7515    aco_ptr<VOP3A_instruction> vop3a{create_instruction<VOP3A_instruction>(aco_opcode::v_rcp_f32, asVOP3(Format::VOP1), 1, 1)};
7516    vop3a->operands[0] = Operand(ma);
7517    vop3a->abs[0] = true;
7518    Temp invma = bld.tmp(v1);
7519    vop3a->definitions[0] = Definition(invma);
7520    ctx->block->instructions.emplace_back(std::move(vop3a));
7521
7522    sc = bld.vop3(aco_opcode::v_cubesc_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7523    if (!is_deriv)
7524       sc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), sc, invma, Operand(0x3fc00000u/*1.5*/));
7525
7526    tc = bld.vop3(aco_opcode::v_cubetc_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7527    if (!is_deriv)
7528       tc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), tc, invma, Operand(0x3fc00000u/*1.5*/));
7529
7530    id = bld.vop3(aco_opcode::v_cubeid_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7531
7532    if (is_deriv) {
7533       sc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), sc, invma);
7534       tc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tc, invma);
7535
7536       for (unsigned i = 0; i < 2; i++) {
7537          // see comment in ac_prepare_cube_coords()
7538          Temp deriv_ma;
7539          Temp deriv_sc, deriv_tc;
7540          build_cube_select(ctx, ma, id, i ? *ddy : *ddx,
7541                            &deriv_ma, &deriv_sc, &deriv_tc);
7542
7543          deriv_ma = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, invma);
7544
7545          Temp x = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1),
7546                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_sc, invma),
7547                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, sc));
7548          Temp y = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1),
7549                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_tc, invma),
7550                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, tc));
7551          *(i ? ddy : ddx) = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), x, y);
7552       }
7553
7554       sc = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), Operand(0x3fc00000u/*1.5*/), sc);
7555       tc = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), Operand(0x3fc00000u/*1.5*/), tc);
7556    }
7557
7558    if (is_array)
7559       id = bld.vop2(aco_opcode::v_madmk_f32, bld.def(v1), coords[3], id, Operand(0x41000000u/*8.0*/));
7560    coords.resize(3);
7561    coords[0] = sc;
7562    coords[1] = tc;
7563    coords[2] = id;
7564 }
7565
7566 void get_const_vec(nir_ssa_def *vec, nir_const_value *cv[4])
7567 {
7568    if (vec->parent_instr->type != nir_instr_type_alu)
7569       return;
7570    nir_alu_instr *vec_instr = nir_instr_as_alu(vec->parent_instr);
7571    if (vec_instr->op != nir_op_vec(vec->num_components))
7572       return;
7573
7574    for (unsigned i = 0; i < vec->num_components; i++) {
7575       cv[i] = vec_instr->src[i].swizzle[0] == 0 ?
7576               nir_src_as_const_value(vec_instr->src[i].src) : NULL;
7577    }
7578 }
7579
7580 void visit_tex(isel_context *ctx, nir_tex_instr *instr)
7581 {
7582    Builder bld(ctx->program, ctx->block);
7583    bool has_bias = false, has_lod = false, level_zero = false, has_compare = false,
7584         has_offset = false, has_ddx = false, has_ddy = false, has_derivs = false, has_sample_index = false;
7585    Temp resource, sampler, fmask_ptr, bias = Temp(), compare = Temp(), sample_index = Temp(),
7586         lod = Temp(), offset = Temp(), ddx = Temp(), ddy = Temp();
7587    std::vector<Temp> coords;
7588    std::vector<Temp> derivs;
7589    nir_const_value *sample_index_cv = NULL;
7590    nir_const_value *const_offset[4] = {NULL, NULL, NULL, NULL};
7591    enum glsl_base_type stype;
7592    tex_fetch_ptrs(ctx, instr, &resource, &sampler, &fmask_ptr, &stype);
7593
7594    bool tg4_integer_workarounds = ctx->options->chip_class <= GFX8 && instr->op == nir_texop_tg4 &&
7595                                   (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT);
7596    bool tg4_integer_cube_workaround = tg4_integer_workarounds &&
7597                                       instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
7598
7599    for (unsigned i = 0; i < instr->num_srcs; i++) {
7600       switch (instr->src[i].src_type) {
7601       case nir_tex_src_coord: {
7602          Temp coord = get_ssa_temp(ctx, instr->src[i].src.ssa);
7603          for (unsigned i = 0; i < coord.size(); i++)
7604             coords.emplace_back(emit_extract_vector(ctx, coord, i, v1));
7605          break;
7606       }
7607       case nir_tex_src_bias:
7608          if (instr->op == nir_texop_txb) {
7609             bias = get_ssa_temp(ctx, instr->src[i].src.ssa);
7610             has_bias = true;
7611          }
7612          break;
7613       case nir_tex_src_lod: {
7614          nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
7615
7616          if (val && val->f32 <= 0.0) {
7617             level_zero = true;
7618          } else {
7619             lod = get_ssa_temp(ctx, instr->src[i].src.ssa);
7620             has_lod = true;
7621          }
7622          break;
7623       }
7624       case nir_tex_src_comparator:
7625          if (instr->is_shadow) {
7626             compare = get_ssa_temp(ctx, instr->src[i].src.ssa);
7627             has_compare = true;
7628          }
7629          break;
7630       case nir_tex_src_offset:
7631          offset = get_ssa_temp(ctx, instr->src[i].src.ssa);
7632          get_const_vec(instr->src[i].src.ssa, const_offset);
7633          has_offset = true;
7634          break;
7635       case nir_tex_src_ddx:
7636          ddx = get_ssa_temp(ctx, instr->src[i].src.ssa);
7637          has_ddx = true;
7638          break;
7639       case nir_tex_src_ddy:
7640          ddy = get_ssa_temp(ctx, instr->src[i].src.ssa);
7641          has_ddy = true;
7642          break;
7643       case nir_tex_src_ms_index:
7644          sample_index = get_ssa_temp(ctx, instr->src[i].src.ssa);
7645          sample_index_cv = nir_src_as_const_value(instr->src[i].src);
7646          has_sample_index = true;
7647          break;
7648       case nir_tex_src_texture_offset:
7649       case nir_tex_src_sampler_offset:
7650       default:
7651          break;
7652       }
7653    }
7654
7655    if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
7656       return get_buffer_size(ctx, resource, get_ssa_temp(ctx, &instr->dest.ssa), true);
7657
7658    if (instr->op == nir_texop_texture_samples) {
7659       Temp dword3 = emit_extract_vector(ctx, resource, 3, s1);
7660
7661       Temp samples_log2 = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), dword3, Operand(16u | 4u<<16));
7662       Temp samples = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), Operand(1u), samples_log2);
7663       Temp type = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), dword3, Operand(28u | 4u<<16 /* offset=28, width=4 */));
7664       Temp is_msaa = bld.sopc(aco_opcode::s_cmp_ge_u32, bld.def(s1, scc), type, Operand(14u));
7665
7666       bld.sop2(aco_opcode::s_cselect_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
7667                samples, Operand(1u), bld.scc(is_msaa));
7668       return;
7669    }
7670
7671    if (has_offset && instr->op != nir_texop_txf && instr->op != nir_texop_txf_ms) {
7672       aco_ptr<Instruction> tmp_instr;
7673       Temp acc, pack = Temp();
7674
7675       uint32_t pack_const = 0;
7676       for (unsigned i = 0; i < offset.size(); i++) {
7677          if (!const_offset[i])
7678             continue;
7679          pack_const |= (const_offset[i]->u32 & 0x3Fu) << (8u * i);
7680       }
7681
7682       if (offset.type() == RegType::sgpr) {
7683          for (unsigned i = 0; i < offset.size(); i++) {
7684             if (const_offset[i])
7685                continue;
7686
7687             acc = emit_extract_vector(ctx, offset, i, s1);
7688             acc = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), acc, Operand(0x3Fu));
7689
7690             if (i) {
7691                acc = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), acc, Operand(8u * i));
7692             }
7693
7694             if (pack == Temp()) {
7695                pack = acc;
7696             } else {
7697                pack = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), pack, acc);
7698             }
7699          }
7700
7701          if (pack_const && pack != Temp())
7702             pack = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(pack_const), pack);
7703       } else {
7704          for (unsigned i = 0; i < offset.size(); i++) {
7705             if (const_offset[i])
7706                continue;
7707
7708             acc = emit_extract_vector(ctx, offset, i, v1);
7709             acc = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x3Fu), acc);
7710
7711             if (i) {
7712                acc = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(8u * i), acc);
7713             }
7714
7715             if (pack == Temp()) {
7716                pack = acc;
7717             } else {
7718                pack = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), pack, acc);
7719             }
7720          }
7721
7722          if (pack_const && pack != Temp())
7723             pack = bld.sop2(aco_opcode::v_or_b32, bld.def(v1), Operand(pack_const), pack);
7724       }
7725       if (pack_const && pack == Temp())
7726          offset = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(pack_const));
7727       else if (pack == Temp())
7728          has_offset = false;
7729       else
7730          offset = pack;
7731    }
7732
7733    if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && instr->coord_components)
7734       prepare_cube_coords(ctx, coords, &ddx, &ddy, instr->op == nir_texop_txd, instr->is_array && instr->op != nir_texop_lod);
7735
7736    /* pack derivatives */
7737    if (has_ddx || has_ddy) {
7738       if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && ctx->options->chip_class == GFX9) {
7739          assert(has_ddx && has_ddy && ddx.size() == 1 && ddy.size() == 1);
7740          Temp zero = bld.copy(bld.def(v1), Operand(0u));
7741          derivs = {ddy, zero, ddy, zero};
7742       } else {
7743          for (unsigned i = 0; has_ddx && i < ddx.size(); i++)
7744             derivs.emplace_back(emit_extract_vector(ctx, ddx, i, v1));
7745          for (unsigned i = 0; has_ddy && i < ddy.size(); i++)
7746             derivs.emplace_back(emit_extract_vector(ctx, ddy, i, v1));
7747       }
7748       has_derivs = true;
7749    }
7750
7751    if (instr->coord_components > 1 &&
7752        instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
7753        instr->is_array &&
7754        instr->op != nir_texop_txf)
7755       coords[1] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coords[1]);
7756
7757    if (instr->coord_components > 2 &&
7758       (instr->sampler_dim == GLSL_SAMPLER_DIM_2D ||
7759        instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
7760        instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS ||
7761        instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
7762        instr->is_array &&
7763        instr->op != nir_texop_txf &&
7764        instr->op != nir_texop_txf_ms &&
7765        instr->op != nir_texop_fragment_fetch &&
7766        instr->op != nir_texop_fragment_mask_fetch)
7767       coords[2] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coords[2]);
7768
7769    if (ctx->options->chip_class == GFX9 &&
7770        instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
7771        instr->op != nir_texop_lod && instr->coord_components) {
7772       assert(coords.size() > 0 && coords.size() < 3);
7773
7774       coords.insert(std::next(coords.begin()), bld.copy(bld.def(v1), instr->op == nir_texop_txf ?
7775                                                                      Operand((uint32_t) 0) :
7776                                                                      Operand((uint32_t) 0x3f000000)));
7777    }
7778
7779    bool da = should_declare_array(ctx, instr->sampler_dim, instr->is_array);
7780
7781    if (instr->op == nir_texop_samples_identical)
7782       resource = fmask_ptr;
7783
7784    else if ((instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
7785              instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
7786             instr->op != nir_texop_txs &&
7787             instr->op != nir_texop_fragment_fetch &&
7788             instr->op != nir_texop_fragment_mask_fetch) {
7789       assert(has_sample_index);
7790       Operand op(sample_index);
7791       if (sample_index_cv)
7792          op = Operand(sample_index_cv->u32);
7793       sample_index = adjust_sample_index_using_fmask(ctx, da, coords, op, fmask_ptr);
7794    }
7795
7796    if (has_offset && (instr->op == nir_texop_txf || instr->op == nir_texop_txf_ms)) {
7797       for (unsigned i = 0; i < std::min(offset.size(), instr->coord_components); i++) {
7798          Temp off = emit_extract_vector(ctx, offset, i, v1);
7799          coords[i] = bld.vadd32(bld.def(v1), coords[i], off);
7800       }
7801       has_offset = false;
7802    }
7803
7804    /* Build tex instruction */
7805    unsigned dmask = nir_ssa_def_components_read(&instr->dest.ssa);
7806    unsigned dim = ctx->options->chip_class >= GFX10 && instr->sampler_dim != GLSL_SAMPLER_DIM_BUF
7807                   ? ac_get_sampler_dim(ctx->options->chip_class, instr->sampler_dim, instr->is_array)
7808                   : 0;
7809    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7810    Temp tmp_dst = dst;
7811
7812    /* gather4 selects the component by dmask and always returns vec4 */
7813    if (instr->op == nir_texop_tg4) {
7814       assert(instr->dest.ssa.num_components == 4);
7815       if (instr->is_shadow)
7816          dmask = 1;
7817       else
7818          dmask = 1 << instr->component;
7819       if (tg4_integer_cube_workaround || dst.type() == RegType::sgpr)
7820          tmp_dst = bld.tmp(v4);
7821    } else if (instr->op == nir_texop_samples_identical) {
7822       tmp_dst = bld.tmp(v1);
7823    } else if (util_bitcount(dmask) != instr->dest.ssa.num_components || dst.type() == RegType::sgpr) {
7824       tmp_dst = bld.tmp(RegClass(RegType::vgpr, util_bitcount(dmask)));
7825    }
7826
7827    aco_ptr<MIMG_instruction> tex;
7828    if (instr->op == nir_texop_txs || instr->op == nir_texop_query_levels) {
7829       if (!has_lod)
7830          lod = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
7831
7832       bool div_by_6 = instr->op == nir_texop_txs &&
7833                       instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
7834                       instr->is_array &&
7835                       (dmask & (1 << 2));
7836       if (tmp_dst.id() == dst.id() && div_by_6)
7837          tmp_dst = bld.tmp(tmp_dst.regClass());
7838
7839       tex.reset(create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 3, 1));
7840       tex->operands[0] = Operand(resource);
7841       tex->operands[1] = Operand(s4); /* no sampler */
7842       tex->operands[2] = Operand(as_vgpr(ctx,lod));
7843       if (ctx->options->chip_class == GFX9 &&
7844           instr->op == nir_texop_txs &&
7845           instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
7846           instr->is_array) {
7847          tex->dmask = (dmask & 0x1) | ((dmask & 0x2) << 1);
7848       } else if (instr->op == nir_texop_query_levels) {
7849          tex->dmask = 1 << 3;
7850       } else {
7851          tex->dmask = dmask;
7852       }
7853       tex->da = da;
7854       tex->definitions[0] = Definition(tmp_dst);
7855       tex->dim = dim;
7856       tex->can_reorder = true;
7857       ctx->block->instructions.emplace_back(std::move(tex));
7858
7859       if (div_by_6) {
7860          /* divide 3rd value by 6 by multiplying with magic number */
7861          emit_split_vector(ctx, tmp_dst, tmp_dst.size());
7862          Temp c = bld.copy(bld.def(s1), Operand((uint32_t) 0x2AAAAAAB));
7863          Temp by_6 = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), emit_extract_vector(ctx, tmp_dst, 2, v1), c);
7864          assert(instr->dest.ssa.num_components == 3);
7865          Temp tmp = dst.type() == RegType::vgpr ? dst : bld.tmp(v3);
7866          tmp_dst = bld.pseudo(aco_opcode::p_create_vector, Definition(tmp),
7867                               emit_extract_vector(ctx, tmp_dst, 0, v1),
7868                               emit_extract_vector(ctx, tmp_dst, 1, v1),
7869                               by_6);
7870
7871       }
7872
7873       expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, dmask);
7874       return;
7875    }
7876
7877    Temp tg4_compare_cube_wa64 = Temp();
7878
7879    if (tg4_integer_workarounds) {
7880       tex.reset(create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 3, 1));
7881       tex->operands[0] = Operand(resource);
7882       tex->operands[1] = Operand(s4); /* no sampler */
7883       tex->operands[2] = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
7884       tex->dim = dim;
7885       tex->dmask = 0x3;
7886       tex->da = da;
7887       Temp size = bld.tmp(v2);
7888       tex->definitions[0] = Definition(size);
7889       tex->can_reorder = true;
7890       ctx->block->instructions.emplace_back(std::move(tex));
7891       emit_split_vector(ctx, size, size.size());
7892
7893       Temp half_texel[2];
7894       for (unsigned i = 0; i < 2; i++) {
7895          half_texel[i] = emit_extract_vector(ctx, size, i, v1);
7896          half_texel[i] = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), half_texel[i]);
7897          half_texel[i] = bld.vop1(aco_opcode::v_rcp_iflag_f32, bld.def(v1), half_texel[i]);
7898          half_texel[i] = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0xbf000000/*-0.5*/), half_texel[i]);
7899       }
7900
7901       Temp new_coords[2] = {
7902          bld.vop2(aco_opcode::v_add_f32, bld.def(v1), coords[0], half_texel[0]),
7903          bld.vop2(aco_opcode::v_add_f32, bld.def(v1), coords[1], half_texel[1])
7904       };
7905
7906       if (tg4_integer_cube_workaround) {
7907          // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
7908          Temp desc[resource.size()];
7909          aco_ptr<Instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector,
7910                                                                            Format::PSEUDO, 1, resource.size())};
7911          split->operands[0] = Operand(resource);
7912          for (unsigned i = 0; i < resource.size(); i++) {
7913             desc[i] = bld.tmp(s1);
7914             split->definitions[i] = Definition(desc[i]);
7915          }
7916          ctx->block->instructions.emplace_back(std::move(split));
7917
7918          Temp dfmt = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), desc[1], Operand(20u | (6u << 16)));
7919          Temp compare_cube_wa = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), dfmt,
7920                                          Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8));
7921
7922          Temp nfmt;
7923          if (stype == GLSL_TYPE_UINT) {
7924             nfmt = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1),
7925                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED),
7926                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT),
7927                             bld.scc(compare_cube_wa));
7928          } else {
7929             nfmt = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1),
7930                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED),
7931                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT),
7932                             bld.scc(compare_cube_wa));
7933          }
7934          tg4_compare_cube_wa64 = bld.tmp(bld.lm);
7935          bool_to_vector_condition(ctx, compare_cube_wa, tg4_compare_cube_wa64);
7936
7937          nfmt = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), nfmt, Operand(26u));
7938
7939          desc[1] = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), desc[1],
7940                             Operand((uint32_t)C_008F14_NUM_FORMAT));
7941          desc[1] = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), desc[1], nfmt);
7942
7943          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector,
7944                                                                          Format::PSEUDO, resource.size(), 1)};
7945          for (unsigned i = 0; i < resource.size(); i++)
7946             vec->operands[i] = Operand(desc[i]);
7947          resource = bld.tmp(resource.regClass());
7948          vec->definitions[0] = Definition(resource);
7949          ctx->block->instructions.emplace_back(std::move(vec));
7950
7951          new_coords[0] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
7952                                   new_coords[0], coords[0], tg4_compare_cube_wa64);
7953          new_coords[1] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
7954                                   new_coords[1], coords[1], tg4_compare_cube_wa64);
7955       }
7956       coords[0] = new_coords[0];
7957       coords[1] = new_coords[1];
7958    }
7959
7960    if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
7961       //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
7962
7963       assert(coords.size() == 1);
7964       unsigned last_bit = util_last_bit(nir_ssa_def_components_read(&instr->dest.ssa));
7965       aco_opcode op;
7966       switch (last_bit) {
7967       case 1:
7968          op = aco_opcode::buffer_load_format_x; break;
7969       case 2:
7970          op = aco_opcode::buffer_load_format_xy; break;
7971       case 3:
7972          op = aco_opcode::buffer_load_format_xyz; break;
7973       case 4:
7974          op = aco_opcode::buffer_load_format_xyzw; break;
7975       default:
7976          unreachable("Tex instruction loads more than 4 components.");
7977       }
7978
7979       /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
7980       if (last_bit == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
7981          tmp_dst = dst;
7982       else
7983          tmp_dst = bld.tmp(RegType::vgpr, last_bit);
7984
7985       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
7986       mubuf->operands[0] = Operand(resource);
7987       mubuf->operands[1] = Operand(coords[0]);
7988       mubuf->operands[2] = Operand((uint32_t) 0);
7989       mubuf->definitions[0] = Definition(tmp_dst);
7990       mubuf->idxen = true;
7991       mubuf->can_reorder = true;
7992       ctx->block->instructions.emplace_back(std::move(mubuf));
7993
7994       expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, (1 << last_bit) - 1);
7995       return;
7996    }
7997
7998    /* gather MIMG address components */
7999    std::vector<Temp> args;
8000    if (has_offset)
8001       args.emplace_back(offset);
8002    if (has_bias)
8003       args.emplace_back(bias);
8004    if (has_compare)
8005       args.emplace_back(compare);
8006    if (has_derivs)
8007       args.insert(args.end(), derivs.begin(), derivs.end());
8008
8009    args.insert(args.end(), coords.begin(), coords.end());
8010    if (has_sample_index)
8011       args.emplace_back(sample_index);
8012    if (has_lod)
8013       args.emplace_back(lod);
8014
8015    Temp arg = bld.tmp(RegClass(RegType::vgpr, args.size()));
8016    aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, args.size(), 1)};
8017    vec->definitions[0] = Definition(arg);
8018    for (unsigned i = 0; i < args.size(); i++)
8019       vec->operands[i] = Operand(args[i]);
8020    ctx->block->instructions.emplace_back(std::move(vec));
8021
8022
8023    if (instr->op == nir_texop_txf ||
8024        instr->op == nir_texop_txf_ms ||
8025        instr->op == nir_texop_samples_identical ||
8026        instr->op == nir_texop_fragment_fetch ||
8027        instr->op == nir_texop_fragment_mask_fetch) {
8028       aco_opcode op = level_zero || instr->sampler_dim == GLSL_SAMPLER_DIM_MS || instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS ? aco_opcode::image_load : aco_opcode::image_load_mip;
8029       tex.reset(create_instruction<MIMG_instruction>(op, Format::MIMG, 3, 1));
8030       tex->operands[0] = Operand(resource);
8031       tex->operands[1] = Operand(s4); /* no sampler */
8032       tex->operands[2] = Operand(arg);
8033       tex->dim = dim;
8034       tex->dmask = dmask;
8035       tex->unrm = true;
8036       tex->da = da;
8037       tex->definitions[0] = Definition(tmp_dst);
8038       tex->can_reorder = true;
8039       ctx->block->instructions.emplace_back(std::move(tex));
8040
8041       if (instr->op == nir_texop_samples_identical) {
8042          assert(dmask == 1 && dst.regClass() == v1);
8043          assert(dst.id() != tmp_dst.id());
8044
8045          Temp tmp = bld.tmp(bld.lm);
8046          bld.vopc(aco_opcode::v_cmp_eq_u32, Definition(tmp), Operand(0u), tmp_dst).def(0).setHint(vcc);
8047          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand((uint32_t)-1), tmp);
8048
8049       } else {
8050          expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, dmask);
8051       }
8052       return;
8053    }
8054
8055    // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8056    aco_opcode opcode = aco_opcode::image_sample;
8057    if (has_offset) { /* image_sample_*_o */
8058       if (has_compare) {
8059          opcode = aco_opcode::image_sample_c_o;
8060          if (has_derivs)
8061             opcode = aco_opcode::image_sample_c_d_o;
8062          if (has_bias)
8063             opcode = aco_opcode::image_sample_c_b_o;
8064          if (level_zero)
8065             opcode = aco_opcode::image_sample_c_lz_o;
8066          if (has_lod)
8067             opcode = aco_opcode::image_sample_c_l_o;
8068       } else {
8069          opcode = aco_opcode::image_sample_o;
8070          if (has_derivs)
8071             opcode = aco_opcode::image_sample_d_o;
8072          if (has_bias)
8073             opcode = aco_opcode::image_sample_b_o;
8074          if (level_zero)
8075             opcode = aco_opcode::image_sample_lz_o;
8076          if (has_lod)
8077             opcode = aco_opcode::image_sample_l_o;
8078       }
8079    } else { /* no offset */
8080       if (has_compare) {
8081          opcode = aco_opcode::image_sample_c;
8082          if (has_derivs)
8083             opcode = aco_opcode::image_sample_c_d;
8084          if (has_bias)
8085             opcode = aco_opcode::image_sample_c_b;
8086          if (level_zero)
8087             opcode = aco_opcode::image_sample_c_lz;
8088          if (has_lod)
8089             opcode = aco_opcode::image_sample_c_l;
8090       } else {
8091          opcode = aco_opcode::image_sample;
8092          if (has_derivs)
8093             opcode = aco_opcode::image_sample_d;
8094          if (has_bias)
8095             opcode = aco_opcode::image_sample_b;
8096          if (level_zero)
8097             opcode = aco_opcode::image_sample_lz;
8098          if (has_lod)
8099             opcode = aco_opcode::image_sample_l;
8100       }
8101    }
8102
8103    if (instr->op == nir_texop_tg4) {
8104       if (has_offset) {
8105          opcode = aco_opcode::image_gather4_lz_o;
8106          if (has_compare)
8107             opcode = aco_opcode::image_gather4_c_lz_o;
8108       } else {
8109          opcode = aco_opcode::image_gather4_lz;
8110          if (has_compare)
8111             opcode = aco_opcode::image_gather4_c_lz;
8112       }
8113    } else if (instr->op == nir_texop_lod) {
8114       opcode = aco_opcode::image_get_lod;
8115    }
8116
8117    /* we don't need the bias, sample index, compare value or offset to be
8118     * computed in WQM but if the p_create_vector copies the coordinates, then it
8119     * needs to be in WQM */
8120    if (ctx->stage == fragment_fs &&
8121        !has_derivs && !has_lod && !level_zero &&
8122        instr->sampler_dim != GLSL_SAMPLER_DIM_MS &&
8123        instr->sampler_dim != GLSL_SAMPLER_DIM_SUBPASS_MS)
8124       arg = emit_wqm(ctx, arg, bld.tmp(arg.regClass()), true);
8125
8126    tex.reset(create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 1));
8127    tex->operands[0] = Operand(resource);
8128    tex->operands[1] = Operand(sampler);
8129    tex->operands[2] = Operand(arg);
8130    tex->dim = dim;
8131    tex->dmask = dmask;
8132    tex->da = da;
8133    tex->definitions[0] = Definition(tmp_dst);
8134    tex->can_reorder = true;
8135    ctx->block->instructions.emplace_back(std::move(tex));
8136
8137    if (tg4_integer_cube_workaround) {
8138       assert(tmp_dst.id() != dst.id());
8139       assert(tmp_dst.size() == dst.size() && dst.size() == 4);
8140
8141       emit_split_vector(ctx, tmp_dst, tmp_dst.size());
8142       Temp val[4];
8143       for (unsigned i = 0; i < dst.size(); i++) {
8144          val[i] = emit_extract_vector(ctx, tmp_dst, i, v1);
8145          Temp cvt_val;
8146          if (stype == GLSL_TYPE_UINT)
8147             cvt_val = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), val[i]);
8148          else
8149             cvt_val = bld.vop1(aco_opcode::v_cvt_i32_f32, bld.def(v1), val[i]);
8150          val[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), val[i], cvt_val, tg4_compare_cube_wa64);
8151       }
8152       Temp tmp = dst.regClass() == v4 ? dst : bld.tmp(v4);
8153       tmp_dst = bld.pseudo(aco_opcode::p_create_vector, Definition(tmp),
8154                            val[0], val[1], val[2], val[3]);
8155    }
8156    unsigned mask = instr->op == nir_texop_tg4 ? 0xF : dmask;
8157    expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, mask);
8158
8159 }
8160
8161
8162 Operand get_phi_operand(isel_context *ctx, nir_ssa_def *ssa)
8163 {
8164    Temp tmp = get_ssa_temp(ctx, ssa);
8165    if (ssa->parent_instr->type == nir_instr_type_ssa_undef)
8166       return Operand(tmp.regClass());
8167    else
8168       return Operand(tmp);
8169 }
8170
8171 void visit_phi(isel_context *ctx, nir_phi_instr *instr)
8172 {
8173    aco_ptr<Pseudo_instruction> phi;
8174    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
8175    assert(instr->dest.ssa.bit_size != 1 || dst.regClass() == ctx->program->lane_mask);
8176
8177    bool logical = !dst.is_linear() || ctx->divergent_vals[instr->dest.ssa.index];
8178    logical |= ctx->block->kind & block_kind_merge;
8179    aco_opcode opcode = logical ? aco_opcode::p_phi : aco_opcode::p_linear_phi;
8180
8181    /* we want a sorted list of sources, since the predecessor list is also sorted */
8182    std::map<unsigned, nir_ssa_def*> phi_src;
8183    nir_foreach_phi_src(src, instr)
8184       phi_src[src->pred->index] = src->src.ssa;
8185
8186    std::vector<unsigned>& preds = logical ? ctx->block->logical_preds : ctx->block->linear_preds;
8187    unsigned num_operands = 0;
8188    Operand operands[std::max(exec_list_length(&instr->srcs), (unsigned)preds.size())];
8189    unsigned num_defined = 0;
8190    unsigned cur_pred_idx = 0;
8191    for (std::pair<unsigned, nir_ssa_def *> src : phi_src) {
8192       if (cur_pred_idx < preds.size()) {
8193          /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8194          unsigned block = ctx->cf_info.nir_to_aco[src.first];
8195          unsigned skipped = 0;
8196          while (cur_pred_idx + skipped < preds.size() && preds[cur_pred_idx + skipped] != block)
8197             skipped++;
8198          if (cur_pred_idx + skipped < preds.size()) {
8199             for (unsigned i = 0; i < skipped; i++)
8200                operands[num_operands++] = Operand(dst.regClass());
8201             cur_pred_idx += skipped;
8202          } else {
8203             continue;
8204          }
8205       }
8206       cur_pred_idx++;
8207       Operand op = get_phi_operand(ctx, src.second);
8208       operands[num_operands++] = op;
8209       num_defined += !op.isUndefined();
8210    }
8211    /* handle block_kind_continue_or_break at loop exit blocks */
8212    while (cur_pred_idx++ < preds.size())
8213       operands[num_operands++] = Operand(dst.regClass());
8214
8215    if (num_defined == 0) {
8216       Builder bld(ctx->program, ctx->block);
8217       if (dst.regClass() == s1) {
8218          bld.sop1(aco_opcode::s_mov_b32, Definition(dst), Operand(0u));
8219       } else if (dst.regClass() == v1) {
8220          bld.vop1(aco_opcode::v_mov_b32, Definition(dst), Operand(0u));
8221       } else {
8222          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
8223          for (unsigned i = 0; i < dst.size(); i++)
8224             vec->operands[i] = Operand(0u);
8225          vec->definitions[0] = Definition(dst);
8226          ctx->block->instructions.emplace_back(std::move(vec));
8227       }
8228       return;
8229    }
8230
8231    /* we can use a linear phi in some cases if one src is undef */
8232    if (dst.is_linear() && ctx->block->kind & block_kind_merge && num_defined == 1) {
8233       phi.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_linear_phi, Format::PSEUDO, num_operands, 1));
8234
8235       Block *linear_else = &ctx->program->blocks[ctx->block->linear_preds[1]];
8236       Block *invert = &ctx->program->blocks[linear_else->linear_preds[0]];
8237       assert(invert->kind & block_kind_invert);
8238
8239       unsigned then_block = invert->linear_preds[0];
8240
8241       Block* insert_block = NULL;
8242       for (unsigned i = 0; i < num_operands; i++) {
8243          Operand op = operands[i];
8244          if (op.isUndefined())
8245             continue;
8246          insert_block = ctx->block->logical_preds[i] == then_block ? invert : ctx->block;
8247          phi->operands[0] = op;
8248          break;
8249       }
8250       assert(insert_block); /* should be handled by the "num_defined == 0" case above */
8251       phi->operands[1] = Operand(dst.regClass());
8252       phi->definitions[0] = Definition(dst);
8253       insert_block->instructions.emplace(insert_block->instructions.begin(), std::move(phi));
8254       return;
8255    }
8256
8257    /* try to scalarize vector phis */
8258    if (instr->dest.ssa.bit_size != 1 && dst.size() > 1) {
8259       // TODO: scalarize linear phis on divergent ifs
8260       bool can_scalarize = (opcode == aco_opcode::p_phi || !(ctx->block->kind & block_kind_merge));
8261       std::array<Temp, NIR_MAX_VEC_COMPONENTS> new_vec;
8262       for (unsigned i = 0; can_scalarize && (i < num_operands); i++) {
8263          Operand src = operands[i];
8264          if (src.isTemp() && ctx->allocated_vec.find(src.tempId()) == ctx->allocated_vec.end())
8265             can_scalarize = false;
8266       }
8267       if (can_scalarize) {
8268          unsigned num_components = instr->dest.ssa.num_components;
8269          assert(dst.size() % num_components == 0);
8270          RegClass rc = RegClass(dst.type(), dst.size() / num_components);
8271
8272          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1)};
8273          for (unsigned k = 0; k < num_components; k++) {
8274             phi.reset(create_instruction<Pseudo_instruction>(opcode, Format::PSEUDO, num_operands, 1));
8275             for (unsigned i = 0; i < num_operands; i++) {
8276                Operand src = operands[i];
8277                phi->operands[i] = src.isTemp() ? Operand(ctx->allocated_vec[src.tempId()][k]) : Operand(rc);
8278             }
8279             Temp phi_dst = {ctx->program->allocateId(), rc};
8280             phi->definitions[0] = Definition(phi_dst);
8281             ctx->block->instructions.emplace(ctx->block->instructions.begin(), std::move(phi));
8282             new_vec[k] = phi_dst;
8283             vec->operands[k] = Operand(phi_dst);
8284          }
8285          vec->definitions[0] = Definition(dst);
8286          ctx->block->instructions.emplace_back(std::move(vec));
8287          ctx->allocated_vec.emplace(dst.id(), new_vec);
8288          return;
8289       }
8290    }
8291
8292    phi.reset(create_instruction<Pseudo_instruction>(opcode, Format::PSEUDO, num_operands, 1));
8293    for (unsigned i = 0; i < num_operands; i++)
8294       phi->operands[i] = operands[i];
8295    phi->definitions[0] = Definition(dst);
8296    ctx->block->instructions.emplace(ctx->block->instructions.begin(), std::move(phi));
8297 }
8298
8299
8300 void visit_undef(isel_context *ctx, nir_ssa_undef_instr *instr)
8301 {
8302    Temp dst = get_ssa_temp(ctx, &instr->def);
8303
8304    assert(dst.type() == RegType::sgpr);
8305
8306    if (dst.size() == 1) {
8307       Builder(ctx->program, ctx->block).copy(Definition(dst), Operand(0u));
8308    } else {
8309       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
8310       for (unsigned i = 0; i < dst.size(); i++)
8311          vec->operands[i] = Operand(0u);
8312       vec->definitions[0] = Definition(dst);
8313       ctx->block->instructions.emplace_back(std::move(vec));
8314    }
8315 }
8316
8317 void visit_jump(isel_context *ctx, nir_jump_instr *instr)
8318 {
8319    Builder bld(ctx->program, ctx->block);
8320    Block *logical_target;
8321    append_logical_end(ctx->block);
8322    unsigned idx = ctx->block->index;
8323
8324    switch (instr->type) {
8325    case nir_jump_break:
8326       logical_target = ctx->cf_info.parent_loop.exit;
8327       add_logical_edge(idx, logical_target);
8328       ctx->block->kind |= block_kind_break;
8329
8330       if (!ctx->cf_info.parent_if.is_divergent &&
8331           !ctx->cf_info.parent_loop.has_divergent_continue) {
8332          /* uniform break - directly jump out of the loop */
8333          ctx->block->kind |= block_kind_uniform;
8334          ctx->cf_info.has_branch = true;
8335          bld.branch(aco_opcode::p_branch);
8336          add_linear_edge(idx, logical_target);
8337          return;
8338       }
8339       ctx->cf_info.parent_loop.has_divergent_branch = true;
8340       ctx->cf_info.nir_to_aco[instr->instr.block->index] = ctx->block->index;
8341       break;
8342    case nir_jump_continue:
8343       logical_target = &ctx->program->blocks[ctx->cf_info.parent_loop.header_idx];
8344       add_logical_edge(idx, logical_target);
8345       ctx->block->kind |= block_kind_continue;
8346
8347       if (ctx->cf_info.parent_if.is_divergent) {
8348          /* for potential uniform breaks after this continue,
8349             we must ensure that they are handled correctly */
8350          ctx->cf_info.parent_loop.has_divergent_continue = true;
8351          ctx->cf_info.parent_loop.has_divergent_branch = true;
8352          ctx->cf_info.nir_to_aco[instr->instr.block->index] = ctx->block->index;
8353       } else {
8354          /* uniform continue - directly jump to the loop header */
8355          ctx->block->kind |= block_kind_uniform;
8356          ctx->cf_info.has_branch = true;
8357          bld.branch(aco_opcode::p_branch);
8358          add_linear_edge(idx, logical_target);
8359          return;
8360       }
8361       break;
8362    default:
8363       fprintf(stderr, "Unknown NIR jump instr: ");
8364       nir_print_instr(&instr->instr, stderr);
8365       fprintf(stderr, "\n");
8366       abort();
8367    }
8368
8369    if (ctx->cf_info.parent_if.is_divergent && !ctx->cf_info.exec_potentially_empty_break) {
8370       ctx->cf_info.exec_potentially_empty_break = true;
8371       ctx->cf_info.exec_potentially_empty_break_depth = ctx->cf_info.loop_nest_depth;
8372    }
8373
8374    /* remove critical edges from linear CFG */
8375    bld.branch(aco_opcode::p_branch);
8376    Block* break_block = ctx->program->create_and_insert_block();
8377    break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8378    break_block->kind |= block_kind_uniform;
8379    add_linear_edge(idx, break_block);
8380    /* the loop_header pointer might be invalidated by this point */
8381    if (instr->type == nir_jump_continue)
8382       logical_target = &ctx->program->blocks[ctx->cf_info.parent_loop.header_idx];
8383    add_linear_edge(break_block->index, logical_target);
8384    bld.reset(break_block);
8385    bld.branch(aco_opcode::p_branch);
8386
8387    Block* continue_block = ctx->program->create_and_insert_block();
8388    continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8389    add_linear_edge(idx, continue_block);
8390    append_logical_start(continue_block);
8391    ctx->block = continue_block;
8392    return;
8393 }
8394
8395 void visit_block(isel_context *ctx, nir_block *block)
8396 {
8397    nir_foreach_instr(instr, block) {
8398       switch (instr->type) {
8399       case nir_instr_type_alu:
8400          visit_alu_instr(ctx, nir_instr_as_alu(instr));
8401          break;
8402       case nir_instr_type_load_const:
8403          visit_load_const(ctx, nir_instr_as_load_const(instr));
8404          break;
8405       case nir_instr_type_intrinsic:
8406          visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
8407          break;
8408       case nir_instr_type_tex:
8409          visit_tex(ctx, nir_instr_as_tex(instr));
8410          break;
8411       case nir_instr_type_phi:
8412          visit_phi(ctx, nir_instr_as_phi(instr));
8413          break;
8414       case nir_instr_type_ssa_undef:
8415          visit_undef(ctx, nir_instr_as_ssa_undef(instr));
8416          break;
8417       case nir_instr_type_deref:
8418          break;
8419       case nir_instr_type_jump:
8420          visit_jump(ctx, nir_instr_as_jump(instr));
8421          break;
8422       default:
8423          fprintf(stderr, "Unknown NIR instr type: ");
8424          nir_print_instr(instr, stderr);
8425          fprintf(stderr, "\n");
8426          //abort();
8427       }
8428    }
8429
8430    if (!ctx->cf_info.parent_loop.has_divergent_branch)
8431       ctx->cf_info.nir_to_aco[block->index] = ctx->block->index;
8432 }
8433
8434
8435
8436 static void visit_loop(isel_context *ctx, nir_loop *loop)
8437 {
8438    //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
8439    append_logical_end(ctx->block);
8440    ctx->block->kind |= block_kind_loop_preheader | block_kind_uniform;
8441    Builder bld(ctx->program, ctx->block);
8442    bld.branch(aco_opcode::p_branch);
8443    unsigned loop_preheader_idx = ctx->block->index;
8444
8445    Block loop_exit = Block();
8446    loop_exit.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8447    loop_exit.kind |= (block_kind_loop_exit | (ctx->block->kind & block_kind_top_level));
8448
8449    Block* loop_header = ctx->program->create_and_insert_block();
8450    loop_header->loop_nest_depth = ctx->cf_info.loop_nest_depth + 1;
8451    loop_header->kind |= block_kind_loop_header;
8452    add_edge(loop_preheader_idx, loop_header);
8453    ctx->block = loop_header;
8454
8455    /* emit loop body */
8456    unsigned loop_header_idx = loop_header->index;
8457    loop_info_RAII loop_raii(ctx, loop_header_idx, &loop_exit);
8458    append_logical_start(ctx->block);
8459    visit_cf_list(ctx, &loop->body);
8460
8461    //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
8462    if (!ctx->cf_info.has_branch) {
8463       append_logical_end(ctx->block);
8464       if (ctx->cf_info.exec_potentially_empty_discard || ctx->cf_info.exec_potentially_empty_break) {
8465          /* Discards can result in code running with an empty exec mask.
8466           * This would result in divergent breaks not ever being taken. As a
8467           * workaround, break the loop when the loop mask is empty instead of
8468           * always continuing. */
8469          ctx->block->kind |= (block_kind_continue_or_break | block_kind_uniform);
8470          unsigned block_idx = ctx->block->index;
8471
8472          /* create helper blocks to avoid critical edges */
8473          Block *break_block = ctx->program->create_and_insert_block();
8474          break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8475          break_block->kind = block_kind_uniform;
8476          bld.reset(break_block);
8477          bld.branch(aco_opcode::p_branch);
8478          add_linear_edge(block_idx, break_block);
8479          add_linear_edge(break_block->index, &loop_exit);
8480
8481          Block *continue_block = ctx->program->create_and_insert_block();
8482          continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8483          continue_block->kind = block_kind_uniform;
8484          bld.reset(continue_block);
8485          bld.branch(aco_opcode::p_branch);
8486          add_linear_edge(block_idx, continue_block);
8487          add_linear_edge(continue_block->index, &ctx->program->blocks[loop_header_idx]);
8488
8489          if (!ctx->cf_info.parent_loop.has_divergent_branch)
8490             add_logical_edge(block_idx, &ctx->program->blocks[loop_header_idx]);
8491          ctx->block = &ctx->program->blocks[block_idx];
8492       } else {
8493          ctx->block->kind |= (block_kind_continue | block_kind_uniform);
8494          if (!ctx->cf_info.parent_loop.has_divergent_branch)
8495             add_edge(ctx->block->index, &ctx->program->blocks[loop_header_idx]);
8496          else
8497             add_linear_edge(ctx->block->index, &ctx->program->blocks[loop_header_idx]);
8498       }
8499
8500       bld.reset(ctx->block);
8501       bld.branch(aco_opcode::p_branch);
8502    }
8503
8504    /* fixup phis in loop header from unreachable blocks */
8505    if (ctx->cf_info.has_branch || ctx->cf_info.parent_loop.has_divergent_branch) {
8506       bool linear = ctx->cf_info.has_branch;
8507       bool logical = ctx->cf_info.has_branch || ctx->cf_info.parent_loop.has_divergent_branch;
8508       for (aco_ptr<Instruction>& instr : ctx->program->blocks[loop_header_idx].instructions) {
8509          if ((logical && instr->opcode == aco_opcode::p_phi) ||
8510              (linear && instr->opcode == aco_opcode::p_linear_phi)) {
8511             /* the last operand should be the one that needs to be removed */
8512             instr->operands.pop_back();
8513          } else if (!is_phi(instr)) {
8514             break;
8515          }
8516       }
8517    }
8518
8519    ctx->cf_info.has_branch = false;
8520
8521    // TODO: if the loop has not a single exit, we must add one °°
8522    /* emit loop successor block */
8523    ctx->block = ctx->program->insert_block(std::move(loop_exit));
8524    append_logical_start(ctx->block);
8525
8526    #if 0
8527    // TODO: check if it is beneficial to not branch on continues
8528    /* trim linear phis in loop header */
8529    for (auto&& instr : loop_entry->instructions) {
8530       if (instr->opcode == aco_opcode::p_linear_phi) {
8531          aco_ptr<Pseudo_instruction> new_phi{create_instruction<Pseudo_instruction>(aco_opcode::p_linear_phi, Format::PSEUDO, loop_entry->linear_predecessors.size(), 1)};
8532          new_phi->definitions[0] = instr->definitions[0];
8533          for (unsigned i = 0; i < new_phi->operands.size(); i++)
8534             new_phi->operands[i] = instr->operands[i];
8535          /* check that the remaining operands are all the same */
8536          for (unsigned i = new_phi->operands.size(); i < instr->operands.size(); i++)
8537             assert(instr->operands[i].tempId() == instr->operands.back().tempId());
8538          instr.swap(new_phi);
8539       } else if (instr->opcode == aco_opcode::p_phi) {
8540          continue;
8541       } else {
8542          break;
8543       }
8544    }
8545    #endif
8546 }
8547
8548 static void begin_divergent_if_then(isel_context *ctx, if_context *ic, Temp cond)
8549 {
8550    ic->cond = cond;
8551
8552    append_logical_end(ctx->block);
8553    ctx->block->kind |= block_kind_branch;
8554
8555    /* branch to linear then block */
8556    assert(cond.regClass() == ctx->program->lane_mask);
8557    aco_ptr<Pseudo_branch_instruction> branch;
8558    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_z, Format::PSEUDO_BRANCH, 1, 0));
8559    branch->operands[0] = Operand(cond);
8560    ctx->block->instructions.push_back(std::move(branch));
8561
8562    ic->BB_if_idx = ctx->block->index;
8563    ic->BB_invert = Block();
8564    ic->BB_invert.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8565    /* Invert blocks are intentionally not marked as top level because they
8566     * are not part of the logical cfg. */
8567    ic->BB_invert.kind |= block_kind_invert;
8568    ic->BB_endif = Block();
8569    ic->BB_endif.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8570    ic->BB_endif.kind |= (block_kind_merge | (ctx->block->kind & block_kind_top_level));
8571
8572    ic->exec_potentially_empty_discard_old = ctx->cf_info.exec_potentially_empty_discard;
8573    ic->exec_potentially_empty_break_old = ctx->cf_info.exec_potentially_empty_break;
8574    ic->exec_potentially_empty_break_depth_old = ctx->cf_info.exec_potentially_empty_break_depth;
8575    ic->divergent_old = ctx->cf_info.parent_if.is_divergent;
8576    ctx->cf_info.parent_if.is_divergent = true;
8577
8578    /* divergent branches use cbranch_execz */
8579    ctx->cf_info.exec_potentially_empty_discard = false;
8580    ctx->cf_info.exec_potentially_empty_break = false;
8581    ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8582
8583    /** emit logical then block */
8584    Block* BB_then_logical = ctx->program->create_and_insert_block();
8585    BB_then_logical->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8586    add_edge(ic->BB_if_idx, BB_then_logical);
8587    ctx->block = BB_then_logical;
8588    append_logical_start(BB_then_logical);
8589 }
8590
8591 static void begin_divergent_if_else(isel_context *ctx, if_context *ic)
8592 {
8593    Block *BB_then_logical = ctx->block;
8594    append_logical_end(BB_then_logical);
8595     /* branch from logical then block to invert block */
8596    aco_ptr<Pseudo_branch_instruction> branch;
8597    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8598    BB_then_logical->instructions.emplace_back(std::move(branch));
8599    add_linear_edge(BB_then_logical->index, &ic->BB_invert);
8600    if (!ctx->cf_info.parent_loop.has_divergent_branch)
8601       add_logical_edge(BB_then_logical->index, &ic->BB_endif);
8602    BB_then_logical->kind |= block_kind_uniform;
8603    assert(!ctx->cf_info.has_branch);
8604    ic->then_branch_divergent = ctx->cf_info.parent_loop.has_divergent_branch;
8605    ctx->cf_info.parent_loop.has_divergent_branch = false;
8606
8607    /** emit linear then block */
8608    Block* BB_then_linear = ctx->program->create_and_insert_block();
8609    BB_then_linear->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8610    BB_then_linear->kind |= block_kind_uniform;
8611    add_linear_edge(ic->BB_if_idx, BB_then_linear);
8612    /* branch from linear then block to invert block */
8613    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8614    BB_then_linear->instructions.emplace_back(std::move(branch));
8615    add_linear_edge(BB_then_linear->index, &ic->BB_invert);
8616
8617    /** emit invert merge block */
8618    ctx->block = ctx->program->insert_block(std::move(ic->BB_invert));
8619    ic->invert_idx = ctx->block->index;
8620
8621    /* branch to linear else block (skip else) */
8622    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_nz, Format::PSEUDO_BRANCH, 1, 0));
8623    branch->operands[0] = Operand(ic->cond);
8624    ctx->block->instructions.push_back(std::move(branch));
8625
8626    ic->exec_potentially_empty_discard_old |= ctx->cf_info.exec_potentially_empty_discard;
8627    ic->exec_potentially_empty_break_old |= ctx->cf_info.exec_potentially_empty_break;
8628    ic->exec_potentially_empty_break_depth_old =
8629       std::min(ic->exec_potentially_empty_break_depth_old, ctx->cf_info.exec_potentially_empty_break_depth);
8630    /* divergent branches use cbranch_execz */
8631    ctx->cf_info.exec_potentially_empty_discard = false;
8632    ctx->cf_info.exec_potentially_empty_break = false;
8633    ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8634
8635    /** emit logical else block */
8636    Block* BB_else_logical = ctx->program->create_and_insert_block();
8637    BB_else_logical->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8638    add_logical_edge(ic->BB_if_idx, BB_else_logical);
8639    add_linear_edge(ic->invert_idx, BB_else_logical);
8640    ctx->block = BB_else_logical;
8641    append_logical_start(BB_else_logical);
8642 }
8643
8644 static void end_divergent_if(isel_context *ctx, if_context *ic)
8645 {
8646    Block *BB_else_logical = ctx->block;
8647    append_logical_end(BB_else_logical);
8648
8649    /* branch from logical else block to endif block */
8650    aco_ptr<Pseudo_branch_instruction> branch;
8651    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8652    BB_else_logical->instructions.emplace_back(std::move(branch));
8653    add_linear_edge(BB_else_logical->index, &ic->BB_endif);
8654    if (!ctx->cf_info.parent_loop.has_divergent_branch)
8655       add_logical_edge(BB_else_logical->index, &ic->BB_endif);
8656    BB_else_logical->kind |= block_kind_uniform;
8657
8658    assert(!ctx->cf_info.has_branch);
8659    ctx->cf_info.parent_loop.has_divergent_branch &= ic->then_branch_divergent;
8660
8661
8662    /** emit linear else block */
8663    Block* BB_else_linear = ctx->program->create_and_insert_block();
8664    BB_else_linear->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8665    BB_else_linear->kind |= block_kind_uniform;
8666    add_linear_edge(ic->invert_idx, BB_else_linear);
8667
8668    /* branch from linear else block to endif block */
8669    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8670    BB_else_linear->instructions.emplace_back(std::move(branch));
8671    add_linear_edge(BB_else_linear->index, &ic->BB_endif);
8672
8673
8674    /** emit endif merge block */
8675    ctx->block = ctx->program->insert_block(std::move(ic->BB_endif));
8676    append_logical_start(ctx->block);
8677
8678
8679    ctx->cf_info.parent_if.is_divergent = ic->divergent_old;
8680    ctx->cf_info.exec_potentially_empty_discard |= ic->exec_potentially_empty_discard_old;
8681    ctx->cf_info.exec_potentially_empty_break |= ic->exec_potentially_empty_break_old;
8682    ctx->cf_info.exec_potentially_empty_break_depth =
8683       std::min(ic->exec_potentially_empty_break_depth_old, ctx->cf_info.exec_potentially_empty_break_depth);
8684    if (ctx->cf_info.loop_nest_depth == ctx->cf_info.exec_potentially_empty_break_depth &&
8685        !ctx->cf_info.parent_if.is_divergent) {
8686       ctx->cf_info.exec_potentially_empty_break = false;
8687       ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8688    }
8689    /* uniform control flow never has an empty exec-mask */
8690    if (!ctx->cf_info.loop_nest_depth && !ctx->cf_info.parent_if.is_divergent) {
8691       ctx->cf_info.exec_potentially_empty_discard = false;
8692       ctx->cf_info.exec_potentially_empty_break = false;
8693       ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8694    }
8695 }
8696
8697 static void visit_if(isel_context *ctx, nir_if *if_stmt)
8698 {
8699    Temp cond = get_ssa_temp(ctx, if_stmt->condition.ssa);
8700    Builder bld(ctx->program, ctx->block);
8701    aco_ptr<Pseudo_branch_instruction> branch;
8702
8703    if (!ctx->divergent_vals[if_stmt->condition.ssa->index]) { /* uniform condition */
8704       /**
8705        * Uniform conditionals are represented in the following way*) :
8706        *
8707        * The linear and logical CFG:
8708        *                        BB_IF
8709        *                        /    \
8710        *       BB_THEN (logical)      BB_ELSE (logical)
8711        *                        \    /
8712        *                        BB_ENDIF
8713        *
8714        * *) Exceptions may be due to break and continue statements within loops
8715        *    If a break/continue happens within uniform control flow, it branches
8716        *    to the loop exit/entry block. Otherwise, it branches to the next
8717        *    merge block.
8718        **/
8719       append_logical_end(ctx->block);
8720       ctx->block->kind |= block_kind_uniform;
8721
8722       /* emit branch */
8723       assert(cond.regClass() == bld.lm);
8724       // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
8725       cond = bool_to_scalar_condition(ctx, cond);
8726
8727       branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_z, Format::PSEUDO_BRANCH, 1, 0));
8728       branch->operands[0] = Operand(cond);
8729       branch->operands[0].setFixed(scc);
8730       ctx->block->instructions.emplace_back(std::move(branch));
8731
8732       unsigned BB_if_idx = ctx->block->index;
8733       Block BB_endif = Block();
8734       BB_endif.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8735       BB_endif.kind |= ctx->block->kind & block_kind_top_level;
8736
8737       /** emit then block */
8738       Block* BB_then = ctx->program->create_and_insert_block();
8739       BB_then->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8740       add_edge(BB_if_idx, BB_then);
8741       append_logical_start(BB_then);
8742       ctx->block = BB_then;
8743       visit_cf_list(ctx, &if_stmt->then_list);
8744       BB_then = ctx->block;
8745       bool then_branch = ctx->cf_info.has_branch;
8746       bool then_branch_divergent = ctx->cf_info.parent_loop.has_divergent_branch;
8747
8748       if (!then_branch) {
8749          append_logical_end(BB_then);
8750          /* branch from then block to endif block */
8751          branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8752          BB_then->instructions.emplace_back(std::move(branch));
8753          add_linear_edge(BB_then->index, &BB_endif);
8754          if (!then_branch_divergent)
8755             add_logical_edge(BB_then->index, &BB_endif);
8756          BB_then->kind |= block_kind_uniform;
8757       }
8758
8759       ctx->cf_info.has_branch = false;
8760       ctx->cf_info.parent_loop.has_divergent_branch = false;
8761
8762       /** emit else block */
8763       Block* BB_else = ctx->program->create_and_insert_block();
8764       BB_else->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8765       add_edge(BB_if_idx, BB_else);
8766       append_logical_start(BB_else);
8767       ctx->block = BB_else;
8768       visit_cf_list(ctx, &if_stmt->else_list);
8769       BB_else = ctx->block;
8770
8771       if (!ctx->cf_info.has_branch) {
8772          append_logical_end(BB_else);
8773          /* branch from then block to endif block */
8774          branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8775          BB_else->instructions.emplace_back(std::move(branch));
8776          add_linear_edge(BB_else->index, &BB_endif);
8777          if (!ctx->cf_info.parent_loop.has_divergent_branch)
8778             add_logical_edge(BB_else->index, &BB_endif);
8779          BB_else->kind |= block_kind_uniform;
8780       }
8781
8782       ctx->cf_info.has_branch &= then_branch;
8783       ctx->cf_info.parent_loop.has_divergent_branch &= then_branch_divergent;
8784
8785       /** emit endif merge block */
8786       if (!ctx->cf_info.has_branch) {
8787          ctx->block = ctx->program->insert_block(std::move(BB_endif));
8788          append_logical_start(ctx->block);
8789       }
8790    } else { /* non-uniform condition */
8791       /**
8792        * To maintain a logical and linear CFG without critical edges,
8793        * non-uniform conditionals are represented in the following way*) :
8794        *
8795        * The linear CFG:
8796        *                        BB_IF
8797        *                        /    \
8798        *       BB_THEN (logical)      BB_THEN (linear)
8799        *                        \    /
8800        *                        BB_INVERT (linear)
8801        *                        /    \
8802        *       BB_ELSE (logical)      BB_ELSE (linear)
8803        *                        \    /
8804        *                        BB_ENDIF
8805        *
8806        * The logical CFG:
8807        *                        BB_IF
8808        *                        /    \
8809        *       BB_THEN (logical)      BB_ELSE (logical)
8810        *                        \    /
8811        *                        BB_ENDIF
8812        *
8813        * *) Exceptions may be due to break and continue statements within loops
8814        **/
8815
8816       if_context ic;
8817
8818       begin_divergent_if_then(ctx, &ic, cond);
8819       visit_cf_list(ctx, &if_stmt->then_list);
8820
8821       begin_divergent_if_else(ctx, &ic);
8822       visit_cf_list(ctx, &if_stmt->else_list);
8823
8824       end_divergent_if(ctx, &ic);
8825    }
8826 }
8827
8828 static void visit_cf_list(isel_context *ctx,
8829                           struct exec_list *list)
8830 {
8831    foreach_list_typed(nir_cf_node, node, node, list) {
8832       switch (node->type) {
8833       case nir_cf_node_block:
8834          visit_block(ctx, nir_cf_node_as_block(node));
8835          break;
8836       case nir_cf_node_if:
8837          visit_if(ctx, nir_cf_node_as_if(node));
8838          break;
8839       case nir_cf_node_loop:
8840          visit_loop(ctx, nir_cf_node_as_loop(node));
8841          break;
8842       default:
8843          unreachable("unimplemented cf list type");
8844       }
8845    }
8846 }
8847
8848 static void export_vs_varying(isel_context *ctx, int slot, bool is_pos, int *next_pos)
8849 {
8850    assert(ctx->stage == vertex_vs ||
8851           ctx->stage == tess_eval_vs ||
8852           ctx->stage == gs_copy_vs);
8853
8854    int offset = ctx->stage == tess_eval_vs
8855                 ? ctx->program->info->tes.outinfo.vs_output_param_offset[slot]
8856                 : ctx->program->info->vs.outinfo.vs_output_param_offset[slot];
8857    uint64_t mask = ctx->outputs.mask[slot];
8858    if (!is_pos && !mask)
8859       return;
8860    if (!is_pos && offset == AC_EXP_PARAM_UNDEFINED)
8861       return;
8862    aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
8863    exp->enabled_mask = mask;
8864    for (unsigned i = 0; i < 4; ++i) {
8865       if (mask & (1 << i))
8866          exp->operands[i] = Operand(ctx->outputs.outputs[slot][i]);
8867       else
8868          exp->operands[i] = Operand(v1);
8869    }
8870    /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
8871     * Setting valid_mask=1 prevents it and has no other effect.
8872     */
8873    exp->valid_mask = ctx->options->chip_class >= GFX10 && is_pos && *next_pos == 0;
8874    exp->done = false;
8875    exp->compressed = false;
8876    if (is_pos)
8877       exp->dest = V_008DFC_SQ_EXP_POS + (*next_pos)++;
8878    else
8879       exp->dest = V_008DFC_SQ_EXP_PARAM + offset;
8880    ctx->block->instructions.emplace_back(std::move(exp));
8881 }
8882
8883 static void export_vs_psiz_layer_viewport(isel_context *ctx, int *next_pos)
8884 {
8885    aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
8886    exp->enabled_mask = 0;
8887    for (unsigned i = 0; i < 4; ++i)
8888       exp->operands[i] = Operand(v1);
8889    if (ctx->outputs.mask[VARYING_SLOT_PSIZ]) {
8890       exp->operands[0] = Operand(ctx->outputs.outputs[VARYING_SLOT_PSIZ][0]);
8891       exp->enabled_mask |= 0x1;
8892    }
8893    if (ctx->outputs.mask[VARYING_SLOT_LAYER]) {
8894       exp->operands[2] = Operand(ctx->outputs.outputs[VARYING_SLOT_LAYER][0]);
8895       exp->enabled_mask |= 0x4;
8896    }
8897    if (ctx->outputs.mask[VARYING_SLOT_VIEWPORT]) {
8898       if (ctx->options->chip_class < GFX9) {
8899          exp->operands[3] = Operand(ctx->outputs.outputs[VARYING_SLOT_VIEWPORT][0]);
8900          exp->enabled_mask |= 0x8;
8901       } else {
8902          Builder bld(ctx->program, ctx->block);
8903
8904          Temp out = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(16u),
8905                              Operand(ctx->outputs.outputs[VARYING_SLOT_VIEWPORT][0]));
8906          if (exp->operands[2].isTemp())
8907             out = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(out), exp->operands[2]);
8908
8909          exp->operands[2] = Operand(out);
8910          exp->enabled_mask |= 0x4;
8911       }
8912    }
8913    exp->valid_mask = ctx->options->chip_class >= GFX10 && *next_pos == 0;
8914    exp->done = false;
8915    exp->compressed = false;
8916    exp->dest = V_008DFC_SQ_EXP_POS + (*next_pos)++;
8917    ctx->block->instructions.emplace_back(std::move(exp));
8918 }
8919
8920 static void create_vs_exports(isel_context *ctx)
8921 {
8922    assert(ctx->stage == vertex_vs ||
8923           ctx->stage == tess_eval_vs ||
8924           ctx->stage == gs_copy_vs);
8925
8926    radv_vs_output_info *outinfo = ctx->stage == tess_eval_vs
8927                                   ? &ctx->program->info->tes.outinfo
8928                                   : &ctx->program->info->vs.outinfo;
8929
8930    if (outinfo->export_prim_id) {
8931       ctx->outputs.mask[VARYING_SLOT_PRIMITIVE_ID] |= 0x1;
8932       ctx->outputs.outputs[VARYING_SLOT_PRIMITIVE_ID][0] = get_arg(ctx, ctx->args->vs_prim_id);
8933    }
8934
8935    if (ctx->options->key.has_multiview_view_index) {
8936       ctx->outputs.mask[VARYING_SLOT_LAYER] |= 0x1;
8937       ctx->outputs.outputs[VARYING_SLOT_LAYER][0] = as_vgpr(ctx, get_arg(ctx, ctx->args->ac.view_index));
8938    }
8939
8940    /* the order these position exports are created is important */
8941    int next_pos = 0;
8942    export_vs_varying(ctx, VARYING_SLOT_POS, true, &next_pos);
8943    if (outinfo->writes_pointsize || outinfo->writes_layer || outinfo->writes_viewport_index) {
8944       export_vs_psiz_layer_viewport(ctx, &next_pos);
8945    }
8946    if (ctx->num_clip_distances + ctx->num_cull_distances > 0)
8947       export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST0, true, &next_pos);
8948    if (ctx->num_clip_distances + ctx->num_cull_distances > 4)
8949       export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST1, true, &next_pos);
8950
8951    if (ctx->export_clip_dists) {
8952       if (ctx->num_clip_distances + ctx->num_cull_distances > 0)
8953          export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST0, false, &next_pos);
8954       if (ctx->num_clip_distances + ctx->num_cull_distances > 4)
8955          export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST1, false, &next_pos);
8956    }
8957
8958    for (unsigned i = 0; i <= VARYING_SLOT_VAR31; ++i) {
8959       if (i < VARYING_SLOT_VAR0 && i != VARYING_SLOT_LAYER &&
8960           i != VARYING_SLOT_PRIMITIVE_ID)
8961          continue;
8962
8963       export_vs_varying(ctx, i, false, NULL);
8964    }
8965 }
8966
8967 static void export_fs_mrt_z(isel_context *ctx)
8968 {
8969    Builder bld(ctx->program, ctx->block);
8970    unsigned enabled_channels = 0;
8971    bool compr = false;
8972    Operand values[4];
8973
8974    for (unsigned i = 0; i < 4; ++i) {
8975       values[i] = Operand(v1);
8976    }
8977
8978    /* Both stencil and sample mask only need 16-bits. */
8979    if (!ctx->program->info->ps.writes_z &&
8980        (ctx->program->info->ps.writes_stencil ||
8981         ctx->program->info->ps.writes_sample_mask)) {
8982       compr = true; /* COMPR flag */
8983
8984       if (ctx->program->info->ps.writes_stencil) {
8985          /* Stencil should be in X[23:16]. */
8986          values[0] = Operand(ctx->outputs.outputs[FRAG_RESULT_STENCIL][0]);
8987          values[0] = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(16u), values[0]);
8988          enabled_channels |= 0x3;
8989       }
8990
8991       if (ctx->program->info->ps.writes_sample_mask) {
8992          /* SampleMask should be in Y[15:0]. */
8993          values[1] = Operand(ctx->outputs.outputs[FRAG_RESULT_SAMPLE_MASK][0]);
8994          enabled_channels |= 0xc;
8995      }
8996    } else {
8997       if (ctx->program->info->ps.writes_z) {
8998          values[0] = Operand(ctx->outputs.outputs[FRAG_RESULT_DEPTH][0]);
8999          enabled_channels |= 0x1;
9000       }
9001
9002       if (ctx->program->info->ps.writes_stencil) {
9003          values[1] = Operand(ctx->outputs.outputs[FRAG_RESULT_STENCIL][0]);
9004          enabled_channels |= 0x2;
9005       }
9006
9007       if (ctx->program->info->ps.writes_sample_mask) {
9008          values[2] = Operand(ctx->outputs.outputs[FRAG_RESULT_SAMPLE_MASK][0]);
9009          enabled_channels |= 0x4;
9010       }
9011    }
9012
9013    /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9014     * writemask component.
9015     */
9016    if (ctx->options->chip_class == GFX6 &&
9017        ctx->options->family != CHIP_OLAND &&
9018        ctx->options->family != CHIP_HAINAN) {
9019             enabled_channels |= 0x1;
9020    }
9021
9022    bld.exp(aco_opcode::exp, values[0], values[1], values[2], values[3],
9023            enabled_channels, V_008DFC_SQ_EXP_MRTZ, compr);
9024 }
9025
9026 static void export_fs_mrt_color(isel_context *ctx, int slot)
9027 {
9028    Builder bld(ctx->program, ctx->block);
9029    unsigned write_mask = ctx->outputs.mask[slot];
9030    Operand values[4];
9031
9032    for (unsigned i = 0; i < 4; ++i) {
9033       if (write_mask & (1 << i)) {
9034          values[i] = Operand(ctx->outputs.outputs[slot][i]);
9035       } else {
9036          values[i] = Operand(v1);
9037       }
9038    }
9039
9040    unsigned target, col_format;
9041    unsigned enabled_channels = 0;
9042    aco_opcode compr_op = (aco_opcode)0;
9043
9044    slot -= FRAG_RESULT_DATA0;
9045    target = V_008DFC_SQ_EXP_MRT + slot;
9046    col_format = (ctx->options->key.fs.col_format >> (4 * slot)) & 0xf;
9047
9048    bool is_int8 = (ctx->options->key.fs.is_int8 >> slot) & 1;
9049    bool is_int10 = (ctx->options->key.fs.is_int10 >> slot) & 1;
9050
9051    switch (col_format)
9052    {
9053    case V_028714_SPI_SHADER_ZERO:
9054       enabled_channels = 0; /* writemask */
9055       target = V_008DFC_SQ_EXP_NULL;
9056       break;
9057
9058    case V_028714_SPI_SHADER_32_R:
9059       enabled_channels = 1;
9060       break;
9061
9062    case V_028714_SPI_SHADER_32_GR:
9063       enabled_channels = 0x3;
9064       break;
9065
9066    case V_028714_SPI_SHADER_32_AR:
9067       if (ctx->options->chip_class >= GFX10) {
9068          /* Special case: on GFX10, the outputs are different for 32_AR */
9069          enabled_channels = 0x3;
9070          values[1] = values[3];
9071          values[3] = Operand(v1);
9072       } else {
9073          enabled_channels = 0x9;
9074       }
9075       break;
9076
9077    case V_028714_SPI_SHADER_FP16_ABGR:
9078       enabled_channels = 0x5;
9079       compr_op = aco_opcode::v_cvt_pkrtz_f16_f32;
9080       break;
9081
9082    case V_028714_SPI_SHADER_UNORM16_ABGR:
9083       enabled_channels = 0x5;
9084       compr_op = aco_opcode::v_cvt_pknorm_u16_f32;
9085       break;
9086
9087    case V_028714_SPI_SHADER_SNORM16_ABGR:
9088       enabled_channels = 0x5;
9089       compr_op = aco_opcode::v_cvt_pknorm_i16_f32;
9090       break;
9091
9092    case V_028714_SPI_SHADER_UINT16_ABGR: {
9093       enabled_channels = 0x5;
9094       compr_op = aco_opcode::v_cvt_pk_u16_u32;
9095       if (is_int8 || is_int10) {
9096          /* clamp */
9097          uint32_t max_rgb = is_int8 ? 255 : is_int10 ? 1023 : 0;
9098          Temp max_rgb_val = bld.copy(bld.def(s1), Operand(max_rgb));
9099
9100          for (unsigned i = 0; i < 4; i++) {
9101             if ((write_mask >> i) & 1) {
9102                values[i] = bld.vop2(aco_opcode::v_min_u32, bld.def(v1),
9103                                     i == 3 && is_int10 ? Operand(3u) : Operand(max_rgb_val),
9104                                     values[i]);
9105             }
9106          }
9107       }
9108       break;
9109    }
9110
9111    case V_028714_SPI_SHADER_SINT16_ABGR:
9112       enabled_channels = 0x5;
9113       compr_op = aco_opcode::v_cvt_pk_i16_i32;
9114       if (is_int8 || is_int10) {
9115          /* clamp */
9116          uint32_t max_rgb = is_int8 ? 127 : is_int10 ? 511 : 0;
9117          uint32_t min_rgb = is_int8 ? -128 :is_int10 ? -512 : 0;
9118          Temp max_rgb_val = bld.copy(bld.def(s1), Operand(max_rgb));
9119          Temp min_rgb_val = bld.copy(bld.def(s1), Operand(min_rgb));
9120
9121          for (unsigned i = 0; i < 4; i++) {
9122             if ((write_mask >> i) & 1) {
9123                values[i] = bld.vop2(aco_opcode::v_min_i32, bld.def(v1),
9124                                     i == 3 && is_int10 ? Operand(1u) : Operand(max_rgb_val),
9125                                     values[i]);
9126                values[i] = bld.vop2(aco_opcode::v_max_i32, bld.def(v1),
9127                                     i == 3 && is_int10 ? Operand(-2u) : Operand(min_rgb_val),
9128                                     values[i]);
9129             }
9130          }
9131       }
9132       break;
9133
9134    case V_028714_SPI_SHADER_32_ABGR:
9135       enabled_channels = 0xF;
9136       break;
9137
9138    default:
9139       break;
9140    }
9141
9142    if (target == V_008DFC_SQ_EXP_NULL)
9143       return;
9144
9145    if ((bool) compr_op) {
9146       for (int i = 0; i < 2; i++) {
9147          /* check if at least one of the values to be compressed is enabled */
9148          unsigned enabled = (write_mask >> (i*2) | write_mask >> (i*2+1)) & 0x1;
9149          if (enabled) {
9150             enabled_channels |= enabled << (i*2);
9151             values[i] = bld.vop3(compr_op, bld.def(v1),
9152                                  values[i*2].isUndefined() ? Operand(0u) : values[i*2],
9153                                  values[i*2+1].isUndefined() ? Operand(0u): values[i*2+1]);
9154          } else {
9155             values[i] = Operand(v1);
9156          }
9157       }
9158       values[2] = Operand(v1);
9159       values[3] = Operand(v1);
9160    } else {
9161       for (int i = 0; i < 4; i++)
9162          values[i] = enabled_channels & (1 << i) ? values[i] : Operand(v1);
9163    }
9164
9165    bld.exp(aco_opcode::exp, values[0], values[1], values[2], values[3],
9166            enabled_channels, target, (bool) compr_op);
9167 }
9168
9169 static void create_fs_exports(isel_context *ctx)
9170 {
9171    /* Export depth, stencil and sample mask. */
9172    if (ctx->outputs.mask[FRAG_RESULT_DEPTH] ||
9173        ctx->outputs.mask[FRAG_RESULT_STENCIL] ||
9174        ctx->outputs.mask[FRAG_RESULT_SAMPLE_MASK]) {
9175       export_fs_mrt_z(ctx);
9176    }
9177
9178    /* Export all color render targets. */
9179    for (unsigned i = FRAG_RESULT_DATA0; i < FRAG_RESULT_DATA7 + 1; ++i) {
9180       if (ctx->outputs.mask[i])
9181          export_fs_mrt_color(ctx, i);
9182    }
9183 }
9184
9185 static void write_tcs_tess_factors(isel_context *ctx)
9186 {
9187    unsigned outer_comps;
9188    unsigned inner_comps;
9189
9190    switch (ctx->args->options->key.tcs.primitive_mode) {
9191    case GL_ISOLINES:
9192       outer_comps = 2;
9193       inner_comps = 0;
9194       break;
9195    case GL_TRIANGLES:
9196       outer_comps = 3;
9197       inner_comps = 1;
9198       break;
9199    case GL_QUADS:
9200       outer_comps = 4;
9201       inner_comps = 2;
9202       break;
9203    default:
9204       return;
9205    }
9206
9207    const unsigned tess_index_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
9208    const unsigned tess_index_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
9209
9210    Builder bld(ctx->program, ctx->block);
9211
9212    bld.barrier(aco_opcode::p_memory_barrier_shared);
9213    unsigned workgroup_size = ctx->tcs_num_patches * ctx->shader->info.tess.tcs_vertices_out;
9214    if (unlikely(ctx->program->chip_class != GFX6 && workgroup_size > ctx->program->wave_size))
9215       bld.sopp(aco_opcode::s_barrier);
9216
9217    Temp tcs_rel_ids = get_arg(ctx, ctx->args->ac.tcs_rel_ids);
9218    Temp invocation_id = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1), tcs_rel_ids, Operand(8u), Operand(5u));
9219
9220    Temp invocation_id_is_zero = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), invocation_id);
9221    if_context ic_invocation_id_is_zero;
9222    begin_divergent_if_then(ctx, &ic_invocation_id_is_zero, invocation_id_is_zero);
9223    bld.reset(ctx->block);
9224
9225    Temp hs_ring_tess_factor = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_HS_TESS_FACTOR * 16u));
9226
9227    std::pair<Temp, unsigned> lds_base = get_tcs_output_lds_offset(ctx);
9228    unsigned stride = inner_comps + outer_comps;
9229    Temp inner[4];
9230    Temp outer[4];
9231    Temp out[6];
9232    assert(inner_comps <= (sizeof(inner) / sizeof(Temp)));
9233    assert(outer_comps <= (sizeof(outer) / sizeof(Temp)));
9234    assert(stride <= (sizeof(out) / sizeof(Temp)));
9235
9236    if (ctx->args->options->key.tcs.primitive_mode == GL_ISOLINES) {
9237       // LINES reversal
9238       outer[0] = out[1] = load_lds(ctx, 4, bld.tmp(v1), lds_base.first, lds_base.second + tess_index_outer * 16 + 0 * 4, 4);
9239       outer[1] = out[0] = load_lds(ctx, 4, bld.tmp(v1), lds_base.first, lds_base.second + tess_index_outer * 16 + 1 * 4, 4);
9240    } else {
9241       for (unsigned i = 0; i < outer_comps; ++i)
9242          outer[i] = out[i] = load_lds(ctx, 4, bld.tmp(v1), lds_base.first, lds_base.second + tess_index_outer * 16 + i * 4, 4);
9243
9244       for (unsigned i = 0; i < inner_comps; ++i)
9245          inner[i] = out[outer_comps + i] = load_lds(ctx, 4, bld.tmp(v1), lds_base.first, lds_base.second + tess_index_inner * 16 + i * 4, 4);
9246    }
9247
9248    Temp rel_patch_id = get_tess_rel_patch_id(ctx);
9249    Temp tf_base = get_arg(ctx, ctx->args->tess_factor_offset);
9250    Temp byte_offset = bld.v_mul_imm(bld.def(v1), rel_patch_id, stride * 4u);
9251    unsigned tf_const_offset = 0;
9252
9253    if (ctx->program->chip_class <= GFX8) {
9254       Temp rel_patch_id_is_zero = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), rel_patch_id);
9255       if_context ic_rel_patch_id_is_zero;
9256       begin_divergent_if_then(ctx, &ic_rel_patch_id_is_zero, rel_patch_id_is_zero);
9257       bld.reset(ctx->block);
9258
9259       /* Store the dynamic HS control word. */
9260       Temp control_word = bld.copy(bld.def(v1), Operand(0x80000000u));
9261       bld.mubuf(aco_opcode::buffer_store_dword,
9262                 /* SRSRC */ hs_ring_tess_factor, /* VADDR */ Operand(v1), /* SOFFSET */ tf_base, /* VDATA */ control_word,
9263                 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
9264                 /* disable_wqm */ false, /* glc */ true);
9265       tf_const_offset += 4;
9266
9267       begin_divergent_if_else(ctx, &ic_rel_patch_id_is_zero);
9268       end_divergent_if(ctx, &ic_rel_patch_id_is_zero);
9269       bld.reset(ctx->block);
9270    }
9271
9272    assert(stride == 2 || stride == 4 || stride == 6);
9273    Temp tf_vec = create_vec_from_array(ctx, out, stride, RegType::vgpr);
9274    store_vmem_mubuf(ctx, tf_vec, hs_ring_tess_factor, byte_offset, tf_base, tf_const_offset, 4, (1 << stride) - 1, true, false);
9275
9276    begin_divergent_if_else(ctx, &ic_invocation_id_is_zero);
9277    end_divergent_if(ctx, &ic_invocation_id_is_zero);
9278 }
9279
9280 static void emit_stream_output(isel_context *ctx,
9281                                Temp const *so_buffers,
9282                                Temp const *so_write_offset,
9283                                const struct radv_stream_output *output)
9284 {
9285    unsigned num_comps = util_bitcount(output->component_mask);
9286    unsigned writemask = (1 << num_comps) - 1;
9287    unsigned loc = output->location;
9288    unsigned buf = output->buffer;
9289
9290    assert(num_comps && num_comps <= 4);
9291    if (!num_comps || num_comps > 4)
9292       return;
9293
9294    unsigned start = ffs(output->component_mask) - 1;
9295
9296    Temp out[4];
9297    bool all_undef = true;
9298    assert(ctx->stage == vertex_vs || ctx->stage == gs_copy_vs);
9299    for (unsigned i = 0; i < num_comps; i++) {
9300       out[i] = ctx->outputs.outputs[loc][start + i];
9301       all_undef = all_undef && !out[i].id();
9302    }
9303    if (all_undef)
9304       return;
9305
9306    while (writemask) {
9307       int start, count;
9308       u_bit_scan_consecutive_range(&writemask, &start, &count);
9309       if (count == 3 && ctx->options->chip_class == GFX6) {
9310          /* GFX6 doesn't support storing vec3, split it. */
9311          writemask |= 1u << (start + 2);
9312          count = 2;
9313       }
9314
9315       unsigned offset = output->offset + start * 4;
9316
9317       Temp write_data = {ctx->program->allocateId(), RegClass(RegType::vgpr, count)};
9318       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
9319       for (int i = 0; i < count; ++i)
9320          vec->operands[i] = (ctx->outputs.mask[loc] & 1 << (start + i)) ? Operand(out[start + i]) : Operand(0u);
9321       vec->definitions[0] = Definition(write_data);
9322       ctx->block->instructions.emplace_back(std::move(vec));
9323
9324       aco_opcode opcode;
9325       switch (count) {
9326       case 1:
9327          opcode = aco_opcode::buffer_store_dword;
9328          break;
9329       case 2:
9330          opcode = aco_opcode::buffer_store_dwordx2;
9331          break;
9332       case 3:
9333          opcode = aco_opcode::buffer_store_dwordx3;
9334          break;
9335       case 4:
9336          opcode = aco_opcode::buffer_store_dwordx4;
9337          break;
9338       default:
9339          unreachable("Unsupported dword count.");
9340       }
9341
9342       aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 4, 0)};
9343       store->operands[0] = Operand(so_buffers[buf]);
9344       store->operands[1] = Operand(so_write_offset[buf]);
9345       store->operands[2] = Operand((uint32_t) 0);
9346       store->operands[3] = Operand(write_data);
9347       if (offset > 4095) {
9348          /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
9349          Builder bld(ctx->program, ctx->block);
9350          store->operands[0] = bld.vadd32(bld.def(v1), Operand(offset), Operand(so_write_offset[buf]));
9351       } else {
9352          store->offset = offset;
9353       }
9354       store->offen = true;
9355       store->glc = true;
9356       store->dlc = false;
9357       store->slc = true;
9358       store->can_reorder = true;
9359       ctx->block->instructions.emplace_back(std::move(store));
9360    }
9361 }
9362
9363 static void emit_streamout(isel_context *ctx, unsigned stream)
9364 {
9365    Builder bld(ctx->program, ctx->block);
9366
9367    Temp so_buffers[4];
9368    Temp buf_ptr = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->streamout_buffers));
9369    for (unsigned i = 0; i < 4; i++) {
9370       unsigned stride = ctx->program->info->so.strides[i];
9371       if (!stride)
9372          continue;
9373
9374       Operand off = bld.copy(bld.def(s1), Operand(i * 16u));
9375       so_buffers[i] = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), buf_ptr, off);
9376    }
9377
9378    Temp so_vtx_count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
9379                                 get_arg(ctx, ctx->args->streamout_config), Operand(0x70010u));
9380
9381    Temp tid = emit_mbcnt(ctx, bld.def(v1));
9382
9383    Temp can_emit = bld.vopc(aco_opcode::v_cmp_gt_i32, bld.def(bld.lm), so_vtx_count, tid);
9384
9385    if_context ic;
9386    begin_divergent_if_then(ctx, &ic, can_emit);
9387
9388    bld.reset(ctx->block);
9389
9390    Temp so_write_index = bld.vadd32(bld.def(v1), get_arg(ctx, ctx->args->streamout_write_idx), tid);
9391
9392    Temp so_write_offset[4];
9393
9394    for (unsigned i = 0; i < 4; i++) {
9395       unsigned stride = ctx->program->info->so.strides[i];
9396       if (!stride)
9397          continue;
9398
9399       if (stride == 1) {
9400          Temp offset = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
9401                                 get_arg(ctx, ctx->args->streamout_write_idx),
9402                                 get_arg(ctx, ctx->args->streamout_offset[i]));
9403          Temp new_offset = bld.vadd32(bld.def(v1), offset, tid);
9404
9405          so_write_offset[i] = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), new_offset);
9406       } else {
9407          Temp offset = bld.v_mul_imm(bld.def(v1), so_write_index, stride * 4u);
9408          Temp offset2 = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(4u),
9409                                  get_arg(ctx, ctx->args->streamout_offset[i]));
9410          so_write_offset[i] = bld.vadd32(bld.def(v1), offset, offset2);
9411       }
9412    }
9413
9414    for (unsigned i = 0; i < ctx->program->info->so.num_outputs; i++) {
9415       struct radv_stream_output *output =
9416          &ctx->program->info->so.outputs[i];
9417       if (stream != output->stream)
9418          continue;
9419
9420       emit_stream_output(ctx, so_buffers, so_write_offset, output);
9421    }
9422
9423    begin_divergent_if_else(ctx, &ic);
9424    end_divergent_if(ctx, &ic);
9425 }
9426
9427 } /* end namespace */
9428
9429 void fix_ls_vgpr_init_bug(isel_context *ctx, Pseudo_instruction *startpgm)
9430 {
9431    assert(ctx->shader->info.stage == MESA_SHADER_VERTEX);
9432    Builder bld(ctx->program, ctx->block);
9433    constexpr unsigned hs_idx = 1u;
9434    Builder::Result hs_thread_count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
9435                                               get_arg(ctx, ctx->args->merged_wave_info),
9436                                               Operand((8u << 16) | (hs_idx * 8u)));
9437    Temp ls_has_nonzero_hs_threads = bool_to_vector_condition(ctx, hs_thread_count.def(1).getTemp());
9438
9439    /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
9440
9441    Temp instance_id = bld.sop2(aco_opcode::v_cndmask_b32, bld.def(v1),
9442                                get_arg(ctx, ctx->args->ac.instance_id),
9443                                get_arg(ctx, ctx->args->rel_auto_id),
9444                                ls_has_nonzero_hs_threads);
9445    Temp rel_auto_id = bld.sop2(aco_opcode::v_cndmask_b32, bld.def(v1),
9446                                get_arg(ctx, ctx->args->rel_auto_id),
9447                                get_arg(ctx, ctx->args->ac.tcs_rel_ids),
9448                                ls_has_nonzero_hs_threads);
9449    Temp vertex_id = bld.sop2(aco_opcode::v_cndmask_b32, bld.def(v1),
9450                              get_arg(ctx, ctx->args->ac.vertex_id),
9451                              get_arg(ctx, ctx->args->ac.tcs_patch_id),
9452                              ls_has_nonzero_hs_threads);
9453
9454    ctx->arg_temps[ctx->args->ac.instance_id.arg_index] = instance_id;
9455    ctx->arg_temps[ctx->args->rel_auto_id.arg_index] = rel_auto_id;
9456    ctx->arg_temps[ctx->args->ac.vertex_id.arg_index] = vertex_id;
9457 }
9458
9459 void split_arguments(isel_context *ctx, Pseudo_instruction *startpgm)
9460 {
9461    /* Split all arguments except for the first (ring_offsets) and the last
9462     * (exec) so that the dead channels don't stay live throughout the program.
9463     */
9464    for (int i = 1; i < startpgm->definitions.size() - 1; i++) {
9465       if (startpgm->definitions[i].regClass().size() > 1) {
9466          emit_split_vector(ctx, startpgm->definitions[i].getTemp(),
9467                            startpgm->definitions[i].regClass().size());
9468       }
9469    }
9470 }
9471
9472 void handle_bc_optimize(isel_context *ctx)
9473 {
9474    /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
9475    Builder bld(ctx->program, ctx->block);
9476    uint32_t spi_ps_input_ena = ctx->program->config->spi_ps_input_ena;
9477    bool uses_center = G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena);
9478    bool uses_centroid = G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena);
9479    ctx->persp_centroid = get_arg(ctx, ctx->args->ac.persp_centroid);
9480    ctx->linear_centroid = get_arg(ctx, ctx->args->ac.linear_centroid);
9481    if (uses_center && uses_centroid) {
9482       Temp sel = bld.vopc_e64(aco_opcode::v_cmp_lt_i32, bld.hint_vcc(bld.def(bld.lm)),
9483                               get_arg(ctx, ctx->args->ac.prim_mask), Operand(0u));
9484
9485       if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena)) {
9486          Temp new_coord[2];
9487          for (unsigned i = 0; i < 2; i++) {
9488             Temp persp_centroid = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.persp_centroid), i, v1);
9489             Temp persp_center = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.persp_center), i, v1);
9490             new_coord[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
9491                                     persp_centroid, persp_center, sel);
9492          }
9493          ctx->persp_centroid = bld.tmp(v2);
9494          bld.pseudo(aco_opcode::p_create_vector, Definition(ctx->persp_centroid),
9495                     Operand(new_coord[0]), Operand(new_coord[1]));
9496          emit_split_vector(ctx, ctx->persp_centroid, 2);
9497       }
9498
9499       if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena)) {
9500          Temp new_coord[2];
9501          for (unsigned i = 0; i < 2; i++) {
9502             Temp linear_centroid = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.linear_centroid), i, v1);
9503             Temp linear_center = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.linear_center), i, v1);
9504             new_coord[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
9505                                     linear_centroid, linear_center, sel);
9506          }
9507          ctx->linear_centroid = bld.tmp(v2);
9508          bld.pseudo(aco_opcode::p_create_vector, Definition(ctx->linear_centroid),
9509                     Operand(new_coord[0]), Operand(new_coord[1]));
9510          emit_split_vector(ctx, ctx->linear_centroid, 2);
9511       }
9512    }
9513 }
9514
9515 void setup_fp_mode(isel_context *ctx, nir_shader *shader)
9516 {
9517    Program *program = ctx->program;
9518
9519    unsigned float_controls = shader->info.float_controls_execution_mode;
9520
9521    program->next_fp_mode.preserve_signed_zero_inf_nan32 =
9522       float_controls & FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32;
9523    program->next_fp_mode.preserve_signed_zero_inf_nan16_64 =
9524       float_controls & (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16 |
9525                         FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64);
9526
9527    program->next_fp_mode.must_flush_denorms32 =
9528       float_controls & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32;
9529    program->next_fp_mode.must_flush_denorms16_64 =
9530       float_controls & (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16 |
9531                         FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64);
9532
9533    program->next_fp_mode.care_about_round32 =
9534       float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32 | FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32);
9535
9536    program->next_fp_mode.care_about_round16_64 =
9537       float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64 |
9538                         FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64);
9539
9540    /* default to preserving fp16 and fp64 denorms, since it's free */
9541    if (program->next_fp_mode.must_flush_denorms16_64)
9542       program->next_fp_mode.denorm16_64 = 0;
9543    else
9544       program->next_fp_mode.denorm16_64 = fp_denorm_keep;
9545
9546    /* preserving fp32 denorms is expensive, so only do it if asked */
9547    if (float_controls & FLOAT_CONTROLS_DENORM_PRESERVE_FP32)
9548       program->next_fp_mode.denorm32 = fp_denorm_keep;
9549    else
9550       program->next_fp_mode.denorm32 = 0;
9551
9552    if (float_controls & FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32)
9553       program->next_fp_mode.round32 = fp_round_tz;
9554    else
9555       program->next_fp_mode.round32 = fp_round_ne;
9556
9557    if (float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64))
9558       program->next_fp_mode.round16_64 = fp_round_tz;
9559    else
9560       program->next_fp_mode.round16_64 = fp_round_ne;
9561
9562    ctx->block->fp_mode = program->next_fp_mode;
9563 }
9564
9565 void cleanup_cfg(Program *program)
9566 {
9567    /* create linear_succs/logical_succs */
9568    for (Block& BB : program->blocks) {
9569       for (unsigned idx : BB.linear_preds)
9570          program->blocks[idx].linear_succs.emplace_back(BB.index);
9571       for (unsigned idx : BB.logical_preds)
9572          program->blocks[idx].logical_succs.emplace_back(BB.index);
9573    }
9574 }
9575
9576 void select_program(Program *program,
9577                     unsigned shader_count,
9578                     struct nir_shader *const *shaders,
9579                     ac_shader_config* config,
9580                     struct radv_shader_args *args)
9581 {
9582    isel_context ctx = setup_isel_context(program, shader_count, shaders, config, args, false);
9583
9584    for (unsigned i = 0; i < shader_count; i++) {
9585       nir_shader *nir = shaders[i];
9586       init_context(&ctx, nir);
9587
9588       setup_fp_mode(&ctx, nir);
9589
9590       if (!i) {
9591          /* needs to be after init_context() for FS */
9592          Pseudo_instruction *startpgm = add_startpgm(&ctx);
9593          append_logical_start(ctx.block);
9594
9595          if (unlikely(args->options->has_ls_vgpr_init_bug && ctx.stage == vertex_tess_control_hs))
9596             fix_ls_vgpr_init_bug(&ctx, startpgm);
9597
9598          split_arguments(&ctx, startpgm);
9599       }
9600
9601       if_context ic;
9602       if (shader_count >= 2) {
9603          Builder bld(ctx.program, ctx.block);
9604          Temp count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), get_arg(&ctx, args->merged_wave_info), Operand((8u << 16) | (i * 8u)));
9605          Temp thread_id = emit_mbcnt(&ctx, bld.def(v1));
9606          Temp cond = bld.vopc(aco_opcode::v_cmp_gt_u32, bld.hint_vcc(bld.def(bld.lm)), count, thread_id);
9607
9608          begin_divergent_if_then(&ctx, &ic, cond);
9609       }
9610
9611       if (i) {
9612          Builder bld(ctx.program, ctx.block);
9613
9614          bld.barrier(aco_opcode::p_memory_barrier_shared);
9615          bld.sopp(aco_opcode::s_barrier);
9616
9617          if (ctx.stage == vertex_geometry_gs || ctx.stage == tess_eval_geometry_gs) {
9618             ctx.gs_wave_id = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1, m0), bld.def(s1, scc), get_arg(&ctx, args->merged_wave_info), Operand((8u << 16) | 16u));
9619          }
9620       } else if (ctx.stage == geometry_gs)
9621          ctx.gs_wave_id = get_arg(&ctx, args->gs_wave_id);
9622
9623       if (ctx.stage == fragment_fs)
9624          handle_bc_optimize(&ctx);
9625
9626       nir_function_impl *func = nir_shader_get_entrypoint(nir);
9627       visit_cf_list(&ctx, &func->body);
9628
9629       if (ctx.program->info->so.num_outputs && (ctx.stage == vertex_vs || ctx.stage == tess_eval_vs))
9630          emit_streamout(&ctx, 0);
9631
9632       if (ctx.stage == vertex_vs || ctx.stage == tess_eval_vs) {
9633          create_vs_exports(&ctx);
9634       } else if (nir->info.stage == MESA_SHADER_GEOMETRY) {
9635          Builder bld(ctx.program, ctx.block);
9636          bld.barrier(aco_opcode::p_memory_barrier_gs_data);
9637          bld.sopp(aco_opcode::s_sendmsg, bld.m0(ctx.gs_wave_id), -1, sendmsg_gs_done(false, false, 0));
9638       } else if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
9639          write_tcs_tess_factors(&ctx);
9640       }
9641
9642       if (ctx.stage == fragment_fs)
9643          create_fs_exports(&ctx);
9644
9645       if (shader_count >= 2) {
9646          begin_divergent_if_else(&ctx, &ic);
9647          end_divergent_if(&ctx, &ic);
9648       }
9649
9650       ralloc_free(ctx.divergent_vals);
9651    }
9652
9653    program->config->float_mode = program->blocks[0].fp_mode.val;
9654
9655    append_logical_end(ctx.block);
9656    ctx.block->kind |= block_kind_uniform | block_kind_export_end;
9657    Builder bld(ctx.program, ctx.block);
9658    if (ctx.program->wb_smem_l1_on_end)
9659       bld.smem(aco_opcode::s_dcache_wb, false);
9660    bld.sopp(aco_opcode::s_endpgm);
9661
9662    cleanup_cfg(program);
9663 }
9664
9665 void select_gs_copy_shader(Program *program, struct nir_shader *gs_shader,
9666                            ac_shader_config* config,
9667                            struct radv_shader_args *args)
9668 {
9669    isel_context ctx = setup_isel_context(program, 1, &gs_shader, config, args, true);
9670
9671    program->next_fp_mode.preserve_signed_zero_inf_nan32 = false;
9672    program->next_fp_mode.preserve_signed_zero_inf_nan16_64 = false;
9673    program->next_fp_mode.must_flush_denorms32 = false;
9674    program->next_fp_mode.must_flush_denorms16_64 = false;
9675    program->next_fp_mode.care_about_round32 = false;
9676    program->next_fp_mode.care_about_round16_64 = false;
9677    program->next_fp_mode.denorm16_64 = fp_denorm_keep;
9678    program->next_fp_mode.denorm32 = 0;
9679    program->next_fp_mode.round32 = fp_round_ne;
9680    program->next_fp_mode.round16_64 = fp_round_ne;
9681    ctx.block->fp_mode = program->next_fp_mode;
9682
9683    add_startpgm(&ctx);
9684    append_logical_start(ctx.block);
9685
9686    Builder bld(ctx.program, ctx.block);
9687
9688    Temp gsvs_ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), program->private_segment_buffer, Operand(RING_GSVS_VS * 16u));
9689
9690    Operand stream_id(0u);
9691    if (args->shader_info->so.num_outputs)
9692       stream_id = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
9693                            get_arg(&ctx, ctx.args->streamout_config), Operand(0x20018u));
9694
9695    Temp vtx_offset = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), get_arg(&ctx, ctx.args->ac.vertex_id));
9696
9697    std::stack<Block> endif_blocks;
9698
9699    for (unsigned stream = 0; stream < 4; stream++) {
9700       if (stream_id.isConstant() && stream != stream_id.constantValue())
9701          continue;
9702
9703       unsigned num_components = args->shader_info->gs.num_stream_output_components[stream];
9704       if (stream > 0 && (!num_components || !args->shader_info->so.num_outputs))
9705          continue;
9706
9707       memset(ctx.outputs.mask, 0, sizeof(ctx.outputs.mask));
9708
9709       unsigned BB_if_idx = ctx.block->index;
9710       Block BB_endif = Block();
9711       if (!stream_id.isConstant()) {
9712          /* begin IF */
9713          Temp cond = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), stream_id, Operand(stream));
9714          append_logical_end(ctx.block);
9715          ctx.block->kind |= block_kind_uniform;
9716          bld.branch(aco_opcode::p_cbranch_z, cond);
9717
9718          BB_endif.kind |= ctx.block->kind & block_kind_top_level;
9719
9720          ctx.block = ctx.program->create_and_insert_block();
9721          add_edge(BB_if_idx, ctx.block);
9722          bld.reset(ctx.block);
9723          append_logical_start(ctx.block);
9724       }
9725
9726       unsigned offset = 0;
9727       for (unsigned i = 0; i <= VARYING_SLOT_VAR31; ++i) {
9728          if (args->shader_info->gs.output_streams[i] != stream)
9729             continue;
9730
9731          unsigned output_usage_mask = args->shader_info->gs.output_usage_mask[i];
9732          unsigned length = util_last_bit(output_usage_mask);
9733          for (unsigned j = 0; j < length; ++j) {
9734             if (!(output_usage_mask & (1 << j)))
9735                continue;
9736
9737             unsigned const_offset = offset * args->shader_info->gs.vertices_out * 16 * 4;
9738             Temp voffset = vtx_offset;
9739             if (const_offset >= 4096u) {
9740                voffset = bld.vadd32(bld.def(v1), Operand(const_offset / 4096u * 4096u), voffset);
9741                const_offset %= 4096u;
9742             }
9743
9744             aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(aco_opcode::buffer_load_dword, Format::MUBUF, 3, 1)};
9745             mubuf->definitions[0] = bld.def(v1);
9746             mubuf->operands[0] = Operand(gsvs_ring);
9747             mubuf->operands[1] = Operand(voffset);
9748             mubuf->operands[2] = Operand(0u);
9749             mubuf->offen = true;
9750             mubuf->offset = const_offset;
9751             mubuf->glc = true;
9752             mubuf->slc = true;
9753             mubuf->dlc = args->options->chip_class >= GFX10;
9754             mubuf->barrier = barrier_none;
9755             mubuf->can_reorder = true;
9756
9757             ctx.outputs.mask[i] |= 1 << j;
9758             ctx.outputs.outputs[i][j] = mubuf->definitions[0].getTemp();
9759
9760             bld.insert(std::move(mubuf));
9761
9762             offset++;
9763          }
9764       }
9765
9766       if (args->shader_info->so.num_outputs) {
9767          emit_streamout(&ctx, stream);
9768          bld.reset(ctx.block);
9769       }
9770
9771       if (stream == 0) {
9772          create_vs_exports(&ctx);
9773          ctx.block->kind |= block_kind_export_end;
9774       }
9775
9776       if (!stream_id.isConstant()) {
9777          append_logical_end(ctx.block);
9778
9779          /* branch from then block to endif block */
9780          bld.branch(aco_opcode::p_branch);
9781          add_edge(ctx.block->index, &BB_endif);
9782          ctx.block->kind |= block_kind_uniform;
9783
9784          /* emit else block */
9785          ctx.block = ctx.program->create_and_insert_block();
9786          add_edge(BB_if_idx, ctx.block);
9787          bld.reset(ctx.block);
9788          append_logical_start(ctx.block);
9789
9790          endif_blocks.push(std::move(BB_endif));
9791       }
9792    }
9793
9794    while (!endif_blocks.empty()) {
9795       Block BB_endif = std::move(endif_blocks.top());
9796       endif_blocks.pop();
9797
9798       Block *BB_else = ctx.block;
9799
9800       append_logical_end(BB_else);
9801       /* branch from else block to endif block */
9802       bld.branch(aco_opcode::p_branch);
9803       add_edge(BB_else->index, &BB_endif);
9804       BB_else->kind |= block_kind_uniform;
9805
9806       /** emit endif merge block */
9807       ctx.block = program->insert_block(std::move(BB_endif));
9808       bld.reset(ctx.block);
9809       append_logical_start(ctx.block);
9810    }
9811
9812    program->config->float_mode = program->blocks[0].fp_mode.val;
9813
9814    append_logical_end(ctx.block);
9815    ctx.block->kind |= block_kind_uniform;
9816    bld.sopp(aco_opcode::s_endpgm);
9817
9818    cleanup_cfg(program);
9819 }
9820 }