src/amd/compiler/aco_instruction_selection.cpp

   1 /*
   2  * Copyright © 2018 Valve Corporation
   3  * Copyright © 2018 Google
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <algorithm>
  27 #include <array>
  28 #include <stack>
  29 #include <map>
  30
  31 #include "ac_shader_util.h"
  32 #include "aco_ir.h"
  33 #include "aco_builder.h"
  34 #include "aco_interface.h"
  35 #include "aco_instruction_selection_setup.cpp"
  36 #include "util/fast_idiv_by_const.h"
  37
  38 namespace aco {
  39 namespace {
  40
  41 class loop_info_RAII {
  42    isel_context* ctx;
  43    unsigned header_idx_old;
  44    Block* exit_old;
  45    bool divergent_cont_old;
  46    bool divergent_branch_old;
  47    bool divergent_if_old;
  48
  49 public:
  50    loop_info_RAII(isel_context* ctx, unsigned loop_header_idx, Block* loop_exit)
  51       : ctx(ctx),
  52         header_idx_old(ctx->cf_info.parent_loop.header_idx), exit_old(ctx->cf_info.parent_loop.exit),
  53         divergent_cont_old(ctx->cf_info.parent_loop.has_divergent_continue),
  54         divergent_branch_old(ctx->cf_info.parent_loop.has_divergent_branch),
  55         divergent_if_old(ctx->cf_info.parent_if.is_divergent)
  56    {
  57       ctx->cf_info.parent_loop.header_idx = loop_header_idx;
  58       ctx->cf_info.parent_loop.exit = loop_exit;
  59       ctx->cf_info.parent_loop.has_divergent_continue = false;
  60       ctx->cf_info.parent_loop.has_divergent_branch = false;
  61       ctx->cf_info.parent_if.is_divergent = false;
  62       ctx->cf_info.loop_nest_depth = ctx->cf_info.loop_nest_depth + 1;
  63    }
  64
  65    ~loop_info_RAII()
  66    {
  67       ctx->cf_info.parent_loop.header_idx = header_idx_old;
  68       ctx->cf_info.parent_loop.exit = exit_old;
  69       ctx->cf_info.parent_loop.has_divergent_continue = divergent_cont_old;
  70       ctx->cf_info.parent_loop.has_divergent_branch = divergent_branch_old;
  71       ctx->cf_info.parent_if.is_divergent = divergent_if_old;
  72       ctx->cf_info.loop_nest_depth = ctx->cf_info.loop_nest_depth - 1;
  73       if (!ctx->cf_info.loop_nest_depth && !ctx->cf_info.parent_if.is_divergent)
  74          ctx->cf_info.exec_potentially_empty_discard = false;
  75    }
  76 };
  77
  78 struct if_context {
  79    Temp cond;
  80
  81    bool divergent_old;
  82    bool exec_potentially_empty_discard_old;
  83    bool exec_potentially_empty_break_old;
  84    uint16_t exec_potentially_empty_break_depth_old;
  85
  86    unsigned BB_if_idx;
  87    unsigned invert_idx;
  88    bool then_branch_divergent;
  89    Block BB_invert;
  90    Block BB_endif;
  91 };
  92
  93 static void visit_cf_list(struct isel_context *ctx,
  94                           struct exec_list *list);
  95
  96 static void add_logical_edge(unsigned pred_idx, Block *succ)
  97 {
  98    succ->logical_preds.emplace_back(pred_idx);
  99 }
 100
 101
 102 static void add_linear_edge(unsigned pred_idx, Block *succ)
 103 {
 104    succ->linear_preds.emplace_back(pred_idx);
 105 }
 106
 107 static void add_edge(unsigned pred_idx, Block *succ)
 108 {
 109    add_logical_edge(pred_idx, succ);
 110    add_linear_edge(pred_idx, succ);
 111 }
 112
 113 static void append_logical_start(Block *b)
 114 {
 115    Builder(NULL, b).pseudo(aco_opcode::p_logical_start);
 116 }
 117
 118 static void append_logical_end(Block *b)
 119 {
 120    Builder(NULL, b).pseudo(aco_opcode::p_logical_end);
 121 }
 122
 123 Temp get_ssa_temp(struct isel_context *ctx, nir_ssa_def *def)
 124 {
 125    assert(ctx->allocated[def->index].id());
 126    return ctx->allocated[def->index];
 127 }
 128
 129 Temp emit_mbcnt(isel_context *ctx, Definition dst,
 130                 Operand mask_lo = Operand((uint32_t) -1), Operand mask_hi = Operand((uint32_t) -1))
 131 {
 132    Builder bld(ctx->program, ctx->block);
 133    Definition lo_def = ctx->program->wave_size == 32 ? dst : bld.def(v1);
 134    Temp thread_id_lo = bld.vop3(aco_opcode::v_mbcnt_lo_u32_b32, lo_def, mask_lo, Operand(0u));
 135
 136    if (ctx->program->wave_size == 32) {
 137       return thread_id_lo;
 138    } else {
 139       Temp thread_id_hi = bld.vop3(aco_opcode::v_mbcnt_hi_u32_b32, dst, mask_hi, thread_id_lo);
 140       return thread_id_hi;
 141    }
 142 }
 143
 144 Temp emit_wqm(isel_context *ctx, Temp src, Temp dst=Temp(0, s1), bool program_needs_wqm = false)
 145 {
 146    Builder bld(ctx->program, ctx->block);
 147
 148    if (!dst.id())
 149       dst = bld.tmp(src.regClass());
 150
 151    assert(src.size() == dst.size());
 152
 153    if (ctx->stage != fragment_fs) {
 154       if (!dst.id())
 155          return src;
 156
 157       bld.copy(Definition(dst), src);
 158       return dst;
 159    }
 160
 161    bld.pseudo(aco_opcode::p_wqm, Definition(dst), src);
 162    ctx->program->needs_wqm |= program_needs_wqm;
 163    return dst;
 164 }
 165
 166 static Temp emit_bpermute(isel_context *ctx, Builder &bld, Temp index, Temp data)
 167 {
 168    if (index.regClass() == s1)
 169       return bld.readlane(bld.def(s1), data, index);
 170
 171    Temp index_x4 = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), index);
 172
 173    /* Currently not implemented on GFX6-7 */
 174    assert(ctx->options->chip_class >= GFX8);
 175
 176    if (ctx->options->chip_class <= GFX9 || ctx->program->wave_size == 32) {
 177       return bld.ds(aco_opcode::ds_bpermute_b32, bld.def(v1), index_x4, data);
 178    }
 179
 180    /* GFX10, wave64 mode:
 181     * The bpermute instruction is limited to half-wave operation, which means that it can't
 182     * properly support subgroup shuffle like older generations (or wave32 mode), so we
 183     * emulate it here.
 184     */
 185    if (!ctx->has_gfx10_wave64_bpermute) {
 186       ctx->has_gfx10_wave64_bpermute = true;
 187       ctx->program->config->num_shared_vgprs = 8; /* Shared VGPRs are allocated in groups of 8 */
 188       ctx->program->vgpr_limit -= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
 189    }
 190
 191    Temp lane_id = emit_mbcnt(ctx, bld.def(v1));
 192    Temp lane_is_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x20u), lane_id);
 193    Temp index_is_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x20u), index);
 194    Temp cmp = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm, vcc), lane_is_hi, index_is_hi);
 195
 196    return bld.reduction(aco_opcode::p_wave64_bpermute, bld.def(v1), bld.def(s2), bld.def(s1, scc),
 197                         bld.vcc(cmp), Operand(v2.as_linear()), index_x4, data, gfx10_wave64_bpermute);
 198 }
 199
 200 Temp as_vgpr(isel_context *ctx, Temp val)
 201 {
 202    if (val.type() == RegType::sgpr) {
 203       Builder bld(ctx->program, ctx->block);
 204       return bld.copy(bld.def(RegType::vgpr, val.size()), val);
 205    }
 206    assert(val.type() == RegType::vgpr);
 207    return val;
 208 }
 209
 210 //assumes a != 0xffffffff
 211 void emit_v_div_u32(isel_context *ctx, Temp dst, Temp a, uint32_t b)
 212 {
 213    assert(b != 0);
 214    Builder bld(ctx->program, ctx->block);
 215
 216    if (util_is_power_of_two_or_zero(b)) {
 217       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(dst), Operand((uint32_t)util_logbase2(b)), a);
 218       return;
 219    }
 220
 221    util_fast_udiv_info info = util_compute_fast_udiv_info(b, 32, 32);
 222
 223    assert(info.multiplier <= 0xffffffff);
 224
 225    bool pre_shift = info.pre_shift != 0;
 226    bool increment = info.increment != 0;
 227    bool multiply = true;
 228    bool post_shift = info.post_shift != 0;
 229
 230    if (!pre_shift && !increment && !multiply && !post_shift) {
 231       bld.vop1(aco_opcode::v_mov_b32, Definition(dst), a);
 232       return;
 233    }
 234
 235    Temp pre_shift_dst = a;
 236    if (pre_shift) {
 237       pre_shift_dst = (increment || multiply || post_shift) ? bld.tmp(v1) : dst;
 238       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(pre_shift_dst), Operand((uint32_t)info.pre_shift), a);
 239    }
 240
 241    Temp increment_dst = pre_shift_dst;
 242    if (increment) {
 243       increment_dst = (post_shift || multiply) ? bld.tmp(v1) : dst;
 244       bld.vadd32(Definition(increment_dst), Operand((uint32_t) info.increment), pre_shift_dst);
 245    }
 246
 247    Temp multiply_dst = increment_dst;
 248    if (multiply) {
 249       multiply_dst = post_shift ? bld.tmp(v1) : dst;
 250       bld.vop3(aco_opcode::v_mul_hi_u32, Definition(multiply_dst), increment_dst,
 251                bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand((uint32_t)info.multiplier)));
 252    }
 253
 254    if (post_shift) {
 255       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(dst), Operand((uint32_t)info.post_shift), multiply_dst);
 256    }
 257 }
 258
 259 void emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, Temp dst)
 260 {
 261    Builder bld(ctx->program, ctx->block);
 262    bld.pseudo(aco_opcode::p_extract_vector, Definition(dst), src, Operand(idx));
 263 }
 264
 265
 266 Temp emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, RegClass dst_rc)
 267 {
 268    /* no need to extract the whole vector */
 269    if (src.regClass() == dst_rc) {
 270       assert(idx == 0);
 271       return src;
 272    }
 273    assert(src.size() > idx);
 274    Builder bld(ctx->program, ctx->block);
 275    auto it = ctx->allocated_vec.find(src.id());
 276    /* the size check needs to be early because elements other than 0 may be garbage */
 277    if (it != ctx->allocated_vec.end() && it->second[0].size() == dst_rc.size()) {
 278       if (it->second[idx].regClass() == dst_rc) {
 279          return it->second[idx];
 280       } else {
 281          assert(dst_rc.size() == it->second[idx].regClass().size());
 282          assert(dst_rc.type() == RegType::vgpr && it->second[idx].type() == RegType::sgpr);
 283          return bld.copy(bld.def(dst_rc), it->second[idx]);
 284       }
 285    }
 286
 287    if (src.size() == dst_rc.size()) {
 288       assert(idx == 0);
 289       return bld.copy(bld.def(dst_rc), src);
 290    } else {
 291       Temp dst = bld.tmp(dst_rc);
 292       emit_extract_vector(ctx, src, idx, dst);
 293       return dst;
 294    }
 295 }
 296
 297 void emit_split_vector(isel_context* ctx, Temp vec_src, unsigned num_components)
 298 {
 299    if (num_components == 1)
 300       return;
 301    if (ctx->allocated_vec.find(vec_src.id()) != ctx->allocated_vec.end())
 302       return;
 303    aco_ptr<Pseudo_instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector, Format::PSEUDO, 1, num_components)};
 304    split->operands[0] = Operand(vec_src);
 305    std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 306    for (unsigned i = 0; i < num_components; i++) {
 307       elems[i] = {ctx->program->allocateId(), RegClass(vec_src.type(), vec_src.size() / num_components)};
 308       split->definitions[i] = Definition(elems[i]);
 309    }
 310    ctx->block->instructions.emplace_back(std::move(split));
 311    ctx->allocated_vec.emplace(vec_src.id(), elems);
 312 }
 313
 314 /* This vector expansion uses a mask to determine which elements in the new vector
 315  * come from the original vector. The other elements are undefined. */
 316 void expand_vector(isel_context* ctx, Temp vec_src, Temp dst, unsigned num_components, unsigned mask)
 317 {
 318    emit_split_vector(ctx, vec_src, util_bitcount(mask));
 319
 320    if (vec_src == dst)
 321       return;
 322
 323    Builder bld(ctx->program, ctx->block);
 324    if (num_components == 1) {
 325       if (dst.type() == RegType::sgpr)
 326          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec_src);
 327       else
 328          bld.copy(Definition(dst), vec_src);
 329       return;
 330    }
 331
 332    unsigned component_size = dst.size() / num_components;
 333    std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 334
 335    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1)};
 336    vec->definitions[0] = Definition(dst);
 337    unsigned k = 0;
 338    for (unsigned i = 0; i < num_components; i++) {
 339       if (mask & (1 << i)) {
 340          Temp src = emit_extract_vector(ctx, vec_src, k++, RegClass(vec_src.type(), component_size));
 341          if (dst.type() == RegType::sgpr)
 342             src = bld.as_uniform(src);
 343          vec->operands[i] = Operand(src);
 344       } else {
 345          vec->operands[i] = Operand(0u);
 346       }
 347       elems[i] = vec->operands[i].getTemp();
 348    }
 349    ctx->block->instructions.emplace_back(std::move(vec));
 350    ctx->allocated_vec.emplace(dst.id(), elems);
 351 }
 352
 353 Temp bool_to_vector_condition(isel_context *ctx, Temp val, Temp dst = Temp(0, s2))
 354 {
 355    Builder bld(ctx->program, ctx->block);
 356    if (!dst.id())
 357       dst = bld.tmp(bld.lm);
 358
 359    assert(val.regClass() == s1);
 360    assert(dst.regClass() == bld.lm);
 361
 362    return bld.sop2(Builder::s_cselect, Definition(dst), Operand((uint32_t) -1), Operand(0u), bld.scc(val));
 363 }
 364
 365 Temp bool_to_scalar_condition(isel_context *ctx, Temp val, Temp dst = Temp(0, s1))
 366 {
 367    Builder bld(ctx->program, ctx->block);
 368    if (!dst.id())
 369       dst = bld.tmp(s1);
 370
 371    assert(val.regClass() == bld.lm);
 372    assert(dst.regClass() == s1);
 373
 374    /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
 375    Temp tmp = bld.tmp(s1);
 376    bld.sop2(Builder::s_and, bld.def(bld.lm), bld.scc(Definition(tmp)), val, Operand(exec, bld.lm));
 377    return emit_wqm(ctx, tmp, dst);
 378 }
 379
 380 Temp get_alu_src(struct isel_context *ctx, nir_alu_src src, unsigned size=1)
 381 {
 382    if (src.src.ssa->num_components == 1 && src.swizzle[0] == 0 && size == 1)
 383       return get_ssa_temp(ctx, src.src.ssa);
 384
 385    if (src.src.ssa->num_components == size) {
 386       bool identity_swizzle = true;
 387       for (unsigned i = 0; identity_swizzle && i < size; i++) {
 388          if (src.swizzle[i] != i)
 389             identity_swizzle = false;
 390       }
 391       if (identity_swizzle)
 392          return get_ssa_temp(ctx, src.src.ssa);
 393    }
 394
 395    Temp vec = get_ssa_temp(ctx, src.src.ssa);
 396    unsigned elem_size = vec.size() / src.src.ssa->num_components;
 397    assert(elem_size > 0); /* TODO: 8 and 16-bit vectors not supported */
 398    assert(vec.size() % elem_size == 0);
 399
 400    RegClass elem_rc = RegClass(vec.type(), elem_size);
 401    if (size == 1) {
 402       return emit_extract_vector(ctx, vec, src.swizzle[0], elem_rc);
 403    } else {
 404       assert(size <= 4);
 405       std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 406       aco_ptr<Pseudo_instruction> vec_instr{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, size, 1)};
 407       for (unsigned i = 0; i < size; ++i) {
 408          elems[i] = emit_extract_vector(ctx, vec, src.swizzle[i], elem_rc);
 409          vec_instr->operands[i] = Operand{elems[i]};
 410       }
 411       Temp dst{ctx->program->allocateId(), RegClass(vec.type(), elem_size * size)};
 412       vec_instr->definitions[0] = Definition(dst);
 413       ctx->block->instructions.emplace_back(std::move(vec_instr));
 414       ctx->allocated_vec.emplace(dst.id(), elems);
 415       return dst;
 416    }
 417 }
 418
 419 Temp convert_pointer_to_64_bit(isel_context *ctx, Temp ptr)
 420 {
 421    if (ptr.size() == 2)
 422       return ptr;
 423    Builder bld(ctx->program, ctx->block);
 424    if (ptr.type() == RegType::vgpr)
 425       ptr = bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), ptr);
 426    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s2),
 427                      ptr, Operand((unsigned)ctx->options->address32_hi));
 428 }
 429
 430 void emit_sop2_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst, bool writes_scc)
 431 {
 432    aco_ptr<SOP2_instruction> sop2{create_instruction<SOP2_instruction>(op, Format::SOP2, 2, writes_scc ? 2 : 1)};
 433    sop2->operands[0] = Operand(get_alu_src(ctx, instr->src[0]));
 434    sop2->operands[1] = Operand(get_alu_src(ctx, instr->src[1]));
 435    sop2->definitions[0] = Definition(dst);
 436    if (writes_scc)
 437       sop2->definitions[1] = Definition(ctx->program->allocateId(), scc, s1);
 438    ctx->block->instructions.emplace_back(std::move(sop2));
 439 }
 440
 441 void emit_vop2_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst,
 442                            bool commutative, bool swap_srcs=false, bool flush_denorms = false)
 443 {
 444    Builder bld(ctx->program, ctx->block);
 445    Temp src0 = get_alu_src(ctx, instr->src[swap_srcs ? 1 : 0]);
 446    Temp src1 = get_alu_src(ctx, instr->src[swap_srcs ? 0 : 1]);
 447    if (src1.type() == RegType::sgpr) {
 448       if (commutative && src0.type() == RegType::vgpr) {
 449          Temp t = src0;
 450          src0 = src1;
 451          src1 = t;
 452       } else if (src0.type() == RegType::vgpr &&
 453                  op != aco_opcode::v_madmk_f32 &&
 454                  op != aco_opcode::v_madak_f32 &&
 455                  op != aco_opcode::v_madmk_f16 &&
 456                  op != aco_opcode::v_madak_f16) {
 457          /* If the instruction is not commutative, we emit a VOP3A instruction */
 458          bld.vop2_e64(op, Definition(dst), src0, src1);
 459          return;
 460       } else {
 461          src1 = bld.copy(bld.def(RegType::vgpr, src1.size()), src1); //TODO: as_vgpr
 462       }
 463    }
 464
 465    if (flush_denorms && ctx->program->chip_class < GFX9) {
 466       assert(dst.size() == 1);
 467       Temp tmp = bld.vop2(op, bld.def(v1), src0, src1);
 468       bld.vop2(aco_opcode::v_mul_f32, Definition(dst), Operand(0x3f800000u), tmp);
 469    } else {
 470       bld.vop2(op, Definition(dst), src0, src1);
 471    }
 472 }
 473
 474 void emit_vop3a_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst,
 475                             bool flush_denorms = false)
 476 {
 477    Temp src0 = get_alu_src(ctx, instr->src[0]);
 478    Temp src1 = get_alu_src(ctx, instr->src[1]);
 479    Temp src2 = get_alu_src(ctx, instr->src[2]);
 480
 481    /* ensure that the instruction has at most 1 sgpr operand
 482     * The optimizer will inline constants for us */
 483    if (src0.type() == RegType::sgpr && src1.type() == RegType::sgpr)
 484       src0 = as_vgpr(ctx, src0);
 485    if (src1.type() == RegType::sgpr && src2.type() == RegType::sgpr)
 486       src1 = as_vgpr(ctx, src1);
 487    if (src2.type() == RegType::sgpr && src0.type() == RegType::sgpr)
 488       src2 = as_vgpr(ctx, src2);
 489
 490    Builder bld(ctx->program, ctx->block);
 491    if (flush_denorms && ctx->program->chip_class < GFX9) {
 492       assert(dst.size() == 1);
 493       Temp tmp = bld.vop3(op, Definition(dst), src0, src1, src2);
 494       bld.vop2(aco_opcode::v_mul_f32, Definition(dst), Operand(0x3f800000u), tmp);
 495    } else {
 496       bld.vop3(op, Definition(dst), src0, src1, src2);
 497    }
 498 }
 499
 500 void emit_vop1_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 501 {
 502    Builder bld(ctx->program, ctx->block);
 503    bld.vop1(op, Definition(dst), get_alu_src(ctx, instr->src[0]));
 504 }
 505
 506 void emit_vopc_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 507 {
 508    Temp src0 = get_alu_src(ctx, instr->src[0]);
 509    Temp src1 = get_alu_src(ctx, instr->src[1]);
 510    assert(src0.size() == src1.size());
 511
 512    aco_ptr<Instruction> vopc;
 513    if (src1.type() == RegType::sgpr) {
 514       if (src0.type() == RegType::vgpr) {
 515          /* to swap the operands, we might also have to change the opcode */
 516          switch (op) {
 517             case aco_opcode::v_cmp_lt_f32:
 518                op = aco_opcode::v_cmp_gt_f32;
 519                break;
 520             case aco_opcode::v_cmp_ge_f32:
 521                op = aco_opcode::v_cmp_le_f32;
 522                break;
 523             case aco_opcode::v_cmp_lt_i32:
 524                op = aco_opcode::v_cmp_gt_i32;
 525                break;
 526             case aco_opcode::v_cmp_ge_i32:
 527                op = aco_opcode::v_cmp_le_i32;
 528                break;
 529             case aco_opcode::v_cmp_lt_u32:
 530                op = aco_opcode::v_cmp_gt_u32;
 531                break;
 532             case aco_opcode::v_cmp_ge_u32:
 533                op = aco_opcode::v_cmp_le_u32;
 534                break;
 535             case aco_opcode::v_cmp_lt_f64:
 536                op = aco_opcode::v_cmp_gt_f64;
 537                break;
 538             case aco_opcode::v_cmp_ge_f64:
 539                op = aco_opcode::v_cmp_le_f64;
 540                break;
 541             case aco_opcode::v_cmp_lt_i64:
 542                op = aco_opcode::v_cmp_gt_i64;
 543                break;
 544             case aco_opcode::v_cmp_ge_i64:
 545                op = aco_opcode::v_cmp_le_i64;
 546                break;
 547             case aco_opcode::v_cmp_lt_u64:
 548                op = aco_opcode::v_cmp_gt_u64;
 549                break;
 550             case aco_opcode::v_cmp_ge_u64:
 551                op = aco_opcode::v_cmp_le_u64;
 552                break;
 553             default: /* eq and ne are commutative */
 554                break;
 555          }
 556          Temp t = src0;
 557          src0 = src1;
 558          src1 = t;
 559       } else {
 560          src1 = as_vgpr(ctx, src1);
 561       }
 562    }
 563
 564    Builder bld(ctx->program, ctx->block);
 565    bld.vopc(op, bld.hint_vcc(Definition(dst)), src0, src1);
 566 }
 567
 568 void emit_sopc_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 569 {
 570    Temp src0 = get_alu_src(ctx, instr->src[0]);
 571    Temp src1 = get_alu_src(ctx, instr->src[1]);
 572    Builder bld(ctx->program, ctx->block);
 573
 574    assert(dst.regClass() == bld.lm);
 575    assert(src0.type() == RegType::sgpr);
 576    assert(src1.type() == RegType::sgpr);
 577    assert(src0.regClass() == src1.regClass());
 578
 579    /* Emit the SALU comparison instruction */
 580    Temp cmp = bld.sopc(op, bld.scc(bld.def(s1)), src0, src1);
 581    /* Turn the result into a per-lane bool */
 582    bool_to_vector_condition(ctx, cmp, dst);
 583 }
 584
 585 void emit_comparison(isel_context *ctx, nir_alu_instr *instr, Temp dst,
 586                      aco_opcode v32_op, aco_opcode v64_op, aco_opcode s32_op = aco_opcode::num_opcodes, aco_opcode s64_op = aco_opcode::num_opcodes)
 587 {
 588    aco_opcode s_op = instr->src[0].src.ssa->bit_size == 64 ? s64_op : s32_op;
 589    aco_opcode v_op = instr->src[0].src.ssa->bit_size == 64 ? v64_op : v32_op;
 590    bool divergent_vals = ctx->divergent_vals[instr->dest.dest.ssa.index];
 591    bool use_valu = s_op == aco_opcode::num_opcodes ||
 592                    divergent_vals ||
 593                    ctx->allocated[instr->src[0].src.ssa->index].type() == RegType::vgpr ||
 594                    ctx->allocated[instr->src[1].src.ssa->index].type() == RegType::vgpr;
 595    aco_opcode op = use_valu ? v_op : s_op;
 596    assert(op != aco_opcode::num_opcodes);
 597    assert(dst.regClass() == ctx->program->lane_mask);
 598
 599    if (use_valu)
 600       emit_vopc_instruction(ctx, instr, op, dst);
 601    else
 602       emit_sopc_instruction(ctx, instr, op, dst);
 603 }
 604
 605 void emit_boolean_logic(isel_context *ctx, nir_alu_instr *instr, Builder::WaveSpecificOpcode op, Temp dst)
 606 {
 607    Builder bld(ctx->program, ctx->block);
 608    Temp src0 = get_alu_src(ctx, instr->src[0]);
 609    Temp src1 = get_alu_src(ctx, instr->src[1]);
 610
 611    assert(dst.regClass() == bld.lm);
 612    assert(src0.regClass() == bld.lm);
 613    assert(src1.regClass() == bld.lm);
 614
 615    bld.sop2(op, Definition(dst), bld.def(s1, scc), src0, src1);
 616 }
 617
 618 void emit_bcsel(isel_context *ctx, nir_alu_instr *instr, Temp dst)
 619 {
 620    Builder bld(ctx->program, ctx->block);
 621    Temp cond = get_alu_src(ctx, instr->src[0]);
 622    Temp then = get_alu_src(ctx, instr->src[1]);
 623    Temp els = get_alu_src(ctx, instr->src[2]);
 624
 625    assert(cond.regClass() == bld.lm);
 626
 627    if (dst.type() == RegType::vgpr) {
 628       aco_ptr<Instruction> bcsel;
 629       if (dst.size() == 1) {
 630          then = as_vgpr(ctx, then);
 631          els = as_vgpr(ctx, els);
 632
 633          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), els, then, cond);
 634       } else if (dst.size() == 2) {
 635          Temp then_lo = bld.tmp(v1), then_hi = bld.tmp(v1);
 636          bld.pseudo(aco_opcode::p_split_vector, Definition(then_lo), Definition(then_hi), then);
 637          Temp else_lo = bld.tmp(v1), else_hi = bld.tmp(v1);
 638          bld.pseudo(aco_opcode::p_split_vector, Definition(else_lo), Definition(else_hi), els);
 639
 640          Temp dst0 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_lo, then_lo, cond);
 641          Temp dst1 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_hi, then_hi, cond);
 642
 643          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
 644       } else {
 645          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 646          nir_print_instr(&instr->instr, stderr);
 647          fprintf(stderr, "\n");
 648       }
 649       return;
 650    }
 651
 652    if (instr->dest.dest.ssa.bit_size == 1) {
 653       assert(dst.regClass() == bld.lm);
 654       assert(then.regClass() == bld.lm);
 655       assert(els.regClass() == bld.lm);
 656    }
 657
 658    if (!ctx->divergent_vals[instr->src[0].src.ssa->index]) { /* uniform condition and values in sgpr */
 659       if (dst.regClass() == s1 || dst.regClass() == s2) {
 660          assert((then.regClass() == s1 || then.regClass() == s2) && els.regClass() == then.regClass());
 661          assert(dst.size() == then.size());
 662          aco_opcode op = dst.regClass() == s1 ? aco_opcode::s_cselect_b32 : aco_opcode::s_cselect_b64;
 663          bld.sop2(op, Definition(dst), then, els, bld.scc(bool_to_scalar_condition(ctx, cond)));
 664       } else {
 665          fprintf(stderr, "Unimplemented uniform bcsel bit size: ");
 666          nir_print_instr(&instr->instr, stderr);
 667          fprintf(stderr, "\n");
 668       }
 669       return;
 670    }
 671
 672    /* divergent boolean bcsel
 673     * this implements bcsel on bools: dst = s0 ? s1 : s2
 674     * are going to be: dst = (s0 & s1) | (~s0 & s2) */
 675    assert(instr->dest.dest.ssa.bit_size == 1);
 676
 677    if (cond.id() != then.id())
 678       then = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), cond, then);
 679
 680    if (cond.id() == els.id())
 681       bld.sop1(Builder::s_mov, Definition(dst), then);
 682    else
 683       bld.sop2(Builder::s_or, Definition(dst), bld.def(s1, scc), then,
 684                bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), els, cond));
 685 }
 686
 687 void emit_scaled_op(isel_context *ctx, Builder& bld, Definition dst, Temp val,
 688                     aco_opcode op, uint32_t undo)
 689 {
 690    /* multiply by 16777216 to handle denormals */
 691    Temp is_denormal = bld.vopc(aco_opcode::v_cmp_class_f32, bld.hint_vcc(bld.def(bld.lm)),
 692                                as_vgpr(ctx, val), bld.copy(bld.def(v1), Operand((1u << 7) | (1u << 4))));
 693    Temp scaled = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x4b800000u), val);
 694    scaled = bld.vop1(op, bld.def(v1), scaled);
 695    scaled = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(undo), scaled);
 696
 697    Temp not_scaled = bld.vop1(op, bld.def(v1), val);
 698
 699    bld.vop2(aco_opcode::v_cndmask_b32, dst, not_scaled, scaled, is_denormal);
 700 }
 701
 702 void emit_rcp(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 703 {
 704    if (ctx->block->fp_mode.denorm32 == 0) {
 705       bld.vop1(aco_opcode::v_rcp_f32, dst, val);
 706       return;
 707    }
 708
 709    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_rcp_f32, 0x4b800000u);
 710 }
 711
 712 void emit_rsq(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 713 {
 714    if (ctx->block->fp_mode.denorm32 == 0) {
 715       bld.vop1(aco_opcode::v_rsq_f32, dst, val);
 716       return;
 717    }
 718
 719    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_rsq_f32, 0x45800000u);
 720 }
 721
 722 void emit_sqrt(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 723 {
 724    if (ctx->block->fp_mode.denorm32 == 0) {
 725       bld.vop1(aco_opcode::v_sqrt_f32, dst, val);
 726       return;
 727    }
 728
 729    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_sqrt_f32, 0x39800000u);
 730 }
 731
 732 void emit_log2(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 733 {
 734    if (ctx->block->fp_mode.denorm32 == 0) {
 735       bld.vop1(aco_opcode::v_log_f32, dst, val);
 736       return;
 737    }
 738
 739    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_log_f32, 0xc1c00000u);
 740 }
 741
 742 Temp emit_trunc_f64(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 743 {
 744    if (ctx->options->chip_class >= GFX7)
 745       return bld.vop1(aco_opcode::v_trunc_f64, Definition(dst), val);
 746
 747    /* GFX6 doesn't support V_TRUNC_F64, lower it. */
 748    /* TODO: create more efficient code! */
 749    if (val.type() == RegType::sgpr)
 750       val = as_vgpr(ctx, val);
 751
 752    /* Split the input value. */
 753    Temp val_lo = bld.tmp(v1), val_hi = bld.tmp(v1);
 754    bld.pseudo(aco_opcode::p_split_vector, Definition(val_lo), Definition(val_hi), val);
 755
 756    /* Extract the exponent and compute the unbiased value. */
 757    Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f64, bld.def(v1), val);
 758
 759    /* Extract the fractional part. */
 760    Temp fract_mask = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(-1u), Operand(0x000fffffu));
 761    fract_mask = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), fract_mask, exponent);
 762
 763    Temp fract_mask_lo = bld.tmp(v1), fract_mask_hi = bld.tmp(v1);
 764    bld.pseudo(aco_opcode::p_split_vector, Definition(fract_mask_lo), Definition(fract_mask_hi), fract_mask);
 765
 766    Temp fract_lo = bld.tmp(v1), fract_hi = bld.tmp(v1);
 767    Temp tmp = bld.vop1(aco_opcode::v_not_b32, bld.def(v1), fract_mask_lo);
 768    fract_lo = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), val_lo, tmp);
 769    tmp = bld.vop1(aco_opcode::v_not_b32, bld.def(v1), fract_mask_hi);
 770    fract_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), val_hi, tmp);
 771
 772    /* Get the sign bit. */
 773    Temp sign = bld.vop2(aco_opcode::v_ashr_i32, bld.def(v1), Operand(31u), val_hi);
 774
 775    /* Decide the operation to apply depending on the unbiased exponent. */
 776    Temp exp_lt0 = bld.vopc_e64(aco_opcode::v_cmp_lt_i32, bld.hint_vcc(bld.def(bld.lm)), exponent, Operand(0u));
 777    Temp dst_lo = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), fract_lo, bld.copy(bld.def(v1), Operand(0u)), exp_lt0);
 778    Temp dst_hi = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), fract_hi, sign, exp_lt0);
 779    Temp exp_gt51 = bld.vopc_e64(aco_opcode::v_cmp_gt_i32, bld.def(s2), exponent, Operand(51u));
 780    dst_lo = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), dst_lo, val_lo, exp_gt51);
 781    dst_hi = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), dst_hi, val_hi, exp_gt51);
 782
 783    return bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst_lo, dst_hi);
 784 }
 785
 786 Temp emit_floor_f64(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 787 {
 788    if (ctx->options->chip_class >= GFX7)
 789       return bld.vop1(aco_opcode::v_floor_f64, Definition(dst), val);
 790
 791    /* GFX6 doesn't support V_FLOOR_F64, lower it. */
 792    Temp src0 = as_vgpr(ctx, val);
 793
 794    Temp mask = bld.copy(bld.def(s1), Operand(3u)); /* isnan */
 795    Temp min_val = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(-1u), Operand(0x3fefffffu));
 796
 797    Temp isnan = bld.vopc_e64(aco_opcode::v_cmp_class_f64, bld.hint_vcc(bld.def(bld.lm)), src0, mask);
 798    Temp fract = bld.vop1(aco_opcode::v_fract_f64, bld.def(v2), src0);
 799    Temp min = bld.vop3(aco_opcode::v_min_f64, bld.def(v2), fract, min_val);
 800
 801    Temp then_lo = bld.tmp(v1), then_hi = bld.tmp(v1);
 802    bld.pseudo(aco_opcode::p_split_vector, Definition(then_lo), Definition(then_hi), src0);
 803    Temp else_lo = bld.tmp(v1), else_hi = bld.tmp(v1);
 804    bld.pseudo(aco_opcode::p_split_vector, Definition(else_lo), Definition(else_hi), min);
 805
 806    Temp dst0 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_lo, then_lo, isnan);
 807    Temp dst1 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_hi, then_hi, isnan);
 808
 809    Temp v = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), dst0, dst1);
 810
 811    Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst), src0, v);
 812    static_cast<VOP3A_instruction*>(add)->neg[1] = true;
 813
 814    return add->definitions[0].getTemp();
 815 }
 816
 817 void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
 818 {
 819    if (!instr->dest.dest.is_ssa) {
 820       fprintf(stderr, "nir alu dst not in ssa: ");
 821       nir_print_instr(&instr->instr, stderr);
 822       fprintf(stderr, "\n");
 823       abort();
 824    }
 825    Builder bld(ctx->program, ctx->block);
 826    Temp dst = get_ssa_temp(ctx, &instr->dest.dest.ssa);
 827    switch(instr->op) {
 828    case nir_op_vec2:
 829    case nir_op_vec3:
 830    case nir_op_vec4: {
 831       std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 832       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.dest.ssa.num_components, 1)};
 833       for (unsigned i = 0; i < instr->dest.dest.ssa.num_components; ++i) {
 834          elems[i] = get_alu_src(ctx, instr->src[i]);
 835          vec->operands[i] = Operand{elems[i]};
 836       }
 837       vec->definitions[0] = Definition(dst);
 838       ctx->block->instructions.emplace_back(std::move(vec));
 839       ctx->allocated_vec.emplace(dst.id(), elems);
 840       break;
 841    }
 842    case nir_op_mov: {
 843       Temp src = get_alu_src(ctx, instr->src[0]);
 844       aco_ptr<Instruction> mov;
 845       if (dst.type() == RegType::sgpr) {
 846          if (src.type() == RegType::vgpr)
 847             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), src);
 848          else if (src.regClass() == s1)
 849             bld.sop1(aco_opcode::s_mov_b32, Definition(dst), src);
 850          else if (src.regClass() == s2)
 851             bld.sop1(aco_opcode::s_mov_b64, Definition(dst), src);
 852          else
 853             unreachable("wrong src register class for nir_op_imov");
 854       } else if (dst.regClass() == v1) {
 855          bld.vop1(aco_opcode::v_mov_b32, Definition(dst), src);
 856       } else if (dst.regClass() == v2) {
 857          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src);
 858       } else {
 859          nir_print_instr(&instr->instr, stderr);
 860          unreachable("Should have been lowered to scalar.");
 861       }
 862       break;
 863    }
 864    case nir_op_inot: {
 865       Temp src = get_alu_src(ctx, instr->src[0]);
 866       if (instr->dest.dest.ssa.bit_size == 1) {
 867          assert(src.regClass() == bld.lm);
 868          assert(dst.regClass() == bld.lm);
 869          /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
 870          Temp tmp = bld.sop1(Builder::s_not, bld.def(bld.lm), bld.def(s1, scc), src);
 871          bld.sop2(Builder::s_and, Definition(dst), bld.def(s1, scc), tmp, Operand(exec, bld.lm));
 872       } else if (dst.regClass() == v1) {
 873          emit_vop1_instruction(ctx, instr, aco_opcode::v_not_b32, dst);
 874       } else if (dst.type() == RegType::sgpr) {
 875          aco_opcode opcode = dst.size() == 1 ? aco_opcode::s_not_b32 : aco_opcode::s_not_b64;
 876          bld.sop1(opcode, Definition(dst), bld.def(s1, scc), src);
 877       } else {
 878          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 879          nir_print_instr(&instr->instr, stderr);
 880          fprintf(stderr, "\n");
 881       }
 882       break;
 883    }
 884    case nir_op_ineg: {
 885       Temp src = get_alu_src(ctx, instr->src[0]);
 886       if (dst.regClass() == v1) {
 887          bld.vsub32(Definition(dst), Operand(0u), Operand(src));
 888       } else if (dst.regClass() == s1) {
 889          bld.sop2(aco_opcode::s_mul_i32, Definition(dst), Operand((uint32_t) -1), src);
 890       } else if (dst.size() == 2) {
 891          Temp src0 = bld.tmp(dst.type(), 1);
 892          Temp src1 = bld.tmp(dst.type(), 1);
 893          bld.pseudo(aco_opcode::p_split_vector, Definition(src0), Definition(src1), src);
 894
 895          if (dst.regClass() == s2) {
 896             Temp carry = bld.tmp(s1);
 897             Temp dst0 = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(carry)), Operand(0u), src0);
 898             Temp dst1 = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), src1, carry);
 899             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
 900          } else {
 901             Temp lower = bld.tmp(v1);
 902             Temp borrow = bld.vsub32(Definition(lower), Operand(0u), src0, true).def(1).getTemp();
 903             Temp upper = bld.vsub32(bld.def(v1), Operand(0u), src1, false, borrow);
 904             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
 905          }
 906       } else {
 907          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 908          nir_print_instr(&instr->instr, stderr);
 909          fprintf(stderr, "\n");
 910       }
 911       break;
 912    }
 913    case nir_op_iabs: {
 914       if (dst.regClass() == s1) {
 915          bld.sop1(aco_opcode::s_abs_i32, Definition(dst), bld.def(s1, scc), get_alu_src(ctx, instr->src[0]));
 916       } else if (dst.regClass() == v1) {
 917          Temp src = get_alu_src(ctx, instr->src[0]);
 918          bld.vop2(aco_opcode::v_max_i32, Definition(dst), src, bld.vsub32(bld.def(v1), Operand(0u), src));
 919       } else {
 920          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 921          nir_print_instr(&instr->instr, stderr);
 922          fprintf(stderr, "\n");
 923       }
 924       break;
 925    }
 926    case nir_op_isign: {
 927       Temp src = get_alu_src(ctx, instr->src[0]);
 928       if (dst.regClass() == s1) {
 929          Temp tmp = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
 930          Temp gtz = bld.sopc(aco_opcode::s_cmp_gt_i32, bld.def(s1, scc), src, Operand(0u));
 931          bld.sop2(aco_opcode::s_add_i32, Definition(dst), bld.def(s1, scc), gtz, tmp);
 932       } else if (dst.regClass() == s2) {
 933          Temp neg = bld.sop2(aco_opcode::s_ashr_i64, bld.def(s2), bld.def(s1, scc), src, Operand(63u));
 934          Temp neqz;
 935          if (ctx->program->chip_class >= GFX8)
 936             neqz = bld.sopc(aco_opcode::s_cmp_lg_u64, bld.def(s1, scc), src, Operand(0u));
 937          else
 938             neqz = bld.sop2(aco_opcode::s_or_b64, bld.def(s2), bld.def(s1, scc), src, Operand(0u)).def(1).getTemp();
 939          /* SCC gets zero-extended to 64 bit */
 940          bld.sop2(aco_opcode::s_or_b64, Definition(dst), bld.def(s1, scc), neg, bld.scc(neqz));
 941       } else if (dst.regClass() == v1) {
 942          Temp tmp = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
 943          Temp gtz = bld.vopc(aco_opcode::v_cmp_ge_i32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
 944          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(1u), tmp, gtz);
 945       } else if (dst.regClass() == v2) {
 946          Temp upper = emit_extract_vector(ctx, src, 1, v1);
 947          Temp neg = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), upper);
 948          Temp gtz = bld.vopc(aco_opcode::v_cmp_ge_i64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
 949          Temp lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(1u), neg, gtz);
 950          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), neg, gtz);
 951          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
 952       } else {
 953          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 954          nir_print_instr(&instr->instr, stderr);
 955          fprintf(stderr, "\n");
 956       }
 957       break;
 958    }
 959    case nir_op_imax: {
 960       if (dst.regClass() == v1) {
 961          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_i32, dst, true);
 962       } else if (dst.regClass() == s1) {
 963          emit_sop2_instruction(ctx, instr, aco_opcode::s_max_i32, dst, true);
 964       } else {
 965          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 966          nir_print_instr(&instr->instr, stderr);
 967          fprintf(stderr, "\n");
 968       }
 969       break;
 970    }
 971    case nir_op_umax: {
 972       if (dst.regClass() == v1) {
 973          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_u32, dst, true);
 974       } else if (dst.regClass() == s1) {
 975          emit_sop2_instruction(ctx, instr, aco_opcode::s_max_u32, dst, true);
 976       } else {
 977          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 978          nir_print_instr(&instr->instr, stderr);
 979          fprintf(stderr, "\n");
 980       }
 981       break;
 982    }
 983    case nir_op_imin: {
 984       if (dst.regClass() == v1) {
 985          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_i32, dst, true);
 986       } else if (dst.regClass() == s1) {
 987          emit_sop2_instruction(ctx, instr, aco_opcode::s_min_i32, dst, true);
 988       } else {
 989          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 990          nir_print_instr(&instr->instr, stderr);
 991          fprintf(stderr, "\n");
 992       }
 993       break;
 994    }
 995    case nir_op_umin: {
 996       if (dst.regClass() == v1) {
 997          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_u32, dst, true);
 998       } else if (dst.regClass() == s1) {
 999          emit_sop2_instruction(ctx, instr, aco_opcode::s_min_u32, dst, true);
1000       } else {
1001          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1002          nir_print_instr(&instr->instr, stderr);
1003          fprintf(stderr, "\n");
1004       }
1005       break;
1006    }
1007    case nir_op_ior: {
1008       if (instr->dest.dest.ssa.bit_size == 1) {
1009          emit_boolean_logic(ctx, instr, Builder::s_or, dst);
1010       } else if (dst.regClass() == v1) {
1011          emit_vop2_instruction(ctx, instr, aco_opcode::v_or_b32, dst, true);
1012       } else if (dst.regClass() == s1) {
1013          emit_sop2_instruction(ctx, instr, aco_opcode::s_or_b32, dst, true);
1014       } else if (dst.regClass() == s2) {
1015          emit_sop2_instruction(ctx, instr, aco_opcode::s_or_b64, dst, true);
1016       } else {
1017          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1018          nir_print_instr(&instr->instr, stderr);
1019          fprintf(stderr, "\n");
1020       }
1021       break;
1022    }
1023    case nir_op_iand: {
1024       if (instr->dest.dest.ssa.bit_size == 1) {
1025          emit_boolean_logic(ctx, instr, Builder::s_and, dst);
1026       } else if (dst.regClass() == v1) {
1027          emit_vop2_instruction(ctx, instr, aco_opcode::v_and_b32, dst, true);
1028       } else if (dst.regClass() == s1) {
1029          emit_sop2_instruction(ctx, instr, aco_opcode::s_and_b32, dst, true);
1030       } else if (dst.regClass() == s2) {
1031          emit_sop2_instruction(ctx, instr, aco_opcode::s_and_b64, dst, true);
1032       } else {
1033          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1034          nir_print_instr(&instr->instr, stderr);
1035          fprintf(stderr, "\n");
1036       }
1037       break;
1038    }
1039    case nir_op_ixor: {
1040       if (instr->dest.dest.ssa.bit_size == 1) {
1041          emit_boolean_logic(ctx, instr, Builder::s_xor, dst);
1042       } else if (dst.regClass() == v1) {
1043          emit_vop2_instruction(ctx, instr, aco_opcode::v_xor_b32, dst, true);
1044       } else if (dst.regClass() == s1) {
1045          emit_sop2_instruction(ctx, instr, aco_opcode::s_xor_b32, dst, true);
1046       } else if (dst.regClass() == s2) {
1047          emit_sop2_instruction(ctx, instr, aco_opcode::s_xor_b64, dst, true);
1048       } else {
1049          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1050          nir_print_instr(&instr->instr, stderr);
1051          fprintf(stderr, "\n");
1052       }
1053       break;
1054    }
1055    case nir_op_ushr: {
1056       if (dst.regClass() == v1) {
1057          emit_vop2_instruction(ctx, instr, aco_opcode::v_lshrrev_b32, dst, false, true);
1058       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
1059          bld.vop3(aco_opcode::v_lshrrev_b64, Definition(dst),
1060                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
1061       } else if (dst.regClass() == v2) {
1062          bld.vop3(aco_opcode::v_lshr_b64, Definition(dst),
1063                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1064       } else if (dst.regClass() == s2) {
1065          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshr_b64, dst, true);
1066       } else if (dst.regClass() == s1) {
1067          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshr_b32, dst, true);
1068       } else {
1069          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1070          nir_print_instr(&instr->instr, stderr);
1071          fprintf(stderr, "\n");
1072       }
1073       break;
1074    }
1075    case nir_op_ishl: {
1076       if (dst.regClass() == v1) {
1077          emit_vop2_instruction(ctx, instr, aco_opcode::v_lshlrev_b32, dst, false, true);
1078       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
1079          bld.vop3(aco_opcode::v_lshlrev_b64, Definition(dst),
1080                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
1081       } else if (dst.regClass() == v2) {
1082          bld.vop3(aco_opcode::v_lshl_b64, Definition(dst),
1083                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1084       } else if (dst.regClass() == s1) {
1085          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshl_b32, dst, true);
1086       } else if (dst.regClass() == s2) {
1087          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshl_b64, dst, true);
1088       } else {
1089          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1090          nir_print_instr(&instr->instr, stderr);
1091          fprintf(stderr, "\n");
1092       }
1093       break;
1094    }
1095    case nir_op_ishr: {
1096       if (dst.regClass() == v1) {
1097          emit_vop2_instruction(ctx, instr, aco_opcode::v_ashrrev_i32, dst, false, true);
1098       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
1099          bld.vop3(aco_opcode::v_ashrrev_i64, Definition(dst),
1100                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
1101       } else if (dst.regClass() == v2) {
1102          bld.vop3(aco_opcode::v_ashr_i64, Definition(dst),
1103                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1104       } else if (dst.regClass() == s1) {
1105          emit_sop2_instruction(ctx, instr, aco_opcode::s_ashr_i32, dst, true);
1106       } else if (dst.regClass() == s2) {
1107          emit_sop2_instruction(ctx, instr, aco_opcode::s_ashr_i64, dst, true);
1108       } else {
1109          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1110          nir_print_instr(&instr->instr, stderr);
1111          fprintf(stderr, "\n");
1112       }
1113       break;
1114    }
1115    case nir_op_find_lsb: {
1116       Temp src = get_alu_src(ctx, instr->src[0]);
1117       if (src.regClass() == s1) {
1118          bld.sop1(aco_opcode::s_ff1_i32_b32, Definition(dst), src);
1119       } else if (src.regClass() == v1) {
1120          emit_vop1_instruction(ctx, instr, aco_opcode::v_ffbl_b32, dst);
1121       } else if (src.regClass() == s2) {
1122          bld.sop1(aco_opcode::s_ff1_i32_b64, Definition(dst), src);
1123       } else {
1124          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1125          nir_print_instr(&instr->instr, stderr);
1126          fprintf(stderr, "\n");
1127       }
1128       break;
1129    }
1130    case nir_op_ufind_msb:
1131    case nir_op_ifind_msb: {
1132       Temp src = get_alu_src(ctx, instr->src[0]);
1133       if (src.regClass() == s1 || src.regClass() == s2) {
1134          aco_opcode op = src.regClass() == s2 ?
1135                          (instr->op == nir_op_ufind_msb ? aco_opcode::s_flbit_i32_b64 : aco_opcode::s_flbit_i32_i64) :
1136                          (instr->op == nir_op_ufind_msb ? aco_opcode::s_flbit_i32_b32 : aco_opcode::s_flbit_i32);
1137          Temp msb_rev = bld.sop1(op, bld.def(s1), src);
1138
1139          Builder::Result sub = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc),
1140                                         Operand(src.size() * 32u - 1u), msb_rev);
1141          Temp msb = sub.def(0).getTemp();
1142          Temp carry = sub.def(1).getTemp();
1143
1144          bld.sop2(aco_opcode::s_cselect_b32, Definition(dst), Operand((uint32_t)-1), msb, bld.scc(carry));
1145       } else if (src.regClass() == v1) {
1146          aco_opcode op = instr->op == nir_op_ufind_msb ? aco_opcode::v_ffbh_u32 : aco_opcode::v_ffbh_i32;
1147          Temp msb_rev = bld.tmp(v1);
1148          emit_vop1_instruction(ctx, instr, op, msb_rev);
1149          Temp msb = bld.tmp(v1);
1150          Temp carry = bld.vsub32(Definition(msb), Operand(31u), Operand(msb_rev), true).def(1).getTemp();
1151          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), msb, Operand((uint32_t)-1), carry);
1152       } else {
1153          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1154          nir_print_instr(&instr->instr, stderr);
1155          fprintf(stderr, "\n");
1156       }
1157       break;
1158    }
1159    case nir_op_bitfield_reverse: {
1160       if (dst.regClass() == s1) {
1161          bld.sop1(aco_opcode::s_brev_b32, Definition(dst), get_alu_src(ctx, instr->src[0]));
1162       } else if (dst.regClass() == v1) {
1163          bld.vop1(aco_opcode::v_bfrev_b32, Definition(dst), get_alu_src(ctx, instr->src[0]));
1164       } else {
1165          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1166          nir_print_instr(&instr->instr, stderr);
1167          fprintf(stderr, "\n");
1168       }
1169       break;
1170    }
1171    case nir_op_iadd: {
1172       if (dst.regClass() == s1) {
1173          emit_sop2_instruction(ctx, instr, aco_opcode::s_add_u32, dst, true);
1174          break;
1175       }
1176
1177       Temp src0 = get_alu_src(ctx, instr->src[0]);
1178       Temp src1 = get_alu_src(ctx, instr->src[1]);
1179       if (dst.regClass() == v1) {
1180          bld.vadd32(Definition(dst), Operand(src0), Operand(src1));
1181          break;
1182       }
1183
1184       assert(src0.size() == 2 && src1.size() == 2);
1185       Temp src00 = bld.tmp(src0.type(), 1);
1186       Temp src01 = bld.tmp(dst.type(), 1);
1187       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1188       Temp src10 = bld.tmp(src1.type(), 1);
1189       Temp src11 = bld.tmp(dst.type(), 1);
1190       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1191
1192       if (dst.regClass() == s2) {
1193          Temp carry = bld.tmp(s1);
1194          Temp dst0 = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1195          Temp dst1 = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), src01, src11, bld.scc(carry));
1196          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1197       } else if (dst.regClass() == v2) {
1198          Temp dst0 = bld.tmp(v1);
1199          Temp carry = bld.vadd32(Definition(dst0), src00, src10, true).def(1).getTemp();
1200          Temp dst1 = bld.vadd32(bld.def(v1), src01, src11, false, carry);
1201          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1202       } else {
1203          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1204          nir_print_instr(&instr->instr, stderr);
1205          fprintf(stderr, "\n");
1206       }
1207       break;
1208    }
1209    case nir_op_uadd_sat: {
1210       Temp src0 = get_alu_src(ctx, instr->src[0]);
1211       Temp src1 = get_alu_src(ctx, instr->src[1]);
1212       if (dst.regClass() == s1) {
1213          Temp tmp = bld.tmp(s1), carry = bld.tmp(s1);
1214          bld.sop2(aco_opcode::s_add_u32, Definition(tmp), bld.scc(Definition(carry)),
1215                   src0, src1);
1216          bld.sop2(aco_opcode::s_cselect_b32, Definition(dst), Operand((uint32_t) -1), tmp, bld.scc(carry));
1217       } else if (dst.regClass() == v1) {
1218          if (ctx->options->chip_class >= GFX9) {
1219             aco_ptr<VOP3A_instruction> add{create_instruction<VOP3A_instruction>(aco_opcode::v_add_u32, asVOP3(Format::VOP2), 2, 1)};
1220             add->operands[0] = Operand(src0);
1221             add->operands[1] = Operand(src1);
1222             add->definitions[0] = Definition(dst);
1223             add->clamp = 1;
1224             ctx->block->instructions.emplace_back(std::move(add));
1225          } else {
1226             if (src1.regClass() != v1)
1227                std::swap(src0, src1);
1228             assert(src1.regClass() == v1);
1229             Temp tmp = bld.tmp(v1);
1230             Temp carry = bld.vadd32(Definition(tmp), src0, src1, true).def(1).getTemp();
1231             bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), tmp, Operand((uint32_t) -1), carry);
1232          }
1233       } else {
1234          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1235          nir_print_instr(&instr->instr, stderr);
1236          fprintf(stderr, "\n");
1237       }
1238       break;
1239    }
1240    case nir_op_uadd_carry: {
1241       Temp src0 = get_alu_src(ctx, instr->src[0]);
1242       Temp src1 = get_alu_src(ctx, instr->src[1]);
1243       if (dst.regClass() == s1) {
1244          bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(dst)), src0, src1);
1245          break;
1246       }
1247       if (dst.regClass() == v1) {
1248          Temp carry = bld.vadd32(bld.def(v1), src0, src1, true).def(1).getTemp();
1249          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), carry);
1250          break;
1251       }
1252
1253       Temp src00 = bld.tmp(src0.type(), 1);
1254       Temp src01 = bld.tmp(dst.type(), 1);
1255       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1256       Temp src10 = bld.tmp(src1.type(), 1);
1257       Temp src11 = bld.tmp(dst.type(), 1);
1258       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1259       if (dst.regClass() == s2) {
1260          Temp carry = bld.tmp(s1);
1261          bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1262          carry = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.scc(bld.def(s1)), src01, src11, bld.scc(carry)).def(1).getTemp();
1263          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), carry, Operand(0u));
1264       } else if (dst.regClass() == v2) {
1265          Temp carry = bld.vadd32(bld.def(v1), src00, src10, true).def(1).getTemp();
1266          carry = bld.vadd32(bld.def(v1), src01, src11, true, carry).def(1).getTemp();
1267          carry = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand(1u), carry);
1268          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), carry, Operand(0u));
1269       } else {
1270          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1271          nir_print_instr(&instr->instr, stderr);
1272          fprintf(stderr, "\n");
1273       }
1274       break;
1275    }
1276    case nir_op_isub: {
1277       if (dst.regClass() == s1) {
1278          emit_sop2_instruction(ctx, instr, aco_opcode::s_sub_i32, dst, true);
1279          break;
1280       }
1281
1282       Temp src0 = get_alu_src(ctx, instr->src[0]);
1283       Temp src1 = get_alu_src(ctx, instr->src[1]);
1284       if (dst.regClass() == v1) {
1285          bld.vsub32(Definition(dst), src0, src1);
1286          break;
1287       }
1288
1289       Temp src00 = bld.tmp(src0.type(), 1);
1290       Temp src01 = bld.tmp(dst.type(), 1);
1291       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1292       Temp src10 = bld.tmp(src1.type(), 1);
1293       Temp src11 = bld.tmp(dst.type(), 1);
1294       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1295       if (dst.regClass() == s2) {
1296          Temp carry = bld.tmp(s1);
1297          Temp dst0 = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1298          Temp dst1 = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), src01, src11, carry);
1299          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1300       } else if (dst.regClass() == v2) {
1301          Temp lower = bld.tmp(v1);
1302          Temp borrow = bld.vsub32(Definition(lower), src00, src10, true).def(1).getTemp();
1303          Temp upper = bld.vsub32(bld.def(v1), src01, src11, false, borrow);
1304          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1305       } else {
1306          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1307          nir_print_instr(&instr->instr, stderr);
1308          fprintf(stderr, "\n");
1309       }
1310       break;
1311    }
1312    case nir_op_usub_borrow: {
1313       Temp src0 = get_alu_src(ctx, instr->src[0]);
1314       Temp src1 = get_alu_src(ctx, instr->src[1]);
1315       if (dst.regClass() == s1) {
1316          bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(dst)), src0, src1);
1317          break;
1318       } else if (dst.regClass() == v1) {
1319          Temp borrow = bld.vsub32(bld.def(v1), src0, src1, true).def(1).getTemp();
1320          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), borrow);
1321          break;
1322       }
1323
1324       Temp src00 = bld.tmp(src0.type(), 1);
1325       Temp src01 = bld.tmp(dst.type(), 1);
1326       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1327       Temp src10 = bld.tmp(src1.type(), 1);
1328       Temp src11 = bld.tmp(dst.type(), 1);
1329       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1330       if (dst.regClass() == s2) {
1331          Temp borrow = bld.tmp(s1);
1332          bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(borrow)), src00, src10);
1333          borrow = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.scc(bld.def(s1)), src01, src11, bld.scc(borrow)).def(1).getTemp();
1334          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), borrow, Operand(0u));
1335       } else if (dst.regClass() == v2) {
1336          Temp borrow = bld.vsub32(bld.def(v1), src00, src10, true).def(1).getTemp();
1337          borrow = bld.vsub32(bld.def(v1), src01, src11, true, Operand(borrow)).def(1).getTemp();
1338          borrow = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand(1u), borrow);
1339          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), borrow, Operand(0u));
1340       } else {
1341          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1342          nir_print_instr(&instr->instr, stderr);
1343          fprintf(stderr, "\n");
1344       }
1345       break;
1346    }
1347    case nir_op_imul: {
1348       if (dst.regClass() == v1) {
1349          bld.vop3(aco_opcode::v_mul_lo_u32, Definition(dst),
1350                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1351       } else if (dst.regClass() == s1) {
1352          emit_sop2_instruction(ctx, instr, aco_opcode::s_mul_i32, dst, false);
1353       } else {
1354          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1355          nir_print_instr(&instr->instr, stderr);
1356          fprintf(stderr, "\n");
1357       }
1358       break;
1359    }
1360    case nir_op_umul_high: {
1361       if (dst.regClass() == v1) {
1362          bld.vop3(aco_opcode::v_mul_hi_u32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1363       } else if (dst.regClass() == s1 && ctx->options->chip_class >= GFX9) {
1364          bld.sop2(aco_opcode::s_mul_hi_u32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1365       } else if (dst.regClass() == s1) {
1366          Temp tmp = bld.vop3(aco_opcode::v_mul_hi_u32, bld.def(v1), get_alu_src(ctx, instr->src[0]),
1367                              as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1368          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), tmp);
1369       } else {
1370          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1371          nir_print_instr(&instr->instr, stderr);
1372          fprintf(stderr, "\n");
1373       }
1374       break;
1375    }
1376    case nir_op_imul_high: {
1377       if (dst.regClass() == v1) {
1378          bld.vop3(aco_opcode::v_mul_hi_i32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1379       } else if (dst.regClass() == s1 && ctx->options->chip_class >= GFX9) {
1380          bld.sop2(aco_opcode::s_mul_hi_i32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1381       } else if (dst.regClass() == s1) {
1382          Temp tmp = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), get_alu_src(ctx, instr->src[0]),
1383                              as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1384          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), tmp);
1385       } else {
1386          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1387          nir_print_instr(&instr->instr, stderr);
1388          fprintf(stderr, "\n");
1389       }
1390       break;
1391    }
1392    case nir_op_fmul: {
1393       if (dst.size() == 1) {
1394          emit_vop2_instruction(ctx, instr, aco_opcode::v_mul_f32, dst, true);
1395       } else if (dst.size() == 2) {
1396          bld.vop3(aco_opcode::v_mul_f64, Definition(dst), get_alu_src(ctx, instr->src[0]),
1397                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1398       } else {
1399          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1400          nir_print_instr(&instr->instr, stderr);
1401          fprintf(stderr, "\n");
1402       }
1403       break;
1404    }
1405    case nir_op_fadd: {
1406       if (dst.size() == 1) {
1407          emit_vop2_instruction(ctx, instr, aco_opcode::v_add_f32, dst, true);
1408       } else if (dst.size() == 2) {
1409          bld.vop3(aco_opcode::v_add_f64, Definition(dst), get_alu_src(ctx, instr->src[0]),
1410                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1411       } else {
1412          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1413          nir_print_instr(&instr->instr, stderr);
1414          fprintf(stderr, "\n");
1415       }
1416       break;
1417    }
1418    case nir_op_fsub: {
1419       Temp src0 = get_alu_src(ctx, instr->src[0]);
1420       Temp src1 = get_alu_src(ctx, instr->src[1]);
1421       if (dst.size() == 1) {
1422          if (src1.type() == RegType::vgpr || src0.type() != RegType::vgpr)
1423             emit_vop2_instruction(ctx, instr, aco_opcode::v_sub_f32, dst, false);
1424          else
1425             emit_vop2_instruction(ctx, instr, aco_opcode::v_subrev_f32, dst, true);
1426       } else if (dst.size() == 2) {
1427          Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst),
1428                                      get_alu_src(ctx, instr->src[0]),
1429                                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1430          VOP3A_instruction* sub = static_cast<VOP3A_instruction*>(add);
1431          sub->neg[1] = true;
1432       } else {
1433          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1434          nir_print_instr(&instr->instr, stderr);
1435          fprintf(stderr, "\n");
1436       }
1437       break;
1438    }
1439    case nir_op_fmax: {
1440       if (dst.size() == 1) {
1441          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_f32, dst, true, false, ctx->block->fp_mode.must_flush_denorms32);
1442       } else if (dst.size() == 2) {
1443          if (ctx->block->fp_mode.must_flush_denorms16_64 && ctx->program->chip_class < GFX9) {
1444             Temp tmp = bld.vop3(aco_opcode::v_max_f64, bld.def(v2),
1445                                 get_alu_src(ctx, instr->src[0]),
1446                                 as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1447             bld.vop3(aco_opcode::v_mul_f64, Definition(dst), Operand(0x3FF0000000000000lu), tmp);
1448          } else {
1449             bld.vop3(aco_opcode::v_max_f64, Definition(dst),
1450                      get_alu_src(ctx, instr->src[0]),
1451                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1452          }
1453       } else {
1454          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1455          nir_print_instr(&instr->instr, stderr);
1456          fprintf(stderr, "\n");
1457       }
1458       break;
1459    }
1460    case nir_op_fmin: {
1461       if (dst.size() == 1) {
1462          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_f32, dst, true, false, ctx->block->fp_mode.must_flush_denorms32);
1463       } else if (dst.size() == 2) {
1464          if (ctx->block->fp_mode.must_flush_denorms16_64 && ctx->program->chip_class < GFX9) {
1465             Temp tmp = bld.vop3(aco_opcode::v_min_f64, bld.def(v2),
1466                                 get_alu_src(ctx, instr->src[0]),
1467                                 as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1468             bld.vop3(aco_opcode::v_mul_f64, Definition(dst), Operand(0x3FF0000000000000lu), tmp);
1469          } else {
1470             bld.vop3(aco_opcode::v_min_f64, Definition(dst),
1471                      get_alu_src(ctx, instr->src[0]),
1472                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1473          }
1474       } else {
1475          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1476          nir_print_instr(&instr->instr, stderr);
1477          fprintf(stderr, "\n");
1478       }
1479       break;
1480    }
1481    case nir_op_fmax3: {
1482       if (dst.size() == 1) {
1483          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_f32, dst, ctx->block->fp_mode.must_flush_denorms32);
1484       } else {
1485          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1486          nir_print_instr(&instr->instr, stderr);
1487          fprintf(stderr, "\n");
1488       }
1489       break;
1490    }
1491    case nir_op_fmin3: {
1492       if (dst.size() == 1) {
1493          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_f32, dst, ctx->block->fp_mode.must_flush_denorms32);
1494       } else {
1495          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1496          nir_print_instr(&instr->instr, stderr);
1497          fprintf(stderr, "\n");
1498       }
1499       break;
1500    }
1501    case nir_op_fmed3: {
1502       if (dst.size() == 1) {
1503          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_f32, dst, ctx->block->fp_mode.must_flush_denorms32);
1504       } else {
1505          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1506          nir_print_instr(&instr->instr, stderr);
1507          fprintf(stderr, "\n");
1508       }
1509       break;
1510    }
1511    case nir_op_umax3: {
1512       if (dst.size() == 1) {
1513          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_u32, dst);
1514       } else {
1515          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1516          nir_print_instr(&instr->instr, stderr);
1517          fprintf(stderr, "\n");
1518       }
1519       break;
1520    }
1521    case nir_op_umin3: {
1522       if (dst.size() == 1) {
1523          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_u32, dst);
1524       } else {
1525          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1526          nir_print_instr(&instr->instr, stderr);
1527          fprintf(stderr, "\n");
1528       }
1529       break;
1530    }
1531    case nir_op_umed3: {
1532       if (dst.size() == 1) {
1533          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_u32, dst);
1534       } else {
1535          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1536          nir_print_instr(&instr->instr, stderr);
1537          fprintf(stderr, "\n");
1538       }
1539       break;
1540    }
1541    case nir_op_imax3: {
1542       if (dst.size() == 1) {
1543          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_i32, dst);
1544       } else {
1545          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1546          nir_print_instr(&instr->instr, stderr);
1547          fprintf(stderr, "\n");
1548       }
1549       break;
1550    }
1551    case nir_op_imin3: {
1552       if (dst.size() == 1) {
1553          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_i32, dst);
1554       } else {
1555          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1556          nir_print_instr(&instr->instr, stderr);
1557          fprintf(stderr, "\n");
1558       }
1559       break;
1560    }
1561    case nir_op_imed3: {
1562       if (dst.size() == 1) {
1563          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_i32, dst);
1564       } else {
1565          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1566          nir_print_instr(&instr->instr, stderr);
1567          fprintf(stderr, "\n");
1568       }
1569       break;
1570    }
1571    case nir_op_cube_face_coord: {
1572       Temp in = get_alu_src(ctx, instr->src[0], 3);
1573       Temp src[3] = { emit_extract_vector(ctx, in, 0, v1),
1574                       emit_extract_vector(ctx, in, 1, v1),
1575                       emit_extract_vector(ctx, in, 2, v1) };
1576       Temp ma = bld.vop3(aco_opcode::v_cubema_f32, bld.def(v1), src[0], src[1], src[2]);
1577       ma = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), ma);
1578       Temp sc = bld.vop3(aco_opcode::v_cubesc_f32, bld.def(v1), src[0], src[1], src[2]);
1579       Temp tc = bld.vop3(aco_opcode::v_cubetc_f32, bld.def(v1), src[0], src[1], src[2]);
1580       sc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), sc, ma, Operand(0x3f000000u/*0.5*/));
1581       tc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), tc, ma, Operand(0x3f000000u/*0.5*/));
1582       bld.pseudo(aco_opcode::p_create_vector, Definition(dst), sc, tc);
1583       break;
1584    }
1585    case nir_op_cube_face_index: {
1586       Temp in = get_alu_src(ctx, instr->src[0], 3);
1587       Temp src[3] = { emit_extract_vector(ctx, in, 0, v1),
1588                       emit_extract_vector(ctx, in, 1, v1),
1589                       emit_extract_vector(ctx, in, 2, v1) };
1590       bld.vop3(aco_opcode::v_cubeid_f32, Definition(dst), src[0], src[1], src[2]);
1591       break;
1592    }
1593    case nir_op_bcsel: {
1594       emit_bcsel(ctx, instr, dst);
1595       break;
1596    }
1597    case nir_op_frsq: {
1598       if (dst.size() == 1) {
1599          emit_rsq(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1600       } else if (dst.size() == 2) {
1601          emit_vop1_instruction(ctx, instr, aco_opcode::v_rsq_f64, dst);
1602       } else {
1603          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1604          nir_print_instr(&instr->instr, stderr);
1605          fprintf(stderr, "\n");
1606       }
1607       break;
1608    }
1609    case nir_op_fneg: {
1610       Temp src = get_alu_src(ctx, instr->src[0]);
1611       if (dst.size() == 1) {
1612          if (ctx->block->fp_mode.must_flush_denorms32)
1613             src = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x3f800000u), as_vgpr(ctx, src));
1614          bld.vop2(aco_opcode::v_xor_b32, Definition(dst), Operand(0x80000000u), as_vgpr(ctx, src));
1615       } else if (dst.size() == 2) {
1616          if (ctx->block->fp_mode.must_flush_denorms16_64)
1617             src = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), Operand(0x3FF0000000000000lu), as_vgpr(ctx, src));
1618          Temp upper = bld.tmp(v1), lower = bld.tmp(v1);
1619          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1620          upper = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), Operand(0x80000000u), upper);
1621          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1622       } else {
1623          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1624          nir_print_instr(&instr->instr, stderr);
1625          fprintf(stderr, "\n");
1626       }
1627       break;
1628    }
1629    case nir_op_fabs: {
1630       Temp src = get_alu_src(ctx, instr->src[0]);
1631       if (dst.size() == 1) {
1632          if (ctx->block->fp_mode.must_flush_denorms32)
1633             src = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x3f800000u), as_vgpr(ctx, src));
1634          bld.vop2(aco_opcode::v_and_b32, Definition(dst), Operand(0x7FFFFFFFu), as_vgpr(ctx, src));
1635       } else if (dst.size() == 2) {
1636          if (ctx->block->fp_mode.must_flush_denorms16_64)
1637             src = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), Operand(0x3FF0000000000000lu), as_vgpr(ctx, src));
1638          Temp upper = bld.tmp(v1), lower = bld.tmp(v1);
1639          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1640          upper = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7FFFFFFFu), upper);
1641          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1642       } else {
1643          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1644          nir_print_instr(&instr->instr, stderr);
1645          fprintf(stderr, "\n");
1646       }
1647       break;
1648    }
1649    case nir_op_fsat: {
1650       Temp src = get_alu_src(ctx, instr->src[0]);
1651       if (dst.size() == 1) {
1652          bld.vop3(aco_opcode::v_med3_f32, Definition(dst), Operand(0u), Operand(0x3f800000u), src);
1653          /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1654          // TODO: confirm that this holds under any circumstances
1655       } else if (dst.size() == 2) {
1656          Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst), src, Operand(0u));
1657          VOP3A_instruction* vop3 = static_cast<VOP3A_instruction*>(add);
1658          vop3->clamp = true;
1659       } else {
1660          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1661          nir_print_instr(&instr->instr, stderr);
1662          fprintf(stderr, "\n");
1663       }
1664       break;
1665    }
1666    case nir_op_flog2: {
1667       if (dst.size() == 1) {
1668          emit_log2(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1669       } else {
1670          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1671          nir_print_instr(&instr->instr, stderr);
1672          fprintf(stderr, "\n");
1673       }
1674       break;
1675    }
1676    case nir_op_frcp: {
1677       if (dst.size() == 1) {
1678          emit_rcp(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1679       } else if (dst.size() == 2) {
1680          emit_vop1_instruction(ctx, instr, aco_opcode::v_rcp_f64, dst);
1681       } else {
1682          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1683          nir_print_instr(&instr->instr, stderr);
1684          fprintf(stderr, "\n");
1685       }
1686       break;
1687    }
1688    case nir_op_fexp2: {
1689       if (dst.size() == 1) {
1690          emit_vop1_instruction(ctx, instr, aco_opcode::v_exp_f32, dst);
1691       } else {
1692          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1693          nir_print_instr(&instr->instr, stderr);
1694          fprintf(stderr, "\n");
1695       }
1696       break;
1697    }
1698    case nir_op_fsqrt: {
1699       if (dst.size() == 1) {
1700          emit_sqrt(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1701       } else if (dst.size() == 2) {
1702          emit_vop1_instruction(ctx, instr, aco_opcode::v_sqrt_f64, dst);
1703       } else {
1704          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1705          nir_print_instr(&instr->instr, stderr);
1706          fprintf(stderr, "\n");
1707       }
1708       break;
1709    }
1710    case nir_op_ffract: {
1711       if (dst.size() == 1) {
1712          emit_vop1_instruction(ctx, instr, aco_opcode::v_fract_f32, dst);
1713       } else if (dst.size() == 2) {
1714          emit_vop1_instruction(ctx, instr, aco_opcode::v_fract_f64, dst);
1715       } else {
1716          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1717          nir_print_instr(&instr->instr, stderr);
1718          fprintf(stderr, "\n");
1719       }
1720       break;
1721    }
1722    case nir_op_ffloor: {
1723       if (dst.size() == 1) {
1724          emit_vop1_instruction(ctx, instr, aco_opcode::v_floor_f32, dst);
1725       } else if (dst.size() == 2) {
1726          emit_floor_f64(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1727       } else {
1728          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1729          nir_print_instr(&instr->instr, stderr);
1730          fprintf(stderr, "\n");
1731       }
1732       break;
1733    }
1734    case nir_op_fceil: {
1735       if (dst.size() == 1) {
1736          emit_vop1_instruction(ctx, instr, aco_opcode::v_ceil_f32, dst);
1737       } else if (dst.size() == 2) {
1738          if (ctx->options->chip_class >= GFX7) {
1739             emit_vop1_instruction(ctx, instr, aco_opcode::v_ceil_f64, dst);
1740          } else {
1741             /* GFX6 doesn't support V_CEIL_F64, lower it. */
1742             Temp src0 = get_alu_src(ctx, instr->src[0]);
1743
1744             /* trunc = trunc(src0)
1745              * if (src0 > 0.0 && src0 != trunc)
1746              *    trunc += 1.0
1747              */
1748             Temp trunc = emit_trunc_f64(ctx, bld, bld.def(v2), src0);
1749             Temp tmp0 = bld.vopc_e64(aco_opcode::v_cmp_gt_f64, bld.def(bld.lm), src0, Operand(0u));
1750             Temp tmp1 = bld.vopc(aco_opcode::v_cmp_lg_f64, bld.hint_vcc(bld.def(bld.lm)), src0, trunc);
1751             Temp cond = bld.sop2(aco_opcode::s_and_b64, bld.hint_vcc(bld.def(s2)), bld.def(s1, scc), tmp0, tmp1);
1752             Temp add = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), bld.copy(bld.def(v1), Operand(0u)), bld.copy(bld.def(v1), Operand(0x3ff00000u)), cond);
1753             add = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), bld.copy(bld.def(v1), Operand(0u)), add);
1754             bld.vop3(aco_opcode::v_add_f64, Definition(dst), trunc, add);
1755          }
1756       } else {
1757          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1758          nir_print_instr(&instr->instr, stderr);
1759          fprintf(stderr, "\n");
1760       }
1761       break;
1762    }
1763    case nir_op_ftrunc: {
1764       if (dst.size() == 1) {
1765          emit_vop1_instruction(ctx, instr, aco_opcode::v_trunc_f32, dst);
1766       } else if (dst.size() == 2) {
1767          emit_trunc_f64(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1768       } else {
1769          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1770          nir_print_instr(&instr->instr, stderr);
1771          fprintf(stderr, "\n");
1772       }
1773       break;
1774    }
1775    case nir_op_fround_even: {
1776       if (dst.size() == 1) {
1777          emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f32, dst);
1778       } else if (dst.size() == 2) {
1779          if (ctx->options->chip_class >= GFX7) {
1780             emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f64, dst);
1781          } else {
1782             /* GFX6 doesn't support V_RNDNE_F64, lower it. */
1783             Temp src0 = get_alu_src(ctx, instr->src[0]);
1784
1785             Temp src0_lo = bld.tmp(v1), src0_hi = bld.tmp(v1);
1786             bld.pseudo(aco_opcode::p_split_vector, Definition(src0_lo), Definition(src0_hi), src0);
1787
1788             Temp bitmask = bld.sop1(aco_opcode::s_brev_b32, bld.def(s1), bld.copy(bld.def(s1), Operand(-2u)));
1789             Temp bfi = bld.vop3(aco_opcode::v_bfi_b32, bld.def(v1), bitmask, bld.copy(bld.def(v1), Operand(0x43300000u)), as_vgpr(ctx, src0_hi));
1790             Temp tmp = bld.vop3(aco_opcode::v_add_f64, bld.def(v2), src0, bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), bfi));
1791             Instruction *sub = bld.vop3(aco_opcode::v_add_f64, bld.def(v2), tmp, bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), bfi));
1792             static_cast<VOP3A_instruction*>(sub)->neg[1] = true;
1793             tmp = sub->definitions[0].getTemp();
1794
1795             Temp v = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(-1u), Operand(0x432fffffu));
1796             Instruction* vop3 = bld.vopc_e64(aco_opcode::v_cmp_gt_f64, bld.hint_vcc(bld.def(bld.lm)), src0, v);
1797             static_cast<VOP3A_instruction*>(vop3)->abs[0] = true;
1798             Temp cond = vop3->definitions[0].getTemp();
1799
1800             Temp tmp_lo = bld.tmp(v1), tmp_hi = bld.tmp(v1);
1801             bld.pseudo(aco_opcode::p_split_vector, Definition(tmp_lo), Definition(tmp_hi), tmp);
1802             Temp dst0 = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), tmp_lo, as_vgpr(ctx, src0_lo), cond);
1803             Temp dst1 = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), tmp_hi, as_vgpr(ctx, src0_hi), cond);
1804
1805             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1806          }
1807       } else {
1808          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1809          nir_print_instr(&instr->instr, stderr);
1810          fprintf(stderr, "\n");
1811       }
1812       break;
1813    }
1814    case nir_op_fsin:
1815    case nir_op_fcos: {
1816       Temp src = get_alu_src(ctx, instr->src[0]);
1817       aco_ptr<Instruction> norm;
1818       if (dst.size() == 1) {
1819          Temp half_pi = bld.copy(bld.def(s1), Operand(0x3e22f983u));
1820          Temp tmp = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), half_pi, as_vgpr(ctx, src));
1821
1822          /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
1823          if (ctx->options->chip_class < GFX9)
1824             tmp = bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), tmp);
1825
1826          aco_opcode opcode = instr->op == nir_op_fsin ? aco_opcode::v_sin_f32 : aco_opcode::v_cos_f32;
1827          bld.vop1(opcode, Definition(dst), tmp);
1828       } else {
1829          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1830          nir_print_instr(&instr->instr, stderr);
1831          fprintf(stderr, "\n");
1832       }
1833       break;
1834    }
1835    case nir_op_ldexp: {
1836       if (dst.size() == 1) {
1837          bld.vop3(aco_opcode::v_ldexp_f32, Definition(dst),
1838                   as_vgpr(ctx, get_alu_src(ctx, instr->src[0])),
1839                   get_alu_src(ctx, instr->src[1]));
1840       } else if (dst.size() == 2) {
1841          bld.vop3(aco_opcode::v_ldexp_f64, Definition(dst),
1842                   as_vgpr(ctx, get_alu_src(ctx, instr->src[0])),
1843                   get_alu_src(ctx, instr->src[1]));
1844       } else {
1845          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1846          nir_print_instr(&instr->instr, stderr);
1847          fprintf(stderr, "\n");
1848       }
1849       break;
1850    }
1851    case nir_op_frexp_sig: {
1852       if (dst.size() == 1) {
1853          bld.vop1(aco_opcode::v_frexp_mant_f32, Definition(dst),
1854                   get_alu_src(ctx, instr->src[0]));
1855       } else if (dst.size() == 2) {
1856          bld.vop1(aco_opcode::v_frexp_mant_f64, Definition(dst),
1857                   get_alu_src(ctx, instr->src[0]));
1858       } else {
1859          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1860          nir_print_instr(&instr->instr, stderr);
1861          fprintf(stderr, "\n");
1862       }
1863       break;
1864    }
1865    case nir_op_frexp_exp: {
1866       if (instr->src[0].src.ssa->bit_size == 32) {
1867          bld.vop1(aco_opcode::v_frexp_exp_i32_f32, Definition(dst),
1868                   get_alu_src(ctx, instr->src[0]));
1869       } else if (instr->src[0].src.ssa->bit_size == 64) {
1870          bld.vop1(aco_opcode::v_frexp_exp_i32_f64, Definition(dst),
1871                   get_alu_src(ctx, instr->src[0]));
1872       } else {
1873          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1874          nir_print_instr(&instr->instr, stderr);
1875          fprintf(stderr, "\n");
1876       }
1877       break;
1878    }
1879    case nir_op_fsign: {
1880       Temp src = as_vgpr(ctx, get_alu_src(ctx, instr->src[0]));
1881       if (dst.size() == 1) {
1882          Temp cond = bld.vopc(aco_opcode::v_cmp_nlt_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1883          src = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0x3f800000u), src, cond);
1884          cond = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1885          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0xbf800000u), src, cond);
1886       } else if (dst.size() == 2) {
1887          Temp cond = bld.vopc(aco_opcode::v_cmp_nlt_f64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1888          Temp tmp = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0x3FF00000u));
1889          Temp upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), tmp, emit_extract_vector(ctx, src, 1, v1), cond);
1890
1891          cond = bld.vopc(aco_opcode::v_cmp_le_f64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1892          tmp = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0xBFF00000u));
1893          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), tmp, upper, cond);
1894
1895          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), Operand(0u), upper);
1896       } else {
1897          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1898          nir_print_instr(&instr->instr, stderr);
1899          fprintf(stderr, "\n");
1900       }
1901       break;
1902    }
1903    case nir_op_f2f32: {
1904       if (instr->src[0].src.ssa->bit_size == 64) {
1905          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_f64, dst);
1906       } else {
1907          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1908          nir_print_instr(&instr->instr, stderr);
1909          fprintf(stderr, "\n");
1910       }
1911       break;
1912    }
1913    case nir_op_f2f64: {
1914       if (instr->src[0].src.ssa->bit_size == 32) {
1915          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_f32, dst);
1916       } else {
1917          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1918          nir_print_instr(&instr->instr, stderr);
1919          fprintf(stderr, "\n");
1920       }
1921       break;
1922    }
1923    case nir_op_i2f32: {
1924       assert(dst.size() == 1);
1925       emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_i32, dst);
1926       break;
1927    }
1928    case nir_op_i2f64: {
1929       if (instr->src[0].src.ssa->bit_size == 32) {
1930          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_i32, dst);
1931       } else if (instr->src[0].src.ssa->bit_size == 64) {
1932          Temp src = get_alu_src(ctx, instr->src[0]);
1933          RegClass rc = RegClass(src.type(), 1);
1934          Temp lower = bld.tmp(rc), upper = bld.tmp(rc);
1935          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1936          lower = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), lower);
1937          upper = bld.vop1(aco_opcode::v_cvt_f64_i32, bld.def(v2), upper);
1938          upper = bld.vop3(aco_opcode::v_ldexp_f64, bld.def(v2), upper, Operand(32u));
1939          bld.vop3(aco_opcode::v_add_f64, Definition(dst), lower, upper);
1940
1941       } else {
1942          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1943          nir_print_instr(&instr->instr, stderr);
1944          fprintf(stderr, "\n");
1945       }
1946       break;
1947    }
1948    case nir_op_u2f32: {
1949       assert(dst.size() == 1);
1950       emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_u32, dst);
1951       break;
1952    }
1953    case nir_op_u2f64: {
1954       if (instr->src[0].src.ssa->bit_size == 32) {
1955          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_u32, dst);
1956       } else if (instr->src[0].src.ssa->bit_size == 64) {
1957          Temp src = get_alu_src(ctx, instr->src[0]);
1958          RegClass rc = RegClass(src.type(), 1);
1959          Temp lower = bld.tmp(rc), upper = bld.tmp(rc);
1960          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1961          lower = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), lower);
1962          upper = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), upper);
1963          upper = bld.vop3(aco_opcode::v_ldexp_f64, bld.def(v2), upper, Operand(32u));
1964          bld.vop3(aco_opcode::v_add_f64, Definition(dst), lower, upper);
1965       } else {
1966          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1967          nir_print_instr(&instr->instr, stderr);
1968          fprintf(stderr, "\n");
1969       }
1970       break;
1971    }
1972    case nir_op_f2i32: {
1973       Temp src = get_alu_src(ctx, instr->src[0]);
1974       if (instr->src[0].src.ssa->bit_size == 32) {
1975          if (dst.type() == RegType::vgpr)
1976             bld.vop1(aco_opcode::v_cvt_i32_f32, Definition(dst), src);
1977          else
1978             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1979                        bld.vop1(aco_opcode::v_cvt_i32_f32, bld.def(v1), src));
1980
1981       } else if (instr->src[0].src.ssa->bit_size == 64) {
1982          if (dst.type() == RegType::vgpr)
1983             bld.vop1(aco_opcode::v_cvt_i32_f64, Definition(dst), src);
1984          else
1985             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1986                        bld.vop1(aco_opcode::v_cvt_i32_f64, bld.def(v1), src));
1987
1988       } else {
1989          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1990          nir_print_instr(&instr->instr, stderr);
1991          fprintf(stderr, "\n");
1992       }
1993       break;
1994    }
1995    case nir_op_f2u32: {
1996       Temp src = get_alu_src(ctx, instr->src[0]);
1997       if (instr->src[0].src.ssa->bit_size == 32) {
1998          if (dst.type() == RegType::vgpr)
1999             bld.vop1(aco_opcode::v_cvt_u32_f32, Definition(dst), src);
2000          else
2001             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
2002                        bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), src));
2003
2004       } else if (instr->src[0].src.ssa->bit_size == 64) {
2005          if (dst.type() == RegType::vgpr)
2006             bld.vop1(aco_opcode::v_cvt_u32_f64, Definition(dst), src);
2007          else
2008             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
2009                        bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), src));
2010
2011       } else {
2012          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2013          nir_print_instr(&instr->instr, stderr);
2014          fprintf(stderr, "\n");
2015       }
2016       break;
2017    }
2018    case nir_op_f2i64: {
2019       Temp src = get_alu_src(ctx, instr->src[0]);
2020       if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::vgpr) {
2021          Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f32, bld.def(v1), src);
2022          exponent = bld.vop3(aco_opcode::v_med3_i32, bld.def(v1), Operand(0x0u), exponent, Operand(64u));
2023          Temp mantissa = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffu), src);
2024          Temp sign = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
2025          mantissa = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(0x800000u), mantissa);
2026          mantissa = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(7u), mantissa);
2027          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), mantissa);
2028          Temp new_exponent = bld.tmp(v1);
2029          Temp borrow = bld.vsub32(Definition(new_exponent), Operand(63u), exponent, true).def(1).getTemp();
2030          if (ctx->program->chip_class >= GFX8)
2031             mantissa = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), new_exponent, mantissa);
2032          else
2033             mantissa = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), mantissa, new_exponent);
2034          Temp saturate = bld.vop1(aco_opcode::v_bfrev_b32, bld.def(v1), Operand(0xfffffffeu));
2035          Temp lower = bld.tmp(v1), upper = bld.tmp(v1);
2036          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2037          lower = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), lower, Operand(0xffffffffu), borrow);
2038          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), upper, saturate, borrow);
2039          lower = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), sign, lower);
2040          upper = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), sign, upper);
2041          Temp new_lower = bld.tmp(v1);
2042          borrow = bld.vsub32(Definition(new_lower), lower, sign, true).def(1).getTemp();
2043          Temp new_upper = bld.vsub32(bld.def(v1), upper, sign, false, borrow);
2044          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), new_lower, new_upper);
2045
2046       } else if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::sgpr) {
2047          if (src.type() == RegType::vgpr)
2048             src = bld.as_uniform(src);
2049          Temp exponent = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), src, Operand(0x80017u));
2050          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(126u));
2051          exponent = bld.sop2(aco_opcode::s_max_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), exponent);
2052          exponent = bld.sop2(aco_opcode::s_min_u32, bld.def(s1), bld.def(s1, scc), Operand(64u), exponent);
2053          Temp mantissa = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0x7fffffu), src);
2054          Temp sign = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
2055          mantissa = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(0x800000u), mantissa);
2056          mantissa = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), mantissa, Operand(7u));
2057          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), mantissa);
2058          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), Operand(63u), exponent);
2059          mantissa = bld.sop2(aco_opcode::s_lshr_b64, bld.def(s2), bld.def(s1, scc), mantissa, exponent);
2060          Temp cond = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), exponent, Operand(0xffffffffu)); // exp >= 64
2061          Temp saturate = bld.sop1(aco_opcode::s_brev_b64, bld.def(s2), Operand(0xfffffffeu));
2062          mantissa = bld.sop2(aco_opcode::s_cselect_b64, bld.def(s2), saturate, mantissa, cond);
2063          Temp lower = bld.tmp(s1), upper = bld.tmp(s1);
2064          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2065          lower = bld.sop2(aco_opcode::s_xor_b32, bld.def(s1), bld.def(s1, scc), sign, lower);
2066          upper = bld.sop2(aco_opcode::s_xor_b32, bld.def(s1), bld.def(s1, scc), sign, upper);
2067          Temp borrow = bld.tmp(s1);
2068          lower = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(borrow)), lower, sign);
2069          upper = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), upper, sign, borrow);
2070          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2071
2072       } else if (instr->src[0].src.ssa->bit_size == 64) {
2073          Temp vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0x3df00000u));
2074          Temp trunc = emit_trunc_f64(ctx, bld, bld.def(v2), src);
2075          Temp mul = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), trunc, vec);
2076          vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0xc1f00000u));
2077          Temp floor = emit_floor_f64(ctx, bld, bld.def(v2), mul);
2078          Temp fma = bld.vop3(aco_opcode::v_fma_f64, bld.def(v2), floor, vec, trunc);
2079          Temp lower = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), fma);
2080          Temp upper = bld.vop1(aco_opcode::v_cvt_i32_f64, bld.def(v1), floor);
2081          if (dst.type() == RegType::sgpr) {
2082             lower = bld.as_uniform(lower);
2083             upper = bld.as_uniform(upper);
2084          }
2085          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2086
2087       } else {
2088          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2089          nir_print_instr(&instr->instr, stderr);
2090          fprintf(stderr, "\n");
2091       }
2092       break;
2093    }
2094    case nir_op_f2u64: {
2095       Temp src = get_alu_src(ctx, instr->src[0]);
2096       if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::vgpr) {
2097          Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f32, bld.def(v1), src);
2098          Temp exponent_in_range = bld.vopc(aco_opcode::v_cmp_ge_i32, bld.hint_vcc(bld.def(bld.lm)), Operand(64u), exponent);
2099          exponent = bld.vop2(aco_opcode::v_max_i32, bld.def(v1), Operand(0x0u), exponent);
2100          Temp mantissa = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffu), src);
2101          mantissa = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(0x800000u), mantissa);
2102          Temp exponent_small = bld.vsub32(bld.def(v1), Operand(24u), exponent);
2103          Temp small = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), exponent_small, mantissa);
2104          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), mantissa);
2105          Temp new_exponent = bld.tmp(v1);
2106          Temp cond_small = bld.vsub32(Definition(new_exponent), exponent, Operand(24u), true).def(1).getTemp();
2107          if (ctx->program->chip_class >= GFX8)
2108             mantissa = bld.vop3(aco_opcode::v_lshlrev_b64, bld.def(v2), new_exponent, mantissa);
2109          else
2110             mantissa = bld.vop3(aco_opcode::v_lshl_b64, bld.def(v2), mantissa, new_exponent);
2111          Temp lower = bld.tmp(v1), upper = bld.tmp(v1);
2112          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2113          lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), lower, small, cond_small);
2114          upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), upper, Operand(0u), cond_small);
2115          lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xffffffffu), lower, exponent_in_range);
2116          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xffffffffu), upper, exponent_in_range);
2117          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2118
2119       } else if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::sgpr) {
2120          if (src.type() == RegType::vgpr)
2121             src = bld.as_uniform(src);
2122          Temp exponent = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), src, Operand(0x80017u));
2123          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(126u));
2124          exponent = bld.sop2(aco_opcode::s_max_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), exponent);
2125          Temp mantissa = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0x7fffffu), src);
2126          mantissa = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(0x800000u), mantissa);
2127          Temp exponent_small = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), Operand(24u), exponent);
2128          Temp small = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), mantissa, exponent_small);
2129          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), mantissa);
2130          Temp exponent_large = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(24u));
2131          mantissa = bld.sop2(aco_opcode::s_lshl_b64, bld.def(s2), bld.def(s1, scc), mantissa, exponent_large);
2132          Temp cond = bld.sopc(aco_opcode::s_cmp_ge_i32, bld.def(s1, scc), Operand(64u), exponent);
2133          mantissa = bld.sop2(aco_opcode::s_cselect_b64, bld.def(s2), mantissa, Operand(0xffffffffu), cond);
2134          Temp lower = bld.tmp(s1), upper = bld.tmp(s1);
2135          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2136          Temp cond_small = bld.sopc(aco_opcode::s_cmp_le_i32, bld.def(s1, scc), exponent, Operand(24u));
2137          lower = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), small, lower, cond_small);
2138          upper = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), Operand(0u), upper, cond_small);
2139          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2140
2141       } else if (instr->src[0].src.ssa->bit_size == 64) {
2142          Temp vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0x3df00000u));
2143          Temp trunc = emit_trunc_f64(ctx, bld, bld.def(v2), src);
2144          Temp mul = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), trunc, vec);
2145          vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0xc1f00000u));
2146          Temp floor = emit_floor_f64(ctx, bld, bld.def(v2), mul);
2147          Temp fma = bld.vop3(aco_opcode::v_fma_f64, bld.def(v2), floor, vec, trunc);
2148          Temp lower = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), fma);
2149          Temp upper = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), floor);
2150          if (dst.type() == RegType::sgpr) {
2151             lower = bld.as_uniform(lower);
2152             upper = bld.as_uniform(upper);
2153          }
2154          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2155
2156       } else {
2157          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2158          nir_print_instr(&instr->instr, stderr);
2159          fprintf(stderr, "\n");
2160       }
2161       break;
2162    }
2163    case nir_op_b2f32: {
2164       Temp src = get_alu_src(ctx, instr->src[0]);
2165       assert(src.regClass() == bld.lm);
2166
2167       if (dst.regClass() == s1) {
2168          src = bool_to_scalar_condition(ctx, src);
2169          bld.sop2(aco_opcode::s_mul_i32, Definition(dst), Operand(0x3f800000u), src);
2170       } else if (dst.regClass() == v1) {
2171          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(0x3f800000u), src);
2172       } else {
2173          unreachable("Wrong destination register class for nir_op_b2f32.");
2174       }
2175       break;
2176    }
2177    case nir_op_b2f64: {
2178       Temp src = get_alu_src(ctx, instr->src[0]);
2179       assert(src.regClass() == bld.lm);
2180
2181       if (dst.regClass() == s2) {
2182          src = bool_to_scalar_condition(ctx, src);
2183          bld.sop2(aco_opcode::s_cselect_b64, Definition(dst), Operand(0x3f800000u), Operand(0u), bld.scc(src));
2184       } else if (dst.regClass() == v2) {
2185          Temp one = bld.vop1(aco_opcode::v_mov_b32, bld.def(v2), Operand(0x3FF00000u));
2186          Temp upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), one, src);
2187          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), Operand(0u), upper);
2188       } else {
2189          unreachable("Wrong destination register class for nir_op_b2f64.");
2190       }
2191       break;
2192    }
2193    case nir_op_i2i32: {
2194       Temp src = get_alu_src(ctx, instr->src[0]);
2195       if (instr->src[0].src.ssa->bit_size == 64) {
2196          /* we can actually just say dst = src, as it would map the lower register */
2197          emit_extract_vector(ctx, src, 0, dst);
2198       } else {
2199          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2200          nir_print_instr(&instr->instr, stderr);
2201          fprintf(stderr, "\n");
2202       }
2203       break;
2204    }
2205    case nir_op_u2u32: {
2206       Temp src = get_alu_src(ctx, instr->src[0]);
2207       if (instr->src[0].src.ssa->bit_size == 16) {
2208          if (dst.regClass() == s1) {
2209             bld.sop2(aco_opcode::s_and_b32, Definition(dst), bld.def(s1, scc), Operand(0xFFFFu), src);
2210          } else {
2211             // TODO: do better with SDWA
2212             bld.vop2(aco_opcode::v_and_b32, Definition(dst), Operand(0xFFFFu), src);
2213          }
2214       } else if (instr->src[0].src.ssa->bit_size == 64) {
2215          /* we can actually just say dst = src, as it would map the lower register */
2216          emit_extract_vector(ctx, src, 0, dst);
2217       } else {
2218          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2219          nir_print_instr(&instr->instr, stderr);
2220          fprintf(stderr, "\n");
2221       }
2222       break;
2223    }
2224    case nir_op_i2i64: {
2225       Temp src = get_alu_src(ctx, instr->src[0]);
2226       if (src.regClass() == s1) {
2227          Temp high = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
2228          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, high);
2229       } else if (src.regClass() == v1) {
2230          Temp high = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
2231          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, high);
2232       } else {
2233          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2234          nir_print_instr(&instr->instr, stderr);
2235          fprintf(stderr, "\n");
2236       }
2237       break;
2238    }
2239    case nir_op_u2u64: {
2240       Temp src = get_alu_src(ctx, instr->src[0]);
2241       if (instr->src[0].src.ssa->bit_size == 32) {
2242          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, Operand(0u));
2243       } else {
2244          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2245          nir_print_instr(&instr->instr, stderr);
2246          fprintf(stderr, "\n");
2247       }
2248       break;
2249    }
2250    case nir_op_b2i32: {
2251       Temp src = get_alu_src(ctx, instr->src[0]);
2252       assert(src.regClass() == bld.lm);
2253
2254       if (dst.regClass() == s1) {
2255          // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2256          bool_to_scalar_condition(ctx, src, dst);
2257       } else if (dst.regClass() == v1) {
2258          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), src);
2259       } else {
2260          unreachable("Invalid register class for b2i32");
2261       }
2262       break;
2263    }
2264    case nir_op_i2b1: {
2265       Temp src = get_alu_src(ctx, instr->src[0]);
2266       assert(dst.regClass() == bld.lm);
2267
2268       if (src.type() == RegType::vgpr) {
2269          assert(src.regClass() == v1 || src.regClass() == v2);
2270          assert(dst.regClass() == bld.lm);
2271          bld.vopc(src.size() == 2 ? aco_opcode::v_cmp_lg_u64 : aco_opcode::v_cmp_lg_u32,
2272                   Definition(dst), Operand(0u), src).def(0).setHint(vcc);
2273       } else {
2274          assert(src.regClass() == s1 || src.regClass() == s2);
2275          Temp tmp;
2276          if (src.regClass() == s2 && ctx->program->chip_class <= GFX7) {
2277             tmp = bld.sop2(aco_opcode::s_or_b64, bld.def(s2), bld.def(s1, scc), Operand(0u), src).def(1).getTemp();
2278          } else {
2279             tmp = bld.sopc(src.size() == 2 ? aco_opcode::s_cmp_lg_u64 : aco_opcode::s_cmp_lg_u32,
2280                            bld.scc(bld.def(s1)), Operand(0u), src);
2281          }
2282          bool_to_vector_condition(ctx, tmp, dst);
2283       }
2284       break;
2285    }
2286    case nir_op_pack_64_2x32_split: {
2287       Temp src0 = get_alu_src(ctx, instr->src[0]);
2288       Temp src1 = get_alu_src(ctx, instr->src[1]);
2289
2290       bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src0, src1);
2291       break;
2292    }
2293    case nir_op_unpack_64_2x32_split_x:
2294       bld.pseudo(aco_opcode::p_split_vector, Definition(dst), bld.def(dst.regClass()), get_alu_src(ctx, instr->src[0]));
2295       break;
2296    case nir_op_unpack_64_2x32_split_y:
2297       bld.pseudo(aco_opcode::p_split_vector, bld.def(dst.regClass()), Definition(dst), get_alu_src(ctx, instr->src[0]));
2298       break;
2299    case nir_op_pack_half_2x16: {
2300       Temp src = get_alu_src(ctx, instr->src[0], 2);
2301
2302       if (dst.regClass() == v1) {
2303          Temp src0 = bld.tmp(v1);
2304          Temp src1 = bld.tmp(v1);
2305          bld.pseudo(aco_opcode::p_split_vector, Definition(src0), Definition(src1), src);
2306          if (!ctx->block->fp_mode.care_about_round32 || ctx->block->fp_mode.round32 == fp_round_tz)
2307             bld.vop3(aco_opcode::v_cvt_pkrtz_f16_f32, Definition(dst), src0, src1);
2308          else
2309             bld.vop3(aco_opcode::v_cvt_pk_u16_u32, Definition(dst),
2310                      bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src0),
2311                      bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src1));
2312       } else {
2313          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2314          nir_print_instr(&instr->instr, stderr);
2315          fprintf(stderr, "\n");
2316       }
2317       break;
2318    }
2319    case nir_op_unpack_half_2x16_split_x: {
2320       if (dst.regClass() == v1) {
2321          Builder bld(ctx->program, ctx->block);
2322          bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst), get_alu_src(ctx, instr->src[0]));
2323       } else {
2324          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2325          nir_print_instr(&instr->instr, stderr);
2326          fprintf(stderr, "\n");
2327       }
2328       break;
2329    }
2330    case nir_op_unpack_half_2x16_split_y: {
2331       if (dst.regClass() == v1) {
2332          Builder bld(ctx->program, ctx->block);
2333          /* TODO: use SDWA here */
2334          bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst),
2335                   bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(16u), as_vgpr(ctx, get_alu_src(ctx, instr->src[0]))));
2336       } else {
2337          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2338          nir_print_instr(&instr->instr, stderr);
2339          fprintf(stderr, "\n");
2340       }
2341       break;
2342    }
2343    case nir_op_fquantize2f16: {
2344       Temp src = get_alu_src(ctx, instr->src[0]);
2345       Temp f16 = bld.vop1(aco_opcode::v_cvt_f16_f32, bld.def(v1), src);
2346       Temp f32, cmp_res;
2347
2348       if (ctx->program->chip_class >= GFX8) {
2349          Temp mask = bld.copy(bld.def(s1), Operand(0x36Fu)); /* value is NOT negative/positive denormal value */
2350          cmp_res = bld.vopc_e64(aco_opcode::v_cmp_class_f16, bld.hint_vcc(bld.def(bld.lm)), f16, mask);
2351          f32 = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), f16);
2352       } else {
2353          /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2354           * so compare the result and flush to 0 if it's smaller.
2355           */
2356          f32 = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), f16);
2357          Temp smallest = bld.copy(bld.def(s1), Operand(0x38800000u));
2358          Instruction* vop3 = bld.vopc_e64(aco_opcode::v_cmp_nlt_f32, bld.hint_vcc(bld.def(bld.lm)), f32, smallest);
2359          static_cast<VOP3A_instruction*>(vop3)->abs[0] = true;
2360          cmp_res = vop3->definitions[0].getTemp();
2361       }
2362
2363       if (ctx->block->fp_mode.preserve_signed_zero_inf_nan32 || ctx->program->chip_class < GFX8) {
2364          Temp copysign_0 = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0u), as_vgpr(ctx, src));
2365          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), copysign_0, f32, cmp_res);
2366       } else {
2367          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), f32, cmp_res);
2368       }
2369       break;
2370    }
2371    case nir_op_bfm: {
2372       Temp bits = get_alu_src(ctx, instr->src[0]);
2373       Temp offset = get_alu_src(ctx, instr->src[1]);
2374
2375       if (dst.regClass() == s1) {
2376          bld.sop2(aco_opcode::s_bfm_b32, Definition(dst), bits, offset);
2377       } else if (dst.regClass() == v1) {
2378          bld.vop3(aco_opcode::v_bfm_b32, Definition(dst), bits, offset);
2379       } else {
2380          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2381          nir_print_instr(&instr->instr, stderr);
2382          fprintf(stderr, "\n");
2383       }
2384       break;
2385    }
2386    case nir_op_bitfield_select: {
2387       /* (mask & insert) | (~mask & base) */
2388       Temp bitmask = get_alu_src(ctx, instr->src[0]);
2389       Temp insert = get_alu_src(ctx, instr->src[1]);
2390       Temp base = get_alu_src(ctx, instr->src[2]);
2391
2392       /* dst = (insert & bitmask) | (base & ~bitmask) */
2393       if (dst.regClass() == s1) {
2394          aco_ptr<Instruction> sop2;
2395          nir_const_value* const_bitmask = nir_src_as_const_value(instr->src[0].src);
2396          nir_const_value* const_insert = nir_src_as_const_value(instr->src[1].src);
2397          Operand lhs;
2398          if (const_insert && const_bitmask) {
2399             lhs = Operand(const_insert->u32 & const_bitmask->u32);
2400          } else {
2401             insert = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), insert, bitmask);
2402             lhs = Operand(insert);
2403          }
2404
2405          Operand rhs;
2406          nir_const_value* const_base = nir_src_as_const_value(instr->src[2].src);
2407          if (const_base && const_bitmask) {
2408             rhs = Operand(const_base->u32 & ~const_bitmask->u32);
2409          } else {
2410             base = bld.sop2(aco_opcode::s_andn2_b32, bld.def(s1), bld.def(s1, scc), base, bitmask);
2411             rhs = Operand(base);
2412          }
2413
2414          bld.sop2(aco_opcode::s_or_b32, Definition(dst), bld.def(s1, scc), rhs, lhs);
2415
2416       } else if (dst.regClass() == v1) {
2417          if (base.type() == RegType::sgpr && (bitmask.type() == RegType::sgpr || (insert.type() == RegType::sgpr)))
2418             base = as_vgpr(ctx, base);
2419          if (insert.type() == RegType::sgpr && bitmask.type() == RegType::sgpr)
2420             insert = as_vgpr(ctx, insert);
2421
2422          bld.vop3(aco_opcode::v_bfi_b32, Definition(dst), bitmask, insert, base);
2423
2424       } else {
2425          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2426          nir_print_instr(&instr->instr, stderr);
2427          fprintf(stderr, "\n");
2428       }
2429       break;
2430    }
2431    case nir_op_ubfe:
2432    case nir_op_ibfe: {
2433       Temp base = get_alu_src(ctx, instr->src[0]);
2434       Temp offset = get_alu_src(ctx, instr->src[1]);
2435       Temp bits = get_alu_src(ctx, instr->src[2]);
2436
2437       if (dst.type() == RegType::sgpr) {
2438          Operand extract;
2439          nir_const_value* const_offset = nir_src_as_const_value(instr->src[1].src);
2440          nir_const_value* const_bits = nir_src_as_const_value(instr->src[2].src);
2441          if (const_offset && const_bits) {
2442             uint32_t const_extract = (const_bits->u32 << 16) | const_offset->u32;
2443             extract = Operand(const_extract);
2444          } else {
2445             Operand width;
2446             if (const_bits) {
2447                width = Operand(const_bits->u32 << 16);
2448             } else {
2449                width = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), bits, Operand(16u));
2450             }
2451             extract = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), offset, width);
2452          }
2453
2454          aco_opcode opcode;
2455          if (dst.regClass() == s1) {
2456             if (instr->op == nir_op_ubfe)
2457                opcode = aco_opcode::s_bfe_u32;
2458             else
2459                opcode = aco_opcode::s_bfe_i32;
2460          } else if (dst.regClass() == s2) {
2461             if (instr->op == nir_op_ubfe)
2462                opcode = aco_opcode::s_bfe_u64;
2463             else
2464                opcode = aco_opcode::s_bfe_i64;
2465          } else {
2466             unreachable("Unsupported BFE bit size");
2467          }
2468
2469          bld.sop2(opcode, Definition(dst), bld.def(s1, scc), base, extract);
2470
2471       } else {
2472          aco_opcode opcode;
2473          if (dst.regClass() == v1) {
2474             if (instr->op == nir_op_ubfe)
2475                opcode = aco_opcode::v_bfe_u32;
2476             else
2477                opcode = aco_opcode::v_bfe_i32;
2478          } else {
2479             unreachable("Unsupported BFE bit size");
2480          }
2481
2482          emit_vop3a_instruction(ctx, instr, opcode, dst);
2483       }
2484       break;
2485    }
2486    case nir_op_bit_count: {
2487       Temp src = get_alu_src(ctx, instr->src[0]);
2488       if (src.regClass() == s1) {
2489          bld.sop1(aco_opcode::s_bcnt1_i32_b32, Definition(dst), bld.def(s1, scc), src);
2490       } else if (src.regClass() == v1) {
2491          bld.vop3(aco_opcode::v_bcnt_u32_b32, Definition(dst), src, Operand(0u));
2492       } else if (src.regClass() == v2) {
2493          bld.vop3(aco_opcode::v_bcnt_u32_b32, Definition(dst),
2494                   emit_extract_vector(ctx, src, 1, v1),
2495                   bld.vop3(aco_opcode::v_bcnt_u32_b32, bld.def(v1),
2496                            emit_extract_vector(ctx, src, 0, v1), Operand(0u)));
2497       } else if (src.regClass() == s2) {
2498          bld.sop1(aco_opcode::s_bcnt1_i32_b64, Definition(dst), bld.def(s1, scc), src);
2499       } else {
2500          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2501          nir_print_instr(&instr->instr, stderr);
2502          fprintf(stderr, "\n");
2503       }
2504       break;
2505    }
2506    case nir_op_flt: {
2507       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_f32, aco_opcode::v_cmp_lt_f64);
2508       break;
2509    }
2510    case nir_op_fge: {
2511       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_f32, aco_opcode::v_cmp_ge_f64);
2512       break;
2513    }
2514    case nir_op_feq: {
2515       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_eq_f32, aco_opcode::v_cmp_eq_f64);
2516       break;
2517    }
2518    case nir_op_fne: {
2519       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_neq_f32, aco_opcode::v_cmp_neq_f64);
2520       break;
2521    }
2522    case nir_op_ilt: {
2523       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_i32, aco_opcode::v_cmp_lt_i64, aco_opcode::s_cmp_lt_i32);
2524       break;
2525    }
2526    case nir_op_ige: {
2527       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_i32, aco_opcode::v_cmp_ge_i64, aco_opcode::s_cmp_ge_i32);
2528       break;
2529    }
2530    case nir_op_ieq: {
2531       if (instr->src[0].src.ssa->bit_size == 1)
2532          emit_boolean_logic(ctx, instr, Builder::s_xnor, dst);
2533       else
2534          emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_eq_i32, aco_opcode::v_cmp_eq_i64, aco_opcode::s_cmp_eq_i32,
2535                          ctx->program->chip_class >= GFX8 ? aco_opcode::s_cmp_eq_u64 : aco_opcode::num_opcodes);
2536       break;
2537    }
2538    case nir_op_ine: {
2539       if (instr->src[0].src.ssa->bit_size == 1)
2540          emit_boolean_logic(ctx, instr, Builder::s_xor, dst);
2541       else
2542          emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lg_i32, aco_opcode::v_cmp_lg_i64, aco_opcode::s_cmp_lg_i32,
2543                          ctx->program->chip_class >= GFX8 ? aco_opcode::s_cmp_lg_u64 : aco_opcode::num_opcodes);
2544       break;
2545    }
2546    case nir_op_ult: {
2547       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_u32, aco_opcode::v_cmp_lt_u64, aco_opcode::s_cmp_lt_u32);
2548       break;
2549    }
2550    case nir_op_uge: {
2551       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_u32, aco_opcode::v_cmp_ge_u64, aco_opcode::s_cmp_ge_u32);
2552       break;
2553    }
2554    case nir_op_fddx:
2555    case nir_op_fddy:
2556    case nir_op_fddx_fine:
2557    case nir_op_fddy_fine:
2558    case nir_op_fddx_coarse:
2559    case nir_op_fddy_coarse: {
2560       Temp src = get_alu_src(ctx, instr->src[0]);
2561       uint16_t dpp_ctrl1, dpp_ctrl2;
2562       if (instr->op == nir_op_fddx_fine) {
2563          dpp_ctrl1 = dpp_quad_perm(0, 0, 2, 2);
2564          dpp_ctrl2 = dpp_quad_perm(1, 1, 3, 3);
2565       } else if (instr->op == nir_op_fddy_fine) {
2566          dpp_ctrl1 = dpp_quad_perm(0, 1, 0, 1);
2567          dpp_ctrl2 = dpp_quad_perm(2, 3, 2, 3);
2568       } else {
2569          dpp_ctrl1 = dpp_quad_perm(0, 0, 0, 0);
2570          if (instr->op == nir_op_fddx || instr->op == nir_op_fddx_coarse)
2571             dpp_ctrl2 = dpp_quad_perm(1, 1, 1, 1);
2572          else
2573             dpp_ctrl2 = dpp_quad_perm(2, 2, 2, 2);
2574       }
2575
2576       Temp tmp;
2577       if (ctx->program->chip_class >= GFX8) {
2578          Temp tl = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl1);
2579          tmp = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), src, tl, dpp_ctrl2);
2580       } else {
2581          Temp tl = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl1);
2582          Temp tr = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl2);
2583          tmp = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), tr, tl);
2584       }
2585       emit_wqm(ctx, tmp, dst, true);
2586       break;
2587    }
2588    default:
2589       fprintf(stderr, "Unknown NIR ALU instr: ");
2590       nir_print_instr(&instr->instr, stderr);
2591       fprintf(stderr, "\n");
2592    }
2593 }
2594
2595 void visit_load_const(isel_context *ctx, nir_load_const_instr *instr)
2596 {
2597    Temp dst = get_ssa_temp(ctx, &instr->def);
2598
2599    // TODO: we really want to have the resulting type as this would allow for 64bit literals
2600    // which get truncated the lsb if double and msb if int
2601    // for now, we only use s_mov_b64 with 64bit inline constants
2602    assert(instr->def.num_components == 1 && "Vector load_const should be lowered to scalar.");
2603    assert(dst.type() == RegType::sgpr);
2604
2605    Builder bld(ctx->program, ctx->block);
2606
2607    if (instr->def.bit_size == 1) {
2608       assert(dst.regClass() == bld.lm);
2609       int val = instr->value[0].b ? -1 : 0;
2610       Operand op = bld.lm.size() == 1 ? Operand((uint32_t) val) : Operand((uint64_t) val);
2611       bld.sop1(Builder::s_mov, Definition(dst), op);
2612    } else if (dst.size() == 1) {
2613       bld.copy(Definition(dst), Operand(instr->value[0].u32));
2614    } else {
2615       assert(dst.size() != 1);
2616       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
2617       if (instr->def.bit_size == 64)
2618          for (unsigned i = 0; i < dst.size(); i++)
2619             vec->operands[i] = Operand{(uint32_t)(instr->value[0].u64 >> i * 32)};
2620       else {
2621          for (unsigned i = 0; i < dst.size(); i++)
2622             vec->operands[i] = Operand{instr->value[i].u32};
2623       }
2624       vec->definitions[0] = Definition(dst);
2625       ctx->block->instructions.emplace_back(std::move(vec));
2626    }
2627 }
2628
2629 uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2630 {
2631    uint32_t new_mask = 0;
2632    for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2633       if (mask & (1u << i))
2634          new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2635    return new_mask;
2636 }
2637
2638 Operand load_lds_size_m0(isel_context *ctx)
2639 {
2640    /* TODO: m0 does not need to be initialized on GFX9+ */
2641    Builder bld(ctx->program, ctx->block);
2642    return bld.m0((Temp)bld.sopk(aco_opcode::s_movk_i32, bld.def(s1, m0), 0xffff));
2643 }
2644
2645 void load_lds(isel_context *ctx, unsigned elem_size_bytes, Temp dst,
2646               Temp address, unsigned base_offset, unsigned align)
2647 {
2648    assert(util_is_power_of_two_nonzero(align) && align >= 4);
2649
2650    Builder bld(ctx->program, ctx->block);
2651
2652    Operand m = load_lds_size_m0(ctx);
2653
2654    unsigned num_components = dst.size() * 4u / elem_size_bytes;
2655    unsigned bytes_read = 0;
2656    unsigned result_size = 0;
2657    unsigned total_bytes = num_components * elem_size_bytes;
2658    std::array<Temp, NIR_MAX_VEC_COMPONENTS> result;
2659    bool large_ds_read = ctx->options->chip_class >= GFX7;
2660    bool usable_read2 = ctx->options->chip_class >= GFX7;
2661
2662    while (bytes_read < total_bytes) {
2663       unsigned todo = total_bytes - bytes_read;
2664       bool aligned8 = bytes_read % 8 == 0 && align % 8 == 0;
2665       bool aligned16 = bytes_read % 16 == 0 && align % 16 == 0;
2666
2667       aco_opcode op = aco_opcode::last_opcode;
2668       bool read2 = false;
2669       if (todo >= 16 && aligned16 && large_ds_read) {
2670          op = aco_opcode::ds_read_b128;
2671          todo = 16;
2672       } else if (todo >= 16 && aligned8 && usable_read2) {
2673          op = aco_opcode::ds_read2_b64;
2674          read2 = true;
2675          todo = 16;
2676       } else if (todo >= 12 && aligned16 && large_ds_read) {
2677          op = aco_opcode::ds_read_b96;
2678          todo = 12;
2679       } else if (todo >= 8 && aligned8) {
2680          op = aco_opcode::ds_read_b64;
2681          todo = 8;
2682       } else if (todo >= 8 && usable_read2) {
2683          op = aco_opcode::ds_read2_b32;
2684          read2 = true;
2685          todo = 8;
2686       } else if (todo >= 4) {
2687          op = aco_opcode::ds_read_b32;
2688          todo = 4;
2689       } else {
2690          assert(false);
2691       }
2692       assert(todo % elem_size_bytes == 0);
2693       unsigned num_elements = todo / elem_size_bytes;
2694       unsigned offset = base_offset + bytes_read;
2695       unsigned max_offset = read2 ? 1019 : 65535;
2696
2697       Temp address_offset = address;
2698       if (offset > max_offset) {
2699          address_offset = bld.vadd32(bld.def(v1), Operand(base_offset), address_offset);
2700          offset = bytes_read;
2701       }
2702       assert(offset <= max_offset); /* bytes_read shouldn't be large enough for this to happen */
2703
2704       Temp res;
2705       if (num_components == 1 && dst.type() == RegType::vgpr)
2706          res = dst;
2707       else
2708          res = bld.tmp(RegClass(RegType::vgpr, todo / 4));
2709
2710       if (read2)
2711          res = bld.ds(op, Definition(res), address_offset, m, offset >> 2, (offset >> 2) + 1);
2712       else
2713          res = bld.ds(op, Definition(res), address_offset, m, offset);
2714
2715       if (num_components == 1) {
2716          assert(todo == total_bytes);
2717          if (dst.type() == RegType::sgpr)
2718             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), res);
2719          return;
2720       }
2721
2722       if (dst.type() == RegType::sgpr) {
2723          Temp new_res = bld.tmp(RegType::sgpr, res.size());
2724          expand_vector(ctx, res, new_res, res.size(), (1 << res.size()) - 1);
2725          res = new_res;
2726       }
2727
2728       if (num_elements == 1) {
2729          result[result_size++] = res;
2730       } else {
2731          assert(res != dst && res.size() % num_elements == 0);
2732          aco_ptr<Pseudo_instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector, Format::PSEUDO, 1, num_elements)};
2733          split->operands[0] = Operand(res);
2734          for (unsigned i = 0; i < num_elements; i++)
2735             split->definitions[i] = Definition(result[result_size++] = bld.tmp(res.type(), elem_size_bytes / 4));
2736          ctx->block->instructions.emplace_back(std::move(split));
2737       }
2738
2739       bytes_read += todo;
2740    }
2741
2742    assert(result_size == num_components && result_size > 1);
2743    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, result_size, 1)};
2744    for (unsigned i = 0; i < result_size; i++)
2745       vec->operands[i] = Operand(result[i]);
2746    vec->definitions[0] = Definition(dst);
2747    ctx->block->instructions.emplace_back(std::move(vec));
2748    ctx->allocated_vec.emplace(dst.id(), result);
2749 }
2750
2751 Temp extract_subvector(isel_context *ctx, Temp data, unsigned start, unsigned size, RegType type)
2752 {
2753    if (start == 0 && size == data.size())
2754       return type == RegType::vgpr ? as_vgpr(ctx, data) : data;
2755
2756    unsigned size_hint = 1;
2757    auto it = ctx->allocated_vec.find(data.id());
2758    if (it != ctx->allocated_vec.end())
2759       size_hint = it->second[0].size();
2760    if (size % size_hint || start % size_hint)
2761       size_hint = 1;
2762
2763    start /= size_hint;
2764    size /= size_hint;
2765
2766    Temp elems[size];
2767    for (unsigned i = 0; i < size; i++)
2768       elems[i] = emit_extract_vector(ctx, data, start + i, RegClass(type, size_hint));
2769
2770    if (size == 1)
2771       return type == RegType::vgpr ? as_vgpr(ctx, elems[0]) : elems[0];
2772
2773    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, size, 1)};
2774    for (unsigned i = 0; i < size; i++)
2775       vec->operands[i] = Operand(elems[i]);
2776    Temp res = {ctx->program->allocateId(), RegClass(type, size * size_hint)};
2777    vec->definitions[0] = Definition(res);
2778    ctx->block->instructions.emplace_back(std::move(vec));
2779    return res;
2780 }
2781
2782 void ds_write_helper(isel_context *ctx, Operand m, Temp address, Temp data, unsigned data_start, unsigned total_size, unsigned offset0, unsigned offset1, unsigned align)
2783 {
2784    Builder bld(ctx->program, ctx->block);
2785    unsigned bytes_written = 0;
2786    bool large_ds_write = ctx->options->chip_class >= GFX7;
2787    bool usable_write2 = ctx->options->chip_class >= GFX7;
2788
2789    while (bytes_written < total_size * 4) {
2790       unsigned todo = total_size * 4 - bytes_written;
2791       bool aligned8 = bytes_written % 8 == 0 && align % 8 == 0;
2792       bool aligned16 = bytes_written % 16 == 0 && align % 16 == 0;
2793
2794       aco_opcode op = aco_opcode::last_opcode;
2795       bool write2 = false;
2796       unsigned size = 0;
2797       if (todo >= 16 && aligned16 && large_ds_write) {
2798          op = aco_opcode::ds_write_b128;
2799          size = 4;
2800       } else if (todo >= 16 && aligned8 && usable_write2) {
2801          op = aco_opcode::ds_write2_b64;
2802          write2 = true;
2803          size = 4;
2804       } else if (todo >= 12 && aligned16 && large_ds_write) {
2805          op = aco_opcode::ds_write_b96;
2806          size = 3;
2807       } else if (todo >= 8 && aligned8) {
2808          op = aco_opcode::ds_write_b64;
2809          size = 2;
2810       } else if (todo >= 8 && usable_write2) {
2811          op = aco_opcode::ds_write2_b32;
2812          write2 = true;
2813          size = 2;
2814       } else if (todo >= 4) {
2815          op = aco_opcode::ds_write_b32;
2816          size = 1;
2817       } else {
2818          assert(false);
2819       }
2820
2821       unsigned offset = offset0 + offset1 + bytes_written;
2822       unsigned max_offset = write2 ? 1020 : 65535;
2823       Temp address_offset = address;
2824       if (offset > max_offset) {
2825          address_offset = bld.vadd32(bld.def(v1), Operand(offset0), address_offset);
2826          offset = offset1 + bytes_written;
2827       }
2828       assert(offset <= max_offset); /* offset1 shouldn't be large enough for this to happen */
2829
2830       if (write2) {
2831          Temp val0 = extract_subvector(ctx, data, data_start + (bytes_written >> 2), size / 2, RegType::vgpr);
2832          Temp val1 = extract_subvector(ctx, data, data_start + (bytes_written >> 2) + 1, size / 2, RegType::vgpr);
2833          bld.ds(op, address_offset, val0, val1, m, offset >> 2, (offset >> 2) + 1);
2834       } else {
2835          Temp val = extract_subvector(ctx, data, data_start + (bytes_written >> 2), size, RegType::vgpr);
2836          bld.ds(op, address_offset, val, m, offset);
2837       }
2838
2839       bytes_written += size * 4;
2840    }
2841 }
2842
2843 void store_lds(isel_context *ctx, unsigned elem_size_bytes, Temp data, uint32_t wrmask,
2844                Temp address, unsigned base_offset, unsigned align)
2845 {
2846    assert(util_is_power_of_two_nonzero(align) && align >= 4);
2847
2848    Operand m = load_lds_size_m0(ctx);
2849
2850    /* we need at most two stores for 32bit variables */
2851    int start[2], count[2];
2852    u_bit_scan_consecutive_range(&wrmask, &start[0], &count[0]);
2853    u_bit_scan_consecutive_range(&wrmask, &start[1], &count[1]);
2854    assert(wrmask == 0);
2855
2856    /* one combined store is sufficient */
2857    if (count[0] == count[1]) {
2858       Builder bld(ctx->program, ctx->block);
2859
2860       Temp address_offset = address;
2861       if ((base_offset >> 2) + start[1] > 255) {
2862          address_offset = bld.vadd32(bld.def(v1), Operand(base_offset), address_offset);
2863          base_offset = 0;
2864       }
2865
2866       assert(count[0] == 1);
2867       Temp val0 = emit_extract_vector(ctx, data, start[0], v1);
2868       Temp val1 = emit_extract_vector(ctx, data, start[1], v1);
2869       aco_opcode op = elem_size_bytes == 4 ? aco_opcode::ds_write2_b32 : aco_opcode::ds_write2_b64;
2870       base_offset = base_offset / elem_size_bytes;
2871       bld.ds(op, address_offset, val0, val1, m,
2872              base_offset + start[0], base_offset + start[1]);
2873       return;
2874    }
2875
2876    for (unsigned i = 0; i < 2; i++) {
2877       if (count[i] == 0)
2878          continue;
2879
2880       unsigned elem_size_words = elem_size_bytes / 4;
2881       ds_write_helper(ctx, m, address, data, start[i] * elem_size_words, count[i] * elem_size_words,
2882                       base_offset, start[i] * elem_size_bytes, align);
2883    }
2884    return;
2885 }
2886
2887 void visit_store_vsgs_output(isel_context *ctx, nir_intrinsic_instr *instr)
2888 {
2889    unsigned write_mask = nir_intrinsic_write_mask(instr);
2890    unsigned component = nir_intrinsic_component(instr);
2891    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
2892    unsigned idx = (nir_intrinsic_base(instr) + component) * 4u;
2893    Operand offset(s1);
2894    Builder bld(ctx->program, ctx->block);
2895
2896    nir_instr *off_instr = instr->src[1].ssa->parent_instr;
2897    if (off_instr->type != nir_instr_type_load_const)
2898       offset = bld.v_mul24_imm(bld.def(v1), get_ssa_temp(ctx, instr->src[1].ssa), 16u);
2899    else
2900       idx += nir_instr_as_load_const(off_instr)->value[0].u32 * 16u;
2901
2902    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8u;
2903    if (ctx->stage == vertex_es) {
2904       Temp esgs_ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_ESGS_VS * 16u));
2905
2906       Temp elems[NIR_MAX_VEC_COMPONENTS * 2];
2907       if (elem_size_bytes == 8) {
2908          for (unsigned i = 0; i < src.size() / 2; i++) {
2909             Temp elem = emit_extract_vector(ctx, src, i, v2);
2910             elems[i*2] = bld.tmp(v1);
2911             elems[i*2+1] = bld.tmp(v1);
2912             bld.pseudo(aco_opcode::p_split_vector, Definition(elems[i*2]), Definition(elems[i*2+1]), elem);
2913          }
2914          write_mask = widen_mask(write_mask, 2);
2915          elem_size_bytes /= 2u;
2916       } else {
2917          for (unsigned i = 0; i < src.size(); i++)
2918             elems[i] = emit_extract_vector(ctx, src, i, v1);
2919       }
2920
2921       while (write_mask) {
2922          unsigned index = u_bit_scan(&write_mask);
2923          unsigned offset = index * elem_size_bytes;
2924          Temp elem = emit_extract_vector(ctx, src, index, RegClass(RegType::vgpr, elem_size_bytes / 4));
2925
2926          Operand vaddr_offset(v1);
2927          unsigned const_offset = idx + offset;
2928          if (const_offset >= 4096u) {
2929             vaddr_offset = bld.copy(bld.def(v1), Operand(const_offset / 4096u * 4096u));
2930             const_offset %= 4096u;
2931          }
2932
2933          aco_ptr<MTBUF_instruction> mtbuf{create_instruction<MTBUF_instruction>(aco_opcode::tbuffer_store_format_x, Format::MTBUF, 4, 0)};
2934          mtbuf->operands[0] = Operand(esgs_ring);
2935          mtbuf->operands[1] = vaddr_offset;
2936          mtbuf->operands[2] = Operand(get_arg(ctx, ctx->args->es2gs_offset));
2937          mtbuf->operands[3] = Operand(elem);
2938          mtbuf->offen = !vaddr_offset.isUndefined();
2939          mtbuf->dfmt = V_008F0C_BUF_DATA_FORMAT_32;
2940          mtbuf->nfmt = V_008F0C_BUF_NUM_FORMAT_UINT;
2941          mtbuf->offset = const_offset;
2942          mtbuf->glc = true;
2943          mtbuf->slc = true;
2944          mtbuf->barrier = barrier_none;
2945          mtbuf->can_reorder = true;
2946          bld.insert(std::move(mtbuf));
2947       }
2948    } else {
2949       unsigned itemsize = ctx->program->info->vs.es_info.esgs_itemsize;
2950
2951       Temp vertex_idx = emit_mbcnt(ctx, bld.def(v1));
2952       Temp wave_idx = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), get_arg(ctx, ctx->args->merged_wave_info), Operand(4u << 16 | 24));
2953       vertex_idx = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), vertex_idx,
2954                             bld.v_mul24_imm(bld.def(v1), as_vgpr(ctx, wave_idx), ctx->program->wave_size));
2955
2956       Temp lds_base = bld.v_mul24_imm(bld.def(v1), vertex_idx, itemsize);
2957       if (!offset.isUndefined())
2958          lds_base = bld.vadd32(bld.def(v1), offset, lds_base);
2959
2960       unsigned align = 1 << (ffs(itemsize) - 1);
2961       if (idx)
2962          align = std::min(align, 1u << (ffs(idx) - 1));
2963
2964       store_lds(ctx, elem_size_bytes, src, write_mask, lds_base, idx, align);
2965    }
2966 }
2967
2968 void visit_store_output(isel_context *ctx, nir_intrinsic_instr *instr)
2969 {
2970    if (ctx->stage == vertex_vs ||
2971        ctx->stage == fragment_fs ||
2972        ctx->shader->info.stage == MESA_SHADER_GEOMETRY) {
2973       unsigned write_mask = nir_intrinsic_write_mask(instr);
2974       unsigned component = nir_intrinsic_component(instr);
2975       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
2976       unsigned idx = nir_intrinsic_base(instr) + component;
2977
2978       nir_instr *off_instr = instr->src[1].ssa->parent_instr;
2979       if (off_instr->type != nir_instr_type_load_const) {
2980          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
2981          nir_print_instr(off_instr, stderr);
2982          fprintf(stderr, "\n");
2983       }
2984       idx += nir_instr_as_load_const(off_instr)->value[0].u32 * 4u;
2985
2986       if (instr->src[0].ssa->bit_size == 64)
2987          write_mask = widen_mask(write_mask, 2);
2988
2989       for (unsigned i = 0; i < 8; ++i) {
2990          if (write_mask & (1 << i)) {
2991             ctx->outputs.mask[idx / 4u] |= 1 << (idx % 4u);
2992             ctx->outputs.outputs[idx / 4u][idx % 4u] = emit_extract_vector(ctx, src, i, v1);
2993          }
2994          idx++;
2995       }
2996    } else if (ctx->stage == vertex_es ||
2997               (ctx->stage == vertex_geometry_gs && ctx->shader->info.stage == MESA_SHADER_VERTEX)) {
2998       visit_store_vsgs_output(ctx, instr);
2999    } else {
3000       unreachable("Shader stage not implemented");
3001    }
3002 }
3003
3004 void emit_interp_instr(isel_context *ctx, unsigned idx, unsigned component, Temp src, Temp dst, Temp prim_mask)
3005 {
3006    Temp coord1 = emit_extract_vector(ctx, src, 0, v1);
3007    Temp coord2 = emit_extract_vector(ctx, src, 1, v1);
3008
3009    Builder bld(ctx->program, ctx->block);
3010    Temp tmp = bld.vintrp(aco_opcode::v_interp_p1_f32, bld.def(v1), coord1, bld.m0(prim_mask), idx, component);
3011    bld.vintrp(aco_opcode::v_interp_p2_f32, Definition(dst), coord2, bld.m0(prim_mask), tmp, idx, component);
3012 }
3013
3014 void emit_load_frag_coord(isel_context *ctx, Temp dst, unsigned num_components)
3015 {
3016    aco_ptr<Pseudo_instruction> vec(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1));
3017    for (unsigned i = 0; i < num_components; i++)
3018       vec->operands[i] = Operand(get_arg(ctx, ctx->args->ac.frag_pos[i]));
3019    if (G_0286CC_POS_W_FLOAT_ENA(ctx->program->config->spi_ps_input_ena)) {
3020       assert(num_components == 4);
3021       Builder bld(ctx->program, ctx->block);
3022       vec->operands[3] = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), get_arg(ctx, ctx->args->ac.frag_pos[3]));
3023    }
3024
3025    for (Operand& op : vec->operands)
3026       op = op.isUndefined() ? Operand(0u) : op;
3027
3028    vec->definitions[0] = Definition(dst);
3029    ctx->block->instructions.emplace_back(std::move(vec));
3030    emit_split_vector(ctx, dst, num_components);
3031    return;
3032 }
3033
3034 void visit_load_interpolated_input(isel_context *ctx, nir_intrinsic_instr *instr)
3035 {
3036    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3037    Temp coords = get_ssa_temp(ctx, instr->src[0].ssa);
3038    unsigned idx = nir_intrinsic_base(instr);
3039    unsigned component = nir_intrinsic_component(instr);
3040    Temp prim_mask = get_arg(ctx, ctx->args->ac.prim_mask);
3041
3042    nir_const_value* offset = nir_src_as_const_value(instr->src[1]);
3043    if (offset) {
3044       assert(offset->u32 == 0);
3045    } else {
3046       /* the lower 15bit of the prim_mask contain the offset into LDS
3047        * while the upper bits contain the number of prims */
3048       Temp offset_src = get_ssa_temp(ctx, instr->src[1].ssa);
3049       assert(offset_src.regClass() == s1 && "TODO: divergent offsets...");
3050       Builder bld(ctx->program, ctx->block);
3051       Temp stride = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), prim_mask, Operand(16u));
3052       stride = bld.sop1(aco_opcode::s_bcnt1_i32_b32, bld.def(s1), bld.def(s1, scc), stride);
3053       stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, Operand(48u));
3054       offset_src = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, offset_src);
3055       prim_mask = bld.sop2(aco_opcode::s_add_i32, bld.def(s1, m0), bld.def(s1, scc), offset_src, prim_mask);
3056    }
3057
3058    if (instr->dest.ssa.num_components == 1) {
3059       emit_interp_instr(ctx, idx, component, coords, dst, prim_mask);
3060    } else {
3061       aco_ptr<Pseudo_instruction> vec(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.ssa.num_components, 1));
3062       for (unsigned i = 0; i < instr->dest.ssa.num_components; i++)
3063       {
3064          Temp tmp = {ctx->program->allocateId(), v1};
3065          emit_interp_instr(ctx, idx, component+i, coords, tmp, prim_mask);
3066          vec->operands[i] = Operand(tmp);
3067       }
3068       vec->definitions[0] = Definition(dst);
3069       ctx->block->instructions.emplace_back(std::move(vec));
3070    }
3071 }
3072
3073 bool check_vertex_fetch_size(isel_context *ctx, const ac_data_format_info *vtx_info,
3074                              unsigned offset, unsigned stride, unsigned channels)
3075 {
3076    unsigned vertex_byte_size = vtx_info->chan_byte_size * channels;
3077    if (vtx_info->chan_byte_size != 4 && channels == 3)
3078       return false;
3079    return (ctx->options->chip_class != GFX6 && ctx->options->chip_class != GFX10) ||
3080           (offset % vertex_byte_size == 0 && stride % vertex_byte_size == 0);
3081 }
3082
3083 uint8_t get_fetch_data_format(isel_context *ctx, const ac_data_format_info *vtx_info,
3084                               unsigned offset, unsigned stride, unsigned *channels)
3085 {
3086    if (!vtx_info->chan_byte_size) {
3087       *channels = vtx_info->num_channels;
3088       return vtx_info->chan_format;
3089    }
3090
3091    unsigned num_channels = *channels;
3092    if (!check_vertex_fetch_size(ctx, vtx_info, offset, stride, *channels)) {
3093       unsigned new_channels = num_channels + 1;
3094       /* first, assume more loads is worse and try using a larger data format */
3095       while (new_channels <= 4 && !check_vertex_fetch_size(ctx, vtx_info, offset, stride, new_channels)) {
3096          new_channels++;
3097          /* don't make the attribute potentially out-of-bounds */
3098          if (offset + new_channels * vtx_info->chan_byte_size > stride)
3099             new_channels = 5;
3100       }
3101
3102       if (new_channels == 5) {
3103          /* then try decreasing load size (at the cost of more loads) */
3104          new_channels = *channels;
3105          while (new_channels > 1 && !check_vertex_fetch_size(ctx, vtx_info, offset, stride, new_channels))
3106             new_channels--;
3107       }
3108
3109       if (new_channels < *channels)
3110          *channels = new_channels;
3111       num_channels = new_channels;
3112    }
3113
3114    switch (vtx_info->chan_format) {
3115    case V_008F0C_BUF_DATA_FORMAT_8:
3116       return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8, V_008F0C_BUF_DATA_FORMAT_8_8,
3117                          V_008F0C_BUF_DATA_FORMAT_INVALID, V_008F0C_BUF_DATA_FORMAT_8_8_8_8}[num_channels - 1];
3118    case V_008F0C_BUF_DATA_FORMAT_16:
3119       return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16, V_008F0C_BUF_DATA_FORMAT_16_16,
3120                          V_008F0C_BUF_DATA_FORMAT_INVALID, V_008F0C_BUF_DATA_FORMAT_16_16_16_16}[num_channels - 1];
3121    case V_008F0C_BUF_DATA_FORMAT_32:
3122       return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32, V_008F0C_BUF_DATA_FORMAT_32_32,
3123                          V_008F0C_BUF_DATA_FORMAT_32_32_32, V_008F0C_BUF_DATA_FORMAT_32_32_32_32}[num_channels - 1];
3124    }
3125    unreachable("shouldn't reach here");
3126    return V_008F0C_BUF_DATA_FORMAT_INVALID;
3127 }
3128
3129 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
3130  * so we may need to fix it up. */
3131 Temp adjust_vertex_fetch_alpha(isel_context *ctx, unsigned adjustment, Temp alpha)
3132 {
3133    Builder bld(ctx->program, ctx->block);
3134
3135    if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
3136       alpha = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), alpha);
3137
3138    /* For the integer-like cases, do a natural sign extension.
3139     *
3140     * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
3141     * and happen to contain 0, 1, 2, 3 as the two LSBs of the
3142     * exponent.
3143     */
3144    alpha = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(adjustment == RADV_ALPHA_ADJUST_SNORM ? 7u : 30u), alpha);
3145    alpha = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(30u), alpha);
3146
3147    /* Convert back to the right type. */
3148    if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
3149       alpha = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), alpha);
3150       Temp clamp = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0xbf800000u), alpha);
3151       alpha = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xbf800000u), alpha, clamp);
3152    } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
3153       alpha = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), alpha);
3154    }
3155
3156    return alpha;
3157 }
3158
3159 void visit_load_input(isel_context *ctx, nir_intrinsic_instr *instr)
3160 {
3161    Builder bld(ctx->program, ctx->block);
3162    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3163    if (ctx->shader->info.stage == MESA_SHADER_VERTEX) {
3164
3165       nir_instr *off_instr = instr->src[0].ssa->parent_instr;
3166       if (off_instr->type != nir_instr_type_load_const) {
3167          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
3168          nir_print_instr(off_instr, stderr);
3169          fprintf(stderr, "\n");
3170       }
3171       uint32_t offset = nir_instr_as_load_const(off_instr)->value[0].u32;
3172
3173       Temp vertex_buffers = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->vertex_buffers));
3174
3175       unsigned location = nir_intrinsic_base(instr) / 4 - VERT_ATTRIB_GENERIC0 + offset;
3176       unsigned component = nir_intrinsic_component(instr);
3177       unsigned attrib_binding = ctx->options->key.vs.vertex_attribute_bindings[location];
3178       uint32_t attrib_offset = ctx->options->key.vs.vertex_attribute_offsets[location];
3179       uint32_t attrib_stride = ctx->options->key.vs.vertex_attribute_strides[location];
3180       unsigned attrib_format = ctx->options->key.vs.vertex_attribute_formats[location];
3181
3182       unsigned dfmt = attrib_format & 0xf;
3183       unsigned nfmt = (attrib_format >> 4) & 0x7;
3184       const struct ac_data_format_info *vtx_info = ac_get_data_format_info(dfmt);
3185
3186       unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa) << component;
3187       unsigned num_channels = MIN2(util_last_bit(mask), vtx_info->num_channels);
3188       unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> (location * 2)) & 3;
3189       bool post_shuffle = ctx->options->key.vs.post_shuffle & (1 << location);
3190       if (post_shuffle)
3191          num_channels = MAX2(num_channels, 3);
3192
3193       Operand off = bld.copy(bld.def(s1), Operand(attrib_binding * 16u));
3194       Temp list = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), vertex_buffers, off);
3195
3196       Temp index;
3197       if (ctx->options->key.vs.instance_rate_inputs & (1u << location)) {
3198          uint32_t divisor = ctx->options->key.vs.instance_rate_divisors[location];
3199          Temp start_instance = get_arg(ctx, ctx->args->ac.start_instance);
3200          if (divisor) {
3201             Temp instance_id = get_arg(ctx, ctx->args->ac.instance_id);
3202             if (divisor != 1) {
3203                Temp divided = bld.tmp(v1);
3204                emit_v_div_u32(ctx, divided, as_vgpr(ctx, instance_id), divisor);
3205                index = bld.vadd32(bld.def(v1), start_instance, divided);
3206             } else {
3207                index = bld.vadd32(bld.def(v1), start_instance, instance_id);
3208             }
3209          } else {
3210             index = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), start_instance);
3211          }
3212       } else {
3213          index = bld.vadd32(bld.def(v1),
3214                             get_arg(ctx, ctx->args->ac.base_vertex),
3215                             get_arg(ctx, ctx->args->ac.vertex_id));
3216       }
3217
3218       Temp channels[num_channels];
3219       unsigned channel_start = 0;
3220       bool direct_fetch = false;
3221
3222       /* skip unused channels at the start */
3223       if (vtx_info->chan_byte_size && !post_shuffle) {
3224          channel_start = ffs(mask) - 1;
3225          for (unsigned i = 0; i < channel_start; i++)
3226             channels[i] = Temp(0, s1);
3227       } else if (vtx_info->chan_byte_size && post_shuffle && !(mask & 0x8)) {
3228          num_channels = 3 - (ffs(mask) - 1);
3229       }
3230
3231       /* load channels */
3232       while (channel_start < num_channels) {
3233          unsigned fetch_size = num_channels - channel_start;
3234          unsigned fetch_offset = attrib_offset + channel_start * vtx_info->chan_byte_size;
3235          bool expanded = false;
3236
3237          /* use MUBUF when possible to avoid possible alignment issues */
3238          /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
3239          bool use_mubuf = (nfmt == V_008F0C_BUF_NUM_FORMAT_FLOAT ||
3240                            nfmt == V_008F0C_BUF_NUM_FORMAT_UINT ||
3241                            nfmt == V_008F0C_BUF_NUM_FORMAT_SINT) &&
3242                           vtx_info->chan_byte_size == 4;
3243          unsigned fetch_dfmt = V_008F0C_BUF_DATA_FORMAT_INVALID;
3244          if (!use_mubuf) {
3245             fetch_dfmt = get_fetch_data_format(ctx, vtx_info, fetch_offset, attrib_stride, &fetch_size);
3246          } else {
3247             if (fetch_size == 3 && ctx->options->chip_class == GFX6) {
3248                /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
3249                fetch_size = 4;
3250                expanded = true;
3251             }
3252          }
3253
3254          Temp fetch_index = index;
3255          if (attrib_stride != 0 && fetch_offset > attrib_stride) {
3256             fetch_index = bld.vadd32(bld.def(v1), Operand(fetch_offset / attrib_stride), fetch_index);
3257             fetch_offset = fetch_offset % attrib_stride;
3258          }
3259
3260          Operand soffset(0u);
3261          if (fetch_offset >= 4096) {
3262             soffset = bld.copy(bld.def(s1), Operand(fetch_offset / 4096 * 4096));
3263             fetch_offset %= 4096;
3264          }
3265
3266          aco_opcode opcode;
3267          switch (fetch_size) {
3268          case 1:
3269             opcode = use_mubuf ? aco_opcode::buffer_load_dword : aco_opcode::tbuffer_load_format_x;
3270             break;
3271          case 2:
3272             opcode = use_mubuf ? aco_opcode::buffer_load_dwordx2 : aco_opcode::tbuffer_load_format_xy;
3273             break;
3274          case 3:
3275             assert(ctx->options->chip_class >= GFX7 ||
3276                    (!use_mubuf && ctx->options->chip_class == GFX6));
3277             opcode = use_mubuf ? aco_opcode::buffer_load_dwordx3 : aco_opcode::tbuffer_load_format_xyz;
3278             break;
3279          case 4:
3280             opcode = use_mubuf ? aco_opcode::buffer_load_dwordx4 : aco_opcode::tbuffer_load_format_xyzw;
3281             break;
3282          default:
3283             unreachable("Unimplemented load_input vector size");
3284          }
3285
3286          Temp fetch_dst;
3287          if (channel_start == 0 && fetch_size == dst.size() && !post_shuffle &&
3288              !expanded && (alpha_adjust == RADV_ALPHA_ADJUST_NONE ||
3289                            num_channels <= 3)) {
3290             direct_fetch = true;
3291             fetch_dst = dst;
3292          } else {
3293             fetch_dst = bld.tmp(RegType::vgpr, fetch_size);
3294          }
3295
3296          if (use_mubuf) {
3297             Instruction *mubuf = bld.mubuf(opcode,
3298                                            Definition(fetch_dst), list, fetch_index, soffset,
3299                                            fetch_offset, false, true).instr;
3300             static_cast<MUBUF_instruction*>(mubuf)->can_reorder = true;
3301          } else {
3302             Instruction *mtbuf = bld.mtbuf(opcode,
3303                                            Definition(fetch_dst), list, fetch_index, soffset,
3304                                            fetch_dfmt, nfmt, fetch_offset, false, true).instr;
3305             static_cast<MTBUF_instruction*>(mtbuf)->can_reorder = true;
3306          }
3307
3308          emit_split_vector(ctx, fetch_dst, fetch_dst.size());
3309
3310          if (fetch_size == 1) {
3311             channels[channel_start] = fetch_dst;
3312          } else {
3313             for (unsigned i = 0; i < MIN2(fetch_size, num_channels - channel_start); i++)
3314                channels[channel_start + i] = emit_extract_vector(ctx, fetch_dst, i, v1);
3315          }
3316
3317          channel_start += fetch_size;
3318       }
3319
3320       if (!direct_fetch) {
3321          bool is_float = nfmt != V_008F0C_BUF_NUM_FORMAT_UINT &&
3322                          nfmt != V_008F0C_BUF_NUM_FORMAT_SINT;
3323
3324          static const unsigned swizzle_normal[4] = {0, 1, 2, 3};
3325          static const unsigned swizzle_post_shuffle[4] = {2, 1, 0, 3};
3326          const unsigned *swizzle = post_shuffle ? swizzle_post_shuffle : swizzle_normal;
3327
3328          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
3329          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
3330          unsigned num_temp = 0;
3331          for (unsigned i = 0; i < dst.size(); i++) {
3332             unsigned idx = i + component;
3333             if (swizzle[idx] < num_channels && channels[swizzle[idx]].id()) {
3334                Temp channel = channels[swizzle[idx]];
3335                if (idx == 3 && alpha_adjust != RADV_ALPHA_ADJUST_NONE)
3336                   channel = adjust_vertex_fetch_alpha(ctx, alpha_adjust, channel);
3337                vec->operands[i] = Operand(channel);
3338
3339                num_temp++;
3340                elems[i] = channel;
3341             } else if (is_float && idx == 3) {
3342                vec->operands[i] = Operand(0x3f800000u);
3343             } else if (!is_float && idx == 3) {
3344                vec->operands[i] = Operand(1u);
3345             } else {
3346                vec->operands[i] = Operand(0u);
3347             }
3348          }
3349          vec->definitions[0] = Definition(dst);
3350          ctx->block->instructions.emplace_back(std::move(vec));
3351          emit_split_vector(ctx, dst, dst.size());
3352
3353          if (num_temp == dst.size())
3354             ctx->allocated_vec.emplace(dst.id(), elems);
3355       }
3356    } else if (ctx->shader->info.stage == MESA_SHADER_FRAGMENT) {
3357       unsigned offset_idx = instr->intrinsic == nir_intrinsic_load_input ? 0 : 1;
3358       nir_instr *off_instr = instr->src[offset_idx].ssa->parent_instr;
3359       if (off_instr->type != nir_instr_type_load_const ||
3360           nir_instr_as_load_const(off_instr)->value[0].u32 != 0) {
3361          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
3362          nir_print_instr(off_instr, stderr);
3363          fprintf(stderr, "\n");
3364       }
3365
3366       Temp prim_mask = get_arg(ctx, ctx->args->ac.prim_mask);
3367       nir_const_value* offset = nir_src_as_const_value(instr->src[offset_idx]);
3368       if (offset) {
3369          assert(offset->u32 == 0);
3370       } else {
3371          /* the lower 15bit of the prim_mask contain the offset into LDS
3372           * while the upper bits contain the number of prims */
3373          Temp offset_src = get_ssa_temp(ctx, instr->src[offset_idx].ssa);
3374          assert(offset_src.regClass() == s1 && "TODO: divergent offsets...");
3375          Builder bld(ctx->program, ctx->block);
3376          Temp stride = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), prim_mask, Operand(16u));
3377          stride = bld.sop1(aco_opcode::s_bcnt1_i32_b32, bld.def(s1), bld.def(s1, scc), stride);
3378          stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, Operand(48u));
3379          offset_src = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, offset_src);
3380          prim_mask = bld.sop2(aco_opcode::s_add_i32, bld.def(s1, m0), bld.def(s1, scc), offset_src, prim_mask);
3381       }
3382
3383       unsigned idx = nir_intrinsic_base(instr);
3384       unsigned component = nir_intrinsic_component(instr);
3385       unsigned vertex_id = 2; /* P0 */
3386
3387       if (instr->intrinsic == nir_intrinsic_load_input_vertex) {
3388          nir_const_value* src0 = nir_src_as_const_value(instr->src[0]);
3389          switch (src0->u32) {
3390          case 0:
3391             vertex_id = 2; /* P0 */
3392             break;
3393          case 1:
3394             vertex_id = 0; /* P10 */
3395             break;
3396          case 2:
3397             vertex_id = 1; /* P20 */
3398             break;
3399          default:
3400             unreachable("invalid vertex index");
3401          }
3402       }
3403
3404       if (dst.size() == 1) {
3405          bld.vintrp(aco_opcode::v_interp_mov_f32, Definition(dst), Operand(vertex_id), bld.m0(prim_mask), idx, component);
3406       } else {
3407          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
3408          for (unsigned i = 0; i < dst.size(); i++)
3409             vec->operands[i] = bld.vintrp(aco_opcode::v_interp_mov_f32, bld.def(v1), Operand(vertex_id), bld.m0(prim_mask), idx, component + i);
3410          vec->definitions[0] = Definition(dst);
3411          bld.insert(std::move(vec));
3412       }
3413
3414    } else {
3415       unreachable("Shader stage not implemented");
3416    }
3417 }
3418
3419 void visit_load_per_vertex_input(isel_context *ctx, nir_intrinsic_instr *instr)
3420 {
3421    assert(ctx->stage == vertex_geometry_gs || ctx->stage == geometry_gs);
3422    assert(ctx->shader->info.stage == MESA_SHADER_GEOMETRY);
3423
3424    Builder bld(ctx->program, ctx->block);
3425    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3426
3427    Temp offset = Temp();
3428    if (instr->src[0].ssa->parent_instr->type != nir_instr_type_load_const) {
3429       /* better code could be created, but this case probably doesn't happen
3430        * much in practice */
3431       Temp indirect_vertex = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
3432       for (unsigned i = 0; i < ctx->shader->info.gs.vertices_in; i++) {
3433          Temp elem;
3434          if (ctx->stage == vertex_geometry_gs) {
3435             elem = get_arg(ctx, ctx->args->gs_vtx_offset[i / 2u * 2u]);
3436             if (i % 2u)
3437                elem = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(16u), elem);
3438          } else {
3439             elem = get_arg(ctx, ctx->args->gs_vtx_offset[i]);
3440          }
3441          if (offset.id()) {
3442             Temp cond = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.hint_vcc(bld.def(s2)),
3443                                  Operand(i), indirect_vertex);
3444             offset = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), offset, elem, cond);
3445          } else {
3446             offset = elem;
3447          }
3448       }
3449       if (ctx->stage == vertex_geometry_gs)
3450          offset = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0xffffu), offset);
3451    } else {
3452       unsigned vertex = nir_src_as_uint(instr->src[0]);
3453       if (ctx->stage == vertex_geometry_gs)
3454          offset = bld.vop3(
3455          aco_opcode::v_bfe_u32, bld.def(v1), get_arg(ctx, ctx->args->gs_vtx_offset[vertex / 2u * 2u]),
3456             Operand((vertex % 2u) * 16u), Operand(16u));
3457       else
3458          offset = get_arg(ctx, ctx->args->gs_vtx_offset[vertex]);
3459    }
3460
3461    unsigned const_offset = nir_intrinsic_base(instr);
3462    const_offset += nir_intrinsic_component(instr);
3463
3464    nir_instr *off_instr = instr->src[1].ssa->parent_instr;
3465    if (off_instr->type != nir_instr_type_load_const) {
3466       Temp indirect_offset = get_ssa_temp(ctx, instr->src[1].ssa);
3467       offset = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u),
3468                         bld.vadd32(bld.def(v1), indirect_offset, offset));
3469    } else {
3470       const_offset += nir_instr_as_load_const(off_instr)->value[0].u32 * 4u;
3471    }
3472    const_offset *= 4u;
3473
3474    offset = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), offset);
3475
3476    unsigned itemsize = ctx->program->info->vs.es_info.esgs_itemsize;
3477
3478    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
3479    if (ctx->stage == geometry_gs) {
3480       Temp esgs_ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_ESGS_GS * 16u));
3481
3482       const_offset *= ctx->program->wave_size;
3483
3484       std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
3485       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(
3486          aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.ssa.num_components, 1)};
3487       for (unsigned i = 0; i < instr->dest.ssa.num_components; i++) {
3488          Temp subelems[2];
3489          for (unsigned j = 0; j < elem_size_bytes / 4; j++) {
3490             Operand soffset(0u);
3491             if (const_offset >= 4096u)
3492                soffset = bld.copy(bld.def(s1), Operand(const_offset / 4096u * 4096u));
3493
3494             aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(aco_opcode::buffer_load_dword, Format::MUBUF, 3, 1)};
3495             mubuf->definitions[0] = bld.def(v1);
3496             subelems[j] = mubuf->definitions[0].getTemp();
3497             mubuf->operands[0] = Operand(esgs_ring);
3498             mubuf->operands[1] = Operand(offset);
3499             mubuf->operands[2] = Operand(soffset);
3500             mubuf->offen = true;
3501             mubuf->offset = const_offset % 4096u;
3502             mubuf->glc = true;
3503             mubuf->dlc = ctx->options->chip_class >= GFX10;
3504             mubuf->barrier = barrier_none;
3505             mubuf->can_reorder = true;
3506             bld.insert(std::move(mubuf));
3507
3508             const_offset += ctx->program->wave_size * 4u;
3509          }
3510
3511          if (elem_size_bytes == 4)
3512             elems[i] = subelems[0];
3513          else
3514             elems[i] = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), subelems[0], subelems[1]);
3515          vec->operands[i] = Operand(elems[i]);
3516       }
3517       vec->definitions[0] = Definition(dst);
3518       ctx->block->instructions.emplace_back(std::move(vec));
3519       ctx->allocated_vec.emplace(dst.id(), elems);
3520    } else {
3521       unsigned align = 16; /* alignment of indirect offset */
3522       align = std::min(align, 1u << (ffs(itemsize) - 1));
3523       if (const_offset)
3524          align = std::min(align, 1u << (ffs(const_offset) - 1));
3525
3526       load_lds(ctx, elem_size_bytes, dst, offset, const_offset, align);
3527    }
3528 }
3529
3530 void visit_load_tess_coord(isel_context *ctx, nir_intrinsic_instr *instr)
3531 {
3532    assert(ctx->shader->info.stage == MESA_SHADER_TESS_EVAL);
3533
3534    Builder bld(ctx->program, ctx->block);
3535    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3536
3537    Operand tes_u(get_arg(ctx, ctx->args->tes_u));
3538    Operand tes_v(get_arg(ctx, ctx->args->tes_v));
3539    Operand tes_w(0u);
3540
3541    if (ctx->shader->info.tess.primitive_mode == GL_TRIANGLES) {
3542       Temp tmp = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), tes_u, tes_v);
3543       tmp = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), Operand(0x3f800000u /* 1.0f */), tmp);
3544       tes_w = Operand(tmp);
3545    }
3546
3547    Temp tess_coord = bld.pseudo(aco_opcode::p_create_vector, Definition(dst), tes_u, tes_v, tes_w);
3548    emit_split_vector(ctx, tess_coord, 3);
3549 }
3550
3551 Temp load_desc_ptr(isel_context *ctx, unsigned desc_set)
3552 {
3553    if (ctx->program->info->need_indirect_descriptor_sets) {
3554       Builder bld(ctx->program, ctx->block);
3555       Temp ptr64 = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->descriptor_sets[0]));
3556       Operand off = bld.copy(bld.def(s1), Operand(desc_set << 2));
3557       return bld.smem(aco_opcode::s_load_dword, bld.def(s1), ptr64, off);//, false, false, false);
3558    }
3559
3560    return get_arg(ctx, ctx->args->descriptor_sets[desc_set]);
3561 }
3562
3563
3564 void visit_load_resource(isel_context *ctx, nir_intrinsic_instr *instr)
3565 {
3566    Builder bld(ctx->program, ctx->block);
3567    Temp index = get_ssa_temp(ctx, instr->src[0].ssa);
3568    if (!ctx->divergent_vals[instr->dest.ssa.index])
3569       index = bld.as_uniform(index);
3570    unsigned desc_set = nir_intrinsic_desc_set(instr);
3571    unsigned binding = nir_intrinsic_binding(instr);
3572
3573    Temp desc_ptr;
3574    radv_pipeline_layout *pipeline_layout = ctx->options->layout;
3575    radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
3576    unsigned offset = layout->binding[binding].offset;
3577    unsigned stride;
3578    if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
3579        layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
3580       unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start + layout->binding[binding].dynamic_offset_offset;
3581       desc_ptr = get_arg(ctx, ctx->args->ac.push_constants);
3582       offset = pipeline_layout->push_constant_size + 16 * idx;
3583       stride = 16;
3584    } else {
3585       desc_ptr = load_desc_ptr(ctx, desc_set);
3586       stride = layout->binding[binding].size;
3587    }
3588
3589    nir_const_value* nir_const_index = nir_src_as_const_value(instr->src[0]);
3590    unsigned const_index = nir_const_index ? nir_const_index->u32 : 0;
3591    if (stride != 1) {
3592       if (nir_const_index) {
3593          const_index = const_index * stride;
3594       } else if (index.type() == RegType::vgpr) {
3595          bool index24bit = layout->binding[binding].array_size <= 0x1000000;
3596          index = bld.v_mul_imm(bld.def(v1), index, stride, index24bit);
3597       } else {
3598          index = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), Operand(index));
3599       }
3600    }
3601    if (offset) {
3602       if (nir_const_index) {
3603          const_index = const_index + offset;
3604       } else if (index.type() == RegType::vgpr) {
3605          index = bld.vadd32(bld.def(v1), Operand(offset), index);
3606       } else {
3607          index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset), Operand(index));
3608       }
3609    }
3610
3611    if (nir_const_index && const_index == 0) {
3612       index = desc_ptr;
3613    } else if (index.type() == RegType::vgpr) {
3614       index = bld.vadd32(bld.def(v1),
3615                          nir_const_index ? Operand(const_index) : Operand(index),
3616                          Operand(desc_ptr));
3617    } else {
3618       index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
3619                        nir_const_index ? Operand(const_index) : Operand(index),
3620                        Operand(desc_ptr));
3621    }
3622
3623    bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), index);
3624 }
3625
3626 void load_buffer(isel_context *ctx, unsigned num_components, Temp dst,
3627                  Temp rsrc, Temp offset, bool glc=false, bool readonly=true)
3628 {
3629    Builder bld(ctx->program, ctx->block);
3630
3631    unsigned num_bytes = dst.size() * 4;
3632    bool dlc = glc && ctx->options->chip_class >= GFX10;
3633
3634    aco_opcode op;
3635    if (dst.type() == RegType::vgpr || (ctx->options->chip_class < GFX8 && !readonly)) {
3636       Operand vaddr = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
3637       Operand soffset = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
3638       unsigned const_offset = 0;
3639
3640       Temp lower = Temp();
3641       if (num_bytes > 16) {
3642          assert(num_components == 3 || num_components == 4);
3643          op = aco_opcode::buffer_load_dwordx4;
3644          lower = bld.tmp(v4);
3645          aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
3646          mubuf->definitions[0] = Definition(lower);
3647          mubuf->operands[0] = Operand(rsrc);
3648          mubuf->operands[1] = vaddr;
3649          mubuf->operands[2] = soffset;
3650          mubuf->offen = (offset.type() == RegType::vgpr);
3651          mubuf->glc = glc;
3652          mubuf->dlc = dlc;
3653          mubuf->barrier = readonly ? barrier_none : barrier_buffer;
3654          mubuf->can_reorder = readonly;
3655          bld.insert(std::move(mubuf));
3656          emit_split_vector(ctx, lower, 2);
3657          num_bytes -= 16;
3658          const_offset = 16;
3659       } else if (num_bytes == 12 && ctx->options->chip_class == GFX6) {
3660          /* GFX6 doesn't support loading vec3, expand to vec4. */
3661          num_bytes = 16;
3662       }
3663
3664       switch (num_bytes) {
3665          case 4:
3666             op = aco_opcode::buffer_load_dword;
3667             break;
3668          case 8:
3669             op = aco_opcode::buffer_load_dwordx2;
3670             break;
3671          case 12:
3672             assert(ctx->options->chip_class > GFX6);
3673             op = aco_opcode::buffer_load_dwordx3;
3674             break;
3675          case 16:
3676             op = aco_opcode::buffer_load_dwordx4;
3677             break;
3678          default:
3679             unreachable("Load SSBO not implemented for this size.");
3680       }
3681       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
3682       mubuf->operands[0] = Operand(rsrc);
3683       mubuf->operands[1] = vaddr;
3684       mubuf->operands[2] = soffset;
3685       mubuf->offen = (offset.type() == RegType::vgpr);
3686       mubuf->glc = glc;
3687       mubuf->dlc = dlc;
3688       mubuf->barrier = readonly ? barrier_none : barrier_buffer;
3689       mubuf->can_reorder = readonly;
3690       mubuf->offset = const_offset;
3691       aco_ptr<Instruction> instr = std::move(mubuf);
3692
3693       if (dst.size() > 4) {
3694          assert(lower != Temp());
3695          Temp upper = bld.tmp(RegType::vgpr, dst.size() - lower.size());
3696          instr->definitions[0] = Definition(upper);
3697          bld.insert(std::move(instr));
3698          if (dst.size() == 8)
3699             emit_split_vector(ctx, upper, 2);
3700          instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size() / 2, 1));
3701          instr->operands[0] = Operand(emit_extract_vector(ctx, lower, 0, v2));
3702          instr->operands[1] = Operand(emit_extract_vector(ctx, lower, 1, v2));
3703          instr->operands[2] = Operand(emit_extract_vector(ctx, upper, 0, v2));
3704          if (dst.size() == 8)
3705             instr->operands[3] = Operand(emit_extract_vector(ctx, upper, 1, v2));
3706       } else if (dst.size() == 3 && ctx->options->chip_class == GFX6) {
3707          Temp vec = bld.tmp(v4);
3708          instr->definitions[0] = Definition(vec);
3709          bld.insert(std::move(instr));
3710          emit_split_vector(ctx, vec, 4);
3711
3712          instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, 3, 1));
3713          instr->operands[0] = Operand(emit_extract_vector(ctx, vec, 0, v1));
3714          instr->operands[1] = Operand(emit_extract_vector(ctx, vec, 1, v1));
3715          instr->operands[2] = Operand(emit_extract_vector(ctx, vec, 2, v1));
3716       }
3717
3718       if (dst.type() == RegType::sgpr) {
3719          Temp vec = bld.tmp(RegType::vgpr, dst.size());
3720          instr->definitions[0] = Definition(vec);
3721          bld.insert(std::move(instr));
3722          expand_vector(ctx, vec, dst, num_components, (1 << num_components) - 1);
3723       } else {
3724          instr->definitions[0] = Definition(dst);
3725          bld.insert(std::move(instr));
3726          emit_split_vector(ctx, dst, num_components);
3727       }
3728    } else {
3729       switch (num_bytes) {
3730          case 4:
3731             op = aco_opcode::s_buffer_load_dword;
3732             break;
3733          case 8:
3734             op = aco_opcode::s_buffer_load_dwordx2;
3735             break;
3736          case 12:
3737          case 16:
3738             op = aco_opcode::s_buffer_load_dwordx4;
3739             break;
3740          case 24:
3741          case 32:
3742             op = aco_opcode::s_buffer_load_dwordx8;
3743             break;
3744          default:
3745             unreachable("Load SSBO not implemented for this size.");
3746       }
3747       aco_ptr<SMEM_instruction> load{create_instruction<SMEM_instruction>(op, Format::SMEM, 2, 1)};
3748       load->operands[0] = Operand(rsrc);
3749       load->operands[1] = Operand(bld.as_uniform(offset));
3750       assert(load->operands[1].getTemp().type() == RegType::sgpr);
3751       load->definitions[0] = Definition(dst);
3752       load->glc = glc;
3753       load->dlc = dlc;
3754       load->barrier = readonly ? barrier_none : barrier_buffer;
3755       load->can_reorder = false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
3756       assert(ctx->options->chip_class >= GFX8 || !glc);
3757
3758       /* trim vector */
3759       if (dst.size() == 3) {
3760          Temp vec = bld.tmp(s4);
3761          load->definitions[0] = Definition(vec);
3762          bld.insert(std::move(load));
3763          emit_split_vector(ctx, vec, 4);
3764
3765          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
3766                     emit_extract_vector(ctx, vec, 0, s1),
3767                     emit_extract_vector(ctx, vec, 1, s1),
3768                     emit_extract_vector(ctx, vec, 2, s1));
3769       } else if (dst.size() == 6) {
3770          Temp vec = bld.tmp(s8);
3771          load->definitions[0] = Definition(vec);
3772          bld.insert(std::move(load));
3773          emit_split_vector(ctx, vec, 4);
3774
3775          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
3776                     emit_extract_vector(ctx, vec, 0, s2),
3777                     emit_extract_vector(ctx, vec, 1, s2),
3778                     emit_extract_vector(ctx, vec, 2, s2));
3779       } else {
3780          bld.insert(std::move(load));
3781       }
3782       emit_split_vector(ctx, dst, num_components);
3783    }
3784 }
3785
3786 void visit_load_ubo(isel_context *ctx, nir_intrinsic_instr *instr)
3787 {
3788    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3789    Temp rsrc = get_ssa_temp(ctx, instr->src[0].ssa);
3790
3791    Builder bld(ctx->program, ctx->block);
3792
3793    nir_intrinsic_instr* idx_instr = nir_instr_as_intrinsic(instr->src[0].ssa->parent_instr);
3794    unsigned desc_set = nir_intrinsic_desc_set(idx_instr);
3795    unsigned binding = nir_intrinsic_binding(idx_instr);
3796    radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
3797
3798    if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
3799       uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3800                            S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3801                            S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3802                            S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3803       if (ctx->options->chip_class >= GFX10) {
3804          desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3805                       S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3806                       S_008F0C_RESOURCE_LEVEL(1);
3807       } else {
3808          desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3809                       S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3810       }
3811       Temp upper_dwords = bld.pseudo(aco_opcode::p_create_vector, bld.def(s3),
3812                                      Operand(S_008F04_BASE_ADDRESS_HI(ctx->options->address32_hi)),
3813                                      Operand(0xFFFFFFFFu),
3814                                      Operand(desc_type));
3815       rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
3816                         rsrc, upper_dwords);
3817    } else {
3818       rsrc = convert_pointer_to_64_bit(ctx, rsrc);
3819       rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
3820    }
3821
3822    load_buffer(ctx, instr->num_components, dst, rsrc, get_ssa_temp(ctx, instr->src[1].ssa));
3823 }
3824
3825 void visit_load_push_constant(isel_context *ctx, nir_intrinsic_instr *instr)
3826 {
3827    Builder bld(ctx->program, ctx->block);
3828    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3829
3830    unsigned offset = nir_intrinsic_base(instr);
3831    nir_const_value *index_cv = nir_src_as_const_value(instr->src[0]);
3832    if (index_cv && instr->dest.ssa.bit_size == 32) {
3833
3834       unsigned count = instr->dest.ssa.num_components;
3835       unsigned start = (offset + index_cv->u32) / 4u;
3836       start -= ctx->args->ac.base_inline_push_consts;
3837       if (start + count <= ctx->args->ac.num_inline_push_consts) {
3838          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
3839          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
3840          for (unsigned i = 0; i < count; ++i) {
3841             elems[i] = get_arg(ctx, ctx->args->ac.inline_push_consts[start + i]);
3842             vec->operands[i] = Operand{elems[i]};
3843          }
3844          vec->definitions[0] = Definition(dst);
3845          ctx->block->instructions.emplace_back(std::move(vec));
3846          ctx->allocated_vec.emplace(dst.id(), elems);
3847          return;
3848       }
3849    }
3850
3851    Temp index = bld.as_uniform(get_ssa_temp(ctx, instr->src[0].ssa));
3852    if (offset != 0) // TODO check if index != 0 as well
3853       index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset), index);
3854    Temp ptr = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->ac.push_constants));
3855    Temp vec = dst;
3856    bool trim = false;
3857    aco_opcode op;
3858
3859    switch (dst.size()) {
3860    case 1:
3861       op = aco_opcode::s_load_dword;
3862       break;
3863    case 2:
3864       op = aco_opcode::s_load_dwordx2;
3865       break;
3866    case 3:
3867       vec = bld.tmp(s4);
3868       trim = true;
3869    case 4:
3870       op = aco_opcode::s_load_dwordx4;
3871       break;
3872    case 6:
3873       vec = bld.tmp(s8);
3874       trim = true;
3875    case 8:
3876       op = aco_opcode::s_load_dwordx8;
3877       break;
3878    default:
3879       unreachable("unimplemented or forbidden load_push_constant.");
3880    }
3881
3882    bld.smem(op, Definition(vec), ptr, index);
3883
3884    if (trim) {
3885       emit_split_vector(ctx, vec, 4);
3886       RegClass rc = dst.size() == 3 ? s1 : s2;
3887       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
3888                  emit_extract_vector(ctx, vec, 0, rc),
3889                  emit_extract_vector(ctx, vec, 1, rc),
3890                  emit_extract_vector(ctx, vec, 2, rc));
3891
3892    }
3893    emit_split_vector(ctx, dst, instr->dest.ssa.num_components);
3894 }
3895
3896 void visit_load_constant(isel_context *ctx, nir_intrinsic_instr *instr)
3897 {
3898    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3899
3900    Builder bld(ctx->program, ctx->block);
3901
3902    uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3903                         S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3904                         S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3905                         S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3906    if (ctx->options->chip_class >= GFX10) {
3907       desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3908                    S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3909                    S_008F0C_RESOURCE_LEVEL(1);
3910    } else {
3911       desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3912                    S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3913    }
3914
3915    unsigned base = nir_intrinsic_base(instr);
3916    unsigned range = nir_intrinsic_range(instr);
3917
3918    Temp offset = get_ssa_temp(ctx, instr->src[0].ssa);
3919    if (base && offset.type() == RegType::sgpr)
3920       offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), offset, Operand(base));
3921    else if (base && offset.type() == RegType::vgpr)
3922       offset = bld.vadd32(bld.def(v1), Operand(base), offset);
3923
3924    Temp rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
3925                           bld.sop1(aco_opcode::p_constaddr, bld.def(s2), bld.def(s1, scc), Operand(ctx->constant_data_offset)),
3926                           Operand(MIN2(base + range, ctx->shader->constant_data_size)),
3927                           Operand(desc_type));
3928
3929    load_buffer(ctx, instr->num_components, dst, rsrc, offset);
3930 }
3931
3932 void visit_discard_if(isel_context *ctx, nir_intrinsic_instr *instr)
3933 {
3934    if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
3935       ctx->cf_info.exec_potentially_empty_discard = true;
3936
3937    ctx->program->needs_exact = true;
3938
3939    // TODO: optimize uniform conditions
3940    Builder bld(ctx->program, ctx->block);
3941    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
3942    assert(src.regClass() == bld.lm);
3943    src = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
3944    bld.pseudo(aco_opcode::p_discard_if, src);
3945    ctx->block->kind |= block_kind_uses_discard_if;
3946    return;
3947 }
3948
3949 void visit_discard(isel_context* ctx, nir_intrinsic_instr *instr)
3950 {
3951    Builder bld(ctx->program, ctx->block);
3952
3953    if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
3954       ctx->cf_info.exec_potentially_empty_discard = true;
3955
3956    bool divergent = ctx->cf_info.parent_if.is_divergent ||
3957                     ctx->cf_info.parent_loop.has_divergent_continue;
3958
3959    if (ctx->block->loop_nest_depth &&
3960        ((nir_instr_is_last(&instr->instr) && !divergent) || divergent)) {
3961       /* we handle discards the same way as jump instructions */
3962       append_logical_end(ctx->block);
3963
3964       /* in loops, discard behaves like break */
3965       Block *linear_target = ctx->cf_info.parent_loop.exit;
3966       ctx->block->kind |= block_kind_discard;
3967
3968       if (!divergent) {
3969          /* uniform discard - loop ends here */
3970          assert(nir_instr_is_last(&instr->instr));
3971          ctx->block->kind |= block_kind_uniform;
3972          ctx->cf_info.has_branch = true;
3973          bld.branch(aco_opcode::p_branch);
3974          add_linear_edge(ctx->block->index, linear_target);
3975          return;
3976       }
3977
3978       /* we add a break right behind the discard() instructions */
3979       ctx->block->kind |= block_kind_break;
3980       unsigned idx = ctx->block->index;
3981
3982       /* remove critical edges from linear CFG */
3983       bld.branch(aco_opcode::p_branch);
3984       Block* break_block = ctx->program->create_and_insert_block();
3985       break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
3986       break_block->kind |= block_kind_uniform;
3987       add_linear_edge(idx, break_block);
3988       add_linear_edge(break_block->index, linear_target);
3989       bld.reset(break_block);
3990       bld.branch(aco_opcode::p_branch);
3991
3992       Block* continue_block = ctx->program->create_and_insert_block();
3993       continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
3994       add_linear_edge(idx, continue_block);
3995       append_logical_start(continue_block);
3996       ctx->block = continue_block;
3997
3998       return;
3999    }
4000
4001    /* it can currently happen that NIR doesn't remove the unreachable code */
4002    if (!nir_instr_is_last(&instr->instr)) {
4003       ctx->program->needs_exact = true;
4004       /* save exec somewhere temporarily so that it doesn't get
4005        * overwritten before the discard from outer exec masks */
4006       Temp cond = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), Operand(0xFFFFFFFF), Operand(exec, bld.lm));
4007       bld.pseudo(aco_opcode::p_discard_if, cond);
4008       ctx->block->kind |= block_kind_uses_discard_if;
4009       return;
4010    }
4011
4012    /* This condition is incorrect for uniformly branched discards in a loop
4013     * predicated by a divergent condition, but the above code catches that case
4014     * and the discard would end up turning into a discard_if.
4015     * For example:
4016     * if (divergent) {
4017     *    while (...) {
4018     *       if (uniform) {
4019     *          discard;
4020     *       }
4021     *    }
4022     * }
4023     */
4024    if (!ctx->cf_info.parent_if.is_divergent) {
4025       /* program just ends here */
4026       ctx->block->kind |= block_kind_uniform;
4027       bld.exp(aco_opcode::exp, Operand(v1), Operand(v1), Operand(v1), Operand(v1),
4028               0 /* enabled mask */, 9 /* dest */,
4029               false /* compressed */, true/* done */, true /* valid mask */);
4030       bld.sopp(aco_opcode::s_endpgm);
4031       // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
4032    } else {
4033       ctx->block->kind |= block_kind_discard;
4034       /* branch and linear edge is added by visit_if() */
4035    }
4036 }
4037
4038 enum aco_descriptor_type {
4039    ACO_DESC_IMAGE,
4040    ACO_DESC_FMASK,
4041    ACO_DESC_SAMPLER,
4042    ACO_DESC_BUFFER,
4043    ACO_DESC_PLANE_0,
4044    ACO_DESC_PLANE_1,
4045    ACO_DESC_PLANE_2,
4046 };
4047
4048 static bool
4049 should_declare_array(isel_context *ctx, enum glsl_sampler_dim sampler_dim, bool is_array) {
4050    if (sampler_dim == GLSL_SAMPLER_DIM_BUF)
4051       return false;
4052    ac_image_dim dim = ac_get_sampler_dim(ctx->options->chip_class, sampler_dim, is_array);
4053    return dim == ac_image_cube ||
4054           dim == ac_image_1darray ||
4055           dim == ac_image_2darray ||
4056           dim == ac_image_2darraymsaa;
4057 }
4058
4059 Temp get_sampler_desc(isel_context *ctx, nir_deref_instr *deref_instr,
4060                       enum aco_descriptor_type desc_type,
4061                       const nir_tex_instr *tex_instr, bool image, bool write)
4062 {
4063 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
4064    std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
4065    if (it != ctx->tex_desc.end())
4066       return it->second;
4067 */
4068    Temp index = Temp();
4069    bool index_set = false;
4070    unsigned constant_index = 0;
4071    unsigned descriptor_set;
4072    unsigned base_index;
4073    Builder bld(ctx->program, ctx->block);
4074
4075    if (!deref_instr) {
4076       assert(tex_instr && !image);
4077       descriptor_set = 0;
4078       base_index = tex_instr->sampler_index;
4079    } else {
4080       while(deref_instr->deref_type != nir_deref_type_var) {
4081          unsigned array_size = glsl_get_aoa_size(deref_instr->type);
4082          if (!array_size)
4083             array_size = 1;
4084
4085          assert(deref_instr->deref_type == nir_deref_type_array);
4086          nir_const_value *const_value = nir_src_as_const_value(deref_instr->arr.index);
4087          if (const_value) {
4088             constant_index += array_size * const_value->u32;
4089          } else {
4090             Temp indirect = get_ssa_temp(ctx, deref_instr->arr.index.ssa);
4091             if (indirect.type() == RegType::vgpr)
4092                indirect = bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), indirect);
4093
4094             if (array_size != 1)
4095                indirect = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(array_size), indirect);
4096
4097             if (!index_set) {
4098                index = indirect;
4099                index_set = true;
4100             } else {
4101                index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), index, indirect);
4102             }
4103          }
4104
4105          deref_instr = nir_src_as_deref(deref_instr->parent);
4106       }
4107       descriptor_set = deref_instr->var->data.descriptor_set;
4108       base_index = deref_instr->var->data.binding;
4109    }
4110
4111    Temp list = load_desc_ptr(ctx, descriptor_set);
4112    list = convert_pointer_to_64_bit(ctx, list);
4113
4114    struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4115    struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4116    unsigned offset = binding->offset;
4117    unsigned stride = binding->size;
4118    aco_opcode opcode;
4119    RegClass type;
4120
4121    assert(base_index < layout->binding_count);
4122
4123    switch (desc_type) {
4124    case ACO_DESC_IMAGE:
4125       type = s8;
4126       opcode = aco_opcode::s_load_dwordx8;
4127       break;
4128    case ACO_DESC_FMASK:
4129       type = s8;
4130       opcode = aco_opcode::s_load_dwordx8;
4131       offset += 32;
4132       break;
4133    case ACO_DESC_SAMPLER:
4134       type = s4;
4135       opcode = aco_opcode::s_load_dwordx4;
4136       if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4137          offset += radv_combined_image_descriptor_sampler_offset(binding);
4138       break;
4139    case ACO_DESC_BUFFER:
4140       type = s4;
4141       opcode = aco_opcode::s_load_dwordx4;
4142       break;
4143    case ACO_DESC_PLANE_0:
4144    case ACO_DESC_PLANE_1:
4145       type = s8;
4146       opcode = aco_opcode::s_load_dwordx8;
4147       offset += 32 * (desc_type - ACO_DESC_PLANE_0);
4148       break;
4149    case ACO_DESC_PLANE_2:
4150       type = s4;
4151       opcode = aco_opcode::s_load_dwordx4;
4152       offset += 64;
4153       break;
4154    default:
4155       unreachable("invalid desc_type\n");
4156    }
4157
4158    offset += constant_index * stride;
4159
4160    if (desc_type == ACO_DESC_SAMPLER && binding->immutable_samplers_offset &&
4161       (!index_set || binding->immutable_samplers_equal)) {
4162       if (binding->immutable_samplers_equal)
4163          constant_index = 0;
4164
4165       const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4166       return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
4167                         Operand(samplers[constant_index * 4 + 0]),
4168                         Operand(samplers[constant_index * 4 + 1]),
4169                         Operand(samplers[constant_index * 4 + 2]),
4170                         Operand(samplers[constant_index * 4 + 3]));
4171    }
4172
4173    Operand off;
4174    if (!index_set) {
4175       off = bld.copy(bld.def(s1), Operand(offset));
4176    } else {
4177       off = Operand((Temp)bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset),
4178                                    bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), index)));
4179    }
4180
4181    Temp res = bld.smem(opcode, bld.def(type), list, off);
4182
4183    if (desc_type == ACO_DESC_PLANE_2) {
4184       Temp components[8];
4185       for (unsigned i = 0; i < 8; i++)
4186          components[i] = bld.tmp(s1);
4187       bld.pseudo(aco_opcode::p_split_vector,
4188                  Definition(components[0]),
4189                  Definition(components[1]),
4190                  Definition(components[2]),
4191                  Definition(components[3]),
4192                  res);
4193
4194       Temp desc2 = get_sampler_desc(ctx, deref_instr, ACO_DESC_PLANE_1, tex_instr, image, write);
4195       bld.pseudo(aco_opcode::p_split_vector,
4196                  bld.def(s1), bld.def(s1), bld.def(s1), bld.def(s1),
4197                  Definition(components[4]),
4198                  Definition(components[5]),
4199                  Definition(components[6]),
4200                  Definition(components[7]),
4201                  desc2);
4202
4203       res = bld.pseudo(aco_opcode::p_create_vector, bld.def(s8),
4204                        components[0], components[1], components[2], components[3],
4205                        components[4], components[5], components[6], components[7]);
4206    }
4207
4208    return res;
4209 }
4210
4211 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
4212 {
4213    switch (dim) {
4214    case GLSL_SAMPLER_DIM_BUF:
4215       return 1;
4216    case GLSL_SAMPLER_DIM_1D:
4217       return array ? 2 : 1;
4218    case GLSL_SAMPLER_DIM_2D:
4219       return array ? 3 : 2;
4220    case GLSL_SAMPLER_DIM_MS:
4221       return array ? 4 : 3;
4222    case GLSL_SAMPLER_DIM_3D:
4223    case GLSL_SAMPLER_DIM_CUBE:
4224       return 3;
4225    case GLSL_SAMPLER_DIM_RECT:
4226    case GLSL_SAMPLER_DIM_SUBPASS:
4227       return 2;
4228    case GLSL_SAMPLER_DIM_SUBPASS_MS:
4229       return 3;
4230    default:
4231       break;
4232    }
4233    return 0;
4234 }
4235
4236
4237 /* Adjust the sample index according to FMASK.
4238  *
4239  * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4240  * which is the identity mapping. Each nibble says which physical sample
4241  * should be fetched to get that sample.
4242  *
4243  * For example, 0x11111100 means there are only 2 samples stored and
4244  * the second sample covers 3/4 of the pixel. When reading samples 0
4245  * and 1, return physical sample 0 (determined by the first two 0s
4246  * in FMASK), otherwise return physical sample 1.
4247  *
4248  * The sample index should be adjusted as follows:
4249  *   sample_index = (fmask >> (sample_index * 4)) & 0xF;
4250  */
4251 static Temp adjust_sample_index_using_fmask(isel_context *ctx, bool da, std::vector<Temp>& coords, Operand sample_index, Temp fmask_desc_ptr)
4252 {
4253    Builder bld(ctx->program, ctx->block);
4254    Temp fmask = bld.tmp(v1);
4255    unsigned dim = ctx->options->chip_class >= GFX10
4256                   ? ac_get_sampler_dim(ctx->options->chip_class, GLSL_SAMPLER_DIM_2D, da)
4257                   : 0;
4258
4259    Temp coord = da ? bld.pseudo(aco_opcode::p_create_vector, bld.def(v3), coords[0], coords[1], coords[2]) :
4260                      bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), coords[0], coords[1]);
4261    aco_ptr<MIMG_instruction> load{create_instruction<MIMG_instruction>(aco_opcode::image_load, Format::MIMG, 3, 1)};
4262    load->operands[0] = Operand(fmask_desc_ptr);
4263    load->operands[1] = Operand(s4); /* no sampler */
4264    load->operands[2] = Operand(coord);
4265    load->definitions[0] = Definition(fmask);
4266    load->glc = false;
4267    load->dlc = false;
4268    load->dmask = 0x1;
4269    load->unrm = true;
4270    load->da = da;
4271    load->dim = dim;
4272    load->can_reorder = true; /* fmask images shouldn't be modified */
4273    ctx->block->instructions.emplace_back(std::move(load));
4274
4275    Operand sample_index4;
4276    if (sample_index.isConstant() && sample_index.constantValue() < 16) {
4277       sample_index4 = Operand(sample_index.constantValue() << 2);
4278    } else if (sample_index.regClass() == s1) {
4279       sample_index4 = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), sample_index, Operand(2u));
4280    } else {
4281       assert(sample_index.regClass() == v1);
4282       sample_index4 = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), sample_index);
4283    }
4284
4285    Temp final_sample;
4286    if (sample_index4.isConstant() && sample_index4.constantValue() == 0)
4287       final_sample = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(15u), fmask);
4288    else if (sample_index4.isConstant() && sample_index4.constantValue() == 28)
4289       final_sample = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(28u), fmask);
4290    else
4291       final_sample = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1), fmask, sample_index4, Operand(4u));
4292
4293    /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4294     * resource descriptor is 0 (invalid),
4295     */
4296    Temp compare = bld.tmp(bld.lm);
4297    bld.vopc_e64(aco_opcode::v_cmp_lg_u32, Definition(compare),
4298                 Operand(0u), emit_extract_vector(ctx, fmask_desc_ptr, 1, s1)).def(0).setHint(vcc);
4299
4300    Temp sample_index_v = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), sample_index);
4301
4302    /* Replace the MSAA sample index. */
4303    return bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), sample_index_v, final_sample, compare);
4304 }
4305
4306 static Temp get_image_coords(isel_context *ctx, const nir_intrinsic_instr *instr, const struct glsl_type *type)
4307 {
4308
4309    Temp src0 = get_ssa_temp(ctx, instr->src[1].ssa);
4310    enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4311    bool is_array = glsl_sampler_type_is_array(type);
4312    ASSERTED bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS || dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
4313    assert(!add_frag_pos && "Input attachments should be lowered.");
4314    bool is_ms = (dim == GLSL_SAMPLER_DIM_MS || dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
4315    bool gfx9_1d = ctx->options->chip_class == GFX9 && dim == GLSL_SAMPLER_DIM_1D;
4316    int count = image_type_to_components_count(dim, is_array);
4317    std::vector<Temp> coords(count);
4318    Builder bld(ctx->program, ctx->block);
4319
4320    if (is_ms) {
4321       count--;
4322       Temp src2 = get_ssa_temp(ctx, instr->src[2].ssa);
4323       /* get sample index */
4324       if (instr->intrinsic == nir_intrinsic_image_deref_load) {
4325          nir_const_value *sample_cv = nir_src_as_const_value(instr->src[2]);
4326          Operand sample_index = sample_cv ? Operand(sample_cv->u32) : Operand(emit_extract_vector(ctx, src2, 0, v1));
4327          std::vector<Temp> fmask_load_address;
4328          for (unsigned i = 0; i < (is_array ? 3 : 2); i++)
4329             fmask_load_address.emplace_back(emit_extract_vector(ctx, src0, i, v1));
4330
4331          Temp fmask_desc_ptr = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_FMASK, nullptr, false, false);
4332          coords[count] = adjust_sample_index_using_fmask(ctx, is_array, fmask_load_address, sample_index, fmask_desc_ptr);
4333       } else {
4334          coords[count] = emit_extract_vector(ctx, src2, 0, v1);
4335       }
4336    }
4337
4338    if (gfx9_1d) {
4339       coords[0] = emit_extract_vector(ctx, src0, 0, v1);
4340       coords.resize(coords.size() + 1);
4341       coords[1] = bld.copy(bld.def(v1), Operand(0u));
4342       if (is_array)
4343          coords[2] = emit_extract_vector(ctx, src0, 1, v1);
4344    } else {
4345       for (int i = 0; i < count; i++)
4346          coords[i] = emit_extract_vector(ctx, src0, i, v1);
4347    }
4348
4349    if (instr->intrinsic == nir_intrinsic_image_deref_load ||
4350        instr->intrinsic == nir_intrinsic_image_deref_store) {
4351       int lod_index = instr->intrinsic == nir_intrinsic_image_deref_load ? 3 : 4;
4352       bool level_zero = nir_src_is_const(instr->src[lod_index]) && nir_src_as_uint(instr->src[lod_index]) == 0;
4353
4354       if (!level_zero)
4355          coords.emplace_back(get_ssa_temp(ctx, instr->src[lod_index].ssa));
4356    }
4357
4358    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, coords.size(), 1)};
4359    for (unsigned i = 0; i < coords.size(); i++)
4360       vec->operands[i] = Operand(coords[i]);
4361    Temp res = {ctx->program->allocateId(), RegClass(RegType::vgpr, coords.size())};
4362    vec->definitions[0] = Definition(res);
4363    ctx->block->instructions.emplace_back(std::move(vec));
4364    return res;
4365 }
4366
4367
4368 void visit_image_load(isel_context *ctx, nir_intrinsic_instr *instr)
4369 {
4370    Builder bld(ctx->program, ctx->block);
4371    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4372    const struct glsl_type *type = glsl_without_array(var->type);
4373    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4374    bool is_array = glsl_sampler_type_is_array(type);
4375    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4376
4377    if (dim == GLSL_SAMPLER_DIM_BUF) {
4378       unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
4379       unsigned num_channels = util_last_bit(mask);
4380       Temp rsrc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4381       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4382
4383       aco_opcode opcode;
4384       switch (num_channels) {
4385       case 1:
4386          opcode = aco_opcode::buffer_load_format_x;
4387          break;
4388       case 2:
4389          opcode = aco_opcode::buffer_load_format_xy;
4390          break;
4391       case 3:
4392          opcode = aco_opcode::buffer_load_format_xyz;
4393          break;
4394       case 4:
4395          opcode = aco_opcode::buffer_load_format_xyzw;
4396          break;
4397       default:
4398          unreachable(">4 channel buffer image load");
4399       }
4400       aco_ptr<MUBUF_instruction> load{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 3, 1)};
4401       load->operands[0] = Operand(rsrc);
4402       load->operands[1] = Operand(vindex);
4403       load->operands[2] = Operand((uint32_t) 0);
4404       Temp tmp;
4405       if (num_channels == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
4406          tmp = dst;
4407       else
4408          tmp = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_channels)};
4409       load->definitions[0] = Definition(tmp);
4410       load->idxen = true;
4411       load->glc = var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT);
4412       load->dlc = load->glc && ctx->options->chip_class >= GFX10;
4413       load->barrier = barrier_image;
4414       ctx->block->instructions.emplace_back(std::move(load));
4415
4416       expand_vector(ctx, tmp, dst, instr->dest.ssa.num_components, (1 << num_channels) - 1);
4417       return;
4418    }
4419
4420    Temp coords = get_image_coords(ctx, instr, type);
4421    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
4422
4423    unsigned dmask = nir_ssa_def_components_read(&instr->dest.ssa);
4424    unsigned num_components = util_bitcount(dmask);
4425    Temp tmp;
4426    if (num_components == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
4427       tmp = dst;
4428    else
4429       tmp = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_components)};
4430
4431    bool level_zero = nir_src_is_const(instr->src[3]) && nir_src_as_uint(instr->src[3]) == 0;
4432    aco_opcode opcode = level_zero ? aco_opcode::image_load : aco_opcode::image_load_mip;
4433
4434    aco_ptr<MIMG_instruction> load{create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 1)};
4435    load->operands[0] = Operand(resource);
4436    load->operands[1] = Operand(s4); /* no sampler */
4437    load->operands[2] = Operand(coords);
4438    load->definitions[0] = Definition(tmp);
4439    load->glc = var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT) ? 1 : 0;
4440    load->dlc = load->glc && ctx->options->chip_class >= GFX10;
4441    load->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4442    load->dmask = dmask;
4443    load->unrm = true;
4444    load->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
4445    load->barrier = barrier_image;
4446    ctx->block->instructions.emplace_back(std::move(load));
4447
4448    expand_vector(ctx, tmp, dst, instr->dest.ssa.num_components, dmask);
4449    return;
4450 }
4451
4452 void visit_image_store(isel_context *ctx, nir_intrinsic_instr *instr)
4453 {
4454    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4455    const struct glsl_type *type = glsl_without_array(var->type);
4456    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4457    bool is_array = glsl_sampler_type_is_array(type);
4458    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[3].ssa));
4459
4460    bool glc = ctx->options->chip_class == GFX6 || var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE) ? 1 : 0;
4461
4462    if (dim == GLSL_SAMPLER_DIM_BUF) {
4463       Temp rsrc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4464       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4465       aco_opcode opcode;
4466       switch (data.size()) {
4467       case 1:
4468          opcode = aco_opcode::buffer_store_format_x;
4469          break;
4470       case 2:
4471          opcode = aco_opcode::buffer_store_format_xy;
4472          break;
4473       case 3:
4474          opcode = aco_opcode::buffer_store_format_xyz;
4475          break;
4476       case 4:
4477          opcode = aco_opcode::buffer_store_format_xyzw;
4478          break;
4479       default:
4480          unreachable(">4 channel buffer image store");
4481       }
4482       aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 4, 0)};
4483       store->operands[0] = Operand(rsrc);
4484       store->operands[1] = Operand(vindex);
4485       store->operands[2] = Operand((uint32_t) 0);
4486       store->operands[3] = Operand(data);
4487       store->idxen = true;
4488       store->glc = glc;
4489       store->dlc = false;
4490       store->disable_wqm = true;
4491       store->barrier = barrier_image;
4492       ctx->program->needs_exact = true;
4493       ctx->block->instructions.emplace_back(std::move(store));
4494       return;
4495    }
4496
4497    assert(data.type() == RegType::vgpr);
4498    Temp coords = get_image_coords(ctx, instr, type);
4499    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
4500
4501    bool level_zero = nir_src_is_const(instr->src[4]) && nir_src_as_uint(instr->src[4]) == 0;
4502    aco_opcode opcode = level_zero ? aco_opcode::image_store : aco_opcode::image_store_mip;
4503
4504    aco_ptr<MIMG_instruction> store{create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 0)};
4505    store->operands[0] = Operand(resource);
4506    store->operands[1] = Operand(data);
4507    store->operands[2] = Operand(coords);
4508    store->glc = glc;
4509    store->dlc = false;
4510    store->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4511    store->dmask = (1 << data.size()) - 1;
4512    store->unrm = true;
4513    store->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
4514    store->disable_wqm = true;
4515    store->barrier = barrier_image;
4516    ctx->program->needs_exact = true;
4517    ctx->block->instructions.emplace_back(std::move(store));
4518    return;
4519 }
4520
4521 void visit_image_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
4522 {
4523    /* return the previous value if dest is ever used */
4524    bool return_previous = false;
4525    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
4526       return_previous = true;
4527       break;
4528    }
4529    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
4530       return_previous = true;
4531       break;
4532    }
4533
4534    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4535    const struct glsl_type *type = glsl_without_array(var->type);
4536    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4537    bool is_array = glsl_sampler_type_is_array(type);
4538    Builder bld(ctx->program, ctx->block);
4539
4540    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[3].ssa));
4541    assert(data.size() == 1 && "64bit ssbo atomics not yet implemented.");
4542
4543    if (instr->intrinsic == nir_intrinsic_image_deref_atomic_comp_swap)
4544       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), get_ssa_temp(ctx, instr->src[4].ssa), data);
4545
4546    aco_opcode buf_op, image_op;
4547    switch (instr->intrinsic) {
4548       case nir_intrinsic_image_deref_atomic_add:
4549          buf_op = aco_opcode::buffer_atomic_add;
4550          image_op = aco_opcode::image_atomic_add;
4551          break;
4552       case nir_intrinsic_image_deref_atomic_umin:
4553          buf_op = aco_opcode::buffer_atomic_umin;
4554          image_op = aco_opcode::image_atomic_umin;
4555          break;
4556       case nir_intrinsic_image_deref_atomic_imin:
4557          buf_op = aco_opcode::buffer_atomic_smin;
4558          image_op = aco_opcode::image_atomic_smin;
4559          break;
4560       case nir_intrinsic_image_deref_atomic_umax:
4561          buf_op = aco_opcode::buffer_atomic_umax;
4562          image_op = aco_opcode::image_atomic_umax;
4563          break;
4564       case nir_intrinsic_image_deref_atomic_imax:
4565          buf_op = aco_opcode::buffer_atomic_smax;
4566          image_op = aco_opcode::image_atomic_smax;
4567          break;
4568       case nir_intrinsic_image_deref_atomic_and:
4569          buf_op = aco_opcode::buffer_atomic_and;
4570          image_op = aco_opcode::image_atomic_and;
4571          break;
4572       case nir_intrinsic_image_deref_atomic_or:
4573          buf_op = aco_opcode::buffer_atomic_or;
4574          image_op = aco_opcode::image_atomic_or;
4575          break;
4576       case nir_intrinsic_image_deref_atomic_xor:
4577          buf_op = aco_opcode::buffer_atomic_xor;
4578          image_op = aco_opcode::image_atomic_xor;
4579          break;
4580       case nir_intrinsic_image_deref_atomic_exchange:
4581          buf_op = aco_opcode::buffer_atomic_swap;
4582          image_op = aco_opcode::image_atomic_swap;
4583          break;
4584       case nir_intrinsic_image_deref_atomic_comp_swap:
4585          buf_op = aco_opcode::buffer_atomic_cmpswap;
4586          image_op = aco_opcode::image_atomic_cmpswap;
4587          break;
4588       default:
4589          unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
4590    }
4591
4592    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4593
4594    if (dim == GLSL_SAMPLER_DIM_BUF) {
4595       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4596       Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4597       //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
4598       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(buf_op, Format::MUBUF, 4, return_previous ? 1 : 0)};
4599       mubuf->operands[0] = Operand(resource);
4600       mubuf->operands[1] = Operand(vindex);
4601       mubuf->operands[2] = Operand((uint32_t)0);
4602       mubuf->operands[3] = Operand(data);
4603       if (return_previous)
4604          mubuf->definitions[0] = Definition(dst);
4605       mubuf->offset = 0;
4606       mubuf->idxen = true;
4607       mubuf->glc = return_previous;
4608       mubuf->dlc = false; /* Not needed for atomics */
4609       mubuf->disable_wqm = true;
4610       mubuf->barrier = barrier_image;
4611       ctx->program->needs_exact = true;
4612       ctx->block->instructions.emplace_back(std::move(mubuf));
4613       return;
4614    }
4615
4616    Temp coords = get_image_coords(ctx, instr, type);
4617    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
4618    aco_ptr<MIMG_instruction> mimg{create_instruction<MIMG_instruction>(image_op, Format::MIMG, 3, return_previous ? 1 : 0)};
4619    mimg->operands[0] = Operand(resource);
4620    mimg->operands[1] = Operand(data);
4621    mimg->operands[2] = Operand(coords);
4622    if (return_previous)
4623       mimg->definitions[0] = Definition(dst);
4624    mimg->glc = return_previous;
4625    mimg->dlc = false; /* Not needed for atomics */
4626    mimg->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4627    mimg->dmask = (1 << data.size()) - 1;
4628    mimg->unrm = true;
4629    mimg->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
4630    mimg->disable_wqm = true;
4631    mimg->barrier = barrier_image;
4632    ctx->program->needs_exact = true;
4633    ctx->block->instructions.emplace_back(std::move(mimg));
4634    return;
4635 }
4636
4637 void get_buffer_size(isel_context *ctx, Temp desc, Temp dst, bool in_elements)
4638 {
4639    if (in_elements && ctx->options->chip_class == GFX8) {
4640       /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
4641       Builder bld(ctx->program, ctx->block);
4642
4643       Temp size = emit_extract_vector(ctx, desc, 2, s1);
4644
4645       Temp size_div3 = bld.vop3(aco_opcode::v_mul_hi_u32, bld.def(v1), bld.copy(bld.def(v1), Operand(0xaaaaaaabu)), size);
4646       size_div3 = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.as_uniform(size_div3), Operand(1u));
4647
4648       Temp stride = emit_extract_vector(ctx, desc, 1, s1);
4649       stride = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), stride, Operand((5u << 16) | 16u));
4650
4651       Temp is12 = bld.sopc(aco_opcode::s_cmp_eq_i32, bld.def(s1, scc), stride, Operand(12u));
4652       size = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), size_div3, size, bld.scc(is12));
4653
4654       Temp shr_dst = dst.type() == RegType::vgpr ? bld.tmp(s1) : dst;
4655       bld.sop2(aco_opcode::s_lshr_b32, Definition(shr_dst), bld.def(s1, scc),
4656                size, bld.sop1(aco_opcode::s_ff1_i32_b32, bld.def(s1), stride));
4657       if (dst.type() == RegType::vgpr)
4658          bld.copy(Definition(dst), shr_dst);
4659
4660       /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
4661    } else {
4662       emit_extract_vector(ctx, desc, 2, dst);
4663    }
4664 }
4665
4666 void visit_image_size(isel_context *ctx, nir_intrinsic_instr *instr)
4667 {
4668    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4669    const struct glsl_type *type = glsl_without_array(var->type);
4670    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4671    bool is_array = glsl_sampler_type_is_array(type);
4672    Builder bld(ctx->program, ctx->block);
4673
4674    if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
4675       Temp desc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, NULL, true, false);
4676       return get_buffer_size(ctx, desc, get_ssa_temp(ctx, &instr->dest.ssa), true);
4677    }
4678
4679    /* LOD */
4680    Temp lod = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
4681
4682    /* Resource */
4683    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, NULL, true, false);
4684
4685    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4686
4687    aco_ptr<MIMG_instruction> mimg{create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 3, 1)};
4688    mimg->operands[0] = Operand(resource);
4689    mimg->operands[1] = Operand(s4); /* no sampler */
4690    mimg->operands[2] = Operand(lod);
4691    uint8_t& dmask = mimg->dmask;
4692    mimg->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4693    mimg->dmask = (1 << instr->dest.ssa.num_components) - 1;
4694    mimg->da = glsl_sampler_type_is_array(type);
4695    mimg->can_reorder = true;
4696    Definition& def = mimg->definitions[0];
4697    ctx->block->instructions.emplace_back(std::move(mimg));
4698
4699    if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
4700        glsl_sampler_type_is_array(type)) {
4701
4702       assert(instr->dest.ssa.num_components == 3);
4703       Temp tmp = {ctx->program->allocateId(), v3};
4704       def = Definition(tmp);
4705       emit_split_vector(ctx, tmp, 3);
4706
4707       /* divide 3rd value by 6 by multiplying with magic number */
4708       Temp c = bld.copy(bld.def(s1), Operand((uint32_t) 0x2AAAAAAB));
4709       Temp by_6 = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), emit_extract_vector(ctx, tmp, 2, v1), c);
4710
4711       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4712                  emit_extract_vector(ctx, tmp, 0, v1),
4713                  emit_extract_vector(ctx, tmp, 1, v1),
4714                  by_6);
4715
4716    } else if (ctx->options->chip_class == GFX9 &&
4717               glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
4718               glsl_sampler_type_is_array(type)) {
4719       assert(instr->dest.ssa.num_components == 2);
4720       def = Definition(dst);
4721       dmask = 0x5;
4722    } else {
4723       def = Definition(dst);
4724    }
4725
4726    emit_split_vector(ctx, dst, instr->dest.ssa.num_components);
4727 }
4728
4729 void visit_load_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
4730 {
4731    Builder bld(ctx->program, ctx->block);
4732    unsigned num_components = instr->num_components;
4733
4734    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4735    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4736    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
4737
4738    bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT);
4739    load_buffer(ctx, num_components, dst, rsrc, get_ssa_temp(ctx, instr->src[1].ssa), glc, false);
4740 }
4741
4742 void visit_store_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
4743 {
4744    Builder bld(ctx->program, ctx->block);
4745    Temp data = get_ssa_temp(ctx, instr->src[0].ssa);
4746    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
4747    unsigned writemask = nir_intrinsic_write_mask(instr);
4748    Temp offset = get_ssa_temp(ctx, instr->src[2].ssa);
4749
4750    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
4751    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
4752
4753    bool smem = !ctx->divergent_vals[instr->src[2].ssa->index] &&
4754                ctx->options->chip_class >= GFX8;
4755    if (smem)
4756       offset = bld.as_uniform(offset);
4757    bool smem_nonfs = smem && ctx->stage != fragment_fs;
4758
4759    while (writemask) {
4760       int start, count;
4761       u_bit_scan_consecutive_range(&writemask, &start, &count);
4762       if (count == 3 && (smem || ctx->options->chip_class == GFX6)) {
4763          /* GFX6 doesn't support storing vec3, split it. */
4764          writemask |= 1u << (start + 2);
4765          count = 2;
4766       }
4767       int num_bytes = count * elem_size_bytes;
4768
4769       if (num_bytes > 16) {
4770          assert(elem_size_bytes == 8);
4771          writemask |= (((count - 2) << 1) - 1) << (start + 2);
4772          count = 2;
4773          num_bytes = 16;
4774       }
4775
4776       // TODO: check alignment of sub-dword stores
4777       // TODO: split 3 bytes. there is no store instruction for that
4778
4779       Temp write_data;
4780       if (count != instr->num_components) {
4781          emit_split_vector(ctx, data, instr->num_components);
4782          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
4783          for (int i = 0; i < count; i++) {
4784             Temp elem = emit_extract_vector(ctx, data, start + i, RegClass(data.type(), elem_size_bytes / 4));
4785             vec->operands[i] = Operand(smem_nonfs ? bld.as_uniform(elem) : elem);
4786          }
4787          write_data = bld.tmp(!smem ? RegType::vgpr : smem_nonfs ? RegType::sgpr : data.type(), count * elem_size_bytes / 4);
4788          vec->definitions[0] = Definition(write_data);
4789          ctx->block->instructions.emplace_back(std::move(vec));
4790       } else if (!smem && data.type() != RegType::vgpr) {
4791          assert(num_bytes % 4 == 0);
4792          write_data = bld.copy(bld.def(RegType::vgpr, num_bytes / 4), data);
4793       } else if (smem_nonfs && data.type() == RegType::vgpr) {
4794          assert(num_bytes % 4 == 0);
4795          write_data = bld.as_uniform(data);
4796       } else {
4797          write_data = data;
4798       }
4799
4800       aco_opcode vmem_op, smem_op;
4801       switch (num_bytes) {
4802          case 4:
4803             vmem_op = aco_opcode::buffer_store_dword;
4804             smem_op = aco_opcode::s_buffer_store_dword;
4805             break;
4806          case 8:
4807             vmem_op = aco_opcode::buffer_store_dwordx2;
4808             smem_op = aco_opcode::s_buffer_store_dwordx2;
4809             break;
4810          case 12:
4811             vmem_op = aco_opcode::buffer_store_dwordx3;
4812             smem_op = aco_opcode::last_opcode;
4813             assert(!smem && ctx->options->chip_class > GFX6);
4814             break;
4815          case 16:
4816             vmem_op = aco_opcode::buffer_store_dwordx4;
4817             smem_op = aco_opcode::s_buffer_store_dwordx4;
4818             break;
4819          default:
4820             unreachable("Store SSBO not implemented for this size.");
4821       }
4822       if (ctx->stage == fragment_fs)
4823          smem_op = aco_opcode::p_fs_buffer_store_smem;
4824
4825       if (smem) {
4826          aco_ptr<SMEM_instruction> store{create_instruction<SMEM_instruction>(smem_op, Format::SMEM, 3, 0)};
4827          store->operands[0] = Operand(rsrc);
4828          if (start) {
4829             Temp off = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
4830                                 offset, Operand(start * elem_size_bytes));
4831             store->operands[1] = Operand(off);
4832          } else {
4833             store->operands[1] = Operand(offset);
4834          }
4835          if (smem_op != aco_opcode::p_fs_buffer_store_smem)
4836             store->operands[1].setFixed(m0);
4837          store->operands[2] = Operand(write_data);
4838          store->glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
4839          store->dlc = false;
4840          store->disable_wqm = true;
4841          store->barrier = barrier_buffer;
4842          ctx->block->instructions.emplace_back(std::move(store));
4843          ctx->program->wb_smem_l1_on_end = true;
4844          if (smem_op == aco_opcode::p_fs_buffer_store_smem) {
4845             ctx->block->kind |= block_kind_needs_lowering;
4846             ctx->program->needs_exact = true;
4847          }
4848       } else {
4849          aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(vmem_op, Format::MUBUF, 4, 0)};
4850          store->operands[0] = Operand(rsrc);
4851          store->operands[1] = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
4852          store->operands[2] = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
4853          store->operands[3] = Operand(write_data);
4854          store->offset = start * elem_size_bytes;
4855          store->offen = (offset.type() == RegType::vgpr);
4856          store->glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
4857          store->dlc = false;
4858          store->disable_wqm = true;
4859          store->barrier = barrier_buffer;
4860          ctx->program->needs_exact = true;
4861          ctx->block->instructions.emplace_back(std::move(store));
4862       }
4863    }
4864 }
4865
4866 void visit_atomic_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
4867 {
4868    /* return the previous value if dest is ever used */
4869    bool return_previous = false;
4870    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
4871       return_previous = true;
4872       break;
4873    }
4874    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
4875       return_previous = true;
4876       break;
4877    }
4878
4879    Builder bld(ctx->program, ctx->block);
4880    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[2].ssa));
4881
4882    if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap)
4883       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(RegType::vgpr, data.size() * 2),
4884                         get_ssa_temp(ctx, instr->src[3].ssa), data);
4885
4886    Temp offset = get_ssa_temp(ctx, instr->src[1].ssa);
4887    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4888    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
4889
4890    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4891
4892    aco_opcode op32, op64;
4893    switch (instr->intrinsic) {
4894       case nir_intrinsic_ssbo_atomic_add:
4895          op32 = aco_opcode::buffer_atomic_add;
4896          op64 = aco_opcode::buffer_atomic_add_x2;
4897          break;
4898       case nir_intrinsic_ssbo_atomic_imin:
4899          op32 = aco_opcode::buffer_atomic_smin;
4900          op64 = aco_opcode::buffer_atomic_smin_x2;
4901          break;
4902       case nir_intrinsic_ssbo_atomic_umin:
4903          op32 = aco_opcode::buffer_atomic_umin;
4904          op64 = aco_opcode::buffer_atomic_umin_x2;
4905          break;
4906       case nir_intrinsic_ssbo_atomic_imax:
4907          op32 = aco_opcode::buffer_atomic_smax;
4908          op64 = aco_opcode::buffer_atomic_smax_x2;
4909          break;
4910       case nir_intrinsic_ssbo_atomic_umax:
4911          op32 = aco_opcode::buffer_atomic_umax;
4912          op64 = aco_opcode::buffer_atomic_umax_x2;
4913          break;
4914       case nir_intrinsic_ssbo_atomic_and:
4915          op32 = aco_opcode::buffer_atomic_and;
4916          op64 = aco_opcode::buffer_atomic_and_x2;
4917          break;
4918       case nir_intrinsic_ssbo_atomic_or:
4919          op32 = aco_opcode::buffer_atomic_or;
4920          op64 = aco_opcode::buffer_atomic_or_x2;
4921          break;
4922       case nir_intrinsic_ssbo_atomic_xor:
4923          op32 = aco_opcode::buffer_atomic_xor;
4924          op64 = aco_opcode::buffer_atomic_xor_x2;
4925          break;
4926       case nir_intrinsic_ssbo_atomic_exchange:
4927          op32 = aco_opcode::buffer_atomic_swap;
4928          op64 = aco_opcode::buffer_atomic_swap_x2;
4929          break;
4930       case nir_intrinsic_ssbo_atomic_comp_swap:
4931          op32 = aco_opcode::buffer_atomic_cmpswap;
4932          op64 = aco_opcode::buffer_atomic_cmpswap_x2;
4933          break;
4934       default:
4935          unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
4936    }
4937    aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
4938    aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, return_previous ? 1 : 0)};
4939    mubuf->operands[0] = Operand(rsrc);
4940    mubuf->operands[1] = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
4941    mubuf->operands[2] = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
4942    mubuf->operands[3] = Operand(data);
4943    if (return_previous)
4944       mubuf->definitions[0] = Definition(dst);
4945    mubuf->offset = 0;
4946    mubuf->offen = (offset.type() == RegType::vgpr);
4947    mubuf->glc = return_previous;
4948    mubuf->dlc = false; /* Not needed for atomics */
4949    mubuf->disable_wqm = true;
4950    mubuf->barrier = barrier_buffer;
4951    ctx->program->needs_exact = true;
4952    ctx->block->instructions.emplace_back(std::move(mubuf));
4953 }
4954
4955 void visit_get_buffer_size(isel_context *ctx, nir_intrinsic_instr *instr) {
4956
4957    Temp index = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4958    Builder bld(ctx->program, ctx->block);
4959    Temp desc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), index, Operand(0u));
4960    get_buffer_size(ctx, desc, get_ssa_temp(ctx, &instr->dest.ssa), false);
4961 }
4962
4963 Temp get_gfx6_global_rsrc(Builder& bld, Temp addr)
4964 {
4965    uint32_t rsrc_conf = S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
4966                         S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
4967
4968    if (addr.type() == RegType::vgpr)
4969       return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf));
4970    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), addr, Operand(-1u), Operand(rsrc_conf));
4971 }
4972
4973 void visit_load_global(isel_context *ctx, nir_intrinsic_instr *instr)
4974 {
4975    Builder bld(ctx->program, ctx->block);
4976    unsigned num_components = instr->num_components;
4977    unsigned num_bytes = num_components * instr->dest.ssa.bit_size / 8;
4978
4979    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4980    Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
4981
4982    bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT);
4983    bool dlc = glc && ctx->options->chip_class >= GFX10;
4984    aco_opcode op;
4985    if (dst.type() == RegType::vgpr || (glc && ctx->options->chip_class < GFX8)) {
4986       bool global = ctx->options->chip_class >= GFX9;
4987
4988       if (ctx->options->chip_class >= GFX7) {
4989          aco_opcode op;
4990          switch (num_bytes) {
4991          case 4:
4992             op = global ? aco_opcode::global_load_dword : aco_opcode::flat_load_dword;
4993             break;
4994          case 8:
4995             op = global ? aco_opcode::global_load_dwordx2 : aco_opcode::flat_load_dwordx2;
4996             break;
4997          case 12:
4998             op = global ? aco_opcode::global_load_dwordx3 : aco_opcode::flat_load_dwordx3;
4999             break;
5000          case 16:
5001             op = global ? aco_opcode::global_load_dwordx4 : aco_opcode::flat_load_dwordx4;
5002             break;
5003          default:
5004             unreachable("load_global not implemented for this size.");
5005          }
5006
5007          aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 2, 1)};
5008          flat->operands[0] = Operand(addr);
5009          flat->operands[1] = Operand(s1);
5010          flat->glc = glc;
5011          flat->dlc = dlc;
5012          flat->barrier = barrier_buffer;
5013
5014          if (dst.type() == RegType::sgpr) {
5015             Temp vec = bld.tmp(RegType::vgpr, dst.size());
5016             flat->definitions[0] = Definition(vec);
5017             ctx->block->instructions.emplace_back(std::move(flat));
5018             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec);
5019          } else {
5020             flat->definitions[0] = Definition(dst);
5021             ctx->block->instructions.emplace_back(std::move(flat));
5022          }
5023          emit_split_vector(ctx, dst, num_components);
5024       } else {
5025          assert(ctx->options->chip_class == GFX6);
5026
5027          /* GFX6 doesn't support loading vec3, expand to vec4. */
5028          num_bytes = num_bytes == 12 ? 16 : num_bytes;
5029
5030          aco_opcode op;
5031          switch (num_bytes) {
5032          case 4:
5033             op = aco_opcode::buffer_load_dword;
5034             break;
5035          case 8:
5036             op = aco_opcode::buffer_load_dwordx2;
5037             break;
5038          case 16:
5039             op = aco_opcode::buffer_load_dwordx4;
5040             break;
5041          default:
5042             unreachable("load_global not implemented for this size.");
5043          }
5044
5045          Temp rsrc = get_gfx6_global_rsrc(bld, addr);
5046
5047          aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
5048          mubuf->operands[0] = Operand(rsrc);
5049          mubuf->operands[1] = addr.type() == RegType::vgpr ? Operand(addr) : Operand(v1);
5050          mubuf->operands[2] = Operand(0u);
5051          mubuf->glc = glc;
5052          mubuf->dlc = false;
5053          mubuf->offset = 0;
5054          mubuf->addr64 = addr.type() == RegType::vgpr;
5055          mubuf->disable_wqm = false;
5056          mubuf->barrier = barrier_buffer;
5057          aco_ptr<Instruction> instr = std::move(mubuf);
5058
5059          /* expand vector */
5060          if (dst.size() == 3) {
5061             Temp vec = bld.tmp(v4);
5062             instr->definitions[0] = Definition(vec);
5063             bld.insert(std::move(instr));
5064             emit_split_vector(ctx, vec, 4);
5065
5066             instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, 3, 1));
5067             instr->operands[0] = Operand(emit_extract_vector(ctx, vec, 0, v1));
5068             instr->operands[1] = Operand(emit_extract_vector(ctx, vec, 1, v1));
5069             instr->operands[2] = Operand(emit_extract_vector(ctx, vec, 2, v1));
5070          }
5071
5072          if (dst.type() == RegType::sgpr) {
5073             Temp vec = bld.tmp(RegType::vgpr, dst.size());
5074             instr->definitions[0] = Definition(vec);
5075             bld.insert(std::move(instr));
5076             expand_vector(ctx, vec, dst, num_components, (1 << num_components) - 1);
5077             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec);
5078          } else {
5079             instr->definitions[0] = Definition(dst);
5080             bld.insert(std::move(instr));
5081             emit_split_vector(ctx, dst, num_components);
5082          }
5083       }
5084    } else {
5085       switch (num_bytes) {
5086          case 4:
5087             op = aco_opcode::s_load_dword;
5088             break;
5089          case 8:
5090             op = aco_opcode::s_load_dwordx2;
5091             break;
5092          case 12:
5093          case 16:
5094             op = aco_opcode::s_load_dwordx4;
5095             break;
5096          default:
5097             unreachable("load_global not implemented for this size.");
5098       }
5099       aco_ptr<SMEM_instruction> load{create_instruction<SMEM_instruction>(op, Format::SMEM, 2, 1)};
5100       load->operands[0] = Operand(addr);
5101       load->operands[1] = Operand(0u);
5102       load->definitions[0] = Definition(dst);
5103       load->glc = glc;
5104       load->dlc = dlc;
5105       load->barrier = barrier_buffer;
5106       assert(ctx->options->chip_class >= GFX8 || !glc);
5107
5108       if (dst.size() == 3) {
5109          /* trim vector */
5110          Temp vec = bld.tmp(s4);
5111          load->definitions[0] = Definition(vec);
5112          ctx->block->instructions.emplace_back(std::move(load));
5113          emit_split_vector(ctx, vec, 4);
5114
5115          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
5116                     emit_extract_vector(ctx, vec, 0, s1),
5117                     emit_extract_vector(ctx, vec, 1, s1),
5118                     emit_extract_vector(ctx, vec, 2, s1));
5119       } else {
5120          ctx->block->instructions.emplace_back(std::move(load));
5121       }
5122    }
5123 }
5124
5125 void visit_store_global(isel_context *ctx, nir_intrinsic_instr *instr)
5126 {
5127    Builder bld(ctx->program, ctx->block);
5128    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
5129
5130    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5131    Temp addr = get_ssa_temp(ctx, instr->src[1].ssa);
5132
5133    if (ctx->options->chip_class >= GFX7)
5134       addr = as_vgpr(ctx, addr);
5135
5136    unsigned writemask = nir_intrinsic_write_mask(instr);
5137    while (writemask) {
5138       int start, count;
5139       u_bit_scan_consecutive_range(&writemask, &start, &count);
5140       if (count == 3 && ctx->options->chip_class == GFX6) {
5141          /* GFX6 doesn't support storing vec3, split it. */
5142          writemask |= 1u << (start + 2);
5143          count = 2;
5144       }
5145       unsigned num_bytes = count * elem_size_bytes;
5146
5147       Temp write_data = data;
5148       if (count != instr->num_components) {
5149          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
5150          for (int i = 0; i < count; i++)
5151             vec->operands[i] = Operand(emit_extract_vector(ctx, data, start + i, v1));
5152          write_data = bld.tmp(RegType::vgpr, count);
5153          vec->definitions[0] = Definition(write_data);
5154          ctx->block->instructions.emplace_back(std::move(vec));
5155       }
5156
5157       bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
5158       unsigned offset = start * elem_size_bytes;
5159
5160       if (ctx->options->chip_class >= GFX7) {
5161          if (offset > 0 && ctx->options->chip_class < GFX9) {
5162             Temp addr0 = bld.tmp(v1), addr1 = bld.tmp(v1);
5163             Temp new_addr0 = bld.tmp(v1), new_addr1 = bld.tmp(v1);
5164             Temp carry = bld.tmp(bld.lm);
5165             bld.pseudo(aco_opcode::p_split_vector, Definition(addr0), Definition(addr1), addr);
5166
5167             bld.vop2(aco_opcode::v_add_co_u32, Definition(new_addr0), bld.hint_vcc(Definition(carry)),
5168                      Operand(offset), addr0);
5169             bld.vop2(aco_opcode::v_addc_co_u32, Definition(new_addr1), bld.def(bld.lm),
5170                      Operand(0u), addr1,
5171                      carry).def(1).setHint(vcc);
5172
5173             addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), new_addr0, new_addr1);
5174
5175             offset = 0;
5176          }
5177
5178          bool global = ctx->options->chip_class >= GFX9;
5179          aco_opcode op;
5180          switch (num_bytes) {
5181          case 4:
5182             op = global ? aco_opcode::global_store_dword : aco_opcode::flat_store_dword;
5183             break;
5184          case 8:
5185             op = global ? aco_opcode::global_store_dwordx2 : aco_opcode::flat_store_dwordx2;
5186             break;
5187          case 12:
5188             op = global ? aco_opcode::global_store_dwordx3 : aco_opcode::flat_store_dwordx3;
5189             break;
5190          case 16:
5191             op = global ? aco_opcode::global_store_dwordx4 : aco_opcode::flat_store_dwordx4;
5192             break;
5193          default:
5194             unreachable("store_global not implemented for this size.");
5195          }
5196
5197          aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 3, 0)};
5198          flat->operands[0] = Operand(addr);
5199          flat->operands[1] = Operand(s1);
5200          flat->operands[2] = Operand(data);
5201          flat->glc = glc;
5202          flat->dlc = false;
5203          flat->offset = offset;
5204          flat->disable_wqm = true;
5205          flat->barrier = barrier_buffer;
5206          ctx->program->needs_exact = true;
5207          ctx->block->instructions.emplace_back(std::move(flat));
5208       } else {
5209          assert(ctx->options->chip_class == GFX6);
5210
5211          aco_opcode op;
5212          switch (num_bytes) {
5213          case 4:
5214             op = aco_opcode::buffer_store_dword;
5215             break;
5216          case 8:
5217             op = aco_opcode::buffer_store_dwordx2;
5218             break;
5219          case 16:
5220             op = aco_opcode::buffer_store_dwordx4;
5221             break;
5222          default:
5223             unreachable("store_global not implemented for this size.");
5224          }
5225
5226          Temp rsrc = get_gfx6_global_rsrc(bld, addr);
5227
5228          aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, 0)};
5229          mubuf->operands[0] = Operand(rsrc);
5230          mubuf->operands[1] = addr.type() == RegType::vgpr ? Operand(addr) : Operand(v1);
5231          mubuf->operands[2] = Operand(0u);
5232          mubuf->operands[3] = Operand(write_data);
5233          mubuf->glc = glc;
5234          mubuf->dlc = false;
5235          mubuf->offset = offset;
5236          mubuf->addr64 = addr.type() == RegType::vgpr;
5237          mubuf->disable_wqm = true;
5238          mubuf->barrier = barrier_buffer;
5239          ctx->program->needs_exact = true;
5240          ctx->block->instructions.emplace_back(std::move(mubuf));
5241       }
5242    }
5243 }
5244
5245 void visit_global_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
5246 {
5247    /* return the previous value if dest is ever used */
5248    bool return_previous = false;
5249    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
5250       return_previous = true;
5251       break;
5252    }
5253    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
5254       return_previous = true;
5255       break;
5256    }
5257
5258    Builder bld(ctx->program, ctx->block);
5259    Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
5260    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5261
5262    if (ctx->options->chip_class >= GFX7)
5263       addr = as_vgpr(ctx, addr);
5264
5265    if (instr->intrinsic == nir_intrinsic_global_atomic_comp_swap)
5266       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(RegType::vgpr, data.size() * 2),
5267                         get_ssa_temp(ctx, instr->src[2].ssa), data);
5268
5269    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5270
5271    aco_opcode op32, op64;
5272
5273    if (ctx->options->chip_class >= GFX7) {
5274       bool global = ctx->options->chip_class >= GFX9;
5275       switch (instr->intrinsic) {
5276          case nir_intrinsic_global_atomic_add:
5277             op32 = global ? aco_opcode::global_atomic_add : aco_opcode::flat_atomic_add;
5278             op64 = global ? aco_opcode::global_atomic_add_x2 : aco_opcode::flat_atomic_add_x2;
5279             break;
5280          case nir_intrinsic_global_atomic_imin:
5281             op32 = global ? aco_opcode::global_atomic_smin : aco_opcode::flat_atomic_smin;
5282             op64 = global ? aco_opcode::global_atomic_smin_x2 : aco_opcode::flat_atomic_smin_x2;
5283             break;
5284          case nir_intrinsic_global_atomic_umin:
5285             op32 = global ? aco_opcode::global_atomic_umin : aco_opcode::flat_atomic_umin;
5286             op64 = global ? aco_opcode::global_atomic_umin_x2 : aco_opcode::flat_atomic_umin_x2;
5287             break;
5288          case nir_intrinsic_global_atomic_imax:
5289             op32 = global ? aco_opcode::global_atomic_smax : aco_opcode::flat_atomic_smax;
5290             op64 = global ? aco_opcode::global_atomic_smax_x2 : aco_opcode::flat_atomic_smax_x2;
5291             break;
5292          case nir_intrinsic_global_atomic_umax:
5293             op32 = global ? aco_opcode::global_atomic_umax : aco_opcode::flat_atomic_umax;
5294             op64 = global ? aco_opcode::global_atomic_umax_x2 : aco_opcode::flat_atomic_umax_x2;
5295             break;
5296          case nir_intrinsic_global_atomic_and:
5297             op32 = global ? aco_opcode::global_atomic_and : aco_opcode::flat_atomic_and;
5298             op64 = global ? aco_opcode::global_atomic_and_x2 : aco_opcode::flat_atomic_and_x2;
5299             break;
5300          case nir_intrinsic_global_atomic_or:
5301             op32 = global ? aco_opcode::global_atomic_or : aco_opcode::flat_atomic_or;
5302             op64 = global ? aco_opcode::global_atomic_or_x2 : aco_opcode::flat_atomic_or_x2;
5303             break;
5304          case nir_intrinsic_global_atomic_xor:
5305             op32 = global ? aco_opcode::global_atomic_xor : aco_opcode::flat_atomic_xor;
5306             op64 = global ? aco_opcode::global_atomic_xor_x2 : aco_opcode::flat_atomic_xor_x2;
5307             break;
5308          case nir_intrinsic_global_atomic_exchange:
5309             op32 = global ? aco_opcode::global_atomic_swap : aco_opcode::flat_atomic_swap;
5310             op64 = global ? aco_opcode::global_atomic_swap_x2 : aco_opcode::flat_atomic_swap_x2;
5311             break;
5312          case nir_intrinsic_global_atomic_comp_swap:
5313             op32 = global ? aco_opcode::global_atomic_cmpswap : aco_opcode::flat_atomic_cmpswap;
5314             op64 = global ? aco_opcode::global_atomic_cmpswap_x2 : aco_opcode::flat_atomic_cmpswap_x2;
5315             break;
5316          default:
5317             unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
5318       }
5319
5320       aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
5321       aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 3, return_previous ? 1 : 0)};
5322       flat->operands[0] = Operand(addr);
5323       flat->operands[1] = Operand(s1);
5324       flat->operands[2] = Operand(data);
5325       if (return_previous)
5326          flat->definitions[0] = Definition(dst);
5327       flat->glc = return_previous;
5328       flat->dlc = false; /* Not needed for atomics */
5329       flat->offset = 0;
5330       flat->disable_wqm = true;
5331       flat->barrier = barrier_buffer;
5332       ctx->program->needs_exact = true;
5333       ctx->block->instructions.emplace_back(std::move(flat));
5334    } else {
5335       assert(ctx->options->chip_class == GFX6);
5336
5337       switch (instr->intrinsic) {
5338          case nir_intrinsic_global_atomic_add:
5339             op32 = aco_opcode::buffer_atomic_add;
5340             op64 = aco_opcode::buffer_atomic_add_x2;
5341             break;
5342          case nir_intrinsic_global_atomic_imin:
5343             op32 = aco_opcode::buffer_atomic_smin;
5344             op64 = aco_opcode::buffer_atomic_smin_x2;
5345             break;
5346          case nir_intrinsic_global_atomic_umin:
5347             op32 = aco_opcode::buffer_atomic_umin;
5348             op64 = aco_opcode::buffer_atomic_umin_x2;
5349             break;
5350          case nir_intrinsic_global_atomic_imax:
5351             op32 = aco_opcode::buffer_atomic_smax;
5352             op64 = aco_opcode::buffer_atomic_smax_x2;
5353             break;
5354          case nir_intrinsic_global_atomic_umax:
5355             op32 = aco_opcode::buffer_atomic_umax;
5356             op64 = aco_opcode::buffer_atomic_umax_x2;
5357             break;
5358          case nir_intrinsic_global_atomic_and:
5359             op32 = aco_opcode::buffer_atomic_and;
5360             op64 = aco_opcode::buffer_atomic_and_x2;
5361             break;
5362          case nir_intrinsic_global_atomic_or:
5363             op32 = aco_opcode::buffer_atomic_or;
5364             op64 = aco_opcode::buffer_atomic_or_x2;
5365             break;
5366          case nir_intrinsic_global_atomic_xor:
5367             op32 = aco_opcode::buffer_atomic_xor;
5368             op64 = aco_opcode::buffer_atomic_xor_x2;
5369             break;
5370          case nir_intrinsic_global_atomic_exchange:
5371             op32 = aco_opcode::buffer_atomic_swap;
5372             op64 = aco_opcode::buffer_atomic_swap_x2;
5373             break;
5374          case nir_intrinsic_global_atomic_comp_swap:
5375             op32 = aco_opcode::buffer_atomic_cmpswap;
5376             op64 = aco_opcode::buffer_atomic_cmpswap_x2;
5377             break;
5378          default:
5379             unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
5380       }
5381
5382       Temp rsrc = get_gfx6_global_rsrc(bld, addr);
5383
5384       aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
5385
5386       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, return_previous ? 1 : 0)};
5387       mubuf->operands[0] = Operand(rsrc);
5388       mubuf->operands[1] = addr.type() == RegType::vgpr ? Operand(addr) : Operand(v1);
5389       mubuf->operands[2] = Operand(0u);
5390       mubuf->operands[3] = Operand(data);
5391       if (return_previous)
5392          mubuf->definitions[0] = Definition(dst);
5393       mubuf->glc = return_previous;
5394       mubuf->dlc = false;
5395       mubuf->offset = 0;
5396       mubuf->addr64 = addr.type() == RegType::vgpr;
5397       mubuf->disable_wqm = true;
5398       mubuf->barrier = barrier_buffer;
5399       ctx->program->needs_exact = true;
5400       ctx->block->instructions.emplace_back(std::move(mubuf));
5401    }
5402 }
5403
5404 void emit_memory_barrier(isel_context *ctx, nir_intrinsic_instr *instr) {
5405    Builder bld(ctx->program, ctx->block);
5406    switch(instr->intrinsic) {
5407       case nir_intrinsic_group_memory_barrier:
5408       case nir_intrinsic_memory_barrier:
5409          bld.barrier(aco_opcode::p_memory_barrier_common);
5410          break;
5411       case nir_intrinsic_memory_barrier_buffer:
5412          bld.barrier(aco_opcode::p_memory_barrier_buffer);
5413          break;
5414       case nir_intrinsic_memory_barrier_image:
5415          bld.barrier(aco_opcode::p_memory_barrier_image);
5416          break;
5417       case nir_intrinsic_memory_barrier_tcs_patch:
5418       case nir_intrinsic_memory_barrier_shared:
5419          bld.barrier(aco_opcode::p_memory_barrier_shared);
5420          break;
5421       default:
5422          unreachable("Unimplemented memory barrier intrinsic");
5423          break;
5424    }
5425 }
5426
5427 void visit_load_shared(isel_context *ctx, nir_intrinsic_instr *instr)
5428 {
5429    // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
5430    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5431    assert(instr->dest.ssa.bit_size >= 32 && "Bitsize not supported in load_shared.");
5432    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5433    Builder bld(ctx->program, ctx->block);
5434
5435    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
5436    unsigned align = nir_intrinsic_align_mul(instr) ? nir_intrinsic_align(instr) : elem_size_bytes;
5437    load_lds(ctx, elem_size_bytes, dst, address, nir_intrinsic_base(instr), align);
5438 }
5439
5440 void visit_store_shared(isel_context *ctx, nir_intrinsic_instr *instr)
5441 {
5442    unsigned writemask = nir_intrinsic_write_mask(instr);
5443    Temp data = get_ssa_temp(ctx, instr->src[0].ssa);
5444    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5445    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
5446    assert(elem_size_bytes >= 4 && "Only 32bit & 64bit store_shared currently supported.");
5447
5448    unsigned align = nir_intrinsic_align_mul(instr) ? nir_intrinsic_align(instr) : elem_size_bytes;
5449    store_lds(ctx, elem_size_bytes, data, writemask, address, nir_intrinsic_base(instr), align);
5450 }
5451
5452 void visit_shared_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
5453 {
5454    unsigned offset = nir_intrinsic_base(instr);
5455    Operand m = load_lds_size_m0(ctx);
5456    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5457    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5458
5459    unsigned num_operands = 3;
5460    aco_opcode op32, op64, op32_rtn, op64_rtn;
5461    switch(instr->intrinsic) {
5462       case nir_intrinsic_shared_atomic_add:
5463          op32 = aco_opcode::ds_add_u32;
5464          op64 = aco_opcode::ds_add_u64;
5465          op32_rtn = aco_opcode::ds_add_rtn_u32;
5466          op64_rtn = aco_opcode::ds_add_rtn_u64;
5467          break;
5468       case nir_intrinsic_shared_atomic_imin:
5469          op32 = aco_opcode::ds_min_i32;
5470          op64 = aco_opcode::ds_min_i64;
5471          op32_rtn = aco_opcode::ds_min_rtn_i32;
5472          op64_rtn = aco_opcode::ds_min_rtn_i64;
5473          break;
5474       case nir_intrinsic_shared_atomic_umin:
5475          op32 = aco_opcode::ds_min_u32;
5476          op64 = aco_opcode::ds_min_u64;
5477          op32_rtn = aco_opcode::ds_min_rtn_u32;
5478          op64_rtn = aco_opcode::ds_min_rtn_u64;
5479          break;
5480       case nir_intrinsic_shared_atomic_imax:
5481          op32 = aco_opcode::ds_max_i32;
5482          op64 = aco_opcode::ds_max_i64;
5483          op32_rtn = aco_opcode::ds_max_rtn_i32;
5484          op64_rtn = aco_opcode::ds_max_rtn_i64;
5485          break;
5486       case nir_intrinsic_shared_atomic_umax:
5487          op32 = aco_opcode::ds_max_u32;
5488          op64 = aco_opcode::ds_max_u64;
5489          op32_rtn = aco_opcode::ds_max_rtn_u32;
5490          op64_rtn = aco_opcode::ds_max_rtn_u64;
5491          break;
5492       case nir_intrinsic_shared_atomic_and:
5493          op32 = aco_opcode::ds_and_b32;
5494          op64 = aco_opcode::ds_and_b64;
5495          op32_rtn = aco_opcode::ds_and_rtn_b32;
5496          op64_rtn = aco_opcode::ds_and_rtn_b64;
5497          break;
5498       case nir_intrinsic_shared_atomic_or:
5499          op32 = aco_opcode::ds_or_b32;
5500          op64 = aco_opcode::ds_or_b64;
5501          op32_rtn = aco_opcode::ds_or_rtn_b32;
5502          op64_rtn = aco_opcode::ds_or_rtn_b64;
5503          break;
5504       case nir_intrinsic_shared_atomic_xor:
5505          op32 = aco_opcode::ds_xor_b32;
5506          op64 = aco_opcode::ds_xor_b64;
5507          op32_rtn = aco_opcode::ds_xor_rtn_b32;
5508          op64_rtn = aco_opcode::ds_xor_rtn_b64;
5509          break;
5510       case nir_intrinsic_shared_atomic_exchange:
5511          op32 = aco_opcode::ds_write_b32;
5512          op64 = aco_opcode::ds_write_b64;
5513          op32_rtn = aco_opcode::ds_wrxchg_rtn_b32;
5514          op64_rtn = aco_opcode::ds_wrxchg2_rtn_b64;
5515          break;
5516       case nir_intrinsic_shared_atomic_comp_swap:
5517          op32 = aco_opcode::ds_cmpst_b32;
5518          op64 = aco_opcode::ds_cmpst_b64;
5519          op32_rtn = aco_opcode::ds_cmpst_rtn_b32;
5520          op64_rtn = aco_opcode::ds_cmpst_rtn_b64;
5521          num_operands = 4;
5522          break;
5523       default:
5524          unreachable("Unhandled shared atomic intrinsic");
5525    }
5526
5527    /* return the previous value if dest is ever used */
5528    bool return_previous = false;
5529    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
5530       return_previous = true;
5531       break;
5532    }
5533    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
5534       return_previous = true;
5535       break;
5536    }
5537
5538    aco_opcode op;
5539    if (data.size() == 1) {
5540       assert(instr->dest.ssa.bit_size == 32);
5541       op = return_previous ? op32_rtn : op32;
5542    } else {
5543       assert(instr->dest.ssa.bit_size == 64);
5544       op = return_previous ? op64_rtn : op64;
5545    }
5546
5547    if (offset > 65535) {
5548       Builder bld(ctx->program, ctx->block);
5549       address = bld.vadd32(bld.def(v1), Operand(offset), address);
5550       offset = 0;
5551    }
5552
5553    aco_ptr<DS_instruction> ds;
5554    ds.reset(create_instruction<DS_instruction>(op, Format::DS, num_operands, return_previous ? 1 : 0));
5555    ds->operands[0] = Operand(address);
5556    ds->operands[1] = Operand(data);
5557    if (num_operands == 4)
5558       ds->operands[2] = Operand(get_ssa_temp(ctx, instr->src[2].ssa));
5559    ds->operands[num_operands - 1] = m;
5560    ds->offset0 = offset;
5561    if (return_previous)
5562       ds->definitions[0] = Definition(get_ssa_temp(ctx, &instr->dest.ssa));
5563    ctx->block->instructions.emplace_back(std::move(ds));
5564 }
5565
5566 Temp get_scratch_resource(isel_context *ctx)
5567 {
5568    Builder bld(ctx->program, ctx->block);
5569    Temp scratch_addr = ctx->program->private_segment_buffer;
5570    if (ctx->stage != compute_cs)
5571       scratch_addr = bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), scratch_addr, Operand(0u));
5572
5573    uint32_t rsrc_conf = S_008F0C_ADD_TID_ENABLE(1) |
5574                         S_008F0C_INDEX_STRIDE(ctx->program->wave_size == 64 ? 3 : 2);;
5575
5576    if (ctx->program->chip_class >= GFX10) {
5577       rsrc_conf |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
5578                    S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
5579                    S_008F0C_RESOURCE_LEVEL(1);
5580    } else if (ctx->program->chip_class <= GFX7) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
5581       rsrc_conf |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5582                    S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
5583    }
5584
5585    /* older generations need element size = 16 bytes. element size removed in GFX9 */
5586    if (ctx->program->chip_class <= GFX8)
5587       rsrc_conf |= S_008F0C_ELEMENT_SIZE(3);
5588
5589    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), scratch_addr, Operand(-1u), Operand(rsrc_conf));
5590 }
5591
5592 void visit_load_scratch(isel_context *ctx, nir_intrinsic_instr *instr) {
5593    assert(instr->dest.ssa.bit_size == 32 || instr->dest.ssa.bit_size == 64);
5594    Builder bld(ctx->program, ctx->block);
5595    Temp rsrc = get_scratch_resource(ctx);
5596    Temp offset = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5597    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5598
5599    aco_opcode op;
5600    switch (dst.size()) {
5601       case 1:
5602          op = aco_opcode::buffer_load_dword;
5603          break;
5604       case 2:
5605          op = aco_opcode::buffer_load_dwordx2;
5606          break;
5607       case 3:
5608          op = aco_opcode::buffer_load_dwordx3;
5609          break;
5610       case 4:
5611          op = aco_opcode::buffer_load_dwordx4;
5612          break;
5613       case 6:
5614       case 8: {
5615          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
5616          Temp lower = bld.mubuf(aco_opcode::buffer_load_dwordx4,
5617                                 bld.def(v4), rsrc, offset,
5618                                 ctx->program->scratch_offset, 0, true);
5619          Temp upper = bld.mubuf(dst.size() == 6 ? aco_opcode::buffer_load_dwordx2 :
5620                                                   aco_opcode::buffer_load_dwordx4,
5621                                 dst.size() == 6 ? bld.def(v2) : bld.def(v4),
5622                                 rsrc, offset, ctx->program->scratch_offset, 16, true);
5623          emit_split_vector(ctx, lower, 2);
5624          elems[0] = emit_extract_vector(ctx, lower, 0, v2);
5625          elems[1] = emit_extract_vector(ctx, lower, 1, v2);
5626          if (dst.size() == 8) {
5627             emit_split_vector(ctx, upper, 2);
5628             elems[2] = emit_extract_vector(ctx, upper, 0, v2);
5629             elems[3] = emit_extract_vector(ctx, upper, 1, v2);
5630          } else {
5631             elems[2] = upper;
5632          }
5633
5634          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector,
5635                                                                          Format::PSEUDO, dst.size() / 2, 1)};
5636          for (unsigned i = 0; i < dst.size() / 2; i++)
5637             vec->operands[i] = Operand(elems[i]);
5638          vec->definitions[0] = Definition(dst);
5639          bld.insert(std::move(vec));
5640          ctx->allocated_vec.emplace(dst.id(), elems);
5641          return;
5642       }
5643       default:
5644          unreachable("Wrong dst size for nir_intrinsic_load_scratch");
5645    }
5646
5647    bld.mubuf(op, Definition(dst), rsrc, offset, ctx->program->scratch_offset, 0, true);
5648    emit_split_vector(ctx, dst, instr->num_components);
5649 }
5650
5651 void visit_store_scratch(isel_context *ctx, nir_intrinsic_instr *instr) {
5652    assert(instr->src[0].ssa->bit_size == 32 || instr->src[0].ssa->bit_size == 64);
5653    Builder bld(ctx->program, ctx->block);
5654    Temp rsrc = get_scratch_resource(ctx);
5655    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5656    Temp offset = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5657
5658    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
5659    unsigned writemask = nir_intrinsic_write_mask(instr);
5660
5661    while (writemask) {
5662       int start, count;
5663       u_bit_scan_consecutive_range(&writemask, &start, &count);
5664       int num_bytes = count * elem_size_bytes;
5665
5666       if (num_bytes > 16) {
5667          assert(elem_size_bytes == 8);
5668          writemask |= (((count - 2) << 1) - 1) << (start + 2);
5669          count = 2;
5670          num_bytes = 16;
5671       }
5672
5673       // TODO: check alignment of sub-dword stores
5674       // TODO: split 3 bytes. there is no store instruction for that
5675
5676       Temp write_data;
5677       if (count != instr->num_components) {
5678          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
5679          for (int i = 0; i < count; i++) {
5680             Temp elem = emit_extract_vector(ctx, data, start + i, RegClass(RegType::vgpr, elem_size_bytes / 4));
5681             vec->operands[i] = Operand(elem);
5682          }
5683          write_data = bld.tmp(RegClass(RegType::vgpr, count * elem_size_bytes / 4));
5684          vec->definitions[0] = Definition(write_data);
5685          ctx->block->instructions.emplace_back(std::move(vec));
5686       } else {
5687          write_data = data;
5688       }
5689
5690       aco_opcode op;
5691       switch (num_bytes) {
5692          case 4:
5693             op = aco_opcode::buffer_store_dword;
5694             break;
5695          case 8:
5696             op = aco_opcode::buffer_store_dwordx2;
5697             break;
5698          case 12:
5699             op = aco_opcode::buffer_store_dwordx3;
5700             break;
5701          case 16:
5702             op = aco_opcode::buffer_store_dwordx4;
5703             break;
5704          default:
5705             unreachable("Invalid data size for nir_intrinsic_store_scratch.");
5706       }
5707
5708       bld.mubuf(op, rsrc, offset, ctx->program->scratch_offset, write_data, start * elem_size_bytes, true);
5709    }
5710 }
5711
5712 void visit_load_sample_mask_in(isel_context *ctx, nir_intrinsic_instr *instr) {
5713    uint8_t log2_ps_iter_samples;
5714    if (ctx->program->info->ps.force_persample) {
5715       log2_ps_iter_samples =
5716          util_logbase2(ctx->options->key.fs.num_samples);
5717    } else {
5718       log2_ps_iter_samples = ctx->options->key.fs.log2_ps_iter_samples;
5719    }
5720
5721    /* The bit pattern matches that used by fixed function fragment
5722     * processing. */
5723    static const unsigned ps_iter_masks[] = {
5724       0xffff, /* not used */
5725       0x5555,
5726       0x1111,
5727       0x0101,
5728       0x0001,
5729    };
5730    assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
5731
5732    Builder bld(ctx->program, ctx->block);
5733
5734    Temp sample_id = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1),
5735                              get_arg(ctx, ctx->args->ac.ancillary), Operand(8u), Operand(4u));
5736    Temp ps_iter_mask = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(ps_iter_masks[log2_ps_iter_samples]));
5737    Temp mask = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), sample_id, ps_iter_mask);
5738    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5739    bld.vop2(aco_opcode::v_and_b32, Definition(dst), mask, get_arg(ctx, ctx->args->ac.sample_coverage));
5740 }
5741
5742 void visit_emit_vertex_with_counter(isel_context *ctx, nir_intrinsic_instr *instr) {
5743    Builder bld(ctx->program, ctx->block);
5744
5745    unsigned stream = nir_intrinsic_stream_id(instr);
5746    Temp next_vertex = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5747    next_vertex = bld.v_mul_imm(bld.def(v1), next_vertex, 4u);
5748    nir_const_value *next_vertex_cv = nir_src_as_const_value(instr->src[0]);
5749
5750    /* get GSVS ring */
5751    Temp gsvs_ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_GSVS_GS * 16u));
5752
5753    unsigned num_components =
5754       ctx->program->info->gs.num_stream_output_components[stream];
5755    assert(num_components);
5756
5757    unsigned stride = 4u * num_components * ctx->shader->info.gs.vertices_out;
5758    unsigned stream_offset = 0;
5759    for (unsigned i = 0; i < stream; i++) {
5760       unsigned prev_stride = 4u * ctx->program->info->gs.num_stream_output_components[i] * ctx->shader->info.gs.vertices_out;
5761       stream_offset += prev_stride * ctx->program->wave_size;
5762    }
5763
5764    /* Limit on the stride field for <= GFX7. */
5765    assert(stride < (1 << 14));
5766
5767    Temp gsvs_dwords[4];
5768    for (unsigned i = 0; i < 4; i++)
5769       gsvs_dwords[i] = bld.tmp(s1);
5770    bld.pseudo(aco_opcode::p_split_vector,
5771               Definition(gsvs_dwords[0]),
5772               Definition(gsvs_dwords[1]),
5773               Definition(gsvs_dwords[2]),
5774               Definition(gsvs_dwords[3]),
5775               gsvs_ring);
5776
5777    if (stream_offset) {
5778       Temp stream_offset_tmp = bld.copy(bld.def(s1), Operand(stream_offset));
5779
5780       Temp carry = bld.tmp(s1);
5781       gsvs_dwords[0] = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), gsvs_dwords[0], stream_offset_tmp);
5782       gsvs_dwords[1] = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), gsvs_dwords[1], Operand(0u), bld.scc(carry));
5783    }
5784
5785    gsvs_dwords[1] = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), gsvs_dwords[1], Operand(S_008F04_STRIDE(stride)));
5786    gsvs_dwords[2] = bld.copy(bld.def(s1), Operand((uint32_t)ctx->program->wave_size));
5787
5788    gsvs_ring = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
5789                           gsvs_dwords[0], gsvs_dwords[1], gsvs_dwords[2], gsvs_dwords[3]);
5790
5791    unsigned offset = 0;
5792    for (unsigned i = 0; i <= VARYING_SLOT_VAR31; i++) {
5793       if (ctx->program->info->gs.output_streams[i] != stream)
5794          continue;
5795
5796       for (unsigned j = 0; j < 4; j++) {
5797          if (!(ctx->program->info->gs.output_usage_mask[i] & (1 << j)))
5798             continue;
5799
5800          if (ctx->outputs.mask[i] & (1 << j)) {
5801             Operand vaddr_offset = next_vertex_cv ? Operand(v1) : Operand(next_vertex);
5802             unsigned const_offset = (offset + (next_vertex_cv ? next_vertex_cv->u32 : 0u)) * 4u;
5803             if (const_offset >= 4096u) {
5804                if (vaddr_offset.isUndefined())
5805                   vaddr_offset = bld.copy(bld.def(v1), Operand(const_offset / 4096u * 4096u));
5806                else
5807                   vaddr_offset = bld.vadd32(bld.def(v1), Operand(const_offset / 4096u * 4096u), vaddr_offset);
5808                const_offset %= 4096u;
5809             }
5810
5811             aco_ptr<MTBUF_instruction> mtbuf{create_instruction<MTBUF_instruction>(aco_opcode::tbuffer_store_format_x, Format::MTBUF, 4, 0)};
5812             mtbuf->operands[0] = Operand(gsvs_ring);
5813             mtbuf->operands[1] = vaddr_offset;
5814             mtbuf->operands[2] = Operand(get_arg(ctx, ctx->args->gs2vs_offset));
5815             mtbuf->operands[3] = Operand(ctx->outputs.outputs[i][j]);
5816             mtbuf->offen = !vaddr_offset.isUndefined();
5817             mtbuf->dfmt = V_008F0C_BUF_DATA_FORMAT_32;
5818             mtbuf->nfmt = V_008F0C_BUF_NUM_FORMAT_UINT;
5819             mtbuf->offset = const_offset;
5820             mtbuf->glc = true;
5821             mtbuf->slc = true;
5822             mtbuf->barrier = barrier_gs_data;
5823             mtbuf->can_reorder = true;
5824             bld.insert(std::move(mtbuf));
5825          }
5826
5827          offset += ctx->shader->info.gs.vertices_out;
5828       }
5829
5830       /* outputs for the next vertex are undefined and keeping them around can
5831        * create invalid IR with control flow */
5832       ctx->outputs.mask[i] = 0;
5833    }
5834
5835    bld.sopp(aco_opcode::s_sendmsg, bld.m0(ctx->gs_wave_id), -1, sendmsg_gs(false, true, stream));
5836 }
5837
5838 Temp emit_boolean_reduce(isel_context *ctx, nir_op op, unsigned cluster_size, Temp src)
5839 {
5840    Builder bld(ctx->program, ctx->block);
5841
5842    if (cluster_size == 1) {
5843       return src;
5844    } if (op == nir_op_iand && cluster_size == 4) {
5845       //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
5846       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src);
5847       return bld.sop1(Builder::s_not, bld.def(bld.lm), bld.def(s1, scc),
5848                       bld.sop1(Builder::s_wqm, bld.def(bld.lm), bld.def(s1, scc), tmp));
5849    } else if (op == nir_op_ior && cluster_size == 4) {
5850       //subgroupClusteredOr(val, 4) -> wqm(val & exec)
5851       return bld.sop1(Builder::s_wqm, bld.def(bld.lm), bld.def(s1, scc),
5852                       bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm)));
5853    } else if (op == nir_op_iand && cluster_size == ctx->program->wave_size) {
5854       //subgroupAnd(val) -> (exec & ~val) == 0
5855       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src).def(1).getTemp();
5856       Temp cond = bool_to_vector_condition(ctx, emit_wqm(ctx, tmp));
5857       return bld.sop1(Builder::s_not, bld.def(bld.lm), bld.def(s1, scc), cond);
5858    } else if (op == nir_op_ior && cluster_size == ctx->program->wave_size) {
5859       //subgroupOr(val) -> (val & exec) != 0
5860       Temp tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm)).def(1).getTemp();
5861       return bool_to_vector_condition(ctx, tmp);
5862    } else if (op == nir_op_ixor && cluster_size == ctx->program->wave_size) {
5863       //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
5864       Temp tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
5865       tmp = bld.sop1(Builder::s_bcnt1_i32, bld.def(s1), bld.def(s1, scc), tmp);
5866       tmp = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), tmp, Operand(1u)).def(1).getTemp();
5867       return bool_to_vector_condition(ctx, tmp);
5868    } else {
5869       //subgroupClustered{And,Or,Xor}(val, n) ->
5870       //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ;  just v_mbcnt_lo_u32_b32 on wave32
5871       //cluster_offset = ~(n - 1) & lane_id
5872       //cluster_mask = ((1 << n) - 1)
5873       //subgroupClusteredAnd():
5874       //   return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
5875       //subgroupClusteredOr():
5876       //   return ((val & exec) >> cluster_offset) & cluster_mask != 0
5877       //subgroupClusteredXor():
5878       //   return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
5879       Temp lane_id = emit_mbcnt(ctx, bld.def(v1));
5880       Temp cluster_offset = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(~uint32_t(cluster_size - 1)), lane_id);
5881
5882       Temp tmp;
5883       if (op == nir_op_iand)
5884          tmp = bld.sop2(Builder::s_orn2, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
5885       else
5886          tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
5887
5888       uint32_t cluster_mask = cluster_size == 32 ? -1 : (1u << cluster_size) - 1u;
5889
5890       if (ctx->program->chip_class <= GFX7)
5891          tmp = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), tmp, cluster_offset);
5892       else if (ctx->program->wave_size == 64)
5893          tmp = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), cluster_offset, tmp);
5894       else
5895          tmp = bld.vop2_e64(aco_opcode::v_lshrrev_b32, bld.def(v1), cluster_offset, tmp);
5896       tmp = emit_extract_vector(ctx, tmp, 0, v1);
5897       if (cluster_mask != 0xffffffff)
5898          tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(cluster_mask), tmp);
5899
5900       Definition cmp_def = Definition();
5901       if (op == nir_op_iand) {
5902          cmp_def = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm), Operand(cluster_mask), tmp).def(0);
5903       } else if (op == nir_op_ior) {
5904          cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp).def(0);
5905       } else if (op == nir_op_ixor) {
5906          tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u),
5907                         bld.vop3(aco_opcode::v_bcnt_u32_b32, bld.def(v1), tmp, Operand(0u)));
5908          cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp).def(0);
5909       }
5910       cmp_def.setHint(vcc);
5911       return cmp_def.getTemp();
5912    }
5913 }
5914
5915 Temp emit_boolean_exclusive_scan(isel_context *ctx, nir_op op, Temp src)
5916 {
5917    Builder bld(ctx->program, ctx->block);
5918
5919    //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
5920    //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
5921    //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
5922    Temp tmp;
5923    if (op == nir_op_iand)
5924       tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src);
5925    else
5926       tmp = bld.sop2(Builder::s_and, bld.def(s2), bld.def(s1, scc), src, Operand(exec, bld.lm));
5927
5928    Builder::Result lohi = bld.pseudo(aco_opcode::p_split_vector, bld.def(s1), bld.def(s1), tmp);
5929    Temp lo = lohi.def(0).getTemp();
5930    Temp hi = lohi.def(1).getTemp();
5931    Temp mbcnt = emit_mbcnt(ctx, bld.def(v1), Operand(lo), Operand(hi));
5932
5933    Definition cmp_def = Definition();
5934    if (op == nir_op_iand)
5935       cmp_def = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm), Operand(0u), mbcnt).def(0);
5936    else if (op == nir_op_ior)
5937       cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), mbcnt).def(0);
5938    else if (op == nir_op_ixor)
5939       cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u),
5940                          bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u), mbcnt)).def(0);
5941    cmp_def.setHint(vcc);
5942    return cmp_def.getTemp();
5943 }
5944
5945 Temp emit_boolean_inclusive_scan(isel_context *ctx, nir_op op, Temp src)
5946 {
5947    Builder bld(ctx->program, ctx->block);
5948
5949    //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
5950    //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
5951    //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
5952    Temp tmp = emit_boolean_exclusive_scan(ctx, op, src);
5953    if (op == nir_op_iand)
5954       return bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
5955    else if (op == nir_op_ior)
5956       return bld.sop2(Builder::s_or, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
5957    else if (op == nir_op_ixor)
5958       return bld.sop2(Builder::s_xor, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
5959
5960    assert(false);
5961    return Temp();
5962 }
5963
5964 void emit_uniform_subgroup(isel_context *ctx, nir_intrinsic_instr *instr, Temp src)
5965 {
5966    Builder bld(ctx->program, ctx->block);
5967    Definition dst(get_ssa_temp(ctx, &instr->dest.ssa));
5968    if (src.regClass().type() == RegType::vgpr) {
5969       bld.pseudo(aco_opcode::p_as_uniform, dst, src);
5970    } else if (src.regClass() == s1) {
5971       bld.sop1(aco_opcode::s_mov_b32, dst, src);
5972    } else if (src.regClass() == s2) {
5973       bld.sop1(aco_opcode::s_mov_b64, dst, src);
5974    } else {
5975       fprintf(stderr, "Unimplemented NIR instr bit size: ");
5976       nir_print_instr(&instr->instr, stderr);
5977       fprintf(stderr, "\n");
5978    }
5979 }
5980
5981 void emit_interp_center(isel_context *ctx, Temp dst, Temp pos1, Temp pos2)
5982 {
5983    Builder bld(ctx->program, ctx->block);
5984    Temp persp_center = get_arg(ctx, ctx->args->ac.persp_center);
5985    Temp p1 = emit_extract_vector(ctx, persp_center, 0, v1);
5986    Temp p2 = emit_extract_vector(ctx, persp_center, 1, v1);
5987
5988    Temp ddx_1, ddx_2, ddy_1, ddy_2;
5989    uint32_t dpp_ctrl0 = dpp_quad_perm(0, 0, 0, 0);
5990    uint32_t dpp_ctrl1 = dpp_quad_perm(1, 1, 1, 1);
5991    uint32_t dpp_ctrl2 = dpp_quad_perm(2, 2, 2, 2);
5992
5993    /* Build DD X/Y */
5994    if (ctx->program->chip_class >= GFX8) {
5995       Temp tl_1 = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), p1, dpp_ctrl0);
5996       ddx_1 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p1, tl_1, dpp_ctrl1);
5997       ddy_1 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p1, tl_1, dpp_ctrl2);
5998       Temp tl_2 = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), p2, dpp_ctrl0);
5999       ddx_2 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p2, tl_2, dpp_ctrl1);
6000       ddy_2 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p2, tl_2, dpp_ctrl2);
6001    } else {
6002       Temp tl_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl0);
6003       ddx_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl1);
6004       ddx_1 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddx_1, tl_1);
6005       ddx_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl2);
6006       ddx_2 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddx_2, tl_1);
6007       Temp tl_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl0);
6008       ddy_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl1);
6009       ddy_1 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddy_1, tl_2);
6010       ddy_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl2);
6011       ddy_2 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddy_2, tl_2);
6012    }
6013
6014    /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
6015    Temp tmp1 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddx_1, pos1, p1);
6016    Temp tmp2 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddx_2, pos1, p2);
6017    tmp1 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddy_1, pos2, tmp1);
6018    tmp2 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddy_2, pos2, tmp2);
6019    Temp wqm1 = bld.tmp(v1);
6020    emit_wqm(ctx, tmp1, wqm1, true);
6021    Temp wqm2 = bld.tmp(v1);
6022    emit_wqm(ctx, tmp2, wqm2, true);
6023    bld.pseudo(aco_opcode::p_create_vector, Definition(dst), wqm1, wqm2);
6024    return;
6025 }
6026
6027 void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr)
6028 {
6029    Builder bld(ctx->program, ctx->block);
6030    switch(instr->intrinsic) {
6031    case nir_intrinsic_load_barycentric_sample:
6032    case nir_intrinsic_load_barycentric_pixel:
6033    case nir_intrinsic_load_barycentric_centroid: {
6034       glsl_interp_mode mode = (glsl_interp_mode)nir_intrinsic_interp_mode(instr);
6035       Temp bary = Temp(0, s2);
6036       switch (mode) {
6037       case INTERP_MODE_SMOOTH:
6038       case INTERP_MODE_NONE:
6039          if (instr->intrinsic == nir_intrinsic_load_barycentric_pixel)
6040             bary = get_arg(ctx, ctx->args->ac.persp_center);
6041          else if (instr->intrinsic == nir_intrinsic_load_barycentric_centroid)
6042             bary = ctx->persp_centroid;
6043          else if (instr->intrinsic == nir_intrinsic_load_barycentric_sample)
6044             bary = get_arg(ctx, ctx->args->ac.persp_sample);
6045          break;
6046       case INTERP_MODE_NOPERSPECTIVE:
6047          if (instr->intrinsic == nir_intrinsic_load_barycentric_pixel)
6048             bary = get_arg(ctx, ctx->args->ac.linear_center);
6049          else if (instr->intrinsic == nir_intrinsic_load_barycentric_centroid)
6050             bary = ctx->linear_centroid;
6051          else if (instr->intrinsic == nir_intrinsic_load_barycentric_sample)
6052             bary = get_arg(ctx, ctx->args->ac.linear_sample);
6053          break;
6054       default:
6055          break;
6056       }
6057       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6058       Temp p1 = emit_extract_vector(ctx, bary, 0, v1);
6059       Temp p2 = emit_extract_vector(ctx, bary, 1, v1);
6060       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
6061                  Operand(p1), Operand(p2));
6062       emit_split_vector(ctx, dst, 2);
6063       break;
6064    }
6065    case nir_intrinsic_load_barycentric_model: {
6066       Temp model = get_arg(ctx, ctx->args->ac.pull_model);
6067
6068       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6069       Temp p1 = emit_extract_vector(ctx, model, 0, v1);
6070       Temp p2 = emit_extract_vector(ctx, model, 1, v1);
6071       Temp p3 = emit_extract_vector(ctx, model, 2, v1);
6072       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
6073                  Operand(p1), Operand(p2), Operand(p3));
6074       emit_split_vector(ctx, dst, 3);
6075       break;
6076    }
6077    case nir_intrinsic_load_barycentric_at_sample: {
6078       uint32_t sample_pos_offset = RING_PS_SAMPLE_POSITIONS * 16;
6079       switch (ctx->options->key.fs.num_samples) {
6080          case 2: sample_pos_offset += 1 << 3; break;
6081          case 4: sample_pos_offset += 3 << 3; break;
6082          case 8: sample_pos_offset += 7 << 3; break;
6083          default: break;
6084       }
6085       Temp sample_pos;
6086       Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
6087       nir_const_value* const_addr = nir_src_as_const_value(instr->src[0]);
6088       Temp private_segment_buffer = ctx->program->private_segment_buffer;
6089       if (addr.type() == RegType::sgpr) {
6090          Operand offset;
6091          if (const_addr) {
6092             sample_pos_offset += const_addr->u32 << 3;
6093             offset = Operand(sample_pos_offset);
6094          } else if (ctx->options->chip_class >= GFX9) {
6095             offset = bld.sop2(aco_opcode::s_lshl3_add_u32, bld.def(s1), bld.def(s1, scc), addr, Operand(sample_pos_offset));
6096          } else {
6097             offset = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), addr, Operand(3u));
6098             offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), addr, Operand(sample_pos_offset));
6099          }
6100
6101          Operand off = bld.copy(bld.def(s1), Operand(offset));
6102          sample_pos = bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), private_segment_buffer, off);
6103
6104       } else if (ctx->options->chip_class >= GFX9) {
6105          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
6106          sample_pos = bld.global(aco_opcode::global_load_dwordx2, bld.def(v2), addr, private_segment_buffer, sample_pos_offset);
6107       } else if (ctx->options->chip_class >= GFX7) {
6108          /* addr += private_segment_buffer + sample_pos_offset */
6109          Temp tmp0 = bld.tmp(s1);
6110          Temp tmp1 = bld.tmp(s1);
6111          bld.pseudo(aco_opcode::p_split_vector, Definition(tmp0), Definition(tmp1), private_segment_buffer);
6112          Definition scc_tmp = bld.def(s1, scc);
6113          tmp0 = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), scc_tmp, tmp0, Operand(sample_pos_offset));
6114          tmp1 = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), tmp1, Operand(0u), bld.scc(scc_tmp.getTemp()));
6115          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
6116          Temp pck0 = bld.tmp(v1);
6117          Temp carry = bld.vadd32(Definition(pck0), tmp0, addr, true).def(1).getTemp();
6118          tmp1 = as_vgpr(ctx, tmp1);
6119          Temp pck1 = bld.vop2_e64(aco_opcode::v_addc_co_u32, bld.def(v1), bld.hint_vcc(bld.def(bld.lm)), tmp1, Operand(0u), carry);
6120          addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), pck0, pck1);
6121
6122          /* sample_pos = flat_load_dwordx2 addr */
6123          sample_pos = bld.flat(aco_opcode::flat_load_dwordx2, bld.def(v2), addr, Operand(s1));
6124       } else {
6125          assert(ctx->options->chip_class == GFX6);
6126
6127          uint32_t rsrc_conf = S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
6128                               S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
6129          Temp rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), private_segment_buffer, Operand(0u), Operand(rsrc_conf));
6130
6131          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
6132          addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), addr, Operand(0u));
6133
6134          sample_pos = bld.tmp(v2);
6135
6136          aco_ptr<MUBUF_instruction> load{create_instruction<MUBUF_instruction>(aco_opcode::buffer_load_dwordx2, Format::MUBUF, 3, 1)};
6137          load->definitions[0] = Definition(sample_pos);
6138          load->operands[0] = Operand(rsrc);
6139          load->operands[1] = Operand(addr);
6140          load->operands[2] = Operand(0u);
6141          load->offset = sample_pos_offset;
6142          load->offen = 0;
6143          load->addr64 = true;
6144          load->glc = false;
6145          load->dlc = false;
6146          load->disable_wqm = false;
6147          load->barrier = barrier_none;
6148          load->can_reorder = true;
6149          ctx->block->instructions.emplace_back(std::move(load));
6150       }
6151
6152       /* sample_pos -= 0.5 */
6153       Temp pos1 = bld.tmp(RegClass(sample_pos.type(), 1));
6154       Temp pos2 = bld.tmp(RegClass(sample_pos.type(), 1));
6155       bld.pseudo(aco_opcode::p_split_vector, Definition(pos1), Definition(pos2), sample_pos);
6156       pos1 = bld.vop2_e64(aco_opcode::v_sub_f32, bld.def(v1), pos1, Operand(0x3f000000u));
6157       pos2 = bld.vop2_e64(aco_opcode::v_sub_f32, bld.def(v1), pos2, Operand(0x3f000000u));
6158
6159       emit_interp_center(ctx, get_ssa_temp(ctx, &instr->dest.ssa), pos1, pos2);
6160       break;
6161    }
6162    case nir_intrinsic_load_barycentric_at_offset: {
6163       Temp offset = get_ssa_temp(ctx, instr->src[0].ssa);
6164       RegClass rc = RegClass(offset.type(), 1);
6165       Temp pos1 = bld.tmp(rc), pos2 = bld.tmp(rc);
6166       bld.pseudo(aco_opcode::p_split_vector, Definition(pos1), Definition(pos2), offset);
6167       emit_interp_center(ctx, get_ssa_temp(ctx, &instr->dest.ssa), pos1, pos2);
6168       break;
6169    }
6170    case nir_intrinsic_load_front_face: {
6171       bld.vopc(aco_opcode::v_cmp_lg_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6172                Operand(0u), get_arg(ctx, ctx->args->ac.front_face)).def(0).setHint(vcc);
6173       break;
6174    }
6175    case nir_intrinsic_load_view_index: {
6176       if (ctx->stage & (sw_vs | sw_gs | sw_tcs | sw_tes)) {
6177          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6178          bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.view_index)));
6179          break;
6180       }
6181
6182       /* fallthrough */
6183    }
6184    case nir_intrinsic_load_layer_id: {
6185       unsigned idx = nir_intrinsic_base(instr);
6186       bld.vintrp(aco_opcode::v_interp_mov_f32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6187                  Operand(2u), bld.m0(get_arg(ctx, ctx->args->ac.prim_mask)), idx, 0);
6188       break;
6189    }
6190    case nir_intrinsic_load_frag_coord: {
6191       emit_load_frag_coord(ctx, get_ssa_temp(ctx, &instr->dest.ssa), 4);
6192       break;
6193    }
6194    case nir_intrinsic_load_sample_pos: {
6195       Temp posx = get_arg(ctx, ctx->args->ac.frag_pos[0]);
6196       Temp posy = get_arg(ctx, ctx->args->ac.frag_pos[1]);
6197       bld.pseudo(aco_opcode::p_create_vector, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6198                  posx.id() ? bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), posx) : Operand(0u),
6199                  posy.id() ? bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), posy) : Operand(0u));
6200       break;
6201    }
6202    case nir_intrinsic_load_tess_coord:
6203       visit_load_tess_coord(ctx, instr);
6204       break;
6205    case nir_intrinsic_load_interpolated_input:
6206       visit_load_interpolated_input(ctx, instr);
6207       break;
6208    case nir_intrinsic_store_output:
6209       visit_store_output(ctx, instr);
6210       break;
6211    case nir_intrinsic_load_input:
6212    case nir_intrinsic_load_input_vertex:
6213       visit_load_input(ctx, instr);
6214       break;
6215    case nir_intrinsic_load_per_vertex_input:
6216       visit_load_per_vertex_input(ctx, instr);
6217       break;
6218    case nir_intrinsic_load_ubo:
6219       visit_load_ubo(ctx, instr);
6220       break;
6221    case nir_intrinsic_load_push_constant:
6222       visit_load_push_constant(ctx, instr);
6223       break;
6224    case nir_intrinsic_load_constant:
6225       visit_load_constant(ctx, instr);
6226       break;
6227    case nir_intrinsic_vulkan_resource_index:
6228       visit_load_resource(ctx, instr);
6229       break;
6230    case nir_intrinsic_discard:
6231       visit_discard(ctx, instr);
6232       break;
6233    case nir_intrinsic_discard_if:
6234       visit_discard_if(ctx, instr);
6235       break;
6236    case nir_intrinsic_load_shared:
6237       visit_load_shared(ctx, instr);
6238       break;
6239    case nir_intrinsic_store_shared:
6240       visit_store_shared(ctx, instr);
6241       break;
6242    case nir_intrinsic_shared_atomic_add:
6243    case nir_intrinsic_shared_atomic_imin:
6244    case nir_intrinsic_shared_atomic_umin:
6245    case nir_intrinsic_shared_atomic_imax:
6246    case nir_intrinsic_shared_atomic_umax:
6247    case nir_intrinsic_shared_atomic_and:
6248    case nir_intrinsic_shared_atomic_or:
6249    case nir_intrinsic_shared_atomic_xor:
6250    case nir_intrinsic_shared_atomic_exchange:
6251    case nir_intrinsic_shared_atomic_comp_swap:
6252       visit_shared_atomic(ctx, instr);
6253       break;
6254    case nir_intrinsic_image_deref_load:
6255       visit_image_load(ctx, instr);
6256       break;
6257    case nir_intrinsic_image_deref_store:
6258       visit_image_store(ctx, instr);
6259       break;
6260    case nir_intrinsic_image_deref_atomic_add:
6261    case nir_intrinsic_image_deref_atomic_umin:
6262    case nir_intrinsic_image_deref_atomic_imin:
6263    case nir_intrinsic_image_deref_atomic_umax:
6264    case nir_intrinsic_image_deref_atomic_imax:
6265    case nir_intrinsic_image_deref_atomic_and:
6266    case nir_intrinsic_image_deref_atomic_or:
6267    case nir_intrinsic_image_deref_atomic_xor:
6268    case nir_intrinsic_image_deref_atomic_exchange:
6269    case nir_intrinsic_image_deref_atomic_comp_swap:
6270       visit_image_atomic(ctx, instr);
6271       break;
6272    case nir_intrinsic_image_deref_size:
6273       visit_image_size(ctx, instr);
6274       break;
6275    case nir_intrinsic_load_ssbo:
6276       visit_load_ssbo(ctx, instr);
6277       break;
6278    case nir_intrinsic_store_ssbo:
6279       visit_store_ssbo(ctx, instr);
6280       break;
6281    case nir_intrinsic_load_global:
6282       visit_load_global(ctx, instr);
6283       break;
6284    case nir_intrinsic_store_global:
6285       visit_store_global(ctx, instr);
6286       break;
6287    case nir_intrinsic_global_atomic_add:
6288    case nir_intrinsic_global_atomic_imin:
6289    case nir_intrinsic_global_atomic_umin:
6290    case nir_intrinsic_global_atomic_imax:
6291    case nir_intrinsic_global_atomic_umax:
6292    case nir_intrinsic_global_atomic_and:
6293    case nir_intrinsic_global_atomic_or:
6294    case nir_intrinsic_global_atomic_xor:
6295    case nir_intrinsic_global_atomic_exchange:
6296    case nir_intrinsic_global_atomic_comp_swap:
6297       visit_global_atomic(ctx, instr);
6298       break;
6299    case nir_intrinsic_ssbo_atomic_add:
6300    case nir_intrinsic_ssbo_atomic_imin:
6301    case nir_intrinsic_ssbo_atomic_umin:
6302    case nir_intrinsic_ssbo_atomic_imax:
6303    case nir_intrinsic_ssbo_atomic_umax:
6304    case nir_intrinsic_ssbo_atomic_and:
6305    case nir_intrinsic_ssbo_atomic_or:
6306    case nir_intrinsic_ssbo_atomic_xor:
6307    case nir_intrinsic_ssbo_atomic_exchange:
6308    case nir_intrinsic_ssbo_atomic_comp_swap:
6309       visit_atomic_ssbo(ctx, instr);
6310       break;
6311    case nir_intrinsic_load_scratch:
6312       visit_load_scratch(ctx, instr);
6313       break;
6314    case nir_intrinsic_store_scratch:
6315       visit_store_scratch(ctx, instr);
6316       break;
6317    case nir_intrinsic_get_buffer_size:
6318       visit_get_buffer_size(ctx, instr);
6319       break;
6320    case nir_intrinsic_control_barrier: {
6321       if (ctx->program->chip_class == GFX6 && ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) {
6322          /* GFX6 only (thanks to a hw bug workaround):
6323           * The real barrier instruction isn’t needed, because an entire patch
6324           * always fits into a single wave.
6325           */
6326          break;
6327       }
6328
6329       if (ctx->shader->info.stage == MESA_SHADER_COMPUTE) {
6330          unsigned* bsize = ctx->program->info->cs.block_size;
6331          unsigned workgroup_size = bsize[0] * bsize[1] * bsize[2];
6332          if (workgroup_size > ctx->program->wave_size)
6333             bld.sopp(aco_opcode::s_barrier);
6334       } else if (ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) {
6335          /* For each patch provided during rendering, n TCS shader invocations will be processed,
6336           * where n is the number of vertices in the output patch.
6337           */
6338          unsigned workgroup_size = ctx->tcs_num_patches * ctx->shader->info.tess.tcs_vertices_out;
6339          if (workgroup_size > ctx->program->wave_size)
6340             bld.sopp(aco_opcode::s_barrier);
6341       } else {
6342          /* We don't know the workgroup size, so always emit the s_barrier. */
6343          bld.sopp(aco_opcode::s_barrier);
6344       }
6345
6346       break;
6347    }
6348    case nir_intrinsic_memory_barrier_tcs_patch:
6349    case nir_intrinsic_group_memory_barrier:
6350    case nir_intrinsic_memory_barrier:
6351    case nir_intrinsic_memory_barrier_buffer:
6352    case nir_intrinsic_memory_barrier_image:
6353    case nir_intrinsic_memory_barrier_shared:
6354       emit_memory_barrier(ctx, instr);
6355       break;
6356    case nir_intrinsic_load_num_work_groups: {
6357       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6358       bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.num_work_groups)));
6359       emit_split_vector(ctx, dst, 3);
6360       break;
6361    }
6362    case nir_intrinsic_load_local_invocation_id: {
6363       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6364       bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.local_invocation_ids)));
6365       emit_split_vector(ctx, dst, 3);
6366       break;
6367    }
6368    case nir_intrinsic_load_work_group_id: {
6369       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6370       struct ac_arg *args = ctx->args->ac.workgroup_ids;
6371       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
6372                  args[0].used ? Operand(get_arg(ctx, args[0])) : Operand(0u),
6373                  args[1].used ? Operand(get_arg(ctx, args[1])) : Operand(0u),
6374                  args[2].used ? Operand(get_arg(ctx, args[2])) : Operand(0u));
6375       emit_split_vector(ctx, dst, 3);
6376       break;
6377    }
6378    case nir_intrinsic_load_local_invocation_index: {
6379       Temp id = emit_mbcnt(ctx, bld.def(v1));
6380
6381       /* The tg_size bits [6:11] contain the subgroup id,
6382        * we need this multiplied by the wave size, and then OR the thread id to it.
6383        */
6384       if (ctx->program->wave_size == 64) {
6385          /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
6386          Temp tg_num = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0xfc0u),
6387                                 get_arg(ctx, ctx->args->ac.tg_size));
6388          bld.vop2(aco_opcode::v_or_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), tg_num, id);
6389       } else {
6390          /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR  */
6391          Temp tg_num = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
6392                                 get_arg(ctx, ctx->args->ac.tg_size), Operand(0x6u | (0x6u << 16)));
6393          bld.vop3(aco_opcode::v_lshl_or_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), tg_num, Operand(0x5u), id);
6394       }
6395       break;
6396    }
6397    case nir_intrinsic_load_subgroup_id: {
6398       if (ctx->stage == compute_cs) {
6399          bld.sop2(aco_opcode::s_bfe_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), bld.def(s1, scc),
6400                   get_arg(ctx, ctx->args->ac.tg_size), Operand(0x6u | (0x6u << 16)));
6401       } else {
6402          bld.sop1(aco_opcode::s_mov_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand(0x0u));
6403       }
6404       break;
6405    }
6406    case nir_intrinsic_load_subgroup_invocation: {
6407       emit_mbcnt(ctx, Definition(get_ssa_temp(ctx, &instr->dest.ssa)));
6408       break;
6409    }
6410    case nir_intrinsic_load_num_subgroups: {
6411       if (ctx->stage == compute_cs)
6412          bld.sop2(aco_opcode::s_and_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), bld.def(s1, scc), Operand(0x3fu),
6413                   get_arg(ctx, ctx->args->ac.tg_size));
6414       else
6415          bld.sop1(aco_opcode::s_mov_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand(0x1u));
6416       break;
6417    }
6418    case nir_intrinsic_ballot: {
6419       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6420       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6421       Definition tmp = bld.def(dst.regClass());
6422       Definition lanemask_tmp = dst.size() == bld.lm.size() ? tmp : bld.def(src.regClass());
6423       if (instr->src[0].ssa->bit_size == 1) {
6424          assert(src.regClass() == bld.lm);
6425          bld.sop2(Builder::s_and, lanemask_tmp, bld.def(s1, scc), Operand(exec, bld.lm), src);
6426       } else if (instr->src[0].ssa->bit_size == 32 && src.regClass() == v1) {
6427          bld.vopc(aco_opcode::v_cmp_lg_u32, lanemask_tmp, Operand(0u), src);
6428       } else if (instr->src[0].ssa->bit_size == 64 && src.regClass() == v2) {
6429          bld.vopc(aco_opcode::v_cmp_lg_u64, lanemask_tmp, Operand(0u), src);
6430       } else {
6431          fprintf(stderr, "Unimplemented NIR instr bit size: ");
6432          nir_print_instr(&instr->instr, stderr);
6433          fprintf(stderr, "\n");
6434       }
6435       if (dst.size() != bld.lm.size()) {
6436          /* Wave32 with ballot size set to 64 */
6437          bld.pseudo(aco_opcode::p_create_vector, Definition(tmp), lanemask_tmp.getTemp(), Operand(0u));
6438       }
6439       emit_wqm(ctx, tmp.getTemp(), dst);
6440       break;
6441    }
6442    case nir_intrinsic_shuffle:
6443    case nir_intrinsic_read_invocation: {
6444       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6445       if (!ctx->divergent_vals[instr->src[0].ssa->index]) {
6446          emit_uniform_subgroup(ctx, instr, src);
6447       } else {
6448          Temp tid = get_ssa_temp(ctx, instr->src[1].ssa);
6449          if (instr->intrinsic == nir_intrinsic_read_invocation || !ctx->divergent_vals[instr->src[1].ssa->index])
6450             tid = bld.as_uniform(tid);
6451          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6452          if (src.regClass() == v1) {
6453             emit_wqm(ctx, emit_bpermute(ctx, bld, tid, src), dst);
6454          } else if (src.regClass() == v2) {
6455             Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6456             bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6457             lo = emit_wqm(ctx, emit_bpermute(ctx, bld, tid, lo));
6458             hi = emit_wqm(ctx, emit_bpermute(ctx, bld, tid, hi));
6459             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6460             emit_split_vector(ctx, dst, 2);
6461          } else if (instr->dest.ssa.bit_size == 1 && tid.regClass() == s1) {
6462             assert(src.regClass() == bld.lm);
6463             Temp tmp = bld.sopc(Builder::s_bitcmp1, bld.def(s1, scc), src, tid);
6464             bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
6465          } else if (instr->dest.ssa.bit_size == 1 && tid.regClass() == v1) {
6466             assert(src.regClass() == bld.lm);
6467             Temp tmp;
6468             if (ctx->program->chip_class <= GFX7)
6469                tmp = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), src, tid);
6470             else if (ctx->program->wave_size == 64)
6471                tmp = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), tid, src);
6472             else
6473                tmp = bld.vop2_e64(aco_opcode::v_lshrrev_b32, bld.def(v1), tid, src);
6474             tmp = emit_extract_vector(ctx, tmp, 0, v1);
6475             tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u), tmp);
6476             emit_wqm(ctx, bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp), dst);
6477          } else {
6478             fprintf(stderr, "Unimplemented NIR instr bit size: ");
6479             nir_print_instr(&instr->instr, stderr);
6480             fprintf(stderr, "\n");
6481          }
6482       }
6483       break;
6484    }
6485    case nir_intrinsic_load_sample_id: {
6486       bld.vop3(aco_opcode::v_bfe_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6487                get_arg(ctx, ctx->args->ac.ancillary), Operand(8u), Operand(4u));
6488       break;
6489    }
6490    case nir_intrinsic_load_sample_mask_in: {
6491       visit_load_sample_mask_in(ctx, instr);
6492       break;
6493    }
6494    case nir_intrinsic_read_first_invocation: {
6495       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6496       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6497       if (src.regClass() == v1) {
6498          emit_wqm(ctx,
6499                   bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), src),
6500                   dst);
6501       } else if (src.regClass() == v2) {
6502          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6503          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6504          lo = emit_wqm(ctx, bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), lo));
6505          hi = emit_wqm(ctx, bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), hi));
6506          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6507          emit_split_vector(ctx, dst, 2);
6508       } else if (instr->dest.ssa.bit_size == 1) {
6509          assert(src.regClass() == bld.lm);
6510          Temp tmp = bld.sopc(Builder::s_bitcmp1, bld.def(s1, scc), src,
6511                              bld.sop1(Builder::s_ff1_i32, bld.def(s1), Operand(exec, bld.lm)));
6512          bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
6513       } else if (src.regClass() == s1) {
6514          bld.sop1(aco_opcode::s_mov_b32, Definition(dst), src);
6515       } else if (src.regClass() == s2) {
6516          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src);
6517       } else {
6518          fprintf(stderr, "Unimplemented NIR instr bit size: ");
6519          nir_print_instr(&instr->instr, stderr);
6520          fprintf(stderr, "\n");
6521       }
6522       break;
6523    }
6524    case nir_intrinsic_vote_all: {
6525       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6526       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6527       assert(src.regClass() == bld.lm);
6528       assert(dst.regClass() == bld.lm);
6529
6530       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src).def(1).getTemp();
6531       Temp cond = bool_to_vector_condition(ctx, emit_wqm(ctx, tmp));
6532       bld.sop1(Builder::s_not, Definition(dst), bld.def(s1, scc), cond);
6533       break;
6534    }
6535    case nir_intrinsic_vote_any: {
6536       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6537       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6538       assert(src.regClass() == bld.lm);
6539       assert(dst.regClass() == bld.lm);
6540
6541       Temp tmp = bool_to_scalar_condition(ctx, src);
6542       bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
6543       break;
6544    }
6545    case nir_intrinsic_reduce:
6546    case nir_intrinsic_inclusive_scan:
6547    case nir_intrinsic_exclusive_scan: {
6548       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6549       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6550       nir_op op = (nir_op) nir_intrinsic_reduction_op(instr);
6551       unsigned cluster_size = instr->intrinsic == nir_intrinsic_reduce ?
6552          nir_intrinsic_cluster_size(instr) : 0;
6553       cluster_size = util_next_power_of_two(MIN2(cluster_size ? cluster_size : ctx->program->wave_size, ctx->program->wave_size));
6554
6555       if (!ctx->divergent_vals[instr->src[0].ssa->index] && (op == nir_op_ior || op == nir_op_iand)) {
6556          emit_uniform_subgroup(ctx, instr, src);
6557       } else if (instr->dest.ssa.bit_size == 1) {
6558          if (op == nir_op_imul || op == nir_op_umin || op == nir_op_imin)
6559             op = nir_op_iand;
6560          else if (op == nir_op_iadd)
6561             op = nir_op_ixor;
6562          else if (op == nir_op_umax || op == nir_op_imax)
6563             op = nir_op_ior;
6564          assert(op == nir_op_iand || op == nir_op_ior || op == nir_op_ixor);
6565
6566          switch (instr->intrinsic) {
6567          case nir_intrinsic_reduce:
6568             emit_wqm(ctx, emit_boolean_reduce(ctx, op, cluster_size, src), dst);
6569             break;
6570          case nir_intrinsic_exclusive_scan:
6571             emit_wqm(ctx, emit_boolean_exclusive_scan(ctx, op, src), dst);
6572             break;
6573          case nir_intrinsic_inclusive_scan:
6574             emit_wqm(ctx, emit_boolean_inclusive_scan(ctx, op, src), dst);
6575             break;
6576          default:
6577             assert(false);
6578          }
6579       } else if (cluster_size == 1) {
6580          bld.copy(Definition(dst), src);
6581       } else {
6582          src = as_vgpr(ctx, src);
6583
6584          ReduceOp reduce_op;
6585          switch (op) {
6586          #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
6587             CASE(iadd)
6588             CASE(imul)
6589             CASE(fadd)
6590             CASE(fmul)
6591             CASE(imin)
6592             CASE(umin)
6593             CASE(fmin)
6594             CASE(imax)
6595             CASE(umax)
6596             CASE(fmax)
6597             CASE(iand)
6598             CASE(ior)
6599             CASE(ixor)
6600             default:
6601                unreachable("unknown reduction op");
6602          #undef CASE
6603          }
6604
6605          aco_opcode aco_op;
6606          switch (instr->intrinsic) {
6607             case nir_intrinsic_reduce: aco_op = aco_opcode::p_reduce; break;
6608             case nir_intrinsic_inclusive_scan: aco_op = aco_opcode::p_inclusive_scan; break;
6609             case nir_intrinsic_exclusive_scan: aco_op = aco_opcode::p_exclusive_scan; break;
6610             default:
6611                unreachable("unknown reduce intrinsic");
6612          }
6613
6614          aco_ptr<Pseudo_reduction_instruction> reduce{create_instruction<Pseudo_reduction_instruction>(aco_op, Format::PSEUDO_REDUCTION, 3, 5)};
6615          reduce->operands[0] = Operand(src);
6616          // filled in by aco_reduce_assign.cpp, used internally as part of the
6617          // reduce sequence
6618          assert(dst.size() == 1 || dst.size() == 2);
6619          reduce->operands[1] = Operand(RegClass(RegType::vgpr, dst.size()).as_linear());
6620          reduce->operands[2] = Operand(v1.as_linear());
6621
6622          Temp tmp_dst = bld.tmp(dst.regClass());
6623          reduce->definitions[0] = Definition(tmp_dst);
6624          reduce->definitions[1] = bld.def(ctx->program->lane_mask); // used internally
6625          reduce->definitions[2] = Definition();
6626          reduce->definitions[3] = Definition(scc, s1);
6627          reduce->definitions[4] = Definition();
6628          reduce->reduce_op = reduce_op;
6629          reduce->cluster_size = cluster_size;
6630          ctx->block->instructions.emplace_back(std::move(reduce));
6631
6632          emit_wqm(ctx, tmp_dst, dst);
6633       }
6634       break;
6635    }
6636    case nir_intrinsic_quad_broadcast: {
6637       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6638       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
6639          emit_uniform_subgroup(ctx, instr, src);
6640       } else {
6641          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6642          unsigned lane = nir_src_as_const_value(instr->src[1])->u32;
6643          uint32_t dpp_ctrl = dpp_quad_perm(lane, lane, lane, lane);
6644
6645          if (instr->dest.ssa.bit_size == 1) {
6646             assert(src.regClass() == bld.lm);
6647             assert(dst.regClass() == bld.lm);
6648             uint32_t half_mask = 0x11111111u << lane;
6649             Temp mask_tmp = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(half_mask), Operand(half_mask));
6650             Temp tmp = bld.tmp(bld.lm);
6651             bld.sop1(Builder::s_wqm, Definition(tmp),
6652                      bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), mask_tmp,
6653                               bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm))));
6654             emit_wqm(ctx, tmp, dst);
6655          } else if (instr->dest.ssa.bit_size == 32) {
6656             if (ctx->program->chip_class >= GFX8)
6657                emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl), dst);
6658             else
6659                emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl), dst);
6660          } else if (instr->dest.ssa.bit_size == 64) {
6661             Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6662             bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6663             if (ctx->program->chip_class >= GFX8) {
6664                lo = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), lo, dpp_ctrl));
6665                hi = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), hi, dpp_ctrl));
6666             } else {
6667                lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, (1 << 15) | dpp_ctrl));
6668                hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, (1 << 15) | dpp_ctrl));
6669             }
6670             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6671             emit_split_vector(ctx, dst, 2);
6672          } else {
6673             fprintf(stderr, "Unimplemented NIR instr bit size: ");
6674             nir_print_instr(&instr->instr, stderr);
6675             fprintf(stderr, "\n");
6676          }
6677       }
6678       break;
6679    }
6680    case nir_intrinsic_quad_swap_horizontal:
6681    case nir_intrinsic_quad_swap_vertical:
6682    case nir_intrinsic_quad_swap_diagonal:
6683    case nir_intrinsic_quad_swizzle_amd: {
6684       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6685       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
6686          emit_uniform_subgroup(ctx, instr, src);
6687          break;
6688       }
6689       uint16_t dpp_ctrl = 0;
6690       switch (instr->intrinsic) {
6691       case nir_intrinsic_quad_swap_horizontal:
6692          dpp_ctrl = dpp_quad_perm(1, 0, 3, 2);
6693          break;
6694       case nir_intrinsic_quad_swap_vertical:
6695          dpp_ctrl = dpp_quad_perm(2, 3, 0, 1);
6696          break;
6697       case nir_intrinsic_quad_swap_diagonal:
6698          dpp_ctrl = dpp_quad_perm(3, 2, 1, 0);
6699          break;
6700       case nir_intrinsic_quad_swizzle_amd:
6701          dpp_ctrl = nir_intrinsic_swizzle_mask(instr);
6702          break;
6703       default:
6704          break;
6705       }
6706       if (ctx->program->chip_class < GFX8)
6707          dpp_ctrl |= (1 << 15);
6708
6709       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6710       if (instr->dest.ssa.bit_size == 1) {
6711          assert(src.regClass() == bld.lm);
6712          src = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand((uint32_t)-1), src);
6713          if (ctx->program->chip_class >= GFX8)
6714             src = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl);
6715          else
6716             src = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, dpp_ctrl);
6717          Temp tmp = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), src);
6718          emit_wqm(ctx, tmp, dst);
6719       } else if (instr->dest.ssa.bit_size == 32) {
6720          Temp tmp;
6721          if (ctx->program->chip_class >= GFX8)
6722             tmp = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl);
6723          else
6724             tmp = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, dpp_ctrl);
6725          emit_wqm(ctx, tmp, dst);
6726       } else if (instr->dest.ssa.bit_size == 64) {
6727          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6728          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6729          if (ctx->program->chip_class >= GFX8) {
6730             lo = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), lo, dpp_ctrl));
6731             hi = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), hi, dpp_ctrl));
6732          } else {
6733             lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, dpp_ctrl));
6734             hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, dpp_ctrl));
6735          }
6736          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6737          emit_split_vector(ctx, dst, 2);
6738       } else {
6739          fprintf(stderr, "Unimplemented NIR instr bit size: ");
6740          nir_print_instr(&instr->instr, stderr);
6741          fprintf(stderr, "\n");
6742       }
6743       break;
6744    }
6745    case nir_intrinsic_masked_swizzle_amd: {
6746       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6747       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
6748          emit_uniform_subgroup(ctx, instr, src);
6749          break;
6750       }
6751       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6752       uint32_t mask = nir_intrinsic_swizzle_mask(instr);
6753       if (dst.regClass() == v1) {
6754          emit_wqm(ctx,
6755                   bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, mask, 0, false),
6756                   dst);
6757       } else if (dst.regClass() == v2) {
6758          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6759          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6760          lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, mask, 0, false));
6761          hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, mask, 0, false));
6762          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6763          emit_split_vector(ctx, dst, 2);
6764       } else {
6765          fprintf(stderr, "Unimplemented NIR instr bit size: ");
6766          nir_print_instr(&instr->instr, stderr);
6767          fprintf(stderr, "\n");
6768       }
6769       break;
6770    }
6771    case nir_intrinsic_write_invocation_amd: {
6772       Temp src = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
6773       Temp val = bld.as_uniform(get_ssa_temp(ctx, instr->src[1].ssa));
6774       Temp lane = bld.as_uniform(get_ssa_temp(ctx, instr->src[2].ssa));
6775       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6776       if (dst.regClass() == v1) {
6777          /* src2 is ignored for writelane. RA assigns the same reg for dst */
6778          emit_wqm(ctx, bld.writelane(bld.def(v1), val, lane, src), dst);
6779       } else if (dst.regClass() == v2) {
6780          Temp src_lo = bld.tmp(v1), src_hi = bld.tmp(v1);
6781          Temp val_lo = bld.tmp(s1), val_hi = bld.tmp(s1);
6782          bld.pseudo(aco_opcode::p_split_vector, Definition(src_lo), Definition(src_hi), src);
6783          bld.pseudo(aco_opcode::p_split_vector, Definition(val_lo), Definition(val_hi), val);
6784          Temp lo = emit_wqm(ctx, bld.writelane(bld.def(v1), val_lo, lane, src_hi));
6785          Temp hi = emit_wqm(ctx, bld.writelane(bld.def(v1), val_hi, lane, src_hi));
6786          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6787          emit_split_vector(ctx, dst, 2);
6788       } else {
6789          fprintf(stderr, "Unimplemented NIR instr bit size: ");
6790          nir_print_instr(&instr->instr, stderr);
6791          fprintf(stderr, "\n");
6792       }
6793       break;
6794    }
6795    case nir_intrinsic_mbcnt_amd: {
6796       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6797       RegClass rc = RegClass(src.type(), 1);
6798       Temp mask_lo = bld.tmp(rc), mask_hi = bld.tmp(rc);
6799       bld.pseudo(aco_opcode::p_split_vector, Definition(mask_lo), Definition(mask_hi), src);
6800       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6801       Temp wqm_tmp = emit_mbcnt(ctx, bld.def(v1), Operand(mask_lo), Operand(mask_hi));
6802       emit_wqm(ctx, wqm_tmp, dst);
6803       break;
6804    }
6805    case nir_intrinsic_load_helper_invocation: {
6806       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6807       bld.pseudo(aco_opcode::p_load_helper, Definition(dst));
6808       ctx->block->kind |= block_kind_needs_lowering;
6809       ctx->program->needs_exact = true;
6810       break;
6811    }
6812    case nir_intrinsic_is_helper_invocation: {
6813       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6814       bld.pseudo(aco_opcode::p_is_helper, Definition(dst));
6815       ctx->block->kind |= block_kind_needs_lowering;
6816       ctx->program->needs_exact = true;
6817       break;
6818    }
6819    case nir_intrinsic_demote:
6820       bld.pseudo(aco_opcode::p_demote_to_helper, Operand(-1u));
6821
6822       if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
6823          ctx->cf_info.exec_potentially_empty_discard = true;
6824       ctx->block->kind |= block_kind_uses_demote;
6825       ctx->program->needs_exact = true;
6826       break;
6827    case nir_intrinsic_demote_if: {
6828       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6829       assert(src.regClass() == bld.lm);
6830       Temp cond = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
6831       bld.pseudo(aco_opcode::p_demote_to_helper, cond);
6832
6833       if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
6834          ctx->cf_info.exec_potentially_empty_discard = true;
6835       ctx->block->kind |= block_kind_uses_demote;
6836       ctx->program->needs_exact = true;
6837       break;
6838    }
6839    case nir_intrinsic_first_invocation: {
6840       emit_wqm(ctx, bld.sop1(Builder::s_ff1_i32, bld.def(s1), Operand(exec, bld.lm)),
6841                get_ssa_temp(ctx, &instr->dest.ssa));
6842       break;
6843    }
6844    case nir_intrinsic_shader_clock:
6845       bld.smem(aco_opcode::s_memtime, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), false);
6846       emit_split_vector(ctx, get_ssa_temp(ctx, &instr->dest.ssa), 2);
6847       break;
6848    case nir_intrinsic_load_vertex_id_zero_base: {
6849       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6850       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.vertex_id));
6851       break;
6852    }
6853    case nir_intrinsic_load_first_vertex: {
6854       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6855       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.base_vertex));
6856       break;
6857    }
6858    case nir_intrinsic_load_base_instance: {
6859       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6860       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.start_instance));
6861       break;
6862    }
6863    case nir_intrinsic_load_instance_id: {
6864       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6865       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.instance_id));
6866       break;
6867    }
6868    case nir_intrinsic_load_draw_id: {
6869       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6870       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.draw_id));
6871       break;
6872    }
6873    case nir_intrinsic_load_invocation_id: {
6874       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6875
6876       if (ctx->shader->info.stage == MESA_SHADER_GEOMETRY) {
6877          if (ctx->options->chip_class >= GFX10)
6878             bld.vop2_e64(aco_opcode::v_and_b32, Definition(dst), Operand(127u), get_arg(ctx, ctx->args->ac.gs_invocation_id));
6879          else
6880             bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.gs_invocation_id));
6881       } else if (ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) {
6882          bld.vop3(aco_opcode::v_bfe_u32, Definition(dst),
6883                   get_arg(ctx, ctx->args->ac.tcs_rel_ids), Operand(8u), Operand(5u));
6884       } else {
6885          unreachable("Unsupported stage for load_invocation_id");
6886       }
6887
6888       break;
6889    }
6890    case nir_intrinsic_load_primitive_id: {
6891       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6892
6893       switch (ctx->shader->info.stage) {
6894       case MESA_SHADER_GEOMETRY:
6895          bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.gs_prim_id));
6896          break;
6897       case MESA_SHADER_TESS_CTRL:
6898          bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.tcs_patch_id));
6899          break;
6900       case MESA_SHADER_TESS_EVAL:
6901          bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.tes_patch_id));
6902          break;
6903       default:
6904          unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
6905       }
6906
6907       break;
6908    }
6909    case nir_intrinsic_load_patch_vertices_in: {
6910       assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL ||
6911              ctx->shader->info.stage == MESA_SHADER_TESS_EVAL);
6912
6913       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6914       bld.copy(Definition(dst), Operand(ctx->args->options->key.tcs.input_vertices));
6915       break;
6916    }
6917    case nir_intrinsic_emit_vertex_with_counter: {
6918       visit_emit_vertex_with_counter(ctx, instr);
6919       break;
6920    }
6921    case nir_intrinsic_end_primitive_with_counter: {
6922       unsigned stream = nir_intrinsic_stream_id(instr);
6923       bld.sopp(aco_opcode::s_sendmsg, bld.m0(ctx->gs_wave_id), -1, sendmsg_gs(true, false, stream));
6924       break;
6925    }
6926    case nir_intrinsic_set_vertex_count: {
6927       /* unused, the HW keeps track of this for us */
6928       break;
6929    }
6930    default:
6931       fprintf(stderr, "Unimplemented intrinsic instr: ");
6932       nir_print_instr(&instr->instr, stderr);
6933       fprintf(stderr, "\n");
6934       abort();
6935
6936       break;
6937    }
6938 }
6939
6940
6941 void tex_fetch_ptrs(isel_context *ctx, nir_tex_instr *instr,
6942                     Temp *res_ptr, Temp *samp_ptr, Temp *fmask_ptr,
6943                     enum glsl_base_type *stype)
6944 {
6945    nir_deref_instr *texture_deref_instr = NULL;
6946    nir_deref_instr *sampler_deref_instr = NULL;
6947    int plane = -1;
6948
6949    for (unsigned i = 0; i < instr->num_srcs; i++) {
6950       switch (instr->src[i].src_type) {
6951       case nir_tex_src_texture_deref:
6952          texture_deref_instr = nir_src_as_deref(instr->src[i].src);
6953          break;
6954       case nir_tex_src_sampler_deref:
6955          sampler_deref_instr = nir_src_as_deref(instr->src[i].src);
6956          break;
6957       case nir_tex_src_plane:
6958          plane = nir_src_as_int(instr->src[i].src);
6959          break;
6960       default:
6961          break;
6962       }
6963    }
6964
6965    *stype = glsl_get_sampler_result_type(texture_deref_instr->type);
6966
6967    if (!sampler_deref_instr)
6968       sampler_deref_instr = texture_deref_instr;
6969
6970    if (plane >= 0) {
6971       assert(instr->op != nir_texop_txf_ms &&
6972              instr->op != nir_texop_samples_identical);
6973       assert(instr->sampler_dim  != GLSL_SAMPLER_DIM_BUF);
6974       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, (aco_descriptor_type)(ACO_DESC_PLANE_0 + plane), instr, false, false);
6975    } else if (instr->sampler_dim  == GLSL_SAMPLER_DIM_BUF) {
6976       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_BUFFER, instr, false, false);
6977    } else if (instr->op == nir_texop_fragment_mask_fetch) {
6978       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_FMASK, instr, false, false);
6979    } else {
6980       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_IMAGE, instr, false, false);
6981    }
6982    if (samp_ptr) {
6983       *samp_ptr = get_sampler_desc(ctx, sampler_deref_instr, ACO_DESC_SAMPLER, instr, false, false);
6984
6985       if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT && ctx->options->chip_class < GFX8) {
6986          /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
6987          Builder bld(ctx->program, ctx->block);
6988
6989          /* to avoid unnecessary moves, we split and recombine sampler and image */
6990          Temp img[8] = {bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1),
6991                         bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1)};
6992          Temp samp[4] = {bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1)};
6993          bld.pseudo(aco_opcode::p_split_vector, Definition(img[0]), Definition(img[1]),
6994                     Definition(img[2]), Definition(img[3]), Definition(img[4]),
6995                     Definition(img[5]), Definition(img[6]), Definition(img[7]), *res_ptr);
6996          bld.pseudo(aco_opcode::p_split_vector, Definition(samp[0]), Definition(samp[1]),
6997                     Definition(samp[2]), Definition(samp[3]), *samp_ptr);
6998
6999          samp[0] = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), samp[0], img[7]);
7000          *res_ptr = bld.pseudo(aco_opcode::p_create_vector, bld.def(s8),
7001                                img[0], img[1], img[2], img[3],
7002                                img[4], img[5], img[6], img[7]);
7003          *samp_ptr = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
7004                                 samp[0], samp[1], samp[2], samp[3]);
7005       }
7006    }
7007    if (fmask_ptr && (instr->op == nir_texop_txf_ms ||
7008                      instr->op == nir_texop_samples_identical))
7009       *fmask_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_FMASK, instr, false, false);
7010 }
7011
7012 void build_cube_select(isel_context *ctx, Temp ma, Temp id, Temp deriv,
7013                        Temp *out_ma, Temp *out_sc, Temp *out_tc)
7014 {
7015    Builder bld(ctx->program, ctx->block);
7016
7017    Temp deriv_x = emit_extract_vector(ctx, deriv, 0, v1);
7018    Temp deriv_y = emit_extract_vector(ctx, deriv, 1, v1);
7019    Temp deriv_z = emit_extract_vector(ctx, deriv, 2, v1);
7020
7021    Operand neg_one(0xbf800000u);
7022    Operand one(0x3f800000u);
7023    Operand two(0x40000000u);
7024    Operand four(0x40800000u);
7025
7026    Temp is_ma_positive = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), ma);
7027    Temp sgn_ma = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), neg_one, one, is_ma_positive);
7028    Temp neg_sgn_ma = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), Operand(0u), sgn_ma);
7029
7030    Temp is_ma_z = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), four, id);
7031    Temp is_ma_y = bld.vopc(aco_opcode::v_cmp_le_f32, bld.def(bld.lm), two, id);
7032    is_ma_y = bld.sop2(Builder::s_andn2, bld.hint_vcc(bld.def(bld.lm)), is_ma_y, is_ma_z);
7033    Temp is_not_ma_x = bld.sop2(aco_opcode::s_or_b64, bld.hint_vcc(bld.def(bld.lm)), bld.def(s1, scc), is_ma_z, is_ma_y);
7034
7035    // select sc
7036    Temp tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_z, deriv_x, is_not_ma_x);
7037    Temp sgn = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1),
7038                        bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), neg_sgn_ma, sgn_ma, is_ma_z),
7039                        one, is_ma_y);
7040    *out_sc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tmp, sgn);
7041
7042    // select tc
7043    tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_y, deriv_z, is_ma_y);
7044    sgn = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), neg_one, sgn_ma, is_ma_y);
7045    *out_tc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tmp, sgn);
7046
7047    // select ma
7048    tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
7049                   bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_x, deriv_y, is_ma_y),
7050                   deriv_z, is_ma_z);
7051    tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffffu), tmp);
7052    *out_ma = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), two, tmp);
7053 }
7054
7055 void prepare_cube_coords(isel_context *ctx, std::vector<Temp>& coords, Temp* ddx, Temp* ddy, bool is_deriv, bool is_array)
7056 {
7057    Builder bld(ctx->program, ctx->block);
7058    Temp ma, tc, sc, id;
7059
7060    if (is_array) {
7061       coords[3] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coords[3]);
7062
7063       // see comment in ac_prepare_cube_coords()
7064       if (ctx->options->chip_class <= GFX8)
7065          coords[3] = bld.vop2(aco_opcode::v_max_f32, bld.def(v1), Operand(0u), coords[3]);
7066    }
7067
7068    ma = bld.vop3(aco_opcode::v_cubema_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7069
7070    aco_ptr<VOP3A_instruction> vop3a{create_instruction<VOP3A_instruction>(aco_opcode::v_rcp_f32, asVOP3(Format::VOP1), 1, 1)};
7071    vop3a->operands[0] = Operand(ma);
7072    vop3a->abs[0] = true;
7073    Temp invma = bld.tmp(v1);
7074    vop3a->definitions[0] = Definition(invma);
7075    ctx->block->instructions.emplace_back(std::move(vop3a));
7076
7077    sc = bld.vop3(aco_opcode::v_cubesc_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7078    if (!is_deriv)
7079       sc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), sc, invma, Operand(0x3fc00000u/*1.5*/));
7080
7081    tc = bld.vop3(aco_opcode::v_cubetc_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7082    if (!is_deriv)
7083       tc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), tc, invma, Operand(0x3fc00000u/*1.5*/));
7084
7085    id = bld.vop3(aco_opcode::v_cubeid_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7086
7087    if (is_deriv) {
7088       sc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), sc, invma);
7089       tc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tc, invma);
7090
7091       for (unsigned i = 0; i < 2; i++) {
7092          // see comment in ac_prepare_cube_coords()
7093          Temp deriv_ma;
7094          Temp deriv_sc, deriv_tc;
7095          build_cube_select(ctx, ma, id, i ? *ddy : *ddx,
7096                            &deriv_ma, &deriv_sc, &deriv_tc);
7097
7098          deriv_ma = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, invma);
7099
7100          Temp x = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1),
7101                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_sc, invma),
7102                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, sc));
7103          Temp y = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1),
7104                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_tc, invma),
7105                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, tc));
7106          *(i ? ddy : ddx) = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), x, y);
7107       }
7108
7109       sc = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), Operand(0x3fc00000u/*1.5*/), sc);
7110       tc = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), Operand(0x3fc00000u/*1.5*/), tc);
7111    }
7112
7113    if (is_array)
7114       id = bld.vop2(aco_opcode::v_madmk_f32, bld.def(v1), coords[3], id, Operand(0x41000000u/*8.0*/));
7115    coords.resize(3);
7116    coords[0] = sc;
7117    coords[1] = tc;
7118    coords[2] = id;
7119 }
7120
7121 void get_const_vec(nir_ssa_def *vec, nir_const_value *cv[4])
7122 {
7123    if (vec->parent_instr->type != nir_instr_type_alu)
7124       return;
7125    nir_alu_instr *vec_instr = nir_instr_as_alu(vec->parent_instr);
7126    if (vec_instr->op != nir_op_vec(vec->num_components))
7127       return;
7128
7129    for (unsigned i = 0; i < vec->num_components; i++) {
7130       cv[i] = vec_instr->src[i].swizzle[0] == 0 ?
7131               nir_src_as_const_value(vec_instr->src[i].src) : NULL;
7132    }
7133 }
7134
7135 void visit_tex(isel_context *ctx, nir_tex_instr *instr)
7136 {
7137    Builder bld(ctx->program, ctx->block);
7138    bool has_bias = false, has_lod = false, level_zero = false, has_compare = false,
7139         has_offset = false, has_ddx = false, has_ddy = false, has_derivs = false, has_sample_index = false;
7140    Temp resource, sampler, fmask_ptr, bias = Temp(), compare = Temp(), sample_index = Temp(),
7141         lod = Temp(), offset = Temp(), ddx = Temp(), ddy = Temp();
7142    std::vector<Temp> coords;
7143    std::vector<Temp> derivs;
7144    nir_const_value *sample_index_cv = NULL;
7145    nir_const_value *const_offset[4] = {NULL, NULL, NULL, NULL};
7146    enum glsl_base_type stype;
7147    tex_fetch_ptrs(ctx, instr, &resource, &sampler, &fmask_ptr, &stype);
7148
7149    bool tg4_integer_workarounds = ctx->options->chip_class <= GFX8 && instr->op == nir_texop_tg4 &&
7150                                   (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT);
7151    bool tg4_integer_cube_workaround = tg4_integer_workarounds &&
7152                                       instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
7153
7154    for (unsigned i = 0; i < instr->num_srcs; i++) {
7155       switch (instr->src[i].src_type) {
7156       case nir_tex_src_coord: {
7157          Temp coord = get_ssa_temp(ctx, instr->src[i].src.ssa);
7158          for (unsigned i = 0; i < coord.size(); i++)
7159             coords.emplace_back(emit_extract_vector(ctx, coord, i, v1));
7160          break;
7161       }
7162       case nir_tex_src_bias:
7163          if (instr->op == nir_texop_txb) {
7164             bias = get_ssa_temp(ctx, instr->src[i].src.ssa);
7165             has_bias = true;
7166          }
7167          break;
7168       case nir_tex_src_lod: {
7169          nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
7170
7171          if (val && val->f32 <= 0.0) {
7172             level_zero = true;
7173          } else {
7174             lod = get_ssa_temp(ctx, instr->src[i].src.ssa);
7175             has_lod = true;
7176          }
7177          break;
7178       }
7179       case nir_tex_src_comparator:
7180          if (instr->is_shadow) {
7181             compare = get_ssa_temp(ctx, instr->src[i].src.ssa);
7182             has_compare = true;
7183          }
7184          break;
7185       case nir_tex_src_offset:
7186          offset = get_ssa_temp(ctx, instr->src[i].src.ssa);
7187          get_const_vec(instr->src[i].src.ssa, const_offset);
7188          has_offset = true;
7189          break;
7190       case nir_tex_src_ddx:
7191          ddx = get_ssa_temp(ctx, instr->src[i].src.ssa);
7192          has_ddx = true;
7193          break;
7194       case nir_tex_src_ddy:
7195          ddy = get_ssa_temp(ctx, instr->src[i].src.ssa);
7196          has_ddy = true;
7197          break;
7198       case nir_tex_src_ms_index:
7199          sample_index = get_ssa_temp(ctx, instr->src[i].src.ssa);
7200          sample_index_cv = nir_src_as_const_value(instr->src[i].src);
7201          has_sample_index = true;
7202          break;
7203       case nir_tex_src_texture_offset:
7204       case nir_tex_src_sampler_offset:
7205       default:
7206          break;
7207       }
7208    }
7209
7210    if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
7211       return get_buffer_size(ctx, resource, get_ssa_temp(ctx, &instr->dest.ssa), true);
7212
7213    if (instr->op == nir_texop_texture_samples) {
7214       Temp dword3 = emit_extract_vector(ctx, resource, 3, s1);
7215
7216       Temp samples_log2 = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), dword3, Operand(16u | 4u<<16));
7217       Temp samples = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), Operand(1u), samples_log2);
7218       Temp type = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), dword3, Operand(28u | 4u<<16 /* offset=28, width=4 */));
7219       Temp is_msaa = bld.sopc(aco_opcode::s_cmp_ge_u32, bld.def(s1, scc), type, Operand(14u));
7220
7221       bld.sop2(aco_opcode::s_cselect_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
7222                samples, Operand(1u), bld.scc(is_msaa));
7223       return;
7224    }
7225
7226    if (has_offset && instr->op != nir_texop_txf && instr->op != nir_texop_txf_ms) {
7227       aco_ptr<Instruction> tmp_instr;
7228       Temp acc, pack = Temp();
7229
7230       uint32_t pack_const = 0;
7231       for (unsigned i = 0; i < offset.size(); i++) {
7232          if (!const_offset[i])
7233             continue;
7234          pack_const |= (const_offset[i]->u32 & 0x3Fu) << (8u * i);
7235       }
7236
7237       if (offset.type() == RegType::sgpr) {
7238          for (unsigned i = 0; i < offset.size(); i++) {
7239             if (const_offset[i])
7240                continue;
7241
7242             acc = emit_extract_vector(ctx, offset, i, s1);
7243             acc = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), acc, Operand(0x3Fu));
7244
7245             if (i) {
7246                acc = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), acc, Operand(8u * i));
7247             }
7248
7249             if (pack == Temp()) {
7250                pack = acc;
7251             } else {
7252                pack = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), pack, acc);
7253             }
7254          }
7255
7256          if (pack_const && pack != Temp())
7257             pack = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(pack_const), pack);
7258       } else {
7259          for (unsigned i = 0; i < offset.size(); i++) {
7260             if (const_offset[i])
7261                continue;
7262
7263             acc = emit_extract_vector(ctx, offset, i, v1);
7264             acc = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x3Fu), acc);
7265
7266             if (i) {
7267                acc = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(8u * i), acc);
7268             }
7269
7270             if (pack == Temp()) {
7271                pack = acc;
7272             } else {
7273                pack = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), pack, acc);
7274             }
7275          }
7276
7277          if (pack_const && pack != Temp())
7278             pack = bld.sop2(aco_opcode::v_or_b32, bld.def(v1), Operand(pack_const), pack);
7279       }
7280       if (pack_const && pack == Temp())
7281          offset = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(pack_const));
7282       else if (pack == Temp())
7283          has_offset = false;
7284       else
7285          offset = pack;
7286    }
7287
7288    if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && instr->coord_components)
7289       prepare_cube_coords(ctx, coords, &ddx, &ddy, instr->op == nir_texop_txd, instr->is_array && instr->op != nir_texop_lod);
7290
7291    /* pack derivatives */
7292    if (has_ddx || has_ddy) {
7293       if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && ctx->options->chip_class == GFX9) {
7294          assert(has_ddx && has_ddy && ddx.size() == 1 && ddy.size() == 1);
7295          Temp zero = bld.copy(bld.def(v1), Operand(0u));
7296          derivs = {ddy, zero, ddy, zero};
7297       } else {
7298          for (unsigned i = 0; has_ddx && i < ddx.size(); i++)
7299             derivs.emplace_back(emit_extract_vector(ctx, ddx, i, v1));
7300          for (unsigned i = 0; has_ddy && i < ddy.size(); i++)
7301             derivs.emplace_back(emit_extract_vector(ctx, ddy, i, v1));
7302       }
7303       has_derivs = true;
7304    }
7305
7306    if (instr->coord_components > 1 &&
7307        instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
7308        instr->is_array &&
7309        instr->op != nir_texop_txf)
7310       coords[1] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coords[1]);
7311
7312    if (instr->coord_components > 2 &&
7313       (instr->sampler_dim == GLSL_SAMPLER_DIM_2D ||
7314        instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
7315        instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS ||
7316        instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
7317        instr->is_array &&
7318        instr->op != nir_texop_txf &&
7319        instr->op != nir_texop_txf_ms &&
7320        instr->op != nir_texop_fragment_fetch &&
7321        instr->op != nir_texop_fragment_mask_fetch)
7322       coords[2] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coords[2]);
7323
7324    if (ctx->options->chip_class == GFX9 &&
7325        instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
7326        instr->op != nir_texop_lod && instr->coord_components) {
7327       assert(coords.size() > 0 && coords.size() < 3);
7328
7329       coords.insert(std::next(coords.begin()), bld.copy(bld.def(v1), instr->op == nir_texop_txf ?
7330                                                                      Operand((uint32_t) 0) :
7331                                                                      Operand((uint32_t) 0x3f000000)));
7332    }
7333
7334    bool da = should_declare_array(ctx, instr->sampler_dim, instr->is_array);
7335
7336    if (instr->op == nir_texop_samples_identical)
7337       resource = fmask_ptr;
7338
7339    else if ((instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
7340              instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
7341             instr->op != nir_texop_txs &&
7342             instr->op != nir_texop_fragment_fetch &&
7343             instr->op != nir_texop_fragment_mask_fetch) {
7344       assert(has_sample_index);
7345       Operand op(sample_index);
7346       if (sample_index_cv)
7347          op = Operand(sample_index_cv->u32);
7348       sample_index = adjust_sample_index_using_fmask(ctx, da, coords, op, fmask_ptr);
7349    }
7350
7351    if (has_offset && (instr->op == nir_texop_txf || instr->op == nir_texop_txf_ms)) {
7352       for (unsigned i = 0; i < std::min(offset.size(), instr->coord_components); i++) {
7353          Temp off = emit_extract_vector(ctx, offset, i, v1);
7354          coords[i] = bld.vadd32(bld.def(v1), coords[i], off);
7355       }
7356       has_offset = false;
7357    }
7358
7359    /* Build tex instruction */
7360    unsigned dmask = nir_ssa_def_components_read(&instr->dest.ssa);
7361    unsigned dim = ctx->options->chip_class >= GFX10 && instr->sampler_dim != GLSL_SAMPLER_DIM_BUF
7362                   ? ac_get_sampler_dim(ctx->options->chip_class, instr->sampler_dim, instr->is_array)
7363                   : 0;
7364    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7365    Temp tmp_dst = dst;
7366
7367    /* gather4 selects the component by dmask and always returns vec4 */
7368    if (instr->op == nir_texop_tg4) {
7369       assert(instr->dest.ssa.num_components == 4);
7370       if (instr->is_shadow)
7371          dmask = 1;
7372       else
7373          dmask = 1 << instr->component;
7374       if (tg4_integer_cube_workaround || dst.type() == RegType::sgpr)
7375          tmp_dst = bld.tmp(v4);
7376    } else if (instr->op == nir_texop_samples_identical) {
7377       tmp_dst = bld.tmp(v1);
7378    } else if (util_bitcount(dmask) != instr->dest.ssa.num_components || dst.type() == RegType::sgpr) {
7379       tmp_dst = bld.tmp(RegClass(RegType::vgpr, util_bitcount(dmask)));
7380    }
7381
7382    aco_ptr<MIMG_instruction> tex;
7383    if (instr->op == nir_texop_txs || instr->op == nir_texop_query_levels) {
7384       if (!has_lod)
7385          lod = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
7386
7387       bool div_by_6 = instr->op == nir_texop_txs &&
7388                       instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
7389                       instr->is_array &&
7390                       (dmask & (1 << 2));
7391       if (tmp_dst.id() == dst.id() && div_by_6)
7392          tmp_dst = bld.tmp(tmp_dst.regClass());
7393
7394       tex.reset(create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 3, 1));
7395       tex->operands[0] = Operand(resource);
7396       tex->operands[1] = Operand(s4); /* no sampler */
7397       tex->operands[2] = Operand(as_vgpr(ctx,lod));
7398       if (ctx->options->chip_class == GFX9 &&
7399           instr->op == nir_texop_txs &&
7400           instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
7401           instr->is_array) {
7402          tex->dmask = (dmask & 0x1) | ((dmask & 0x2) << 1);
7403       } else if (instr->op == nir_texop_query_levels) {
7404          tex->dmask = 1 << 3;
7405       } else {
7406          tex->dmask = dmask;
7407       }
7408       tex->da = da;
7409       tex->definitions[0] = Definition(tmp_dst);
7410       tex->dim = dim;
7411       tex->can_reorder = true;
7412       ctx->block->instructions.emplace_back(std::move(tex));
7413
7414       if (div_by_6) {
7415          /* divide 3rd value by 6 by multiplying with magic number */
7416          emit_split_vector(ctx, tmp_dst, tmp_dst.size());
7417          Temp c = bld.copy(bld.def(s1), Operand((uint32_t) 0x2AAAAAAB));
7418          Temp by_6 = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), emit_extract_vector(ctx, tmp_dst, 2, v1), c);
7419          assert(instr->dest.ssa.num_components == 3);
7420          Temp tmp = dst.type() == RegType::vgpr ? dst : bld.tmp(v3);
7421          tmp_dst = bld.pseudo(aco_opcode::p_create_vector, Definition(tmp),
7422                               emit_extract_vector(ctx, tmp_dst, 0, v1),
7423                               emit_extract_vector(ctx, tmp_dst, 1, v1),
7424                               by_6);
7425
7426       }
7427
7428       expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, dmask);
7429       return;
7430    }
7431
7432    Temp tg4_compare_cube_wa64 = Temp();
7433
7434    if (tg4_integer_workarounds) {
7435       tex.reset(create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 3, 1));
7436       tex->operands[0] = Operand(resource);
7437       tex->operands[1] = Operand(s4); /* no sampler */
7438       tex->operands[2] = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
7439       tex->dim = dim;
7440       tex->dmask = 0x3;
7441       tex->da = da;
7442       Temp size = bld.tmp(v2);
7443       tex->definitions[0] = Definition(size);
7444       tex->can_reorder = true;
7445       ctx->block->instructions.emplace_back(std::move(tex));
7446       emit_split_vector(ctx, size, size.size());
7447
7448       Temp half_texel[2];
7449       for (unsigned i = 0; i < 2; i++) {
7450          half_texel[i] = emit_extract_vector(ctx, size, i, v1);
7451          half_texel[i] = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), half_texel[i]);
7452          half_texel[i] = bld.vop1(aco_opcode::v_rcp_iflag_f32, bld.def(v1), half_texel[i]);
7453          half_texel[i] = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0xbf000000/*-0.5*/), half_texel[i]);
7454       }
7455
7456       Temp new_coords[2] = {
7457          bld.vop2(aco_opcode::v_add_f32, bld.def(v1), coords[0], half_texel[0]),
7458          bld.vop2(aco_opcode::v_add_f32, bld.def(v1), coords[1], half_texel[1])
7459       };
7460
7461       if (tg4_integer_cube_workaround) {
7462          // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
7463          Temp desc[resource.size()];
7464          aco_ptr<Instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector,
7465                                                                            Format::PSEUDO, 1, resource.size())};
7466          split->operands[0] = Operand(resource);
7467          for (unsigned i = 0; i < resource.size(); i++) {
7468             desc[i] = bld.tmp(s1);
7469             split->definitions[i] = Definition(desc[i]);
7470          }
7471          ctx->block->instructions.emplace_back(std::move(split));
7472
7473          Temp dfmt = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), desc[1], Operand(20u | (6u << 16)));
7474          Temp compare_cube_wa = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), dfmt,
7475                                          Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8));
7476
7477          Temp nfmt;
7478          if (stype == GLSL_TYPE_UINT) {
7479             nfmt = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1),
7480                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED),
7481                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT),
7482                             bld.scc(compare_cube_wa));
7483          } else {
7484             nfmt = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1),
7485                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED),
7486                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT),
7487                             bld.scc(compare_cube_wa));
7488          }
7489          tg4_compare_cube_wa64 = bld.tmp(bld.lm);
7490          bool_to_vector_condition(ctx, compare_cube_wa, tg4_compare_cube_wa64);
7491
7492          nfmt = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), nfmt, Operand(26u));
7493
7494          desc[1] = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), desc[1],
7495                             Operand((uint32_t)C_008F14_NUM_FORMAT));
7496          desc[1] = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), desc[1], nfmt);
7497
7498          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector,
7499                                                                          Format::PSEUDO, resource.size(), 1)};
7500          for (unsigned i = 0; i < resource.size(); i++)
7501             vec->operands[i] = Operand(desc[i]);
7502          resource = bld.tmp(resource.regClass());
7503          vec->definitions[0] = Definition(resource);
7504          ctx->block->instructions.emplace_back(std::move(vec));
7505
7506          new_coords[0] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
7507                                   new_coords[0], coords[0], tg4_compare_cube_wa64);
7508          new_coords[1] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
7509                                   new_coords[1], coords[1], tg4_compare_cube_wa64);
7510       }
7511       coords[0] = new_coords[0];
7512       coords[1] = new_coords[1];
7513    }
7514
7515    if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
7516       //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
7517
7518       assert(coords.size() == 1);
7519       unsigned last_bit = util_last_bit(nir_ssa_def_components_read(&instr->dest.ssa));
7520       aco_opcode op;
7521       switch (last_bit) {
7522       case 1:
7523          op = aco_opcode::buffer_load_format_x; break;
7524       case 2:
7525          op = aco_opcode::buffer_load_format_xy; break;
7526       case 3:
7527          op = aco_opcode::buffer_load_format_xyz; break;
7528       case 4:
7529          op = aco_opcode::buffer_load_format_xyzw; break;
7530       default:
7531          unreachable("Tex instruction loads more than 4 components.");
7532       }
7533
7534       /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
7535       if (last_bit == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
7536          tmp_dst = dst;
7537       else
7538          tmp_dst = bld.tmp(RegType::vgpr, last_bit);
7539
7540       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
7541       mubuf->operands[0] = Operand(resource);
7542       mubuf->operands[1] = Operand(coords[0]);
7543       mubuf->operands[2] = Operand((uint32_t) 0);
7544       mubuf->definitions[0] = Definition(tmp_dst);
7545       mubuf->idxen = true;
7546       mubuf->can_reorder = true;
7547       ctx->block->instructions.emplace_back(std::move(mubuf));
7548
7549       expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, (1 << last_bit) - 1);
7550       return;
7551    }
7552
7553    /* gather MIMG address components */
7554    std::vector<Temp> args;
7555    if (has_offset)
7556       args.emplace_back(offset);
7557    if (has_bias)
7558       args.emplace_back(bias);
7559    if (has_compare)
7560       args.emplace_back(compare);
7561    if (has_derivs)
7562       args.insert(args.end(), derivs.begin(), derivs.end());
7563
7564    args.insert(args.end(), coords.begin(), coords.end());
7565    if (has_sample_index)
7566       args.emplace_back(sample_index);
7567    if (has_lod)
7568       args.emplace_back(lod);
7569
7570    Temp arg = bld.tmp(RegClass(RegType::vgpr, args.size()));
7571    aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, args.size(), 1)};
7572    vec->definitions[0] = Definition(arg);
7573    for (unsigned i = 0; i < args.size(); i++)
7574       vec->operands[i] = Operand(args[i]);
7575    ctx->block->instructions.emplace_back(std::move(vec));
7576
7577
7578    if (instr->op == nir_texop_txf ||
7579        instr->op == nir_texop_txf_ms ||
7580        instr->op == nir_texop_samples_identical ||
7581        instr->op == nir_texop_fragment_fetch ||
7582        instr->op == nir_texop_fragment_mask_fetch) {
7583       aco_opcode op = level_zero || instr->sampler_dim == GLSL_SAMPLER_DIM_MS || instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS ? aco_opcode::image_load : aco_opcode::image_load_mip;
7584       tex.reset(create_instruction<MIMG_instruction>(op, Format::MIMG, 3, 1));
7585       tex->operands[0] = Operand(resource);
7586       tex->operands[1] = Operand(s4); /* no sampler */
7587       tex->operands[2] = Operand(arg);
7588       tex->dim = dim;
7589       tex->dmask = dmask;
7590       tex->unrm = true;
7591       tex->da = da;
7592       tex->definitions[0] = Definition(tmp_dst);
7593       tex->can_reorder = true;
7594       ctx->block->instructions.emplace_back(std::move(tex));
7595
7596       if (instr->op == nir_texop_samples_identical) {
7597          assert(dmask == 1 && dst.regClass() == v1);
7598          assert(dst.id() != tmp_dst.id());
7599
7600          Temp tmp = bld.tmp(bld.lm);
7601          bld.vopc(aco_opcode::v_cmp_eq_u32, Definition(tmp), Operand(0u), tmp_dst).def(0).setHint(vcc);
7602          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand((uint32_t)-1), tmp);
7603
7604       } else {
7605          expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, dmask);
7606       }
7607       return;
7608    }
7609
7610    // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
7611    aco_opcode opcode = aco_opcode::image_sample;
7612    if (has_offset) { /* image_sample_*_o */
7613       if (has_compare) {
7614          opcode = aco_opcode::image_sample_c_o;
7615          if (has_derivs)
7616             opcode = aco_opcode::image_sample_c_d_o;
7617          if (has_bias)
7618             opcode = aco_opcode::image_sample_c_b_o;
7619          if (level_zero)
7620             opcode = aco_opcode::image_sample_c_lz_o;
7621          if (has_lod)
7622             opcode = aco_opcode::image_sample_c_l_o;
7623       } else {
7624          opcode = aco_opcode::image_sample_o;
7625          if (has_derivs)
7626             opcode = aco_opcode::image_sample_d_o;
7627          if (has_bias)
7628             opcode = aco_opcode::image_sample_b_o;
7629          if (level_zero)
7630             opcode = aco_opcode::image_sample_lz_o;
7631          if (has_lod)
7632             opcode = aco_opcode::image_sample_l_o;
7633       }
7634    } else { /* no offset */
7635       if (has_compare) {
7636          opcode = aco_opcode::image_sample_c;
7637          if (has_derivs)
7638             opcode = aco_opcode::image_sample_c_d;
7639          if (has_bias)
7640             opcode = aco_opcode::image_sample_c_b;
7641          if (level_zero)
7642             opcode = aco_opcode::image_sample_c_lz;
7643          if (has_lod)
7644             opcode = aco_opcode::image_sample_c_l;
7645       } else {
7646          opcode = aco_opcode::image_sample;
7647          if (has_derivs)
7648             opcode = aco_opcode::image_sample_d;
7649          if (has_bias)
7650             opcode = aco_opcode::image_sample_b;
7651          if (level_zero)
7652             opcode = aco_opcode::image_sample_lz;
7653          if (has_lod)
7654             opcode = aco_opcode::image_sample_l;
7655       }
7656    }
7657
7658    if (instr->op == nir_texop_tg4) {
7659       if (has_offset) {
7660          opcode = aco_opcode::image_gather4_lz_o;
7661          if (has_compare)
7662             opcode = aco_opcode::image_gather4_c_lz_o;
7663       } else {
7664          opcode = aco_opcode::image_gather4_lz;
7665          if (has_compare)
7666             opcode = aco_opcode::image_gather4_c_lz;
7667       }
7668    } else if (instr->op == nir_texop_lod) {
7669       opcode = aco_opcode::image_get_lod;
7670    }
7671
7672    /* we don't need the bias, sample index, compare value or offset to be
7673     * computed in WQM but if the p_create_vector copies the coordinates, then it
7674     * needs to be in WQM */
7675    if (ctx->stage == fragment_fs &&
7676        !has_derivs && !has_lod && !level_zero &&
7677        instr->sampler_dim != GLSL_SAMPLER_DIM_MS &&
7678        instr->sampler_dim != GLSL_SAMPLER_DIM_SUBPASS_MS)
7679       arg = emit_wqm(ctx, arg, bld.tmp(arg.regClass()), true);
7680
7681    tex.reset(create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 1));
7682    tex->operands[0] = Operand(resource);
7683    tex->operands[1] = Operand(sampler);
7684    tex->operands[2] = Operand(arg);
7685    tex->dim = dim;
7686    tex->dmask = dmask;
7687    tex->da = da;
7688    tex->definitions[0] = Definition(tmp_dst);
7689    tex->can_reorder = true;
7690    ctx->block->instructions.emplace_back(std::move(tex));
7691
7692    if (tg4_integer_cube_workaround) {
7693       assert(tmp_dst.id() != dst.id());
7694       assert(tmp_dst.size() == dst.size() && dst.size() == 4);
7695
7696       emit_split_vector(ctx, tmp_dst, tmp_dst.size());
7697       Temp val[4];
7698       for (unsigned i = 0; i < dst.size(); i++) {
7699          val[i] = emit_extract_vector(ctx, tmp_dst, i, v1);
7700          Temp cvt_val;
7701          if (stype == GLSL_TYPE_UINT)
7702             cvt_val = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), val[i]);
7703          else
7704             cvt_val = bld.vop1(aco_opcode::v_cvt_i32_f32, bld.def(v1), val[i]);
7705          val[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), val[i], cvt_val, tg4_compare_cube_wa64);
7706       }
7707       Temp tmp = dst.regClass() == v4 ? dst : bld.tmp(v4);
7708       tmp_dst = bld.pseudo(aco_opcode::p_create_vector, Definition(tmp),
7709                            val[0], val[1], val[2], val[3]);
7710    }
7711    unsigned mask = instr->op == nir_texop_tg4 ? 0xF : dmask;
7712    expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, mask);
7713
7714 }
7715
7716
7717 Operand get_phi_operand(isel_context *ctx, nir_ssa_def *ssa)
7718 {
7719    Temp tmp = get_ssa_temp(ctx, ssa);
7720    if (ssa->parent_instr->type == nir_instr_type_ssa_undef)
7721       return Operand(tmp.regClass());
7722    else
7723       return Operand(tmp);
7724 }
7725
7726 void visit_phi(isel_context *ctx, nir_phi_instr *instr)
7727 {
7728    aco_ptr<Pseudo_instruction> phi;
7729    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7730    assert(instr->dest.ssa.bit_size != 1 || dst.regClass() == ctx->program->lane_mask);
7731
7732    bool logical = !dst.is_linear() || ctx->divergent_vals[instr->dest.ssa.index];
7733    logical |= ctx->block->kind & block_kind_merge;
7734    aco_opcode opcode = logical ? aco_opcode::p_phi : aco_opcode::p_linear_phi;
7735
7736    /* we want a sorted list of sources, since the predecessor list is also sorted */
7737    std::map<unsigned, nir_ssa_def*> phi_src;
7738    nir_foreach_phi_src(src, instr)
7739       phi_src[src->pred->index] = src->src.ssa;
7740
7741    std::vector<unsigned>& preds = logical ? ctx->block->logical_preds : ctx->block->linear_preds;
7742    unsigned num_operands = 0;
7743    Operand operands[std::max(exec_list_length(&instr->srcs), (unsigned)preds.size())];
7744    unsigned num_defined = 0;
7745    unsigned cur_pred_idx = 0;
7746    for (std::pair<unsigned, nir_ssa_def *> src : phi_src) {
7747       if (cur_pred_idx < preds.size()) {
7748          /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
7749          unsigned block = ctx->cf_info.nir_to_aco[src.first];
7750          unsigned skipped = 0;
7751          while (cur_pred_idx + skipped < preds.size() && preds[cur_pred_idx + skipped] != block)
7752             skipped++;
7753          if (cur_pred_idx + skipped < preds.size()) {
7754             for (unsigned i = 0; i < skipped; i++)
7755                operands[num_operands++] = Operand(dst.regClass());
7756             cur_pred_idx += skipped;
7757          } else {
7758             continue;
7759          }
7760       }
7761       cur_pred_idx++;
7762       Operand op = get_phi_operand(ctx, src.second);
7763       operands[num_operands++] = op;
7764       num_defined += !op.isUndefined();
7765    }
7766    /* handle block_kind_continue_or_break at loop exit blocks */
7767    while (cur_pred_idx++ < preds.size())
7768       operands[num_operands++] = Operand(dst.regClass());
7769
7770    if (num_defined == 0) {
7771       Builder bld(ctx->program, ctx->block);
7772       if (dst.regClass() == s1) {
7773          bld.sop1(aco_opcode::s_mov_b32, Definition(dst), Operand(0u));
7774       } else if (dst.regClass() == v1) {
7775          bld.vop1(aco_opcode::v_mov_b32, Definition(dst), Operand(0u));
7776       } else {
7777          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
7778          for (unsigned i = 0; i < dst.size(); i++)
7779             vec->operands[i] = Operand(0u);
7780          vec->definitions[0] = Definition(dst);
7781          ctx->block->instructions.emplace_back(std::move(vec));
7782       }
7783       return;
7784    }
7785
7786    /* we can use a linear phi in some cases if one src is undef */
7787    if (dst.is_linear() && ctx->block->kind & block_kind_merge && num_defined == 1) {
7788       phi.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_linear_phi, Format::PSEUDO, num_operands, 1));
7789
7790       Block *linear_else = &ctx->program->blocks[ctx->block->linear_preds[1]];
7791       Block *invert = &ctx->program->blocks[linear_else->linear_preds[0]];
7792       assert(invert->kind & block_kind_invert);
7793
7794       unsigned then_block = invert->linear_preds[0];
7795
7796       Block* insert_block = NULL;
7797       for (unsigned i = 0; i < num_operands; i++) {
7798          Operand op = operands[i];
7799          if (op.isUndefined())
7800             continue;
7801          insert_block = ctx->block->logical_preds[i] == then_block ? invert : ctx->block;
7802          phi->operands[0] = op;
7803          break;
7804       }
7805       assert(insert_block); /* should be handled by the "num_defined == 0" case above */
7806       phi->operands[1] = Operand(dst.regClass());
7807       phi->definitions[0] = Definition(dst);
7808       insert_block->instructions.emplace(insert_block->instructions.begin(), std::move(phi));
7809       return;
7810    }
7811
7812    /* try to scalarize vector phis */
7813    if (instr->dest.ssa.bit_size != 1 && dst.size() > 1) {
7814       // TODO: scalarize linear phis on divergent ifs
7815       bool can_scalarize = (opcode == aco_opcode::p_phi || !(ctx->block->kind & block_kind_merge));
7816       std::array<Temp, NIR_MAX_VEC_COMPONENTS> new_vec;
7817       for (unsigned i = 0; can_scalarize && (i < num_operands); i++) {
7818          Operand src = operands[i];
7819          if (src.isTemp() && ctx->allocated_vec.find(src.tempId()) == ctx->allocated_vec.end())
7820             can_scalarize = false;
7821       }
7822       if (can_scalarize) {
7823          unsigned num_components = instr->dest.ssa.num_components;
7824          assert(dst.size() % num_components == 0);
7825          RegClass rc = RegClass(dst.type(), dst.size() / num_components);
7826
7827          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1)};
7828          for (unsigned k = 0; k < num_components; k++) {
7829             phi.reset(create_instruction<Pseudo_instruction>(opcode, Format::PSEUDO, num_operands, 1));
7830             for (unsigned i = 0; i < num_operands; i++) {
7831                Operand src = operands[i];
7832                phi->operands[i] = src.isTemp() ? Operand(ctx->allocated_vec[src.tempId()][k]) : Operand(rc);
7833             }
7834             Temp phi_dst = {ctx->program->allocateId(), rc};
7835             phi->definitions[0] = Definition(phi_dst);
7836             ctx->block->instructions.emplace(ctx->block->instructions.begin(), std::move(phi));
7837             new_vec[k] = phi_dst;
7838             vec->operands[k] = Operand(phi_dst);
7839          }
7840          vec->definitions[0] = Definition(dst);
7841          ctx->block->instructions.emplace_back(std::move(vec));
7842          ctx->allocated_vec.emplace(dst.id(), new_vec);
7843          return;
7844       }
7845    }
7846
7847    phi.reset(create_instruction<Pseudo_instruction>(opcode, Format::PSEUDO, num_operands, 1));
7848    for (unsigned i = 0; i < num_operands; i++)
7849       phi->operands[i] = operands[i];
7850    phi->definitions[0] = Definition(dst);
7851    ctx->block->instructions.emplace(ctx->block->instructions.begin(), std::move(phi));
7852 }
7853
7854
7855 void visit_undef(isel_context *ctx, nir_ssa_undef_instr *instr)
7856 {
7857    Temp dst = get_ssa_temp(ctx, &instr->def);
7858
7859    assert(dst.type() == RegType::sgpr);
7860
7861    if (dst.size() == 1) {
7862       Builder(ctx->program, ctx->block).copy(Definition(dst), Operand(0u));
7863    } else {
7864       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
7865       for (unsigned i = 0; i < dst.size(); i++)
7866          vec->operands[i] = Operand(0u);
7867       vec->definitions[0] = Definition(dst);
7868       ctx->block->instructions.emplace_back(std::move(vec));
7869    }
7870 }
7871
7872 void visit_jump(isel_context *ctx, nir_jump_instr *instr)
7873 {
7874    Builder bld(ctx->program, ctx->block);
7875    Block *logical_target;
7876    append_logical_end(ctx->block);
7877    unsigned idx = ctx->block->index;
7878
7879    switch (instr->type) {
7880    case nir_jump_break:
7881       logical_target = ctx->cf_info.parent_loop.exit;
7882       add_logical_edge(idx, logical_target);
7883       ctx->block->kind |= block_kind_break;
7884
7885       if (!ctx->cf_info.parent_if.is_divergent &&
7886           !ctx->cf_info.parent_loop.has_divergent_continue) {
7887          /* uniform break - directly jump out of the loop */
7888          ctx->block->kind |= block_kind_uniform;
7889          ctx->cf_info.has_branch = true;
7890          bld.branch(aco_opcode::p_branch);
7891          add_linear_edge(idx, logical_target);
7892          return;
7893       }
7894       ctx->cf_info.parent_loop.has_divergent_branch = true;
7895       ctx->cf_info.nir_to_aco[instr->instr.block->index] = ctx->block->index;
7896       break;
7897    case nir_jump_continue:
7898       logical_target = &ctx->program->blocks[ctx->cf_info.parent_loop.header_idx];
7899       add_logical_edge(idx, logical_target);
7900       ctx->block->kind |= block_kind_continue;
7901
7902       if (ctx->cf_info.parent_if.is_divergent) {
7903          /* for potential uniform breaks after this continue,
7904             we must ensure that they are handled correctly */
7905          ctx->cf_info.parent_loop.has_divergent_continue = true;
7906          ctx->cf_info.parent_loop.has_divergent_branch = true;
7907          ctx->cf_info.nir_to_aco[instr->instr.block->index] = ctx->block->index;
7908       } else {
7909          /* uniform continue - directly jump to the loop header */
7910          ctx->block->kind |= block_kind_uniform;
7911          ctx->cf_info.has_branch = true;
7912          bld.branch(aco_opcode::p_branch);
7913          add_linear_edge(idx, logical_target);
7914          return;
7915       }
7916       break;
7917    default:
7918       fprintf(stderr, "Unknown NIR jump instr: ");
7919       nir_print_instr(&instr->instr, stderr);
7920       fprintf(stderr, "\n");
7921       abort();
7922    }
7923
7924    if (ctx->cf_info.parent_if.is_divergent && !ctx->cf_info.exec_potentially_empty_break) {
7925       ctx->cf_info.exec_potentially_empty_break = true;
7926       ctx->cf_info.exec_potentially_empty_break_depth = ctx->cf_info.loop_nest_depth;
7927    }
7928
7929    /* remove critical edges from linear CFG */
7930    bld.branch(aco_opcode::p_branch);
7931    Block* break_block = ctx->program->create_and_insert_block();
7932    break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7933    break_block->kind |= block_kind_uniform;
7934    add_linear_edge(idx, break_block);
7935    /* the loop_header pointer might be invalidated by this point */
7936    if (instr->type == nir_jump_continue)
7937       logical_target = &ctx->program->blocks[ctx->cf_info.parent_loop.header_idx];
7938    add_linear_edge(break_block->index, logical_target);
7939    bld.reset(break_block);
7940    bld.branch(aco_opcode::p_branch);
7941
7942    Block* continue_block = ctx->program->create_and_insert_block();
7943    continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7944    add_linear_edge(idx, continue_block);
7945    append_logical_start(continue_block);
7946    ctx->block = continue_block;
7947    return;
7948 }
7949
7950 void visit_block(isel_context *ctx, nir_block *block)
7951 {
7952    nir_foreach_instr(instr, block) {
7953       switch (instr->type) {
7954       case nir_instr_type_alu:
7955          visit_alu_instr(ctx, nir_instr_as_alu(instr));
7956          break;
7957       case nir_instr_type_load_const:
7958          visit_load_const(ctx, nir_instr_as_load_const(instr));
7959          break;
7960       case nir_instr_type_intrinsic:
7961          visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
7962          break;
7963       case nir_instr_type_tex:
7964          visit_tex(ctx, nir_instr_as_tex(instr));
7965          break;
7966       case nir_instr_type_phi:
7967          visit_phi(ctx, nir_instr_as_phi(instr));
7968          break;
7969       case nir_instr_type_ssa_undef:
7970          visit_undef(ctx, nir_instr_as_ssa_undef(instr));
7971          break;
7972       case nir_instr_type_deref:
7973          break;
7974       case nir_instr_type_jump:
7975          visit_jump(ctx, nir_instr_as_jump(instr));
7976          break;
7977       default:
7978          fprintf(stderr, "Unknown NIR instr type: ");
7979          nir_print_instr(instr, stderr);
7980          fprintf(stderr, "\n");
7981          //abort();
7982       }
7983    }
7984
7985    if (!ctx->cf_info.parent_loop.has_divergent_branch)
7986       ctx->cf_info.nir_to_aco[block->index] = ctx->block->index;
7987 }
7988
7989
7990
7991 static void visit_loop(isel_context *ctx, nir_loop *loop)
7992 {
7993    //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
7994    append_logical_end(ctx->block);
7995    ctx->block->kind |= block_kind_loop_preheader | block_kind_uniform;
7996    Builder bld(ctx->program, ctx->block);
7997    bld.branch(aco_opcode::p_branch);
7998    unsigned loop_preheader_idx = ctx->block->index;
7999
8000    Block loop_exit = Block();
8001    loop_exit.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8002    loop_exit.kind |= (block_kind_loop_exit | (ctx->block->kind & block_kind_top_level));
8003
8004    Block* loop_header = ctx->program->create_and_insert_block();
8005    loop_header->loop_nest_depth = ctx->cf_info.loop_nest_depth + 1;
8006    loop_header->kind |= block_kind_loop_header;
8007    add_edge(loop_preheader_idx, loop_header);
8008    ctx->block = loop_header;
8009
8010    /* emit loop body */
8011    unsigned loop_header_idx = loop_header->index;
8012    loop_info_RAII loop_raii(ctx, loop_header_idx, &loop_exit);
8013    append_logical_start(ctx->block);
8014    visit_cf_list(ctx, &loop->body);
8015
8016    //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
8017    if (!ctx->cf_info.has_branch) {
8018       append_logical_end(ctx->block);
8019       if (ctx->cf_info.exec_potentially_empty_discard || ctx->cf_info.exec_potentially_empty_break) {
8020          /* Discards can result in code running with an empty exec mask.
8021           * This would result in divergent breaks not ever being taken. As a
8022           * workaround, break the loop when the loop mask is empty instead of
8023           * always continuing. */
8024          ctx->block->kind |= (block_kind_continue_or_break | block_kind_uniform);
8025          unsigned block_idx = ctx->block->index;
8026
8027          /* create helper blocks to avoid critical edges */
8028          Block *break_block = ctx->program->create_and_insert_block();
8029          break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8030          break_block->kind = block_kind_uniform;
8031          bld.reset(break_block);
8032          bld.branch(aco_opcode::p_branch);
8033          add_linear_edge(block_idx, break_block);
8034          add_linear_edge(break_block->index, &loop_exit);
8035
8036          Block *continue_block = ctx->program->create_and_insert_block();
8037          continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8038          continue_block->kind = block_kind_uniform;
8039          bld.reset(continue_block);
8040          bld.branch(aco_opcode::p_branch);
8041          add_linear_edge(block_idx, continue_block);
8042          add_linear_edge(continue_block->index, &ctx->program->blocks[loop_header_idx]);
8043
8044          if (!ctx->cf_info.parent_loop.has_divergent_branch)
8045             add_logical_edge(block_idx, &ctx->program->blocks[loop_header_idx]);
8046          ctx->block = &ctx->program->blocks[block_idx];
8047       } else {
8048          ctx->block->kind |= (block_kind_continue | block_kind_uniform);
8049          if (!ctx->cf_info.parent_loop.has_divergent_branch)
8050             add_edge(ctx->block->index, &ctx->program->blocks[loop_header_idx]);
8051          else
8052             add_linear_edge(ctx->block->index, &ctx->program->blocks[loop_header_idx]);
8053       }
8054
8055       bld.reset(ctx->block);
8056       bld.branch(aco_opcode::p_branch);
8057    }
8058
8059    /* fixup phis in loop header from unreachable blocks */
8060    if (ctx->cf_info.has_branch || ctx->cf_info.parent_loop.has_divergent_branch) {
8061       bool linear = ctx->cf_info.has_branch;
8062       bool logical = ctx->cf_info.has_branch || ctx->cf_info.parent_loop.has_divergent_branch;
8063       for (aco_ptr<Instruction>& instr : ctx->program->blocks[loop_header_idx].instructions) {
8064          if ((logical && instr->opcode == aco_opcode::p_phi) ||
8065              (linear && instr->opcode == aco_opcode::p_linear_phi)) {
8066             /* the last operand should be the one that needs to be removed */
8067             instr->operands.pop_back();
8068          } else if (!is_phi(instr)) {
8069             break;
8070          }
8071       }
8072    }
8073
8074    ctx->cf_info.has_branch = false;
8075
8076    // TODO: if the loop has not a single exit, we must add one °°
8077    /* emit loop successor block */
8078    ctx->block = ctx->program->insert_block(std::move(loop_exit));
8079    append_logical_start(ctx->block);
8080
8081    #if 0
8082    // TODO: check if it is beneficial to not branch on continues
8083    /* trim linear phis in loop header */
8084    for (auto&& instr : loop_entry->instructions) {
8085       if (instr->opcode == aco_opcode::p_linear_phi) {
8086          aco_ptr<Pseudo_instruction> new_phi{create_instruction<Pseudo_instruction>(aco_opcode::p_linear_phi, Format::PSEUDO, loop_entry->linear_predecessors.size(), 1)};
8087          new_phi->definitions[0] = instr->definitions[0];
8088          for (unsigned i = 0; i < new_phi->operands.size(); i++)
8089             new_phi->operands[i] = instr->operands[i];
8090          /* check that the remaining operands are all the same */
8091          for (unsigned i = new_phi->operands.size(); i < instr->operands.size(); i++)
8092             assert(instr->operands[i].tempId() == instr->operands.back().tempId());
8093          instr.swap(new_phi);
8094       } else if (instr->opcode == aco_opcode::p_phi) {
8095          continue;
8096       } else {
8097          break;
8098       }
8099    }
8100    #endif
8101 }
8102
8103 static void begin_divergent_if_then(isel_context *ctx, if_context *ic, Temp cond)
8104 {
8105    ic->cond = cond;
8106
8107    append_logical_end(ctx->block);
8108    ctx->block->kind |= block_kind_branch;
8109
8110    /* branch to linear then block */
8111    assert(cond.regClass() == ctx->program->lane_mask);
8112    aco_ptr<Pseudo_branch_instruction> branch;
8113    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_z, Format::PSEUDO_BRANCH, 1, 0));
8114    branch->operands[0] = Operand(cond);
8115    ctx->block->instructions.push_back(std::move(branch));
8116
8117    ic->BB_if_idx = ctx->block->index;
8118    ic->BB_invert = Block();
8119    ic->BB_invert.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8120    /* Invert blocks are intentionally not marked as top level because they
8121     * are not part of the logical cfg. */
8122    ic->BB_invert.kind |= block_kind_invert;
8123    ic->BB_endif = Block();
8124    ic->BB_endif.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8125    ic->BB_endif.kind |= (block_kind_merge | (ctx->block->kind & block_kind_top_level));
8126
8127    ic->exec_potentially_empty_discard_old = ctx->cf_info.exec_potentially_empty_discard;
8128    ic->exec_potentially_empty_break_old = ctx->cf_info.exec_potentially_empty_break;
8129    ic->exec_potentially_empty_break_depth_old = ctx->cf_info.exec_potentially_empty_break_depth;
8130    ic->divergent_old = ctx->cf_info.parent_if.is_divergent;
8131    ctx->cf_info.parent_if.is_divergent = true;
8132
8133    /* divergent branches use cbranch_execz */
8134    ctx->cf_info.exec_potentially_empty_discard = false;
8135    ctx->cf_info.exec_potentially_empty_break = false;
8136    ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8137
8138    /** emit logical then block */
8139    Block* BB_then_logical = ctx->program->create_and_insert_block();
8140    BB_then_logical->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8141    add_edge(ic->BB_if_idx, BB_then_logical);
8142    ctx->block = BB_then_logical;
8143    append_logical_start(BB_then_logical);
8144 }
8145
8146 static void begin_divergent_if_else(isel_context *ctx, if_context *ic)
8147 {
8148    Block *BB_then_logical = ctx->block;
8149    append_logical_end(BB_then_logical);
8150     /* branch from logical then block to invert block */
8151    aco_ptr<Pseudo_branch_instruction> branch;
8152    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8153    BB_then_logical->instructions.emplace_back(std::move(branch));
8154    add_linear_edge(BB_then_logical->index, &ic->BB_invert);
8155    if (!ctx->cf_info.parent_loop.has_divergent_branch)
8156       add_logical_edge(BB_then_logical->index, &ic->BB_endif);
8157    BB_then_logical->kind |= block_kind_uniform;
8158    assert(!ctx->cf_info.has_branch);
8159    ic->then_branch_divergent = ctx->cf_info.parent_loop.has_divergent_branch;
8160    ctx->cf_info.parent_loop.has_divergent_branch = false;
8161
8162    /** emit linear then block */
8163    Block* BB_then_linear = ctx->program->create_and_insert_block();
8164    BB_then_linear->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8165    BB_then_linear->kind |= block_kind_uniform;
8166    add_linear_edge(ic->BB_if_idx, BB_then_linear);
8167    /* branch from linear then block to invert block */
8168    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8169    BB_then_linear->instructions.emplace_back(std::move(branch));
8170    add_linear_edge(BB_then_linear->index, &ic->BB_invert);
8171
8172    /** emit invert merge block */
8173    ctx->block = ctx->program->insert_block(std::move(ic->BB_invert));
8174    ic->invert_idx = ctx->block->index;
8175
8176    /* branch to linear else block (skip else) */
8177    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_nz, Format::PSEUDO_BRANCH, 1, 0));
8178    branch->operands[0] = Operand(ic->cond);
8179    ctx->block->instructions.push_back(std::move(branch));
8180
8181    ic->exec_potentially_empty_discard_old |= ctx->cf_info.exec_potentially_empty_discard;
8182    ic->exec_potentially_empty_break_old |= ctx->cf_info.exec_potentially_empty_break;
8183    ic->exec_potentially_empty_break_depth_old =
8184       std::min(ic->exec_potentially_empty_break_depth_old, ctx->cf_info.exec_potentially_empty_break_depth);
8185    /* divergent branches use cbranch_execz */
8186    ctx->cf_info.exec_potentially_empty_discard = false;
8187    ctx->cf_info.exec_potentially_empty_break = false;
8188    ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8189
8190    /** emit logical else block */
8191    Block* BB_else_logical = ctx->program->create_and_insert_block();
8192    BB_else_logical->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8193    add_logical_edge(ic->BB_if_idx, BB_else_logical);
8194    add_linear_edge(ic->invert_idx, BB_else_logical);
8195    ctx->block = BB_else_logical;
8196    append_logical_start(BB_else_logical);
8197 }
8198
8199 static void end_divergent_if(isel_context *ctx, if_context *ic)
8200 {
8201    Block *BB_else_logical = ctx->block;
8202    append_logical_end(BB_else_logical);
8203
8204    /* branch from logical else block to endif block */
8205    aco_ptr<Pseudo_branch_instruction> branch;
8206    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8207    BB_else_logical->instructions.emplace_back(std::move(branch));
8208    add_linear_edge(BB_else_logical->index, &ic->BB_endif);
8209    if (!ctx->cf_info.parent_loop.has_divergent_branch)
8210       add_logical_edge(BB_else_logical->index, &ic->BB_endif);
8211    BB_else_logical->kind |= block_kind_uniform;
8212
8213    assert(!ctx->cf_info.has_branch);
8214    ctx->cf_info.parent_loop.has_divergent_branch &= ic->then_branch_divergent;
8215
8216
8217    /** emit linear else block */
8218    Block* BB_else_linear = ctx->program->create_and_insert_block();
8219    BB_else_linear->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8220    BB_else_linear->kind |= block_kind_uniform;
8221    add_linear_edge(ic->invert_idx, BB_else_linear);
8222
8223    /* branch from linear else block to endif block */
8224    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8225    BB_else_linear->instructions.emplace_back(std::move(branch));
8226    add_linear_edge(BB_else_linear->index, &ic->BB_endif);
8227
8228
8229    /** emit endif merge block */
8230    ctx->block = ctx->program->insert_block(std::move(ic->BB_endif));
8231    append_logical_start(ctx->block);
8232
8233
8234    ctx->cf_info.parent_if.is_divergent = ic->divergent_old;
8235    ctx->cf_info.exec_potentially_empty_discard |= ic->exec_potentially_empty_discard_old;
8236    ctx->cf_info.exec_potentially_empty_break |= ic->exec_potentially_empty_break_old;
8237    ctx->cf_info.exec_potentially_empty_break_depth =
8238       std::min(ic->exec_potentially_empty_break_depth_old, ctx->cf_info.exec_potentially_empty_break_depth);
8239    if (ctx->cf_info.loop_nest_depth == ctx->cf_info.exec_potentially_empty_break_depth &&
8240        !ctx->cf_info.parent_if.is_divergent) {
8241       ctx->cf_info.exec_potentially_empty_break = false;
8242       ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8243    }
8244    /* uniform control flow never has an empty exec-mask */
8245    if (!ctx->cf_info.loop_nest_depth && !ctx->cf_info.parent_if.is_divergent) {
8246       ctx->cf_info.exec_potentially_empty_discard = false;
8247       ctx->cf_info.exec_potentially_empty_break = false;
8248       ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8249    }
8250 }
8251
8252 static void visit_if(isel_context *ctx, nir_if *if_stmt)
8253 {
8254    Temp cond = get_ssa_temp(ctx, if_stmt->condition.ssa);
8255    Builder bld(ctx->program, ctx->block);
8256    aco_ptr<Pseudo_branch_instruction> branch;
8257
8258    if (!ctx->divergent_vals[if_stmt->condition.ssa->index]) { /* uniform condition */
8259       /**
8260        * Uniform conditionals are represented in the following way*) :
8261        *
8262        * The linear and logical CFG:
8263        *                        BB_IF
8264        *                        /    \
8265        *       BB_THEN (logical)      BB_ELSE (logical)
8266        *                        \    /
8267        *                        BB_ENDIF
8268        *
8269        * *) Exceptions may be due to break and continue statements within loops
8270        *    If a break/continue happens within uniform control flow, it branches
8271        *    to the loop exit/entry block. Otherwise, it branches to the next
8272        *    merge block.
8273        **/
8274       append_logical_end(ctx->block);
8275       ctx->block->kind |= block_kind_uniform;
8276
8277       /* emit branch */
8278       assert(cond.regClass() == bld.lm);
8279       // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
8280       cond = bool_to_scalar_condition(ctx, cond);
8281
8282       branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_z, Format::PSEUDO_BRANCH, 1, 0));
8283       branch->operands[0] = Operand(cond);
8284       branch->operands[0].setFixed(scc);
8285       ctx->block->instructions.emplace_back(std::move(branch));
8286
8287       unsigned BB_if_idx = ctx->block->index;
8288       Block BB_endif = Block();
8289       BB_endif.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8290       BB_endif.kind |= ctx->block->kind & block_kind_top_level;
8291
8292       /** emit then block */
8293       Block* BB_then = ctx->program->create_and_insert_block();
8294       BB_then->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8295       add_edge(BB_if_idx, BB_then);
8296       append_logical_start(BB_then);
8297       ctx->block = BB_then;
8298       visit_cf_list(ctx, &if_stmt->then_list);
8299       BB_then = ctx->block;
8300       bool then_branch = ctx->cf_info.has_branch;
8301       bool then_branch_divergent = ctx->cf_info.parent_loop.has_divergent_branch;
8302
8303       if (!then_branch) {
8304          append_logical_end(BB_then);
8305          /* branch from then block to endif block */
8306          branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8307          BB_then->instructions.emplace_back(std::move(branch));
8308          add_linear_edge(BB_then->index, &BB_endif);
8309          if (!then_branch_divergent)
8310             add_logical_edge(BB_then->index, &BB_endif);
8311          BB_then->kind |= block_kind_uniform;
8312       }
8313
8314       ctx->cf_info.has_branch = false;
8315       ctx->cf_info.parent_loop.has_divergent_branch = false;
8316
8317       /** emit else block */
8318       Block* BB_else = ctx->program->create_and_insert_block();
8319       BB_else->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8320       add_edge(BB_if_idx, BB_else);
8321       append_logical_start(BB_else);
8322       ctx->block = BB_else;
8323       visit_cf_list(ctx, &if_stmt->else_list);
8324       BB_else = ctx->block;
8325
8326       if (!ctx->cf_info.has_branch) {
8327          append_logical_end(BB_else);
8328          /* branch from then block to endif block */
8329          branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8330          BB_else->instructions.emplace_back(std::move(branch));
8331          add_linear_edge(BB_else->index, &BB_endif);
8332          if (!ctx->cf_info.parent_loop.has_divergent_branch)
8333             add_logical_edge(BB_else->index, &BB_endif);
8334          BB_else->kind |= block_kind_uniform;
8335       }
8336
8337       ctx->cf_info.has_branch &= then_branch;
8338       ctx->cf_info.parent_loop.has_divergent_branch &= then_branch_divergent;
8339
8340       /** emit endif merge block */
8341       if (!ctx->cf_info.has_branch) {
8342          ctx->block = ctx->program->insert_block(std::move(BB_endif));
8343          append_logical_start(ctx->block);
8344       }
8345    } else { /* non-uniform condition */
8346       /**
8347        * To maintain a logical and linear CFG without critical edges,
8348        * non-uniform conditionals are represented in the following way*) :
8349        *
8350        * The linear CFG:
8351        *                        BB_IF
8352        *                        /    \
8353        *       BB_THEN (logical)      BB_THEN (linear)
8354        *                        \    /
8355        *                        BB_INVERT (linear)
8356        *                        /    \
8357        *       BB_ELSE (logical)      BB_ELSE (linear)
8358        *                        \    /
8359        *                        BB_ENDIF
8360        *
8361        * The logical CFG:
8362        *                        BB_IF
8363        *                        /    \
8364        *       BB_THEN (logical)      BB_ELSE (logical)
8365        *                        \    /
8366        *                        BB_ENDIF
8367        *
8368        * *) Exceptions may be due to break and continue statements within loops
8369        **/
8370
8371       if_context ic;
8372
8373       begin_divergent_if_then(ctx, &ic, cond);
8374       visit_cf_list(ctx, &if_stmt->then_list);
8375
8376       begin_divergent_if_else(ctx, &ic);
8377       visit_cf_list(ctx, &if_stmt->else_list);
8378
8379       end_divergent_if(ctx, &ic);
8380    }
8381 }
8382
8383 static void visit_cf_list(isel_context *ctx,
8384                           struct exec_list *list)
8385 {
8386    foreach_list_typed(nir_cf_node, node, node, list) {
8387       switch (node->type) {
8388       case nir_cf_node_block:
8389          visit_block(ctx, nir_cf_node_as_block(node));
8390          break;
8391       case nir_cf_node_if:
8392          visit_if(ctx, nir_cf_node_as_if(node));
8393          break;
8394       case nir_cf_node_loop:
8395          visit_loop(ctx, nir_cf_node_as_loop(node));
8396          break;
8397       default:
8398          unreachable("unimplemented cf list type");
8399       }
8400    }
8401 }
8402
8403 static void export_vs_varying(isel_context *ctx, int slot, bool is_pos, int *next_pos)
8404 {
8405    int offset = ctx->program->info->vs.outinfo.vs_output_param_offset[slot];
8406    uint64_t mask = ctx->outputs.mask[slot];
8407    if (!is_pos && !mask)
8408       return;
8409    if (!is_pos && offset == AC_EXP_PARAM_UNDEFINED)
8410       return;
8411    aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
8412    exp->enabled_mask = mask;
8413    for (unsigned i = 0; i < 4; ++i) {
8414       if (mask & (1 << i))
8415          exp->operands[i] = Operand(ctx->outputs.outputs[slot][i]);
8416       else
8417          exp->operands[i] = Operand(v1);
8418    }
8419    /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
8420     * Setting valid_mask=1 prevents it and has no other effect.
8421     */
8422    exp->valid_mask = ctx->options->chip_class >= GFX10 && is_pos && *next_pos == 0;
8423    exp->done = false;
8424    exp->compressed = false;
8425    if (is_pos)
8426       exp->dest = V_008DFC_SQ_EXP_POS + (*next_pos)++;
8427    else
8428       exp->dest = V_008DFC_SQ_EXP_PARAM + offset;
8429    ctx->block->instructions.emplace_back(std::move(exp));
8430 }
8431
8432 static void export_vs_psiz_layer_viewport(isel_context *ctx, int *next_pos)
8433 {
8434    aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
8435    exp->enabled_mask = 0;
8436    for (unsigned i = 0; i < 4; ++i)
8437       exp->operands[i] = Operand(v1);
8438    if (ctx->outputs.mask[VARYING_SLOT_PSIZ]) {
8439       exp->operands[0] = Operand(ctx->outputs.outputs[VARYING_SLOT_PSIZ][0]);
8440       exp->enabled_mask |= 0x1;
8441    }
8442    if (ctx->outputs.mask[VARYING_SLOT_LAYER]) {
8443       exp->operands[2] = Operand(ctx->outputs.outputs[VARYING_SLOT_LAYER][0]);
8444       exp->enabled_mask |= 0x4;
8445    }
8446    if (ctx->outputs.mask[VARYING_SLOT_VIEWPORT]) {
8447       if (ctx->options->chip_class < GFX9) {
8448          exp->operands[3] = Operand(ctx->outputs.outputs[VARYING_SLOT_VIEWPORT][0]);
8449          exp->enabled_mask |= 0x8;
8450       } else {
8451          Builder bld(ctx->program, ctx->block);
8452
8453          Temp out = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(16u),
8454                              Operand(ctx->outputs.outputs[VARYING_SLOT_VIEWPORT][0]));
8455          if (exp->operands[2].isTemp())
8456             out = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(out), exp->operands[2]);
8457
8458          exp->operands[2] = Operand(out);
8459          exp->enabled_mask |= 0x4;
8460       }
8461    }
8462    exp->valid_mask = ctx->options->chip_class >= GFX10 && *next_pos == 0;
8463    exp->done = false;
8464    exp->compressed = false;
8465    exp->dest = V_008DFC_SQ_EXP_POS + (*next_pos)++;
8466    ctx->block->instructions.emplace_back(std::move(exp));
8467 }
8468
8469 static void create_vs_exports(isel_context *ctx)
8470 {
8471    radv_vs_output_info *outinfo = &ctx->program->info->vs.outinfo;
8472
8473    if (outinfo->export_prim_id) {
8474       ctx->outputs.mask[VARYING_SLOT_PRIMITIVE_ID] |= 0x1;
8475       ctx->outputs.outputs[VARYING_SLOT_PRIMITIVE_ID][0] = get_arg(ctx, ctx->args->vs_prim_id);
8476    }
8477
8478    if (ctx->options->key.has_multiview_view_index) {
8479       ctx->outputs.mask[VARYING_SLOT_LAYER] |= 0x1;
8480       ctx->outputs.outputs[VARYING_SLOT_LAYER][0] = as_vgpr(ctx, get_arg(ctx, ctx->args->ac.view_index));
8481    }
8482
8483    /* the order these position exports are created is important */
8484    int next_pos = 0;
8485    export_vs_varying(ctx, VARYING_SLOT_POS, true, &next_pos);
8486    if (outinfo->writes_pointsize || outinfo->writes_layer || outinfo->writes_viewport_index) {
8487       export_vs_psiz_layer_viewport(ctx, &next_pos);
8488    }
8489    if (ctx->num_clip_distances + ctx->num_cull_distances > 0)
8490       export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST0, true, &next_pos);
8491    if (ctx->num_clip_distances + ctx->num_cull_distances > 4)
8492       export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST1, true, &next_pos);
8493
8494    if (ctx->export_clip_dists) {
8495       if (ctx->num_clip_distances + ctx->num_cull_distances > 0)
8496          export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST0, false, &next_pos);
8497       if (ctx->num_clip_distances + ctx->num_cull_distances > 4)
8498          export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST1, false, &next_pos);
8499    }
8500
8501    for (unsigned i = 0; i <= VARYING_SLOT_VAR31; ++i) {
8502       if (i < VARYING_SLOT_VAR0 && i != VARYING_SLOT_LAYER &&
8503           i != VARYING_SLOT_PRIMITIVE_ID)
8504          continue;
8505
8506       export_vs_varying(ctx, i, false, NULL);
8507    }
8508 }
8509
8510 static void export_fs_mrt_z(isel_context *ctx)
8511 {
8512    Builder bld(ctx->program, ctx->block);
8513    unsigned enabled_channels = 0;
8514    bool compr = false;
8515    Operand values[4];
8516
8517    for (unsigned i = 0; i < 4; ++i) {
8518       values[i] = Operand(v1);
8519    }
8520
8521    /* Both stencil and sample mask only need 16-bits. */
8522    if (!ctx->program->info->ps.writes_z &&
8523        (ctx->program->info->ps.writes_stencil ||
8524         ctx->program->info->ps.writes_sample_mask)) {
8525       compr = true; /* COMPR flag */
8526
8527       if (ctx->program->info->ps.writes_stencil) {
8528          /* Stencil should be in X[23:16]. */
8529          values[0] = Operand(ctx->outputs.outputs[FRAG_RESULT_STENCIL][0]);
8530          values[0] = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(16u), values[0]);
8531          enabled_channels |= 0x3;
8532       }
8533
8534       if (ctx->program->info->ps.writes_sample_mask) {
8535          /* SampleMask should be in Y[15:0]. */
8536          values[1] = Operand(ctx->outputs.outputs[FRAG_RESULT_SAMPLE_MASK][0]);
8537          enabled_channels |= 0xc;
8538      }
8539    } else {
8540       if (ctx->program->info->ps.writes_z) {
8541          values[0] = Operand(ctx->outputs.outputs[FRAG_RESULT_DEPTH][0]);
8542          enabled_channels |= 0x1;
8543       }
8544
8545       if (ctx->program->info->ps.writes_stencil) {
8546          values[1] = Operand(ctx->outputs.outputs[FRAG_RESULT_STENCIL][0]);
8547          enabled_channels |= 0x2;
8548       }
8549
8550       if (ctx->program->info->ps.writes_sample_mask) {
8551          values[2] = Operand(ctx->outputs.outputs[FRAG_RESULT_SAMPLE_MASK][0]);
8552          enabled_channels |= 0x4;
8553       }
8554    }
8555
8556    /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
8557     * writemask component.
8558     */
8559    if (ctx->options->chip_class == GFX6 &&
8560        ctx->options->family != CHIP_OLAND &&
8561        ctx->options->family != CHIP_HAINAN) {
8562             enabled_channels |= 0x1;
8563    }
8564
8565    bld.exp(aco_opcode::exp, values[0], values[1], values[2], values[3],
8566            enabled_channels, V_008DFC_SQ_EXP_MRTZ, compr);
8567 }
8568
8569 static void export_fs_mrt_color(isel_context *ctx, int slot)
8570 {
8571    Builder bld(ctx->program, ctx->block);
8572    unsigned write_mask = ctx->outputs.mask[slot];
8573    Operand values[4];
8574
8575    for (unsigned i = 0; i < 4; ++i) {
8576       if (write_mask & (1 << i)) {
8577          values[i] = Operand(ctx->outputs.outputs[slot][i]);
8578       } else {
8579          values[i] = Operand(v1);
8580       }
8581    }
8582
8583    unsigned target, col_format;
8584    unsigned enabled_channels = 0;
8585    aco_opcode compr_op = (aco_opcode)0;
8586
8587    slot -= FRAG_RESULT_DATA0;
8588    target = V_008DFC_SQ_EXP_MRT + slot;
8589    col_format = (ctx->options->key.fs.col_format >> (4 * slot)) & 0xf;
8590
8591    bool is_int8 = (ctx->options->key.fs.is_int8 >> slot) & 1;
8592    bool is_int10 = (ctx->options->key.fs.is_int10 >> slot) & 1;
8593
8594    switch (col_format)
8595    {
8596    case V_028714_SPI_SHADER_ZERO:
8597       enabled_channels = 0; /* writemask */
8598       target = V_008DFC_SQ_EXP_NULL;
8599       break;
8600
8601    case V_028714_SPI_SHADER_32_R:
8602       enabled_channels = 1;
8603       break;
8604
8605    case V_028714_SPI_SHADER_32_GR:
8606       enabled_channels = 0x3;
8607       break;
8608
8609    case V_028714_SPI_SHADER_32_AR:
8610       if (ctx->options->chip_class >= GFX10) {
8611          /* Special case: on GFX10, the outputs are different for 32_AR */
8612          enabled_channels = 0x3;
8613          values[1] = values[3];
8614          values[3] = Operand(v1);
8615       } else {
8616          enabled_channels = 0x9;
8617       }
8618       break;
8619
8620    case V_028714_SPI_SHADER_FP16_ABGR:
8621       enabled_channels = 0x5;
8622       compr_op = aco_opcode::v_cvt_pkrtz_f16_f32;
8623       break;
8624
8625    case V_028714_SPI_SHADER_UNORM16_ABGR:
8626       enabled_channels = 0x5;
8627       compr_op = aco_opcode::v_cvt_pknorm_u16_f32;
8628       break;
8629
8630    case V_028714_SPI_SHADER_SNORM16_ABGR:
8631       enabled_channels = 0x5;
8632       compr_op = aco_opcode::v_cvt_pknorm_i16_f32;
8633       break;
8634
8635    case V_028714_SPI_SHADER_UINT16_ABGR: {
8636       enabled_channels = 0x5;
8637       compr_op = aco_opcode::v_cvt_pk_u16_u32;
8638       if (is_int8 || is_int10) {
8639          /* clamp */
8640          uint32_t max_rgb = is_int8 ? 255 : is_int10 ? 1023 : 0;
8641          Temp max_rgb_val = bld.copy(bld.def(s1), Operand(max_rgb));
8642
8643          for (unsigned i = 0; i < 4; i++) {
8644             if ((write_mask >> i) & 1) {
8645                values[i] = bld.vop2(aco_opcode::v_min_u32, bld.def(v1),
8646                                     i == 3 && is_int10 ? Operand(3u) : Operand(max_rgb_val),
8647                                     values[i]);
8648             }
8649          }
8650       }
8651       break;
8652    }
8653
8654    case V_028714_SPI_SHADER_SINT16_ABGR:
8655       enabled_channels = 0x5;
8656       compr_op = aco_opcode::v_cvt_pk_i16_i32;
8657       if (is_int8 || is_int10) {
8658          /* clamp */
8659          uint32_t max_rgb = is_int8 ? 127 : is_int10 ? 511 : 0;
8660          uint32_t min_rgb = is_int8 ? -128 :is_int10 ? -512 : 0;
8661          Temp max_rgb_val = bld.copy(bld.def(s1), Operand(max_rgb));
8662          Temp min_rgb_val = bld.copy(bld.def(s1), Operand(min_rgb));
8663
8664          for (unsigned i = 0; i < 4; i++) {
8665             if ((write_mask >> i) & 1) {
8666                values[i] = bld.vop2(aco_opcode::v_min_i32, bld.def(v1),
8667                                     i == 3 && is_int10 ? Operand(1u) : Operand(max_rgb_val),
8668                                     values[i]);
8669                values[i] = bld.vop2(aco_opcode::v_max_i32, bld.def(v1),
8670                                     i == 3 && is_int10 ? Operand(-2u) : Operand(min_rgb_val),
8671                                     values[i]);
8672             }
8673          }
8674       }
8675       break;
8676
8677    case V_028714_SPI_SHADER_32_ABGR:
8678       enabled_channels = 0xF;
8679       break;
8680
8681    default:
8682       break;
8683    }
8684
8685    if (target == V_008DFC_SQ_EXP_NULL)
8686       return;
8687
8688    if ((bool) compr_op) {
8689       for (int i = 0; i < 2; i++) {
8690          /* check if at least one of the values to be compressed is enabled */
8691          unsigned enabled = (write_mask >> (i*2) | write_mask >> (i*2+1)) & 0x1;
8692          if (enabled) {
8693             enabled_channels |= enabled << (i*2);
8694             values[i] = bld.vop3(compr_op, bld.def(v1),
8695                                  values[i*2].isUndefined() ? Operand(0u) : values[i*2],
8696                                  values[i*2+1].isUndefined() ? Operand(0u): values[i*2+1]);
8697          } else {
8698             values[i] = Operand(v1);
8699          }
8700       }
8701       values[2] = Operand(v1);
8702       values[3] = Operand(v1);
8703    } else {
8704       for (int i = 0; i < 4; i++)
8705          values[i] = enabled_channels & (1 << i) ? values[i] : Operand(v1);
8706    }
8707
8708    bld.exp(aco_opcode::exp, values[0], values[1], values[2], values[3],
8709            enabled_channels, target, (bool) compr_op);
8710 }
8711
8712 static void create_fs_exports(isel_context *ctx)
8713 {
8714    /* Export depth, stencil and sample mask. */
8715    if (ctx->outputs.mask[FRAG_RESULT_DEPTH] ||
8716        ctx->outputs.mask[FRAG_RESULT_STENCIL] ||
8717        ctx->outputs.mask[FRAG_RESULT_SAMPLE_MASK]) {
8718       export_fs_mrt_z(ctx);
8719    }
8720
8721    /* Export all color render targets. */
8722    for (unsigned i = FRAG_RESULT_DATA0; i < FRAG_RESULT_DATA7 + 1; ++i) {
8723       if (ctx->outputs.mask[i])
8724          export_fs_mrt_color(ctx, i);
8725    }
8726 }
8727
8728 static void emit_stream_output(isel_context *ctx,
8729                                Temp const *so_buffers,
8730                                Temp const *so_write_offset,
8731                                const struct radv_stream_output *output)
8732 {
8733    unsigned num_comps = util_bitcount(output->component_mask);
8734    unsigned writemask = (1 << num_comps) - 1;
8735    unsigned loc = output->location;
8736    unsigned buf = output->buffer;
8737
8738    assert(num_comps && num_comps <= 4);
8739    if (!num_comps || num_comps > 4)
8740       return;
8741
8742    unsigned start = ffs(output->component_mask) - 1;
8743
8744    Temp out[4];
8745    bool all_undef = true;
8746    assert(ctx->stage == vertex_vs || ctx->stage == gs_copy_vs);
8747    for (unsigned i = 0; i < num_comps; i++) {
8748       out[i] = ctx->outputs.outputs[loc][start + i];
8749       all_undef = all_undef && !out[i].id();
8750    }
8751    if (all_undef)
8752       return;
8753
8754    while (writemask) {
8755       int start, count;
8756       u_bit_scan_consecutive_range(&writemask, &start, &count);
8757       if (count == 3 && ctx->options->chip_class == GFX6) {
8758          /* GFX6 doesn't support storing vec3, split it. */
8759          writemask |= 1u << (start + 2);
8760          count = 2;
8761       }
8762
8763       unsigned offset = output->offset + start * 4;
8764
8765       Temp write_data = {ctx->program->allocateId(), RegClass(RegType::vgpr, count)};
8766       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
8767       for (int i = 0; i < count; ++i)
8768          vec->operands[i] = (ctx->outputs.mask[loc] & 1 << (start + i)) ? Operand(out[start + i]) : Operand(0u);
8769       vec->definitions[0] = Definition(write_data);
8770       ctx->block->instructions.emplace_back(std::move(vec));
8771
8772       aco_opcode opcode;
8773       switch (count) {
8774       case 1:
8775          opcode = aco_opcode::buffer_store_dword;
8776          break;
8777       case 2:
8778          opcode = aco_opcode::buffer_store_dwordx2;
8779          break;
8780       case 3:
8781          opcode = aco_opcode::buffer_store_dwordx3;
8782          break;
8783       case 4:
8784          opcode = aco_opcode::buffer_store_dwordx4;
8785          break;
8786       default:
8787          unreachable("Unsupported dword count.");
8788       }
8789
8790       aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 4, 0)};
8791       store->operands[0] = Operand(so_buffers[buf]);
8792       store->operands[1] = Operand(so_write_offset[buf]);
8793       store->operands[2] = Operand((uint32_t) 0);
8794       store->operands[3] = Operand(write_data);
8795       if (offset > 4095) {
8796          /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
8797          Builder bld(ctx->program, ctx->block);
8798          store->operands[0] = bld.vadd32(bld.def(v1), Operand(offset), Operand(so_write_offset[buf]));
8799       } else {
8800          store->offset = offset;
8801       }
8802       store->offen = true;
8803       store->glc = true;
8804       store->dlc = false;
8805       store->slc = true;
8806       store->can_reorder = true;
8807       ctx->block->instructions.emplace_back(std::move(store));
8808    }
8809 }
8810
8811 static void emit_streamout(isel_context *ctx, unsigned stream)
8812 {
8813    Builder bld(ctx->program, ctx->block);
8814
8815    Temp so_buffers[4];
8816    Temp buf_ptr = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->streamout_buffers));
8817    for (unsigned i = 0; i < 4; i++) {
8818       unsigned stride = ctx->program->info->so.strides[i];
8819       if (!stride)
8820          continue;
8821
8822       Operand off = bld.copy(bld.def(s1), Operand(i * 16u));
8823       so_buffers[i] = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), buf_ptr, off);
8824    }
8825
8826    Temp so_vtx_count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
8827                                 get_arg(ctx, ctx->args->streamout_config), Operand(0x70010u));
8828
8829    Temp tid = emit_mbcnt(ctx, bld.def(v1));
8830
8831    Temp can_emit = bld.vopc(aco_opcode::v_cmp_gt_i32, bld.def(bld.lm), so_vtx_count, tid);
8832
8833    if_context ic;
8834    begin_divergent_if_then(ctx, &ic, can_emit);
8835
8836    bld.reset(ctx->block);
8837
8838    Temp so_write_index = bld.vadd32(bld.def(v1), get_arg(ctx, ctx->args->streamout_write_idx), tid);
8839
8840    Temp so_write_offset[4];
8841
8842    for (unsigned i = 0; i < 4; i++) {
8843       unsigned stride = ctx->program->info->so.strides[i];
8844       if (!stride)
8845          continue;
8846
8847       if (stride == 1) {
8848          Temp offset = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
8849                                 get_arg(ctx, ctx->args->streamout_write_idx),
8850                                 get_arg(ctx, ctx->args->streamout_offset[i]));
8851          Temp new_offset = bld.vadd32(bld.def(v1), offset, tid);
8852
8853          so_write_offset[i] = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), new_offset);
8854       } else {
8855          Temp offset = bld.v_mul_imm(bld.def(v1), so_write_index, stride * 4u);
8856          Temp offset2 = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(4u),
8857                                  get_arg(ctx, ctx->args->streamout_offset[i]));
8858          so_write_offset[i] = bld.vadd32(bld.def(v1), offset, offset2);
8859       }
8860    }
8861
8862    for (unsigned i = 0; i < ctx->program->info->so.num_outputs; i++) {
8863       struct radv_stream_output *output =
8864          &ctx->program->info->so.outputs[i];
8865       if (stream != output->stream)
8866          continue;
8867
8868       emit_stream_output(ctx, so_buffers, so_write_offset, output);
8869    }
8870
8871    begin_divergent_if_else(ctx, &ic);
8872    end_divergent_if(ctx, &ic);
8873 }
8874
8875 } /* end namespace */
8876
8877 void split_arguments(isel_context *ctx, Pseudo_instruction *startpgm)
8878 {
8879    /* Split all arguments except for the first (ring_offsets) and the last
8880     * (exec) so that the dead channels don't stay live throughout the program.
8881     */
8882    for (int i = 1; i < startpgm->definitions.size() - 1; i++) {
8883       if (startpgm->definitions[i].regClass().size() > 1) {
8884          emit_split_vector(ctx, startpgm->definitions[i].getTemp(),
8885                            startpgm->definitions[i].regClass().size());
8886       }
8887    }
8888 }
8889
8890 void handle_bc_optimize(isel_context *ctx)
8891 {
8892    /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
8893    Builder bld(ctx->program, ctx->block);
8894    uint32_t spi_ps_input_ena = ctx->program->config->spi_ps_input_ena;
8895    bool uses_center = G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena);
8896    bool uses_centroid = G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena);
8897    ctx->persp_centroid = get_arg(ctx, ctx->args->ac.persp_centroid);
8898    ctx->linear_centroid = get_arg(ctx, ctx->args->ac.linear_centroid);
8899    if (uses_center && uses_centroid) {
8900       Temp sel = bld.vopc_e64(aco_opcode::v_cmp_lt_i32, bld.hint_vcc(bld.def(bld.lm)),
8901                               get_arg(ctx, ctx->args->ac.prim_mask), Operand(0u));
8902
8903       if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena)) {
8904          Temp new_coord[2];
8905          for (unsigned i = 0; i < 2; i++) {
8906             Temp persp_centroid = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.persp_centroid), i, v1);
8907             Temp persp_center = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.persp_center), i, v1);
8908             new_coord[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
8909                                     persp_centroid, persp_center, sel);
8910          }
8911          ctx->persp_centroid = bld.tmp(v2);
8912          bld.pseudo(aco_opcode::p_create_vector, Definition(ctx->persp_centroid),
8913                     Operand(new_coord[0]), Operand(new_coord[1]));
8914          emit_split_vector(ctx, ctx->persp_centroid, 2);
8915       }
8916
8917       if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena)) {
8918          Temp new_coord[2];
8919          for (unsigned i = 0; i < 2; i++) {
8920             Temp linear_centroid = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.linear_centroid), i, v1);
8921             Temp linear_center = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.linear_center), i, v1);
8922             new_coord[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
8923                                     linear_centroid, linear_center, sel);
8924          }
8925          ctx->linear_centroid = bld.tmp(v2);
8926          bld.pseudo(aco_opcode::p_create_vector, Definition(ctx->linear_centroid),
8927                     Operand(new_coord[0]), Operand(new_coord[1]));
8928          emit_split_vector(ctx, ctx->linear_centroid, 2);
8929       }
8930    }
8931 }
8932
8933 void setup_fp_mode(isel_context *ctx, nir_shader *shader)
8934 {
8935    Program *program = ctx->program;
8936
8937    unsigned float_controls = shader->info.float_controls_execution_mode;
8938
8939    program->next_fp_mode.preserve_signed_zero_inf_nan32 =
8940       float_controls & FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32;
8941    program->next_fp_mode.preserve_signed_zero_inf_nan16_64 =
8942       float_controls & (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16 |
8943                         FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64);
8944
8945    program->next_fp_mode.must_flush_denorms32 =
8946       float_controls & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32;
8947    program->next_fp_mode.must_flush_denorms16_64 =
8948       float_controls & (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16 |
8949                         FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64);
8950
8951    program->next_fp_mode.care_about_round32 =
8952       float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32 | FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32);
8953
8954    program->next_fp_mode.care_about_round16_64 =
8955       float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64 |
8956                         FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64);
8957
8958    /* default to preserving fp16 and fp64 denorms, since it's free */
8959    if (program->next_fp_mode.must_flush_denorms16_64)
8960       program->next_fp_mode.denorm16_64 = 0;
8961    else
8962       program->next_fp_mode.denorm16_64 = fp_denorm_keep;
8963
8964    /* preserving fp32 denorms is expensive, so only do it if asked */
8965    if (float_controls & FLOAT_CONTROLS_DENORM_PRESERVE_FP32)
8966       program->next_fp_mode.denorm32 = fp_denorm_keep;
8967    else
8968       program->next_fp_mode.denorm32 = 0;
8969
8970    if (float_controls & FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32)
8971       program->next_fp_mode.round32 = fp_round_tz;
8972    else
8973       program->next_fp_mode.round32 = fp_round_ne;
8974
8975    if (float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64))
8976       program->next_fp_mode.round16_64 = fp_round_tz;
8977    else
8978       program->next_fp_mode.round16_64 = fp_round_ne;
8979
8980    ctx->block->fp_mode = program->next_fp_mode;
8981 }
8982
8983 void cleanup_cfg(Program *program)
8984 {
8985    /* create linear_succs/logical_succs */
8986    for (Block& BB : program->blocks) {
8987       for (unsigned idx : BB.linear_preds)
8988          program->blocks[idx].linear_succs.emplace_back(BB.index);
8989       for (unsigned idx : BB.logical_preds)
8990          program->blocks[idx].logical_succs.emplace_back(BB.index);
8991    }
8992 }
8993
8994 void select_program(Program *program,
8995                     unsigned shader_count,
8996                     struct nir_shader *const *shaders,
8997                     ac_shader_config* config,
8998                     struct radv_shader_args *args)
8999 {
9000    isel_context ctx = setup_isel_context(program, shader_count, shaders, config, args, false);
9001
9002    for (unsigned i = 0; i < shader_count; i++) {
9003       nir_shader *nir = shaders[i];
9004       init_context(&ctx, nir);
9005
9006       setup_fp_mode(&ctx, nir);
9007
9008       if (!i) {
9009          /* needs to be after init_context() for FS */
9010          Pseudo_instruction *startpgm = add_startpgm(&ctx);
9011          append_logical_start(ctx.block);
9012          split_arguments(&ctx, startpgm);
9013       }
9014
9015       if_context ic;
9016       if (shader_count >= 2) {
9017          Builder bld(ctx.program, ctx.block);
9018          Temp count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), get_arg(&ctx, args->merged_wave_info), Operand((8u << 16) | (i * 8u)));
9019          Temp thread_id = emit_mbcnt(&ctx, bld.def(v1));
9020          Temp cond = bld.vopc(aco_opcode::v_cmp_gt_u32, bld.hint_vcc(bld.def(bld.lm)), count, thread_id);
9021
9022          begin_divergent_if_then(&ctx, &ic, cond);
9023       }
9024
9025       if (i) {
9026          Builder bld(ctx.program, ctx.block);
9027          assert(ctx.stage == vertex_geometry_gs);
9028          bld.barrier(aco_opcode::p_memory_barrier_shared);
9029          bld.sopp(aco_opcode::s_barrier);
9030
9031          ctx.gs_wave_id = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1, m0), bld.def(s1, scc), get_arg(&ctx, args->merged_wave_info), Operand((8u << 16) | 16u));
9032       } else if (ctx.stage == geometry_gs)
9033          ctx.gs_wave_id = get_arg(&ctx, args->gs_wave_id);
9034
9035       if (ctx.stage == fragment_fs)
9036          handle_bc_optimize(&ctx);
9037
9038       nir_function_impl *func = nir_shader_get_entrypoint(nir);
9039       visit_cf_list(&ctx, &func->body);
9040
9041       if (ctx.program->info->so.num_outputs && ctx.stage == vertex_vs)
9042          emit_streamout(&ctx, 0);
9043
9044       if (ctx.stage == vertex_vs) {
9045          create_vs_exports(&ctx);
9046       } else if (nir->info.stage == MESA_SHADER_GEOMETRY) {
9047          Builder bld(ctx.program, ctx.block);
9048          bld.barrier(aco_opcode::p_memory_barrier_gs_data);
9049          bld.sopp(aco_opcode::s_sendmsg, bld.m0(ctx.gs_wave_id), -1, sendmsg_gs_done(false, false, 0));
9050       }
9051
9052       if (ctx.stage == fragment_fs)
9053          create_fs_exports(&ctx);
9054
9055       if (shader_count >= 2) {
9056          begin_divergent_if_else(&ctx, &ic);
9057          end_divergent_if(&ctx, &ic);
9058       }
9059
9060       ralloc_free(ctx.divergent_vals);
9061    }
9062
9063    program->config->float_mode = program->blocks[0].fp_mode.val;
9064
9065    append_logical_end(ctx.block);
9066    ctx.block->kind |= block_kind_uniform | block_kind_export_end;
9067    Builder bld(ctx.program, ctx.block);
9068    if (ctx.program->wb_smem_l1_on_end)
9069       bld.smem(aco_opcode::s_dcache_wb, false);
9070    bld.sopp(aco_opcode::s_endpgm);
9071
9072    cleanup_cfg(program);
9073 }
9074
9075 void select_gs_copy_shader(Program *program, struct nir_shader *gs_shader,
9076                            ac_shader_config* config,
9077                            struct radv_shader_args *args)
9078 {
9079    isel_context ctx = setup_isel_context(program, 1, &gs_shader, config, args, true);
9080
9081    program->next_fp_mode.preserve_signed_zero_inf_nan32 = false;
9082    program->next_fp_mode.preserve_signed_zero_inf_nan16_64 = false;
9083    program->next_fp_mode.must_flush_denorms32 = false;
9084    program->next_fp_mode.must_flush_denorms16_64 = false;
9085    program->next_fp_mode.care_about_round32 = false;
9086    program->next_fp_mode.care_about_round16_64 = false;
9087    program->next_fp_mode.denorm16_64 = fp_denorm_keep;
9088    program->next_fp_mode.denorm32 = 0;
9089    program->next_fp_mode.round32 = fp_round_ne;
9090    program->next_fp_mode.round16_64 = fp_round_ne;
9091    ctx.block->fp_mode = program->next_fp_mode;
9092
9093    add_startpgm(&ctx);
9094    append_logical_start(ctx.block);
9095
9096    Builder bld(ctx.program, ctx.block);
9097
9098    Temp gsvs_ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), program->private_segment_buffer, Operand(RING_GSVS_VS * 16u));
9099
9100    Operand stream_id(0u);
9101    if (args->shader_info->so.num_outputs)
9102       stream_id = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
9103                            get_arg(&ctx, ctx.args->streamout_config), Operand(0x20018u));
9104
9105    Temp vtx_offset = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), get_arg(&ctx, ctx.args->ac.vertex_id));
9106
9107    std::stack<Block> endif_blocks;
9108
9109    for (unsigned stream = 0; stream < 4; stream++) {
9110       if (stream_id.isConstant() && stream != stream_id.constantValue())
9111          continue;
9112
9113       unsigned num_components = args->shader_info->gs.num_stream_output_components[stream];
9114       if (stream > 0 && (!num_components || !args->shader_info->so.num_outputs))
9115          continue;
9116
9117       memset(ctx.outputs.mask, 0, sizeof(ctx.outputs.mask));
9118
9119       unsigned BB_if_idx = ctx.block->index;
9120       Block BB_endif = Block();
9121       if (!stream_id.isConstant()) {
9122          /* begin IF */
9123          Temp cond = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), stream_id, Operand(stream));
9124          append_logical_end(ctx.block);
9125          ctx.block->kind |= block_kind_uniform;
9126          bld.branch(aco_opcode::p_cbranch_z, cond);
9127
9128          BB_endif.kind |= ctx.block->kind & block_kind_top_level;
9129
9130          ctx.block = ctx.program->create_and_insert_block();
9131          add_edge(BB_if_idx, ctx.block);
9132          bld.reset(ctx.block);
9133          append_logical_start(ctx.block);
9134       }
9135
9136       unsigned offset = 0;
9137       for (unsigned i = 0; i <= VARYING_SLOT_VAR31; ++i) {
9138          if (args->shader_info->gs.output_streams[i] != stream)
9139             continue;
9140
9141          unsigned output_usage_mask = args->shader_info->gs.output_usage_mask[i];
9142          unsigned length = util_last_bit(output_usage_mask);
9143          for (unsigned j = 0; j < length; ++j) {
9144             if (!(output_usage_mask & (1 << j)))
9145                continue;
9146
9147             unsigned const_offset = offset * args->shader_info->gs.vertices_out * 16 * 4;
9148             Temp voffset = vtx_offset;
9149             if (const_offset >= 4096u) {
9150                voffset = bld.vadd32(bld.def(v1), Operand(const_offset / 4096u * 4096u), voffset);
9151                const_offset %= 4096u;
9152             }
9153
9154             aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(aco_opcode::buffer_load_dword, Format::MUBUF, 3, 1)};
9155             mubuf->definitions[0] = bld.def(v1);
9156             mubuf->operands[0] = Operand(gsvs_ring);
9157             mubuf->operands[1] = Operand(voffset);
9158             mubuf->operands[2] = Operand(0u);
9159             mubuf->offen = true;
9160             mubuf->offset = const_offset;
9161             mubuf->glc = true;
9162             mubuf->slc = true;
9163             mubuf->dlc = args->options->chip_class >= GFX10;
9164             mubuf->barrier = barrier_none;
9165             mubuf->can_reorder = true;
9166
9167             ctx.outputs.mask[i] |= 1 << j;
9168             ctx.outputs.outputs[i][j] = mubuf->definitions[0].getTemp();
9169
9170             bld.insert(std::move(mubuf));
9171
9172             offset++;
9173          }
9174       }
9175
9176       if (args->shader_info->so.num_outputs) {
9177          emit_streamout(&ctx, stream);
9178          bld.reset(ctx.block);
9179       }
9180
9181       if (stream == 0) {
9182          create_vs_exports(&ctx);
9183          ctx.block->kind |= block_kind_export_end;
9184       }
9185
9186       if (!stream_id.isConstant()) {
9187          append_logical_end(ctx.block);
9188
9189          /* branch from then block to endif block */
9190          bld.branch(aco_opcode::p_branch);
9191          add_edge(ctx.block->index, &BB_endif);
9192          ctx.block->kind |= block_kind_uniform;
9193
9194          /* emit else block */
9195          ctx.block = ctx.program->create_and_insert_block();
9196          add_edge(BB_if_idx, ctx.block);
9197          bld.reset(ctx.block);
9198          append_logical_start(ctx.block);
9199
9200          endif_blocks.push(std::move(BB_endif));
9201       }
9202    }
9203
9204    while (!endif_blocks.empty()) {
9205       Block BB_endif = std::move(endif_blocks.top());
9206       endif_blocks.pop();
9207
9208       Block *BB_else = ctx.block;
9209
9210       append_logical_end(BB_else);
9211       /* branch from else block to endif block */
9212       bld.branch(aco_opcode::p_branch);
9213       add_edge(BB_else->index, &BB_endif);
9214       BB_else->kind |= block_kind_uniform;
9215
9216       /** emit endif merge block */
9217       ctx.block = program->insert_block(std::move(BB_endif));
9218       bld.reset(ctx.block);
9219       append_logical_start(ctx.block);
9220    }
9221
9222    program->config->float_mode = program->blocks[0].fp_mode.val;
9223
9224    append_logical_end(ctx.block);
9225    ctx.block->kind |= block_kind_uniform;
9226    bld.sopp(aco_opcode::s_endpgm);
9227
9228    cleanup_cfg(program);
9229 }
9230 }