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radv/ac: add support for indirect access of descriptor sets.
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "radv_private.h"
30 #include "nir/nir.h"
31 #include "nir/nir_builder.h"
32 #include "spirv/nir_spirv.h"
33
34 #include <llvm-c/Core.h>
35 #include <llvm-c/TargetMachine.h>
36
37 #include "sid.h"
38 #include "r600d_common.h"
39 #include "ac_binary.h"
40 #include "ac_llvm_util.h"
41 #include "ac_nir_to_llvm.h"
42 #include "vk_format.h"
43 #include "util/debug.h"
44
45 void radv_shader_variant_destroy(struct radv_device *device,
46 struct radv_shader_variant *variant);
47
48 static const struct nir_shader_compiler_options nir_options = {
49 .vertex_id_zero_based = true,
50 .lower_scmp = true,
51 .lower_flrp32 = true,
52 .lower_fsat = true,
53 .lower_pack_snorm_2x16 = true,
54 .lower_pack_snorm_4x8 = true,
55 .lower_pack_unorm_2x16 = true,
56 .lower_pack_unorm_4x8 = true,
57 .lower_unpack_snorm_2x16 = true,
58 .lower_unpack_snorm_4x8 = true,
59 .lower_unpack_unorm_2x16 = true,
60 .lower_unpack_unorm_4x8 = true,
61 .lower_extract_byte = true,
62 .lower_extract_word = true,
63 };
64
65 VkResult radv_CreateShaderModule(
66 VkDevice _device,
67 const VkShaderModuleCreateInfo* pCreateInfo,
68 const VkAllocationCallbacks* pAllocator,
69 VkShaderModule* pShaderModule)
70 {
71 RADV_FROM_HANDLE(radv_device, device, _device);
72 struct radv_shader_module *module;
73
74 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
75 assert(pCreateInfo->flags == 0);
76
77 module = vk_alloc2(&device->alloc, pAllocator,
78 sizeof(*module) + pCreateInfo->codeSize, 8,
79 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
80 if (module == NULL)
81 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
82
83 module->nir = NULL;
84 module->size = pCreateInfo->codeSize;
85 memcpy(module->data, pCreateInfo->pCode, module->size);
86
87 _mesa_sha1_compute(module->data, module->size, module->sha1);
88
89 *pShaderModule = radv_shader_module_to_handle(module);
90
91 return VK_SUCCESS;
92 }
93
94 void radv_DestroyShaderModule(
95 VkDevice _device,
96 VkShaderModule _module,
97 const VkAllocationCallbacks* pAllocator)
98 {
99 RADV_FROM_HANDLE(radv_device, device, _device);
100 RADV_FROM_HANDLE(radv_shader_module, module, _module);
101
102 if (!module)
103 return;
104
105 vk_free2(&device->alloc, pAllocator, module);
106 }
107
108
109 static void
110 radv_pipeline_destroy(struct radv_device *device,
111 struct radv_pipeline *pipeline,
112 const VkAllocationCallbacks* allocator)
113 {
114 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
115 if (pipeline->shaders[i])
116 radv_shader_variant_destroy(device, pipeline->shaders[i]);
117
118 if (pipeline->gs_copy_shader)
119 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
120
121 vk_free2(&device->alloc, allocator, pipeline);
122 }
123
124 void radv_DestroyPipeline(
125 VkDevice _device,
126 VkPipeline _pipeline,
127 const VkAllocationCallbacks* pAllocator)
128 {
129 RADV_FROM_HANDLE(radv_device, device, _device);
130 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
131
132 if (!_pipeline)
133 return;
134
135 radv_pipeline_destroy(device, pipeline, pAllocator);
136 }
137
138
139 static void
140 radv_optimize_nir(struct nir_shader *shader)
141 {
142 bool progress;
143
144 do {
145 progress = false;
146
147 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
148 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
149 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
150
151 NIR_PASS(progress, shader, nir_copy_prop);
152 NIR_PASS(progress, shader, nir_opt_remove_phis);
153 NIR_PASS(progress, shader, nir_opt_dce);
154 NIR_PASS(progress, shader, nir_opt_dead_cf);
155 NIR_PASS(progress, shader, nir_opt_cse);
156 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
157 NIR_PASS(progress, shader, nir_opt_algebraic);
158 NIR_PASS(progress, shader, nir_opt_constant_folding);
159 NIR_PASS(progress, shader, nir_opt_undef);
160 NIR_PASS(progress, shader, nir_opt_conditional_discard);
161 } while (progress);
162 }
163
164 static nir_shader *
165 radv_shader_compile_to_nir(struct radv_device *device,
166 struct radv_shader_module *module,
167 const char *entrypoint_name,
168 gl_shader_stage stage,
169 const VkSpecializationInfo *spec_info,
170 bool dump)
171 {
172 if (strcmp(entrypoint_name, "main") != 0) {
173 radv_finishme("Multiple shaders per module not really supported");
174 }
175
176 nir_shader *nir;
177 nir_function *entry_point;
178 if (module->nir) {
179 /* Some things such as our meta clear/blit code will give us a NIR
180 * shader directly. In that case, we just ignore the SPIR-V entirely
181 * and just use the NIR shader */
182 nir = module->nir;
183 nir->options = &nir_options;
184 nir_validate_shader(nir);
185
186 assert(exec_list_length(&nir->functions) == 1);
187 struct exec_node *node = exec_list_get_head(&nir->functions);
188 entry_point = exec_node_data(nir_function, node, node);
189 } else {
190 uint32_t *spirv = (uint32_t *) module->data;
191 assert(module->size % 4 == 0);
192
193 uint32_t num_spec_entries = 0;
194 struct nir_spirv_specialization *spec_entries = NULL;
195 if (spec_info && spec_info->mapEntryCount > 0) {
196 num_spec_entries = spec_info->mapEntryCount;
197 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
198 for (uint32_t i = 0; i < num_spec_entries; i++) {
199 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
200 const void *data = spec_info->pData + entry.offset;
201 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
202
203 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
204 if (spec_info->dataSize == 8)
205 spec_entries[i].data64 = *(const uint64_t *)data;
206 else
207 spec_entries[i].data32 = *(const uint32_t *)data;
208 }
209 }
210 const struct nir_spirv_supported_extensions supported_ext = {
211 .draw_parameters = true,
212 .float64 = true,
213 .image_read_without_format = true,
214 .image_write_without_format = true,
215 .tessellation = true,
216 };
217 entry_point = spirv_to_nir(spirv, module->size / 4,
218 spec_entries, num_spec_entries,
219 stage, entrypoint_name, &supported_ext, &nir_options);
220 nir = entry_point->shader;
221 assert(nir->stage == stage);
222 nir_validate_shader(nir);
223
224 free(spec_entries);
225
226 /* We have to lower away local constant initializers right before we
227 * inline functions. That way they get properly initialized at the top
228 * of the function and not at the top of its caller.
229 */
230 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
231 NIR_PASS_V(nir, nir_lower_returns);
232 NIR_PASS_V(nir, nir_inline_functions);
233
234 /* Pick off the single entrypoint that we want */
235 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
236 if (func != entry_point)
237 exec_node_remove(&func->node);
238 }
239 assert(exec_list_length(&nir->functions) == 1);
240 entry_point->name = ralloc_strdup(entry_point, "main");
241
242 NIR_PASS_V(nir, nir_remove_dead_variables,
243 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
244
245 /* Now that we've deleted all but the main function, we can go ahead and
246 * lower the rest of the constant initializers.
247 */
248 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
249 NIR_PASS_V(nir, nir_lower_system_values);
250 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
251 }
252
253 /* Vulkan uses the separate-shader linking model */
254 nir->info->separate_shader = true;
255
256 nir_shader_gather_info(nir, entry_point->impl);
257
258 nir_variable_mode indirect_mask = 0;
259 indirect_mask |= nir_var_shader_in;
260 indirect_mask |= nir_var_local;
261
262 nir_lower_indirect_derefs(nir, indirect_mask);
263
264 static const nir_lower_tex_options tex_options = {
265 .lower_txp = ~0,
266 };
267
268 nir_lower_tex(nir, &tex_options);
269
270 nir_lower_vars_to_ssa(nir);
271 nir_lower_var_copies(nir);
272 nir_lower_global_vars_to_local(nir);
273 nir_remove_dead_variables(nir, nir_var_local);
274 radv_optimize_nir(nir);
275
276 if (dump)
277 nir_print_shader(nir, stderr);
278
279 return nir;
280 }
281
282 static const char *radv_get_shader_name(struct radv_shader_variant *var,
283 gl_shader_stage stage)
284 {
285 switch (stage) {
286 case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
287 case MESA_SHADER_GEOMETRY: return "Geometry Shader";
288 case MESA_SHADER_FRAGMENT: return "Pixel Shader";
289 case MESA_SHADER_COMPUTE: return "Compute Shader";
290 case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
291 case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
292 default:
293 return "Unknown shader";
294 };
295
296 }
297 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
298 {
299 unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
300 struct radv_shader_variant *var;
301 struct ac_shader_config *conf;
302 int i;
303 FILE *file = stderr;
304 unsigned max_simd_waves = 10;
305 unsigned lds_per_wave = 0;
306
307 for (i = 0; i < MESA_SHADER_STAGES; i++) {
308 if (!pipeline->shaders[i])
309 continue;
310 var = pipeline->shaders[i];
311
312 conf = &var->config;
313
314 if (i == MESA_SHADER_FRAGMENT) {
315 lds_per_wave = conf->lds_size * lds_increment +
316 align(var->info.fs.num_interp * 48, lds_increment);
317 }
318
319 if (conf->num_sgprs) {
320 if (device->physical_device->rad_info.chip_class >= VI)
321 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
322 else
323 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
324 }
325
326 if (conf->num_vgprs)
327 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
328
329 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
330 * that PS can use.
331 */
332 if (lds_per_wave)
333 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
334
335 fprintf(file, "\n%s:\n",
336 radv_get_shader_name(var, i));
337 if (i == MESA_SHADER_FRAGMENT) {
338 fprintf(file, "*** SHADER CONFIG ***\n"
339 "SPI_PS_INPUT_ADDR = 0x%04x\n"
340 "SPI_PS_INPUT_ENA = 0x%04x\n",
341 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
342 }
343 fprintf(file, "*** SHADER STATS ***\n"
344 "SGPRS: %d\n"
345 "VGPRS: %d\n"
346 "Spilled SGPRs: %d\n"
347 "Spilled VGPRs: %d\n"
348 "Code Size: %d bytes\n"
349 "LDS: %d blocks\n"
350 "Scratch: %d bytes per wave\n"
351 "Max Waves: %d\n"
352 "********************\n\n\n",
353 conf->num_sgprs, conf->num_vgprs,
354 conf->spilled_sgprs, conf->spilled_vgprs, var->code_size,
355 conf->lds_size, conf->scratch_bytes_per_wave,
356 max_simd_waves);
357 }
358 }
359
360 void radv_shader_variant_destroy(struct radv_device *device,
361 struct radv_shader_variant *variant)
362 {
363 if (__sync_fetch_and_sub(&variant->ref_count, 1) != 1)
364 return;
365
366 device->ws->buffer_destroy(variant->bo);
367 free(variant);
368 }
369
370 static void radv_fill_shader_variant(struct radv_device *device,
371 struct radv_shader_variant *variant,
372 struct ac_shader_binary *binary,
373 gl_shader_stage stage)
374 {
375 bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
376 unsigned vgpr_comp_cnt = 0;
377
378 if (scratch_enabled && !device->llvm_supports_spill)
379 radv_finishme("shader scratch support only available with LLVM 4.0");
380
381 variant->code_size = binary->code_size;
382 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
383 S_00B12C_SCRATCH_EN(scratch_enabled);
384
385 switch (stage) {
386 case MESA_SHADER_TESS_EVAL:
387 vgpr_comp_cnt = 3;
388 /* fallthrough */
389 case MESA_SHADER_TESS_CTRL:
390 variant->rsrc2 |= S_00B42C_OC_LDS_EN(1);
391 break;
392 case MESA_SHADER_VERTEX:
393 case MESA_SHADER_GEOMETRY:
394 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
395 break;
396 case MESA_SHADER_FRAGMENT:
397 break;
398 case MESA_SHADER_COMPUTE:
399 variant->rsrc2 |=
400 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
401 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
402 S_00B84C_TG_SIZE_EN(1) |
403 S_00B84C_LDS_SIZE(variant->config.lds_size);
404 break;
405 default:
406 unreachable("unsupported shader type");
407 break;
408 }
409
410 variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
411 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
412 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
413 S_00B848_DX10_CLAMP(1) |
414 S_00B848_FLOAT_MODE(variant->config.float_mode);
415
416 variant->bo = device->ws->buffer_create(device->ws, binary->code_size, 256,
417 RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS);
418
419 void *ptr = device->ws->buffer_map(variant->bo);
420 memcpy(ptr, binary->code, binary->code_size);
421 device->ws->buffer_unmap(variant->bo);
422
423
424 }
425
426 static struct radv_shader_variant *radv_shader_variant_create(struct radv_device *device,
427 struct nir_shader *shader,
428 struct radv_pipeline_layout *layout,
429 const union ac_shader_variant_key *key,
430 void** code_out,
431 unsigned *code_size_out,
432 bool dump)
433 {
434 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
435 enum radeon_family chip_family = device->physical_device->rad_info.family;
436 LLVMTargetMachineRef tm;
437 if (!variant)
438 return NULL;
439
440 struct ac_nir_compiler_options options = {0};
441 options.layout = layout;
442 if (key)
443 options.key = *key;
444
445 struct ac_shader_binary binary;
446
447 options.unsafe_math = !!(device->debug_flags & RADV_DEBUG_UNSAFE_MATH);
448 options.family = chip_family;
449 options.chip_class = device->physical_device->rad_info.chip_class;
450 options.supports_spill = device->llvm_supports_spill;
451 tm = ac_create_target_machine(chip_family, options.supports_spill);
452 ac_compile_nir_shader(tm, &binary, &variant->config,
453 &variant->info, shader, &options, dump);
454 LLVMDisposeTargetMachine(tm);
455
456 radv_fill_shader_variant(device, variant, &binary, shader->stage);
457
458 if (code_out) {
459 *code_out = binary.code;
460 *code_size_out = binary.code_size;
461 } else
462 free(binary.code);
463 free(binary.config);
464 free(binary.rodata);
465 free(binary.global_symbol_offsets);
466 free(binary.relocs);
467 free(binary.disasm_string);
468 variant->ref_count = 1;
469 return variant;
470 }
471
472 static struct radv_shader_variant *
473 radv_pipeline_create_gs_copy_shader(struct radv_pipeline *pipeline,
474 struct nir_shader *nir,
475 void** code_out,
476 unsigned *code_size_out,
477 bool dump_shader)
478 {
479 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
480 enum radeon_family chip_family = pipeline->device->physical_device->rad_info.family;
481 LLVMTargetMachineRef tm;
482 if (!variant)
483 return NULL;
484
485 struct ac_nir_compiler_options options = {0};
486 struct ac_shader_binary binary;
487 options.family = chip_family;
488 options.chip_class = pipeline->device->physical_device->rad_info.chip_class;
489 options.supports_spill = pipeline->device->llvm_supports_spill;
490 tm = ac_create_target_machine(chip_family, options.supports_spill);
491 ac_create_gs_copy_shader(tm, nir, &binary, &variant->config, &variant->info, &options, dump_shader);
492 LLVMDisposeTargetMachine(tm);
493
494 radv_fill_shader_variant(pipeline->device, variant, &binary, MESA_SHADER_VERTEX);
495
496 if (code_out) {
497 *code_out = binary.code;
498 *code_size_out = binary.code_size;
499 } else
500 free(binary.code);
501 free(binary.config);
502 free(binary.rodata);
503 free(binary.global_symbol_offsets);
504 free(binary.relocs);
505 free(binary.disasm_string);
506 variant->ref_count = 1;
507 return variant;
508 }
509
510 static struct radv_shader_variant *
511 radv_pipeline_compile(struct radv_pipeline *pipeline,
512 struct radv_pipeline_cache *cache,
513 struct radv_shader_module *module,
514 const char *entrypoint,
515 gl_shader_stage stage,
516 const VkSpecializationInfo *spec_info,
517 struct radv_pipeline_layout *layout,
518 const union ac_shader_variant_key *key)
519 {
520 unsigned char sha1[20];
521 unsigned char gs_copy_sha1[20];
522 struct radv_shader_variant *variant;
523 nir_shader *nir;
524 void *code = NULL;
525 unsigned code_size = 0;
526 bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS);
527
528 if (module->nir)
529 _mesa_sha1_compute(module->nir->info->name,
530 strlen(module->nir->info->name),
531 module->sha1);
532
533 radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key, 0);
534 if (stage == MESA_SHADER_GEOMETRY)
535 radv_hash_shader(gs_copy_sha1, module, entrypoint, spec_info,
536 layout, key, 1);
537
538 variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
539 cache,
540 sha1);
541
542 if (stage == MESA_SHADER_GEOMETRY) {
543 pipeline->gs_copy_shader =
544 radv_create_shader_variant_from_pipeline_cache(
545 pipeline->device,
546 cache,
547 gs_copy_sha1);
548 }
549
550 if (variant &&
551 (stage != MESA_SHADER_GEOMETRY || pipeline->gs_copy_shader))
552 return variant;
553
554 nir = radv_shader_compile_to_nir(pipeline->device,
555 module, entrypoint, stage,
556 spec_info, dump);
557 if (nir == NULL)
558 return NULL;
559
560 if (!variant) {
561 variant = radv_shader_variant_create(pipeline->device, nir,
562 layout, key, &code,
563 &code_size, dump);
564 }
565
566 if (stage == MESA_SHADER_GEOMETRY && !pipeline->gs_copy_shader) {
567 void *gs_copy_code = NULL;
568 unsigned gs_copy_code_size = 0;
569 pipeline->gs_copy_shader = radv_pipeline_create_gs_copy_shader(
570 pipeline, nir, &gs_copy_code, &gs_copy_code_size, dump);
571
572 if (pipeline->gs_copy_shader) {
573 pipeline->gs_copy_shader =
574 radv_pipeline_cache_insert_shader(cache,
575 gs_copy_sha1,
576 pipeline->gs_copy_shader,
577 gs_copy_code,
578 gs_copy_code_size);
579 }
580 }
581 if (!module->nir)
582 ralloc_free(nir);
583
584 if (variant)
585 variant = radv_pipeline_cache_insert_shader(cache, sha1, variant,
586 code, code_size);
587
588 if (code)
589 free(code);
590 return variant;
591 }
592
593 static union ac_shader_variant_key
594 radv_compute_tes_key(bool as_es)
595 {
596 union ac_shader_variant_key key;
597 memset(&key, 0, sizeof(key));
598 key.tes.as_es = as_es;
599 return key;
600 }
601
602 static union ac_shader_variant_key
603 radv_compute_tcs_key(unsigned primitive_mode, unsigned input_vertices)
604 {
605 union ac_shader_variant_key key;
606 memset(&key, 0, sizeof(key));
607 key.tcs.primitive_mode = primitive_mode;
608 key.tcs.input_vertices = input_vertices;
609 return key;
610 }
611
612 static void
613 radv_tess_pipeline_compile(struct radv_pipeline *pipeline,
614 struct radv_pipeline_cache *cache,
615 struct radv_shader_module *tcs_module,
616 struct radv_shader_module *tes_module,
617 const char *tcs_entrypoint,
618 const char *tes_entrypoint,
619 const VkSpecializationInfo *tcs_spec_info,
620 const VkSpecializationInfo *tes_spec_info,
621 struct radv_pipeline_layout *layout,
622 unsigned input_vertices)
623 {
624 unsigned char tcs_sha1[20], tes_sha1[20];
625 struct radv_shader_variant *tes_variant = NULL, *tcs_variant = NULL;
626 nir_shader *tes_nir, *tcs_nir;
627 void *tes_code = NULL, *tcs_code = NULL;
628 unsigned tes_code_size = 0, tcs_code_size = 0;
629 union ac_shader_variant_key tes_key = radv_compute_tes_key(radv_pipeline_has_gs(pipeline));
630 union ac_shader_variant_key tcs_key;
631 bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS);
632
633 if (tes_module->nir)
634 _mesa_sha1_compute(tes_module->nir->info->name,
635 strlen(tes_module->nir->info->name),
636 tes_module->sha1);
637 radv_hash_shader(tes_sha1, tes_module, tes_entrypoint, tes_spec_info, layout, &tes_key, 0);
638
639 tes_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
640 cache,
641 tes_sha1);
642
643 if (tes_variant) {
644 tcs_key = radv_compute_tcs_key(tes_variant->info.tes.primitive_mode, input_vertices);
645
646 if (tcs_module->nir)
647 _mesa_sha1_compute(tcs_module->nir->info->name,
648 strlen(tcs_module->nir->info->name),
649 tcs_module->sha1);
650
651 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
652
653 tcs_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
654 cache,
655 tcs_sha1);
656 }
657
658 if (tcs_variant && tes_variant) {
659 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
660 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
661 return;
662 }
663
664 tes_nir = radv_shader_compile_to_nir(pipeline->device,
665 tes_module, tes_entrypoint, MESA_SHADER_TESS_EVAL,
666 tes_spec_info, dump);
667 if (tes_nir == NULL)
668 return;
669
670 tcs_nir = radv_shader_compile_to_nir(pipeline->device,
671 tcs_module, tcs_entrypoint, MESA_SHADER_TESS_CTRL,
672 tcs_spec_info, dump);
673 if (tcs_nir == NULL)
674 return;
675
676 nir_lower_tes_patch_vertices(tes_nir,
677 tcs_nir->info->tess.tcs_vertices_out);
678
679 tes_variant = radv_shader_variant_create(pipeline->device, tes_nir,
680 layout, &tes_key, &tes_code,
681 &tes_code_size, dump);
682
683 tcs_key = radv_compute_tcs_key(tes_nir->info->tess.primitive_mode, input_vertices);
684 if (tcs_module->nir)
685 _mesa_sha1_compute(tcs_module->nir->info->name,
686 strlen(tcs_module->nir->info->name),
687 tcs_module->sha1);
688
689 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
690
691 tcs_variant = radv_shader_variant_create(pipeline->device, tcs_nir,
692 layout, &tcs_key, &tcs_code,
693 &tcs_code_size, dump);
694
695 if (!tes_module->nir)
696 ralloc_free(tes_nir);
697
698 if (!tcs_module->nir)
699 ralloc_free(tcs_nir);
700
701 if (tes_variant)
702 tes_variant = radv_pipeline_cache_insert_shader(cache, tes_sha1, tes_variant,
703 tes_code, tes_code_size);
704
705 if (tcs_variant)
706 tcs_variant = radv_pipeline_cache_insert_shader(cache, tcs_sha1, tcs_variant,
707 tcs_code, tcs_code_size);
708
709 if (tes_code)
710 free(tes_code);
711 if (tcs_code)
712 free(tcs_code);
713 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
714 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
715 return;
716 }
717
718 static VkResult
719 radv_pipeline_scratch_init(struct radv_device *device,
720 struct radv_pipeline *pipeline)
721 {
722 unsigned scratch_bytes_per_wave = 0;
723 unsigned max_waves = 0;
724 unsigned min_waves = 1;
725
726 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
727 if (pipeline->shaders[i]) {
728 unsigned max_stage_waves = device->scratch_waves;
729
730 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
731 pipeline->shaders[i]->config.scratch_bytes_per_wave);
732
733 max_stage_waves = MIN2(max_stage_waves,
734 4 * device->physical_device->rad_info.num_good_compute_units *
735 (256 / pipeline->shaders[i]->config.num_vgprs));
736 max_waves = MAX2(max_waves, max_stage_waves);
737 }
738 }
739
740 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
741 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
742 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
743 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
744 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
745 }
746
747 if (scratch_bytes_per_wave)
748 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
749
750 if (scratch_bytes_per_wave && max_waves < min_waves) {
751 /* Not really true at this moment, but will be true on first
752 * execution. Avoid having hanging shaders. */
753 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
754 }
755 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
756 pipeline->max_waves = max_waves;
757 return VK_SUCCESS;
758 }
759
760 static uint32_t si_translate_blend_function(VkBlendOp op)
761 {
762 switch (op) {
763 case VK_BLEND_OP_ADD:
764 return V_028780_COMB_DST_PLUS_SRC;
765 case VK_BLEND_OP_SUBTRACT:
766 return V_028780_COMB_SRC_MINUS_DST;
767 case VK_BLEND_OP_REVERSE_SUBTRACT:
768 return V_028780_COMB_DST_MINUS_SRC;
769 case VK_BLEND_OP_MIN:
770 return V_028780_COMB_MIN_DST_SRC;
771 case VK_BLEND_OP_MAX:
772 return V_028780_COMB_MAX_DST_SRC;
773 default:
774 return 0;
775 }
776 }
777
778 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
779 {
780 switch (factor) {
781 case VK_BLEND_FACTOR_ZERO:
782 return V_028780_BLEND_ZERO;
783 case VK_BLEND_FACTOR_ONE:
784 return V_028780_BLEND_ONE;
785 case VK_BLEND_FACTOR_SRC_COLOR:
786 return V_028780_BLEND_SRC_COLOR;
787 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
788 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
789 case VK_BLEND_FACTOR_DST_COLOR:
790 return V_028780_BLEND_DST_COLOR;
791 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
792 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
793 case VK_BLEND_FACTOR_SRC_ALPHA:
794 return V_028780_BLEND_SRC_ALPHA;
795 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
796 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
797 case VK_BLEND_FACTOR_DST_ALPHA:
798 return V_028780_BLEND_DST_ALPHA;
799 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
800 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
801 case VK_BLEND_FACTOR_CONSTANT_COLOR:
802 return V_028780_BLEND_CONSTANT_COLOR;
803 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
804 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
805 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
806 return V_028780_BLEND_CONSTANT_ALPHA;
807 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
808 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
809 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
810 return V_028780_BLEND_SRC_ALPHA_SATURATE;
811 case VK_BLEND_FACTOR_SRC1_COLOR:
812 return V_028780_BLEND_SRC1_COLOR;
813 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
814 return V_028780_BLEND_INV_SRC1_COLOR;
815 case VK_BLEND_FACTOR_SRC1_ALPHA:
816 return V_028780_BLEND_SRC1_ALPHA;
817 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
818 return V_028780_BLEND_INV_SRC1_ALPHA;
819 default:
820 return 0;
821 }
822 }
823
824 static bool is_dual_src(VkBlendFactor factor)
825 {
826 switch (factor) {
827 case VK_BLEND_FACTOR_SRC1_COLOR:
828 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
829 case VK_BLEND_FACTOR_SRC1_ALPHA:
830 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
831 return true;
832 default:
833 return false;
834 }
835 }
836
837 static unsigned si_choose_spi_color_format(VkFormat vk_format,
838 bool blend_enable,
839 bool blend_need_alpha)
840 {
841 const struct vk_format_description *desc = vk_format_description(vk_format);
842 unsigned format, ntype, swap;
843
844 /* Alpha is needed for alpha-to-coverage.
845 * Blending may be with or without alpha.
846 */
847 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
848 unsigned alpha = 0; /* exports alpha, but may not support blending */
849 unsigned blend = 0; /* supports blending, but may not export alpha */
850 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
851
852 format = radv_translate_colorformat(vk_format);
853 ntype = radv_translate_color_numformat(vk_format, desc,
854 vk_format_get_first_non_void_channel(vk_format));
855 swap = radv_translate_colorswap(vk_format, false);
856
857 /* Choose the SPI color formats. These are required values for Stoney/RB+.
858 * Other chips have multiple choices, though they are not necessarily better.
859 */
860 switch (format) {
861 case V_028C70_COLOR_5_6_5:
862 case V_028C70_COLOR_1_5_5_5:
863 case V_028C70_COLOR_5_5_5_1:
864 case V_028C70_COLOR_4_4_4_4:
865 case V_028C70_COLOR_10_11_11:
866 case V_028C70_COLOR_11_11_10:
867 case V_028C70_COLOR_8:
868 case V_028C70_COLOR_8_8:
869 case V_028C70_COLOR_8_8_8_8:
870 case V_028C70_COLOR_10_10_10_2:
871 case V_028C70_COLOR_2_10_10_10:
872 if (ntype == V_028C70_NUMBER_UINT)
873 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
874 else if (ntype == V_028C70_NUMBER_SINT)
875 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
876 else
877 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
878 break;
879
880 case V_028C70_COLOR_16:
881 case V_028C70_COLOR_16_16:
882 case V_028C70_COLOR_16_16_16_16:
883 if (ntype == V_028C70_NUMBER_UNORM ||
884 ntype == V_028C70_NUMBER_SNORM) {
885 /* UNORM16 and SNORM16 don't support blending */
886 if (ntype == V_028C70_NUMBER_UNORM)
887 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
888 else
889 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
890
891 /* Use 32 bits per channel for blending. */
892 if (format == V_028C70_COLOR_16) {
893 if (swap == V_028C70_SWAP_STD) { /* R */
894 blend = V_028714_SPI_SHADER_32_R;
895 blend_alpha = V_028714_SPI_SHADER_32_AR;
896 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
897 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
898 else
899 assert(0);
900 } else if (format == V_028C70_COLOR_16_16) {
901 if (swap == V_028C70_SWAP_STD) { /* RG */
902 blend = V_028714_SPI_SHADER_32_GR;
903 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
904 } else if (swap == V_028C70_SWAP_ALT) /* RA */
905 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
906 else
907 assert(0);
908 } else /* 16_16_16_16 */
909 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
910 } else if (ntype == V_028C70_NUMBER_UINT)
911 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
912 else if (ntype == V_028C70_NUMBER_SINT)
913 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
914 else if (ntype == V_028C70_NUMBER_FLOAT)
915 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
916 else
917 assert(0);
918 break;
919
920 case V_028C70_COLOR_32:
921 if (swap == V_028C70_SWAP_STD) { /* R */
922 blend = normal = V_028714_SPI_SHADER_32_R;
923 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
924 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
925 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
926 else
927 assert(0);
928 break;
929
930 case V_028C70_COLOR_32_32:
931 if (swap == V_028C70_SWAP_STD) { /* RG */
932 blend = normal = V_028714_SPI_SHADER_32_GR;
933 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
934 } else if (swap == V_028C70_SWAP_ALT) /* RA */
935 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
936 else
937 assert(0);
938 break;
939
940 case V_028C70_COLOR_32_32_32_32:
941 case V_028C70_COLOR_8_24:
942 case V_028C70_COLOR_24_8:
943 case V_028C70_COLOR_X24_8_32_FLOAT:
944 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
945 break;
946
947 default:
948 unreachable("unhandled blend format");
949 }
950
951 if (blend_enable && blend_need_alpha)
952 return blend_alpha;
953 else if(blend_need_alpha)
954 return alpha;
955 else if(blend_enable)
956 return blend;
957 else
958 return normal;
959 }
960
961 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
962 {
963 unsigned i, cb_shader_mask = 0;
964
965 for (i = 0; i < 8; i++) {
966 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
967 case V_028714_SPI_SHADER_ZERO:
968 break;
969 case V_028714_SPI_SHADER_32_R:
970 cb_shader_mask |= 0x1 << (i * 4);
971 break;
972 case V_028714_SPI_SHADER_32_GR:
973 cb_shader_mask |= 0x3 << (i * 4);
974 break;
975 case V_028714_SPI_SHADER_32_AR:
976 cb_shader_mask |= 0x9 << (i * 4);
977 break;
978 case V_028714_SPI_SHADER_FP16_ABGR:
979 case V_028714_SPI_SHADER_UNORM16_ABGR:
980 case V_028714_SPI_SHADER_SNORM16_ABGR:
981 case V_028714_SPI_SHADER_UINT16_ABGR:
982 case V_028714_SPI_SHADER_SINT16_ABGR:
983 case V_028714_SPI_SHADER_32_ABGR:
984 cb_shader_mask |= 0xf << (i * 4);
985 break;
986 default:
987 assert(0);
988 }
989 }
990 return cb_shader_mask;
991 }
992
993 static void
994 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
995 const VkGraphicsPipelineCreateInfo *pCreateInfo,
996 uint32_t blend_enable,
997 uint32_t blend_need_alpha,
998 bool single_cb_enable,
999 bool blend_mrt0_is_dual_src)
1000 {
1001 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1002 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1003 struct radv_blend_state *blend = &pipeline->graphics.blend;
1004 unsigned col_format = 0;
1005
1006 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
1007 struct radv_render_pass_attachment *attachment;
1008 unsigned cf;
1009
1010 attachment = pass->attachments + subpass->color_attachments[i].attachment;
1011
1012 cf = si_choose_spi_color_format(attachment->format,
1013 blend_enable & (1 << i),
1014 blend_need_alpha & (1 << i));
1015
1016 col_format |= cf << (4 * i);
1017 }
1018
1019 blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
1020
1021 if (blend_mrt0_is_dual_src)
1022 col_format |= (col_format & 0xf) << 4;
1023 blend->spi_shader_col_format = col_format;
1024 }
1025
1026 static bool
1027 format_is_int8(VkFormat format)
1028 {
1029 const struct vk_format_description *desc = vk_format_description(format);
1030 int channel = vk_format_get_first_non_void_channel(format);
1031
1032 return channel >= 0 && desc->channel[channel].pure_integer &&
1033 desc->channel[channel].size == 8;
1034 }
1035
1036 unsigned radv_format_meta_fs_key(VkFormat format)
1037 {
1038 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
1039 bool is_int8 = format_is_int8(format);
1040
1041 return col_format + (is_int8 ? 3 : 0);
1042 }
1043
1044 static unsigned
1045 radv_pipeline_compute_is_int8(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1046 {
1047 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1048 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1049 unsigned is_int8 = 0;
1050
1051 for (unsigned i = 0; i < subpass->color_count; ++i) {
1052 struct radv_render_pass_attachment *attachment;
1053
1054 attachment = pass->attachments + subpass->color_attachments[i].attachment;
1055
1056 if (format_is_int8(attachment->format))
1057 is_int8 |= 1 << i;
1058 }
1059
1060 return is_int8;
1061 }
1062
1063 static void
1064 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
1065 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1066 const struct radv_graphics_pipeline_create_info *extra)
1067 {
1068 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
1069 struct radv_blend_state *blend = &pipeline->graphics.blend;
1070 unsigned mode = V_028808_CB_NORMAL;
1071 uint32_t blend_enable = 0, blend_need_alpha = 0;
1072 bool blend_mrt0_is_dual_src = false;
1073 int i;
1074 bool single_cb_enable = false;
1075
1076 if (!vkblend)
1077 return;
1078
1079 if (extra && extra->custom_blend_mode) {
1080 single_cb_enable = true;
1081 mode = extra->custom_blend_mode;
1082 }
1083 blend->cb_color_control = 0;
1084 if (vkblend->logicOpEnable)
1085 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
1086 else
1087 blend->cb_color_control |= S_028808_ROP3(0xcc);
1088
1089 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
1090 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
1091 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
1092 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
1093
1094 blend->cb_target_mask = 0;
1095 for (i = 0; i < vkblend->attachmentCount; i++) {
1096 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
1097 unsigned blend_cntl = 0;
1098 VkBlendOp eqRGB = att->colorBlendOp;
1099 VkBlendFactor srcRGB = att->srcColorBlendFactor;
1100 VkBlendFactor dstRGB = att->dstColorBlendFactor;
1101 VkBlendOp eqA = att->alphaBlendOp;
1102 VkBlendFactor srcA = att->srcAlphaBlendFactor;
1103 VkBlendFactor dstA = att->dstAlphaBlendFactor;
1104
1105 blend->sx_mrt0_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
1106
1107 if (!att->colorWriteMask)
1108 continue;
1109
1110 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
1111 if (!att->blendEnable) {
1112 blend->cb_blend_control[i] = blend_cntl;
1113 continue;
1114 }
1115
1116 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
1117 if (i == 0)
1118 blend_mrt0_is_dual_src = true;
1119
1120 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
1121 srcRGB = VK_BLEND_FACTOR_ONE;
1122 dstRGB = VK_BLEND_FACTOR_ONE;
1123 }
1124 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
1125 srcA = VK_BLEND_FACTOR_ONE;
1126 dstA = VK_BLEND_FACTOR_ONE;
1127 }
1128
1129 blend_cntl |= S_028780_ENABLE(1);
1130
1131 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
1132 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
1133 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
1134 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
1135 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
1136 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
1137 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
1138 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
1139 }
1140 blend->cb_blend_control[i] = blend_cntl;
1141
1142 blend_enable |= 1 << i;
1143
1144 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1145 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1146 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1147 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1148 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
1149 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
1150 blend_need_alpha |= 1 << i;
1151 }
1152 for (i = vkblend->attachmentCount; i < 8; i++)
1153 blend->cb_blend_control[i] = 0;
1154
1155 if (blend->cb_target_mask)
1156 blend->cb_color_control |= S_028808_MODE(mode);
1157 else
1158 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
1159
1160 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
1161 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
1162 }
1163
1164 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
1165 {
1166 switch (op) {
1167 case VK_STENCIL_OP_KEEP:
1168 return V_02842C_STENCIL_KEEP;
1169 case VK_STENCIL_OP_ZERO:
1170 return V_02842C_STENCIL_ZERO;
1171 case VK_STENCIL_OP_REPLACE:
1172 return V_02842C_STENCIL_REPLACE_TEST;
1173 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
1174 return V_02842C_STENCIL_ADD_CLAMP;
1175 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
1176 return V_02842C_STENCIL_SUB_CLAMP;
1177 case VK_STENCIL_OP_INVERT:
1178 return V_02842C_STENCIL_INVERT;
1179 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
1180 return V_02842C_STENCIL_ADD_WRAP;
1181 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
1182 return V_02842C_STENCIL_SUB_WRAP;
1183 default:
1184 return 0;
1185 }
1186 }
1187 static void
1188 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
1189 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1190 const struct radv_graphics_pipeline_create_info *extra)
1191 {
1192 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
1193 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
1194
1195 memset(ds, 0, sizeof(*ds));
1196 if (!vkds)
1197 return;
1198 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
1199 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
1200 S_028800_ZFUNC(vkds->depthCompareOp) |
1201 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
1202
1203 if (vkds->stencilTestEnable) {
1204 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
1205 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
1206 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
1207 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
1208 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
1209
1210 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
1211 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
1212 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
1213 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
1214 }
1215
1216 if (extra) {
1217
1218 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
1219 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
1220
1221 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
1222 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
1223 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
1224 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
1225 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
1226 }
1227 }
1228
1229 static uint32_t si_translate_fill(VkPolygonMode func)
1230 {
1231 switch(func) {
1232 case VK_POLYGON_MODE_FILL:
1233 return V_028814_X_DRAW_TRIANGLES;
1234 case VK_POLYGON_MODE_LINE:
1235 return V_028814_X_DRAW_LINES;
1236 case VK_POLYGON_MODE_POINT:
1237 return V_028814_X_DRAW_POINTS;
1238 default:
1239 assert(0);
1240 return V_028814_X_DRAW_POINTS;
1241 }
1242 }
1243 static void
1244 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
1245 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1246 {
1247 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
1248 struct radv_raster_state *raster = &pipeline->graphics.raster;
1249
1250 memset(raster, 0, sizeof(*raster));
1251
1252 raster->spi_interp_control =
1253 S_0286D4_FLAT_SHADE_ENA(1) |
1254 S_0286D4_PNT_SPRITE_ENA(1) |
1255 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1256 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1257 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1258 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
1259 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
1260
1261
1262 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
1263 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
1264 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1265 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1266 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
1267 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1268
1269 raster->pa_su_vtx_cntl =
1270 S_028BE4_PIX_CENTER(1) | // TODO verify
1271 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
1272 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
1273
1274 raster->pa_su_sc_mode_cntl =
1275 S_028814_FACE(vkraster->frontFace) |
1276 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
1277 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
1278 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
1279 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1280 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1281 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1282 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1283 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
1284
1285 }
1286
1287 static void
1288 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1289 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1290 {
1291 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1292 struct radv_blend_state *blend = &pipeline->graphics.blend;
1293 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1294 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1295 int ps_iter_samples = 1;
1296 uint32_t mask = 0xffff;
1297
1298 if (vkms)
1299 ms->num_samples = vkms->rasterizationSamples;
1300 else
1301 ms->num_samples = 1;
1302
1303 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.force_persample) {
1304 ps_iter_samples = ms->num_samples;
1305 }
1306
1307 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1308 ms->pa_sc_aa_config = 0;
1309 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1310 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1311 ms->pa_sc_mode_cntl_1 =
1312 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1313 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1314 /* always 1: */
1315 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1316 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1317 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1318 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1319 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1320 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1321
1322 if (ms->num_samples > 1) {
1323 unsigned log_samples = util_logbase2(ms->num_samples);
1324 unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples));
1325 ms->pa_sc_mode_cntl_0 = S_028A48_MSAA_ENABLE(1);
1326 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1327 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1328 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1329 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1330 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1331 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1332 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1333 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1334 ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1335 }
1336
1337 if (vkms) {
1338 if (vkms->alphaToCoverageEnable)
1339 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
1340
1341 if (vkms->pSampleMask)
1342 mask = vkms->pSampleMask[0] & 0xffff;
1343 }
1344
1345 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1346 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1347 }
1348
1349 static bool
1350 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1351 {
1352 switch (topology) {
1353 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1354 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1355 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1356 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1357 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1358 return false;
1359 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1360 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1361 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1362 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1363 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1364 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1365 return true;
1366 default:
1367 unreachable("unhandled primitive type");
1368 }
1369 }
1370
1371 static uint32_t
1372 si_translate_prim(enum VkPrimitiveTopology topology)
1373 {
1374 switch (topology) {
1375 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1376 return V_008958_DI_PT_POINTLIST;
1377 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1378 return V_008958_DI_PT_LINELIST;
1379 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1380 return V_008958_DI_PT_LINESTRIP;
1381 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1382 return V_008958_DI_PT_TRILIST;
1383 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1384 return V_008958_DI_PT_TRISTRIP;
1385 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1386 return V_008958_DI_PT_TRIFAN;
1387 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1388 return V_008958_DI_PT_LINELIST_ADJ;
1389 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1390 return V_008958_DI_PT_LINESTRIP_ADJ;
1391 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1392 return V_008958_DI_PT_TRILIST_ADJ;
1393 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1394 return V_008958_DI_PT_TRISTRIP_ADJ;
1395 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1396 return V_008958_DI_PT_PATCH;
1397 default:
1398 assert(0);
1399 return 0;
1400 }
1401 }
1402
1403 static uint32_t
1404 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1405 {
1406 switch (gl_prim) {
1407 case 0: /* GL_POINTS */
1408 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1409 case 1: /* GL_LINES */
1410 case 3: /* GL_LINE_STRIP */
1411 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1412 case 0x8E7A: /* GL_ISOLINES */
1413 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1414
1415 case 4: /* GL_TRIANGLES */
1416 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1417 case 5: /* GL_TRIANGLE_STRIP */
1418 case 7: /* GL_QUADS */
1419 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1420 default:
1421 assert(0);
1422 return 0;
1423 }
1424 }
1425
1426 static uint32_t
1427 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1428 {
1429 switch (topology) {
1430 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1431 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1432 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1433 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1434 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1435 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1436 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1437 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1438 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1439 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1440 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1441 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1442 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1443 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1444 default:
1445 assert(0);
1446 return 0;
1447 }
1448 }
1449
1450 static unsigned si_map_swizzle(unsigned swizzle)
1451 {
1452 switch (swizzle) {
1453 case VK_SWIZZLE_Y:
1454 return V_008F0C_SQ_SEL_Y;
1455 case VK_SWIZZLE_Z:
1456 return V_008F0C_SQ_SEL_Z;
1457 case VK_SWIZZLE_W:
1458 return V_008F0C_SQ_SEL_W;
1459 case VK_SWIZZLE_0:
1460 return V_008F0C_SQ_SEL_0;
1461 case VK_SWIZZLE_1:
1462 return V_008F0C_SQ_SEL_1;
1463 default: /* VK_SWIZZLE_X */
1464 return V_008F0C_SQ_SEL_X;
1465 }
1466 }
1467
1468 static void
1469 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1470 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1471 {
1472 radv_cmd_dirty_mask_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
1473 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1474 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1475
1476 pipeline->dynamic_state = default_dynamic_state;
1477
1478 if (pCreateInfo->pDynamicState) {
1479 /* Remove all of the states that are marked as dynamic */
1480 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1481 for (uint32_t s = 0; s < count; s++)
1482 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1483 }
1484
1485 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1486
1487 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1488 *
1489 * pViewportState is [...] NULL if the pipeline
1490 * has rasterization disabled.
1491 */
1492 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1493 assert(pCreateInfo->pViewportState);
1494
1495 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1496 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1497 typed_memcpy(dynamic->viewport.viewports,
1498 pCreateInfo->pViewportState->pViewports,
1499 pCreateInfo->pViewportState->viewportCount);
1500 }
1501
1502 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1503 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1504 typed_memcpy(dynamic->scissor.scissors,
1505 pCreateInfo->pViewportState->pScissors,
1506 pCreateInfo->pViewportState->scissorCount);
1507 }
1508 }
1509
1510 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1511 assert(pCreateInfo->pRasterizationState);
1512 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1513 }
1514
1515 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1516 assert(pCreateInfo->pRasterizationState);
1517 dynamic->depth_bias.bias =
1518 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1519 dynamic->depth_bias.clamp =
1520 pCreateInfo->pRasterizationState->depthBiasClamp;
1521 dynamic->depth_bias.slope =
1522 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1523 }
1524
1525 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1526 *
1527 * pColorBlendState is [...] NULL if the pipeline has rasterization
1528 * disabled or if the subpass of the render pass the pipeline is
1529 * created against does not use any color attachments.
1530 */
1531 bool uses_color_att = false;
1532 for (unsigned i = 0; i < subpass->color_count; ++i) {
1533 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1534 uses_color_att = true;
1535 break;
1536 }
1537 }
1538
1539 if (uses_color_att && states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1540 assert(pCreateInfo->pColorBlendState);
1541 typed_memcpy(dynamic->blend_constants,
1542 pCreateInfo->pColorBlendState->blendConstants, 4);
1543 }
1544
1545 /* If there is no depthstencil attachment, then don't read
1546 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1547 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1548 * no need to override the depthstencil defaults in
1549 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1550 *
1551 * Section 9.2 of the Vulkan 1.0.15 spec says:
1552 *
1553 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1554 * disabled or if the subpass of the render pass the pipeline is created
1555 * against does not use a depth/stencil attachment.
1556 */
1557 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1558 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1559 assert(pCreateInfo->pDepthStencilState);
1560
1561 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1562 dynamic->depth_bounds.min =
1563 pCreateInfo->pDepthStencilState->minDepthBounds;
1564 dynamic->depth_bounds.max =
1565 pCreateInfo->pDepthStencilState->maxDepthBounds;
1566 }
1567
1568 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1569 dynamic->stencil_compare_mask.front =
1570 pCreateInfo->pDepthStencilState->front.compareMask;
1571 dynamic->stencil_compare_mask.back =
1572 pCreateInfo->pDepthStencilState->back.compareMask;
1573 }
1574
1575 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1576 dynamic->stencil_write_mask.front =
1577 pCreateInfo->pDepthStencilState->front.writeMask;
1578 dynamic->stencil_write_mask.back =
1579 pCreateInfo->pDepthStencilState->back.writeMask;
1580 }
1581
1582 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1583 dynamic->stencil_reference.front =
1584 pCreateInfo->pDepthStencilState->front.reference;
1585 dynamic->stencil_reference.back =
1586 pCreateInfo->pDepthStencilState->back.reference;
1587 }
1588 }
1589
1590 pipeline->dynamic_state_mask = states;
1591 }
1592
1593 static union ac_shader_variant_key
1594 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo, bool as_es, bool as_ls)
1595 {
1596 union ac_shader_variant_key key;
1597 const VkPipelineVertexInputStateCreateInfo *input_state =
1598 pCreateInfo->pVertexInputState;
1599
1600 memset(&key, 0, sizeof(key));
1601 key.vs.instance_rate_inputs = 0;
1602 key.vs.as_es = as_es;
1603 key.vs.as_ls = as_ls;
1604
1605 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1606 unsigned binding;
1607 binding = input_state->pVertexAttributeDescriptions[i].binding;
1608 if (input_state->pVertexBindingDescriptions[binding].inputRate)
1609 key.vs.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1610 }
1611 return key;
1612 }
1613
1614 static void
1615 calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
1616 {
1617 struct radv_device *device = pipeline->device;
1618 unsigned num_se = device->physical_device->rad_info.max_se;
1619 unsigned wave_size = 64;
1620 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1621 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1622 unsigned alignment = 256 * num_se;
1623 /* The maximum size is 63.999 MB per SE. */
1624 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1625 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1626 struct ac_es_output_info *es_info = radv_pipeline_has_tess(pipeline) ?
1627 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1628 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1629
1630 /* Calculate the minimum size. */
1631 unsigned min_esgs_ring_size = align(es_info->esgs_itemsize * gs_vertex_reuse *
1632 wave_size, alignment);
1633 /* These are recommended sizes, not minimum sizes. */
1634 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1635 es_info->esgs_itemsize * gs_info->gs.vertices_in;
1636 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1637 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1638
1639 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1640 esgs_ring_size = align(esgs_ring_size, alignment);
1641 gsvs_ring_size = align(gsvs_ring_size, alignment);
1642
1643 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1644 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1645 }
1646
1647 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1648 unsigned *lds_size)
1649 {
1650 /* SPI barrier management bug:
1651 * Make sure we have at least 4k of LDS in use to avoid the bug.
1652 * It applies to workgroup sizes of more than one wavefront.
1653 */
1654 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1655 device->physical_device->rad_info.family == CHIP_KABINI ||
1656 device->physical_device->rad_info.family == CHIP_MULLINS)
1657 *lds_size = MAX2(*lds_size, 8);
1658 }
1659
1660 static void
1661 calculate_tess_state(struct radv_pipeline *pipeline,
1662 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1663 {
1664 unsigned num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1665 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
1666 unsigned num_tcs_patch_outputs;
1667 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
1668 unsigned input_patch_size, output_patch_size, output_patch0_offset;
1669 unsigned lds_size, hardware_lds_size;
1670 unsigned perpatch_output_offset;
1671 unsigned num_patches;
1672 struct radv_tessellation_state *tess = &pipeline->graphics.tess;
1673
1674 /* This calculates how shader inputs and outputs among VS, TCS, and TES
1675 * are laid out in LDS. */
1676 num_tcs_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outputs_written);
1677
1678 num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); //tcs->outputs_written
1679 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1680 num_tcs_patch_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.patch_outputs_written);
1681
1682 /* Ensure that we only need one wave per SIMD so we don't need to check
1683 * resource usage. Also ensures that the number of tcs in and out
1684 * vertices per threadgroup are at most 256.
1685 */
1686 input_vertex_size = num_tcs_inputs * 16;
1687 output_vertex_size = num_tcs_outputs * 16;
1688
1689 input_patch_size = num_tcs_input_cp * input_vertex_size;
1690
1691 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
1692 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
1693 /* Ensure that we only need one wave per SIMD so we don't need to check
1694 * resource usage. Also ensures that the number of tcs in and out
1695 * vertices per threadgroup are at most 256.
1696 */
1697 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
1698
1699 /* Make sure that the data fits in LDS. This assumes the shaders only
1700 * use LDS for the inputs and outputs.
1701 */
1702 hardware_lds_size = pipeline->device->physical_device->rad_info.chip_class >= CIK ? 65536 : 32768;
1703 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
1704
1705 /* Make sure the output data fits in the offchip buffer */
1706 num_patches = MIN2(num_patches,
1707 (pipeline->device->tess_offchip_block_dw_size * 4) /
1708 output_patch_size);
1709
1710 /* Not necessary for correctness, but improves performance. The
1711 * specific value is taken from the proprietary driver.
1712 */
1713 num_patches = MIN2(num_patches, 40);
1714
1715 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
1716 if (pipeline->device->physical_device->rad_info.chip_class == SI) {
1717 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
1718 num_patches = MIN2(num_patches, one_wave);
1719 }
1720
1721 output_patch0_offset = input_patch_size * num_patches;
1722 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
1723
1724 lds_size = output_patch0_offset + output_patch_size * num_patches;
1725
1726 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1727 assert(lds_size <= 65536);
1728 lds_size = align(lds_size, 512) / 512;
1729 } else {
1730 assert(lds_size <= 32768);
1731 lds_size = align(lds_size, 256) / 256;
1732 }
1733 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1734
1735 tess->lds_size = lds_size;
1736
1737 tess->tcs_in_layout = (input_patch_size / 4) |
1738 ((input_vertex_size / 4) << 13);
1739 tess->tcs_out_layout = (output_patch_size / 4) |
1740 ((output_vertex_size / 4) << 13);
1741 tess->tcs_out_offsets = (output_patch0_offset / 16) |
1742 ((perpatch_output_offset / 16) << 16);
1743 tess->offchip_layout = (pervertex_output_patch_size * num_patches << 16) |
1744 (num_tcs_output_cp << 9) | num_patches;
1745
1746 tess->ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1747 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1748 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1749 tess->num_patches = num_patches;
1750 tess->num_tcs_input_cp = num_tcs_input_cp;
1751
1752 struct radv_shader_variant *tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
1753 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1754
1755 switch (tes->info.tes.primitive_mode) {
1756 case GL_TRIANGLES:
1757 type = V_028B6C_TESS_TRIANGLE;
1758 break;
1759 case GL_QUADS:
1760 type = V_028B6C_TESS_QUAD;
1761 break;
1762 case GL_ISOLINES:
1763 type = V_028B6C_TESS_ISOLINE;
1764 break;
1765 }
1766
1767 switch (tes->info.tes.spacing) {
1768 case TESS_SPACING_EQUAL:
1769 partitioning = V_028B6C_PART_INTEGER;
1770 break;
1771 case TESS_SPACING_FRACTIONAL_ODD:
1772 partitioning = V_028B6C_PART_FRAC_ODD;
1773 break;
1774 case TESS_SPACING_FRACTIONAL_EVEN:
1775 partitioning = V_028B6C_PART_FRAC_EVEN;
1776 break;
1777 default:
1778 break;
1779 }
1780
1781 if (tes->info.tes.point_mode)
1782 topology = V_028B6C_OUTPUT_POINT;
1783 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1784 topology = V_028B6C_OUTPUT_LINE;
1785 else if (tes->info.tes.ccw)
1786 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1787 else
1788 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1789
1790 if (pipeline->device->has_distributed_tess) {
1791 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1792 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1793 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1794 else
1795 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1796 } else
1797 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1798
1799 tess->tf_param = S_028B6C_TYPE(type) |
1800 S_028B6C_PARTITIONING(partitioning) |
1801 S_028B6C_TOPOLOGY(topology) |
1802 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1803 }
1804
1805 static const struct radv_prim_vertex_count prim_size_table[] = {
1806 [V_008958_DI_PT_NONE] = {0, 0},
1807 [V_008958_DI_PT_POINTLIST] = {1, 1},
1808 [V_008958_DI_PT_LINELIST] = {2, 2},
1809 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1810 [V_008958_DI_PT_TRILIST] = {3, 3},
1811 [V_008958_DI_PT_TRIFAN] = {3, 1},
1812 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1813 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1814 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1815 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1816 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1817 [V_008958_DI_PT_RECTLIST] = {3, 3},
1818 [V_008958_DI_PT_LINELOOP] = {2, 1},
1819 [V_008958_DI_PT_POLYGON] = {3, 1},
1820 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1821 };
1822
1823 static uint32_t si_vgt_gs_mode(struct radv_shader_variant *gs)
1824 {
1825 unsigned gs_max_vert_out = gs->info.gs.vertices_out;
1826 unsigned cut_mode;
1827
1828 if (gs_max_vert_out <= 128) {
1829 cut_mode = V_028A40_GS_CUT_128;
1830 } else if (gs_max_vert_out <= 256) {
1831 cut_mode = V_028A40_GS_CUT_256;
1832 } else if (gs_max_vert_out <= 512) {
1833 cut_mode = V_028A40_GS_CUT_512;
1834 } else {
1835 assert(gs_max_vert_out <= 1024);
1836 cut_mode = V_028A40_GS_CUT_1024;
1837 }
1838
1839 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1840 S_028A40_CUT_MODE(cut_mode)|
1841 S_028A40_ES_WRITE_OPTIMIZE(1) |
1842 S_028A40_GS_WRITE_OPTIMIZE(1);
1843 }
1844
1845 static void calculate_pa_cl_vs_out_cntl(struct radv_pipeline *pipeline)
1846 {
1847 struct radv_shader_variant *vs;
1848 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
1849
1850 struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
1851
1852 unsigned clip_dist_mask, cull_dist_mask, total_mask;
1853 clip_dist_mask = outinfo->clip_dist_mask;
1854 cull_dist_mask = outinfo->cull_dist_mask;
1855 total_mask = clip_dist_mask | cull_dist_mask;
1856
1857 bool misc_vec_ena = outinfo->writes_pointsize ||
1858 outinfo->writes_layer ||
1859 outinfo->writes_viewport_index;
1860 pipeline->graphics.pa_cl_vs_out_cntl =
1861 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
1862 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
1863 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
1864 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1865 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
1866 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
1867 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
1868 cull_dist_mask << 8 |
1869 clip_dist_mask;
1870
1871 }
1872 static void calculate_ps_inputs(struct radv_pipeline *pipeline)
1873 {
1874 struct radv_shader_variant *ps, *vs;
1875 struct ac_vs_output_info *outinfo;
1876
1877 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
1878 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
1879
1880 outinfo = &vs->info.vs.outinfo;
1881
1882 unsigned ps_offset = 0;
1883 if (ps->info.fs.has_pcoord) {
1884 unsigned val;
1885 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
1886 pipeline->graphics.ps_input_cntl[ps_offset] = val;
1887 ps_offset++;
1888 }
1889
1890 if (ps->info.fs.prim_id_input && (outinfo->prim_id_output != 0xffffffff)) {
1891 unsigned vs_offset, flat_shade;
1892 unsigned val;
1893 vs_offset = outinfo->prim_id_output;
1894 flat_shade = true;
1895 val = S_028644_OFFSET(vs_offset) | S_028644_FLAT_SHADE(flat_shade);
1896 pipeline->graphics.ps_input_cntl[ps_offset] = val;
1897 ++ps_offset;
1898 }
1899
1900 if (ps->info.fs.layer_input && (outinfo->layer_output != 0xffffffff)) {
1901 unsigned vs_offset, flat_shade;
1902 unsigned val;
1903 vs_offset = outinfo->layer_output;
1904 flat_shade = true;
1905 val = S_028644_OFFSET(vs_offset) | S_028644_FLAT_SHADE(flat_shade);
1906 pipeline->graphics.ps_input_cntl[ps_offset] = val;
1907 ++ps_offset;
1908 }
1909
1910 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
1911 unsigned vs_offset, flat_shade;
1912 unsigned val;
1913
1914 if (!(ps->info.fs.input_mask & (1u << i)))
1915 continue;
1916
1917 if (!(outinfo->export_mask & (1u << i))) {
1918 pipeline->graphics.ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
1919 ++ps_offset;
1920 continue;
1921 }
1922
1923 vs_offset = util_bitcount(outinfo->export_mask & ((1u << i) - 1));
1924 if (outinfo->prim_id_output != 0xffffffff) {
1925 if (vs_offset >= outinfo->prim_id_output)
1926 vs_offset++;
1927 }
1928 if (outinfo->layer_output != 0xffffffff) {
1929 if (vs_offset >= outinfo->layer_output)
1930 vs_offset++;
1931 }
1932 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
1933
1934 val = S_028644_OFFSET(vs_offset) | S_028644_FLAT_SHADE(flat_shade);
1935 pipeline->graphics.ps_input_cntl[ps_offset] = val;
1936 ++ps_offset;
1937 }
1938
1939 pipeline->graphics.ps_input_cntl_num = ps_offset;
1940 }
1941
1942 VkResult
1943 radv_pipeline_init(struct radv_pipeline *pipeline,
1944 struct radv_device *device,
1945 struct radv_pipeline_cache *cache,
1946 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1947 const struct radv_graphics_pipeline_create_info *extra,
1948 const VkAllocationCallbacks *alloc)
1949 {
1950 struct radv_shader_module fs_m = {0};
1951 VkResult result;
1952
1953 if (alloc == NULL)
1954 alloc = &device->alloc;
1955
1956 pipeline->device = device;
1957 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1958
1959 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
1960 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
1961 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1962 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1963 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1964 pStages[stage] = &pCreateInfo->pStages[i];
1965 modules[stage] = radv_shader_module_from_handle(pStages[stage]->module);
1966 }
1967
1968 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
1969
1970 if (modules[MESA_SHADER_VERTEX]) {
1971 bool as_es = false;
1972 bool as_ls = false;
1973 if (modules[MESA_SHADER_TESS_CTRL])
1974 as_ls = true;
1975 else if (modules[MESA_SHADER_GEOMETRY])
1976 as_es = true;
1977 union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, as_es, as_ls);
1978
1979 pipeline->shaders[MESA_SHADER_VERTEX] =
1980 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
1981 pStages[MESA_SHADER_VERTEX]->pName,
1982 MESA_SHADER_VERTEX,
1983 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
1984 pipeline->layout, &key);
1985
1986 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX);
1987 }
1988
1989 if (modules[MESA_SHADER_GEOMETRY]) {
1990 union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, false, false);
1991
1992 pipeline->shaders[MESA_SHADER_GEOMETRY] =
1993 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_GEOMETRY],
1994 pStages[MESA_SHADER_GEOMETRY]->pName,
1995 MESA_SHADER_GEOMETRY,
1996 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo,
1997 pipeline->layout, &key);
1998
1999 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_GEOMETRY);
2000
2001 pipeline->graphics.vgt_gs_mode = si_vgt_gs_mode(pipeline->shaders[MESA_SHADER_GEOMETRY]);
2002 } else
2003 pipeline->graphics.vgt_gs_mode = 0;
2004
2005 if (modules[MESA_SHADER_TESS_EVAL]) {
2006 assert(modules[MESA_SHADER_TESS_CTRL]);
2007
2008 radv_tess_pipeline_compile(pipeline,
2009 cache,
2010 modules[MESA_SHADER_TESS_CTRL],
2011 modules[MESA_SHADER_TESS_EVAL],
2012 pStages[MESA_SHADER_TESS_CTRL]->pName,
2013 pStages[MESA_SHADER_TESS_EVAL]->pName,
2014 pStages[MESA_SHADER_TESS_CTRL]->pSpecializationInfo,
2015 pStages[MESA_SHADER_TESS_EVAL]->pSpecializationInfo,
2016 pipeline->layout,
2017 pCreateInfo->pTessellationState->patchControlPoints);
2018 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_TESS_EVAL) |
2019 mesa_to_vk_shader_stage(MESA_SHADER_TESS_CTRL);
2020 }
2021
2022 if (!modules[MESA_SHADER_FRAGMENT]) {
2023 nir_builder fs_b;
2024 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2025 fs_b.shader->info->name = ralloc_strdup(fs_b.shader, "noop_fs");
2026 fs_m.nir = fs_b.shader;
2027 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2028 }
2029
2030 if (modules[MESA_SHADER_FRAGMENT]) {
2031 union ac_shader_variant_key key;
2032 key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
2033 key.fs.is_int8 = radv_pipeline_compute_is_int8(pCreateInfo);
2034
2035 const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT];
2036
2037 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2038 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_FRAGMENT],
2039 stage ? stage->pName : "main",
2040 MESA_SHADER_FRAGMENT,
2041 stage ? stage->pSpecializationInfo : NULL,
2042 pipeline->layout, &key);
2043 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
2044 }
2045
2046 if (fs_m.nir)
2047 ralloc_free(fs_m.nir);
2048
2049 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
2050 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
2051 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
2052 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
2053 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
2054
2055 if (radv_pipeline_has_gs(pipeline)) {
2056 pipeline->graphics.gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
2057 pipeline->graphics.can_use_guardband = pipeline->graphics.gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2058 } else {
2059 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
2060 }
2061 if (extra && extra->use_rectlist) {
2062 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
2063 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2064 pipeline->graphics.can_use_guardband = true;
2065 }
2066 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
2067 /* prim vertex count will need TESS changes */
2068 pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim];
2069
2070 /* Ensure that some export memory is always allocated, for two reasons:
2071 *
2072 * 1) Correctness: The hardware ignores the EXEC mask if no export
2073 * memory is allocated, so KILL and alpha test do not work correctly
2074 * without this.
2075 * 2) Performance: Every shader needs at least a NULL export, even when
2076 * it writes no color/depth output. The NULL export instruction
2077 * stalls without this setting.
2078 *
2079 * Don't add this to CB_SHADER_MASK.
2080 */
2081 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2082 if (!pipeline->graphics.blend.spi_shader_col_format) {
2083 if (!ps->info.fs.writes_z &&
2084 !ps->info.fs.writes_stencil &&
2085 !ps->info.fs.writes_sample_mask)
2086 pipeline->graphics.blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
2087 }
2088
2089 unsigned z_order;
2090 pipeline->graphics.db_shader_control = 0;
2091 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
2092 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
2093 else
2094 z_order = V_02880C_LATE_Z;
2095
2096 pipeline->graphics.db_shader_control =
2097 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
2098 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
2099 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
2100 S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) |
2101 S_02880C_Z_ORDER(z_order) |
2102 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
2103 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
2104 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory);
2105
2106 pipeline->graphics.shader_z_format =
2107 ps->info.fs.writes_sample_mask ? V_028710_SPI_SHADER_32_ABGR :
2108 ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
2109 ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
2110 V_028710_SPI_SHADER_ZERO;
2111
2112 calculate_pa_cl_vs_out_cntl(pipeline);
2113 calculate_ps_inputs(pipeline);
2114
2115 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2116 if (pipeline->shaders[i]) {
2117 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
2118 }
2119 }
2120
2121 uint32_t stages = 0;
2122 if (radv_pipeline_has_tess(pipeline)) {
2123 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2124 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2125
2126 if (radv_pipeline_has_gs(pipeline))
2127 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2128 S_028B54_GS_EN(1) |
2129 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2130 else
2131 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2132 } else if (radv_pipeline_has_gs(pipeline))
2133 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2134 S_028B54_GS_EN(1) |
2135 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2136 pipeline->graphics.vgt_shader_stages_en = stages;
2137
2138 if (radv_pipeline_has_gs(pipeline))
2139 calculate_gs_ring_sizes(pipeline);
2140
2141 if (radv_pipeline_has_tess(pipeline)) {
2142 if (pipeline->graphics.prim == V_008958_DI_PT_PATCH) {
2143 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
2144 pipeline->graphics.prim_vertex_count.incr = 1;
2145 }
2146 calculate_tess_state(pipeline, pCreateInfo);
2147 }
2148
2149 const VkPipelineVertexInputStateCreateInfo *vi_info =
2150 pCreateInfo->pVertexInputState;
2151 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
2152 const VkVertexInputAttributeDescription *desc =
2153 &vi_info->pVertexAttributeDescriptions[i];
2154 unsigned loc = desc->location;
2155 const struct vk_format_description *format_desc;
2156 int first_non_void;
2157 uint32_t num_format, data_format;
2158 format_desc = vk_format_description(desc->format);
2159 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2160
2161 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2162 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2163
2164 pipeline->va_rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
2165 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
2166 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
2167 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
2168 S_008F0C_NUM_FORMAT(num_format) |
2169 S_008F0C_DATA_FORMAT(data_format);
2170 pipeline->va_format_size[loc] = format_desc->block.bits / 8;
2171 pipeline->va_offset[loc] = desc->offset;
2172 pipeline->va_binding[loc] = desc->binding;
2173 pipeline->num_vertex_attribs = MAX2(pipeline->num_vertex_attribs, loc + 1);
2174 }
2175
2176 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
2177 const VkVertexInputBindingDescription *desc =
2178 &vi_info->pVertexBindingDescriptions[i];
2179
2180 pipeline->binding_stride[desc->binding] = desc->stride;
2181 }
2182
2183 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2184 radv_dump_pipeline_stats(device, pipeline);
2185 }
2186
2187 result = radv_pipeline_scratch_init(device, pipeline);
2188 return result;
2189 }
2190
2191 VkResult
2192 radv_graphics_pipeline_create(
2193 VkDevice _device,
2194 VkPipelineCache _cache,
2195 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2196 const struct radv_graphics_pipeline_create_info *extra,
2197 const VkAllocationCallbacks *pAllocator,
2198 VkPipeline *pPipeline)
2199 {
2200 RADV_FROM_HANDLE(radv_device, device, _device);
2201 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2202 struct radv_pipeline *pipeline;
2203 VkResult result;
2204
2205 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2206 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2207 if (pipeline == NULL)
2208 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2209
2210 memset(pipeline, 0, sizeof(*pipeline));
2211 result = radv_pipeline_init(pipeline, device, cache,
2212 pCreateInfo, extra, pAllocator);
2213 if (result != VK_SUCCESS) {
2214 radv_pipeline_destroy(device, pipeline, pAllocator);
2215 return result;
2216 }
2217
2218 *pPipeline = radv_pipeline_to_handle(pipeline);
2219
2220 return VK_SUCCESS;
2221 }
2222
2223 VkResult radv_CreateGraphicsPipelines(
2224 VkDevice _device,
2225 VkPipelineCache pipelineCache,
2226 uint32_t count,
2227 const VkGraphicsPipelineCreateInfo* pCreateInfos,
2228 const VkAllocationCallbacks* pAllocator,
2229 VkPipeline* pPipelines)
2230 {
2231 VkResult result = VK_SUCCESS;
2232 unsigned i = 0;
2233
2234 for (; i < count; i++) {
2235 VkResult r;
2236 r = radv_graphics_pipeline_create(_device,
2237 pipelineCache,
2238 &pCreateInfos[i],
2239 NULL, pAllocator, &pPipelines[i]);
2240 if (r != VK_SUCCESS) {
2241 result = r;
2242 pPipelines[i] = VK_NULL_HANDLE;
2243 }
2244 }
2245
2246 return result;
2247 }
2248
2249 static VkResult radv_compute_pipeline_create(
2250 VkDevice _device,
2251 VkPipelineCache _cache,
2252 const VkComputePipelineCreateInfo* pCreateInfo,
2253 const VkAllocationCallbacks* pAllocator,
2254 VkPipeline* pPipeline)
2255 {
2256 RADV_FROM_HANDLE(radv_device, device, _device);
2257 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2258 RADV_FROM_HANDLE(radv_shader_module, module, pCreateInfo->stage.module);
2259 struct radv_pipeline *pipeline;
2260 VkResult result;
2261
2262 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2263 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2264 if (pipeline == NULL)
2265 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2266
2267 memset(pipeline, 0, sizeof(*pipeline));
2268 pipeline->device = device;
2269 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2270
2271 pipeline->shaders[MESA_SHADER_COMPUTE] =
2272 radv_pipeline_compile(pipeline, cache, module,
2273 pCreateInfo->stage.pName,
2274 MESA_SHADER_COMPUTE,
2275 pCreateInfo->stage.pSpecializationInfo,
2276 pipeline->layout, NULL);
2277
2278
2279 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
2280 result = radv_pipeline_scratch_init(device, pipeline);
2281 if (result != VK_SUCCESS) {
2282 radv_pipeline_destroy(device, pipeline, pAllocator);
2283 return result;
2284 }
2285
2286 *pPipeline = radv_pipeline_to_handle(pipeline);
2287
2288 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2289 radv_dump_pipeline_stats(device, pipeline);
2290 }
2291 return VK_SUCCESS;
2292 }
2293 VkResult radv_CreateComputePipelines(
2294 VkDevice _device,
2295 VkPipelineCache pipelineCache,
2296 uint32_t count,
2297 const VkComputePipelineCreateInfo* pCreateInfos,
2298 const VkAllocationCallbacks* pAllocator,
2299 VkPipeline* pPipelines)
2300 {
2301 VkResult result = VK_SUCCESS;
2302
2303 unsigned i = 0;
2304 for (; i < count; i++) {
2305 VkResult r;
2306 r = radv_compute_pipeline_create(_device, pipelineCache,
2307 &pCreateInfos[i],
2308 pAllocator, &pPipelines[i]);
2309 if (r != VK_SUCCESS) {
2310 result = r;
2311 pPipelines[i] = VK_NULL_HANDLE;
2312 }
2313 }
2314
2315 return result;
2316 }