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radv/gfx10: implement a bug workaround for GE_PC_ALLOC
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_cs.h"
33 #include "radv_shader.h"
34 #include "nir/nir.h"
35 #include "nir/nir_builder.h"
36 #include "nir/nir_xfb_info.h"
37 #include "spirv/nir_spirv.h"
38 #include "vk_util.h"
39
40 #include <llvm-c/Core.h>
41 #include <llvm-c/TargetMachine.h>
42
43 #include "sid.h"
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50 #include "ac_shader_util.h"
51 #include "main/menums.h"
52
53 struct radv_blend_state {
54 uint32_t blend_enable_4bit;
55 uint32_t need_src_alpha;
56
57 uint32_t cb_color_control;
58 uint32_t cb_target_mask;
59 uint32_t cb_target_enabled_4bit;
60 uint32_t sx_mrt_blend_opt[8];
61 uint32_t cb_blend_control[8];
62
63 uint32_t spi_shader_col_format;
64 uint32_t cb_shader_mask;
65 uint32_t db_alpha_to_mask;
66
67 uint32_t commutative_4bit;
68
69 bool single_cb_enable;
70 bool mrt0_is_dual_src;
71 };
72
73 struct radv_dsa_order_invariance {
74 /* Whether the final result in Z/S buffers is guaranteed to be
75 * invariant under changes to the order in which fragments arrive.
76 */
77 bool zs;
78
79 /* Whether the set of fragments that pass the combined Z/S test is
80 * guaranteed to be invariant under changes to the order in which
81 * fragments arrive.
82 */
83 bool pass_set;
84 };
85
86 struct radv_tessellation_state {
87 uint32_t ls_hs_config;
88 unsigned num_patches;
89 unsigned lds_size;
90 uint32_t tf_param;
91 };
92
93 struct radv_gs_state {
94 uint32_t vgt_gs_onchip_cntl;
95 uint32_t vgt_gs_max_prims_per_subgroup;
96 uint32_t vgt_esgs_ring_itemsize;
97 uint32_t lds_size;
98 };
99
100 struct radv_ngg_state {
101 uint16_t ngg_emit_size; /* in dwords */
102 uint32_t hw_max_esverts;
103 uint32_t max_gsprims;
104 uint32_t max_out_verts;
105 uint32_t prim_amp_factor;
106 uint32_t vgt_esgs_ring_itemsize;
107 bool max_vert_out_per_gs_instance;
108 };
109
110 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
111 {
112 struct radv_shader_variant *variant = NULL;
113 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
114 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
115 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
116 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
117 else if (pipeline->shaders[MESA_SHADER_VERTEX])
118 variant = pipeline->shaders[MESA_SHADER_VERTEX];
119 else
120 return false;
121 return variant->info.is_ngg;
122 }
123
124 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline)
125 {
126 if (!radv_pipeline_has_gs(pipeline))
127 return false;
128
129 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
130 * On GFX10, it might be required in rare cases if it's not possible to
131 * enable NGG.
132 */
133 if (radv_pipeline_has_ngg(pipeline))
134 return false;
135
136 assert(pipeline->gs_copy_shader);
137 return true;
138 }
139
140 static void
141 radv_pipeline_destroy(struct radv_device *device,
142 struct radv_pipeline *pipeline,
143 const VkAllocationCallbacks* allocator)
144 {
145 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
146 if (pipeline->shaders[i])
147 radv_shader_variant_destroy(device, pipeline->shaders[i]);
148
149 if (pipeline->gs_copy_shader)
150 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
151
152 if(pipeline->cs.buf)
153 free(pipeline->cs.buf);
154 vk_free2(&device->alloc, allocator, pipeline);
155 }
156
157 void radv_DestroyPipeline(
158 VkDevice _device,
159 VkPipeline _pipeline,
160 const VkAllocationCallbacks* pAllocator)
161 {
162 RADV_FROM_HANDLE(radv_device, device, _device);
163 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
164
165 if (!_pipeline)
166 return;
167
168 radv_pipeline_destroy(device, pipeline, pAllocator);
169 }
170
171 static uint32_t get_hash_flags(struct radv_device *device)
172 {
173 uint32_t hash_flags = 0;
174
175 if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH)
176 hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH;
177 if (device->instance->debug_flags & RADV_DEBUG_NO_NGG)
178 hash_flags |= RADV_HASH_SHADER_NO_NGG;
179 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
180 hash_flags |= RADV_HASH_SHADER_SISCHED;
181 return hash_flags;
182 }
183
184 static VkResult
185 radv_pipeline_scratch_init(struct radv_device *device,
186 struct radv_pipeline *pipeline)
187 {
188 unsigned scratch_bytes_per_wave = 0;
189 unsigned max_waves = 0;
190 unsigned min_waves = 1;
191
192 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
193 if (pipeline->shaders[i]) {
194 unsigned max_stage_waves = device->scratch_waves;
195
196 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
197 pipeline->shaders[i]->config.scratch_bytes_per_wave);
198
199 max_stage_waves = MIN2(max_stage_waves,
200 4 * device->physical_device->rad_info.num_good_compute_units *
201 (256 / pipeline->shaders[i]->config.num_vgprs));
202 max_waves = MAX2(max_waves, max_stage_waves);
203 }
204 }
205
206 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
207 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
208 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
209 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
210 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
211 }
212
213 if (scratch_bytes_per_wave)
214 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
215
216 if (scratch_bytes_per_wave && max_waves < min_waves) {
217 /* Not really true at this moment, but will be true on first
218 * execution. Avoid having hanging shaders. */
219 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
220 }
221 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
222 pipeline->max_waves = max_waves;
223 return VK_SUCCESS;
224 }
225
226 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
227 {
228 switch (op) {
229 case VK_LOGIC_OP_CLEAR:
230 return V_028808_ROP3_CLEAR;
231 case VK_LOGIC_OP_AND:
232 return V_028808_ROP3_AND;
233 case VK_LOGIC_OP_AND_REVERSE:
234 return V_028808_ROP3_AND_REVERSE;
235 case VK_LOGIC_OP_COPY:
236 return V_028808_ROP3_COPY;
237 case VK_LOGIC_OP_AND_INVERTED:
238 return V_028808_ROP3_AND_INVERTED;
239 case VK_LOGIC_OP_NO_OP:
240 return V_028808_ROP3_NO_OP;
241 case VK_LOGIC_OP_XOR:
242 return V_028808_ROP3_XOR;
243 case VK_LOGIC_OP_OR:
244 return V_028808_ROP3_OR;
245 case VK_LOGIC_OP_NOR:
246 return V_028808_ROP3_NOR;
247 case VK_LOGIC_OP_EQUIVALENT:
248 return V_028808_ROP3_EQUIVALENT;
249 case VK_LOGIC_OP_INVERT:
250 return V_028808_ROP3_INVERT;
251 case VK_LOGIC_OP_OR_REVERSE:
252 return V_028808_ROP3_OR_REVERSE;
253 case VK_LOGIC_OP_COPY_INVERTED:
254 return V_028808_ROP3_COPY_INVERTED;
255 case VK_LOGIC_OP_OR_INVERTED:
256 return V_028808_ROP3_OR_INVERTED;
257 case VK_LOGIC_OP_NAND:
258 return V_028808_ROP3_NAND;
259 case VK_LOGIC_OP_SET:
260 return V_028808_ROP3_SET;
261 default:
262 unreachable("Unhandled logic op");
263 }
264 }
265
266
267 static uint32_t si_translate_blend_function(VkBlendOp op)
268 {
269 switch (op) {
270 case VK_BLEND_OP_ADD:
271 return V_028780_COMB_DST_PLUS_SRC;
272 case VK_BLEND_OP_SUBTRACT:
273 return V_028780_COMB_SRC_MINUS_DST;
274 case VK_BLEND_OP_REVERSE_SUBTRACT:
275 return V_028780_COMB_DST_MINUS_SRC;
276 case VK_BLEND_OP_MIN:
277 return V_028780_COMB_MIN_DST_SRC;
278 case VK_BLEND_OP_MAX:
279 return V_028780_COMB_MAX_DST_SRC;
280 default:
281 return 0;
282 }
283 }
284
285 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
286 {
287 switch (factor) {
288 case VK_BLEND_FACTOR_ZERO:
289 return V_028780_BLEND_ZERO;
290 case VK_BLEND_FACTOR_ONE:
291 return V_028780_BLEND_ONE;
292 case VK_BLEND_FACTOR_SRC_COLOR:
293 return V_028780_BLEND_SRC_COLOR;
294 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
295 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
296 case VK_BLEND_FACTOR_DST_COLOR:
297 return V_028780_BLEND_DST_COLOR;
298 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
299 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
300 case VK_BLEND_FACTOR_SRC_ALPHA:
301 return V_028780_BLEND_SRC_ALPHA;
302 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
303 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
304 case VK_BLEND_FACTOR_DST_ALPHA:
305 return V_028780_BLEND_DST_ALPHA;
306 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
307 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
308 case VK_BLEND_FACTOR_CONSTANT_COLOR:
309 return V_028780_BLEND_CONSTANT_COLOR;
310 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
311 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
312 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
313 return V_028780_BLEND_CONSTANT_ALPHA;
314 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
315 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
316 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
317 return V_028780_BLEND_SRC_ALPHA_SATURATE;
318 case VK_BLEND_FACTOR_SRC1_COLOR:
319 return V_028780_BLEND_SRC1_COLOR;
320 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
321 return V_028780_BLEND_INV_SRC1_COLOR;
322 case VK_BLEND_FACTOR_SRC1_ALPHA:
323 return V_028780_BLEND_SRC1_ALPHA;
324 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
325 return V_028780_BLEND_INV_SRC1_ALPHA;
326 default:
327 return 0;
328 }
329 }
330
331 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
332 {
333 switch (op) {
334 case VK_BLEND_OP_ADD:
335 return V_028760_OPT_COMB_ADD;
336 case VK_BLEND_OP_SUBTRACT:
337 return V_028760_OPT_COMB_SUBTRACT;
338 case VK_BLEND_OP_REVERSE_SUBTRACT:
339 return V_028760_OPT_COMB_REVSUBTRACT;
340 case VK_BLEND_OP_MIN:
341 return V_028760_OPT_COMB_MIN;
342 case VK_BLEND_OP_MAX:
343 return V_028760_OPT_COMB_MAX;
344 default:
345 return V_028760_OPT_COMB_BLEND_DISABLED;
346 }
347 }
348
349 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
350 {
351 switch (factor) {
352 case VK_BLEND_FACTOR_ZERO:
353 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
354 case VK_BLEND_FACTOR_ONE:
355 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
356 case VK_BLEND_FACTOR_SRC_COLOR:
357 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
358 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
359 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
360 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
361 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
362 case VK_BLEND_FACTOR_SRC_ALPHA:
363 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
364 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
365 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
366 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
367 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
368 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
369 default:
370 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
371 }
372 }
373
374 /**
375 * Get rid of DST in the blend factors by commuting the operands:
376 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
377 */
378 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
379 unsigned *dst_factor, unsigned expected_dst,
380 unsigned replacement_src)
381 {
382 if (*src_factor == expected_dst &&
383 *dst_factor == VK_BLEND_FACTOR_ZERO) {
384 *src_factor = VK_BLEND_FACTOR_ZERO;
385 *dst_factor = replacement_src;
386
387 /* Commuting the operands requires reversing subtractions. */
388 if (*func == VK_BLEND_OP_SUBTRACT)
389 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
390 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
391 *func = VK_BLEND_OP_SUBTRACT;
392 }
393 }
394
395 static bool si_blend_factor_uses_dst(unsigned factor)
396 {
397 return factor == VK_BLEND_FACTOR_DST_COLOR ||
398 factor == VK_BLEND_FACTOR_DST_ALPHA ||
399 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
400 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
401 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
402 }
403
404 static bool is_dual_src(VkBlendFactor factor)
405 {
406 switch (factor) {
407 case VK_BLEND_FACTOR_SRC1_COLOR:
408 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
409 case VK_BLEND_FACTOR_SRC1_ALPHA:
410 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
411 return true;
412 default:
413 return false;
414 }
415 }
416
417 static unsigned si_choose_spi_color_format(VkFormat vk_format,
418 bool blend_enable,
419 bool blend_need_alpha)
420 {
421 const struct vk_format_description *desc = vk_format_description(vk_format);
422 unsigned format, ntype, swap;
423
424 /* Alpha is needed for alpha-to-coverage.
425 * Blending may be with or without alpha.
426 */
427 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
428 unsigned alpha = 0; /* exports alpha, but may not support blending */
429 unsigned blend = 0; /* supports blending, but may not export alpha */
430 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
431
432 format = radv_translate_colorformat(vk_format);
433 ntype = radv_translate_color_numformat(vk_format, desc,
434 vk_format_get_first_non_void_channel(vk_format));
435 swap = radv_translate_colorswap(vk_format, false);
436
437 /* Choose the SPI color formats. These are required values for Stoney/RB+.
438 * Other chips have multiple choices, though they are not necessarily better.
439 */
440 switch (format) {
441 case V_028C70_COLOR_5_6_5:
442 case V_028C70_COLOR_1_5_5_5:
443 case V_028C70_COLOR_5_5_5_1:
444 case V_028C70_COLOR_4_4_4_4:
445 case V_028C70_COLOR_10_11_11:
446 case V_028C70_COLOR_11_11_10:
447 case V_028C70_COLOR_8:
448 case V_028C70_COLOR_8_8:
449 case V_028C70_COLOR_8_8_8_8:
450 case V_028C70_COLOR_10_10_10_2:
451 case V_028C70_COLOR_2_10_10_10:
452 if (ntype == V_028C70_NUMBER_UINT)
453 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
454 else if (ntype == V_028C70_NUMBER_SINT)
455 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
456 else
457 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
458 break;
459
460 case V_028C70_COLOR_16:
461 case V_028C70_COLOR_16_16:
462 case V_028C70_COLOR_16_16_16_16:
463 if (ntype == V_028C70_NUMBER_UNORM ||
464 ntype == V_028C70_NUMBER_SNORM) {
465 /* UNORM16 and SNORM16 don't support blending */
466 if (ntype == V_028C70_NUMBER_UNORM)
467 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
468 else
469 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
470
471 /* Use 32 bits per channel for blending. */
472 if (format == V_028C70_COLOR_16) {
473 if (swap == V_028C70_SWAP_STD) { /* R */
474 blend = V_028714_SPI_SHADER_32_R;
475 blend_alpha = V_028714_SPI_SHADER_32_AR;
476 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
477 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
478 else
479 assert(0);
480 } else if (format == V_028C70_COLOR_16_16) {
481 if (swap == V_028C70_SWAP_STD) { /* RG */
482 blend = V_028714_SPI_SHADER_32_GR;
483 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
484 } else if (swap == V_028C70_SWAP_ALT) /* RA */
485 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
486 else
487 assert(0);
488 } else /* 16_16_16_16 */
489 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
490 } else if (ntype == V_028C70_NUMBER_UINT)
491 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
492 else if (ntype == V_028C70_NUMBER_SINT)
493 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
494 else if (ntype == V_028C70_NUMBER_FLOAT)
495 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
496 else
497 assert(0);
498 break;
499
500 case V_028C70_COLOR_32:
501 if (swap == V_028C70_SWAP_STD) { /* R */
502 blend = normal = V_028714_SPI_SHADER_32_R;
503 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
504 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
505 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
506 else
507 assert(0);
508 break;
509
510 case V_028C70_COLOR_32_32:
511 if (swap == V_028C70_SWAP_STD) { /* RG */
512 blend = normal = V_028714_SPI_SHADER_32_GR;
513 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
514 } else if (swap == V_028C70_SWAP_ALT) /* RA */
515 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
516 else
517 assert(0);
518 break;
519
520 case V_028C70_COLOR_32_32_32_32:
521 case V_028C70_COLOR_8_24:
522 case V_028C70_COLOR_24_8:
523 case V_028C70_COLOR_X24_8_32_FLOAT:
524 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
525 break;
526
527 default:
528 unreachable("unhandled blend format");
529 }
530
531 if (blend_enable && blend_need_alpha)
532 return blend_alpha;
533 else if(blend_need_alpha)
534 return alpha;
535 else if(blend_enable)
536 return blend;
537 else
538 return normal;
539 }
540
541 static void
542 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
543 const VkGraphicsPipelineCreateInfo *pCreateInfo,
544 struct radv_blend_state *blend)
545 {
546 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
547 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
548 unsigned col_format = 0;
549 unsigned num_targets;
550
551 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
552 unsigned cf;
553
554 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
555 cf = V_028714_SPI_SHADER_ZERO;
556 } else {
557 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
558 bool blend_enable =
559 blend->blend_enable_4bit & (0xfu << (i * 4));
560
561 cf = si_choose_spi_color_format(attachment->format,
562 blend_enable,
563 blend->need_src_alpha & (1 << i));
564 }
565
566 col_format |= cf << (4 * i);
567 }
568
569 if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
570 /* When a subpass doesn't have any color attachments, write the
571 * alpha channel of MRT0 when alpha coverage is enabled because
572 * the depth attachment needs it.
573 */
574 col_format |= V_028714_SPI_SHADER_32_AR;
575 }
576
577 /* If the i-th target format is set, all previous target formats must
578 * be non-zero to avoid hangs.
579 */
580 num_targets = (util_last_bit(col_format) + 3) / 4;
581 for (unsigned i = 0; i < num_targets; i++) {
582 if (!(col_format & (0xf << (i * 4)))) {
583 col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
584 }
585 }
586
587 /* The output for dual source blending should have the same format as
588 * the first output.
589 */
590 if (blend->mrt0_is_dual_src)
591 col_format |= (col_format & 0xf) << 4;
592
593 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
594 blend->spi_shader_col_format = col_format;
595 }
596
597 static bool
598 format_is_int8(VkFormat format)
599 {
600 const struct vk_format_description *desc = vk_format_description(format);
601 int channel = vk_format_get_first_non_void_channel(format);
602
603 return channel >= 0 && desc->channel[channel].pure_integer &&
604 desc->channel[channel].size == 8;
605 }
606
607 static bool
608 format_is_int10(VkFormat format)
609 {
610 const struct vk_format_description *desc = vk_format_description(format);
611
612 if (desc->nr_channels != 4)
613 return false;
614 for (unsigned i = 0; i < 4; i++) {
615 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
616 return true;
617 }
618 return false;
619 }
620
621 /*
622 * Ordered so that for each i,
623 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
624 */
625 const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
626 VK_FORMAT_R32_SFLOAT,
627 VK_FORMAT_R32G32_SFLOAT,
628 VK_FORMAT_R8G8B8A8_UNORM,
629 VK_FORMAT_R16G16B16A16_UNORM,
630 VK_FORMAT_R16G16B16A16_SNORM,
631 VK_FORMAT_R16G16B16A16_UINT,
632 VK_FORMAT_R16G16B16A16_SINT,
633 VK_FORMAT_R32G32B32A32_SFLOAT,
634 VK_FORMAT_R8G8B8A8_UINT,
635 VK_FORMAT_R8G8B8A8_SINT,
636 VK_FORMAT_A2R10G10B10_UINT_PACK32,
637 VK_FORMAT_A2R10G10B10_SINT_PACK32,
638 };
639
640 unsigned radv_format_meta_fs_key(VkFormat format)
641 {
642 unsigned col_format = si_choose_spi_color_format(format, false, false);
643
644 assert(col_format != V_028714_SPI_SHADER_32_AR);
645 if (col_format >= V_028714_SPI_SHADER_32_AR)
646 --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
647
648 --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
649 bool is_int8 = format_is_int8(format);
650 bool is_int10 = format_is_int10(format);
651
652 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
653 }
654
655 static void
656 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
657 unsigned *is_int8, unsigned *is_int10)
658 {
659 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
660 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
661 *is_int8 = 0;
662 *is_int10 = 0;
663
664 for (unsigned i = 0; i < subpass->color_count; ++i) {
665 struct radv_render_pass_attachment *attachment;
666
667 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
668 continue;
669
670 attachment = pass->attachments + subpass->color_attachments[i].attachment;
671
672 if (format_is_int8(attachment->format))
673 *is_int8 |= 1 << i;
674 if (format_is_int10(attachment->format))
675 *is_int10 |= 1 << i;
676 }
677 }
678
679 static void
680 radv_blend_check_commutativity(struct radv_blend_state *blend,
681 VkBlendOp op, VkBlendFactor src,
682 VkBlendFactor dst, unsigned chanmask)
683 {
684 /* Src factor is allowed when it does not depend on Dst. */
685 static const uint32_t src_allowed =
686 (1u << VK_BLEND_FACTOR_ONE) |
687 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
688 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
689 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
690 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
691 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
692 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
693 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
694 (1u << VK_BLEND_FACTOR_ZERO) |
695 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
696 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
697 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
698 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
699 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
700 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
701
702 if (dst == VK_BLEND_FACTOR_ONE &&
703 (src_allowed & (1u << src))) {
704 /* Addition is commutative, but floating point addition isn't
705 * associative: subtle changes can be introduced via different
706 * rounding. Be conservative, only enable for min and max.
707 */
708 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
709 blend->commutative_4bit |= chanmask;
710 }
711 }
712
713 static struct radv_blend_state
714 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
715 const VkGraphicsPipelineCreateInfo *pCreateInfo,
716 const struct radv_graphics_pipeline_create_info *extra)
717 {
718 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
719 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
720 struct radv_blend_state blend = {0};
721 unsigned mode = V_028808_CB_NORMAL;
722 int i;
723
724 if (!vkblend)
725 return blend;
726
727 if (extra && extra->custom_blend_mode) {
728 blend.single_cb_enable = true;
729 mode = extra->custom_blend_mode;
730 }
731 blend.cb_color_control = 0;
732 if (vkblend->logicOpEnable)
733 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
734 else
735 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
736
737 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
738 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
739 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
740 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
741 S_028B70_OFFSET_ROUND(1);
742
743 if (vkms && vkms->alphaToCoverageEnable) {
744 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
745 blend.need_src_alpha |= 0x1;
746 }
747
748 blend.cb_target_mask = 0;
749 for (i = 0; i < vkblend->attachmentCount; i++) {
750 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
751 unsigned blend_cntl = 0;
752 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
753 VkBlendOp eqRGB = att->colorBlendOp;
754 VkBlendFactor srcRGB = att->srcColorBlendFactor;
755 VkBlendFactor dstRGB = att->dstColorBlendFactor;
756 VkBlendOp eqA = att->alphaBlendOp;
757 VkBlendFactor srcA = att->srcAlphaBlendFactor;
758 VkBlendFactor dstA = att->dstAlphaBlendFactor;
759
760 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
761
762 if (!att->colorWriteMask)
763 continue;
764
765 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
766 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
767 if (!att->blendEnable) {
768 blend.cb_blend_control[i] = blend_cntl;
769 continue;
770 }
771
772 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
773 if (i == 0)
774 blend.mrt0_is_dual_src = true;
775
776 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
777 srcRGB = VK_BLEND_FACTOR_ONE;
778 dstRGB = VK_BLEND_FACTOR_ONE;
779 }
780 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
781 srcA = VK_BLEND_FACTOR_ONE;
782 dstA = VK_BLEND_FACTOR_ONE;
783 }
784
785 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
786 0x7 << (4 * i));
787 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
788 0x8 << (4 * i));
789
790 /* Blending optimizations for RB+.
791 * These transformations don't change the behavior.
792 *
793 * First, get rid of DST in the blend factors:
794 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
795 */
796 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
797 VK_BLEND_FACTOR_DST_COLOR,
798 VK_BLEND_FACTOR_SRC_COLOR);
799
800 si_blend_remove_dst(&eqA, &srcA, &dstA,
801 VK_BLEND_FACTOR_DST_COLOR,
802 VK_BLEND_FACTOR_SRC_COLOR);
803
804 si_blend_remove_dst(&eqA, &srcA, &dstA,
805 VK_BLEND_FACTOR_DST_ALPHA,
806 VK_BLEND_FACTOR_SRC_ALPHA);
807
808 /* Look up the ideal settings from tables. */
809 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
810 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
811 srcA_opt = si_translate_blend_opt_factor(srcA, true);
812 dstA_opt = si_translate_blend_opt_factor(dstA, true);
813
814 /* Handle interdependencies. */
815 if (si_blend_factor_uses_dst(srcRGB))
816 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
817 if (si_blend_factor_uses_dst(srcA))
818 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
819
820 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
821 (dstRGB == VK_BLEND_FACTOR_ZERO ||
822 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
823 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
824 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
825
826 /* Set the final value. */
827 blend.sx_mrt_blend_opt[i] =
828 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
829 S_028760_COLOR_DST_OPT(dstRGB_opt) |
830 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
831 S_028760_ALPHA_SRC_OPT(srcA_opt) |
832 S_028760_ALPHA_DST_OPT(dstA_opt) |
833 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
834 blend_cntl |= S_028780_ENABLE(1);
835
836 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
837 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
838 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
839 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
840 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
841 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
842 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
843 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
844 }
845 blend.cb_blend_control[i] = blend_cntl;
846
847 blend.blend_enable_4bit |= 0xfu << (i * 4);
848
849 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
850 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
851 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
852 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
853 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
854 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
855 blend.need_src_alpha |= 1 << i;
856 }
857 for (i = vkblend->attachmentCount; i < 8; i++) {
858 blend.cb_blend_control[i] = 0;
859 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
860 }
861
862 if (pipeline->device->physical_device->has_rbplus) {
863 /* Disable RB+ blend optimizations for dual source blending. */
864 if (blend.mrt0_is_dual_src) {
865 for (i = 0; i < 8; i++) {
866 blend.sx_mrt_blend_opt[i] =
867 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
868 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
869 }
870 }
871
872 /* RB+ doesn't work with dual source blending, logic op and
873 * RESOLVE.
874 */
875 if (blend.mrt0_is_dual_src || vkblend->logicOpEnable ||
876 mode == V_028808_CB_RESOLVE)
877 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
878 }
879
880 if (blend.cb_target_mask)
881 blend.cb_color_control |= S_028808_MODE(mode);
882 else
883 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
884
885 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
886 return blend;
887 }
888
889 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
890 {
891 switch (op) {
892 case VK_STENCIL_OP_KEEP:
893 return V_02842C_STENCIL_KEEP;
894 case VK_STENCIL_OP_ZERO:
895 return V_02842C_STENCIL_ZERO;
896 case VK_STENCIL_OP_REPLACE:
897 return V_02842C_STENCIL_REPLACE_TEST;
898 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
899 return V_02842C_STENCIL_ADD_CLAMP;
900 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
901 return V_02842C_STENCIL_SUB_CLAMP;
902 case VK_STENCIL_OP_INVERT:
903 return V_02842C_STENCIL_INVERT;
904 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
905 return V_02842C_STENCIL_ADD_WRAP;
906 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
907 return V_02842C_STENCIL_SUB_WRAP;
908 default:
909 return 0;
910 }
911 }
912
913 static uint32_t si_translate_fill(VkPolygonMode func)
914 {
915 switch(func) {
916 case VK_POLYGON_MODE_FILL:
917 return V_028814_X_DRAW_TRIANGLES;
918 case VK_POLYGON_MODE_LINE:
919 return V_028814_X_DRAW_LINES;
920 case VK_POLYGON_MODE_POINT:
921 return V_028814_X_DRAW_POINTS;
922 default:
923 assert(0);
924 return V_028814_X_DRAW_POINTS;
925 }
926 }
927
928 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo *vkms)
929 {
930 uint32_t num_samples = vkms->rasterizationSamples;
931 uint32_t ps_iter_samples = 1;
932
933 if (vkms->sampleShadingEnable) {
934 ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
935 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
936 }
937 return ps_iter_samples;
938 }
939
940 static bool
941 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
942 {
943 return pCreateInfo->depthTestEnable &&
944 pCreateInfo->depthWriteEnable &&
945 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
946 }
947
948 static bool
949 radv_writes_stencil(const VkStencilOpState *state)
950 {
951 return state->writeMask &&
952 (state->failOp != VK_STENCIL_OP_KEEP ||
953 state->passOp != VK_STENCIL_OP_KEEP ||
954 state->depthFailOp != VK_STENCIL_OP_KEEP);
955 }
956
957 static bool
958 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
959 {
960 return pCreateInfo->stencilTestEnable &&
961 (radv_writes_stencil(&pCreateInfo->front) ||
962 radv_writes_stencil(&pCreateInfo->back));
963 }
964
965 static bool
966 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
967 {
968 return radv_is_depth_write_enabled(pCreateInfo) ||
969 radv_is_stencil_write_enabled(pCreateInfo);
970 }
971
972 static bool
973 radv_order_invariant_stencil_op(VkStencilOp op)
974 {
975 /* REPLACE is normally order invariant, except when the stencil
976 * reference value is written by the fragment shader. Tracking this
977 * interaction does not seem worth the effort, so be conservative.
978 */
979 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
980 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
981 op != VK_STENCIL_OP_REPLACE;
982 }
983
984 static bool
985 radv_order_invariant_stencil_state(const VkStencilOpState *state)
986 {
987 /* Compute whether, assuming Z writes are disabled, this stencil state
988 * is order invariant in the sense that the set of passing fragments as
989 * well as the final stencil buffer result does not depend on the order
990 * of fragments.
991 */
992 return !state->writeMask ||
993 /* The following assumes that Z writes are disabled. */
994 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
995 radv_order_invariant_stencil_op(state->passOp) &&
996 radv_order_invariant_stencil_op(state->depthFailOp)) ||
997 (state->compareOp == VK_COMPARE_OP_NEVER &&
998 radv_order_invariant_stencil_op(state->failOp));
999 }
1000
1001 static bool
1002 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
1003 struct radv_blend_state *blend,
1004 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1005 {
1006 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1007 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1008 unsigned colormask = blend->cb_target_enabled_4bit;
1009
1010 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
1011 return false;
1012
1013 /* Be conservative if a logic operation is enabled with color buffers. */
1014 if (colormask && pCreateInfo->pColorBlendState->logicOpEnable)
1015 return false;
1016
1017 /* Default depth/stencil invariance when no attachment is bound. */
1018 struct radv_dsa_order_invariance dsa_order_invariant = {
1019 .zs = true, .pass_set = true
1020 };
1021
1022 if (pCreateInfo->pDepthStencilState &&
1023 subpass->depth_stencil_attachment) {
1024 const VkPipelineDepthStencilStateCreateInfo *vkds =
1025 pCreateInfo->pDepthStencilState;
1026 struct radv_render_pass_attachment *attachment =
1027 pass->attachments + subpass->depth_stencil_attachment->attachment;
1028 bool has_stencil = vk_format_is_stencil(attachment->format);
1029 struct radv_dsa_order_invariance order_invariance[2];
1030 struct radv_shader_variant *ps =
1031 pipeline->shaders[MESA_SHADER_FRAGMENT];
1032
1033 /* Compute depth/stencil order invariance in order to know if
1034 * it's safe to enable out-of-order.
1035 */
1036 bool zfunc_is_ordered =
1037 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
1038 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
1039 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
1040 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
1041 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
1042
1043 bool nozwrite_and_order_invariant_stencil =
1044 !radv_is_ds_write_enabled(vkds) ||
1045 (!radv_is_depth_write_enabled(vkds) &&
1046 radv_order_invariant_stencil_state(&vkds->front) &&
1047 radv_order_invariant_stencil_state(&vkds->back));
1048
1049 order_invariance[1].zs =
1050 nozwrite_and_order_invariant_stencil ||
1051 (!radv_is_stencil_write_enabled(vkds) &&
1052 zfunc_is_ordered);
1053 order_invariance[0].zs =
1054 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
1055
1056 order_invariance[1].pass_set =
1057 nozwrite_and_order_invariant_stencil ||
1058 (!radv_is_stencil_write_enabled(vkds) &&
1059 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1060 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
1061 order_invariance[0].pass_set =
1062 !radv_is_depth_write_enabled(vkds) ||
1063 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1064 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
1065
1066 dsa_order_invariant = order_invariance[has_stencil];
1067 if (!dsa_order_invariant.zs)
1068 return false;
1069
1070 /* The set of PS invocations is always order invariant,
1071 * except when early Z/S tests are requested.
1072 */
1073 if (ps &&
1074 ps->info.info.ps.writes_memory &&
1075 ps->info.fs.early_fragment_test &&
1076 !dsa_order_invariant.pass_set)
1077 return false;
1078
1079 /* Determine if out-of-order rasterization should be disabled
1080 * when occlusion queries are used.
1081 */
1082 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1083 !dsa_order_invariant.pass_set;
1084 }
1085
1086 /* No color buffers are enabled for writing. */
1087 if (!colormask)
1088 return true;
1089
1090 unsigned blendmask = colormask & blend->blend_enable_4bit;
1091
1092 if (blendmask) {
1093 /* Only commutative blending. */
1094 if (blendmask & ~blend->commutative_4bit)
1095 return false;
1096
1097 if (!dsa_order_invariant.pass_set)
1098 return false;
1099 }
1100
1101 if (colormask & ~blendmask)
1102 return false;
1103
1104 return true;
1105 }
1106
1107 static void
1108 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1109 struct radv_blend_state *blend,
1110 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1111 {
1112 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1113 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1114 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1115 bool out_of_order_rast = false;
1116 int ps_iter_samples = 1;
1117 uint32_t mask = 0xffff;
1118
1119 if (vkms)
1120 ms->num_samples = vkms->rasterizationSamples;
1121 else
1122 ms->num_samples = 1;
1123
1124 if (vkms)
1125 ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
1126 if (vkms && !vkms->sampleShadingEnable && pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
1127 ps_iter_samples = ms->num_samples;
1128 }
1129
1130 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1131 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1132 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1133 /* Out-of-order rasterization is explicitly enabled by the
1134 * application.
1135 */
1136 out_of_order_rast = true;
1137 } else {
1138 /* Determine if the driver can enable out-of-order
1139 * rasterization internally.
1140 */
1141 out_of_order_rast =
1142 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1143 }
1144
1145 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1146 ms->pa_sc_aa_config = 0;
1147 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1148 S_028804_INCOHERENT_EQAA_READS(1) |
1149 S_028804_INTERPOLATE_COMP_Z(1) |
1150 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1151 ms->pa_sc_mode_cntl_1 =
1152 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1153 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1154 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
1155 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1156 /* always 1: */
1157 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1158 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1159 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1160 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1161 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1162 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1163 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1164 S_028A48_VPORT_SCISSOR_ENABLE(1);
1165
1166 if (ms->num_samples > 1) {
1167 unsigned log_samples = util_logbase2(ms->num_samples);
1168 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1169 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1170 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1171 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1172 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1173 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1174 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1175 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1176 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
1177 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1178 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1179 if (ps_iter_samples > 1)
1180 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1181 }
1182
1183 if (vkms && vkms->pSampleMask) {
1184 mask = vkms->pSampleMask[0] & 0xffff;
1185 }
1186
1187 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1188 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1189 }
1190
1191 static bool
1192 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1193 {
1194 switch (topology) {
1195 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1196 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1197 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1198 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1199 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1200 return false;
1201 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1202 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1203 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1204 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1205 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1206 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1207 return true;
1208 default:
1209 unreachable("unhandled primitive type");
1210 }
1211 }
1212
1213 static uint32_t
1214 si_translate_prim(enum VkPrimitiveTopology topology)
1215 {
1216 switch (topology) {
1217 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1218 return V_008958_DI_PT_POINTLIST;
1219 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1220 return V_008958_DI_PT_LINELIST;
1221 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1222 return V_008958_DI_PT_LINESTRIP;
1223 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1224 return V_008958_DI_PT_TRILIST;
1225 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1226 return V_008958_DI_PT_TRISTRIP;
1227 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1228 return V_008958_DI_PT_TRIFAN;
1229 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1230 return V_008958_DI_PT_LINELIST_ADJ;
1231 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1232 return V_008958_DI_PT_LINESTRIP_ADJ;
1233 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1234 return V_008958_DI_PT_TRILIST_ADJ;
1235 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1236 return V_008958_DI_PT_TRISTRIP_ADJ;
1237 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1238 return V_008958_DI_PT_PATCH;
1239 default:
1240 assert(0);
1241 return 0;
1242 }
1243 }
1244
1245 static uint32_t
1246 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1247 {
1248 switch (gl_prim) {
1249 case 0: /* GL_POINTS */
1250 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1251 case 1: /* GL_LINES */
1252 case 3: /* GL_LINE_STRIP */
1253 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1254 case 0x8E7A: /* GL_ISOLINES */
1255 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1256
1257 case 4: /* GL_TRIANGLES */
1258 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1259 case 5: /* GL_TRIANGLE_STRIP */
1260 case 7: /* GL_QUADS */
1261 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1262 default:
1263 assert(0);
1264 return 0;
1265 }
1266 }
1267
1268 static uint32_t
1269 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1270 {
1271 switch (topology) {
1272 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1273 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1274 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1275 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1276 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1277 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1278 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1279 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1280 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1281 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1282 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1283 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1284 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1285 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1286 default:
1287 assert(0);
1288 return 0;
1289 }
1290 }
1291
1292 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1293 {
1294 switch(state) {
1295 case VK_DYNAMIC_STATE_VIEWPORT:
1296 return RADV_DYNAMIC_VIEWPORT;
1297 case VK_DYNAMIC_STATE_SCISSOR:
1298 return RADV_DYNAMIC_SCISSOR;
1299 case VK_DYNAMIC_STATE_LINE_WIDTH:
1300 return RADV_DYNAMIC_LINE_WIDTH;
1301 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1302 return RADV_DYNAMIC_DEPTH_BIAS;
1303 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1304 return RADV_DYNAMIC_BLEND_CONSTANTS;
1305 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1306 return RADV_DYNAMIC_DEPTH_BOUNDS;
1307 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1308 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1309 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1310 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1311 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1312 return RADV_DYNAMIC_STENCIL_REFERENCE;
1313 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1314 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1315 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
1316 return RADV_DYNAMIC_SAMPLE_LOCATIONS;
1317 default:
1318 unreachable("Unhandled dynamic state");
1319 }
1320 }
1321
1322 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1323 {
1324 uint32_t states = RADV_DYNAMIC_ALL;
1325
1326 /* If rasterization is disabled we do not care about any of the dynamic states,
1327 * since they are all rasterization related only. */
1328 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1329 return 0;
1330
1331 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1332 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1333
1334 if (!pCreateInfo->pDepthStencilState ||
1335 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1336 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1337
1338 if (!pCreateInfo->pDepthStencilState ||
1339 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1340 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1341 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1342 RADV_DYNAMIC_STENCIL_REFERENCE);
1343
1344 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1345 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1346
1347 if (!pCreateInfo->pMultisampleState ||
1348 !vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1349 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT))
1350 states &= ~RADV_DYNAMIC_SAMPLE_LOCATIONS;
1351
1352 /* TODO: blend constants & line width. */
1353
1354 return states;
1355 }
1356
1357
1358 static void
1359 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1360 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1361 {
1362 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1363 uint32_t states = needed_states;
1364 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1365 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1366
1367 pipeline->dynamic_state = default_dynamic_state;
1368 pipeline->graphics.needed_dynamic_state = needed_states;
1369
1370 if (pCreateInfo->pDynamicState) {
1371 /* Remove all of the states that are marked as dynamic */
1372 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1373 for (uint32_t s = 0; s < count; s++)
1374 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1375 }
1376
1377 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1378
1379 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1380 assert(pCreateInfo->pViewportState);
1381
1382 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1383 if (states & RADV_DYNAMIC_VIEWPORT) {
1384 typed_memcpy(dynamic->viewport.viewports,
1385 pCreateInfo->pViewportState->pViewports,
1386 pCreateInfo->pViewportState->viewportCount);
1387 }
1388 }
1389
1390 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1391 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1392 if (states & RADV_DYNAMIC_SCISSOR) {
1393 typed_memcpy(dynamic->scissor.scissors,
1394 pCreateInfo->pViewportState->pScissors,
1395 pCreateInfo->pViewportState->scissorCount);
1396 }
1397 }
1398
1399 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1400 assert(pCreateInfo->pRasterizationState);
1401 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1402 }
1403
1404 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1405 assert(pCreateInfo->pRasterizationState);
1406 dynamic->depth_bias.bias =
1407 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1408 dynamic->depth_bias.clamp =
1409 pCreateInfo->pRasterizationState->depthBiasClamp;
1410 dynamic->depth_bias.slope =
1411 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1412 }
1413
1414 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1415 *
1416 * pColorBlendState is [...] NULL if the pipeline has rasterization
1417 * disabled or if the subpass of the render pass the pipeline is
1418 * created against does not use any color attachments.
1419 */
1420 if (subpass->has_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1421 assert(pCreateInfo->pColorBlendState);
1422 typed_memcpy(dynamic->blend_constants,
1423 pCreateInfo->pColorBlendState->blendConstants, 4);
1424 }
1425
1426 /* If there is no depthstencil attachment, then don't read
1427 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1428 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1429 * no need to override the depthstencil defaults in
1430 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1431 *
1432 * Section 9.2 of the Vulkan 1.0.15 spec says:
1433 *
1434 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1435 * disabled or if the subpass of the render pass the pipeline is created
1436 * against does not use a depth/stencil attachment.
1437 */
1438 if (needed_states && subpass->depth_stencil_attachment) {
1439 assert(pCreateInfo->pDepthStencilState);
1440
1441 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1442 dynamic->depth_bounds.min =
1443 pCreateInfo->pDepthStencilState->minDepthBounds;
1444 dynamic->depth_bounds.max =
1445 pCreateInfo->pDepthStencilState->maxDepthBounds;
1446 }
1447
1448 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1449 dynamic->stencil_compare_mask.front =
1450 pCreateInfo->pDepthStencilState->front.compareMask;
1451 dynamic->stencil_compare_mask.back =
1452 pCreateInfo->pDepthStencilState->back.compareMask;
1453 }
1454
1455 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1456 dynamic->stencil_write_mask.front =
1457 pCreateInfo->pDepthStencilState->front.writeMask;
1458 dynamic->stencil_write_mask.back =
1459 pCreateInfo->pDepthStencilState->back.writeMask;
1460 }
1461
1462 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1463 dynamic->stencil_reference.front =
1464 pCreateInfo->pDepthStencilState->front.reference;
1465 dynamic->stencil_reference.back =
1466 pCreateInfo->pDepthStencilState->back.reference;
1467 }
1468 }
1469
1470 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1471 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1472 if (needed_states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1473 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1474 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1475 typed_memcpy(dynamic->discard_rectangle.rectangles,
1476 discard_rectangle_info->pDiscardRectangles,
1477 discard_rectangle_info->discardRectangleCount);
1478 }
1479 }
1480
1481 if (needed_states & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
1482 const VkPipelineSampleLocationsStateCreateInfoEXT *sample_location_info =
1483 vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1484 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1485 /* If sampleLocationsEnable is VK_FALSE, the default sample
1486 * locations are used and the values specified in
1487 * sampleLocationsInfo are ignored.
1488 */
1489 if (sample_location_info->sampleLocationsEnable) {
1490 const VkSampleLocationsInfoEXT *pSampleLocationsInfo =
1491 &sample_location_info->sampleLocationsInfo;
1492
1493 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
1494
1495 dynamic->sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
1496 dynamic->sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
1497 dynamic->sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
1498 typed_memcpy(&dynamic->sample_location.locations[0],
1499 pSampleLocationsInfo->pSampleLocations,
1500 pSampleLocationsInfo->sampleLocationsCount);
1501 }
1502 }
1503
1504 pipeline->dynamic_state.mask = states;
1505 }
1506
1507 static struct radv_gs_state
1508 calculate_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1509 const struct radv_pipeline *pipeline)
1510 {
1511 struct radv_gs_state gs = {0};
1512 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1513 struct radv_es_output_info *es_info;
1514 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1515 es_info = radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1516 else
1517 es_info = radv_pipeline_has_tess(pipeline) ?
1518 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1519 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1520
1521 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1522 bool uses_adjacency;
1523 switch(pCreateInfo->pInputAssemblyState->topology) {
1524 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1525 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1526 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1527 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1528 uses_adjacency = true;
1529 break;
1530 default:
1531 uses_adjacency = false;
1532 break;
1533 }
1534
1535 /* All these are in dwords: */
1536 /* We can't allow using the whole LDS, because GS waves compete with
1537 * other shader stages for LDS space. */
1538 const unsigned max_lds_size = 8 * 1024;
1539 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1540 unsigned esgs_lds_size;
1541
1542 /* All these are per subgroup: */
1543 const unsigned max_out_prims = 32 * 1024;
1544 const unsigned max_es_verts = 255;
1545 const unsigned ideal_gs_prims = 64;
1546 unsigned max_gs_prims, gs_prims;
1547 unsigned min_es_verts, es_verts, worst_case_es_verts;
1548
1549 if (uses_adjacency || gs_num_invocations > 1)
1550 max_gs_prims = 127 / gs_num_invocations;
1551 else
1552 max_gs_prims = 255;
1553
1554 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1555 * Make sure we don't go over the maximum value.
1556 */
1557 if (gs_info->gs.vertices_out > 0) {
1558 max_gs_prims = MIN2(max_gs_prims,
1559 max_out_prims /
1560 (gs_info->gs.vertices_out * gs_num_invocations));
1561 }
1562 assert(max_gs_prims > 0);
1563
1564 /* If the primitive has adjacency, halve the number of vertices
1565 * that will be reused in multiple primitives.
1566 */
1567 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1568
1569 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1570 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1571
1572 /* Compute ESGS LDS size based on the worst case number of ES vertices
1573 * needed to create the target number of GS prims per subgroup.
1574 */
1575 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1576
1577 /* If total LDS usage is too big, refactor partitions based on ratio
1578 * of ESGS item sizes.
1579 */
1580 if (esgs_lds_size > max_lds_size) {
1581 /* Our target GS Prims Per Subgroup was too large. Calculate
1582 * the maximum number of GS Prims Per Subgroup that will fit
1583 * into LDS, capped by the maximum that the hardware can support.
1584 */
1585 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1586 max_gs_prims);
1587 assert(gs_prims > 0);
1588 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1589 max_es_verts);
1590
1591 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1592 assert(esgs_lds_size <= max_lds_size);
1593 }
1594
1595 /* Now calculate remaining ESGS information. */
1596 if (esgs_lds_size)
1597 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1598 else
1599 es_verts = max_es_verts;
1600
1601 /* Vertices for adjacency primitives are not always reused, so restore
1602 * it for ES_VERTS_PER_SUBGRP.
1603 */
1604 min_es_verts = gs_info->gs.vertices_in;
1605
1606 /* For normal primitives, the VGT only checks if they are past the ES
1607 * verts per subgroup after allocating a full GS primitive and if they
1608 * are, kick off a new subgroup. But if those additional ES verts are
1609 * unique (e.g. not reused) we need to make sure there is enough LDS
1610 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1611 */
1612 es_verts -= min_es_verts - 1;
1613
1614 uint32_t es_verts_per_subgroup = es_verts;
1615 uint32_t gs_prims_per_subgroup = gs_prims;
1616 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1617 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1618 gs.lds_size = align(esgs_lds_size, 128) / 128;
1619 gs.vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1620 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1621 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1622 gs.vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1623 gs.vgt_esgs_ring_itemsize = esgs_itemsize;
1624 assert(max_prims_per_subgroup <= max_out_prims);
1625
1626 return gs;
1627 }
1628
1629 static void clamp_gsprims_to_esverts(unsigned *max_gsprims, unsigned max_esverts,
1630 unsigned min_verts_per_prim, bool use_adjacency)
1631 {
1632 unsigned max_reuse = max_esverts - min_verts_per_prim;
1633 if (use_adjacency)
1634 max_reuse /= 2;
1635 *max_gsprims = MIN2(*max_gsprims, 1 + max_reuse);
1636 }
1637
1638 static unsigned
1639 radv_get_num_input_vertices(struct radv_pipeline *pipeline)
1640 {
1641 if (radv_pipeline_has_gs(pipeline)) {
1642 struct radv_shader_variant *gs =
1643 radv_get_shader(pipeline, MESA_SHADER_GEOMETRY);
1644
1645 return gs->info.gs.vertices_in;
1646 }
1647
1648 if (radv_pipeline_has_tess(pipeline)) {
1649 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
1650
1651 if (tes->info.tes.point_mode)
1652 return 1;
1653 if (tes->info.tes.primitive_mode == GL_ISOLINES)
1654 return 2;
1655 return 3;
1656 }
1657
1658 return 3;
1659 }
1660
1661 static struct radv_ngg_state
1662 calculate_ngg_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1663 struct radv_pipeline *pipeline)
1664 {
1665 struct radv_ngg_state ngg = {0};
1666 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1667 struct radv_es_output_info *es_info =
1668 radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1669 unsigned gs_type = radv_pipeline_has_gs(pipeline) ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
1670 unsigned max_verts_per_prim = radv_get_num_input_vertices(pipeline);
1671 unsigned min_verts_per_prim =
1672 gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
1673 unsigned gs_num_invocations = radv_pipeline_has_gs(pipeline) ? MAX2(gs_info->gs.invocations, 1) : 1;
1674 bool uses_adjacency;
1675 switch(pCreateInfo->pInputAssemblyState->topology) {
1676 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1677 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1678 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1679 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1680 uses_adjacency = true;
1681 break;
1682 default:
1683 uses_adjacency = false;
1684 break;
1685 }
1686
1687 /* All these are in dwords: */
1688 /* We can't allow using the whole LDS, because GS waves compete with
1689 * other shader stages for LDS space.
1690 *
1691 * Streamout can increase the ESGS buffer size later on, so be more
1692 * conservative with streamout and use 4K dwords. This may be suboptimal.
1693 *
1694 * Otherwise, use the limit of 7K dwords. The reason is that we need
1695 * to leave some headroom for the max_esverts increase at the end.
1696 *
1697 * TODO: We should really take the shader's internal LDS use into
1698 * account. The linker will fail if the size is greater than
1699 * 8K dwords.
1700 */
1701 const unsigned max_lds_size = (0 /*gs_info->info.so.num_outputs*/ ? 4 : 7) * 1024 - 128;
1702 const unsigned target_lds_size = max_lds_size;
1703 unsigned esvert_lds_size = 0;
1704 unsigned gsprim_lds_size = 0;
1705
1706 /* All these are per subgroup: */
1707 bool max_vert_out_per_gs_instance = false;
1708 unsigned max_esverts_base = 256;
1709 unsigned max_gsprims_base = 128; /* default prim group size clamp */
1710
1711 /* Hardware has the following non-natural restrictions on the value
1712 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1713 * the draw:
1714 * - at most 252 for any line input primitive type
1715 * - at most 251 for any quad input primitive type
1716 * - at most 251 for triangle strips with adjacency (this happens to
1717 * be the natural limit for triangle *lists* with adjacency)
1718 */
1719 max_esverts_base = MIN2(max_esverts_base, 251 + max_verts_per_prim - 1);
1720
1721 if (gs_type == MESA_SHADER_GEOMETRY) {
1722 unsigned max_out_verts_per_gsprim =
1723 gs_info->gs.vertices_out * gs_num_invocations;
1724
1725 if (max_out_verts_per_gsprim <= 256) {
1726 if (max_out_verts_per_gsprim) {
1727 max_gsprims_base = MIN2(max_gsprims_base,
1728 256 / max_out_verts_per_gsprim);
1729 }
1730 } else {
1731 /* Use special multi-cycling mode in which each GS
1732 * instance gets its own subgroup. Does not work with
1733 * tessellation. */
1734 max_vert_out_per_gs_instance = true;
1735 max_gsprims_base = 1;
1736 max_out_verts_per_gsprim = gs_info->gs.vertices_out;
1737 }
1738
1739 esvert_lds_size = es_info->esgs_itemsize / 4;
1740 gsprim_lds_size = (gs_info->gs.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim;
1741 } else {
1742 /* TODO: This needs to be adjusted once LDS use for compaction
1743 * after culling is implemented. */
1744 /*
1745 if (es_info->info.so.num_outputs)
1746 esvert_lds_size = 4 * es_info->info.so.num_outputs + 1;
1747 */
1748 }
1749
1750 unsigned max_gsprims = max_gsprims_base;
1751 unsigned max_esverts = max_esverts_base;
1752
1753 if (esvert_lds_size)
1754 max_esverts = MIN2(max_esverts, target_lds_size / esvert_lds_size);
1755 if (gsprim_lds_size)
1756 max_gsprims = MIN2(max_gsprims, target_lds_size / gsprim_lds_size);
1757
1758 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1759 clamp_gsprims_to_esverts(&max_gsprims, max_esverts, min_verts_per_prim, uses_adjacency);
1760 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1761
1762 if (esvert_lds_size || gsprim_lds_size) {
1763 /* Now that we have a rough proportionality between esverts
1764 * and gsprims based on the primitive type, scale both of them
1765 * down simultaneously based on required LDS space.
1766 *
1767 * We could be smarter about this if we knew how much vertex
1768 * reuse to expect.
1769 */
1770 unsigned lds_total = max_esverts * esvert_lds_size +
1771 max_gsprims * gsprim_lds_size;
1772 if (lds_total > target_lds_size) {
1773 max_esverts = max_esverts * target_lds_size / lds_total;
1774 max_gsprims = max_gsprims * target_lds_size / lds_total;
1775
1776 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1777 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1778 min_verts_per_prim, uses_adjacency);
1779 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1780 }
1781 }
1782
1783 /* Round up towards full wave sizes for better ALU utilization. */
1784 if (!max_vert_out_per_gs_instance) {
1785 const unsigned wavesize = 64;
1786 unsigned orig_max_esverts;
1787 unsigned orig_max_gsprims;
1788 do {
1789 orig_max_esverts = max_esverts;
1790 orig_max_gsprims = max_gsprims;
1791
1792 max_esverts = align(max_esverts, wavesize);
1793 max_esverts = MIN2(max_esverts, max_esverts_base);
1794 if (esvert_lds_size)
1795 max_esverts = MIN2(max_esverts,
1796 (max_lds_size - max_gsprims * gsprim_lds_size) /
1797 esvert_lds_size);
1798 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1799
1800 max_gsprims = align(max_gsprims, wavesize);
1801 max_gsprims = MIN2(max_gsprims, max_gsprims_base);
1802 if (gsprim_lds_size)
1803 max_gsprims = MIN2(max_gsprims,
1804 (max_lds_size - max_esverts * esvert_lds_size) /
1805 gsprim_lds_size);
1806 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1807 min_verts_per_prim, uses_adjacency);
1808 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1809 } while (orig_max_esverts != max_esverts || orig_max_gsprims != max_gsprims);
1810 }
1811
1812 /* Hardware restriction: minimum value of max_esverts */
1813 max_esverts = MAX2(max_esverts, 23 + max_verts_per_prim);
1814
1815 unsigned max_out_vertices =
1816 max_vert_out_per_gs_instance ? gs_info->gs.vertices_out :
1817 gs_type == MESA_SHADER_GEOMETRY ?
1818 max_gsprims * gs_num_invocations * gs_info->gs.vertices_out :
1819 max_esverts;
1820 assert(max_out_vertices <= 256);
1821
1822 unsigned prim_amp_factor = 1;
1823 if (gs_type == MESA_SHADER_GEOMETRY) {
1824 /* Number of output primitives per GS input primitive after
1825 * GS instancing. */
1826 prim_amp_factor = gs_info->gs.vertices_out;
1827 }
1828
1829 /* The GE only checks against the maximum number of ES verts after
1830 * allocating a full GS primitive. So we need to ensure that whenever
1831 * this check passes, there is enough space for a full primitive without
1832 * vertex reuse.
1833 */
1834 ngg.hw_max_esverts = max_esverts - max_verts_per_prim + 1;
1835 ngg.max_gsprims = max_gsprims;
1836 ngg.max_out_verts = max_out_vertices;
1837 ngg.prim_amp_factor = prim_amp_factor;
1838 ngg.max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
1839 ngg.ngg_emit_size = max_gsprims * gsprim_lds_size;
1840
1841 if (gs_type == MESA_SHADER_GEOMETRY) {
1842 ngg.vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
1843 } else {
1844 ngg.vgt_esgs_ring_itemsize = 1;
1845 }
1846
1847 pipeline->graphics.esgs_ring_size = 4 * max_esverts * esvert_lds_size;
1848
1849 assert(ngg.hw_max_esverts >= 24); /* HW limitation */
1850
1851 return ngg;
1852 }
1853
1854 static void
1855 calculate_gs_ring_sizes(struct radv_pipeline *pipeline, const struct radv_gs_state *gs)
1856 {
1857 struct radv_device *device = pipeline->device;
1858 unsigned num_se = device->physical_device->rad_info.max_se;
1859 unsigned wave_size = 64;
1860 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1861 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1862 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1863 */
1864 unsigned gs_vertex_reuse =
1865 (device->physical_device->rad_info.chip_class >= GFX8 ? 32 : 16) * num_se;
1866 unsigned alignment = 256 * num_se;
1867 /* The maximum size is 63.999 MB per SE. */
1868 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1869 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1870
1871 /* Calculate the minimum size. */
1872 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1873 wave_size, alignment);
1874 /* These are recommended sizes, not minimum sizes. */
1875 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1876 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1877 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1878 gs_info->gs.max_gsvs_emit_size;
1879
1880 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1881 esgs_ring_size = align(esgs_ring_size, alignment);
1882 gsvs_ring_size = align(gsvs_ring_size, alignment);
1883
1884 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
1885 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1886
1887 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1888 }
1889
1890 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1891 unsigned *lds_size)
1892 {
1893 /* If tessellation is all offchip and on-chip GS isn't used, this
1894 * workaround is not needed.
1895 */
1896 return;
1897
1898 /* SPI barrier management bug:
1899 * Make sure we have at least 4k of LDS in use to avoid the bug.
1900 * It applies to workgroup sizes of more than one wavefront.
1901 */
1902 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1903 device->physical_device->rad_info.family == CHIP_KABINI)
1904 *lds_size = MAX2(*lds_size, 8);
1905 }
1906
1907 struct radv_shader_variant *
1908 radv_get_shader(struct radv_pipeline *pipeline,
1909 gl_shader_stage stage)
1910 {
1911 if (stage == MESA_SHADER_VERTEX) {
1912 if (pipeline->shaders[MESA_SHADER_VERTEX])
1913 return pipeline->shaders[MESA_SHADER_VERTEX];
1914 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1915 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1916 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1917 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1918 } else if (stage == MESA_SHADER_TESS_EVAL) {
1919 if (!radv_pipeline_has_tess(pipeline))
1920 return NULL;
1921 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1922 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1923 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1924 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1925 }
1926 return pipeline->shaders[stage];
1927 }
1928
1929 static struct radv_tessellation_state
1930 calculate_tess_state(struct radv_pipeline *pipeline,
1931 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1932 {
1933 unsigned num_tcs_input_cp;
1934 unsigned num_tcs_output_cp;
1935 unsigned lds_size;
1936 unsigned num_patches;
1937 struct radv_tessellation_state tess = {0};
1938
1939 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1940 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1941 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1942
1943 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
1944
1945 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
1946 assert(lds_size <= 65536);
1947 lds_size = align(lds_size, 512) / 512;
1948 } else {
1949 assert(lds_size <= 32768);
1950 lds_size = align(lds_size, 256) / 256;
1951 }
1952 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1953
1954 tess.lds_size = lds_size;
1955
1956 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1957 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1958 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1959 tess.num_patches = num_patches;
1960
1961 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
1962 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1963
1964 switch (tes->info.tes.primitive_mode) {
1965 case GL_TRIANGLES:
1966 type = V_028B6C_TESS_TRIANGLE;
1967 break;
1968 case GL_QUADS:
1969 type = V_028B6C_TESS_QUAD;
1970 break;
1971 case GL_ISOLINES:
1972 type = V_028B6C_TESS_ISOLINE;
1973 break;
1974 }
1975
1976 switch (tes->info.tes.spacing) {
1977 case TESS_SPACING_EQUAL:
1978 partitioning = V_028B6C_PART_INTEGER;
1979 break;
1980 case TESS_SPACING_FRACTIONAL_ODD:
1981 partitioning = V_028B6C_PART_FRAC_ODD;
1982 break;
1983 case TESS_SPACING_FRACTIONAL_EVEN:
1984 partitioning = V_028B6C_PART_FRAC_EVEN;
1985 break;
1986 default:
1987 break;
1988 }
1989
1990 bool ccw = tes->info.tes.ccw;
1991 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state =
1992 vk_find_struct_const(pCreateInfo->pTessellationState,
1993 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
1994
1995 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT)
1996 ccw = !ccw;
1997
1998 if (tes->info.tes.point_mode)
1999 topology = V_028B6C_OUTPUT_POINT;
2000 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
2001 topology = V_028B6C_OUTPUT_LINE;
2002 else if (ccw)
2003 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2004 else
2005 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2006
2007 if (pipeline->device->has_distributed_tess) {
2008 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
2009 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
2010 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
2011 else
2012 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
2013 } else
2014 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
2015
2016 tess.tf_param = S_028B6C_TYPE(type) |
2017 S_028B6C_PARTITIONING(partitioning) |
2018 S_028B6C_TOPOLOGY(topology) |
2019 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
2020
2021 return tess;
2022 }
2023
2024 static const struct radv_prim_vertex_count prim_size_table[] = {
2025 [V_008958_DI_PT_NONE] = {0, 0},
2026 [V_008958_DI_PT_POINTLIST] = {1, 1},
2027 [V_008958_DI_PT_LINELIST] = {2, 2},
2028 [V_008958_DI_PT_LINESTRIP] = {2, 1},
2029 [V_008958_DI_PT_TRILIST] = {3, 3},
2030 [V_008958_DI_PT_TRIFAN] = {3, 1},
2031 [V_008958_DI_PT_TRISTRIP] = {3, 1},
2032 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
2033 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
2034 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
2035 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
2036 [V_008958_DI_PT_RECTLIST] = {3, 3},
2037 [V_008958_DI_PT_LINELOOP] = {2, 1},
2038 [V_008958_DI_PT_POLYGON] = {3, 1},
2039 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
2040 };
2041
2042 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
2043 {
2044 if (radv_pipeline_has_gs(pipeline))
2045 if (radv_pipeline_has_ngg(pipeline))
2046 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2047 else
2048 return &pipeline->gs_copy_shader->info.vs.outinfo;
2049 else if (radv_pipeline_has_tess(pipeline))
2050 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2051 else
2052 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2053 }
2054
2055 static void
2056 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
2057 {
2058 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
2059 int shader_count = 0;
2060
2061 if(shaders[MESA_SHADER_FRAGMENT]) {
2062 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
2063 }
2064 if(shaders[MESA_SHADER_GEOMETRY]) {
2065 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
2066 }
2067 if(shaders[MESA_SHADER_TESS_EVAL]) {
2068 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
2069 }
2070 if(shaders[MESA_SHADER_TESS_CTRL]) {
2071 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
2072 }
2073 if(shaders[MESA_SHADER_VERTEX]) {
2074 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
2075 }
2076
2077 if (shader_count > 1) {
2078 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
2079 unsigned last = ordered_shaders[0]->info.stage;
2080
2081 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
2082 ordered_shaders[1]->info.has_transform_feedback_varyings)
2083 nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
2084
2085 for (int i = 0; i < shader_count; ++i) {
2086 nir_variable_mode mask = 0;
2087
2088 if (ordered_shaders[i]->info.stage != first)
2089 mask = mask | nir_var_shader_in;
2090
2091 if (ordered_shaders[i]->info.stage != last)
2092 mask = mask | nir_var_shader_out;
2093
2094 nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
2095 radv_optimize_nir(ordered_shaders[i], false, false);
2096 }
2097 }
2098
2099 for (int i = 1; i < shader_count; ++i) {
2100 nir_lower_io_arrays_to_elements(ordered_shaders[i],
2101 ordered_shaders[i - 1]);
2102
2103 if (nir_link_opt_varyings(ordered_shaders[i],
2104 ordered_shaders[i - 1]))
2105 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2106
2107 nir_remove_dead_variables(ordered_shaders[i],
2108 nir_var_shader_out);
2109 nir_remove_dead_variables(ordered_shaders[i - 1],
2110 nir_var_shader_in);
2111
2112 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
2113 ordered_shaders[i - 1]);
2114
2115 nir_compact_varyings(ordered_shaders[i],
2116 ordered_shaders[i - 1], true);
2117
2118 if (progress) {
2119 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
2120 ac_lower_indirect_derefs(ordered_shaders[i],
2121 pipeline->device->physical_device->rad_info.chip_class);
2122 }
2123 radv_optimize_nir(ordered_shaders[i], false, false);
2124
2125 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
2126 ac_lower_indirect_derefs(ordered_shaders[i - 1],
2127 pipeline->device->physical_device->rad_info.chip_class);
2128 }
2129 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2130 }
2131 }
2132 }
2133
2134 static uint32_t
2135 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state,
2136 uint32_t attrib_binding)
2137 {
2138 for (uint32_t i = 0; i < input_state->vertexBindingDescriptionCount; i++) {
2139 const VkVertexInputBindingDescription *input_binding =
2140 &input_state->pVertexBindingDescriptions[i];
2141
2142 if (input_binding->binding == attrib_binding)
2143 return input_binding->stride;
2144 }
2145
2146 return 0;
2147 }
2148
2149 static struct radv_pipeline_key
2150 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
2151 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2152 const struct radv_blend_state *blend,
2153 bool has_view_index)
2154 {
2155 const VkPipelineVertexInputStateCreateInfo *input_state =
2156 pCreateInfo->pVertexInputState;
2157 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
2158 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
2159
2160 struct radv_pipeline_key key;
2161 memset(&key, 0, sizeof(key));
2162
2163 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
2164 key.optimisations_disabled = 1;
2165
2166 key.has_multiview_view_index = has_view_index;
2167
2168 uint32_t binding_input_rate = 0;
2169 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
2170 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
2171 if (input_state->pVertexBindingDescriptions[i].inputRate) {
2172 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
2173 binding_input_rate |= 1u << binding;
2174 instance_rate_divisors[binding] = 1;
2175 }
2176 }
2177 if (divisor_state) {
2178 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
2179 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
2180 divisor_state->pVertexBindingDivisors[i].divisor;
2181 }
2182 }
2183
2184 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
2185 const VkVertexInputAttributeDescription *desc =
2186 &input_state->pVertexAttributeDescriptions[i];
2187 const struct vk_format_description *format_desc;
2188 unsigned location = desc->location;
2189 unsigned binding = desc->binding;
2190 unsigned num_format, data_format;
2191 int first_non_void;
2192
2193 if (binding_input_rate & (1u << binding)) {
2194 key.instance_rate_inputs |= 1u << location;
2195 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
2196 }
2197
2198 format_desc = vk_format_description(desc->format);
2199 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2200
2201 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2202 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2203
2204 key.vertex_attribute_formats[location] = data_format | (num_format << 4);
2205 key.vertex_attribute_bindings[location] = desc->binding;
2206 key.vertex_attribute_offsets[location] = desc->offset;
2207 key.vertex_attribute_strides[location] = radv_get_attrib_stride(input_state, desc->binding);
2208
2209 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8 &&
2210 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
2211 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
2212 uint64_t adjust;
2213 switch(format) {
2214 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2215 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
2216 adjust = RADV_ALPHA_ADJUST_SNORM;
2217 break;
2218 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2219 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
2220 adjust = RADV_ALPHA_ADJUST_SSCALED;
2221 break;
2222 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2223 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
2224 adjust = RADV_ALPHA_ADJUST_SINT;
2225 break;
2226 default:
2227 adjust = 0;
2228 break;
2229 }
2230 key.vertex_alpha_adjust |= adjust << (2 * location);
2231 }
2232
2233 switch (desc->format) {
2234 case VK_FORMAT_B8G8R8A8_UNORM:
2235 case VK_FORMAT_B8G8R8A8_SNORM:
2236 case VK_FORMAT_B8G8R8A8_USCALED:
2237 case VK_FORMAT_B8G8R8A8_SSCALED:
2238 case VK_FORMAT_B8G8R8A8_UINT:
2239 case VK_FORMAT_B8G8R8A8_SINT:
2240 case VK_FORMAT_B8G8R8A8_SRGB:
2241 case VK_FORMAT_A2R10G10B10_UNORM_PACK32:
2242 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2243 case VK_FORMAT_A2R10G10B10_USCALED_PACK32:
2244 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2245 case VK_FORMAT_A2R10G10B10_UINT_PACK32:
2246 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2247 key.vertex_post_shuffle |= 1 << location;
2248 break;
2249 default:
2250 break;
2251 }
2252 }
2253
2254 if (pCreateInfo->pTessellationState)
2255 key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
2256
2257
2258 if (pCreateInfo->pMultisampleState &&
2259 pCreateInfo->pMultisampleState->rasterizationSamples > 1) {
2260 uint32_t num_samples = pCreateInfo->pMultisampleState->rasterizationSamples;
2261 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo->pMultisampleState);
2262 key.num_samples = num_samples;
2263 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
2264 }
2265
2266 key.col_format = blend->spi_shader_col_format;
2267 if (pipeline->device->physical_device->rad_info.chip_class < GFX8)
2268 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
2269
2270 return key;
2271 }
2272
2273 static bool
2274 radv_nir_stage_uses_xfb(const nir_shader *nir)
2275 {
2276 nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
2277 bool uses_xfb = !!xfb;
2278
2279 ralloc_free(xfb);
2280 return uses_xfb;
2281 }
2282
2283 static void
2284 radv_fill_shader_keys(struct radv_device *device,
2285 struct radv_shader_variant_key *keys,
2286 const struct radv_pipeline_key *key,
2287 nir_shader **nir)
2288 {
2289 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
2290 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
2291 keys[MESA_SHADER_VERTEX].vs.post_shuffle = key->vertex_post_shuffle;
2292 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) {
2293 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
2294 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_formats[i] = key->vertex_attribute_formats[i];
2295 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_bindings[i] = key->vertex_attribute_bindings[i];
2296 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i];
2297 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i];
2298 }
2299
2300 if (nir[MESA_SHADER_TESS_CTRL]) {
2301 keys[MESA_SHADER_VERTEX].vs_common_out.as_ls = true;
2302 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
2303 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
2304 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
2305
2306 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
2307 }
2308
2309 if (nir[MESA_SHADER_GEOMETRY]) {
2310 if (nir[MESA_SHADER_TESS_CTRL])
2311 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_es = true;
2312 else
2313 keys[MESA_SHADER_VERTEX].vs_common_out.as_es = true;
2314 }
2315
2316 if (device->physical_device->rad_info.chip_class >= GFX10 &&
2317 !(device->instance->debug_flags & RADV_DEBUG_NO_NGG)) {
2318 if (nir[MESA_SHADER_TESS_CTRL]) {
2319 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true;
2320 } else {
2321 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = true;
2322 }
2323
2324 if (nir[MESA_SHADER_TESS_CTRL] &&
2325 nir[MESA_SHADER_GEOMETRY] &&
2326 nir[MESA_SHADER_GEOMETRY]->info.gs.invocations *
2327 nir[MESA_SHADER_GEOMETRY]->info.gs.vertices_out > 256) {
2328 /* Fallback to the legacy path if tessellation is
2329 * enabled with extreme geometry because
2330 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2331 * might hang.
2332 */
2333 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2334 }
2335
2336 /* TODO: Implement streamout support for NGG. */
2337 gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
2338
2339 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
2340 if (nir[i])
2341 last_xfb_stage = i;
2342 }
2343
2344 if (nir[last_xfb_stage] &&
2345 radv_nir_stage_uses_xfb(nir[last_xfb_stage])) {
2346 if (nir[MESA_SHADER_TESS_CTRL])
2347 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2348 else
2349 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2350 }
2351 }
2352
2353 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
2354 keys[i].has_multiview_view_index = key->has_multiview_view_index;
2355
2356 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
2357 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
2358 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
2359 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
2360 keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
2361 }
2362
2363 static void
2364 merge_tess_info(struct shader_info *tes_info,
2365 const struct shader_info *tcs_info)
2366 {
2367 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2368 *
2369 * "PointMode. Controls generation of points rather than triangles
2370 * or lines. This functionality defaults to disabled, and is
2371 * enabled if either shader stage includes the execution mode.
2372 *
2373 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2374 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2375 * and OutputVertices, it says:
2376 *
2377 * "One mode must be set in at least one of the tessellation
2378 * shader stages."
2379 *
2380 * So, the fields can be set in either the TCS or TES, but they must
2381 * agree if set in both. Our backend looks at TES, so bitwise-or in
2382 * the values from the TCS.
2383 */
2384 assert(tcs_info->tess.tcs_vertices_out == 0 ||
2385 tes_info->tess.tcs_vertices_out == 0 ||
2386 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
2387 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
2388
2389 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2390 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2391 tcs_info->tess.spacing == tes_info->tess.spacing);
2392 tes_info->tess.spacing |= tcs_info->tess.spacing;
2393
2394 assert(tcs_info->tess.primitive_mode == 0 ||
2395 tes_info->tess.primitive_mode == 0 ||
2396 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
2397 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
2398 tes_info->tess.ccw |= tcs_info->tess.ccw;
2399 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
2400 }
2401
2402 static
2403 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT *ext)
2404 {
2405 if (!ext)
2406 return;
2407
2408 if (ext->pPipelineCreationFeedback) {
2409 ext->pPipelineCreationFeedback->flags = 0;
2410 ext->pPipelineCreationFeedback->duration = 0;
2411 }
2412
2413 for (unsigned i = 0; i < ext->pipelineStageCreationFeedbackCount; ++i) {
2414 ext->pPipelineStageCreationFeedbacks[i].flags = 0;
2415 ext->pPipelineStageCreationFeedbacks[i].duration = 0;
2416 }
2417 }
2418
2419 static
2420 void radv_start_feedback(VkPipelineCreationFeedbackEXT *feedback)
2421 {
2422 if (!feedback)
2423 return;
2424
2425 feedback->duration -= radv_get_current_time();
2426 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT;
2427 }
2428
2429 static
2430 void radv_stop_feedback(VkPipelineCreationFeedbackEXT *feedback, bool cache_hit)
2431 {
2432 if (!feedback)
2433 return;
2434
2435 feedback->duration += radv_get_current_time();
2436 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT |
2437 (cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0);
2438 }
2439
2440 static
2441 void radv_create_shaders(struct radv_pipeline *pipeline,
2442 struct radv_device *device,
2443 struct radv_pipeline_cache *cache,
2444 const struct radv_pipeline_key *key,
2445 const VkPipelineShaderStageCreateInfo **pStages,
2446 const VkPipelineCreateFlags flags,
2447 VkPipelineCreationFeedbackEXT *pipeline_feedback,
2448 VkPipelineCreationFeedbackEXT **stage_feedbacks)
2449 {
2450 struct radv_shader_module fs_m = {0};
2451 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2452 nir_shader *nir[MESA_SHADER_STAGES] = {0};
2453 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2454 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}};
2455 unsigned char hash[20], gs_copy_hash[20];
2456
2457 radv_start_feedback(pipeline_feedback);
2458
2459 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2460 if (pStages[i]) {
2461 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
2462 if (modules[i]->nir)
2463 _mesa_sha1_compute(modules[i]->nir->info.name,
2464 strlen(modules[i]->nir->info.name),
2465 modules[i]->sha1);
2466
2467 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
2468 }
2469 }
2470
2471 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
2472 memcpy(gs_copy_hash, hash, 20);
2473 gs_copy_hash[0] ^= 1;
2474
2475 bool found_in_application_cache = true;
2476 if (modules[MESA_SHADER_GEOMETRY]) {
2477 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2478 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants,
2479 &found_in_application_cache);
2480 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
2481 }
2482
2483 if (radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
2484 &found_in_application_cache) &&
2485 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
2486 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2487 return;
2488 }
2489
2490 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2491 nir_builder fs_b;
2492 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2493 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2494 fs_m.nir = fs_b.shader;
2495 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2496 }
2497
2498 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2499 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2500
2501 if (!modules[i])
2502 continue;
2503
2504 radv_start_feedback(stage_feedbacks[i]);
2505
2506 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2507 stage ? stage->pName : "main", i,
2508 stage ? stage->pSpecializationInfo : NULL,
2509 flags, pipeline->layout);
2510
2511 /* We don't want to alter meta shaders IR directly so clone it
2512 * first.
2513 */
2514 if (nir[i]->info.name) {
2515 nir[i] = nir_shader_clone(NULL, nir[i]);
2516 }
2517
2518 radv_stop_feedback(stage_feedbacks[i], false);
2519 }
2520
2521 if (nir[MESA_SHADER_TESS_CTRL]) {
2522 nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
2523 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2524 }
2525
2526 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2527 radv_link_shaders(pipeline, nir);
2528
2529 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2530 if (nir[i]) {
2531 NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
2532 NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
2533 nir_lower_non_uniform_ubo_access |
2534 nir_lower_non_uniform_ssbo_access |
2535 nir_lower_non_uniform_texture_access |
2536 nir_lower_non_uniform_image_access);
2537 }
2538
2539 if (radv_can_dump_shader(device, modules[i], false))
2540 nir_print_shader(nir[i], stderr);
2541 }
2542
2543 radv_fill_shader_keys(device, keys, key, nir);
2544
2545 if (nir[MESA_SHADER_FRAGMENT]) {
2546 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
2547 radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]);
2548
2549 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2550 radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
2551 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
2552 &binaries[MESA_SHADER_FRAGMENT]);
2553
2554 radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
2555 }
2556
2557 /* TODO: These are no longer used as keys we should refactor this */
2558 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2559 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
2560 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2561 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
2562 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2563 !!pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.num_input_clips_culls;
2564 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2565 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
2566 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2567 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
2568 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2569 !!pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.num_input_clips_culls;
2570 }
2571
2572 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2573 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2574 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2575 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2576 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2577
2578 radv_start_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL]);
2579
2580 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2581 pipeline->layout,
2582 &key, &binaries[MESA_SHADER_TESS_CTRL]);
2583
2584 radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false);
2585 }
2586 modules[MESA_SHADER_VERTEX] = NULL;
2587 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2588 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
2589 }
2590
2591 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2592 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2593 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2594 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2595
2596 radv_start_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY]);
2597
2598 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2599 pipeline->layout,
2600 &keys[pre_stage] , &binaries[MESA_SHADER_GEOMETRY]);
2601
2602 radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
2603 }
2604 modules[pre_stage] = NULL;
2605 }
2606
2607 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2608 if(modules[i] && !pipeline->shaders[i]) {
2609 if (i == MESA_SHADER_TESS_CTRL) {
2610 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.ls_outputs_written);
2611 }
2612 if (i == MESA_SHADER_TESS_EVAL) {
2613 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2614 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
2615 }
2616
2617 radv_start_feedback(stage_feedbacks[i]);
2618
2619 pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1,
2620 pipeline->layout,
2621 keys + i, &binaries[i]);
2622
2623 radv_stop_feedback(stage_feedbacks[i], false);
2624 }
2625 }
2626
2627 if(modules[MESA_SHADER_GEOMETRY]) {
2628 struct radv_shader_binary *gs_copy_binary = NULL;
2629 if (!pipeline->gs_copy_shader &&
2630 !radv_pipeline_has_ngg(pipeline)) {
2631 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2632 device, nir[MESA_SHADER_GEOMETRY], &gs_copy_binary,
2633 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2634 }
2635
2636 if (pipeline->gs_copy_shader) {
2637 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2638 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2639
2640 binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary;
2641 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2642
2643 radv_pipeline_cache_insert_shaders(device, cache,
2644 gs_copy_hash,
2645 variants,
2646 binaries);
2647 }
2648 free(gs_copy_binary);
2649 }
2650
2651 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
2652 binaries);
2653
2654 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2655 free(binaries[i]);
2656 if (nir[i]) {
2657 if (!pipeline->device->keep_shader_info)
2658 ralloc_free(nir[i]);
2659
2660 if (radv_can_dump_shader_stats(device, modules[i]))
2661 radv_shader_dump_stats(device,
2662 pipeline->shaders[i],
2663 i, stderr);
2664 }
2665 }
2666
2667 if (fs_m.nir)
2668 ralloc_free(fs_m.nir);
2669
2670 radv_stop_feedback(pipeline_feedback, false);
2671 }
2672
2673 static uint32_t
2674 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
2675 gl_shader_stage stage, enum chip_class chip_class)
2676 {
2677 bool has_gs = radv_pipeline_has_gs(pipeline);
2678 bool has_tess = radv_pipeline_has_tess(pipeline);
2679 bool has_ngg = radv_pipeline_has_ngg(pipeline);
2680
2681 switch (stage) {
2682 case MESA_SHADER_FRAGMENT:
2683 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
2684 case MESA_SHADER_VERTEX:
2685 if (has_tess) {
2686 if (chip_class >= GFX10) {
2687 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
2688 } else if (chip_class == GFX9) {
2689 return R_00B430_SPI_SHADER_USER_DATA_LS_0;
2690 } else {
2691 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
2692 }
2693
2694 }
2695
2696 if (has_gs) {
2697 if (chip_class >= GFX10) {
2698 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2699 } else {
2700 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
2701 }
2702 }
2703
2704 if (has_ngg)
2705 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2706
2707 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2708 case MESA_SHADER_GEOMETRY:
2709 return chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2710 R_00B230_SPI_SHADER_USER_DATA_GS_0;
2711 case MESA_SHADER_COMPUTE:
2712 return R_00B900_COMPUTE_USER_DATA_0;
2713 case MESA_SHADER_TESS_CTRL:
2714 return chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2715 R_00B430_SPI_SHADER_USER_DATA_HS_0;
2716 case MESA_SHADER_TESS_EVAL:
2717 if (has_gs) {
2718 return chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 :
2719 R_00B330_SPI_SHADER_USER_DATA_ES_0;
2720 } else if (has_ngg) {
2721 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2722 } else {
2723 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2724 }
2725 default:
2726 unreachable("unknown shader");
2727 }
2728 }
2729
2730 struct radv_bin_size_entry {
2731 unsigned bpp;
2732 VkExtent2D extent;
2733 };
2734
2735 static VkExtent2D
2736 radv_gfx9_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
2737 {
2738 static const struct radv_bin_size_entry color_size_table[][3][9] = {
2739 {
2740 /* One RB / SE */
2741 {
2742 /* One shader engine */
2743 { 0, {128, 128}},
2744 { 1, { 64, 128}},
2745 { 2, { 32, 128}},
2746 { 3, { 16, 128}},
2747 { 17, { 0, 0}},
2748 { UINT_MAX, { 0, 0}},
2749 },
2750 {
2751 /* Two shader engines */
2752 { 0, {128, 128}},
2753 { 2, { 64, 128}},
2754 { 3, { 32, 128}},
2755 { 5, { 16, 128}},
2756 { 17, { 0, 0}},
2757 { UINT_MAX, { 0, 0}},
2758 },
2759 {
2760 /* Four shader engines */
2761 { 0, {128, 128}},
2762 { 3, { 64, 128}},
2763 { 5, { 16, 128}},
2764 { 17, { 0, 0}},
2765 { UINT_MAX, { 0, 0}},
2766 },
2767 },
2768 {
2769 /* Two RB / SE */
2770 {
2771 /* One shader engine */
2772 { 0, {128, 128}},
2773 { 2, { 64, 128}},
2774 { 3, { 32, 128}},
2775 { 5, { 16, 128}},
2776 { 33, { 0, 0}},
2777 { UINT_MAX, { 0, 0}},
2778 },
2779 {
2780 /* Two shader engines */
2781 { 0, {128, 128}},
2782 { 3, { 64, 128}},
2783 { 5, { 32, 128}},
2784 { 9, { 16, 128}},
2785 { 33, { 0, 0}},
2786 { UINT_MAX, { 0, 0}},
2787 },
2788 {
2789 /* Four shader engines */
2790 { 0, {256, 256}},
2791 { 2, {128, 256}},
2792 { 3, {128, 128}},
2793 { 5, { 64, 128}},
2794 { 9, { 16, 128}},
2795 { 33, { 0, 0}},
2796 { UINT_MAX, { 0, 0}},
2797 },
2798 },
2799 {
2800 /* Four RB / SE */
2801 {
2802 /* One shader engine */
2803 { 0, {128, 256}},
2804 { 2, {128, 128}},
2805 { 3, { 64, 128}},
2806 { 5, { 32, 128}},
2807 { 9, { 16, 128}},
2808 { 33, { 0, 0}},
2809 { UINT_MAX, { 0, 0}},
2810 },
2811 {
2812 /* Two shader engines */
2813 { 0, {256, 256}},
2814 { 2, {128, 256}},
2815 { 3, {128, 128}},
2816 { 5, { 64, 128}},
2817 { 9, { 32, 128}},
2818 { 17, { 16, 128}},
2819 { 33, { 0, 0}},
2820 { UINT_MAX, { 0, 0}},
2821 },
2822 {
2823 /* Four shader engines */
2824 { 0, {256, 512}},
2825 { 2, {256, 256}},
2826 { 3, {128, 256}},
2827 { 5, {128, 128}},
2828 { 9, { 64, 128}},
2829 { 17, { 16, 128}},
2830 { 33, { 0, 0}},
2831 { UINT_MAX, { 0, 0}},
2832 },
2833 },
2834 };
2835 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
2836 {
2837 // One RB / SE
2838 {
2839 // One shader engine
2840 { 0, {128, 256}},
2841 { 2, {128, 128}},
2842 { 4, { 64, 128}},
2843 { 7, { 32, 128}},
2844 { 13, { 16, 128}},
2845 { 49, { 0, 0}},
2846 { UINT_MAX, { 0, 0}},
2847 },
2848 {
2849 // Two shader engines
2850 { 0, {256, 256}},
2851 { 2, {128, 256}},
2852 { 4, {128, 128}},
2853 { 7, { 64, 128}},
2854 { 13, { 32, 128}},
2855 { 25, { 16, 128}},
2856 { 49, { 0, 0}},
2857 { UINT_MAX, { 0, 0}},
2858 },
2859 {
2860 // Four shader engines
2861 { 0, {256, 512}},
2862 { 2, {256, 256}},
2863 { 4, {128, 256}},
2864 { 7, {128, 128}},
2865 { 13, { 64, 128}},
2866 { 25, { 16, 128}},
2867 { 49, { 0, 0}},
2868 { UINT_MAX, { 0, 0}},
2869 },
2870 },
2871 {
2872 // Two RB / SE
2873 {
2874 // One shader engine
2875 { 0, {256, 256}},
2876 { 2, {128, 256}},
2877 { 4, {128, 128}},
2878 { 7, { 64, 128}},
2879 { 13, { 32, 128}},
2880 { 25, { 16, 128}},
2881 { 97, { 0, 0}},
2882 { UINT_MAX, { 0, 0}},
2883 },
2884 {
2885 // Two shader engines
2886 { 0, {256, 512}},
2887 { 2, {256, 256}},
2888 { 4, {128, 256}},
2889 { 7, {128, 128}},
2890 { 13, { 64, 128}},
2891 { 25, { 32, 128}},
2892 { 49, { 16, 128}},
2893 { 97, { 0, 0}},
2894 { UINT_MAX, { 0, 0}},
2895 },
2896 {
2897 // Four shader engines
2898 { 0, {512, 512}},
2899 { 2, {256, 512}},
2900 { 4, {256, 256}},
2901 { 7, {128, 256}},
2902 { 13, {128, 128}},
2903 { 25, { 64, 128}},
2904 { 49, { 16, 128}},
2905 { 97, { 0, 0}},
2906 { UINT_MAX, { 0, 0}},
2907 },
2908 },
2909 {
2910 // Four RB / SE
2911 {
2912 // One shader engine
2913 { 0, {256, 512}},
2914 { 2, {256, 256}},
2915 { 4, {128, 256}},
2916 { 7, {128, 128}},
2917 { 13, { 64, 128}},
2918 { 25, { 32, 128}},
2919 { 49, { 16, 128}},
2920 { UINT_MAX, { 0, 0}},
2921 },
2922 {
2923 // Two shader engines
2924 { 0, {512, 512}},
2925 { 2, {256, 512}},
2926 { 4, {256, 256}},
2927 { 7, {128, 256}},
2928 { 13, {128, 128}},
2929 { 25, { 64, 128}},
2930 { 49, { 32, 128}},
2931 { 97, { 16, 128}},
2932 { UINT_MAX, { 0, 0}},
2933 },
2934 {
2935 // Four shader engines
2936 { 0, {512, 512}},
2937 { 4, {256, 512}},
2938 { 7, {256, 256}},
2939 { 13, {128, 256}},
2940 { 25, {128, 128}},
2941 { 49, { 64, 128}},
2942 { 97, { 16, 128}},
2943 { UINT_MAX, { 0, 0}},
2944 },
2945 },
2946 };
2947
2948 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2949 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2950 VkExtent2D extent = {512, 512};
2951
2952 unsigned log_num_rb_per_se =
2953 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
2954 pipeline->device->physical_device->rad_info.max_se);
2955 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
2956
2957 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
2958 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
2959 unsigned effective_samples = total_samples;
2960 unsigned color_bytes_per_pixel = 0;
2961
2962 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
2963 if (vkblend) {
2964 for (unsigned i = 0; i < subpass->color_count; i++) {
2965 if (!vkblend->pAttachments[i].colorWriteMask)
2966 continue;
2967
2968 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
2969 continue;
2970
2971 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
2972 color_bytes_per_pixel += vk_format_get_blocksize(format);
2973 }
2974
2975 /* MSAA images typically don't use all samples all the time. */
2976 if (effective_samples >= 2 && ps_iter_samples <= 1)
2977 effective_samples = 2;
2978 color_bytes_per_pixel *= effective_samples;
2979 }
2980
2981 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
2982 while(color_entry[1].bpp <= color_bytes_per_pixel)
2983 ++color_entry;
2984
2985 extent = color_entry->extent;
2986
2987 if (subpass->depth_stencil_attachment) {
2988 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
2989
2990 /* Coefficients taken from AMDVLK */
2991 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
2992 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
2993 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
2994
2995 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
2996 while(ds_entry[1].bpp <= ds_bytes_per_pixel)
2997 ++ds_entry;
2998
2999 if (ds_entry->extent.width * ds_entry->extent.height < extent.width * extent.height)
3000 extent = ds_entry->extent;
3001 }
3002
3003 return extent;
3004 }
3005
3006 static VkExtent2D
3007 radv_gfx10_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3008 {
3009 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3010 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3011 VkExtent2D extent = {512, 512};
3012
3013 unsigned sdp_interface_count;
3014
3015 switch(pipeline->device->physical_device->rad_info.family) {
3016 case CHIP_NAVI10:
3017 case CHIP_NAVI12:
3018 sdp_interface_count = 16;
3019 break;
3020 case CHIP_NAVI14:
3021 sdp_interface_count = 8;
3022 break;
3023 default:
3024 unreachable("Unhandled GFX10 chip");
3025 }
3026
3027 const unsigned db_tag_size = 64;
3028 const unsigned db_tag_count = 312;
3029 const unsigned color_tag_size = 1024;
3030 const unsigned color_tag_count = 31;
3031 const unsigned fmask_tag_size = 256;
3032 const unsigned fmask_tag_count = 44;
3033
3034 const unsigned rb_count = pipeline->device->physical_device->rad_info.num_render_backends;
3035 const unsigned pipe_count = MAX2(rb_count, sdp_interface_count);
3036
3037 const unsigned db_tag_part = (db_tag_count * rb_count / pipe_count) * db_tag_size * pipe_count;
3038 const unsigned color_tag_part = (color_tag_count * rb_count / pipe_count) * color_tag_size * pipe_count;
3039 const unsigned fmask_tag_part = (fmask_tag_count * rb_count / pipe_count) * fmask_tag_size * pipe_count;
3040
3041 const unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3042 const unsigned samples_log = util_logbase2_ceil(total_samples);
3043
3044 unsigned color_bytes_per_pixel = 0;
3045 unsigned fmask_bytes_per_pixel = 0;
3046
3047 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
3048 if (vkblend) {
3049 for (unsigned i = 0; i < subpass->color_count; i++) {
3050 if (!vkblend->pAttachments[i].colorWriteMask)
3051 continue;
3052
3053 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3054 continue;
3055
3056 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3057 color_bytes_per_pixel += vk_format_get_blocksize(format);
3058
3059 if (total_samples > 1) {
3060 const unsigned fmask_array[] = {0, 1, 1, 4};
3061 fmask_bytes_per_pixel += fmask_array[samples_log];
3062 }
3063 }
3064
3065 color_bytes_per_pixel *= total_samples;
3066 }
3067 color_bytes_per_pixel = MAX2(color_bytes_per_pixel, 1);
3068
3069 const unsigned color_pixel_count_log = util_logbase2(color_tag_part / color_bytes_per_pixel);
3070 extent.width = 1ull << ((color_pixel_count_log + 1) / 2);
3071 extent.height = 1ull << (color_pixel_count_log / 2);
3072
3073 if (fmask_bytes_per_pixel) {
3074 const unsigned fmask_pixel_count_log = util_logbase2(fmask_tag_part / fmask_bytes_per_pixel);
3075
3076 const VkExtent2D fmask_extent = (VkExtent2D){
3077 .width = 1ull << ((fmask_pixel_count_log + 1) / 2),
3078 .height = 1ull << (color_pixel_count_log / 2)
3079 };
3080
3081 if (fmask_extent.width * fmask_extent.height < extent.width * extent.height)
3082 extent = fmask_extent;
3083 }
3084
3085 if (subpass->depth_stencil_attachment) {
3086 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3087
3088 /* Coefficients taken from AMDVLK */
3089 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3090 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3091 unsigned db_bytes_per_pixel = (depth_coeff + stencil_coeff) * total_samples;
3092
3093 const unsigned db_pixel_count_log = util_logbase2(db_tag_part / db_bytes_per_pixel);
3094
3095 const VkExtent2D db_extent = (VkExtent2D){
3096 .width = 1ull << ((db_pixel_count_log + 1) / 2),
3097 .height = 1ull << (color_pixel_count_log / 2)
3098 };
3099
3100 if (db_extent.width * db_extent.height < extent.width * extent.height)
3101 extent = db_extent;
3102 }
3103
3104 extent.width = MAX2(extent.width, 128);
3105 extent.height = MAX2(extent.width, 64);
3106
3107 return extent;
3108 }
3109
3110 static void
3111 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf *ctx_cs,
3112 struct radv_pipeline *pipeline,
3113 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3114 {
3115 uint32_t pa_sc_binner_cntl_0 =
3116 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
3117 S_028C44_DISABLE_START_OF_PRIM(1);
3118 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3119
3120 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3121 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3122 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3123 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
3124 unsigned min_bytes_per_pixel = 0;
3125
3126 if (vkblend) {
3127 for (unsigned i = 0; i < subpass->color_count; i++) {
3128 if (!vkblend->pAttachments[i].colorWriteMask)
3129 continue;
3130
3131 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3132 continue;
3133
3134 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3135 unsigned bytes = vk_format_get_blocksize(format);
3136 if (!min_bytes_per_pixel || bytes < min_bytes_per_pixel)
3137 min_bytes_per_pixel = bytes;
3138 }
3139 }
3140
3141 pa_sc_binner_cntl_0 =
3142 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
3143 S_028C44_BIN_SIZE_X(0) |
3144 S_028C44_BIN_SIZE_Y(0) |
3145 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3146 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel <= 4 ? 2 : 1) | /* 128 or 64 */
3147 S_028C44_DISABLE_START_OF_PRIM(1);
3148 }
3149
3150 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3151 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3152 }
3153
3154 static void
3155 radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
3156 struct radv_pipeline *pipeline,
3157 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3158 {
3159 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
3160 return;
3161
3162 VkExtent2D bin_size;
3163 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3164 bin_size = radv_gfx10_compute_bin_size(pipeline, pCreateInfo);
3165 } else if (pipeline->device->physical_device->rad_info.chip_class == GFX9) {
3166 bin_size = radv_gfx9_compute_bin_size(pipeline, pCreateInfo);
3167 } else
3168 unreachable("Unhandled generation for binning bin size calculation");
3169
3170 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
3171 unsigned context_states_per_bin; /* allowed range: [1, 6] */
3172 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
3173 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
3174
3175 if (pipeline->device->physical_device->rad_info.has_dedicated_vram) {
3176 context_states_per_bin = 1;
3177 persistent_states_per_bin = 1;
3178 fpovs_per_batch = 63;
3179 } else {
3180 context_states_per_bin = 6;
3181 persistent_states_per_bin = 32;
3182 fpovs_per_batch = 63;
3183 }
3184
3185 const uint32_t pa_sc_binner_cntl_0 =
3186 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
3187 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
3188 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
3189 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
3190 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
3191 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) |
3192 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) |
3193 S_028C44_DISABLE_START_OF_PRIM(1) |
3194 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
3195 S_028C44_OPTIMAL_BIN_SELECTION(1);
3196
3197 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3198
3199 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3200 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3201 } else
3202 radv_pipeline_generate_disabled_binning_state(ctx_cs, pipeline, pCreateInfo);
3203 }
3204
3205
3206 static void
3207 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
3208 struct radv_pipeline *pipeline,
3209 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3210 const struct radv_graphics_pipeline_create_info *extra)
3211 {
3212 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
3213 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3214 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3215 struct radv_render_pass_attachment *attachment = NULL;
3216 uint32_t db_depth_control = 0, db_stencil_control = 0;
3217 uint32_t db_render_control = 0, db_render_override2 = 0;
3218 uint32_t db_render_override = 0;
3219
3220 if (subpass->depth_stencil_attachment)
3221 attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3222
3223 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
3224 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
3225
3226 if (vkds && has_depth_attachment) {
3227 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
3228 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
3229 S_028800_ZFUNC(vkds->depthCompareOp) |
3230 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
3231
3232 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3233 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
3234 }
3235
3236 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
3237 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3238 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
3239 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
3240 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
3241 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
3242
3243 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
3244 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
3245 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
3246 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
3247 }
3248
3249 if (attachment && extra) {
3250 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
3251 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
3252
3253 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
3254 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
3255 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
3256 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
3257 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
3258 }
3259
3260 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3261 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
3262
3263 if (!pCreateInfo->pRasterizationState->depthClampEnable) {
3264 /* From VK_EXT_depth_range_unrestricted spec:
3265 *
3266 * "The behavior described in Primitive Clipping still applies.
3267 * If depth clamping is disabled the depth values are still
3268 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3269 * depth clamping is enabled the above equation is ignored and
3270 * the depth values are instead clamped to the VkViewport
3271 * minDepth and maxDepth values, which in the case of this
3272 * extension can be outside of the 0.0 to 1.0 range."
3273 */
3274 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3275 }
3276
3277 radeon_set_context_reg(ctx_cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
3278 radeon_set_context_reg(ctx_cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
3279
3280 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control);
3281 radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
3282 radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
3283 }
3284
3285 static void
3286 radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
3287 struct radv_pipeline *pipeline,
3288 const struct radv_blend_state *blend)
3289 {
3290 radeon_set_context_reg_seq(ctx_cs, R_028780_CB_BLEND0_CONTROL, 8);
3291 radeon_emit_array(ctx_cs, blend->cb_blend_control,
3292 8);
3293 radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
3294 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
3295
3296 if (pipeline->device->physical_device->has_rbplus) {
3297
3298 radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
3299 radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
3300 }
3301
3302 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
3303
3304 radeon_set_context_reg(ctx_cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
3305 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
3306
3307 pipeline->graphics.col_format = blend->spi_shader_col_format;
3308 pipeline->graphics.cb_target_mask = blend->cb_target_mask;
3309 }
3310
3311 static const VkConservativeRasterizationModeEXT
3312 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo)
3313 {
3314 const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster =
3315 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT);
3316
3317 if (!conservative_raster)
3318 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT;
3319 return conservative_raster->conservativeRasterizationMode;
3320 }
3321
3322 static void
3323 radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs,
3324 struct radv_pipeline *pipeline,
3325 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3326 {
3327 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
3328 const VkConservativeRasterizationModeEXT mode =
3329 radv_get_conservative_raster_mode(vkraster);
3330 uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3331 bool depth_clip_disable = vkraster->depthClampEnable;
3332
3333 const VkPipelineRasterizationDepthClipStateCreateInfoEXT *depth_clip_state =
3334 vk_find_struct_const(vkraster->pNext, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
3335 if (depth_clip_state) {
3336 depth_clip_disable = !depth_clip_state->depthClipEnable;
3337 }
3338
3339 radeon_set_context_reg(ctx_cs, R_028810_PA_CL_CLIP_CNTL,
3340 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3341 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable ? 1 : 0) |
3342 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable ? 1 : 0) |
3343 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
3344 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3345
3346 radeon_set_context_reg(ctx_cs, R_0286D4_SPI_INTERP_CONTROL_0,
3347 S_0286D4_FLAT_SHADE_ENA(1) |
3348 S_0286D4_PNT_SPRITE_ENA(1) |
3349 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
3350 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
3351 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
3352 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
3353 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3354
3355 radeon_set_context_reg(ctx_cs, R_028BE4_PA_SU_VTX_CNTL,
3356 S_028BE4_PIX_CENTER(1) | // TODO verify
3357 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
3358 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
3359
3360 radeon_set_context_reg(ctx_cs, R_028814_PA_SU_SC_MODE_CNTL,
3361 S_028814_FACE(vkraster->frontFace) |
3362 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
3363 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
3364 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
3365 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3366 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3367 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3368 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3369 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
3370
3371 /* Conservative rasterization. */
3372 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
3373 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3374
3375 ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3376 ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3377 S_028804_OVERRASTERIZATION_AMOUNT(4);
3378
3379 pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3380 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3381 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3382
3383 if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
3384 pa_sc_conservative_rast |=
3385 S_028C4C_OVER_RAST_ENABLE(1) |
3386 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3387 S_028C4C_UNDER_RAST_ENABLE(0) |
3388 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3389 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3390 } else {
3391 assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
3392 pa_sc_conservative_rast |=
3393 S_028C4C_OVER_RAST_ENABLE(0) |
3394 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3395 S_028C4C_UNDER_RAST_ENABLE(1) |
3396 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3397 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3398 }
3399 }
3400
3401 radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
3402 pa_sc_conservative_rast);
3403 }
3404
3405
3406 static void
3407 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
3408 struct radv_pipeline *pipeline)
3409 {
3410 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3411
3412 radeon_set_context_reg_seq(ctx_cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3413 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[0]);
3414 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]);
3415
3416 radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
3417 radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
3418
3419 /* The exclusion bits can be set to improve rasterization efficiency
3420 * if no sample lies on the pixel boundary (-8 sample offset). It's
3421 * currently always TRUE because the driver doesn't support 16 samples.
3422 */
3423 bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= GFX7;
3424 radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3425 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3426 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3427 }
3428
3429 static void
3430 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
3431 struct radv_pipeline *pipeline)
3432 {
3433 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3434 const struct radv_shader_variant *vs =
3435 pipeline->shaders[MESA_SHADER_TESS_EVAL] ?
3436 pipeline->shaders[MESA_SHADER_TESS_EVAL] :
3437 pipeline->shaders[MESA_SHADER_VERTEX];
3438 unsigned vgt_primitiveid_en = 0;
3439 uint32_t vgt_gs_mode = 0;
3440
3441 if (radv_pipeline_has_ngg(pipeline))
3442 return;
3443
3444 if (radv_pipeline_has_gs(pipeline)) {
3445 const struct radv_shader_variant *gs =
3446 pipeline->shaders[MESA_SHADER_GEOMETRY];
3447
3448 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
3449 pipeline->device->physical_device->rad_info.chip_class);
3450 } else if (outinfo->export_prim_id || vs->info.info.uses_prim_id) {
3451 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
3452 vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1);
3453 }
3454
3455 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
3456 radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
3457 }
3458
3459 static void
3460 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
3461 struct radeon_cmdbuf *cs,
3462 struct radv_pipeline *pipeline,
3463 struct radv_shader_variant *shader)
3464 {
3465 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3466
3467 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
3468 radeon_emit(cs, va >> 8);
3469 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
3470 radeon_emit(cs, shader->config.rsrc1);
3471 radeon_emit(cs, shader->config.rsrc2);
3472
3473 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3474 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3475 clip_dist_mask = outinfo->clip_dist_mask;
3476 cull_dist_mask = outinfo->cull_dist_mask;
3477 total_mask = clip_dist_mask | cull_dist_mask;
3478 bool misc_vec_ena = outinfo->writes_pointsize ||
3479 outinfo->writes_layer ||
3480 outinfo->writes_viewport_index;
3481 unsigned spi_vs_out_config, nparams;
3482
3483 /* VS is required to export at least one param. */
3484 nparams = MAX2(outinfo->param_exports, 1);
3485 spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
3486
3487 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3488 spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0);
3489 }
3490
3491 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, spi_vs_out_config);
3492
3493 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3494 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3495 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3496 V_02870C_SPI_SHADER_4COMP :
3497 V_02870C_SPI_SHADER_NONE) |
3498 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3499 V_02870C_SPI_SHADER_4COMP :
3500 V_02870C_SPI_SHADER_NONE) |
3501 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3502 V_02870C_SPI_SHADER_4COMP :
3503 V_02870C_SPI_SHADER_NONE));
3504
3505 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3506 S_028818_VTX_W0_FMT(1) |
3507 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3508 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3509 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3510
3511 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3512 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3513 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3514 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3515 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3516 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3517 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3518 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3519 cull_dist_mask << 8 |
3520 clip_dist_mask);
3521
3522 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
3523 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
3524 outinfo->writes_viewport_index);
3525 }
3526
3527 static void
3528 radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs,
3529 struct radv_pipeline *pipeline,
3530 struct radv_shader_variant *shader)
3531 {
3532 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3533
3534 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
3535 radeon_emit(cs, va >> 8);
3536 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3537 radeon_emit(cs, shader->config.rsrc1);
3538 radeon_emit(cs, shader->config.rsrc2);
3539 }
3540
3541 static void
3542 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
3543 struct radv_pipeline *pipeline,
3544 struct radv_shader_variant *shader,
3545 const struct radv_tessellation_state *tess)
3546 {
3547 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3548 uint32_t rsrc2 = shader->config.rsrc2;
3549
3550 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3551 radeon_emit(cs, va >> 8);
3552 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3553
3554 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
3555 if (pipeline->device->physical_device->rad_info.chip_class == GFX7 &&
3556 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
3557 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
3558
3559 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
3560 radeon_emit(cs, shader->config.rsrc1);
3561 radeon_emit(cs, rsrc2);
3562 }
3563
3564 static void
3565 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
3566 struct radeon_cmdbuf *cs,
3567 struct radv_pipeline *pipeline,
3568 struct radv_shader_variant *shader,
3569 const struct radv_ngg_state *ngg_state)
3570 {
3571 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3572 gl_shader_stage es_type =
3573 radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
3574 struct radv_shader_variant *es =
3575 es_type == MESA_SHADER_TESS_EVAL ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX];
3576
3577 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
3578 radeon_emit(cs, va >> 8);
3579 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3580 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3581 radeon_emit(cs, shader->config.rsrc1);
3582 radeon_emit(cs, shader->config.rsrc2);
3583
3584 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3585 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3586 clip_dist_mask = outinfo->clip_dist_mask;
3587 cull_dist_mask = outinfo->cull_dist_mask;
3588 total_mask = clip_dist_mask | cull_dist_mask;
3589 bool misc_vec_ena = outinfo->writes_pointsize ||
3590 outinfo->writes_layer ||
3591 outinfo->writes_viewport_index;
3592 bool es_enable_prim_id = outinfo->export_prim_id ||
3593 (es && es->info.info.uses_prim_id);
3594 bool break_wave_at_eoi = false;
3595 unsigned nparams;
3596
3597 if (es_type == MESA_SHADER_TESS_EVAL) {
3598 struct radv_shader_variant *gs =
3599 pipeline->shaders[MESA_SHADER_GEOMETRY];
3600
3601 if (es_enable_prim_id || (gs && gs->info.info.uses_prim_id))
3602 break_wave_at_eoi = true;
3603 }
3604
3605 nparams = MAX2(outinfo->param_exports, 1);
3606 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG,
3607 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
3608 S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0));
3609
3610 radeon_set_context_reg(ctx_cs, R_028708_SPI_SHADER_IDX_FORMAT,
3611 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP));
3612 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3613 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3614 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3615 V_02870C_SPI_SHADER_4COMP :
3616 V_02870C_SPI_SHADER_NONE) |
3617 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3618 V_02870C_SPI_SHADER_4COMP :
3619 V_02870C_SPI_SHADER_NONE) |
3620 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3621 V_02870C_SPI_SHADER_4COMP :
3622 V_02870C_SPI_SHADER_NONE));
3623
3624 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3625 S_028818_VTX_W0_FMT(1) |
3626 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3627 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3628 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3629 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3630 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3631 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3632 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3633 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3634 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3635 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3636 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3637 cull_dist_mask << 8 |
3638 clip_dist_mask);
3639
3640 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN,
3641 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
3642 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id));
3643
3644 bool vgt_reuse_off = pipeline->device->physical_device->rad_info.family == CHIP_NAVI10 &&
3645 pipeline->device->physical_device->rad_info.chip_external_rev == 0x1 &&
3646 es_type == MESA_SHADER_TESS_EVAL;
3647
3648 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
3649 S_028AB4_REUSE_OFF(vgt_reuse_off));
3650 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
3651 ngg_state->vgt_esgs_ring_itemsize);
3652
3653 /* NGG specific registers. */
3654 struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
3655 uint32_t gs_num_invocations = gs ? gs->info.gs.invocations : 1;
3656
3657 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
3658 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state->hw_max_esverts) |
3659 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state->max_gsprims) |
3660 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state->max_gsprims * gs_num_invocations));
3661 radeon_set_context_reg(ctx_cs, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
3662 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state->max_out_verts));
3663 radeon_set_context_reg(ctx_cs, R_028B4C_GE_NGG_SUBGRP_CNTL,
3664 S_028B4C_PRIM_AMP_FACTOR(ngg_state->prim_amp_factor) |
3665 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
3666 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
3667 S_028B90_CNT(gs_num_invocations) |
3668 S_028B90_ENABLE(gs_num_invocations > 1) |
3669 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state->max_vert_out_per_gs_instance));
3670
3671 /* User edge flags are set by the pos exports. If user edge flags are
3672 * not used, we must use hw-generated edge flags and pass them via
3673 * the prim export to prevent drawing lines on internal edges of
3674 * decomposed primitives (such as quads) with polygon mode = lines.
3675 *
3676 * TODO: We should combine hw-generated edge flags with user edge
3677 * flags in the shader.
3678 */
3679 radeon_set_context_reg(ctx_cs, R_028838_PA_CL_NGG_CNTL,
3680 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) &&
3681 !radv_pipeline_has_gs(pipeline)));
3682
3683 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL,
3684 S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |
3685 S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts) |
3686 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));
3687 }
3688
3689 static void
3690 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
3691 struct radv_pipeline *pipeline,
3692 struct radv_shader_variant *shader,
3693 const struct radv_tessellation_state *tess)
3694 {
3695 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3696
3697 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
3698 unsigned hs_rsrc2 = shader->config.rsrc2;
3699
3700 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3701 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(tess->lds_size);
3702 } else {
3703 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(tess->lds_size);
3704 }
3705
3706 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3707 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3708 radeon_emit(cs, va >> 8);
3709 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3710 } else {
3711 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
3712 radeon_emit(cs, va >> 8);
3713 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
3714 }
3715
3716 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
3717 radeon_emit(cs, shader->config.rsrc1);
3718 radeon_emit(cs, hs_rsrc2);
3719 } else {
3720 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
3721 radeon_emit(cs, va >> 8);
3722 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
3723 radeon_emit(cs, shader->config.rsrc1);
3724 radeon_emit(cs, shader->config.rsrc2);
3725 }
3726 }
3727
3728 static void
3729 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs,
3730 struct radeon_cmdbuf *cs,
3731 struct radv_pipeline *pipeline,
3732 const struct radv_tessellation_state *tess,
3733 const struct radv_ngg_state *ngg)
3734 {
3735 struct radv_shader_variant *vs;
3736
3737 /* Skip shaders merged into HS/GS */
3738 vs = pipeline->shaders[MESA_SHADER_VERTEX];
3739 if (!vs)
3740 return;
3741
3742 if (vs->info.vs.as_ls)
3743 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
3744 else if (vs->info.vs.as_es)
3745 radv_pipeline_generate_hw_es(cs, pipeline, vs);
3746 else if (vs->info.is_ngg)
3747 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, vs, ngg);
3748 else
3749 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, vs);
3750 }
3751
3752 static void
3753 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
3754 struct radeon_cmdbuf *cs,
3755 struct radv_pipeline *pipeline,
3756 const struct radv_tessellation_state *tess,
3757 const struct radv_ngg_state *ngg)
3758 {
3759 if (!radv_pipeline_has_tess(pipeline))
3760 return;
3761
3762 struct radv_shader_variant *tes, *tcs;
3763
3764 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
3765 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
3766
3767 if (tes) {
3768 if (tes->info.is_ngg) {
3769 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, tes, ngg);
3770 } else if (tes->info.tes.as_es)
3771 radv_pipeline_generate_hw_es(cs, pipeline, tes);
3772 else
3773 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes);
3774 }
3775
3776 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
3777
3778 radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
3779 tess->tf_param);
3780
3781 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7)
3782 radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, 2,
3783 tess->ls_hs_config);
3784 else
3785 radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
3786 tess->ls_hs_config);
3787 }
3788
3789 static void
3790 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs,
3791 struct radeon_cmdbuf *cs,
3792 struct radv_pipeline *pipeline,
3793 struct radv_shader_variant *gs,
3794 const struct radv_gs_state *gs_state)
3795 {
3796 unsigned gs_max_out_vertices;
3797 uint8_t *num_components;
3798 uint8_t max_stream;
3799 unsigned offset;
3800 uint64_t va;
3801
3802 gs_max_out_vertices = gs->info.gs.vertices_out;
3803 max_stream = gs->info.info.gs.max_stream;
3804 num_components = gs->info.info.gs.num_stream_output_components;
3805
3806 offset = num_components[0] * gs_max_out_vertices;
3807
3808 radeon_set_context_reg_seq(ctx_cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
3809 radeon_emit(ctx_cs, offset);
3810 if (max_stream >= 1)
3811 offset += num_components[1] * gs_max_out_vertices;
3812 radeon_emit(ctx_cs, offset);
3813 if (max_stream >= 2)
3814 offset += num_components[2] * gs_max_out_vertices;
3815 radeon_emit(ctx_cs, offset);
3816 if (max_stream >= 3)
3817 offset += num_components[3] * gs_max_out_vertices;
3818 radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
3819
3820 radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
3821 radeon_emit(ctx_cs, num_components[0]);
3822 radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0);
3823 radeon_emit(ctx_cs, (max_stream >= 2) ? num_components[2] : 0);
3824 radeon_emit(ctx_cs, (max_stream >= 3) ? num_components[3] : 0);
3825
3826 uint32_t gs_num_invocations = gs->info.gs.invocations;
3827 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
3828 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
3829 S_028B90_ENABLE(gs_num_invocations > 0));
3830
3831 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
3832 gs_state->vgt_esgs_ring_itemsize);
3833
3834 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
3835
3836 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
3837 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3838 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
3839 radeon_emit(cs, va >> 8);
3840 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3841 } else {
3842 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
3843 radeon_emit(cs, va >> 8);
3844 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
3845 }
3846
3847 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3848 radeon_emit(cs, gs->config.rsrc1);
3849 radeon_emit(cs, gs->config.rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
3850
3851 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
3852 radeon_set_context_reg(ctx_cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
3853 } else {
3854 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
3855 radeon_emit(cs, va >> 8);
3856 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
3857 radeon_emit(cs, gs->config.rsrc1);
3858 radeon_emit(cs, gs->config.rsrc2);
3859 }
3860
3861 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, pipeline->gs_copy_shader);
3862 }
3863
3864 static void
3865 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
3866 struct radeon_cmdbuf *cs,
3867 struct radv_pipeline *pipeline,
3868 const struct radv_gs_state *gs_state,
3869 const struct radv_ngg_state *ngg_state)
3870 {
3871 struct radv_shader_variant *gs;
3872
3873 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
3874 if (!gs)
3875 return;
3876
3877 if (gs->info.is_ngg)
3878 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs, ngg_state);
3879 else
3880 radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs, gs_state);
3881
3882 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT,
3883 gs->info.gs.vertices_out);
3884 }
3885
3886 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade, bool float16)
3887 {
3888 uint32_t ps_input_cntl;
3889 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3890 ps_input_cntl = S_028644_OFFSET(offset);
3891 if (flat_shade)
3892 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3893 if (float16) {
3894 ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
3895 S_028644_ATTR0_VALID(1);
3896 }
3897 } else {
3898 /* The input is a DEFAULT_VAL constant. */
3899 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3900 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3901 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3902 ps_input_cntl = S_028644_OFFSET(0x20) |
3903 S_028644_DEFAULT_VAL(offset);
3904 }
3905 return ps_input_cntl;
3906 }
3907
3908 static void
3909 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
3910 struct radv_pipeline *pipeline)
3911 {
3912 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3913 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3914 uint32_t ps_input_cntl[32];
3915
3916 unsigned ps_offset = 0;
3917
3918 if (ps->info.info.ps.prim_id_input) {
3919 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
3920 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
3921 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
3922 ++ps_offset;
3923 }
3924 }
3925
3926 if (ps->info.info.ps.layer_input ||
3927 ps->info.info.needs_multiview_view_index) {
3928 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
3929 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
3930 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
3931 else
3932 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false);
3933 ++ps_offset;
3934 }
3935
3936 if (ps->info.info.ps.has_pcoord) {
3937 unsigned val;
3938 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
3939 ps_input_cntl[ps_offset] = val;
3940 ps_offset++;
3941 }
3942
3943 if (ps->info.info.ps.num_input_clips_culls) {
3944 unsigned vs_offset;
3945
3946 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
3947 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
3948 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
3949 ++ps_offset;
3950 }
3951
3952 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
3953 if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
3954 ps->info.info.ps.num_input_clips_culls > 4) {
3955 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
3956 ++ps_offset;
3957 }
3958 }
3959
3960 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
3961 unsigned vs_offset;
3962 bool flat_shade;
3963 bool float16;
3964 if (!(ps->info.fs.input_mask & (1u << i)))
3965 continue;
3966
3967 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
3968 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
3969 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
3970 ++ps_offset;
3971 continue;
3972 }
3973
3974 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
3975 float16 = !!(ps->info.fs.float16_shaded_mask & (1u << ps_offset));
3976
3977 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, float16);
3978 ++ps_offset;
3979 }
3980
3981 if (ps_offset) {
3982 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
3983 for (unsigned i = 0; i < ps_offset; i++) {
3984 radeon_emit(ctx_cs, ps_input_cntl[i]);
3985 }
3986 }
3987 }
3988
3989 static uint32_t
3990 radv_compute_db_shader_control(const struct radv_device *device,
3991 const struct radv_pipeline *pipeline,
3992 const struct radv_shader_variant *ps)
3993 {
3994 unsigned z_order;
3995 if (ps->info.fs.early_fragment_test || !ps->info.info.ps.writes_memory)
3996 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
3997 else
3998 z_order = V_02880C_LATE_Z;
3999
4000 bool disable_rbplus = device->physical_device->has_rbplus &&
4001 !device->physical_device->rbplus_allowed;
4002
4003 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4004 * but this appears to break Project Cars (DXVK). See
4005 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4006 */
4007 bool mask_export_enable = ps->info.info.ps.writes_sample_mask;
4008
4009 return S_02880C_Z_EXPORT_ENABLE(ps->info.info.ps.writes_z) |
4010 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.info.ps.writes_stencil) |
4011 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
4012 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
4013 S_02880C_Z_ORDER(z_order) |
4014 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
4015 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.fs.post_depth_coverage) |
4016 S_02880C_EXEC_ON_HIER_FAIL(ps->info.info.ps.writes_memory) |
4017 S_02880C_EXEC_ON_NOOP(ps->info.info.ps.writes_memory) |
4018 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
4019 }
4020
4021 static void
4022 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs,
4023 struct radeon_cmdbuf *cs,
4024 struct radv_pipeline *pipeline)
4025 {
4026 struct radv_shader_variant *ps;
4027 uint64_t va;
4028 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
4029
4030 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4031 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
4032
4033 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
4034 radeon_emit(cs, va >> 8);
4035 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
4036 radeon_emit(cs, ps->config.rsrc1);
4037 radeon_emit(cs, ps->config.rsrc2);
4038
4039 radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL,
4040 radv_compute_db_shader_control(pipeline->device,
4041 pipeline, ps));
4042
4043 radeon_set_context_reg(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA,
4044 ps->config.spi_ps_input_ena);
4045
4046 radeon_set_context_reg(ctx_cs, R_0286D0_SPI_PS_INPUT_ADDR,
4047 ps->config.spi_ps_input_addr);
4048
4049 radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL,
4050 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
4051
4052 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
4053
4054 radeon_set_context_reg(ctx_cs, R_028710_SPI_SHADER_Z_FORMAT,
4055 ac_get_spi_shader_z_format(ps->info.info.ps.writes_z,
4056 ps->info.info.ps.writes_stencil,
4057 ps->info.info.ps.writes_sample_mask));
4058
4059 if (pipeline->device->dfsm_allowed) {
4060 /* optimise this? */
4061 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4062 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
4063 }
4064 }
4065
4066 static void
4067 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs,
4068 struct radv_pipeline *pipeline)
4069 {
4070 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4071 pipeline->device->physical_device->rad_info.chip_class >= GFX10)
4072 return;
4073
4074 unsigned vtx_reuse_depth = 30;
4075 if (radv_pipeline_has_tess(pipeline) &&
4076 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
4077 vtx_reuse_depth = 14;
4078 }
4079 radeon_set_context_reg(ctx_cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
4080 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
4081 }
4082
4083 static uint32_t
4084 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
4085 {
4086 uint32_t stages = 0;
4087 if (radv_pipeline_has_tess(pipeline)) {
4088 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
4089 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4090
4091 if (radv_pipeline_has_gs(pipeline))
4092 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
4093 S_028B54_GS_EN(1);
4094 else if (radv_pipeline_has_ngg(pipeline))
4095 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
4096 else
4097 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
4098 } else if (radv_pipeline_has_gs(pipeline)) {
4099 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
4100 S_028B54_GS_EN(1);
4101 } else if (radv_pipeline_has_ngg(pipeline)) {
4102 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
4103 }
4104
4105 if (radv_pipeline_has_ngg(pipeline)) {
4106 stages |= S_028B54_PRIMGEN_EN(1);
4107 } else if (radv_pipeline_has_gs(pipeline)) {
4108 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
4109 }
4110
4111 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
4112 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4113
4114 return stages;
4115 }
4116
4117 static uint32_t
4118 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
4119 {
4120 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
4121 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
4122
4123 if (!discard_rectangle_info)
4124 return 0xffff;
4125
4126 unsigned mask = 0;
4127
4128 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
4129 /* Interpret i as a bitmask, and then set the bit in the mask if
4130 * that combination of rectangles in which the pixel is contained
4131 * should pass the cliprect test. */
4132 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
4133
4134 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
4135 !relevant_subset)
4136 continue;
4137
4138 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
4139 relevant_subset)
4140 continue;
4141
4142 mask |= 1u << i;
4143 }
4144
4145 return mask;
4146 }
4147
4148 static void
4149 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs,
4150 struct radv_pipeline *pipeline,
4151 const struct radv_tessellation_state *tess,
4152 const struct radv_gs_state *gs_state)
4153 {
4154 bool break_wave_at_eoi = false;
4155 unsigned primgroup_size;
4156 unsigned vertgroup_size;
4157
4158 if (radv_pipeline_has_tess(pipeline)) {
4159 primgroup_size = tess->num_patches; /* must be a multiple of NUM_PATCHES */
4160 vertgroup_size = 0;
4161 } else if (radv_pipeline_has_gs(pipeline)) {
4162 unsigned vgt_gs_onchip_cntl = gs_state->vgt_gs_onchip_cntl;
4163 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
4164 vertgroup_size = G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl);
4165 } else {
4166 primgroup_size = 128; /* recommended without a GS and tess */
4167 vertgroup_size = 0;
4168 }
4169
4170 if (radv_pipeline_has_tess(pipeline)) {
4171 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id ||
4172 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.info.uses_prim_id)
4173 break_wave_at_eoi = true;
4174 }
4175
4176 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL,
4177 S_03096C_PRIM_GRP_SIZE(primgroup_size) |
4178 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
4179 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4180 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));
4181 }
4182
4183 static void
4184 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
4185 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4186 const struct radv_graphics_pipeline_create_info *extra,
4187 const struct radv_blend_state *blend,
4188 const struct radv_tessellation_state *tess,
4189 const struct radv_gs_state *gs,
4190 const struct radv_ngg_state *ngg,
4191 unsigned prim, unsigned gs_out)
4192 {
4193 struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs;
4194 struct radeon_cmdbuf *cs = &pipeline->cs;
4195
4196 cs->max_dw = 64;
4197 ctx_cs->max_dw = 256;
4198 cs->buf = malloc(4 * (cs->max_dw + ctx_cs->max_dw));
4199 ctx_cs->buf = cs->buf + cs->max_dw;
4200
4201 radv_pipeline_generate_depth_stencil_state(ctx_cs, pipeline, pCreateInfo, extra);
4202 radv_pipeline_generate_blend_state(ctx_cs, pipeline, blend);
4203 radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo);
4204 radv_pipeline_generate_multisample_state(ctx_cs, pipeline);
4205 radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline);
4206 radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline, tess, ngg);
4207 radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline, tess, ngg);
4208 radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline, gs, ngg);
4209 radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline);
4210 radv_pipeline_generate_ps_inputs(ctx_cs, pipeline);
4211 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline);
4212 radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo);
4213
4214 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && !radv_pipeline_has_ngg(pipeline))
4215 gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline, tess, gs);
4216
4217 radeon_set_context_reg(ctx_cs, R_0286E8_SPI_TMPRING_SIZE,
4218 S_0286E8_WAVES(pipeline->max_waves) |
4219 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
4220
4221 radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
4222
4223 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
4224 radeon_set_uconfig_reg_idx(pipeline->device->physical_device,
4225 cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
4226 } else {
4227 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
4228 }
4229 radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
4230
4231 radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
4232
4233 pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4);
4234
4235 assert(ctx_cs->cdw <= ctx_cs->max_dw);
4236 assert(cs->cdw <= cs->max_dw);
4237 }
4238
4239 static struct radv_ia_multi_vgt_param_helpers
4240 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
4241 const struct radv_tessellation_state *tess,
4242 uint32_t prim)
4243 {
4244 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
4245 const struct radv_device *device = pipeline->device;
4246
4247 if (radv_pipeline_has_tess(pipeline))
4248 ia_multi_vgt_param.primgroup_size = tess->num_patches;
4249 else if (radv_pipeline_has_gs(pipeline))
4250 ia_multi_vgt_param.primgroup_size = 64;
4251 else
4252 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
4253
4254 /* GS requirement. */
4255 ia_multi_vgt_param.partial_es_wave = false;
4256 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8)
4257 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
4258 ia_multi_vgt_param.partial_es_wave = true;
4259
4260 ia_multi_vgt_param.wd_switch_on_eop = false;
4261 if (device->physical_device->rad_info.chip_class >= GFX7) {
4262 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4263 * 4 shader engines. Set 1 to pass the assertion below.
4264 * The other cases are hardware requirements. */
4265 if (device->physical_device->rad_info.max_se < 4 ||
4266 prim == V_008958_DI_PT_POLYGON ||
4267 prim == V_008958_DI_PT_LINELOOP ||
4268 prim == V_008958_DI_PT_TRIFAN ||
4269 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
4270 (pipeline->graphics.prim_restart_enable &&
4271 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4272 (prim != V_008958_DI_PT_POINTLIST &&
4273 prim != V_008958_DI_PT_LINESTRIP))))
4274 ia_multi_vgt_param.wd_switch_on_eop = true;
4275 }
4276
4277 ia_multi_vgt_param.ia_switch_on_eoi = false;
4278 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input)
4279 ia_multi_vgt_param.ia_switch_on_eoi = true;
4280 if (radv_pipeline_has_gs(pipeline) &&
4281 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.info.uses_prim_id)
4282 ia_multi_vgt_param.ia_switch_on_eoi = true;
4283 if (radv_pipeline_has_tess(pipeline)) {
4284 /* SWITCH_ON_EOI must be set if PrimID is used. */
4285 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id ||
4286 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.info.uses_prim_id)
4287 ia_multi_vgt_param.ia_switch_on_eoi = true;
4288 }
4289
4290 ia_multi_vgt_param.partial_vs_wave = false;
4291 if (radv_pipeline_has_tess(pipeline)) {
4292 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4293 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
4294 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
4295 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
4296 radv_pipeline_has_gs(pipeline))
4297 ia_multi_vgt_param.partial_vs_wave = true;
4298 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4299 if (device->has_distributed_tess) {
4300 if (radv_pipeline_has_gs(pipeline)) {
4301 if (device->physical_device->rad_info.chip_class <= GFX8)
4302 ia_multi_vgt_param.partial_es_wave = true;
4303 } else {
4304 ia_multi_vgt_param.partial_vs_wave = true;
4305 }
4306 }
4307 }
4308
4309 /* Workaround for a VGT hang when strip primitive types are used with
4310 * primitive restart.
4311 */
4312 if (pipeline->graphics.prim_restart_enable &&
4313 (prim == V_008958_DI_PT_LINESTRIP ||
4314 prim == V_008958_DI_PT_TRISTRIP ||
4315 prim == V_008958_DI_PT_LINESTRIP_ADJ ||
4316 prim == V_008958_DI_PT_TRISTRIP_ADJ)) {
4317 ia_multi_vgt_param.partial_vs_wave = true;
4318 }
4319
4320 if (radv_pipeline_has_gs(pipeline)) {
4321 /* On these chips there is the possibility of a hang if the
4322 * pipeline uses a GS and partial_vs_wave is not set.
4323 *
4324 * This mostly does not hit 4-SE chips, as those typically set
4325 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4326 * with GS due to another workaround.
4327 *
4328 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4329 */
4330 if (device->physical_device->rad_info.family == CHIP_TONGA ||
4331 device->physical_device->rad_info.family == CHIP_FIJI ||
4332 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
4333 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
4334 device->physical_device->rad_info.family == CHIP_POLARIS12 ||
4335 device->physical_device->rad_info.family == CHIP_VEGAM) {
4336 ia_multi_vgt_param.partial_vs_wave = true;
4337 }
4338 }
4339
4340 ia_multi_vgt_param.base =
4341 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
4342 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4343 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == GFX8 ? 2 : 0) |
4344 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
4345 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
4346
4347 return ia_multi_vgt_param;
4348 }
4349
4350
4351 static void
4352 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
4353 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4354 {
4355 const VkPipelineVertexInputStateCreateInfo *vi_info =
4356 pCreateInfo->pVertexInputState;
4357 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
4358
4359 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
4360 const VkVertexInputAttributeDescription *desc =
4361 &vi_info->pVertexAttributeDescriptions[i];
4362 unsigned loc = desc->location;
4363 const struct vk_format_description *format_desc;
4364
4365 format_desc = vk_format_description(desc->format);
4366
4367 velems->format_size[loc] = format_desc->block.bits / 8;
4368 }
4369
4370 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
4371 const VkVertexInputBindingDescription *desc =
4372 &vi_info->pVertexBindingDescriptions[i];
4373
4374 pipeline->binding_stride[desc->binding] = desc->stride;
4375 pipeline->num_vertex_bindings =
4376 MAX2(pipeline->num_vertex_bindings, desc->binding + 1);
4377 }
4378 }
4379
4380 static struct radv_shader_variant *
4381 radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
4382 {
4383 int i;
4384
4385 for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) {
4386 struct radv_shader_variant *shader =
4387 radv_get_shader(pipeline, i);
4388
4389 if (shader && shader->info.info.so.num_outputs > 0)
4390 return shader;
4391 }
4392
4393 return NULL;
4394 }
4395
4396 static VkResult
4397 radv_pipeline_init(struct radv_pipeline *pipeline,
4398 struct radv_device *device,
4399 struct radv_pipeline_cache *cache,
4400 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4401 const struct radv_graphics_pipeline_create_info *extra)
4402 {
4403 VkResult result;
4404 bool has_view_index = false;
4405
4406 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
4407 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
4408 if (subpass->view_mask)
4409 has_view_index = true;
4410
4411 pipeline->device = device;
4412 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
4413 assert(pipeline->layout);
4414
4415 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
4416
4417 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
4418 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
4419 radv_init_feedback(creation_feedback);
4420
4421 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
4422
4423 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
4424 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
4425 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
4426 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
4427 pStages[stage] = &pCreateInfo->pStages[i];
4428 if(creation_feedback)
4429 stage_feedbacks[stage] = &creation_feedback->pPipelineStageCreationFeedbacks[i];
4430 }
4431
4432 struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index);
4433 radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks);
4434
4435 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
4436 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
4437 uint32_t gs_out;
4438 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
4439
4440 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
4441
4442 if (radv_pipeline_has_gs(pipeline)) {
4443 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
4444 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4445 } else if (radv_pipeline_has_tess(pipeline)) {
4446 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode)
4447 gs_out = V_028A6C_OUTPRIM_TYPE_POINTLIST;
4448 else
4449 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mode);
4450 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4451 } else {
4452 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
4453 }
4454 if (extra && extra->use_rectlist) {
4455 prim = V_008958_DI_PT_RECTLIST;
4456 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4457 pipeline->graphics.can_use_guardband = true;
4458 if (radv_pipeline_has_ngg(pipeline))
4459 gs_out = V_028A6C_VGT_OUT_RECT_V0;
4460 }
4461 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
4462 /* prim vertex count will need TESS changes */
4463 pipeline->graphics.prim_vertex_count = prim_size_table[prim];
4464
4465 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
4466
4467 /* Ensure that some export memory is always allocated, for two reasons:
4468 *
4469 * 1) Correctness: The hardware ignores the EXEC mask if no export
4470 * memory is allocated, so KILL and alpha test do not work correctly
4471 * without this.
4472 * 2) Performance: Every shader needs at least a NULL export, even when
4473 * it writes no color/depth output. The NULL export instruction
4474 * stalls without this setting.
4475 *
4476 * Don't add this to CB_SHADER_MASK.
4477 *
4478 * GFX10 supports pixel shaders without exports by setting both the
4479 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
4480 * instructions if any are present.
4481 */
4482 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4483 if ((pipeline->device->physical_device->rad_info.chip_class <= GFX9 ||
4484 ps->info.fs.can_discard) &&
4485 !blend.spi_shader_col_format) {
4486 if (!ps->info.info.ps.writes_z &&
4487 !ps->info.info.ps.writes_stencil &&
4488 !ps->info.info.ps.writes_sample_mask)
4489 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
4490 }
4491
4492 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
4493 if (pipeline->shaders[i]) {
4494 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
4495 }
4496 }
4497
4498 struct radv_ngg_state ngg = {0};
4499 struct radv_gs_state gs = {0};
4500
4501 if (radv_pipeline_has_ngg(pipeline)) {
4502 ngg = calculate_ngg_info(pCreateInfo, pipeline);
4503 } else if (radv_pipeline_has_gs(pipeline)) {
4504 gs = calculate_gs_info(pCreateInfo, pipeline);
4505 calculate_gs_ring_sizes(pipeline, &gs);
4506 }
4507
4508 struct radv_tessellation_state tess = {0};
4509 if (radv_pipeline_has_tess(pipeline)) {
4510 if (prim == V_008958_DI_PT_PATCH) {
4511 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
4512 pipeline->graphics.prim_vertex_count.incr = 1;
4513 }
4514 tess = calculate_tess_state(pipeline, pCreateInfo);
4515 }
4516
4517 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
4518
4519 radv_compute_vertex_input_state(pipeline, pCreateInfo);
4520
4521 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
4522 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
4523
4524 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
4525 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
4526 if (loc->sgpr_idx != -1) {
4527 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
4528 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
4529 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id)
4530 pipeline->graphics.vtx_emit_num = 3;
4531 else
4532 pipeline->graphics.vtx_emit_num = 2;
4533 }
4534
4535 /* Find the last vertex shader stage that eventually uses streamout. */
4536 pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
4537
4538 result = radv_pipeline_scratch_init(device, pipeline);
4539 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, &gs, &ngg, prim, gs_out);
4540
4541 return result;
4542 }
4543
4544 VkResult
4545 radv_graphics_pipeline_create(
4546 VkDevice _device,
4547 VkPipelineCache _cache,
4548 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4549 const struct radv_graphics_pipeline_create_info *extra,
4550 const VkAllocationCallbacks *pAllocator,
4551 VkPipeline *pPipeline)
4552 {
4553 RADV_FROM_HANDLE(radv_device, device, _device);
4554 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
4555 struct radv_pipeline *pipeline;
4556 VkResult result;
4557
4558 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
4559 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4560 if (pipeline == NULL)
4561 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4562
4563 result = radv_pipeline_init(pipeline, device, cache,
4564 pCreateInfo, extra);
4565 if (result != VK_SUCCESS) {
4566 radv_pipeline_destroy(device, pipeline, pAllocator);
4567 return result;
4568 }
4569
4570 *pPipeline = radv_pipeline_to_handle(pipeline);
4571
4572 return VK_SUCCESS;
4573 }
4574
4575 VkResult radv_CreateGraphicsPipelines(
4576 VkDevice _device,
4577 VkPipelineCache pipelineCache,
4578 uint32_t count,
4579 const VkGraphicsPipelineCreateInfo* pCreateInfos,
4580 const VkAllocationCallbacks* pAllocator,
4581 VkPipeline* pPipelines)
4582 {
4583 VkResult result = VK_SUCCESS;
4584 unsigned i = 0;
4585
4586 for (; i < count; i++) {
4587 VkResult r;
4588 r = radv_graphics_pipeline_create(_device,
4589 pipelineCache,
4590 &pCreateInfos[i],
4591 NULL, pAllocator, &pPipelines[i]);
4592 if (r != VK_SUCCESS) {
4593 result = r;
4594 pPipelines[i] = VK_NULL_HANDLE;
4595 }
4596 }
4597
4598 return result;
4599 }
4600
4601
4602 static void
4603 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
4604 {
4605 struct radv_shader_variant *compute_shader;
4606 struct radv_device *device = pipeline->device;
4607 unsigned threads_per_threadgroup;
4608 unsigned threadgroups_per_cu = 1;
4609 unsigned waves_per_threadgroup;
4610 unsigned max_waves_per_sh = 0;
4611 uint64_t va;
4612
4613 pipeline->cs.buf = malloc(20 * 4);
4614 pipeline->cs.max_dw = 20;
4615
4616 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4617 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
4618
4619 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
4620 radeon_emit(&pipeline->cs, va >> 8);
4621 radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
4622
4623 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
4624 radeon_emit(&pipeline->cs, compute_shader->config.rsrc1);
4625 radeon_emit(&pipeline->cs, compute_shader->config.rsrc2);
4626
4627 radeon_set_sh_reg(&pipeline->cs, R_00B860_COMPUTE_TMPRING_SIZE,
4628 S_00B860_WAVES(pipeline->max_waves) |
4629 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
4630
4631 /* Calculate best compute resource limits. */
4632 threads_per_threadgroup = compute_shader->info.cs.block_size[0] *
4633 compute_shader->info.cs.block_size[1] *
4634 compute_shader->info.cs.block_size[2];
4635 waves_per_threadgroup = DIV_ROUND_UP(threads_per_threadgroup,
4636 device->physical_device->cs_wave_size);
4637
4638 if (device->physical_device->rad_info.chip_class >= GFX10 &&
4639 waves_per_threadgroup == 1)
4640 threadgroups_per_cu = 2;
4641
4642 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
4643 ac_get_compute_resource_limits(&device->physical_device->rad_info,
4644 waves_per_threadgroup,
4645 max_waves_per_sh,
4646 threadgroups_per_cu));
4647
4648 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4649 radeon_emit(&pipeline->cs,
4650 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
4651 radeon_emit(&pipeline->cs,
4652 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
4653 radeon_emit(&pipeline->cs,
4654 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
4655
4656 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
4657 }
4658
4659 static VkResult radv_compute_pipeline_create(
4660 VkDevice _device,
4661 VkPipelineCache _cache,
4662 const VkComputePipelineCreateInfo* pCreateInfo,
4663 const VkAllocationCallbacks* pAllocator,
4664 VkPipeline* pPipeline)
4665 {
4666 RADV_FROM_HANDLE(radv_device, device, _device);
4667 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
4668 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
4669 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
4670 struct radv_pipeline *pipeline;
4671 VkResult result;
4672
4673 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
4674 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4675 if (pipeline == NULL)
4676 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4677
4678 pipeline->device = device;
4679 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
4680 assert(pipeline->layout);
4681
4682 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
4683 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
4684 radv_init_feedback(creation_feedback);
4685
4686 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
4687 if (creation_feedback)
4688 stage_feedbacks[MESA_SHADER_COMPUTE] = &creation_feedback->pPipelineStageCreationFeedbacks[0];
4689
4690 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
4691 radv_create_shaders(pipeline, device, cache, &(struct radv_pipeline_key) {0}, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks);
4692
4693 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
4694 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
4695 result = radv_pipeline_scratch_init(device, pipeline);
4696 if (result != VK_SUCCESS) {
4697 radv_pipeline_destroy(device, pipeline, pAllocator);
4698 return result;
4699 }
4700
4701 radv_compute_generate_pm4(pipeline);
4702
4703 *pPipeline = radv_pipeline_to_handle(pipeline);
4704
4705 return VK_SUCCESS;
4706 }
4707
4708 VkResult radv_CreateComputePipelines(
4709 VkDevice _device,
4710 VkPipelineCache pipelineCache,
4711 uint32_t count,
4712 const VkComputePipelineCreateInfo* pCreateInfos,
4713 const VkAllocationCallbacks* pAllocator,
4714 VkPipeline* pPipelines)
4715 {
4716 VkResult result = VK_SUCCESS;
4717
4718 unsigned i = 0;
4719 for (; i < count; i++) {
4720 VkResult r;
4721 r = radv_compute_pipeline_create(_device, pipelineCache,
4722 &pCreateInfos[i],
4723 pAllocator, &pPipelines[i]);
4724 if (r != VK_SUCCESS) {
4725 result = r;
4726 pPipelines[i] = VK_NULL_HANDLE;
4727 }
4728 }
4729
4730 return result;
4731 }