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radv/gfx10: emit VGT_VERTEX_REUSE_BLOCK_CNTL during gfx initialization
[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for AMD GCN */
29
30 #include "radv_private.h"
31 #include "radv_shader.h"
32 #include "radv_cs.h"
33 #include "sid.h"
34 #include "radv_util.h"
35 #include "main/macros.h"
36
37 static void
38 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
39 struct radeon_cmdbuf *cs,
40 unsigned raster_config,
41 unsigned raster_config_1)
42 {
43 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
44 unsigned raster_config_se[4];
45 unsigned se;
46
47 ac_get_harvested_configs(&physical_device->rad_info,
48 raster_config,
49 &raster_config_1,
50 raster_config_se);
51
52 for (se = 0; se < num_se; se++) {
53 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
54 if (physical_device->rad_info.chip_class < GFX7)
55 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
56 S_00802C_SE_INDEX(se) |
57 S_00802C_SH_BROADCAST_WRITES(1) |
58 S_00802C_INSTANCE_BROADCAST_WRITES(1));
59 else
60 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
61 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
62 S_030800_INSTANCE_BROADCAST_WRITES(1));
63 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
64 }
65
66 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
67 if (physical_device->rad_info.chip_class < GFX7)
68 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
69 S_00802C_SE_BROADCAST_WRITES(1) |
70 S_00802C_SH_BROADCAST_WRITES(1) |
71 S_00802C_INSTANCE_BROADCAST_WRITES(1));
72 else
73 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
74 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
75 S_030800_INSTANCE_BROADCAST_WRITES(1));
76
77 if (physical_device->rad_info.chip_class >= GFX7)
78 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
79 }
80
81 void
82 si_emit_compute(struct radv_physical_device *physical_device,
83 struct radeon_cmdbuf *cs)
84 {
85 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
86 radeon_emit(cs, 0);
87 radeon_emit(cs, 0);
88 radeon_emit(cs, 0);
89
90 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
91 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1,
92 * renamed COMPUTE_DESTINATION_EN_SEn on gfx10. */
93 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
94 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
95
96 if (physical_device->rad_info.chip_class >= GFX7) {
97 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
98 radeon_set_sh_reg_seq(cs,
99 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
100 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
101 S_00B858_SH1_CU_EN(0xffff));
102 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
103 S_00B858_SH1_CU_EN(0xffff));
104 }
105
106 if (physical_device->rad_info.chip_class >= GFX10)
107 radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0);
108
109 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
110 * and is now per pipe, so it should be handled in the
111 * kernel if we want to use something other than the default value,
112 * which is now 0x22f.
113 */
114 if (physical_device->rad_info.chip_class <= GFX6) {
115 /* XXX: This should be:
116 * (number of compute units) * 4 * (waves per simd) - 1 */
117
118 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
119 0x190 /* Default value */);
120 }
121 }
122
123 /* 12.4 fixed-point */
124 static unsigned radv_pack_float_12p4(float x)
125 {
126 return x <= 0 ? 0 :
127 x >= 4096 ? 0xffff : x * 16;
128 }
129
130 static void
131 si_set_raster_config(struct radv_physical_device *physical_device,
132 struct radeon_cmdbuf *cs)
133 {
134 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
135 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
136 unsigned raster_config, raster_config_1;
137
138 ac_get_raster_config(&physical_device->rad_info,
139 &raster_config,
140 &raster_config_1, NULL);
141
142 /* Always use the default config when all backends are enabled
143 * (or when we failed to determine the enabled backends).
144 */
145 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
146 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
147 raster_config);
148 if (physical_device->rad_info.chip_class >= GFX7)
149 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
150 raster_config_1);
151 } else {
152 si_write_harvested_raster_configs(physical_device, cs,
153 raster_config,
154 raster_config_1);
155 }
156 }
157
158 void
159 si_emit_graphics(struct radv_physical_device *physical_device,
160 struct radeon_cmdbuf *cs)
161 {
162 int i;
163
164 /* Only GFX6 can disable CLEAR_STATE for now. */
165 assert(physical_device->has_clear_state ||
166 physical_device->rad_info.chip_class == GFX6);
167
168 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
169 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
170 radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
171
172 if (physical_device->has_clear_state) {
173 radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));
174 radeon_emit(cs, 0);
175 }
176
177 if (physical_device->rad_info.chip_class <= GFX8)
178 si_set_raster_config(physical_device, cs);
179
180 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
181 if (!physical_device->has_clear_state)
182 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
183
184 /* FIXME calculate these values somehow ??? */
185 if (physical_device->rad_info.chip_class <= GFX8) {
186 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
187 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
188 }
189
190 if (!physical_device->has_clear_state) {
191 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
192 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
193 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
194 }
195
196 radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
197 if (!physical_device->has_clear_state)
198 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
199 if (physical_device->rad_info.chip_class < GFX7)
200 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
201 S_008A14_CLIP_VTX_REORDER_ENA(1));
202
203 if (!physical_device->has_clear_state)
204 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
205
206 /* CLEAR_STATE doesn't clear these correctly on certain generations.
207 * I don't know why. Deduced by trial and error.
208 */
209 if (physical_device->rad_info.chip_class <= GFX7) {
210 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
211 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL,
212 S_028204_WINDOW_OFFSET_DISABLE(1));
213 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL,
214 S_028240_WINDOW_OFFSET_DISABLE(1));
215 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
216 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
217 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
218 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
219 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
220 }
221
222 if (!physical_device->has_clear_state) {
223 for (i = 0; i < 16; i++) {
224 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
225 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
226 }
227 }
228
229 if (!physical_device->has_clear_state) {
230 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
231 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
232 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on GFX6 */
233 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
234 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
235 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
236 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
237 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
238 }
239
240 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
241 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
242 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
243
244 if (physical_device->rad_info.chip_class >= GFX10) {
245 radeon_set_uconfig_reg(cs, R_030964_GE_MAX_VTX_INDX, ~0);
246 radeon_set_uconfig_reg(cs, R_030924_GE_MIN_VTX_INDX, 0);
247 radeon_set_uconfig_reg(cs, R_030928_GE_INDX_OFFSET, 0);
248 } else if (physical_device->rad_info.chip_class >= GFX9) {
249 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
250 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
251 radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
252 } else {
253 /* These registers, when written, also overwrite the
254 * CLEAR_STATE context, so we can't rely on CLEAR_STATE setting
255 * them. It would be an issue if there was another UMD
256 * changing them.
257 */
258 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
259 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
260 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
261 }
262
263 if (physical_device->rad_info.chip_class >= GFX7) {
264 if (physical_device->rad_info.chip_class >= GFX10) {
265 /* Logical CUs 16 - 31 */
266 radeon_set_sh_reg(cs, R_00B404_SPI_SHADER_PGM_RSRC4_HS,
267 S_00B404_CU_EN(0xffff));
268 radeon_set_sh_reg(cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
269 S_00B204_CU_EN(0xffff) |
270 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0));
271 radeon_set_sh_reg(cs, R_00B104_SPI_SHADER_PGM_RSRC4_VS,
272 S_00B104_CU_EN(0xffff));
273 radeon_set_sh_reg(cs, R_00B004_SPI_SHADER_PGM_RSRC4_PS,
274 S_00B004_CU_EN(0xffff));
275 }
276
277 if (physical_device->rad_info.chip_class >= GFX9) {
278 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
279 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
280 } else {
281 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
282 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
283 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
284 S_00B41C_WAVE_LIMIT(0x3F));
285 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
286 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
287 /* If this is 0, Bonaire can hang even if GS isn't being used.
288 * Other chips are unaffected. These are suboptimal values,
289 * but we don't use on-chip GS.
290 */
291 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
292 S_028A44_ES_VERTS_PER_SUBGRP(64) |
293 S_028A44_GS_PRIMS_PER_SUBGRP(4));
294 }
295 radeon_set_sh_reg(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
296 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
297
298 if (physical_device->rad_info.num_good_cu_per_sh <= 4) {
299 /* Too few available compute units per SH. Disallowing
300 * VS to run on CU0 could hurt us more than late VS
301 * allocation would help.
302 *
303 * LATE_ALLOC_VS = 2 is the highest safe number.
304 */
305 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
306 S_00B118_CU_EN(0xffff) | S_00B118_WAVE_LIMIT(0x3F) );
307 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
308 } else {
309 /* Set LATE_ALLOC_VS == 31. It should be less than
310 * the number of scratch waves. Limitations:
311 * - VS can't execute on CU0.
312 * - If HS writes outputs to LDS, LS can't execute on CU0.
313 */
314 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
315 S_00B118_CU_EN(0xfffe) | S_00B118_WAVE_LIMIT(0x3F));
316 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
317 }
318
319 radeon_set_sh_reg(cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
320 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
321 }
322
323 if (physical_device->rad_info.chip_class >= GFX10) {
324 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
325 radeon_set_context_reg(cs, R_02835C_PA_SC_TILE_STEERING_OVERRIDE,
326 physical_device->rad_info.pa_sc_tile_steering_override);
327 radeon_set_context_reg(cs, R_02807C_DB_RMI_L2_CACHE_CONTROL,
328 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
329 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
330 S_02807C_HTILE_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
331 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
332 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD) |
333 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD) |
334 S_02807C_HTILE_RD_POLICY(V_02807C_CACHE_NOA_RD));
335
336 radeon_set_context_reg(cs, R_028410_CB_RMI_GL2_CACHE_CONTROL,
337 S_028410_CMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
338 S_028410_FMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
339 S_028410_DCC_WR_POLICY(V_028410_CACHE_STREAM_WR) |
340 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR) |
341 S_028410_CMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
342 S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
343 S_028410_DCC_RD_POLICY(V_028410_CACHE_NOA_RD) |
344 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD));
345 }
346
347 if (physical_device->rad_info.chip_class >= GFX8) {
348 uint32_t vgt_tess_distribution;
349
350 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
351 S_028B50_ACCUM_TRI(11) |
352 S_028B50_ACCUM_QUAD(11) |
353 S_028B50_DONUT_SPLIT(16);
354
355 if (physical_device->rad_info.family == CHIP_FIJI ||
356 physical_device->rad_info.family >= CHIP_POLARIS10)
357 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
358
359 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
360 vgt_tess_distribution);
361 } else if (!physical_device->has_clear_state) {
362 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
363 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
364 }
365
366 if (physical_device->rad_info.chip_class >= GFX9) {
367 unsigned num_se = physical_device->rad_info.max_se;
368 unsigned pc_lines = 0;
369 unsigned max_alloc_count = 0;
370
371 switch (physical_device->rad_info.family) {
372 case CHIP_VEGA10:
373 case CHIP_VEGA12:
374 case CHIP_VEGA20:
375 pc_lines = 4096;
376 break;
377 case CHIP_RAVEN:
378 case CHIP_RAVEN2:
379 case CHIP_NAVI10:
380 case CHIP_NAVI12:
381 pc_lines = 1024;
382 break;
383 case CHIP_NAVI14:
384 pc_lines = 512;
385 break;
386 default:
387 assert(0);
388 }
389
390 if (physical_device->rad_info.chip_class >= GFX10) {
391 max_alloc_count = pc_lines / 3;
392 } else {
393 max_alloc_count = MIN2(128, pc_lines / (4 * num_se));
394 }
395
396 radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
397 S_028C48_MAX_ALLOC_COUNT(max_alloc_count) |
398 S_028C48_MAX_PRIM_PER_BATCH(1023));
399 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
400 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
401 radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
402 }
403
404 unsigned tmp = (unsigned)(1.0 * 8.0);
405 radeon_set_context_reg_seq(cs, R_028A00_PA_SU_POINT_SIZE, 1);
406 radeon_emit(cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
407 radeon_set_context_reg_seq(cs, R_028A04_PA_SU_POINT_MINMAX, 1);
408 radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
409 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2)));
410
411 if (!physical_device->has_clear_state) {
412 radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL,
413 S_028004_ZPASS_INCREMENT_DISABLE(1));
414 }
415
416 /* Enable the Polaris small primitive filter control.
417 * XXX: There is possibly an issue when MSAA is off (see RadeonSI
418 * has_msaa_sample_loc_bug). But this doesn't seem to regress anything,
419 * and AMDVLK doesn't have a workaround as well.
420 */
421 if (physical_device->rad_info.family >= CHIP_POLARIS10) {
422 unsigned small_prim_filter_cntl =
423 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
424 /* Workaround for a hw line bug. */
425 S_028830_LINE_FILTER_DISABLE(physical_device->rad_info.family <= CHIP_POLARIS12);
426
427 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
428 small_prim_filter_cntl);
429 }
430
431 si_emit_compute(physical_device, cs);
432 }
433
434 void
435 cik_create_gfx_config(struct radv_device *device)
436 {
437 struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, RING_GFX);
438 if (!cs)
439 return;
440
441 si_emit_graphics(device->physical_device, cs);
442
443 while (cs->cdw & 7) {
444 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
445 radeon_emit(cs, 0x80000000);
446 else
447 radeon_emit(cs, 0xffff1000);
448 }
449
450 device->gfx_init = device->ws->buffer_create(device->ws,
451 cs->cdw * 4, 4096,
452 RADEON_DOMAIN_GTT,
453 RADEON_FLAG_CPU_ACCESS|
454 RADEON_FLAG_NO_INTERPROCESS_SHARING |
455 RADEON_FLAG_READ_ONLY,
456 RADV_BO_PRIORITY_CS);
457 if (!device->gfx_init)
458 goto fail;
459
460 void *map = device->ws->buffer_map(device->gfx_init);
461 if (!map) {
462 device->ws->buffer_destroy(device->gfx_init);
463 device->gfx_init = NULL;
464 goto fail;
465 }
466 memcpy(map, cs->buf, cs->cdw * 4);
467
468 device->ws->buffer_unmap(device->gfx_init);
469 device->gfx_init_size_dw = cs->cdw;
470 fail:
471 device->ws->cs_destroy(cs);
472 }
473
474 static void
475 get_viewport_xform(const VkViewport *viewport,
476 float scale[3], float translate[3])
477 {
478 float x = viewport->x;
479 float y = viewport->y;
480 float half_width = 0.5f * viewport->width;
481 float half_height = 0.5f * viewport->height;
482 double n = viewport->minDepth;
483 double f = viewport->maxDepth;
484
485 scale[0] = half_width;
486 translate[0] = half_width + x;
487 scale[1] = half_height;
488 translate[1] = half_height + y;
489
490 scale[2] = (f - n);
491 translate[2] = n;
492 }
493
494 void
495 si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
496 int count, const VkViewport *viewports)
497 {
498 int i;
499
500 assert(count);
501 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
502 first_vp * 4 * 6, count * 6);
503
504 for (i = 0; i < count; i++) {
505 float scale[3], translate[3];
506
507
508 get_viewport_xform(&viewports[i], scale, translate);
509 radeon_emit(cs, fui(scale[0]));
510 radeon_emit(cs, fui(translate[0]));
511 radeon_emit(cs, fui(scale[1]));
512 radeon_emit(cs, fui(translate[1]));
513 radeon_emit(cs, fui(scale[2]));
514 radeon_emit(cs, fui(translate[2]));
515 }
516
517 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
518 first_vp * 4 * 2, count * 2);
519 for (i = 0; i < count; i++) {
520 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
521 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
522 radeon_emit(cs, fui(zmin));
523 radeon_emit(cs, fui(zmax));
524 }
525 }
526
527 static VkRect2D si_scissor_from_viewport(const VkViewport *viewport)
528 {
529 float scale[3], translate[3];
530 VkRect2D rect;
531
532 get_viewport_xform(viewport, scale, translate);
533
534 rect.offset.x = translate[0] - fabs(scale[0]);
535 rect.offset.y = translate[1] - fabs(scale[1]);
536 rect.extent.width = ceilf(translate[0] + fabs(scale[0])) - rect.offset.x;
537 rect.extent.height = ceilf(translate[1] + fabs(scale[1])) - rect.offset.y;
538
539 return rect;
540 }
541
542 static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) {
543 VkRect2D ret;
544 ret.offset.x = MAX2(a->offset.x, b->offset.x);
545 ret.offset.y = MAX2(a->offset.y, b->offset.y);
546 ret.extent.width = MIN2(a->offset.x + a->extent.width,
547 b->offset.x + b->extent.width) - ret.offset.x;
548 ret.extent.height = MIN2(a->offset.y + a->extent.height,
549 b->offset.y + b->extent.height) - ret.offset.y;
550 return ret;
551 }
552
553 void
554 si_write_scissors(struct radeon_cmdbuf *cs, int first,
555 int count, const VkRect2D *scissors,
556 const VkViewport *viewports, bool can_use_guardband)
557 {
558 int i;
559 float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY;
560 const float max_range = 32767.0f;
561 if (!count)
562 return;
563
564 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
565 for (i = 0; i < count; i++) {
566 VkRect2D viewport_scissor = si_scissor_from_viewport(viewports + i);
567 VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
568
569 get_viewport_xform(viewports + i, scale, translate);
570 scale[0] = fabsf(scale[0]);
571 scale[1] = fabsf(scale[1]);
572
573 if (scale[0] < 0.5)
574 scale[0] = 0.5;
575 if (scale[1] < 0.5)
576 scale[1] = 0.5;
577
578 guardband_x = MIN2(guardband_x, (max_range - fabsf(translate[0])) / scale[0]);
579 guardband_y = MIN2(guardband_y, (max_range - fabsf(translate[1])) / scale[1]);
580
581 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
582 S_028250_TL_Y(scissor.offset.y) |
583 S_028250_WINDOW_OFFSET_DISABLE(1));
584 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
585 S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
586 }
587 if (!can_use_guardband) {
588 guardband_x = 1.0;
589 guardband_y = 1.0;
590 }
591
592 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
593 radeon_emit(cs, fui(guardband_y));
594 radeon_emit(cs, fui(1.0));
595 radeon_emit(cs, fui(guardband_x));
596 radeon_emit(cs, fui(1.0));
597 }
598
599 static inline unsigned
600 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
601 {
602 if (num == 0)
603 return 0;
604
605 if (info->incr == 0)
606 return 0;
607
608 if (num < info->min)
609 return 0;
610
611 return 1 + ((num - info->min) / info->incr);
612 }
613
614 uint32_t
615 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
616 bool instanced_draw, bool indirect_draw,
617 bool count_from_stream_output,
618 uint32_t draw_vertex_count)
619 {
620 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
621 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
622 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
623 const unsigned max_primgroup_in_wave = 2;
624 /* SWITCH_ON_EOP(0) is always preferable. */
625 bool wd_switch_on_eop = false;
626 bool ia_switch_on_eop = false;
627 bool ia_switch_on_eoi = false;
628 bool partial_vs_wave = false;
629 bool partial_es_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_es_wave;
630 bool multi_instances_smaller_than_primgroup;
631
632 multi_instances_smaller_than_primgroup = indirect_draw;
633 if (!multi_instances_smaller_than_primgroup && instanced_draw) {
634 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
635 if (num_prims < cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.primgroup_size)
636 multi_instances_smaller_than_primgroup = true;
637 }
638
639 ia_switch_on_eoi = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.ia_switch_on_eoi;
640 partial_vs_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_vs_wave;
641
642 if (chip_class >= GFX7) {
643 wd_switch_on_eop = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.wd_switch_on_eop;
644
645 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
646 * We don't know that for indirect drawing, so treat it as
647 * always problematic. */
648 if (family == CHIP_HAWAII &&
649 (instanced_draw || indirect_draw))
650 wd_switch_on_eop = true;
651
652 /* Performance recommendation for 4 SE Gfx7-8 parts if
653 * instances are smaller than a primgroup.
654 * Assume indirect draws always use small instances.
655 * This is needed for good VS wave utilization.
656 */
657 if (chip_class <= GFX8 &&
658 info->max_se == 4 &&
659 multi_instances_smaller_than_primgroup)
660 wd_switch_on_eop = true;
661
662 /* Required on GFX7 and later. */
663 if (info->max_se > 2 && !wd_switch_on_eop)
664 ia_switch_on_eoi = true;
665
666 /* Required by Hawaii and, for some special cases, by GFX8. */
667 if (ia_switch_on_eoi &&
668 (family == CHIP_HAWAII ||
669 (chip_class == GFX8 &&
670 /* max primgroup in wave is always 2 - leave this for documentation */
671 (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
672 partial_vs_wave = true;
673
674 /* Instancing bug on Bonaire. */
675 if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
676 (instanced_draw || indirect_draw))
677 partial_vs_wave = true;
678
679 /* Hardware requirement when drawing primitives from a stream
680 * output buffer.
681 */
682 if (count_from_stream_output)
683 wd_switch_on_eop = true;
684
685 /* If the WD switch is false, the IA switch must be false too. */
686 assert(wd_switch_on_eop || !ia_switch_on_eop);
687 }
688 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
689 if (chip_class <= GFX8 && ia_switch_on_eoi)
690 partial_es_wave = true;
691
692 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
693 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
694 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
695 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
696 */
697 if (family == CHIP_HAWAII && ia_switch_on_eoi) {
698 bool set_vgt_flush = indirect_draw;
699 if (!set_vgt_flush && instanced_draw) {
700 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
701 if (num_prims <= 1)
702 set_vgt_flush = true;
703 }
704 if (set_vgt_flush)
705 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
706 }
707 }
708
709 return cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.base |
710 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
711 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
712 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
713 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
714 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= GFX7 ? wd_switch_on_eop : 0);
715
716 }
717
718 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
719 enum chip_class chip_class,
720 bool is_mec,
721 unsigned event, unsigned event_flags,
722 unsigned data_sel,
723 uint64_t va,
724 uint32_t new_fence,
725 uint64_t gfx9_eop_bug_va)
726 {
727 unsigned op = EVENT_TYPE(event) |
728 EVENT_INDEX(5) |
729 event_flags;
730 unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
731 unsigned sel = EOP_DATA_SEL(data_sel);
732
733 /* Wait for write confirmation before writing data, but don't send
734 * an interrupt. */
735 if (data_sel != EOP_DATA_SEL_DISCARD)
736 sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM);
737
738 if (chip_class >= GFX9 || is_gfx8_mec) {
739 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
740 * counters) must immediately precede every timestamp event to
741 * prevent a GPU hang on GFX9.
742 */
743 if (chip_class == GFX9 && !is_mec) {
744 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
745 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
746 radeon_emit(cs, gfx9_eop_bug_va);
747 radeon_emit(cs, gfx9_eop_bug_va >> 32);
748 }
749
750 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, false));
751 radeon_emit(cs, op);
752 radeon_emit(cs, sel);
753 radeon_emit(cs, va); /* address lo */
754 radeon_emit(cs, va >> 32); /* address hi */
755 radeon_emit(cs, new_fence); /* immediate data lo */
756 radeon_emit(cs, 0); /* immediate data hi */
757 if (!is_gfx8_mec)
758 radeon_emit(cs, 0); /* unused */
759 } else {
760 if (chip_class == GFX7 ||
761 chip_class == GFX8) {
762 /* Two EOP events are required to make all engines go idle
763 * (and optional cache flushes executed) before the timestamp
764 * is written.
765 */
766 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
767 radeon_emit(cs, op);
768 radeon_emit(cs, va);
769 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
770 radeon_emit(cs, 0); /* immediate data */
771 radeon_emit(cs, 0); /* unused */
772 }
773
774 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
775 radeon_emit(cs, op);
776 radeon_emit(cs, va);
777 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
778 radeon_emit(cs, new_fence); /* immediate data */
779 radeon_emit(cs, 0); /* unused */
780 }
781 }
782
783 void
784 radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
785 uint32_t ref, uint32_t mask)
786 {
787 assert(op == WAIT_REG_MEM_EQUAL ||
788 op == WAIT_REG_MEM_NOT_EQUAL ||
789 op == WAIT_REG_MEM_GREATER_OR_EQUAL);
790
791 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, false));
792 radeon_emit(cs, op | WAIT_REG_MEM_MEM_SPACE(1));
793 radeon_emit(cs, va);
794 radeon_emit(cs, va >> 32);
795 radeon_emit(cs, ref); /* reference value */
796 radeon_emit(cs, mask); /* mask */
797 radeon_emit(cs, 4); /* poll interval */
798 }
799
800 static void
801 si_emit_acquire_mem(struct radeon_cmdbuf *cs,
802 bool is_mec,
803 bool is_gfx9,
804 unsigned cp_coher_cntl)
805 {
806 if (is_mec || is_gfx9) {
807 uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff;
808 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, false) |
809 PKT3_SHADER_TYPE_S(is_mec));
810 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
811 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
812 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */
813 radeon_emit(cs, 0); /* CP_COHER_BASE */
814 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
815 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
816 } else {
817 /* ACQUIRE_MEM is only required on a compute ring. */
818 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, false));
819 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
820 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
821 radeon_emit(cs, 0); /* CP_COHER_BASE */
822 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
823 }
824 }
825
826 void
827 si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
828 enum chip_class chip_class,
829 uint32_t *flush_cnt,
830 uint64_t flush_va,
831 bool is_mec,
832 enum radv_cmd_flush_bits flush_bits,
833 uint64_t gfx9_eop_bug_va)
834 {
835 unsigned cp_coher_cntl = 0;
836 uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
837 RADV_CMD_FLAG_FLUSH_AND_INV_DB);
838
839 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
840 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
841 if (flush_bits & RADV_CMD_FLAG_INV_SCACHE)
842 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
843
844 if (chip_class <= GFX8) {
845 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
846 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
847 S_0085F0_CB0_DEST_BASE_ENA(1) |
848 S_0085F0_CB1_DEST_BASE_ENA(1) |
849 S_0085F0_CB2_DEST_BASE_ENA(1) |
850 S_0085F0_CB3_DEST_BASE_ENA(1) |
851 S_0085F0_CB4_DEST_BASE_ENA(1) |
852 S_0085F0_CB5_DEST_BASE_ENA(1) |
853 S_0085F0_CB6_DEST_BASE_ENA(1) |
854 S_0085F0_CB7_DEST_BASE_ENA(1);
855
856 /* Necessary for DCC */
857 if (chip_class >= GFX8) {
858 si_cs_emit_write_event_eop(cs,
859 chip_class,
860 is_mec,
861 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
862 0,
863 EOP_DATA_SEL_DISCARD,
864 0, 0,
865 gfx9_eop_bug_va);
866 }
867 }
868 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
869 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
870 S_0085F0_DB_DEST_BASE_ENA(1);
871 }
872 }
873
874 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
875 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
876 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
877 }
878
879 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
880 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
881 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
882 }
883
884 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
885 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
886 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
887 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
888 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
889 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
890 }
891
892 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
893 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
894 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
895 }
896
897 if (chip_class >= GFX9 && flush_cb_db) {
898 unsigned cb_db_event, tc_flags;
899
900 /* Set the CB/DB flush event. */
901 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
902
903 /* These are the only allowed combinations. If you need to
904 * do multiple operations at once, do them separately.
905 * All operations that invalidate L2 also seem to invalidate
906 * metadata. Volatile (VOL) and WC flushes are not listed here.
907 *
908 * TC | TC_WB = writeback & invalidate L2 & L1
909 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
910 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
911 * TC | TC_NC = invalidate L2 for MTYPE == NC
912 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
913 * TCL1 = invalidate L1
914 */
915 tc_flags = EVENT_TC_ACTION_ENA |
916 EVENT_TC_MD_ACTION_ENA;
917
918 /* Ideally flush TC together with CB/DB. */
919 if (flush_bits & RADV_CMD_FLAG_INV_L2) {
920 /* Writeback and invalidate everything in L2 & L1. */
921 tc_flags = EVENT_TC_ACTION_ENA |
922 EVENT_TC_WB_ACTION_ENA;
923
924
925 /* Clear the flags. */
926 flush_bits &= ~(RADV_CMD_FLAG_INV_L2 |
927 RADV_CMD_FLAG_WB_L2 |
928 RADV_CMD_FLAG_INV_VCACHE);
929 }
930 assert(flush_cnt);
931 (*flush_cnt)++;
932
933 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event, tc_flags,
934 EOP_DATA_SEL_VALUE_32BIT,
935 flush_va, *flush_cnt,
936 gfx9_eop_bug_va);
937 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
938 *flush_cnt, 0xffffffff);
939 }
940
941 /* VGT state sync */
942 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
943 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
944 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
945 }
946
947 /* VGT streamout state sync */
948 if (flush_bits & RADV_CMD_FLAG_VGT_STREAMOUT_SYNC) {
949 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
950 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
951 }
952
953 /* Make sure ME is idle (it executes most packets) before continuing.
954 * This prevents read-after-write hazards between PFP and ME.
955 */
956 if ((cp_coher_cntl ||
957 (flush_bits & (RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
958 RADV_CMD_FLAG_INV_VCACHE |
959 RADV_CMD_FLAG_INV_L2 |
960 RADV_CMD_FLAG_WB_L2))) &&
961 !is_mec) {
962 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
963 radeon_emit(cs, 0);
964 }
965
966 if ((flush_bits & RADV_CMD_FLAG_INV_L2) ||
967 (chip_class <= GFX7 && (flush_bits & RADV_CMD_FLAG_WB_L2))) {
968 si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9,
969 cp_coher_cntl |
970 S_0085F0_TC_ACTION_ENA(1) |
971 S_0085F0_TCL1_ACTION_ENA(1) |
972 S_0301F0_TC_WB_ACTION_ENA(chip_class >= GFX8));
973 cp_coher_cntl = 0;
974 } else {
975 if(flush_bits & RADV_CMD_FLAG_WB_L2) {
976 /* WB = write-back
977 * NC = apply to non-coherent MTYPEs
978 * (i.e. MTYPE <= 1, which is what we use everywhere)
979 *
980 * WB doesn't work without NC.
981 */
982 si_emit_acquire_mem(cs, is_mec,
983 chip_class >= GFX9,
984 cp_coher_cntl |
985 S_0301F0_TC_WB_ACTION_ENA(1) |
986 S_0301F0_TC_NC_ACTION_ENA(1));
987 cp_coher_cntl = 0;
988 }
989 if (flush_bits & RADV_CMD_FLAG_INV_VCACHE) {
990 si_emit_acquire_mem(cs, is_mec,
991 chip_class >= GFX9,
992 cp_coher_cntl |
993 S_0085F0_TCL1_ACTION_ENA(1));
994 cp_coher_cntl = 0;
995 }
996 }
997
998 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
999 * Therefore, it should be last. Done in PFP.
1000 */
1001 if (cp_coher_cntl)
1002 si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9, cp_coher_cntl);
1003
1004 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
1005 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1006 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1007 EVENT_INDEX(0));
1008 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
1009 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1010 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1011 EVENT_INDEX(0));
1012 }
1013 }
1014
1015 void
1016 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
1017 {
1018 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1019
1020 if (is_compute)
1021 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1022 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1023 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1024 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1025 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1026 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1027 RADV_CMD_FLAG_VGT_FLUSH |
1028 RADV_CMD_FLAG_START_PIPELINE_STATS |
1029 RADV_CMD_FLAG_STOP_PIPELINE_STATS);
1030
1031 if (!cmd_buffer->state.flush_bits)
1032 return;
1033
1034 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
1035
1036 si_cs_emit_cache_flush(cmd_buffer->cs,
1037 cmd_buffer->device->physical_device->rad_info.chip_class,
1038 &cmd_buffer->gfx9_fence_idx,
1039 cmd_buffer->gfx9_fence_va,
1040 radv_cmd_buffer_uses_mec(cmd_buffer),
1041 cmd_buffer->state.flush_bits,
1042 cmd_buffer->gfx9_eop_bug_va);
1043
1044
1045 if (unlikely(cmd_buffer->device->trace_bo))
1046 radv_cmd_buffer_trace_emit(cmd_buffer);
1047
1048 /* Clear the caches that have been flushed to avoid syncing too much
1049 * when there is some pending active queries.
1050 */
1051 cmd_buffer->active_query_flush_bits &= ~cmd_buffer->state.flush_bits;
1052
1053 cmd_buffer->state.flush_bits = 0;
1054
1055 /* If the driver used a compute shader for resetting a query pool, it
1056 * should be finished at this point.
1057 */
1058 cmd_buffer->pending_reset_query = false;
1059 }
1060
1061 /* sets the CP predication state using a boolean stored at va */
1062 void
1063 si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1064 bool draw_visible, uint64_t va)
1065 {
1066 uint32_t op = 0;
1067
1068 if (va) {
1069 op = PRED_OP(PREDICATION_OP_BOOL64);
1070
1071 /* PREDICATION_DRAW_VISIBLE means that if the 32-bit value is
1072 * zero, all rendering commands are discarded. Otherwise, they
1073 * are discarded if the value is non zero.
1074 */
1075 op |= draw_visible ? PREDICATION_DRAW_VISIBLE :
1076 PREDICATION_DRAW_NOT_VISIBLE;
1077 }
1078 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1079 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
1080 radeon_emit(cmd_buffer->cs, op);
1081 radeon_emit(cmd_buffer->cs, va);
1082 radeon_emit(cmd_buffer->cs, va >> 32);
1083 } else {
1084 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
1085 radeon_emit(cmd_buffer->cs, va);
1086 radeon_emit(cmd_buffer->cs, op | ((va >> 32) & 0xFF));
1087 }
1088 }
1089
1090 /* Set this if you want the 3D engine to wait until CP DMA is done.
1091 * It should be set on the last CP DMA packet. */
1092 #define CP_DMA_SYNC (1 << 0)
1093
1094 /* Set this if the source data was used as a destination in a previous CP DMA
1095 * packet. It's for preventing a read-after-write (RAW) hazard between two
1096 * CP DMA packets. */
1097 #define CP_DMA_RAW_WAIT (1 << 1)
1098 #define CP_DMA_USE_L2 (1 << 2)
1099 #define CP_DMA_CLEAR (1 << 3)
1100
1101 /* Alignment for optimal performance. */
1102 #define SI_CPDMA_ALIGNMENT 32
1103
1104 /* The max number of bytes that can be copied per packet. */
1105 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer *cmd_buffer)
1106 {
1107 unsigned max = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 ?
1108 S_414_BYTE_COUNT_GFX9(~0u) :
1109 S_414_BYTE_COUNT_GFX6(~0u);
1110
1111 /* make it aligned for optimal performance */
1112 return max & ~(SI_CPDMA_ALIGNMENT - 1);
1113 }
1114
1115 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1116 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1117 * clear value.
1118 */
1119 static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer,
1120 uint64_t dst_va, uint64_t src_va,
1121 unsigned size, unsigned flags)
1122 {
1123 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1124 uint32_t header = 0, command = 0;
1125
1126 assert(size <= cp_dma_max_byte_count(cmd_buffer));
1127
1128 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1129 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1130 command |= S_414_BYTE_COUNT_GFX9(size);
1131 else
1132 command |= S_414_BYTE_COUNT_GFX6(size);
1133
1134 /* Sync flags. */
1135 if (flags & CP_DMA_SYNC)
1136 header |= S_411_CP_SYNC(1);
1137 else {
1138 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1139 command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1140 else
1141 command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1142 }
1143
1144 if (flags & CP_DMA_RAW_WAIT)
1145 command |= S_414_RAW_WAIT(1);
1146
1147 /* Src and dst flags. */
1148 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
1149 !(flags & CP_DMA_CLEAR) &&
1150 src_va == dst_va)
1151 header |= S_411_DST_SEL(V_411_NOWHERE); /* prefetch only */
1152 else if (flags & CP_DMA_USE_L2)
1153 header |= S_411_DST_SEL(V_411_DST_ADDR_TC_L2);
1154
1155 if (flags & CP_DMA_CLEAR)
1156 header |= S_411_SRC_SEL(V_411_DATA);
1157 else if (flags & CP_DMA_USE_L2)
1158 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
1159
1160 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1161 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating));
1162 radeon_emit(cs, header);
1163 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1164 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
1165 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1166 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
1167 radeon_emit(cs, command);
1168 } else {
1169 assert(!(flags & CP_DMA_USE_L2));
1170 header |= S_411_SRC_ADDR_HI(src_va >> 32);
1171 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, cmd_buffer->state.predicating));
1172 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1173 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
1174 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1175 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1176 radeon_emit(cs, command);
1177 }
1178
1179 /* CP DMA is executed in ME, but index buffers are read by PFP.
1180 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1181 * indices. If we wanted to execute CP DMA in PFP, this packet
1182 * should precede it.
1183 */
1184 if (flags & CP_DMA_SYNC) {
1185 if (cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
1186 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1187 radeon_emit(cs, 0);
1188 }
1189
1190 /* CP will see the sync flag and wait for all DMAs to complete. */
1191 cmd_buffer->state.dma_is_busy = false;
1192 }
1193
1194 if (unlikely(cmd_buffer->device->trace_bo))
1195 radv_cmd_buffer_trace_emit(cmd_buffer);
1196 }
1197
1198 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1199 unsigned size)
1200 {
1201 uint64_t aligned_va = va & ~(SI_CPDMA_ALIGNMENT - 1);
1202 uint64_t aligned_size = ((va + size + SI_CPDMA_ALIGNMENT -1) & ~(SI_CPDMA_ALIGNMENT - 1)) - aligned_va;
1203
1204 si_emit_cp_dma(cmd_buffer, aligned_va, aligned_va,
1205 aligned_size, CP_DMA_USE_L2);
1206 }
1207
1208 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
1209 uint64_t remaining_size, unsigned *flags)
1210 {
1211
1212 /* Flush the caches for the first copy only.
1213 * Also wait for the previous CP DMA operations.
1214 */
1215 if (cmd_buffer->state.flush_bits) {
1216 si_emit_cache_flush(cmd_buffer);
1217 *flags |= CP_DMA_RAW_WAIT;
1218 }
1219
1220 /* Do the synchronization after the last dma, so that all data
1221 * is written to memory.
1222 */
1223 if (byte_count == remaining_size)
1224 *flags |= CP_DMA_SYNC;
1225 }
1226
1227 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
1228 {
1229 uint64_t va;
1230 uint32_t offset;
1231 unsigned dma_flags = 0;
1232 unsigned buf_size = SI_CPDMA_ALIGNMENT * 2;
1233 void *ptr;
1234
1235 assert(size < SI_CPDMA_ALIGNMENT);
1236
1237 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, SI_CPDMA_ALIGNMENT, &offset, &ptr);
1238
1239 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1240 va += offset;
1241
1242 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
1243
1244 si_emit_cp_dma(cmd_buffer, va, va + SI_CPDMA_ALIGNMENT, size,
1245 dma_flags);
1246 }
1247
1248 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1249 uint64_t src_va, uint64_t dest_va,
1250 uint64_t size)
1251 {
1252 uint64_t main_src_va, main_dest_va;
1253 uint64_t skipped_size = 0, realign_size = 0;
1254
1255 /* Assume that we are not going to sync after the last DMA operation. */
1256 cmd_buffer->state.dma_is_busy = true;
1257
1258 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1259 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1260 /* If the size is not aligned, we must add a dummy copy at the end
1261 * just to align the internal counter. Otherwise, the DMA engine
1262 * would slow down by an order of magnitude for following copies.
1263 */
1264 if (size % SI_CPDMA_ALIGNMENT)
1265 realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
1266
1267 /* If the copy begins unaligned, we must start copying from the next
1268 * aligned block and the skipped part should be copied after everything
1269 * else has been copied. Only the src alignment matters, not dst.
1270 */
1271 if (src_va % SI_CPDMA_ALIGNMENT) {
1272 skipped_size = SI_CPDMA_ALIGNMENT - (src_va % SI_CPDMA_ALIGNMENT);
1273 /* The main part will be skipped if the size is too small. */
1274 skipped_size = MIN2(skipped_size, size);
1275 size -= skipped_size;
1276 }
1277 }
1278 main_src_va = src_va + skipped_size;
1279 main_dest_va = dest_va + skipped_size;
1280
1281 while (size) {
1282 unsigned dma_flags = 0;
1283 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1284
1285 si_cp_dma_prepare(cmd_buffer, byte_count,
1286 size + skipped_size + realign_size,
1287 &dma_flags);
1288
1289 dma_flags &= ~CP_DMA_SYNC;
1290
1291 si_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va,
1292 byte_count, dma_flags);
1293
1294 size -= byte_count;
1295 main_src_va += byte_count;
1296 main_dest_va += byte_count;
1297 }
1298
1299 if (skipped_size) {
1300 unsigned dma_flags = 0;
1301
1302 si_cp_dma_prepare(cmd_buffer, skipped_size,
1303 size + skipped_size + realign_size,
1304 &dma_flags);
1305
1306 si_emit_cp_dma(cmd_buffer, dest_va, src_va,
1307 skipped_size, dma_flags);
1308 }
1309 if (realign_size)
1310 si_cp_dma_realign_engine(cmd_buffer, realign_size);
1311 }
1312
1313 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1314 uint64_t size, unsigned value)
1315 {
1316
1317 if (!size)
1318 return;
1319
1320 assert(va % 4 == 0 && size % 4 == 0);
1321
1322 /* Assume that we are not going to sync after the last DMA operation. */
1323 cmd_buffer->state.dma_is_busy = true;
1324
1325 while (size) {
1326 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1327 unsigned dma_flags = CP_DMA_CLEAR;
1328
1329 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1330
1331 /* Emit the clear packet. */
1332 si_emit_cp_dma(cmd_buffer, va, value, byte_count,
1333 dma_flags);
1334
1335 size -= byte_count;
1336 va += byte_count;
1337 }
1338 }
1339
1340 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer)
1341 {
1342 if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX7)
1343 return;
1344
1345 if (!cmd_buffer->state.dma_is_busy)
1346 return;
1347
1348 /* Issue a dummy DMA that copies zero bytes.
1349 *
1350 * The DMA engine will see that there's no work to do and skip this
1351 * DMA request, however, the CP will see the sync flag and still wait
1352 * for all DMAs to complete.
1353 */
1354 si_emit_cp_dma(cmd_buffer, 0, 0, 0, CP_DMA_SYNC);
1355
1356 cmd_buffer->state.dma_is_busy = false;
1357 }
1358
1359 /* For MSAA sample positions. */
1360 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1361 ((((unsigned)(s0x) & 0xf) << 0) | (((unsigned)(s0y) & 0xf) << 4) | \
1362 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1363 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1364 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1365
1366 /* For obtaining location coordinates from registers */
1367 #define SEXT4(x) ((int)((x) | ((x) & 0x8 ? 0xfffffff0 : 0)))
1368 #define GET_SFIELD(reg, index) SEXT4(((reg) >> ((index) * 4)) & 0xf)
1369 #define GET_SX(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2)
1370 #define GET_SY(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2 + 1)
1371
1372 /* 1x MSAA */
1373 static const uint32_t sample_locs_1x =
1374 FILL_SREG(0, 0, 0, 0, 0, 0, 0, 0);
1375 static const unsigned max_dist_1x = 0;
1376 static const uint64_t centroid_priority_1x = 0x0000000000000000ull;
1377
1378 /* 2xMSAA */
1379 static const uint32_t sample_locs_2x =
1380 FILL_SREG(4,4, -4, -4, 0, 0, 0, 0);
1381 static const unsigned max_dist_2x = 4;
1382 static const uint64_t centroid_priority_2x = 0x1010101010101010ull;
1383
1384 /* 4xMSAA */
1385 static const uint32_t sample_locs_4x =
1386 FILL_SREG(-2,-6, 6, -2, -6, 2, 2, 6);
1387 static const unsigned max_dist_4x = 6;
1388 static const uint64_t centroid_priority_4x = 0x3210321032103210ull;
1389
1390 /* 8xMSAA */
1391 static const uint32_t sample_locs_8x[] = {
1392 FILL_SREG( 1,-3, -1, 3, 5, 1, -3,-5),
1393 FILL_SREG(-5, 5, -7,-1, 3, 7, 7,-7),
1394 /* The following are unused by hardware, but we emit them to IBs
1395 * instead of multiple SET_CONTEXT_REG packets. */
1396 0,
1397 0,
1398 };
1399 static const unsigned max_dist_8x = 7;
1400 static const uint64_t centroid_priority_8x = 0x7654321076543210ull;
1401
1402 unsigned radv_get_default_max_sample_dist(int log_samples)
1403 {
1404 unsigned max_dist[] = {
1405 max_dist_1x,
1406 max_dist_2x,
1407 max_dist_4x,
1408 max_dist_8x,
1409 };
1410 return max_dist[log_samples];
1411 }
1412
1413 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples)
1414 {
1415 switch (nr_samples) {
1416 default:
1417 case 1:
1418 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1419 radeon_emit(cs, (uint32_t)centroid_priority_1x);
1420 radeon_emit(cs, centroid_priority_1x >> 32);
1421 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_1x);
1422 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_1x);
1423 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_1x);
1424 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_1x);
1425 break;
1426 case 2:
1427 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1428 radeon_emit(cs, (uint32_t)centroid_priority_2x);
1429 radeon_emit(cs, centroid_priority_2x >> 32);
1430 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x);
1431 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x);
1432 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x);
1433 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x);
1434 break;
1435 case 4:
1436 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1437 radeon_emit(cs, (uint32_t)centroid_priority_4x);
1438 radeon_emit(cs, centroid_priority_4x >> 32);
1439 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x);
1440 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x);
1441 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x);
1442 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x);
1443 break;
1444 case 8:
1445 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1446 radeon_emit(cs, (uint32_t)centroid_priority_8x);
1447 radeon_emit(cs, centroid_priority_8x >> 32);
1448 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1449 radeon_emit_array(cs, sample_locs_8x, 4);
1450 radeon_emit_array(cs, sample_locs_8x, 4);
1451 radeon_emit_array(cs, sample_locs_8x, 4);
1452 radeon_emit_array(cs, sample_locs_8x, 2);
1453 break;
1454 }
1455 }
1456
1457 static void radv_get_sample_position(struct radv_device *device,
1458 unsigned sample_count,
1459 unsigned sample_index, float *out_value)
1460 {
1461 const uint32_t *sample_locs;
1462
1463 switch (sample_count) {
1464 case 1:
1465 default:
1466 sample_locs = &sample_locs_1x;
1467 break;
1468 case 2:
1469 sample_locs = &sample_locs_2x;
1470 break;
1471 case 4:
1472 sample_locs = &sample_locs_4x;
1473 break;
1474 case 8:
1475 sample_locs = sample_locs_8x;
1476 break;
1477 }
1478
1479 out_value[0] = (GET_SX(sample_locs, sample_index) + 8) / 16.0f;
1480 out_value[1] = (GET_SY(sample_locs, sample_index) + 8) / 16.0f;
1481 }
1482
1483 void radv_device_init_msaa(struct radv_device *device)
1484 {
1485 int i;
1486
1487 radv_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1488
1489 for (i = 0; i < 2; i++)
1490 radv_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1491 for (i = 0; i < 4; i++)
1492 radv_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1493 for (i = 0; i < 8; i++)
1494 radv_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1495 }