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radv: Emit cache flushes before CP DMA.
[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for SI */
29
30 #include "radv_private.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "radv_util.h"
34 #include "main/macros.h"
35
36 #define SI_GS_PER_ES 128
37
38 static void
39 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
40 struct radeon_winsys_cs *cs,
41 unsigned raster_config,
42 unsigned raster_config_1)
43 {
44 unsigned sh_per_se = MAX2(physical_device->rad_info.max_sh_per_se, 1);
45 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
46 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
47 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
48 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
49 unsigned rb_per_se = num_rb / num_se;
50 unsigned se_mask[4];
51 unsigned se;
52
53 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
54 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
55 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
56 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
57
58 assert(num_se == 1 || num_se == 2 || num_se == 4);
59 assert(sh_per_se == 1 || sh_per_se == 2);
60 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
61
62 /* XXX: I can't figure out what the *_XSEL and *_YSEL
63 * fields are for, so I'm leaving them as their default
64 * values. */
65
66 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
67 (!se_mask[2] && !se_mask[3]))) {
68 raster_config_1 &= C_028354_SE_PAIR_MAP;
69
70 if (!se_mask[0] && !se_mask[1]) {
71 raster_config_1 |=
72 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
73 } else {
74 raster_config_1 |=
75 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
76 }
77 }
78
79 for (se = 0; se < num_se; se++) {
80 unsigned raster_config_se = raster_config;
81 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
82 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
83 int idx = (se / 2) * 2;
84
85 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
86 raster_config_se &= C_028350_SE_MAP;
87
88 if (!se_mask[idx]) {
89 raster_config_se |=
90 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
91 } else {
92 raster_config_se |=
93 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
94 }
95 }
96
97 pkr0_mask &= rb_mask;
98 pkr1_mask &= rb_mask;
99 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
100 raster_config_se &= C_028350_PKR_MAP;
101
102 if (!pkr0_mask) {
103 raster_config_se |=
104 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
105 } else {
106 raster_config_se |=
107 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
108 }
109 }
110
111 if (rb_per_se >= 2) {
112 unsigned rb0_mask = 1 << (se * rb_per_se);
113 unsigned rb1_mask = rb0_mask << 1;
114
115 rb0_mask &= rb_mask;
116 rb1_mask &= rb_mask;
117 if (!rb0_mask || !rb1_mask) {
118 raster_config_se &= C_028350_RB_MAP_PKR0;
119
120 if (!rb0_mask) {
121 raster_config_se |=
122 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
123 } else {
124 raster_config_se |=
125 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
126 }
127 }
128
129 if (rb_per_se > 2) {
130 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
131 rb1_mask = rb0_mask << 1;
132 rb0_mask &= rb_mask;
133 rb1_mask &= rb_mask;
134 if (!rb0_mask || !rb1_mask) {
135 raster_config_se &= C_028350_RB_MAP_PKR1;
136
137 if (!rb0_mask) {
138 raster_config_se |=
139 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
140 } else {
141 raster_config_se |=
142 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
143 }
144 }
145 }
146 }
147
148 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
149 if (physical_device->rad_info.chip_class < CIK)
150 radeon_set_config_reg(cs, GRBM_GFX_INDEX,
151 SE_INDEX(se) | SH_BROADCAST_WRITES |
152 INSTANCE_BROADCAST_WRITES);
153 else
154 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
155 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
156 S_030800_INSTANCE_BROADCAST_WRITES(1));
157 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
158 if (physical_device->rad_info.chip_class >= CIK)
159 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
160 }
161
162 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
163 if (physical_device->rad_info.chip_class < CIK)
164 radeon_set_config_reg(cs, GRBM_GFX_INDEX,
165 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
166 INSTANCE_BROADCAST_WRITES);
167 else
168 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
169 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
170 S_030800_INSTANCE_BROADCAST_WRITES(1));
171 }
172
173 static void
174 si_emit_compute(struct radv_physical_device *physical_device,
175 struct radeon_winsys_cs *cs)
176 {
177 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
178 radeon_emit(cs, 0);
179 radeon_emit(cs, 0);
180 radeon_emit(cs, 0);
181
182 radeon_set_sh_reg_seq(cs, R_00B854_COMPUTE_RESOURCE_LIMITS, 3);
183 radeon_emit(cs, 0);
184 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
185 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
186 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
187
188 if (physical_device->rad_info.chip_class >= CIK) {
189 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
190 radeon_set_sh_reg_seq(cs,
191 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
192 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
193 S_00B864_SH1_CU_EN(0xffff));
194 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
195 S_00B868_SH1_CU_EN(0xffff));
196 }
197
198 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
199 * and is now per pipe, so it should be handled in the
200 * kernel if we want to use something other than the default value,
201 * which is now 0x22f.
202 */
203 if (physical_device->rad_info.chip_class <= SI) {
204 /* XXX: This should be:
205 * (number of compute units) * 4 * (waves per simd) - 1 */
206
207 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
208 0x190 /* Default value */);
209 }
210 }
211
212 void
213 si_init_compute(struct radv_cmd_buffer *cmd_buffer)
214 {
215 struct radv_physical_device *physical_device = cmd_buffer->device->physical_device;
216 si_emit_compute(physical_device, cmd_buffer->cs);
217 }
218
219 static void
220 si_emit_config(struct radv_physical_device *physical_device,
221 struct radeon_winsys_cs *cs)
222 {
223 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
224 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
225 unsigned raster_config, raster_config_1;
226 int i;
227
228 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
229 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
230 radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
231
232 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
233 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
234
235 /* FIXME calculate these values somehow ??? */
236 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
237 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
238 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
239
240 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
241 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
242
243 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
244 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
245 if (physical_device->rad_info.chip_class < CIK)
246 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
247 S_008A14_CLIP_VTX_REORDER_ENA(1));
248
249 radeon_set_context_reg(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
250 radeon_set_context_reg(cs, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
251
252 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
253
254 for (i = 0; i < 16; i++) {
255 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
256 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
257 }
258
259 switch (physical_device->rad_info.family) {
260 case CHIP_TAHITI:
261 case CHIP_PITCAIRN:
262 raster_config = 0x2a00126a;
263 raster_config_1 = 0x00000000;
264 break;
265 case CHIP_VERDE:
266 raster_config = 0x0000124a;
267 raster_config_1 = 0x00000000;
268 break;
269 case CHIP_OLAND:
270 raster_config = 0x00000082;
271 raster_config_1 = 0x00000000;
272 break;
273 case CHIP_HAINAN:
274 raster_config = 0x00000000;
275 raster_config_1 = 0x00000000;
276 break;
277 case CHIP_BONAIRE:
278 raster_config = 0x16000012;
279 raster_config_1 = 0x00000000;
280 break;
281 case CHIP_HAWAII:
282 raster_config = 0x3a00161a;
283 raster_config_1 = 0x0000002e;
284 break;
285 case CHIP_FIJI:
286 if (physical_device->rad_info.cik_macrotile_mode_array[0] == 0x000000e8) {
287 /* old kernels with old tiling config */
288 raster_config = 0x16000012;
289 raster_config_1 = 0x0000002a;
290 } else {
291 raster_config = 0x3a00161a;
292 raster_config_1 = 0x0000002e;
293 }
294 break;
295 case CHIP_POLARIS10:
296 raster_config = 0x16000012;
297 raster_config_1 = 0x0000002a;
298 break;
299 case CHIP_POLARIS11:
300 raster_config = 0x16000012;
301 raster_config_1 = 0x00000000;
302 break;
303 case CHIP_TONGA:
304 raster_config = 0x16000012;
305 raster_config_1 = 0x0000002a;
306 break;
307 case CHIP_ICELAND:
308 if (num_rb == 1)
309 raster_config = 0x00000000;
310 else
311 raster_config = 0x00000002;
312 raster_config_1 = 0x00000000;
313 break;
314 case CHIP_CARRIZO:
315 raster_config = 0x00000002;
316 raster_config_1 = 0x00000000;
317 break;
318 case CHIP_KAVERI:
319 /* KV should be 0x00000002, but that causes problems with radeon */
320 raster_config = 0x00000000; /* 0x00000002 */
321 raster_config_1 = 0x00000000;
322 break;
323 case CHIP_KABINI:
324 case CHIP_MULLINS:
325 case CHIP_STONEY:
326 raster_config = 0x00000000;
327 raster_config_1 = 0x00000000;
328 break;
329 default:
330 fprintf(stderr,
331 "radeonsi: Unknown GPU, using 0 for raster_config\n");
332 raster_config = 0x00000000;
333 raster_config_1 = 0x00000000;
334 break;
335 }
336
337 /* Always use the default config when all backends are enabled
338 * (or when we failed to determine the enabled backends).
339 */
340 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
341 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
342 raster_config);
343 if (physical_device->rad_info.chip_class >= CIK)
344 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
345 raster_config_1);
346 } else {
347 si_write_harvested_raster_configs(physical_device, cs, raster_config, raster_config_1);
348 }
349
350 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
351 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
352 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
353 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
354 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
355 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
356 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
357
358 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
359 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
360 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
361 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
362 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
363
364 radeon_set_context_reg(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, fui(1.0));
365 radeon_set_context_reg(cs, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, fui(1.0));
366 radeon_set_context_reg(cs, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, fui(1.0));
367 radeon_set_context_reg(cs, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, fui(1.0));
368
369 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
370 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
371 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
372 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
373 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
374 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
375
376 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
377 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
378 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
379
380 if (physical_device->rad_info.chip_class >= CIK) {
381 /* If this is 0, Bonaire can hang even if GS isn't being used.
382 * Other chips are unaffected. These are suboptimal values,
383 * but we don't use on-chip GS.
384 */
385 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
386 S_028A44_ES_VERTS_PER_SUBGRP(64) |
387 S_028A44_GS_PRIMS_PER_SUBGRP(4));
388
389 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
390 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
391 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
392 radeon_set_sh_reg(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
393
394 if (physical_device->rad_info.num_good_compute_units /
395 (physical_device->rad_info.max_se * physical_device->rad_info.max_sh_per_se) <= 4) {
396 /* Too few available compute units per SH. Disallowing
397 * VS to run on CU0 could hurt us more than late VS
398 * allocation would help.
399 *
400 * LATE_ALLOC_VS = 2 is the highest safe number.
401 */
402 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
403 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
404 } else {
405 /* Set LATE_ALLOC_VS == 31. It should be less than
406 * the number of scratch waves. Limitations:
407 * - VS can't execute on CU0.
408 * - If HS writes outputs to LDS, LS can't execute on CU0.
409 */
410 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
411 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
412 }
413
414 radeon_set_sh_reg(cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
415 }
416
417 if (physical_device->rad_info.chip_class >= VI) {
418 radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL,
419 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
420 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
421 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
422 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
423 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
424 S_028B50_ACCUM_ISOLINE(32) |
425 S_028B50_ACCUM_TRI(11) |
426 S_028B50_ACCUM_QUAD(11) |
427 S_028B50_DONUT_SPLIT(16));
428 } else {
429 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
430 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
431 }
432
433 if (physical_device->rad_info.family == CHIP_STONEY)
434 radeon_set_context_reg(cs, R_028C40_PA_SC_SHADER_CONTROL, 0);
435
436 si_emit_compute(physical_device, cs);
437 }
438
439 void si_init_config(struct radv_cmd_buffer *cmd_buffer)
440 {
441 struct radv_physical_device *physical_device = cmd_buffer->device->physical_device;
442
443 si_emit_config(physical_device, cmd_buffer->cs);
444 }
445
446 void
447 cik_create_gfx_config(struct radv_device *device)
448 {
449 struct radeon_winsys_cs *cs = device->ws->cs_create(device->ws, RING_GFX);
450 if (!cs)
451 return;
452
453 si_emit_config(device->physical_device, cs);
454
455 while (cs->cdw & 7) {
456 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
457 radeon_emit(cs, 0x80000000);
458 else
459 radeon_emit(cs, 0xffff1000);
460 }
461
462 device->gfx_init = device->ws->buffer_create(device->ws,
463 cs->cdw * 4, 4096,
464 RADEON_DOMAIN_GTT,
465 RADEON_FLAG_CPU_ACCESS);
466 if (!device->gfx_init)
467 goto fail;
468
469 void *map = device->ws->buffer_map(device->gfx_init);
470 if (!map) {
471 device->ws->buffer_destroy(device->gfx_init);
472 device->gfx_init = NULL;
473 goto fail;
474 }
475 memcpy(map, cs->buf, cs->cdw * 4);
476
477 device->ws->buffer_unmap(device->gfx_init);
478 device->gfx_init_size_dw = cs->cdw;
479 fail:
480 device->ws->cs_destroy(cs);
481 }
482
483 static void
484 get_viewport_xform(const VkViewport *viewport,
485 float scale[3], float translate[3])
486 {
487 float x = viewport->x;
488 float y = viewport->y;
489 float half_width = 0.5f * viewport->width;
490 float half_height = 0.5f * viewport->height;
491 double n = viewport->minDepth;
492 double f = viewport->maxDepth;
493
494 scale[0] = half_width;
495 translate[0] = half_width + x;
496 scale[1] = half_height;
497 translate[1] = half_height + y;
498
499 scale[2] = (f - n);
500 translate[2] = n;
501 }
502
503 void
504 si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
505 int count, const VkViewport *viewports)
506 {
507 int i;
508
509 if (count == 0) {
510 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6);
511 radeon_emit(cs, fui(1.0));
512 radeon_emit(cs, fui(0.0));
513 radeon_emit(cs, fui(1.0));
514 radeon_emit(cs, fui(0.0));
515 radeon_emit(cs, fui(1.0));
516 radeon_emit(cs, fui(0.0));
517
518 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
519 radeon_emit(cs, fui(0.0));
520 radeon_emit(cs, fui(1.0));
521
522 return;
523 }
524 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
525 first_vp * 4 * 6, count * 6);
526
527 for (i = 0; i < count; i++) {
528 float scale[3], translate[3];
529
530
531 get_viewport_xform(&viewports[i], scale, translate);
532 radeon_emit(cs, fui(scale[0]));
533 radeon_emit(cs, fui(translate[0]));
534 radeon_emit(cs, fui(scale[1]));
535 radeon_emit(cs, fui(translate[1]));
536 radeon_emit(cs, fui(scale[2]));
537 radeon_emit(cs, fui(translate[2]));
538 }
539
540 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
541 first_vp * 4 * 2, count * 2);
542 for (i = 0; i < count; i++) {
543 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
544 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
545 radeon_emit(cs, fui(zmin));
546 radeon_emit(cs, fui(zmax));
547 }
548 }
549
550 void
551 si_write_scissors(struct radeon_winsys_cs *cs, int first,
552 int count, const VkRect2D *scissors)
553 {
554 int i;
555 if (count == 0)
556 return;
557
558 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
559 for (i = 0; i < count; i++) {
560 radeon_emit(cs, S_028250_TL_X(scissors[i].offset.x) |
561 S_028250_TL_Y(scissors[i].offset.y) |
562 S_028250_WINDOW_OFFSET_DISABLE(1));
563 radeon_emit(cs, S_028254_BR_X(scissors[i].offset.x + scissors[i].extent.width) |
564 S_028254_BR_Y(scissors[i].offset.y + scissors[i].extent.height));
565 }
566 }
567
568 static inline unsigned
569 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
570 {
571 if (num == 0)
572 return 0;
573
574 if (info->incr == 0)
575 return 0;
576
577 if (num < info->min)
578 return 0;
579
580 return 1 + ((num - info->min) / info->incr);
581 }
582
583 uint32_t
584 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
585 bool instanced_or_indirect_draw,
586 uint32_t draw_vertex_count)
587 {
588 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
589 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
590 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
591 unsigned prim = cmd_buffer->state.pipeline->graphics.prim;
592 unsigned primgroup_size = 128; /* recommended without a GS */
593 unsigned max_primgroup_in_wave = 2;
594 /* SWITCH_ON_EOP(0) is always preferable. */
595 bool wd_switch_on_eop = false;
596 bool ia_switch_on_eop = false;
597 bool ia_switch_on_eoi = false;
598 bool partial_vs_wave = false;
599 bool partial_es_wave = false;
600 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
601 bool multi_instances_smaller_than_primgroup;
602
603 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
604 primgroup_size = 64; /* recommended with a GS */
605
606 multi_instances_smaller_than_primgroup = (instanced_or_indirect_draw ||
607 num_prims < primgroup_size);
608 /* TODO TES */
609
610 /* TODO linestipple */
611
612 if (chip_class >= CIK) {
613 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
614 * 4 shader engines. Set 1 to pass the assertion below.
615 * The other cases are hardware requirements. */
616 if (info->max_se < 4 ||
617 prim == V_008958_DI_PT_POLYGON ||
618 prim == V_008958_DI_PT_LINELOOP ||
619 prim == V_008958_DI_PT_TRIFAN ||
620 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
621 (cmd_buffer->state.pipeline->graphics.prim_restart_enable &&
622 (family < CHIP_POLARIS10 ||
623 (prim != V_008958_DI_PT_POINTLIST &&
624 prim != V_008958_DI_PT_LINESTRIP &&
625 prim != V_008958_DI_PT_TRISTRIP))))
626 wd_switch_on_eop = true;
627
628 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
629 * We don't know that for indirect drawing, so treat it as
630 * always problematic. */
631 if (family == CHIP_HAWAII &&
632 instanced_or_indirect_draw)
633 wd_switch_on_eop = true;
634
635 /* Performance recommendation for 4 SE Gfx7-8 parts if
636 * instances are smaller than a primgroup.
637 * Assume indirect draws always use small instances.
638 * This is needed for good VS wave utilization.
639 */
640 if (chip_class <= VI &&
641 info->max_se == 4 &&
642 multi_instances_smaller_than_primgroup)
643 wd_switch_on_eop = true;
644
645 /* Required on CIK and later. */
646 if (info->max_se > 2 && !wd_switch_on_eop)
647 ia_switch_on_eoi = true;
648
649 /* Required by Hawaii and, for some special cases, by VI. */
650 if (ia_switch_on_eoi &&
651 (family == CHIP_HAWAII ||
652 (chip_class == VI &&
653 (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
654 partial_vs_wave = true;
655
656 /* Instancing bug on Bonaire. */
657 if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
658 instanced_or_indirect_draw)
659 partial_vs_wave = true;
660
661 /* If the WD switch is false, the IA switch must be false too. */
662 assert(wd_switch_on_eop || !ia_switch_on_eop);
663 }
664 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
665 if (ia_switch_on_eoi)
666 partial_es_wave = true;
667
668 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
669 /* GS requirement. */
670 if (SI_GS_PER_ES / primgroup_size >= cmd_buffer->device->gs_table_depth - 3)
671 partial_es_wave = true;
672
673 /* Hw bug with single-primitive instances and SWITCH_ON_EOI
674 * on multi-SE chips. */
675 if (info->max_se >= 2 && ia_switch_on_eoi &&
676 (instanced_or_indirect_draw &&
677 num_prims <= 1))
678 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
679 }
680
681 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
682 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
683 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
684 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
685 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
686 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= CIK ? wd_switch_on_eop : 0) |
687 S_028AA8_MAX_PRIMGRP_IN_WAVE(chip_class >= VI ?
688 max_primgroup_in_wave : 0);
689
690 }
691
692 static void
693 si_emit_acquire_mem(struct radeon_winsys_cs *cs,
694 bool is_mec,
695 unsigned cp_coher_cntl)
696 {
697 if (is_mec) {
698 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0) |
699 PKT3_SHADER_TYPE_S(1));
700 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
701 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
702 radeon_emit(cs, 0xff); /* CP_COHER_SIZE_HI */
703 radeon_emit(cs, 0); /* CP_COHER_BASE */
704 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
705 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
706 } else {
707 /* ACQUIRE_MEM is only required on a compute ring. */
708 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
709 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
710 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
711 radeon_emit(cs, 0); /* CP_COHER_BASE */
712 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
713 }
714 }
715
716 void
717 si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
718 enum chip_class chip_class,
719 bool is_mec,
720 enum radv_cmd_flush_bits flush_bits)
721 {
722 unsigned cp_coher_cntl = 0;
723
724 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
725 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
726 if (flush_bits & RADV_CMD_FLAG_INV_SMEM_L1)
727 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
728
729 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
730 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
731 S_0085F0_CB0_DEST_BASE_ENA(1) |
732 S_0085F0_CB1_DEST_BASE_ENA(1) |
733 S_0085F0_CB2_DEST_BASE_ENA(1) |
734 S_0085F0_CB3_DEST_BASE_ENA(1) |
735 S_0085F0_CB4_DEST_BASE_ENA(1) |
736 S_0085F0_CB5_DEST_BASE_ENA(1) |
737 S_0085F0_CB6_DEST_BASE_ENA(1) |
738 S_0085F0_CB7_DEST_BASE_ENA(1);
739
740 /* Necessary for DCC */
741 if (chip_class >= VI) {
742 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
743 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_DATA_TS) |
744 EVENT_INDEX(5));
745 radeon_emit(cs, 0);
746 radeon_emit(cs, 0);
747 radeon_emit(cs, 0);
748 radeon_emit(cs, 0);
749 }
750 }
751
752 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
753 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
754 S_0085F0_DB_DEST_BASE_ENA(1);
755 }
756
757 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
758 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
759 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
760 }
761
762 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
763 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
764 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
765 }
766
767 if (!(flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
768 RADV_CMD_FLAG_FLUSH_AND_INV_DB))) {
769 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
770 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
771 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
772 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
773 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
774 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
775 }
776 }
777
778 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
779 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
780 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
781 }
782
783 /* VGT state sync */
784 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
785 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
786 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
787 }
788
789 /* Make sure ME is idle (it executes most packets) before continuing.
790 * This prevents read-after-write hazards between PFP and ME.
791 */
792 if ((cp_coher_cntl || (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) &&
793 !is_mec) {
794 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
795 radeon_emit(cs, 0);
796 }
797
798 if ((flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) ||
799 (chip_class <= CIK && (flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) {
800 cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1);
801 if (chip_class >= VI)
802 cp_coher_cntl |= S_0301F0_TC_WB_ACTION_ENA(1);
803 } else if(flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2) {
804 cp_coher_cntl |= S_0301F0_TC_WB_ACTION_ENA(1) |
805 S_0301F0_TC_NC_ACTION_ENA(1);
806
807 /* L2 writeback doesn't combine with L1 invalidate */
808 si_emit_acquire_mem(cs, is_mec, cp_coher_cntl);
809
810 cp_coher_cntl = 0;
811 }
812
813 if (flush_bits & RADV_CMD_FLAG_INV_VMEM_L1)
814 cp_coher_cntl |= S_0085F0_TCL1_ACTION_ENA(1);
815
816 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
817 * Therefore, it should be last. Done in PFP.
818 */
819 if (cp_coher_cntl)
820 si_emit_acquire_mem(cs, is_mec, cp_coher_cntl);
821 }
822
823 void
824 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
825 {
826 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
827
828 if (is_compute)
829 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
830 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
831 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
832 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
833 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
834 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
835 RADV_CMD_FLAG_VGT_FLUSH);
836
837 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
838
839 si_cs_emit_cache_flush(cmd_buffer->cs,
840 cmd_buffer->device->physical_device->rad_info.chip_class,
841 radv_cmd_buffer_uses_mec(cmd_buffer),
842 cmd_buffer->state.flush_bits);
843
844
845 if (cmd_buffer->state.flush_bits)
846 radv_cmd_buffer_trace_emit(cmd_buffer);
847 cmd_buffer->state.flush_bits = 0;
848 }
849
850
851 /* Set this if you want the 3D engine to wait until CP DMA is done.
852 * It should be set on the last CP DMA packet. */
853 #define R600_CP_DMA_SYNC (1 << 0) /* R600+ */
854
855 /* Set this if the source data was used as a destination in a previous CP DMA
856 * packet. It's for preventing a read-after-write (RAW) hazard between two
857 * CP DMA packets. */
858 #define SI_CP_DMA_RAW_WAIT (1 << 1) /* SI+ */
859 #define CIK_CP_DMA_USE_L2 (1 << 2)
860
861 /* Alignment for optimal performance. */
862 #define CP_DMA_ALIGNMENT 32
863 /* The max number of bytes to copy per packet. */
864 #define CP_DMA_MAX_BYTE_COUNT ((1 << 21) - CP_DMA_ALIGNMENT)
865
866 static void si_emit_cp_dma_copy_buffer(struct radv_cmd_buffer *cmd_buffer,
867 uint64_t dst_va, uint64_t src_va,
868 unsigned size, unsigned flags)
869 {
870 struct radeon_winsys_cs *cs = cmd_buffer->cs;
871 uint32_t sync_flag = flags & R600_CP_DMA_SYNC ? S_411_CP_SYNC(1) : 0;
872 uint32_t wr_confirm = !(flags & R600_CP_DMA_SYNC) ? S_414_DISABLE_WR_CONFIRM(1) : 0;
873 uint32_t raw_wait = flags & SI_CP_DMA_RAW_WAIT ? S_414_RAW_WAIT(1) : 0;
874 uint32_t sel = flags & CIK_CP_DMA_USE_L2 ?
875 S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2) |
876 S_411_DSL_SEL(V_411_DST_ADDR_TC_L2) : 0;
877
878 assert(size);
879 assert((size & ((1<<21)-1)) == size);
880
881 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
882
883 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
884 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
885 radeon_emit(cs, sync_flag | sel); /* CP_SYNC [31] */
886 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
887 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
888 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
889 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
890 radeon_emit(cs, size | wr_confirm | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
891 } else {
892 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
893 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
894 radeon_emit(cs, sync_flag | ((src_va >> 32) & 0xffff)); /* CP_SYNC [31] | SRC_ADDR_HI [15:0] */
895 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
896 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
897 radeon_emit(cs, size | wr_confirm | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
898 }
899
900 /* CP DMA is executed in ME, but index buffers are read by PFP.
901 * This ensures that ME (CP DMA) is idle before PFP starts fetching
902 * indices. If we wanted to execute CP DMA in PFP, this packet
903 * should precede it.
904 */
905 if (sync_flag && cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
906 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
907 radeon_emit(cs, 0);
908 }
909
910 radv_cmd_buffer_trace_emit(cmd_buffer);
911 }
912
913 /* Emit a CP DMA packet to clear a buffer. The size must fit in bits [20:0]. */
914 static void si_emit_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer,
915 uint64_t dst_va, unsigned size,
916 uint32_t clear_value, unsigned flags)
917 {
918 struct radeon_winsys_cs *cs = cmd_buffer->cs;
919 uint32_t sync_flag = flags & R600_CP_DMA_SYNC ? S_411_CP_SYNC(1) : 0;
920 uint32_t wr_confirm = !(flags & R600_CP_DMA_SYNC) ? S_414_DISABLE_WR_CONFIRM(1) : 0;
921 uint32_t raw_wait = flags & SI_CP_DMA_RAW_WAIT ? S_414_RAW_WAIT(1) : 0;
922 uint32_t dst_sel = flags & CIK_CP_DMA_USE_L2 ? S_411_DSL_SEL(V_411_DST_ADDR_TC_L2) : 0;
923
924 assert(size);
925 assert((size & ((1<<21)-1)) == size);
926
927 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
928
929 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
930 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
931 radeon_emit(cs, sync_flag | dst_sel | S_411_SRC_SEL(V_411_DATA)); /* CP_SYNC [31] | SRC_SEL[30:29] */
932 radeon_emit(cs, clear_value); /* DATA [31:0] */
933 radeon_emit(cs, 0);
934 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
935 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [15:0] */
936 radeon_emit(cs, size | wr_confirm | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
937 } else {
938 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
939 radeon_emit(cs, clear_value); /* DATA [31:0] */
940 radeon_emit(cs, sync_flag | S_411_SRC_SEL(V_411_DATA)); /* CP_SYNC [31] | SRC_SEL[30:29] */
941 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
942 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
943 radeon_emit(cs, size | wr_confirm | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
944 }
945
946 /* See "copy_buffer" for explanation. */
947 if (sync_flag && cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
948 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
949 radeon_emit(cs, 0);
950 }
951 radv_cmd_buffer_trace_emit(cmd_buffer);
952 }
953
954 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
955 uint64_t remaining_size, unsigned *flags)
956 {
957
958 /* Flush the caches for the first copy only.
959 * Also wait for the previous CP DMA operations.
960 */
961 if (cmd_buffer->state.flush_bits) {
962 si_emit_cache_flush(cmd_buffer);
963 *flags |= SI_CP_DMA_RAW_WAIT;
964 }
965
966 /* Do the synchronization after the last dma, so that all data
967 * is written to memory.
968 */
969 if (byte_count == remaining_size)
970 *flags |= R600_CP_DMA_SYNC;
971 }
972
973 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
974 {
975 uint64_t va;
976 uint32_t offset;
977 unsigned dma_flags = 0;
978 unsigned buf_size = CP_DMA_ALIGNMENT * 2;
979 void *ptr;
980
981 assert(size < CP_DMA_ALIGNMENT);
982
983 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, CP_DMA_ALIGNMENT, &offset, &ptr);
984
985 va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
986 va += offset;
987
988 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
989
990 si_emit_cp_dma_copy_buffer(cmd_buffer, va, va + CP_DMA_ALIGNMENT, size,
991 dma_flags);
992 }
993
994 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
995 uint64_t src_va, uint64_t dest_va,
996 uint64_t size)
997 {
998 uint64_t main_src_va, main_dest_va;
999 uint64_t skipped_size = 0, realign_size = 0;
1000
1001 si_emit_cache_flush(cmd_buffer);
1002
1003 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1004 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1005 /* If the size is not aligned, we must add a dummy copy at the end
1006 * just to align the internal counter. Otherwise, the DMA engine
1007 * would slow down by an order of magnitude for following copies.
1008 */
1009 if (size % CP_DMA_ALIGNMENT)
1010 realign_size = CP_DMA_ALIGNMENT - (size % CP_DMA_ALIGNMENT);
1011
1012 /* If the copy begins unaligned, we must start copying from the next
1013 * aligned block and the skipped part should be copied after everything
1014 * else has been copied. Only the src alignment matters, not dst.
1015 */
1016 if (src_va % CP_DMA_ALIGNMENT) {
1017 skipped_size = CP_DMA_ALIGNMENT - (src_va % CP_DMA_ALIGNMENT);
1018 /* The main part will be skipped if the size is too small. */
1019 skipped_size = MIN2(skipped_size, size);
1020 size -= skipped_size;
1021 }
1022 }
1023 main_src_va = src_va + skipped_size;
1024 main_dest_va = dest_va + skipped_size;
1025
1026 while (size) {
1027 unsigned dma_flags = 0;
1028 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
1029
1030 si_cp_dma_prepare(cmd_buffer, byte_count,
1031 size + skipped_size + realign_size,
1032 &dma_flags);
1033
1034 si_emit_cp_dma_copy_buffer(cmd_buffer, main_dest_va, main_src_va,
1035 byte_count, dma_flags);
1036
1037 size -= byte_count;
1038 main_src_va += byte_count;
1039 main_dest_va += byte_count;
1040 }
1041
1042 if (skipped_size) {
1043 unsigned dma_flags = 0;
1044
1045 si_cp_dma_prepare(cmd_buffer, skipped_size,
1046 size + skipped_size + realign_size,
1047 &dma_flags);
1048
1049 si_emit_cp_dma_copy_buffer(cmd_buffer, dest_va, src_va,
1050 skipped_size, dma_flags);
1051 }
1052 if (realign_size)
1053 si_cp_dma_realign_engine(cmd_buffer, realign_size);
1054 }
1055
1056 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1057 uint64_t size, unsigned value)
1058 {
1059
1060 if (!size)
1061 return;
1062
1063 assert(va % 4 == 0 && size % 4 == 0);
1064
1065 si_emit_cache_flush(cmd_buffer);
1066
1067 while (size) {
1068 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
1069 unsigned dma_flags = 0;
1070
1071 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1072
1073 /* Emit the clear packet. */
1074 si_emit_cp_dma_clear_buffer(cmd_buffer, va, byte_count, value,
1075 dma_flags);
1076
1077 size -= byte_count;
1078 va += byte_count;
1079 }
1080 }
1081
1082 /* For MSAA sample positions. */
1083 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1084 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
1085 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1086 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1087 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1088
1089
1090 /* 2xMSAA
1091 * There are two locations (4, 4), (-4, -4). */
1092 const uint32_t eg_sample_locs_2x[4] = {
1093 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1094 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1095 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1096 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1097 };
1098 const unsigned eg_max_dist_2x = 4;
1099 /* 4xMSAA
1100 * There are 4 locations: (-2, 6), (6, -2), (-6, 2), (2, 6). */
1101 const uint32_t eg_sample_locs_4x[4] = {
1102 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1103 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1104 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1105 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1106 };
1107 const unsigned eg_max_dist_4x = 6;
1108
1109 /* Cayman 8xMSAA */
1110 static const uint32_t cm_sample_locs_8x[] = {
1111 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1112 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1113 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1114 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1115 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1116 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1117 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1118 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1119 };
1120 static const unsigned cm_max_dist_8x = 8;
1121 /* Cayman 16xMSAA */
1122 static const uint32_t cm_sample_locs_16x[] = {
1123 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1124 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1125 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1126 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1127 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1128 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1129 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1130 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1131 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1132 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1133 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1134 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1135 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1136 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1137 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1138 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1139 };
1140 static const unsigned cm_max_dist_16x = 8;
1141
1142 unsigned radv_cayman_get_maxdist(int log_samples)
1143 {
1144 unsigned max_dist[] = {
1145 0,
1146 eg_max_dist_2x,
1147 eg_max_dist_4x,
1148 cm_max_dist_8x,
1149 cm_max_dist_16x
1150 };
1151 return max_dist[log_samples];
1152 }
1153
1154 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples)
1155 {
1156 switch (nr_samples) {
1157 default:
1158 case 1:
1159 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0);
1160 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0);
1161 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0);
1162 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0);
1163 break;
1164 case 2:
1165 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]);
1166 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]);
1167 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]);
1168 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]);
1169 break;
1170 case 4:
1171 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]);
1172 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_4x[1]);
1173 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_4x[2]);
1174 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_4x[3]);
1175 break;
1176 case 8:
1177 radeon_set_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1178 radeon_emit(cs, cm_sample_locs_8x[0]);
1179 radeon_emit(cs, cm_sample_locs_8x[4]);
1180 radeon_emit(cs, 0);
1181 radeon_emit(cs, 0);
1182 radeon_emit(cs, cm_sample_locs_8x[1]);
1183 radeon_emit(cs, cm_sample_locs_8x[5]);
1184 radeon_emit(cs, 0);
1185 radeon_emit(cs, 0);
1186 radeon_emit(cs, cm_sample_locs_8x[2]);
1187 radeon_emit(cs, cm_sample_locs_8x[6]);
1188 radeon_emit(cs, 0);
1189 radeon_emit(cs, 0);
1190 radeon_emit(cs, cm_sample_locs_8x[3]);
1191 radeon_emit(cs, cm_sample_locs_8x[7]);
1192 break;
1193 case 16:
1194 radeon_set_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
1195 radeon_emit(cs, cm_sample_locs_16x[0]);
1196 radeon_emit(cs, cm_sample_locs_16x[4]);
1197 radeon_emit(cs, cm_sample_locs_16x[8]);
1198 radeon_emit(cs, cm_sample_locs_16x[12]);
1199 radeon_emit(cs, cm_sample_locs_16x[1]);
1200 radeon_emit(cs, cm_sample_locs_16x[5]);
1201 radeon_emit(cs, cm_sample_locs_16x[9]);
1202 radeon_emit(cs, cm_sample_locs_16x[13]);
1203 radeon_emit(cs, cm_sample_locs_16x[2]);
1204 radeon_emit(cs, cm_sample_locs_16x[6]);
1205 radeon_emit(cs, cm_sample_locs_16x[10]);
1206 radeon_emit(cs, cm_sample_locs_16x[14]);
1207 radeon_emit(cs, cm_sample_locs_16x[3]);
1208 radeon_emit(cs, cm_sample_locs_16x[7]);
1209 radeon_emit(cs, cm_sample_locs_16x[11]);
1210 radeon_emit(cs, cm_sample_locs_16x[15]);
1211 break;
1212 }
1213 }
1214
1215 static void radv_cayman_get_sample_position(struct radv_device *device,
1216 unsigned sample_count,
1217 unsigned sample_index, float *out_value)
1218 {
1219 int offset, index;
1220 struct {
1221 int idx:4;
1222 } val;
1223 switch (sample_count) {
1224 case 1:
1225 default:
1226 out_value[0] = out_value[1] = 0.5;
1227 break;
1228 case 2:
1229 offset = 4 * (sample_index * 2);
1230 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1231 out_value[0] = (float)(val.idx + 8) / 16.0f;
1232 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1233 out_value[1] = (float)(val.idx + 8) / 16.0f;
1234 break;
1235 case 4:
1236 offset = 4 * (sample_index * 2);
1237 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1238 out_value[0] = (float)(val.idx + 8) / 16.0f;
1239 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1240 out_value[1] = (float)(val.idx + 8) / 16.0f;
1241 break;
1242 case 8:
1243 offset = 4 * (sample_index % 4 * 2);
1244 index = (sample_index / 4) * 4;
1245 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
1246 out_value[0] = (float)(val.idx + 8) / 16.0f;
1247 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
1248 out_value[1] = (float)(val.idx + 8) / 16.0f;
1249 break;
1250 case 16:
1251 offset = 4 * (sample_index % 4 * 2);
1252 index = (sample_index / 4) * 4;
1253 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
1254 out_value[0] = (float)(val.idx + 8) / 16.0f;
1255 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
1256 out_value[1] = (float)(val.idx + 8) / 16.0f;
1257 break;
1258 }
1259 }
1260
1261 void radv_device_init_msaa(struct radv_device *device)
1262 {
1263 int i;
1264 radv_cayman_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1265
1266 for (i = 0; i < 2; i++)
1267 radv_cayman_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1268 for (i = 0; i < 4; i++)
1269 radv_cayman_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1270 for (i = 0; i < 8; i++)
1271 radv_cayman_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1272 for (i = 0; i < 16; i++)
1273 radv_cayman_get_sample_position(device, 16, i, device->sample_locations_16x[i]);
1274 }