src/freedreno/ir3/ir3_nir.c

   1 /*
   2  * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27
  28 #include "util/debug.h"
  29 #include "util/u_math.h"
  30
  31 #include "ir3_nir.h"
  32 #include "ir3_compiler.h"
  33 #include "ir3_shader.h"
  34
  35 static const nir_shader_compiler_options options = {
  36                 .lower_fpow = true,
  37                 .lower_scmp = true,
  38                 .lower_flrp16 = true,
  39                 .lower_flrp32 = true,
  40                 .lower_flrp64 = true,
  41                 .lower_ffract = true,
  42                 .lower_fmod = true,
  43                 .lower_fdiv = true,
  44                 .lower_isign = true,
  45                 .lower_ldexp = true,
  46                 .lower_uadd_carry = true,
  47                 .lower_usub_borrow = true,
  48                 .lower_mul_high = true,
  49                 .lower_mul_2x32_64 = true,
  50                 .fuse_ffma = true,
  51                 .vertex_id_zero_based = true,
  52                 .lower_extract_byte = true,
  53                 .lower_extract_word = true,
  54                 .lower_all_io_to_elements = true,
  55                 .lower_helper_invocation = true,
  56                 .lower_bitfield_insert_to_shifts = true,
  57                 .lower_bitfield_extract_to_shifts = true,
  58                 .lower_pack_half_2x16 = true,
  59                 .lower_pack_snorm_4x8 = true,
  60                 .lower_pack_snorm_2x16 = true,
  61                 .lower_pack_unorm_4x8 = true,
  62                 .lower_pack_unorm_2x16 = true,
  63                 .lower_unpack_half_2x16 = true,
  64                 .lower_unpack_snorm_4x8 = true,
  65                 .lower_unpack_snorm_2x16 = true,
  66                 .lower_unpack_unorm_4x8 = true,
  67                 .lower_unpack_unorm_2x16 = true,
  68                 .lower_pack_split = true,
  69                 .use_interpolated_input_intrinsics = true,
  70                 .lower_rotate = true,
  71                 .lower_to_scalar = true,
  72                 .has_imul24 = true,
  73                 .lower_wpos_pntc = true,
  74
  75                 /* Only needed for the spirv_to_nir() pass done in ir3_cmdline.c
  76                  * but that should be harmless for GL since 64b is not
  77                  * supported there.
  78                  */
  79                 .lower_int64_options = (nir_lower_int64_options)~0,
  80 };
  81
  82 /* we don't want to lower vertex_id to _zero_based on newer gpus: */
  83 static const nir_shader_compiler_options options_a6xx = {
  84                 .lower_fpow = true,
  85                 .lower_scmp = true,
  86                 .lower_flrp16 = true,
  87                 .lower_flrp32 = true,
  88                 .lower_flrp64 = true,
  89                 .lower_ffract = true,
  90                 .lower_fmod = true,
  91                 .lower_fdiv = true,
  92                 .lower_isign = true,
  93                 .lower_ldexp = true,
  94                 .lower_uadd_carry = true,
  95                 .lower_usub_borrow = true,
  96                 .lower_mul_high = true,
  97                 .lower_mul_2x32_64 = true,
  98                 .fuse_ffma = true,
  99                 .vertex_id_zero_based = false,
 100                 .lower_extract_byte = true,
 101                 .lower_extract_word = true,
 102                 .lower_all_io_to_elements = true,
 103                 .lower_helper_invocation = true,
 104                 .lower_bitfield_insert_to_shifts = true,
 105                 .lower_bitfield_extract_to_shifts = true,
 106                 .lower_pack_half_2x16 = true,
 107                 .lower_pack_snorm_4x8 = true,
 108                 .lower_pack_snorm_2x16 = true,
 109                 .lower_pack_unorm_4x8 = true,
 110                 .lower_pack_unorm_2x16 = true,
 111                 .lower_unpack_half_2x16 = true,
 112                 .lower_unpack_snorm_4x8 = true,
 113                 .lower_unpack_snorm_2x16 = true,
 114                 .lower_unpack_unorm_4x8 = true,
 115                 .lower_unpack_unorm_2x16 = true,
 116                 .lower_pack_split = true,
 117                 .use_interpolated_input_intrinsics = true,
 118                 .lower_rotate = true,
 119                 .vectorize_io = true,
 120                 .lower_to_scalar = true,
 121                 .has_imul24 = true,
 122                 .max_unroll_iterations = 32,
 123                 .lower_wpos_pntc = true,
 124
 125                 /* Only needed for the spirv_to_nir() pass done in ir3_cmdline.c
 126                  * but that should be harmless for GL since 64b is not
 127                  * supported there.
 128                  */
 129                 .lower_int64_options = (nir_lower_int64_options)~0,
 130 };
 131
 132 const nir_shader_compiler_options *
 133 ir3_get_compiler_options(struct ir3_compiler *compiler)
 134 {
 135         if (compiler->gpu_id >= 600)
 136                 return &options_a6xx;
 137         return &options;
 138 }
 139
 140 #define OPT(nir, pass, ...) ({                             \
 141    bool this_progress = false;                             \
 142    NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__);      \
 143    this_progress;                                          \
 144 })
 145
 146 #define OPT_V(nir, pass, ...) NIR_PASS_V(nir, pass, ##__VA_ARGS__)
 147
 148 static void
 149 ir3_optimize_loop(nir_shader *s)
 150 {
 151         bool progress;
 152         unsigned lower_flrp =
 153                 (s->options->lower_flrp16 ? 16 : 0) |
 154                 (s->options->lower_flrp32 ? 32 : 0) |
 155                 (s->options->lower_flrp64 ? 64 : 0);
 156
 157         do {
 158                 progress = false;
 159
 160                 OPT_V(s, nir_lower_vars_to_ssa);
 161                 progress |= OPT(s, nir_opt_copy_prop_vars);
 162                 progress |= OPT(s, nir_opt_dead_write_vars);
 163                 progress |= OPT(s, nir_lower_alu_to_scalar, NULL, NULL);
 164                 progress |= OPT(s, nir_lower_phis_to_scalar);
 165
 166                 progress |= OPT(s, nir_copy_prop);
 167                 progress |= OPT(s, nir_opt_dce);
 168                 progress |= OPT(s, nir_opt_cse);
 169                 static int gcm = -1;
 170                 if (gcm == -1)
 171                         gcm = env_var_as_unsigned("GCM", 0);
 172                 if (gcm == 1)
 173                         progress |= OPT(s, nir_opt_gcm, true);
 174                 else if (gcm == 2)
 175                         progress |= OPT(s, nir_opt_gcm, false);
 176                 progress |= OPT(s, nir_opt_peephole_select, 16, true, true);
 177                 progress |= OPT(s, nir_opt_intrinsics);
 178                 progress |= OPT(s, nir_opt_algebraic);
 179                 progress |= OPT(s, nir_lower_alu);
 180                 progress |= OPT(s, nir_lower_pack);
 181                 progress |= OPT(s, nir_opt_constant_folding);
 182
 183                 if (lower_flrp != 0) {
 184                         if (OPT(s, nir_lower_flrp,
 185                                         lower_flrp,
 186                                         false /* always_precise */,
 187                                         s->options->lower_ffma)) {
 188                                 OPT(s, nir_opt_constant_folding);
 189                                 progress = true;
 190                         }
 191
 192                         /* Nothing should rematerialize any flrps, so we only
 193                          * need to do this lowering once.
 194                          */
 195                         lower_flrp = 0;
 196                 }
 197
 198                 progress |= OPT(s, nir_opt_dead_cf);
 199                 if (OPT(s, nir_opt_trivial_continues)) {
 200                         progress |= true;
 201                         /* If nir_opt_trivial_continues makes progress, then we need to clean
 202                          * things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
 203                          * to make progress.
 204                          */
 205                         OPT(s, nir_copy_prop);
 206                         OPT(s, nir_opt_dce);
 207                 }
 208                 progress |= OPT(s, nir_opt_if, false);
 209                 progress |= OPT(s, nir_opt_loop_unroll, nir_var_all);
 210                 progress |= OPT(s, nir_opt_remove_phis);
 211                 progress |= OPT(s, nir_opt_undef);
 212         } while (progress);
 213 }
 214
 215 static bool
 216 should_split_wrmask(const nir_instr *instr, const void *data)
 217 {
 218         nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
 219
 220         switch (intr->intrinsic) {
 221         case nir_intrinsic_store_ssbo:
 222         case nir_intrinsic_store_shared:
 223         case nir_intrinsic_store_global:
 224                 return true;
 225         default:
 226                 return false;
 227         }
 228 }
 229
 230 void
 231 ir3_finalize_nir(struct ir3_compiler *compiler, nir_shader *s)
 232 {
 233         struct nir_lower_tex_options tex_options = {
 234                         .lower_rect = 0,
 235                         .lower_tg4_offsets = true,
 236         };
 237
 238         if (compiler->gpu_id >= 400) {
 239                 /* a4xx seems to have *no* sam.p */
 240                 tex_options.lower_txp = ~0;  /* lower all txp */
 241         } else {
 242                 /* a3xx just needs to avoid sam.p for 3d tex */
 243                 tex_options.lower_txp = (1 << GLSL_SAMPLER_DIM_3D);
 244         }
 245
 246         if (ir3_shader_debug & IR3_DBG_DISASM) {
 247                 debug_printf("----------------------\n");
 248                 nir_print_shader(s, stdout);
 249                 debug_printf("----------------------\n");
 250         }
 251
 252         if (s->info.stage == MESA_SHADER_GEOMETRY)
 253                 NIR_PASS_V(s, ir3_nir_lower_gs);
 254
 255         NIR_PASS_V(s, nir_lower_io_arrays_to_elements_no_indirects, false);
 256
 257         NIR_PASS_V(s, nir_lower_amul, ir3_glsl_type_size);
 258
 259         OPT_V(s, nir_lower_regs_to_ssa);
 260         OPT_V(s, nir_lower_wrmasks, should_split_wrmask, s);
 261
 262         OPT_V(s, nir_lower_tex, &tex_options);
 263         OPT_V(s, nir_lower_load_const_to_scalar);
 264         if (compiler->gpu_id < 500)
 265                 OPT_V(s, ir3_nir_lower_tg4_to_tex);
 266
 267         ir3_optimize_loop(s);
 268
 269         /* do idiv lowering after first opt loop to get a chance to propagate
 270          * constants for divide by immed power-of-two:
 271          */
 272         const bool idiv_progress = OPT(s, nir_lower_idiv, nir_lower_idiv_fast);
 273
 274         if (idiv_progress)
 275                 ir3_optimize_loop(s);
 276
 277         OPT_V(s, nir_remove_dead_variables, nir_var_function_temp, NULL);
 278
 279         if (ir3_shader_debug & IR3_DBG_DISASM) {
 280                 debug_printf("----------------------\n");
 281                 nir_print_shader(s, stdout);
 282                 debug_printf("----------------------\n");
 283         }
 284
 285         nir_sweep(s);
 286 }
 287
 288 /**
 289  * Late passes that need to be done after pscreen->finalize_nir()
 290  */
 291 void
 292 ir3_nir_post_finalize(struct ir3_compiler *compiler, nir_shader *s)
 293 {
 294         NIR_PASS_V(s, nir_lower_io, nir_var_shader_in | nir_var_shader_out,
 295                            ir3_glsl_type_size, (nir_lower_io_options)0);
 296
 297         if (s->info.stage == MESA_SHADER_FRAGMENT) {
 298                 /* NOTE: lower load_barycentric_at_sample first, since it
 299                  * produces load_barycentric_at_offset:
 300                  */
 301                 NIR_PASS_V(s, ir3_nir_lower_load_barycentric_at_sample);
 302                 NIR_PASS_V(s, ir3_nir_lower_load_barycentric_at_offset);
 303                 NIR_PASS_V(s, ir3_nir_move_varying_inputs);
 304                 NIR_PASS_V(s, nir_lower_fb_read);
 305         }
 306
 307         if (compiler->gpu_id >= 600 &&
 308                         s->info.stage == MESA_SHADER_FRAGMENT &&
 309                         !(ir3_shader_debug & IR3_DBG_NOFP16)) {
 310                 NIR_PASS_V(s, nir_lower_mediump_outputs);
 311         }
 312
 313         /* we cannot ensure that ir3_finalize_nir() is only called once, so
 314          * we also need to do trig workarounds here:
 315          */
 316         OPT_V(s, ir3_nir_apply_trig_workarounds);
 317
 318         ir3_optimize_loop(s);
 319 }
 320
 321 static bool
 322 ir3_nir_lower_layer_id(nir_shader *nir)
 323 {
 324         unsigned layer_id_loc = ~0;
 325         nir_foreach_shader_in_variable(var, nir) {
 326                 if (var->data.location == VARYING_SLOT_LAYER) {
 327                         layer_id_loc = var->data.driver_location;
 328                         break;
 329                 }
 330         }
 331
 332         assert(layer_id_loc != ~0);
 333
 334         bool progress = false;
 335         nir_builder b;
 336
 337         nir_foreach_function(func, nir) {
 338                 nir_builder_init(&b, func->impl);
 339
 340                 nir_foreach_block(block, func->impl) {
 341                         nir_foreach_instr_safe(instr, block) {
 342                                 if (instr->type != nir_instr_type_intrinsic)
 343                                         continue;
 344
 345                                 nir_intrinsic_instr *intrin =
 346                                         nir_instr_as_intrinsic(instr);
 347
 348                                 if (intrin->intrinsic != nir_intrinsic_load_input)
 349                                         continue;
 350
 351                                 unsigned base = nir_intrinsic_base(intrin);
 352                                 if (base != layer_id_loc)
 353                                         continue;
 354
 355                                 b.cursor = nir_before_instr(&intrin->instr);
 356                                 nir_ssa_def *zero = nir_imm_int(&b, 0);
 357                                 nir_ssa_def_rewrite_uses(&intrin->dest.ssa,
 358                                                                                  nir_src_for_ssa(zero));
 359                                 nir_instr_remove(&intrin->instr);
 360                                 progress = true;
 361                         }
 362                 }
 363
 364                 if (progress) {
 365                         nir_metadata_preserve(func->impl,
 366                                                                   nir_metadata_block_index |
 367                                                                   nir_metadata_dominance);
 368                 } else {
 369                         nir_metadata_preserve(func->impl, nir_metadata_all);
 370                 }
 371         }
 372
 373         return progress;
 374 }
 375
 376 void
 377 ir3_nir_lower_variant(struct ir3_shader_variant *so, nir_shader *s)
 378 {
 379         if (ir3_shader_debug & IR3_DBG_DISASM) {
 380                 debug_printf("----------------------\n");
 381                 nir_print_shader(s, stdout);
 382                 debug_printf("----------------------\n");
 383         }
 384
 385         bool progress = false;
 386
 387         if (so->key.has_gs || so->key.tessellation) {
 388                 switch (so->shader->type) {
 389                 case MESA_SHADER_VERTEX:
 390                         NIR_PASS_V(s, ir3_nir_lower_to_explicit_output, so, so->key.tessellation);
 391                         progress = true;
 392                         break;
 393                 case MESA_SHADER_TESS_CTRL:
 394                         NIR_PASS_V(s, ir3_nir_lower_tess_ctrl, so, so->key.tessellation);
 395                         NIR_PASS_V(s, ir3_nir_lower_to_explicit_input, so->shader->compiler);
 396                         progress = true;
 397                         break;
 398                 case MESA_SHADER_TESS_EVAL:
 399                         NIR_PASS_V(s, ir3_nir_lower_tess_eval, so->key.tessellation);
 400                         if (so->key.has_gs)
 401                                 NIR_PASS_V(s, ir3_nir_lower_to_explicit_output, so, so->key.tessellation);
 402                         progress = true;
 403                         break;
 404                 case MESA_SHADER_GEOMETRY:
 405                         NIR_PASS_V(s, ir3_nir_lower_to_explicit_input, so->shader->compiler);
 406                         progress = true;
 407                         break;
 408                 default:
 409                         break;
 410                 }
 411         }
 412
 413         if (s->info.stage == MESA_SHADER_VERTEX) {
 414                 if (so->key.ucp_enables)
 415                         progress |= OPT(s, nir_lower_clip_vs, so->key.ucp_enables, false, false, NULL);
 416                 if (so->key.vclamp_color)
 417                         progress |= OPT(s, nir_lower_clamp_color_outputs);
 418         } else if (s->info.stage == MESA_SHADER_FRAGMENT) {
 419                 if (so->key.ucp_enables)
 420                         progress |= OPT(s, nir_lower_clip_fs, so->key.ucp_enables, false);
 421                 if (so->key.fclamp_color)
 422                         progress |= OPT(s, nir_lower_clamp_color_outputs);
 423                 if (so->key.layer_zero && (s->info.inputs_read & VARYING_BIT_LAYER))
 424                         progress |= OPT(s, ir3_nir_lower_layer_id);
 425         }
 426         if (so->key.color_two_side) {
 427                 OPT_V(s, nir_lower_two_sided_color, true);
 428                 progress = true;
 429         }
 430
 431         struct nir_lower_tex_options tex_options = { };
 432
 433         switch (so->shader->type) {
 434         case MESA_SHADER_FRAGMENT:
 435                 tex_options.saturate_s = so->key.fsaturate_s;
 436                 tex_options.saturate_t = so->key.fsaturate_t;
 437                 tex_options.saturate_r = so->key.fsaturate_r;
 438                 break;
 439         case MESA_SHADER_VERTEX:
 440                 tex_options.saturate_s = so->key.vsaturate_s;
 441                 tex_options.saturate_t = so->key.vsaturate_t;
 442                 tex_options.saturate_r = so->key.vsaturate_r;
 443                 break;
 444         default:
 445                 /* TODO */
 446                 break;
 447         }
 448
 449         if (tex_options.saturate_s || tex_options.saturate_t ||
 450                 tex_options.saturate_r) {
 451                 progress |= OPT(s, nir_lower_tex, &tex_options);
 452         }
 453
 454         if (!so->binning_pass)
 455                 OPT_V(s, ir3_nir_analyze_ubo_ranges, so);
 456
 457         progress |= OPT(s, ir3_nir_lower_ubo_loads, so);
 458
 459         /* UBO offset lowering has to come after we've decided what will
 460          * be left as load_ubo
 461          */
 462         OPT_V(s, ir3_nir_lower_io_offsets, so->shader->compiler->gpu_id);
 463
 464         if (progress)
 465                 ir3_optimize_loop(s);
 466
 467         /* Do late algebraic optimization to turn add(a, neg(b)) back into
 468         * subs, then the mandatory cleanup after algebraic.  Note that it may
 469         * produce fnegs, and if so then we need to keep running to squash
 470         * fneg(fneg(a)).
 471         */
 472         bool more_late_algebraic = true;
 473         while (more_late_algebraic) {
 474                 more_late_algebraic = OPT(s, nir_opt_algebraic_late);
 475                 OPT_V(s, nir_opt_constant_folding);
 476                 OPT_V(s, nir_copy_prop);
 477                 OPT_V(s, nir_opt_dce);
 478                 OPT_V(s, nir_opt_cse);
 479         }
 480
 481         OPT_V(s, nir_opt_sink, nir_move_const_undef);
 482
 483         if (ir3_shader_debug & IR3_DBG_DISASM) {
 484                 debug_printf("----------------------\n");
 485                 nir_print_shader(s, stdout);
 486                 debug_printf("----------------------\n");
 487         }
 488
 489         nir_sweep(s);
 490
 491         /* Binning pass variants re-use  the const_state of the corresponding
 492          * draw pass shader, so that same const emit can be re-used for both
 493          * passes:
 494          */
 495         if (!so->binning_pass)
 496                 ir3_setup_const_state(s, so, ir3_const_state(so));
 497 }
 498
 499 static void
 500 ir3_nir_scan_driver_consts(nir_shader *shader,
 501                 struct ir3_const_state *layout)
 502 {
 503         nir_foreach_function (function, shader) {
 504                 if (!function->impl)
 505                         continue;
 506
 507                 nir_foreach_block (block, function->impl) {
 508                         nir_foreach_instr (instr, block) {
 509                                 if (instr->type != nir_instr_type_intrinsic)
 510                                         continue;
 511
 512                                 nir_intrinsic_instr *intr =
 513                                         nir_instr_as_intrinsic(instr);
 514                                 unsigned idx;
 515
 516                                 switch (intr->intrinsic) {
 517                                 case nir_intrinsic_get_buffer_size:
 518                                         if (ir3_bindless_resource(intr->src[0]))
 519                                                 break;
 520                                         idx = nir_src_as_uint(intr->src[0]);
 521                                         if (layout->ssbo_size.mask & (1 << idx))
 522                                                 break;
 523                                         layout->ssbo_size.mask |= (1 << idx);
 524                                         layout->ssbo_size.off[idx] =
 525                                                 layout->ssbo_size.count;
 526                                         layout->ssbo_size.count += 1; /* one const per */
 527                                         break;
 528                                 case nir_intrinsic_image_atomic_add:
 529                                 case nir_intrinsic_image_atomic_imin:
 530                                 case nir_intrinsic_image_atomic_umin:
 531                                 case nir_intrinsic_image_atomic_imax:
 532                                 case nir_intrinsic_image_atomic_umax:
 533                                 case nir_intrinsic_image_atomic_and:
 534                                 case nir_intrinsic_image_atomic_or:
 535                                 case nir_intrinsic_image_atomic_xor:
 536                                 case nir_intrinsic_image_atomic_exchange:
 537                                 case nir_intrinsic_image_atomic_comp_swap:
 538                                 case nir_intrinsic_image_store:
 539                                 case nir_intrinsic_image_size:
 540                                         idx = nir_src_as_uint(intr->src[0]);
 541                                         if (layout->image_dims.mask & (1 << idx))
 542                                                 break;
 543                                         layout->image_dims.mask |= (1 << idx);
 544                                         layout->image_dims.off[idx] =
 545                                                 layout->image_dims.count;
 546                                         layout->image_dims.count += 3; /* three const per */
 547                                         break;
 548                                 case nir_intrinsic_load_base_vertex:
 549                                 case nir_intrinsic_load_first_vertex:
 550                                         layout->num_driver_params =
 551                                                 MAX2(layout->num_driver_params, IR3_DP_VTXID_BASE + 1);
 552                                         break;
 553                                 case nir_intrinsic_load_base_instance:
 554                                         layout->num_driver_params =
 555                                                 MAX2(layout->num_driver_params, IR3_DP_INSTID_BASE + 1);
 556                                         break;
 557                                 case nir_intrinsic_load_user_clip_plane:
 558                                         idx = nir_intrinsic_ucp_id(intr);
 559                                         layout->num_driver_params =
 560                                                 MAX2(layout->num_driver_params, IR3_DP_UCP0_X + (idx + 1) * 4);
 561                                         break;
 562                                 case nir_intrinsic_load_num_work_groups:
 563                                         layout->num_driver_params =
 564                                                 MAX2(layout->num_driver_params, IR3_DP_NUM_WORK_GROUPS_Z + 1);
 565                                         break;
 566                                 case nir_intrinsic_load_local_group_size:
 567                                         layout->num_driver_params =
 568                                                 MAX2(layout->num_driver_params, IR3_DP_LOCAL_GROUP_SIZE_Z + 1);
 569                                         break;
 570                                 default:
 571                                         break;
 572                                 }
 573                         }
 574                 }
 575         }
 576 }
 577
 578 /* Sets up the variant-dependent constant state for the ir3_shader.  Note
 579  * that it is also used from ir3_nir_analyze_ubo_ranges() to figure out the
 580  * maximum number of driver params that would eventually be used, to leave
 581  * space for this function to allocate the driver params.
 582  */
 583 void
 584 ir3_setup_const_state(nir_shader *nir, struct ir3_shader_variant *v,
 585                 struct ir3_const_state *const_state)
 586 {
 587         struct ir3_compiler *compiler = v->shader->compiler;
 588
 589         memset(&const_state->offsets, ~0, sizeof(const_state->offsets));
 590
 591         ir3_nir_scan_driver_consts(nir, const_state);
 592
 593         if ((compiler->gpu_id < 500) &&
 594                         (v->shader->stream_output.num_outputs > 0)) {
 595                 const_state->num_driver_params =
 596                         MAX2(const_state->num_driver_params, IR3_DP_VTXCNT_MAX + 1);
 597         }
 598
 599         const_state->num_ubos = nir->info.num_ubos;
 600
 601         /* num_driver_params is scalar, align to vec4: */
 602         const_state->num_driver_params = align(const_state->num_driver_params, 4);
 603
 604         debug_assert((const_state->ubo_state.size % 16) == 0);
 605         unsigned constoff = const_state->ubo_state.size / 16;
 606         unsigned ptrsz = ir3_pointer_size(compiler);
 607
 608         if (const_state->num_ubos > 0) {
 609                 const_state->offsets.ubo = constoff;
 610                 constoff += align(const_state->num_ubos * ptrsz, 4) / 4;
 611         }
 612
 613         if (const_state->ssbo_size.count > 0) {
 614                 unsigned cnt = const_state->ssbo_size.count;
 615                 const_state->offsets.ssbo_sizes = constoff;
 616                 constoff += align(cnt, 4) / 4;
 617         }
 618
 619         if (const_state->image_dims.count > 0) {
 620                 unsigned cnt = const_state->image_dims.count;
 621                 const_state->offsets.image_dims = constoff;
 622                 constoff += align(cnt, 4) / 4;
 623         }
 624
 625         if (const_state->num_driver_params > 0) {
 626                 /* offset cannot be 0 for vs params loaded by CP_DRAW_INDIRECT_MULTI */
 627                 if (v->type == MESA_SHADER_VERTEX && compiler->gpu_id >= 600)
 628                         constoff = MAX2(constoff, 1);
 629                 const_state->offsets.driver_param = constoff;
 630         }
 631         constoff += const_state->num_driver_params / 4;
 632
 633         if ((v->type == MESA_SHADER_VERTEX) &&
 634                         (compiler->gpu_id < 500) &&
 635                         v->shader->stream_output.num_outputs > 0) {
 636                 const_state->offsets.tfbo = constoff;
 637                 constoff += align(IR3_MAX_SO_BUFFERS * ptrsz, 4) / 4;
 638         }
 639
 640         switch (v->type) {
 641         case MESA_SHADER_VERTEX:
 642                 const_state->offsets.primitive_param = constoff;
 643                 constoff += 1;
 644                 break;
 645         case MESA_SHADER_TESS_CTRL:
 646         case MESA_SHADER_TESS_EVAL:
 647                 constoff = align(constoff - 1, 4) + 3;
 648                 const_state->offsets.primitive_param = constoff;
 649                 const_state->offsets.primitive_map = constoff + 5;
 650                 constoff += 5 + DIV_ROUND_UP(nir->num_inputs, 4);
 651                 break;
 652         case MESA_SHADER_GEOMETRY:
 653                 const_state->offsets.primitive_param = constoff;
 654                 const_state->offsets.primitive_map = constoff + 1;
 655                 constoff += 1 + DIV_ROUND_UP(nir->num_inputs, 4);
 656                 break;
 657         default:
 658                 break;
 659         }
 660
 661         const_state->offsets.immediate = constoff;
 662
 663         assert(constoff <= ir3_max_const(v));
 664 }