src/freedreno/ir3/ir3_nir.c

   1 /*
   2  * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27
  28 #include "util/debug.h"
  29 #include "util/u_math.h"
  30
  31 #include "ir3_nir.h"
  32 #include "ir3_compiler.h"
  33 #include "ir3_shader.h"
  34
  35 static const nir_shader_compiler_options options = {
  36                 .lower_fpow = true,
  37                 .lower_scmp = true,
  38                 .lower_flrp16 = true,
  39                 .lower_flrp32 = true,
  40                 .lower_flrp64 = true,
  41                 .lower_ffract = true,
  42                 .lower_fmod = true,
  43                 .lower_fdiv = true,
  44                 .lower_isign = true,
  45                 .lower_ldexp = true,
  46                 .lower_uadd_carry = true,
  47                 .lower_usub_borrow = true,
  48                 .lower_mul_high = true,
  49                 .lower_mul_2x32_64 = true,
  50                 .fuse_ffma = true,
  51                 .vertex_id_zero_based = true,
  52                 .lower_extract_byte = true,
  53                 .lower_extract_word = true,
  54                 .lower_all_io_to_elements = true,
  55                 .lower_helper_invocation = true,
  56                 .lower_bitfield_insert_to_shifts = true,
  57                 .lower_bitfield_extract_to_shifts = true,
  58                 .lower_pack_half_2x16 = true,
  59                 .lower_pack_snorm_4x8 = true,
  60                 .lower_pack_snorm_2x16 = true,
  61                 .lower_pack_unorm_4x8 = true,
  62                 .lower_pack_unorm_2x16 = true,
  63                 .lower_unpack_half_2x16 = true,
  64                 .lower_unpack_snorm_4x8 = true,
  65                 .lower_unpack_snorm_2x16 = true,
  66                 .lower_unpack_unorm_4x8 = true,
  67                 .lower_unpack_unorm_2x16 = true,
  68                 .lower_pack_split = true,
  69                 .use_interpolated_input_intrinsics = true,
  70                 .lower_rotate = true,
  71                 .lower_to_scalar = true,
  72                 .has_imul24 = true,
  73                 .lower_wpos_pntc = true,
  74 };
  75
  76 /* we don't want to lower vertex_id to _zero_based on newer gpus: */
  77 static const nir_shader_compiler_options options_a6xx = {
  78                 .lower_fpow = true,
  79                 .lower_scmp = true,
  80                 .lower_flrp16 = true,
  81                 .lower_flrp32 = true,
  82                 .lower_flrp64 = true,
  83                 .lower_ffract = true,
  84                 .lower_fmod = true,
  85                 .lower_fdiv = true,
  86                 .lower_isign = true,
  87                 .lower_ldexp = true,
  88                 .lower_uadd_carry = true,
  89                 .lower_usub_borrow = true,
  90                 .lower_mul_high = true,
  91                 .lower_mul_2x32_64 = true,
  92                 .fuse_ffma = true,
  93                 .vertex_id_zero_based = false,
  94                 .lower_extract_byte = true,
  95                 .lower_extract_word = true,
  96                 .lower_all_io_to_elements = true,
  97                 .lower_helper_invocation = true,
  98                 .lower_bitfield_insert_to_shifts = true,
  99                 .lower_bitfield_extract_to_shifts = true,
 100                 .lower_pack_half_2x16 = true,
 101                 .lower_pack_snorm_4x8 = true,
 102                 .lower_pack_snorm_2x16 = true,
 103                 .lower_pack_unorm_4x8 = true,
 104                 .lower_pack_unorm_2x16 = true,
 105                 .lower_unpack_half_2x16 = true,
 106                 .lower_unpack_snorm_4x8 = true,
 107                 .lower_unpack_snorm_2x16 = true,
 108                 .lower_unpack_unorm_4x8 = true,
 109                 .lower_unpack_unorm_2x16 = true,
 110                 .lower_pack_split = true,
 111                 .use_interpolated_input_intrinsics = true,
 112                 .lower_rotate = true,
 113                 .vectorize_io = true,
 114                 .lower_to_scalar = true,
 115                 .has_imul24 = true,
 116                 .max_unroll_iterations = 32,
 117                 .lower_wpos_pntc = true,
 118 };
 119
 120 const nir_shader_compiler_options *
 121 ir3_get_compiler_options(struct ir3_compiler *compiler)
 122 {
 123         if (compiler->gpu_id >= 600)
 124                 return &options_a6xx;
 125         return &options;
 126 }
 127
 128 #define OPT(nir, pass, ...) ({                             \
 129    bool this_progress = false;                             \
 130    NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__);      \
 131    this_progress;                                          \
 132 })
 133
 134 #define OPT_V(nir, pass, ...) NIR_PASS_V(nir, pass, ##__VA_ARGS__)
 135
 136 static void
 137 ir3_optimize_loop(nir_shader *s)
 138 {
 139         bool progress;
 140         unsigned lower_flrp =
 141                 (s->options->lower_flrp16 ? 16 : 0) |
 142                 (s->options->lower_flrp32 ? 32 : 0) |
 143                 (s->options->lower_flrp64 ? 64 : 0);
 144
 145         do {
 146                 progress = false;
 147
 148                 OPT_V(s, nir_lower_vars_to_ssa);
 149                 progress |= OPT(s, nir_opt_copy_prop_vars);
 150                 progress |= OPT(s, nir_opt_dead_write_vars);
 151                 progress |= OPT(s, nir_lower_alu_to_scalar, NULL, NULL);
 152                 progress |= OPT(s, nir_lower_phis_to_scalar);
 153
 154                 progress |= OPT(s, nir_copy_prop);
 155                 progress |= OPT(s, nir_opt_dce);
 156                 progress |= OPT(s, nir_opt_cse);
 157                 static int gcm = -1;
 158                 if (gcm == -1)
 159                         gcm = env_var_as_unsigned("GCM", 0);
 160                 if (gcm == 1)
 161                         progress |= OPT(s, nir_opt_gcm, true);
 162                 else if (gcm == 2)
 163                         progress |= OPT(s, nir_opt_gcm, false);
 164                 progress |= OPT(s, nir_opt_peephole_select, 16, true, true);
 165                 progress |= OPT(s, nir_opt_intrinsics);
 166                 progress |= OPT(s, nir_opt_algebraic);
 167                 progress |= OPT(s, nir_lower_alu);
 168                 progress |= OPT(s, nir_lower_pack);
 169                 progress |= OPT(s, nir_opt_constant_folding);
 170
 171                 if (lower_flrp != 0) {
 172                         if (OPT(s, nir_lower_flrp,
 173                                         lower_flrp,
 174                                         false /* always_precise */,
 175                                         s->options->lower_ffma)) {
 176                                 OPT(s, nir_opt_constant_folding);
 177                                 progress = true;
 178                         }
 179
 180                         /* Nothing should rematerialize any flrps, so we only
 181                          * need to do this lowering once.
 182                          */
 183                         lower_flrp = 0;
 184                 }
 185
 186                 progress |= OPT(s, nir_opt_dead_cf);
 187                 if (OPT(s, nir_opt_trivial_continues)) {
 188                         progress |= true;
 189                         /* If nir_opt_trivial_continues makes progress, then we need to clean
 190                          * things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
 191                          * to make progress.
 192                          */
 193                         OPT(s, nir_copy_prop);
 194                         OPT(s, nir_opt_dce);
 195                 }
 196                 progress |= OPT(s, nir_opt_if, false);
 197                 progress |= OPT(s, nir_opt_remove_phis);
 198                 progress |= OPT(s, nir_opt_undef);
 199         } while (progress);
 200 }
 201
 202 static bool
 203 should_split_wrmask(const nir_instr *instr, const void *data)
 204 {
 205         nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
 206
 207         switch (intr->intrinsic) {
 208         case nir_intrinsic_store_ssbo:
 209         case nir_intrinsic_store_shared:
 210         case nir_intrinsic_store_global:
 211                 return true;
 212         default:
 213                 return false;
 214         }
 215 }
 216
 217 void
 218 ir3_finalize_nir(struct ir3_compiler *compiler, nir_shader *s)
 219 {
 220         struct nir_lower_tex_options tex_options = {
 221                         .lower_rect = 0,
 222                         .lower_tg4_offsets = true,
 223         };
 224
 225         if (compiler->gpu_id >= 400) {
 226                 /* a4xx seems to have *no* sam.p */
 227                 tex_options.lower_txp = ~0;  /* lower all txp */
 228         } else {
 229                 /* a3xx just needs to avoid sam.p for 3d tex */
 230                 tex_options.lower_txp = (1 << GLSL_SAMPLER_DIM_3D);
 231         }
 232
 233         if (ir3_shader_debug & IR3_DBG_DISASM) {
 234                 debug_printf("----------------------\n");
 235                 nir_print_shader(s, stdout);
 236                 debug_printf("----------------------\n");
 237         }
 238
 239         if (s->info.stage == MESA_SHADER_GEOMETRY)
 240                 NIR_PASS_V(s, ir3_nir_lower_gs);
 241
 242         NIR_PASS_V(s, nir_lower_io_arrays_to_elements_no_indirects, false);
 243
 244         NIR_PASS_V(s, nir_lower_amul, ir3_glsl_type_size);
 245
 246         OPT_V(s, nir_lower_regs_to_ssa);
 247         OPT_V(s, nir_lower_wrmasks, should_split_wrmask, s);
 248
 249         OPT_V(s, nir_lower_tex, &tex_options);
 250         OPT_V(s, nir_lower_load_const_to_scalar);
 251         if (compiler->gpu_id < 500)
 252                 OPT_V(s, ir3_nir_lower_tg4_to_tex);
 253
 254         ir3_optimize_loop(s);
 255
 256         /* do idiv lowering after first opt loop to get a chance to propagate
 257          * constants for divide by immed power-of-two:
 258          */
 259         const bool idiv_progress = OPT(s, nir_lower_idiv, nir_lower_idiv_fast);
 260
 261         if (idiv_progress)
 262                 ir3_optimize_loop(s);
 263
 264         OPT_V(s, nir_remove_dead_variables, nir_var_function_temp, NULL);
 265
 266         if (ir3_shader_debug & IR3_DBG_DISASM) {
 267                 debug_printf("----------------------\n");
 268                 nir_print_shader(s, stdout);
 269                 debug_printf("----------------------\n");
 270         }
 271
 272         nir_sweep(s);
 273 }
 274
 275 /**
 276  * Late passes that need to be done after pscreen->finalize_nir()
 277  */
 278 void
 279 ir3_nir_post_finalize(struct ir3_compiler *compiler, nir_shader *s)
 280 {
 281         NIR_PASS_V(s, nir_lower_io, nir_var_shader_in | nir_var_shader_out,
 282                            ir3_glsl_type_size, (nir_lower_io_options)0);
 283
 284         if (s->info.stage == MESA_SHADER_FRAGMENT) {
 285                 /* NOTE: lower load_barycentric_at_sample first, since it
 286                  * produces load_barycentric_at_offset:
 287                  */
 288                 NIR_PASS_V(s, ir3_nir_lower_load_barycentric_at_sample);
 289                 NIR_PASS_V(s, ir3_nir_lower_load_barycentric_at_offset);
 290                 NIR_PASS_V(s, ir3_nir_move_varying_inputs);
 291                 NIR_PASS_V(s, nir_lower_fb_read);
 292         }
 293
 294         if (compiler->gpu_id >= 600 &&
 295                         s->info.stage == MESA_SHADER_FRAGMENT &&
 296                         !(ir3_shader_debug & IR3_DBG_NOFP16)) {
 297                 NIR_PASS_V(s, nir_lower_mediump_outputs);
 298         }
 299
 300         /* we cannot ensure that ir3_finalize_nir() is only called once, so
 301          * we also need to do trig workarounds here:
 302          */
 303         OPT_V(s, ir3_nir_apply_trig_workarounds);
 304
 305         ir3_optimize_loop(s);
 306 }
 307
 308 void
 309 ir3_nir_lower_variant(struct ir3_shader_variant *so, nir_shader *s)
 310 {
 311         if (ir3_shader_debug & IR3_DBG_DISASM) {
 312                 debug_printf("----------------------\n");
 313                 nir_print_shader(s, stdout);
 314                 debug_printf("----------------------\n");
 315         }
 316
 317         bool progress = false;
 318
 319         if (so->key.has_gs || so->key.tessellation) {
 320                 switch (so->shader->type) {
 321                 case MESA_SHADER_VERTEX:
 322                         NIR_PASS_V(s, ir3_nir_lower_to_explicit_output, so, so->key.tessellation);
 323                         progress = true;
 324                         break;
 325                 case MESA_SHADER_TESS_CTRL:
 326                         NIR_PASS_V(s, ir3_nir_lower_tess_ctrl, so, so->key.tessellation);
 327                         NIR_PASS_V(s, ir3_nir_lower_to_explicit_input);
 328                         progress = true;
 329                         break;
 330                 case MESA_SHADER_TESS_EVAL:
 331                         NIR_PASS_V(s, ir3_nir_lower_tess_eval, so->key.tessellation);
 332                         if (so->key.has_gs)
 333                                 NIR_PASS_V(s, ir3_nir_lower_to_explicit_output, so, so->key.tessellation);
 334                         progress = true;
 335                         break;
 336                 case MESA_SHADER_GEOMETRY:
 337                         NIR_PASS_V(s, ir3_nir_lower_to_explicit_input);
 338                         progress = true;
 339                         break;
 340                 default:
 341                         break;
 342                 }
 343         }
 344
 345         if (s->info.stage == MESA_SHADER_VERTEX) {
 346                 if (so->key.ucp_enables)
 347                         progress |= OPT(s, nir_lower_clip_vs, so->key.ucp_enables, false, false, NULL);
 348                 if (so->key.vclamp_color)
 349                         progress |= OPT(s, nir_lower_clamp_color_outputs);
 350         } else if (s->info.stage == MESA_SHADER_FRAGMENT) {
 351                 if (so->key.ucp_enables)
 352                         progress |= OPT(s, nir_lower_clip_fs, so->key.ucp_enables, false);
 353                 if (so->key.fclamp_color)
 354                         progress |= OPT(s, nir_lower_clamp_color_outputs);
 355         }
 356         if (so->key.color_two_side) {
 357                 OPT_V(s, nir_lower_two_sided_color);
 358                 progress = true;
 359         }
 360
 361         struct nir_lower_tex_options tex_options = { };
 362
 363         switch (so->shader->type) {
 364         case MESA_SHADER_FRAGMENT:
 365                 tex_options.saturate_s = so->key.fsaturate_s;
 366                 tex_options.saturate_t = so->key.fsaturate_t;
 367                 tex_options.saturate_r = so->key.fsaturate_r;
 368                 break;
 369         case MESA_SHADER_VERTEX:
 370                 tex_options.saturate_s = so->key.vsaturate_s;
 371                 tex_options.saturate_t = so->key.vsaturate_t;
 372                 tex_options.saturate_r = so->key.vsaturate_r;
 373                 break;
 374         default:
 375                 /* TODO */
 376                 break;
 377         }
 378
 379         if (tex_options.saturate_s || tex_options.saturate_t ||
 380                 tex_options.saturate_r) {
 381                 progress |= OPT(s, nir_lower_tex, &tex_options);
 382         }
 383
 384         if (!so->binning_pass)
 385                 OPT_V(s, ir3_nir_analyze_ubo_ranges, so);
 386
 387         progress |= OPT(s, ir3_nir_lower_ubo_loads, so);
 388
 389         /* UBO offset lowering has to come after we've decided what will
 390          * be left as load_ubo
 391          */
 392         OPT_V(s, ir3_nir_lower_io_offsets, so->shader->compiler->gpu_id);
 393
 394         if (progress)
 395                 ir3_optimize_loop(s);
 396
 397         /* Do late algebraic optimization to turn add(a, neg(b)) back into
 398         * subs, then the mandatory cleanup after algebraic.  Note that it may
 399         * produce fnegs, and if so then we need to keep running to squash
 400         * fneg(fneg(a)).
 401         */
 402         bool more_late_algebraic = true;
 403         while (more_late_algebraic) {
 404                 more_late_algebraic = OPT(s, nir_opt_algebraic_late);
 405                 OPT_V(s, nir_opt_constant_folding);
 406                 OPT_V(s, nir_copy_prop);
 407                 OPT_V(s, nir_opt_dce);
 408                 OPT_V(s, nir_opt_cse);
 409         }
 410
 411         OPT_V(s, nir_opt_sink, nir_move_const_undef);
 412
 413         if (ir3_shader_debug & IR3_DBG_DISASM) {
 414                 debug_printf("----------------------\n");
 415                 nir_print_shader(s, stdout);
 416                 debug_printf("----------------------\n");
 417         }
 418
 419         nir_sweep(s);
 420
 421         /* Binning pass variants re-use  the const_state of the corresponding
 422          * draw pass shader, so that same const emit can be re-used for both
 423          * passes:
 424          */
 425         if (!so->binning_pass)
 426                 ir3_setup_const_state(s, so, ir3_const_state(so));
 427 }
 428
 429 static void
 430 ir3_nir_scan_driver_consts(nir_shader *shader,
 431                 struct ir3_const_state *layout)
 432 {
 433         nir_foreach_function (function, shader) {
 434                 if (!function->impl)
 435                         continue;
 436
 437                 nir_foreach_block (block, function->impl) {
 438                         nir_foreach_instr (instr, block) {
 439                                 if (instr->type != nir_instr_type_intrinsic)
 440                                         continue;
 441
 442                                 nir_intrinsic_instr *intr =
 443                                         nir_instr_as_intrinsic(instr);
 444                                 unsigned idx;
 445
 446                                 switch (intr->intrinsic) {
 447                                 case nir_intrinsic_get_buffer_size:
 448                                         idx = nir_src_as_uint(intr->src[0]);
 449                                         if (layout->ssbo_size.mask & (1 << idx))
 450                                                 break;
 451                                         layout->ssbo_size.mask |= (1 << idx);
 452                                         layout->ssbo_size.off[idx] =
 453                                                 layout->ssbo_size.count;
 454                                         layout->ssbo_size.count += 1; /* one const per */
 455                                         break;
 456                                 case nir_intrinsic_image_atomic_add:
 457                                 case nir_intrinsic_image_atomic_imin:
 458                                 case nir_intrinsic_image_atomic_umin:
 459                                 case nir_intrinsic_image_atomic_imax:
 460                                 case nir_intrinsic_image_atomic_umax:
 461                                 case nir_intrinsic_image_atomic_and:
 462                                 case nir_intrinsic_image_atomic_or:
 463                                 case nir_intrinsic_image_atomic_xor:
 464                                 case nir_intrinsic_image_atomic_exchange:
 465                                 case nir_intrinsic_image_atomic_comp_swap:
 466                                 case nir_intrinsic_image_store:
 467                                 case nir_intrinsic_image_size:
 468                                         idx = nir_src_as_uint(intr->src[0]);
 469                                         if (layout->image_dims.mask & (1 << idx))
 470                                                 break;
 471                                         layout->image_dims.mask |= (1 << idx);
 472                                         layout->image_dims.off[idx] =
 473                                                 layout->image_dims.count;
 474                                         layout->image_dims.count += 3; /* three const per */
 475                                         break;
 476                                 case nir_intrinsic_load_base_vertex:
 477                                 case nir_intrinsic_load_first_vertex:
 478                                         layout->num_driver_params =
 479                                                 MAX2(layout->num_driver_params, IR3_DP_VTXID_BASE + 1);
 480                                         break;
 481                                 case nir_intrinsic_load_base_instance:
 482                                         layout->num_driver_params =
 483                                                 MAX2(layout->num_driver_params, IR3_DP_INSTID_BASE + 1);
 484                                         break;
 485                                 case nir_intrinsic_load_user_clip_plane:
 486                                         idx = nir_intrinsic_ucp_id(intr);
 487                                         layout->num_driver_params =
 488                                                 MAX2(layout->num_driver_params, IR3_DP_UCP0_X + (idx + 1) * 4);
 489                                         break;
 490                                 case nir_intrinsic_load_num_work_groups:
 491                                         layout->num_driver_params =
 492                                                 MAX2(layout->num_driver_params, IR3_DP_NUM_WORK_GROUPS_Z + 1);
 493                                         break;
 494                                 case nir_intrinsic_load_local_group_size:
 495                                         layout->num_driver_params =
 496                                                 MAX2(layout->num_driver_params, IR3_DP_LOCAL_GROUP_SIZE_Z + 1);
 497                                         break;
 498                                 default:
 499                                         break;
 500                                 }
 501                         }
 502                 }
 503         }
 504 }
 505
 506 /* Sets up the variant-dependent constant state for the ir3_shader.  Note
 507  * that it is also used from ir3_nir_analyze_ubo_ranges() to figure out the
 508  * maximum number of driver params that would eventually be used, to leave
 509  * space for this function to allocate the driver params.
 510  */
 511 void
 512 ir3_setup_const_state(nir_shader *nir, struct ir3_shader_variant *v,
 513                 struct ir3_const_state *const_state)
 514 {
 515         struct ir3_compiler *compiler = v->shader->compiler;
 516
 517         memset(&const_state->offsets, ~0, sizeof(const_state->offsets));
 518
 519         ir3_nir_scan_driver_consts(nir, const_state);
 520
 521         if ((compiler->gpu_id < 500) &&
 522                         (v->shader->stream_output.num_outputs > 0)) {
 523                 const_state->num_driver_params =
 524                         MAX2(const_state->num_driver_params, IR3_DP_VTXCNT_MAX + 1);
 525         }
 526
 527         const_state->num_ubos = nir->info.num_ubos;
 528
 529         /* num_driver_params is scalar, align to vec4: */
 530         const_state->num_driver_params = align(const_state->num_driver_params, 4);
 531
 532         debug_assert((const_state->ubo_state.size % 16) == 0);
 533         unsigned constoff = const_state->ubo_state.size / 16;
 534         unsigned ptrsz = ir3_pointer_size(compiler);
 535
 536         if (const_state->num_ubos > 0) {
 537                 const_state->offsets.ubo = constoff;
 538                 constoff += align(const_state->num_ubos * ptrsz, 4) / 4;
 539         }
 540
 541         if (const_state->ssbo_size.count > 0) {
 542                 unsigned cnt = const_state->ssbo_size.count;
 543                 const_state->offsets.ssbo_sizes = constoff;
 544                 constoff += align(cnt, 4) / 4;
 545         }
 546
 547         if (const_state->image_dims.count > 0) {
 548                 unsigned cnt = const_state->image_dims.count;
 549                 const_state->offsets.image_dims = constoff;
 550                 constoff += align(cnt, 4) / 4;
 551         }
 552
 553         if (const_state->num_driver_params > 0) {
 554                 /* offset cannot be 0 for vs params loaded by CP_DRAW_INDIRECT_MULTI */
 555                 if (v->type == MESA_SHADER_VERTEX && compiler->gpu_id >= 600)
 556                         constoff = MAX2(constoff, 1);
 557                 const_state->offsets.driver_param = constoff;
 558         }
 559         constoff += const_state->num_driver_params / 4;
 560
 561         if ((v->type == MESA_SHADER_VERTEX) &&
 562                         (compiler->gpu_id < 500) &&
 563                         v->shader->stream_output.num_outputs > 0) {
 564                 const_state->offsets.tfbo = constoff;
 565                 constoff += align(IR3_MAX_SO_BUFFERS * ptrsz, 4) / 4;
 566         }
 567
 568         switch (v->type) {
 569         case MESA_SHADER_VERTEX:
 570                 const_state->offsets.primitive_param = constoff;
 571                 constoff += 1;
 572                 break;
 573         case MESA_SHADER_TESS_CTRL:
 574         case MESA_SHADER_TESS_EVAL:
 575                 constoff = align(constoff - 1, 4) + 3;
 576                 const_state->offsets.primitive_param = constoff;
 577                 const_state->offsets.primitive_map = constoff + 5;
 578                 constoff += 5 + DIV_ROUND_UP(nir->num_inputs, 4);
 579                 break;
 580         case MESA_SHADER_GEOMETRY:
 581                 const_state->offsets.primitive_param = constoff;
 582                 const_state->offsets.primitive_map = constoff + 1;
 583                 constoff += 1 + DIV_ROUND_UP(nir->num_inputs, 4);
 584                 break;
 585         default:
 586                 break;
 587         }
 588
 589         const_state->offsets.immediate = constoff;
 590
 591         assert(constoff <= ir3_max_const(v));
 592 }