src/gallium/drivers/freedreno/a4xx/fd4_draw.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_prim.h"
  33
  34 #include "freedreno_state.h"
  35 #include "freedreno_resource.h"
  36
  37 #include "fd4_draw.h"
  38 #include "fd4_context.h"
  39 #include "fd4_emit.h"
  40 #include "fd4_program.h"
  41 #include "fd4_format.h"
  42 #include "fd4_zsa.h"
  43
  44
  45 static void
  46 draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
  47                 struct fd4_emit *emit)
  48 {
  49         const struct pipe_draw_info *info = emit->info;
  50         enum pc_di_primtype primtype = ctx->primtypes[info->mode];
  51
  52         fd4_emit_state(ctx, ring, emit);
  53
  54         if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE))
  55                 fd4_emit_vertex_bufs(ring, emit);
  56
  57         OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
  58         OUT_RING(ring, info->indexed ? info->index_bias : info->start); /* VFD_INDEX_OFFSET */
  59         OUT_RING(ring, info->start_instance);   /* ??? UNKNOWN_2209 */
  60
  61         OUT_PKT0(ring, REG_A4XX_PC_RESTART_INDEX, 1);
  62         OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
  63                         info->restart_index : 0xffffffff);
  64
  65         /* points + psize -> spritelist: */
  66         if (ctx->rasterizer->point_size_per_vertex &&
  67                         fd4_emit_get_vp(emit)->writes_psize &&
  68                         (info->mode == PIPE_PRIM_POINTS))
  69                 primtype = DI_PT_POINTLIST_PSIZE;
  70
  71         fd4_draw_emit(ctx->batch, ring, primtype,
  72                         emit->key.binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY,
  73                         info);
  74 }
  75
  76 /* fixup dirty shader state in case some "unrelated" (from the state-
  77  * tracker's perspective) state change causes us to switch to a
  78  * different variant.
  79  */
  80 static void
  81 fixup_shader_state(struct fd_context *ctx, struct ir3_shader_key *key)
  82 {
  83         struct fd4_context *fd4_ctx = fd4_context(ctx);
  84         struct ir3_shader_key *last_key = &fd4_ctx->last_key;
  85
  86         if (!ir3_shader_key_equal(last_key, key)) {
  87                 if (last_key->has_per_samp || key->has_per_samp) {
  88                         if ((last_key->vsaturate_s != key->vsaturate_s) ||
  89                                         (last_key->vsaturate_t != key->vsaturate_t) ||
  90                                         (last_key->vsaturate_r != key->vsaturate_r) ||
  91                                         (last_key->vastc_srgb != key->vastc_srgb))
  92                                 ctx->dirty |= FD_SHADER_DIRTY_VP;
  93
  94                         if ((last_key->fsaturate_s != key->fsaturate_s) ||
  95                                         (last_key->fsaturate_t != key->fsaturate_t) ||
  96                                         (last_key->fsaturate_r != key->fsaturate_r) ||
  97                                         (last_key->fastc_srgb != key->fastc_srgb))
  98                                 ctx->dirty |= FD_SHADER_DIRTY_FP;
  99                 }
 100
 101                 if (last_key->vclamp_color != key->vclamp_color)
 102                         ctx->dirty |= FD_SHADER_DIRTY_VP;
 103
 104                 if (last_key->fclamp_color != key->fclamp_color)
 105                         ctx->dirty |= FD_SHADER_DIRTY_FP;
 106
 107                 if (last_key->color_two_side != key->color_two_side)
 108                         ctx->dirty |= FD_SHADER_DIRTY_FP;
 109
 110                 if (last_key->half_precision != key->half_precision)
 111                         ctx->dirty |= FD_SHADER_DIRTY_FP;
 112
 113                 if (last_key->rasterflat != key->rasterflat)
 114                         ctx->dirty |= FD_SHADER_DIRTY_FP;
 115
 116                 fd4_ctx->last_key = *key;
 117         }
 118 }
 119
 120 static bool
 121 fd4_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info)
 122 {
 123         struct fd4_context *fd4_ctx = fd4_context(ctx);
 124         struct fd4_emit emit = {
 125                 .debug = &ctx->debug,
 126                 .vtx  = &ctx->vtx,
 127                 .prog = &ctx->prog,
 128                 .info = info,
 129                 .key = {
 130                         .color_two_side = ctx->rasterizer->light_twoside,
 131                         .vclamp_color = ctx->rasterizer->clamp_vertex_color,
 132                         .fclamp_color = ctx->rasterizer->clamp_fragment_color,
 133                         .rasterflat = ctx->rasterizer->flatshade,
 134                         // TODO set .half_precision based on render target format,
 135                         // ie. float16 and smaller use half, float32 use full..
 136                         .half_precision = !!(fd_mesa_debug & FD_DBG_FRAGHALF),
 137                         .ucp_enables = ctx->rasterizer->clip_plane_enable,
 138                         .has_per_samp = (fd4_ctx->fsaturate || fd4_ctx->vsaturate ||
 139                                         fd4_ctx->fastc_srgb || fd4_ctx->vastc_srgb),
 140                         .vsaturate_s = fd4_ctx->vsaturate_s,
 141                         .vsaturate_t = fd4_ctx->vsaturate_t,
 142                         .vsaturate_r = fd4_ctx->vsaturate_r,
 143                         .fsaturate_s = fd4_ctx->fsaturate_s,
 144                         .fsaturate_t = fd4_ctx->fsaturate_t,
 145                         .fsaturate_r = fd4_ctx->fsaturate_r,
 146                         .vastc_srgb = fd4_ctx->vastc_srgb,
 147                         .fastc_srgb = fd4_ctx->fastc_srgb,
 148                 },
 149                 .rasterflat = ctx->rasterizer->flatshade,
 150                 .sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
 151                 .sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,
 152         };
 153
 154         fixup_shader_state(ctx, &emit.key);
 155
 156         unsigned dirty = ctx->dirty;
 157
 158         /* do regular pass first, since that is more likely to fail compiling: */
 159
 160         if (!(fd4_emit_get_vp(&emit) && fd4_emit_get_fp(&emit)))
 161                 return false;
 162
 163         emit.key.binning_pass = false;
 164         emit.dirty = dirty;
 165
 166         struct fd_ringbuffer *ring = ctx->batch->draw;
 167
 168         if (ctx->rasterizer->rasterizer_discard) {
 169                 fd_wfi(ctx->batch, ring);
 170                 OUT_PKT3(ring, CP_REG_RMW, 3);
 171                 OUT_RING(ring, REG_A4XX_RB_RENDER_CONTROL);
 172                 OUT_RING(ring, ~A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE);
 173                 OUT_RING(ring, A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE);
 174         }
 175
 176         draw_impl(ctx, ctx->batch->draw, &emit);
 177
 178         if (ctx->rasterizer->rasterizer_discard) {
 179                 fd_wfi(ctx->batch, ring);
 180                 OUT_PKT3(ring, CP_REG_RMW, 3);
 181                 OUT_RING(ring, REG_A4XX_RB_RENDER_CONTROL);
 182                 OUT_RING(ring, ~A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE);
 183                 OUT_RING(ring, 0);
 184         }
 185
 186         /* and now binning pass: */
 187         emit.key.binning_pass = true;
 188         emit.dirty = dirty & ~(FD_DIRTY_BLEND);
 189         emit.vp = NULL;   /* we changed key so need to refetch vp */
 190         emit.fp = NULL;
 191         draw_impl(ctx, ctx->batch->binning, &emit);
 192
 193         return true;
 194 }
 195
 196 /* clear operations ignore viewport state, so we need to reset it
 197  * based on framebuffer state:
 198  */
 199 static void
 200 reset_viewport(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb)
 201 {
 202         float half_width = pfb->width * 0.5f;
 203         float half_height = pfb->height * 0.5f;
 204
 205         OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 4);
 206         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0(half_width));
 207         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0(half_width));
 208         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0(half_height));
 209         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-half_height));
 210 }
 211
 212 /* TODO maybe we should just migrate u_blitter for clear and do it in
 213  * core (so we get normal draw pass state mgmt and binning).. That should
 214  * work well enough for a3xx/a4xx (but maybe not a2xx?)
 215  */
 216
 217 static void
 218 fd4_clear_binning(struct fd_context *ctx, unsigned dirty)
 219 {
 220         struct fd4_context *fd4_ctx = fd4_context(ctx);
 221         struct fd_ringbuffer *ring = ctx->batch->binning;
 222         struct fd4_emit emit = {
 223                 .debug = &ctx->debug,
 224                 .vtx  = &fd4_ctx->solid_vbuf_state,
 225                 .prog = &ctx->solid_prog,
 226                 .key = {
 227                         .binning_pass = true,
 228                         .half_precision = true,
 229                 },
 230                 .dirty = dirty,
 231         };
 232
 233         fd4_emit_state(ctx, ring, &emit);
 234         fd4_emit_vertex_bufs(ring, &emit);
 235         reset_viewport(ring, &ctx->batch->framebuffer);
 236
 237         OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 2);
 238         OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_VAROUT(0) |
 239                         A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 240         OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 241                         A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES));
 242
 243         OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
 244         OUT_RING(ring, 0x00000002);
 245
 246         fd4_draw(ctx->batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 247                         DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX_SIZE_IGN, 0, 0, NULL);
 248 }
 249
 250 static void
 251 fd4_clear(struct fd_context *ctx, unsigned buffers,
 252                 const union pipe_color_union *color, double depth, unsigned stencil)
 253 {
 254         struct fd4_context *fd4_ctx = fd4_context(ctx);
 255         struct fd_ringbuffer *ring = ctx->batch->draw;
 256         struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
 257         unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS] = {0};
 258         unsigned dirty = ctx->dirty;
 259         unsigned i;
 260         struct fd4_emit emit = {
 261                 .debug = &ctx->debug,
 262                 .vtx  = &fd4_ctx->solid_vbuf_state,
 263                 .prog = &ctx->solid_prog,
 264                 .key = {
 265                         .half_precision = fd_half_precision(pfb),
 266                 },
 267         };
 268
 269         dirty &= FD_DIRTY_FRAMEBUFFER | FD_DIRTY_SCISSOR;
 270         dirty |= FD_DIRTY_PROG;
 271         emit.dirty = dirty;
 272
 273         fd4_clear_binning(ctx, dirty);
 274
 275         OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1);
 276         OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 277
 278         /* emit generic state now: */
 279         fd4_emit_state(ctx, ring, &emit);
 280         reset_viewport(ring, pfb);
 281
 282         if (buffers & PIPE_CLEAR_DEPTH) {
 283                 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
 284                 OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
 285                                 A4XX_RB_DEPTH_CONTROL_Z_ENABLE |
 286                                 A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS));
 287
 288                 fd_wfi(ctx->batch, ring);
 289                 OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0, 2);
 290                 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
 291                 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(depth));
 292                 ctx->dirty |= FD_DIRTY_VIEWPORT;
 293         } else {
 294                 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
 295                 OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
 296         }
 297
 298         if (buffers & PIPE_CLEAR_STENCIL) {
 299                 OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
 300                 OUT_RING(ring, A4XX_RB_STENCILREFMASK_STENCILREF(stencil) |
 301                                 A4XX_RB_STENCILREFMASK_STENCILMASK(stencil) |
 302                                 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 303                 OUT_RING(ring, A4XX_RB_STENCILREFMASK_STENCILREF(0) |
 304                                 A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
 305                                 0xff000000 | // XXX ???
 306                                 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 307
 308                 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
 309                 OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
 310                                 A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
 311                                 A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 312                                 A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_REPLACE) |
 313                                 A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 314                                 A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 315                                 A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 316                                 A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 317                                 A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 318                 OUT_RING(ring, A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER);
 319         } else {
 320                 OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
 321                 OUT_RING(ring, A4XX_RB_STENCILREFMASK_STENCILREF(0) |
 322                                 A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
 323                                 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0));
 324                 OUT_RING(ring, A4XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
 325                                 A4XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
 326                                 A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0));
 327
 328                 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
 329                 OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
 330                                 A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 331                                 A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 332                                 A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 333                                 A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 334                                 A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 335                                 A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 336                                 A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 337                 OUT_RING(ring, 0x00000000); /* RB_STENCIL_CONTROL2 */
 338         }
 339
 340         if (buffers & PIPE_CLEAR_COLOR) {
 341                 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
 342                 OUT_RING(ring, A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER));
 343         }
 344
 345         for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
 346                 mrt_comp[i] = (buffers & (PIPE_CLEAR_COLOR0 << i)) ? 0xf : 0x0;
 347
 348                 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
 349                 OUT_RING(ring, A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
 350                                 A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
 351
 352                 OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
 353                 OUT_RING(ring, A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
 354                                 A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 355                                 A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
 356                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
 357                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 358                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
 359         }
 360
 361         OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
 362         OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
 363                         A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
 364                         A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
 365                         A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
 366                         A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
 367                         A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
 368                         A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
 369                         A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
 370
 371         fd4_emit_vertex_bufs(ring, &emit);
 372
 373         OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
 374         OUT_RING(ring, 0x0);          /* XXX GRAS_ALPHA_CONTROL */
 375
 376         OUT_PKT0(ring, REG_A4XX_GRAS_CLEAR_CNTL, 1);
 377         OUT_RING(ring, 0x00000000);
 378
 379         /* until fastclear works: */
 380         fd4_emit_const(ring, SHADER_FRAGMENT, 0, 0, 4, color->ui, NULL);
 381
 382         OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
 383         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 384         OUT_RING(ring, 0);            /* ??? UNKNOWN_2209 */
 385
 386         OUT_PKT0(ring, REG_A4XX_PC_RESTART_INDEX, 1);
 387         OUT_RING(ring, 0xffffffff);   /* PC_RESTART_INDEX */
 388
 389         OUT_PKT3(ring, CP_UNKNOWN_1A, 1);
 390         OUT_RING(ring, 0x00000001);
 391
 392         fd4_draw(ctx->batch, ring, DI_PT_RECTLIST, USE_VISIBILITY,
 393                         DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX_SIZE_IGN, 0, 0, NULL);
 394
 395         OUT_PKT3(ring, CP_UNKNOWN_1A, 1);
 396         OUT_RING(ring, 0x00000000);
 397
 398         OUT_PKT0(ring, REG_A4XX_GRAS_CLEAR_CNTL, 1);
 399         OUT_RING(ring, A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR);
 400
 401         OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
 402         OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 403                         A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
 404                         A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 405                         A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 406 }
 407
 408 void
 409 fd4_draw_init(struct pipe_context *pctx)
 410 {
 411         struct fd_context *ctx = fd_context(pctx);
 412         ctx->draw_vbo = fd4_draw_vbo;
 413         ctx->clear = fd4_clear;
 414 }