2 * Copyright 2017 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
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23 #ifndef IRIS_RESOURCE_H
24 #define IRIS_RESOURCE_H
26 #include "pipe/p_state.h"
27 #include "util/u_inlines.h"
28 #include "util/u_range.h"
29 #include "intel/isl/isl.h"
34 #define IRIS_MAX_MIPLEVELS 15
36 struct iris_format_info
{
38 struct isl_swizzle swizzle
;
41 #define IRIS_RESOURCE_FLAG_SHADER_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
42 #define IRIS_RESOURCE_FLAG_SURFACE_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
43 #define IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
45 enum gen9_astc5x5_wa_tex_type
{
46 GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5
= 1 << 0,
47 GEN9_ASTC5X5_WA_TEX_TYPE_AUX
= 1 << 1,
51 * Resources represent a GPU buffer object or image (mipmap tree).
53 * They contain the storage (BO) and layout information (ISL surface).
55 struct iris_resource
{
56 struct pipe_resource base
;
57 enum pipe_format internal_format
;
60 * The ISL surface layout information for this resource.
62 * This is not filled out for PIPE_BUFFER resources, but is guaranteed
63 * to be zeroed. Note that this also guarantees that res->surf.tiling
64 * will be ISL_TILING_LINEAR, so it's safe to check that.
68 /** Backing storage for the resource */
71 /** offset at which data starts in the BO */
75 * A bitfield of PIPE_BIND_* indicating how this resource was bound
76 * in the past. Only meaningful for PIPE_BUFFER; used for flushing.
78 unsigned bind_history
;
81 * For PIPE_BUFFER resources, a range which may contain valid data.
83 * This is a conservative estimate of what part of the buffer contains
84 * valid data that we have to preserve. The rest of the buffer is
85 * considered invalid, and we can promote writes to that region to
86 * be unsynchronized writes, avoiding blit copies.
88 struct util_range valid_buffer_range
;
91 * Auxiliary buffer information (CCS, MCS, or HiZ).
94 /** The surface layout for the auxiliary buffer. */
97 /** The buffer object containing the auxiliary data. */
100 /** Offset into 'bo' where the auxiliary surface starts. */
104 * Fast clear color for this surface. For depth surfaces, the clear
105 * value is stored as a float32 in the red component.
107 union isl_color_value clear_color
;
109 /** Buffer object containing the indirect clear color. */
110 struct iris_bo
*clear_color_bo
;
112 /** Offset into bo where the clear color can be found. */
113 uint64_t clear_color_offset
;
116 * \brief The type of auxiliary compression used by this resource.
118 * This describes the type of auxiliary compression that is intended to
119 * be used by this resource. An aux usage of ISL_AUX_USAGE_NONE means
120 * that auxiliary compression is permanently disabled. An aux usage
121 * other than ISL_AUX_USAGE_NONE does not imply that auxiliary
122 * compression will always be enabled for this surface.
124 enum isl_aux_usage usage
;
127 * A bitfield of ISL_AUX_* modes that might this resource might use.
129 * For example, a surface might use both CCS_E and CCS_D at times.
131 unsigned possible_usages
;
134 * Same as possible_usages, but only with modes supported for sampling.
136 unsigned sampler_usages
;
139 * \brief Maps miptree slices to their current aux state.
141 * This two-dimensional array is indexed as [level][layer] and stores an
142 * aux state for each slice.
144 enum isl_aux_state
**state
;
147 * If (1 << level) is set, HiZ is enabled for that miplevel.
153 * For external surfaces, this is DRM format modifier that was used to
154 * create or import the surface. For internal surfaces, this will always
155 * be DRM_FORMAT_MOD_INVALID.
157 const struct isl_drm_modifier_info
*mod_info
;
161 * A simple <resource, offset> tuple for storing a reference to a
162 * piece of state stored in a GPU buffer object.
164 struct iris_state_ref
{
165 struct pipe_resource
*res
;
170 * Gallium CSO for sampler views (texture views).
172 * In addition to the normal pipe_resource, this adds an ISL view
173 * which may reinterpret the format or restrict levels/layers.
175 * These can also be linear texture buffers.
177 struct iris_sampler_view
{
178 struct pipe_sampler_view base
;
179 struct isl_view view
;
181 union isl_color_value clear_color
;
183 /* A short-cut (not a reference) to the actual resource being viewed.
184 * Multi-planar (or depth+stencil) images may have multiple resources
185 * chained together; this skips having to traverse base->texture->*.
187 struct iris_resource
*res
;
189 /** The resource (BO) holding our SURFACE_STATE. */
190 struct iris_state_ref surface_state
;
194 * Image view representation.
196 struct iris_image_view
{
197 struct pipe_image_view base
;
199 /** The resource (BO) holding our SURFACE_STATE. */
200 struct iris_state_ref surface_state
;
204 * Gallium CSO for surfaces (framebuffer attachments).
206 * A view of a surface that can be bound to a color render target or
207 * depth/stencil attachment.
209 struct iris_surface
{
210 struct pipe_surface base
;
211 struct isl_view view
;
212 union isl_color_value clear_color
;
214 /** The resource (BO) holding our SURFACE_STATE. */
215 struct iris_state_ref surface_state
;
219 * Transfer object - information about a buffer mapping.
221 struct iris_transfer
{
222 struct pipe_transfer base
;
223 struct pipe_debug_callback
*dbg
;
227 /** A linear staging resource for GPU-based copy_region transfers. */
228 struct pipe_resource
*staging
;
229 struct blorp_context
*blorp
;
230 struct iris_batch
*batch
;
232 void (*unmap
)(struct iris_transfer
*);
236 * Unwrap a pipe_resource to get the underlying iris_bo (for convenience).
238 static inline struct iris_bo
*
239 iris_resource_bo(struct pipe_resource
*p_res
)
241 struct iris_resource
*res
= (void *) p_res
;
245 struct iris_format_info
iris_format_for_usage(const struct gen_device_info
*,
247 isl_surf_usage_flags_t usage
);
249 struct pipe_resource
*iris_resource_get_separate_stencil(struct pipe_resource
*);
251 void iris_get_depth_stencil_resources(struct pipe_resource
*res
,
252 struct iris_resource
**out_z
,
253 struct iris_resource
**out_s
);
254 bool iris_resource_set_clear_color(struct iris_context
*ice
,
255 struct iris_resource
*res
,
256 union isl_color_value color
);
257 union isl_color_value
258 iris_resource_get_clear_color(const struct iris_resource
*res
,
259 struct iris_bo
**clear_color_bo
,
260 uint64_t *clear_color_offset
);
262 void iris_init_screen_resource_functions(struct pipe_screen
*pscreen
);
264 void iris_dirty_for_history(struct iris_context
*ice
,
265 struct iris_resource
*res
);
266 uint32_t iris_flush_bits_for_history(struct iris_resource
*res
);
268 void iris_flush_and_dirty_for_history(struct iris_context
*ice
,
269 struct iris_batch
*batch
,
270 struct iris_resource
*res
,
271 uint32_t extra_flags
,
274 unsigned iris_get_num_logical_layers(const struct iris_resource
*res
,
277 void iris_resource_disable_aux(struct iris_resource
*res
);
279 #define INTEL_REMAINING_LAYERS UINT32_MAX
280 #define INTEL_REMAINING_LEVELS UINT32_MAX
283 iris_hiz_exec(struct iris_context
*ice
,
284 struct iris_batch
*batch
,
285 struct iris_resource
*res
,
286 unsigned int level
, unsigned int start_layer
,
287 unsigned int num_layers
, enum isl_aux_op op
,
288 bool update_clear_depth
);
291 * Prepare a miptree for access
293 * This function should be called prior to any access to miptree in order to
294 * perform any needed resolves.
296 * \param[in] start_level The first mip level to be accessed
298 * \param[in] num_levels The number of miplevels to be accessed or
299 * INTEL_REMAINING_LEVELS to indicate every level
300 * above start_level will be accessed
302 * \param[in] start_layer The first array slice or 3D layer to be accessed
304 * \param[in] num_layers The number of array slices or 3D layers be
305 * accessed or INTEL_REMAINING_LAYERS to indicate
306 * every layer above start_layer will be accessed
308 * \param[in] aux_supported Whether or not the access will support the
309 * miptree's auxiliary compression format; this
310 * must be false for uncompressed miptrees
312 * \param[in] fast_clear_supported Whether or not the access will support
313 * fast clears in the miptree's auxiliary
317 iris_resource_prepare_access(struct iris_context
*ice
,
318 struct iris_batch
*batch
,
319 struct iris_resource
*res
,
320 uint32_t start_level
, uint32_t num_levels
,
321 uint32_t start_layer
, uint32_t num_layers
,
322 enum isl_aux_usage aux_usage
,
323 bool fast_clear_supported
);
326 * Complete a write operation
328 * This function should be called after any operation writes to a miptree.
329 * This will update the miptree's compression state so that future resolves
330 * happen correctly. Technically, this function can be called before the
331 * write occurs but the caller must ensure that they don't interlace
332 * iris_resource_prepare_access and iris_resource_finish_write calls to
333 * overlapping layer/level ranges.
335 * \param[in] level The mip level that was written
337 * \param[in] start_layer The first array slice or 3D layer written
339 * \param[in] num_layers The number of array slices or 3D layers
340 * written or INTEL_REMAINING_LAYERS to indicate
341 * every layer above start_layer was written
343 * \param[in] written_with_aux Whether or not the write was done with
344 * auxiliary compression enabled
347 iris_resource_finish_write(struct iris_context
*ice
,
348 struct iris_resource
*res
, uint32_t level
,
349 uint32_t start_layer
, uint32_t num_layers
,
350 enum isl_aux_usage aux_usage
);
352 /** Get the auxiliary compression state of a miptree slice */
354 iris_resource_get_aux_state(const struct iris_resource
*res
,
355 uint32_t level
, uint32_t layer
);
358 * Set the auxiliary compression state of a miptree slice range
360 * This function directly sets the auxiliary compression state of a slice
361 * range of a miptree. It only modifies data structures and does not do any
362 * resolves. This should only be called by code which directly performs
363 * compression operations such as fast clears and resolves. Most code should
364 * use iris_resource_prepare_access or iris_resource_finish_write.
367 iris_resource_set_aux_state(struct iris_context
*ice
,
368 struct iris_resource
*res
, uint32_t level
,
369 uint32_t start_layer
, uint32_t num_layers
,
370 enum isl_aux_state aux_state
);
373 * Prepare a miptree for raw access
375 * This helper prepares the miptree for access that knows nothing about any
376 * sort of compression whatsoever. This is useful when mapping the surface or
377 * using it with the blitter.
380 iris_resource_access_raw(struct iris_context
*ice
,
381 struct iris_batch
*batch
,
382 struct iris_resource
*res
,
383 uint32_t level
, uint32_t layer
,
387 iris_resource_prepare_access(ice
, batch
, res
, level
, 1, layer
, num_layers
,
388 ISL_AUX_USAGE_NONE
, false);
390 iris_resource_finish_write(ice
, res
, level
, layer
, num_layers
,
395 enum isl_aux_usage
iris_resource_texture_aux_usage(struct iris_context
*ice
,
396 const struct iris_resource
*res
,
397 enum isl_format view_fmt
,
398 enum gen9_astc5x5_wa_tex_type
);
399 void iris_resource_prepare_texture(struct iris_context
*ice
,
400 struct iris_batch
*batch
,
401 struct iris_resource
*res
,
402 enum isl_format view_format
,
403 uint32_t start_level
, uint32_t num_levels
,
404 uint32_t start_layer
, uint32_t num_layers
,
405 enum gen9_astc5x5_wa_tex_type
);
406 void iris_resource_prepare_image(struct iris_context
*ice
,
407 struct iris_batch
*batch
,
408 struct iris_resource
*res
);
411 iris_resource_unfinished_aux_import(struct iris_resource
*res
)
413 return res
->base
.next
!= NULL
&& res
->mod_info
&&
414 res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
417 void iris_resource_finish_aux_import(struct pipe_screen
*pscreen
,
418 struct iris_resource
*res
);
420 bool iris_has_color_unresolved(const struct iris_resource
*res
,
421 unsigned start_level
, unsigned num_levels
,
422 unsigned start_layer
, unsigned num_layers
);
424 void iris_resource_check_level_layer(const struct iris_resource
*res
,
425 uint32_t level
, uint32_t layer
);
427 bool iris_resource_level_has_hiz(const struct iris_resource
*res
,
430 enum isl_aux_usage
iris_resource_render_aux_usage(struct iris_context
*ice
,
431 struct iris_resource
*res
,
432 enum isl_format render_fmt
,
434 bool draw_aux_disabled
);
435 void iris_resource_prepare_render(struct iris_context
*ice
,
436 struct iris_batch
*batch
,
437 struct iris_resource
*res
, uint32_t level
,
438 uint32_t start_layer
, uint32_t layer_count
,
439 enum isl_aux_usage aux_usage
);
440 void iris_resource_finish_render(struct iris_context
*ice
,
441 struct iris_resource
*res
, uint32_t level
,
442 uint32_t start_layer
, uint32_t layer_count
,
443 enum isl_aux_usage aux_usage
);
444 void iris_resource_prepare_depth(struct iris_context
*ice
,
445 struct iris_batch
*batch
,
446 struct iris_resource
*res
, uint32_t level
,
447 uint32_t start_layer
, uint32_t layer_count
);
448 void iris_resource_finish_depth(struct iris_context
*ice
,
449 struct iris_resource
*res
, uint32_t level
,
450 uint32_t start_layer
, uint32_t layer_count
,