2 * Copyright 2017 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #ifndef IRIS_RESOURCE_H
24 #define IRIS_RESOURCE_H
26 #include "pipe/p_state.h"
27 #include "util/u_inlines.h"
28 #include "util/u_range.h"
29 #include "intel/isl/isl.h"
34 #define IRIS_MAX_MIPLEVELS 15
36 struct iris_format_info
{
38 struct isl_swizzle swizzle
;
41 #define IRIS_RESOURCE_FLAG_SHADER_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
42 #define IRIS_RESOURCE_FLAG_SURFACE_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
43 #define IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
45 enum gen9_astc5x5_wa_tex_type
{
46 GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5
= 1 << 0,
47 GEN9_ASTC5X5_WA_TEX_TYPE_AUX
= 1 << 1,
51 * Resources represent a GPU buffer object or image (mipmap tree).
53 * They contain the storage (BO) and layout information (ISL surface).
55 struct iris_resource
{
56 struct pipe_resource base
;
57 enum pipe_format internal_format
;
60 * The ISL surface layout information for this resource.
62 * This is not filled out for PIPE_BUFFER resources, but is guaranteed
63 * to be zeroed. Note that this also guarantees that res->surf.tiling
64 * will be ISL_TILING_LINEAR, so it's safe to check that.
68 /** Backing storage for the resource */
71 /** offset at which data starts in the BO */
75 * A bitfield of PIPE_BIND_* indicating how this resource was bound
76 * in the past. Only meaningful for PIPE_BUFFER; used for flushing.
78 unsigned bind_history
;
81 * For PIPE_BUFFER resources, a range which may contain valid data.
83 * This is a conservative estimate of what part of the buffer contains
84 * valid data that we have to preserve. The rest of the buffer is
85 * considered invalid, and we can promote writes to that region to
86 * be unsynchronized writes, avoiding blit copies.
88 struct util_range valid_buffer_range
;
91 * Auxiliary buffer information (CCS, MCS, or HiZ).
94 /** The surface layout for the auxiliary buffer. */
97 /** The buffer object containing the auxiliary data. */
100 /** Offset into 'bo' where the auxiliary surface starts. */
104 * Fast clear color for this surface. For depth surfaces, the clear
105 * value is stored as a float32 in the red component.
107 union isl_color_value clear_color
;
109 /** Buffer object containing the indirect clear color. */
110 struct iris_bo
*clear_color_bo
;
112 /** Offset into bo where the clear color can be found. */
113 uint64_t clear_color_offset
;
116 * \brief The type of auxiliary compression used by this resource.
118 * This describes the type of auxiliary compression that is intended to
119 * be used by this resource. An aux usage of ISL_AUX_USAGE_NONE means
120 * that auxiliary compression is permanently disabled. An aux usage
121 * other than ISL_AUX_USAGE_NONE does not imply that auxiliary
122 * compression will always be enabled for this surface.
124 enum isl_aux_usage usage
;
127 * A bitfield of ISL_AUX_* modes that might this resource might use.
129 * For example, a surface might use both CCS_E and CCS_D at times.
131 unsigned possible_usages
;
134 * Same as possible_usages, but only with modes supported for sampling.
136 unsigned sampler_usages
;
139 * \brief Maps miptree slices to their current aux state.
141 * This two-dimensional array is indexed as [level][layer] and stores an
142 * aux state for each slice.
144 enum isl_aux_state
**state
;
147 * If (1 << level) is set, HiZ is enabled for that miplevel.
153 * For external surfaces, this is DRM format modifier that was used to
154 * create or import the surface. For internal surfaces, this will always
155 * be DRM_FORMAT_MOD_INVALID.
157 const struct isl_drm_modifier_info
*mod_info
;
161 * A simple <resource, offset> tuple for storing a reference to a
162 * piece of state stored in a GPU buffer object.
164 struct iris_state_ref
{
165 struct pipe_resource
*res
;
170 * Gallium CSO for sampler views (texture views).
172 * In addition to the normal pipe_resource, this adds an ISL view
173 * which may reinterpret the format or restrict levels/layers.
175 * These can also be linear texture buffers.
177 struct iris_sampler_view
{
178 struct pipe_sampler_view base
;
179 struct isl_view view
;
181 union isl_color_value clear_color
;
183 /* A short-cut (not a reference) to the actual resource being viewed.
184 * Multi-planar (or depth+stencil) images may have multiple resources
185 * chained together; this skips having to traverse base->texture->*.
187 struct iris_resource
*res
;
189 /** The resource (BO) holding our SURFACE_STATE. */
190 struct iris_state_ref surface_state
;
194 * Image view representation.
196 struct iris_image_view
{
197 struct pipe_image_view base
;
199 /** The resource (BO) holding our SURFACE_STATE. */
200 struct iris_state_ref surface_state
;
204 * Gallium CSO for surfaces (framebuffer attachments).
206 * A view of a surface that can be bound to a color render target or
207 * depth/stencil attachment.
209 struct iris_surface
{
210 struct pipe_surface base
;
211 struct isl_view view
;
212 struct isl_view read_view
;
213 union isl_color_value clear_color
;
215 /** The resource (BO) holding our SURFACE_STATE. */
216 struct iris_state_ref surface_state
;
217 /** The resource (BO) holding our SURFACE_STATE for read. */
218 struct iris_state_ref surface_state_read
;
222 * Transfer object - information about a buffer mapping.
224 struct iris_transfer
{
225 struct pipe_transfer base
;
226 struct pipe_debug_callback
*dbg
;
230 /** A linear staging resource for GPU-based copy_region transfers. */
231 struct pipe_resource
*staging
;
232 struct blorp_context
*blorp
;
233 struct iris_batch
*batch
;
235 bool dest_had_defined_contents
;
237 void (*unmap
)(struct iris_transfer
*);
241 * Unwrap a pipe_resource to get the underlying iris_bo (for convenience).
243 static inline struct iris_bo
*
244 iris_resource_bo(struct pipe_resource
*p_res
)
246 struct iris_resource
*res
= (void *) p_res
;
250 struct iris_format_info
iris_format_for_usage(const struct gen_device_info
*,
252 isl_surf_usage_flags_t usage
);
254 struct pipe_resource
*iris_resource_get_separate_stencil(struct pipe_resource
*);
256 void iris_get_depth_stencil_resources(struct pipe_resource
*res
,
257 struct iris_resource
**out_z
,
258 struct iris_resource
**out_s
);
259 bool iris_resource_set_clear_color(struct iris_context
*ice
,
260 struct iris_resource
*res
,
261 union isl_color_value color
);
262 union isl_color_value
263 iris_resource_get_clear_color(const struct iris_resource
*res
,
264 struct iris_bo
**clear_color_bo
,
265 uint64_t *clear_color_offset
);
267 void iris_init_screen_resource_functions(struct pipe_screen
*pscreen
);
269 void iris_dirty_for_history(struct iris_context
*ice
,
270 struct iris_resource
*res
);
271 uint32_t iris_flush_bits_for_history(struct iris_resource
*res
);
273 void iris_flush_and_dirty_for_history(struct iris_context
*ice
,
274 struct iris_batch
*batch
,
275 struct iris_resource
*res
,
276 uint32_t extra_flags
,
279 unsigned iris_get_num_logical_layers(const struct iris_resource
*res
,
282 void iris_resource_disable_aux(struct iris_resource
*res
);
284 #define INTEL_REMAINING_LAYERS UINT32_MAX
285 #define INTEL_REMAINING_LEVELS UINT32_MAX
288 iris_hiz_exec(struct iris_context
*ice
,
289 struct iris_batch
*batch
,
290 struct iris_resource
*res
,
291 unsigned int level
, unsigned int start_layer
,
292 unsigned int num_layers
, enum isl_aux_op op
,
293 bool update_clear_depth
);
296 * Prepare a miptree for access
298 * This function should be called prior to any access to miptree in order to
299 * perform any needed resolves.
301 * \param[in] start_level The first mip level to be accessed
303 * \param[in] num_levels The number of miplevels to be accessed or
304 * INTEL_REMAINING_LEVELS to indicate every level
305 * above start_level will be accessed
307 * \param[in] start_layer The first array slice or 3D layer to be accessed
309 * \param[in] num_layers The number of array slices or 3D layers be
310 * accessed or INTEL_REMAINING_LAYERS to indicate
311 * every layer above start_layer will be accessed
313 * \param[in] aux_supported Whether or not the access will support the
314 * miptree's auxiliary compression format; this
315 * must be false for uncompressed miptrees
317 * \param[in] fast_clear_supported Whether or not the access will support
318 * fast clears in the miptree's auxiliary
322 iris_resource_prepare_access(struct iris_context
*ice
,
323 struct iris_batch
*batch
,
324 struct iris_resource
*res
,
325 uint32_t start_level
, uint32_t num_levels
,
326 uint32_t start_layer
, uint32_t num_layers
,
327 enum isl_aux_usage aux_usage
,
328 bool fast_clear_supported
);
331 * Complete a write operation
333 * This function should be called after any operation writes to a miptree.
334 * This will update the miptree's compression state so that future resolves
335 * happen correctly. Technically, this function can be called before the
336 * write occurs but the caller must ensure that they don't interlace
337 * iris_resource_prepare_access and iris_resource_finish_write calls to
338 * overlapping layer/level ranges.
340 * \param[in] level The mip level that was written
342 * \param[in] start_layer The first array slice or 3D layer written
344 * \param[in] num_layers The number of array slices or 3D layers
345 * written or INTEL_REMAINING_LAYERS to indicate
346 * every layer above start_layer was written
348 * \param[in] written_with_aux Whether or not the write was done with
349 * auxiliary compression enabled
352 iris_resource_finish_write(struct iris_context
*ice
,
353 struct iris_resource
*res
, uint32_t level
,
354 uint32_t start_layer
, uint32_t num_layers
,
355 enum isl_aux_usage aux_usage
);
357 /** Get the auxiliary compression state of a miptree slice */
359 iris_resource_get_aux_state(const struct iris_resource
*res
,
360 uint32_t level
, uint32_t layer
);
363 * Set the auxiliary compression state of a miptree slice range
365 * This function directly sets the auxiliary compression state of a slice
366 * range of a miptree. It only modifies data structures and does not do any
367 * resolves. This should only be called by code which directly performs
368 * compression operations such as fast clears and resolves. Most code should
369 * use iris_resource_prepare_access or iris_resource_finish_write.
372 iris_resource_set_aux_state(struct iris_context
*ice
,
373 struct iris_resource
*res
, uint32_t level
,
374 uint32_t start_layer
, uint32_t num_layers
,
375 enum isl_aux_state aux_state
);
378 * Prepare a miptree for raw access
380 * This helper prepares the miptree for access that knows nothing about any
381 * sort of compression whatsoever. This is useful when mapping the surface or
382 * using it with the blitter.
385 iris_resource_access_raw(struct iris_context
*ice
,
386 struct iris_batch
*batch
,
387 struct iris_resource
*res
,
388 uint32_t level
, uint32_t layer
,
392 iris_resource_prepare_access(ice
, batch
, res
, level
, 1, layer
, num_layers
,
393 ISL_AUX_USAGE_NONE
, false);
395 iris_resource_finish_write(ice
, res
, level
, layer
, num_layers
,
400 enum isl_dim_layout
iris_get_isl_dim_layout(const struct gen_device_info
*devinfo
,
401 enum isl_tiling tiling
,
402 enum pipe_texture_target target
);
403 enum isl_surf_dim
target_to_isl_surf_dim(enum pipe_texture_target target
);
404 uint32_t iris_resource_get_tile_offsets(const struct iris_resource
*res
,
405 uint32_t level
, uint32_t z
,
406 uint32_t *tile_x
, uint32_t *tile_y
);
407 enum isl_aux_usage
iris_resource_texture_aux_usage(struct iris_context
*ice
,
408 const struct iris_resource
*res
,
409 enum isl_format view_fmt
,
410 enum gen9_astc5x5_wa_tex_type
);
411 void iris_resource_prepare_texture(struct iris_context
*ice
,
412 struct iris_batch
*batch
,
413 struct iris_resource
*res
,
414 enum isl_format view_format
,
415 uint32_t start_level
, uint32_t num_levels
,
416 uint32_t start_layer
, uint32_t num_layers
,
417 enum gen9_astc5x5_wa_tex_type
);
418 void iris_resource_prepare_image(struct iris_context
*ice
,
419 struct iris_batch
*batch
,
420 struct iris_resource
*res
);
423 iris_resource_unfinished_aux_import(struct iris_resource
*res
)
425 return res
->base
.next
!= NULL
&& res
->mod_info
&&
426 res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
429 void iris_resource_finish_aux_import(struct pipe_screen
*pscreen
,
430 struct iris_resource
*res
);
432 bool iris_has_color_unresolved(const struct iris_resource
*res
,
433 unsigned start_level
, unsigned num_levels
,
434 unsigned start_layer
, unsigned num_layers
);
436 void iris_resource_check_level_layer(const struct iris_resource
*res
,
437 uint32_t level
, uint32_t layer
);
439 bool iris_resource_level_has_hiz(const struct iris_resource
*res
,
441 bool iris_has_color_unresolved(const struct iris_resource
*res
,
442 unsigned start_level
, unsigned num_levels
,
443 unsigned start_layer
, unsigned num_layers
);
445 enum isl_aux_usage
iris_resource_render_aux_usage(struct iris_context
*ice
,
446 struct iris_resource
*res
,
447 enum isl_format render_fmt
,
449 bool draw_aux_disabled
);
450 void iris_resource_prepare_render(struct iris_context
*ice
,
451 struct iris_batch
*batch
,
452 struct iris_resource
*res
, uint32_t level
,
453 uint32_t start_layer
, uint32_t layer_count
,
454 enum isl_aux_usage aux_usage
);
455 void iris_resource_finish_render(struct iris_context
*ice
,
456 struct iris_resource
*res
, uint32_t level
,
457 uint32_t start_layer
, uint32_t layer_count
,
458 enum isl_aux_usage aux_usage
);
459 void iris_resource_prepare_depth(struct iris_context
*ice
,
460 struct iris_batch
*batch
,
461 struct iris_resource
*res
, uint32_t level
,
462 uint32_t start_layer
, uint32_t layer_count
);
463 void iris_resource_finish_depth(struct iris_context
*ice
,
464 struct iris_resource
*res
, uint32_t level
,
465 uint32_t start_layer
, uint32_t layer_count
,