src/gallium/drivers/iris/iris_resource.h

   1 /*
   2  * Copyright 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef IRIS_RESOURCE_H
  24 #define IRIS_RESOURCE_H
  25
  26 #include "pipe/p_state.h"
  27 #include "util/u_inlines.h"
  28 #include "util/u_range.h"
  29 #include "intel/isl/isl.h"
  30
  31 struct iris_batch;
  32 struct iris_context;
  33
  34 #define IRIS_MAX_MIPLEVELS 15
  35
  36 struct iris_format_info {
  37    enum isl_format fmt;
  38    struct isl_swizzle swizzle;
  39 };
  40
  41 #define IRIS_RESOURCE_FLAG_SHADER_MEMZONE  (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  42 #define IRIS_RESOURCE_FLAG_SURFACE_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  43 #define IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  44
  45 enum gen9_astc5x5_wa_tex_type {
  46    GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5 = 1 << 0,
  47    GEN9_ASTC5X5_WA_TEX_TYPE_AUX     = 1 << 1,
  48 };
  49
  50 /**
  51  * Resources represent a GPU buffer object or image (mipmap tree).
  52  *
  53  * They contain the storage (BO) and layout information (ISL surface).
  54  */
  55 struct iris_resource {
  56    struct pipe_resource base;
  57    enum pipe_format internal_format;
  58
  59    /**
  60     * The ISL surface layout information for this resource.
  61     *
  62     * This is not filled out for PIPE_BUFFER resources, but is guaranteed
  63     * to be zeroed.  Note that this also guarantees that res->surf.tiling
  64     * will be ISL_TILING_LINEAR, so it's safe to check that.
  65     */
  66    struct isl_surf surf;
  67
  68    /** Backing storage for the resource */
  69    struct iris_bo *bo;
  70
  71    /**
  72     * A bitfield of PIPE_BIND_* indicating how this resource was bound
  73     * in the past.  Only meaningful for PIPE_BUFFER; used for flushing.
  74     */
  75    unsigned bind_history;
  76
  77    /**
  78     * For PIPE_BUFFER resources, a range which may contain valid data.
  79     *
  80     * This is a conservative estimate of what part of the buffer contains
  81     * valid data that we have to preserve.  The rest of the buffer is
  82     * considered invalid, and we can promote writes to that region to
  83     * be unsynchronized writes, avoiding blit copies.
  84     */
  85    struct util_range valid_buffer_range;
  86
  87    /**
  88     * Auxiliary buffer information (CCS, MCS, or HiZ).
  89     */
  90    struct {
  91       /** The surface layout for the auxiliary buffer. */
  92       struct isl_surf surf;
  93
  94       /** The buffer object containing the auxiliary data. */
  95       struct iris_bo *bo;
  96
  97       /** Offset into 'bo' where the auxiliary surface starts. */
  98       uint32_t offset;
  99
 100       /**
 101        * Fast clear color for this surface.  For depth surfaces, the clear
 102        * value is stored as a float32 in the red component.
 103        */
 104       union isl_color_value clear_color;
 105
 106       /** Buffer object containing the indirect clear color.  */
 107       struct iris_bo *clear_color_bo;
 108
 109       /** Offset into bo where the clear color can be found.  */
 110       uint64_t clear_color_offset;
 111
 112       /**
 113        * \brief The type of auxiliary compression used by this resource.
 114        *
 115        * This describes the type of auxiliary compression that is intended to
 116        * be used by this resource.  An aux usage of ISL_AUX_USAGE_NONE means
 117        * that auxiliary compression is permanently disabled.  An aux usage
 118        * other than ISL_AUX_USAGE_NONE does not imply that auxiliary
 119        * compression will always be enabled for this surface.
 120        */
 121       enum isl_aux_usage usage;
 122
 123       /**
 124        * A bitfield of ISL_AUX_* modes that might this resource might use.
 125        *
 126        * For example, a surface might use both CCS_E and CCS_D at times.
 127        */
 128       unsigned possible_usages;
 129
 130       /**
 131        * Same as possible_usages, but only with modes supported for sampling.
 132        */
 133       unsigned sampler_usages;
 134
 135       /**
 136        * \brief Maps miptree slices to their current aux state.
 137        *
 138        * This two-dimensional array is indexed as [level][layer] and stores an
 139        * aux state for each slice.
 140        */
 141       enum isl_aux_state **state;
 142
 143       /**
 144        * If (1 << level) is set, HiZ is enabled for that miplevel.
 145        */
 146       uint16_t has_hiz;
 147    } aux;
 148
 149    /**
 150     * For external surfaces, this is DRM format modifier that was used to
 151     * create or import the surface.  For internal surfaces, this will always
 152     * be DRM_FORMAT_MOD_INVALID.
 153     */
 154    const struct isl_drm_modifier_info *mod_info;
 155 };
 156
 157 /**
 158  * A simple <resource, offset> tuple for storing a reference to a
 159  * piece of state stored in a GPU buffer object.
 160  */
 161 struct iris_state_ref {
 162    struct pipe_resource *res;
 163    uint32_t offset;
 164 };
 165
 166 /**
 167  * Gallium CSO for sampler views (texture views).
 168  *
 169  * In addition to the normal pipe_resource, this adds an ISL view
 170  * which may reinterpret the format or restrict levels/layers.
 171  *
 172  * These can also be linear texture buffers.
 173  */
 174 struct iris_sampler_view {
 175    struct pipe_sampler_view base;
 176    struct isl_view view;
 177
 178    union isl_color_value clear_color;
 179
 180    /* A short-cut (not a reference) to the actual resource being viewed.
 181     * Multi-planar (or depth+stencil) images may have multiple resources
 182     * chained together; this skips having to traverse base->texture->*.
 183     */
 184    struct iris_resource *res;
 185
 186    /** The resource (BO) holding our SURFACE_STATE. */
 187    struct iris_state_ref surface_state;
 188 };
 189
 190 /**
 191  * Image view representation.
 192  */
 193 struct iris_image_view {
 194    struct pipe_image_view base;
 195
 196    /** The resource (BO) holding our SURFACE_STATE. */
 197    struct iris_state_ref surface_state;
 198 };
 199
 200 /**
 201  * Gallium CSO for surfaces (framebuffer attachments).
 202  *
 203  * A view of a surface that can be bound to a color render target or
 204  * depth/stencil attachment.
 205  */
 206 struct iris_surface {
 207    struct pipe_surface base;
 208    struct isl_view view;
 209    union isl_color_value clear_color;
 210
 211    /** The resource (BO) holding our SURFACE_STATE. */
 212    struct iris_state_ref surface_state;
 213 };
 214
 215 /**
 216  * Transfer object - information about a buffer mapping.
 217  */
 218 struct iris_transfer {
 219    struct pipe_transfer base;
 220    struct pipe_debug_callback *dbg;
 221    void *buffer;
 222    void *ptr;
 223
 224    /** A linear staging resource for GPU-based copy_region transfers. */
 225    struct pipe_resource *staging;
 226    struct blorp_context *blorp;
 227    struct iris_batch *batch;
 228
 229    void (*unmap)(struct iris_transfer *);
 230 };
 231
 232 /**
 233  * Unwrap a pipe_resource to get the underlying iris_bo (for convenience).
 234  */
 235 static inline struct iris_bo *
 236 iris_resource_bo(struct pipe_resource *p_res)
 237 {
 238    struct iris_resource *res = (void *) p_res;
 239    return res->bo;
 240 }
 241
 242 struct iris_format_info iris_format_for_usage(const struct gen_device_info *,
 243                                               enum pipe_format pf,
 244                                               isl_surf_usage_flags_t usage);
 245
 246 struct pipe_resource *iris_resource_get_separate_stencil(struct pipe_resource *);
 247
 248 void iris_get_depth_stencil_resources(struct pipe_resource *res,
 249                                       struct iris_resource **out_z,
 250                                       struct iris_resource **out_s);
 251 bool iris_resource_set_clear_color(struct iris_context *ice,
 252                                    struct iris_resource *res,
 253                                    union isl_color_value color);
 254 union isl_color_value
 255 iris_resource_get_clear_color(const struct iris_resource *res,
 256                               struct iris_bo **clear_color_bo,
 257                               uint64_t *clear_color_offset);
 258
 259 void iris_init_screen_resource_functions(struct pipe_screen *pscreen);
 260
 261 void iris_flush_and_dirty_for_history(struct iris_context *ice,
 262                                       struct iris_batch *batch,
 263                                       struct iris_resource *res);
 264
 265 unsigned iris_get_num_logical_layers(const struct iris_resource *res,
 266                                      unsigned level);
 267
 268 void iris_resource_disable_aux(struct iris_resource *res);
 269
 270 #define INTEL_REMAINING_LAYERS UINT32_MAX
 271 #define INTEL_REMAINING_LEVELS UINT32_MAX
 272
 273 void
 274 iris_hiz_exec(struct iris_context *ice,
 275               struct iris_batch *batch,
 276               struct iris_resource *res,
 277               unsigned int level, unsigned int start_layer,
 278               unsigned int num_layers, enum isl_aux_op op,
 279               bool update_clear_depth);
 280
 281 /**
 282  * Prepare a miptree for access
 283  *
 284  * This function should be called prior to any access to miptree in order to
 285  * perform any needed resolves.
 286  *
 287  * \param[in]  start_level    The first mip level to be accessed
 288  *
 289  * \param[in]  num_levels     The number of miplevels to be accessed or
 290  *                            INTEL_REMAINING_LEVELS to indicate every level
 291  *                            above start_level will be accessed
 292  *
 293  * \param[in]  start_layer    The first array slice or 3D layer to be accessed
 294  *
 295  * \param[in]  num_layers     The number of array slices or 3D layers be
 296  *                            accessed or INTEL_REMAINING_LAYERS to indicate
 297  *                            every layer above start_layer will be accessed
 298  *
 299  * \param[in]  aux_supported  Whether or not the access will support the
 300  *                            miptree's auxiliary compression format;  this
 301  *                            must be false for uncompressed miptrees
 302  *
 303  * \param[in]  fast_clear_supported Whether or not the access will support
 304  *                                  fast clears in the miptree's auxiliary
 305  *                                  compression format
 306  */
 307 void
 308 iris_resource_prepare_access(struct iris_context *ice,
 309                              struct iris_batch *batch,
 310                              struct iris_resource *res,
 311                              uint32_t start_level, uint32_t num_levels,
 312                              uint32_t start_layer, uint32_t num_layers,
 313                              enum isl_aux_usage aux_usage,
 314                              bool fast_clear_supported);
 315
 316 /**
 317  * Complete a write operation
 318  *
 319  * This function should be called after any operation writes to a miptree.
 320  * This will update the miptree's compression state so that future resolves
 321  * happen correctly.  Technically, this function can be called before the
 322  * write occurs but the caller must ensure that they don't interlace
 323  * iris_resource_prepare_access and iris_resource_finish_write calls to
 324  * overlapping layer/level ranges.
 325  *
 326  * \param[in]  level             The mip level that was written
 327  *
 328  * \param[in]  start_layer       The first array slice or 3D layer written
 329  *
 330  * \param[in]  num_layers        The number of array slices or 3D layers
 331  *                               written or INTEL_REMAINING_LAYERS to indicate
 332  *                               every layer above start_layer was written
 333  *
 334  * \param[in]  written_with_aux  Whether or not the write was done with
 335  *                               auxiliary compression enabled
 336  */
 337 void
 338 iris_resource_finish_write(struct iris_context *ice,
 339                            struct iris_resource *res, uint32_t level,
 340                            uint32_t start_layer, uint32_t num_layers,
 341                            enum isl_aux_usage aux_usage);
 342
 343 /** Get the auxiliary compression state of a miptree slice */
 344 enum isl_aux_state
 345 iris_resource_get_aux_state(const struct iris_resource *res,
 346                             uint32_t level, uint32_t layer);
 347
 348 /**
 349  * Set the auxiliary compression state of a miptree slice range
 350  *
 351  * This function directly sets the auxiliary compression state of a slice
 352  * range of a miptree.  It only modifies data structures and does not do any
 353  * resolves.  This should only be called by code which directly performs
 354  * compression operations such as fast clears and resolves.  Most code should
 355  * use iris_resource_prepare_access or iris_resource_finish_write.
 356  */
 357 void
 358 iris_resource_set_aux_state(struct iris_context *ice,
 359                             struct iris_resource *res, uint32_t level,
 360                             uint32_t start_layer, uint32_t num_layers,
 361                             enum isl_aux_state aux_state);
 362
 363 /**
 364  * Prepare a miptree for raw access
 365  *
 366  * This helper prepares the miptree for access that knows nothing about any
 367  * sort of compression whatsoever.  This is useful when mapping the surface or
 368  * using it with the blitter.
 369  */
 370 static inline void
 371 iris_resource_access_raw(struct iris_context *ice,
 372                          struct iris_batch *batch,
 373                          struct iris_resource *res,
 374                          uint32_t level, uint32_t layer,
 375                          uint32_t num_layers,
 376                          bool write)
 377 {
 378    iris_resource_prepare_access(ice, batch, res, level, 1, layer, num_layers,
 379                                 ISL_AUX_USAGE_NONE, false);
 380    if (write) {
 381       iris_resource_finish_write(ice, res, level, layer, num_layers,
 382                                  ISL_AUX_USAGE_NONE);
 383    }
 384 }
 385
 386 enum isl_aux_usage iris_resource_texture_aux_usage(struct iris_context *ice,
 387                                                    const struct iris_resource *res,
 388                                                    enum isl_format view_fmt,
 389                                                    enum gen9_astc5x5_wa_tex_type);
 390 void iris_resource_prepare_texture(struct iris_context *ice,
 391                                    struct iris_batch *batch,
 392                                    struct iris_resource *res,
 393                                    enum isl_format view_format,
 394                                    uint32_t start_level, uint32_t num_levels,
 395                                    uint32_t start_layer, uint32_t num_layers,
 396                                    enum gen9_astc5x5_wa_tex_type);
 397 void iris_resource_prepare_image(struct iris_context *ice,
 398                                  struct iris_batch *batch,
 399                                  struct iris_resource *res);
 400
 401 void iris_resource_check_level_layer(const struct iris_resource *res,
 402                                      uint32_t level, uint32_t layer);
 403
 404 bool iris_resource_level_has_hiz(const struct iris_resource *res,
 405                                  uint32_t level);
 406
 407 enum isl_aux_usage iris_resource_render_aux_usage(struct iris_context *ice,
 408                                                   struct iris_resource *res,
 409                                                   enum isl_format render_fmt,
 410                                                   bool blend_enabled,
 411                                                   bool draw_aux_disabled);
 412 void iris_resource_prepare_render(struct iris_context *ice,
 413                                   struct iris_batch *batch,
 414                                   struct iris_resource *res, uint32_t level,
 415                                   uint32_t start_layer, uint32_t layer_count,
 416                                   enum isl_aux_usage aux_usage);
 417 void iris_resource_finish_render(struct iris_context *ice,
 418                                  struct iris_resource *res, uint32_t level,
 419                                  uint32_t start_layer, uint32_t layer_count,
 420                                  enum isl_aux_usage aux_usage);
 421 void iris_resource_prepare_depth(struct iris_context *ice,
 422                                  struct iris_batch *batch,
 423                                  struct iris_resource *res, uint32_t level,
 424                                  uint32_t start_layer, uint32_t layer_count);
 425 void iris_resource_finish_depth(struct iris_context *ice,
 426                                 struct iris_resource *res, uint32_t level,
 427                                 uint32_t start_layer, uint32_t layer_count,
 428                                 bool depth_written);
 429 #endif