src/gallium/drivers/iris/iris_screen.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 /**
  24  * @file iris_screen.c
  25  *
  26  * Screen related driver hooks and capability lists.
  27  *
  28  * A program may use multiple rendering contexts (iris_context), but
  29  * they all share a common screen (iris_screen).  Global driver state
  30  * can be stored in the screen; it may be accessed by multiple threads.
  31  */
  32
  33 #include <stdio.h>
  34 #include <errno.h>
  35 #include <sys/ioctl.h>
  36 #include "pipe/p_defines.h"
  37 #include "pipe/p_state.h"
  38 #include "pipe/p_context.h"
  39 #include "pipe/p_screen.h"
  40 #include "util/debug.h"
  41 #include "util/u_inlines.h"
  42 #include "util/u_format.h"
  43 #include "util/u_transfer_helper.h"
  44 #include "util/u_upload_mgr.h"
  45 #include "util/ralloc.h"
  46 #include "drm-uapi/i915_drm.h"
  47 #include "iris_context.h"
  48 #include "iris_defines.h"
  49 #include "iris_fence.h"
  50 #include "iris_pipe.h"
  51 #include "iris_resource.h"
  52 #include "iris_screen.h"
  53 #include "intel/compiler/brw_compiler.h"
  54
  55 static void
  56 iris_flush_frontbuffer(struct pipe_screen *_screen,
  57                        struct pipe_resource *resource,
  58                        unsigned level, unsigned layer,
  59                        void *context_private, struct pipe_box *box)
  60 {
  61 }
  62
  63 static const char *
  64 iris_get_vendor(struct pipe_screen *pscreen)
  65 {
  66    return "Mesa Project";
  67 }
  68
  69 static const char *
  70 iris_get_device_vendor(struct pipe_screen *pscreen)
  71 {
  72    return "Intel";
  73 }
  74
  75 static const char *
  76 iris_get_name(struct pipe_screen *pscreen)
  77 {
  78    struct iris_screen *screen = (struct iris_screen *)pscreen;
  79    const char *chipset;
  80
  81    switch (screen->pci_id) {
  82 #undef CHIPSET
  83 #define CHIPSET(id, symbol, str) case id: chipset = str; break;
  84 #include "pci_ids/i965_pci_ids.h"
  85    default:
  86       chipset = "Unknown Intel Chipset";
  87       break;
  88    }
  89    return &chipset[9];
  90 }
  91
  92 static int
  93 iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  94 {
  95    struct iris_screen *screen = (struct iris_screen *)pscreen;
  96    const struct gen_device_info *devinfo = &screen->devinfo;
  97
  98    switch (param) {
  99    case PIPE_CAP_NPOT_TEXTURES:
 100    case PIPE_CAP_ANISOTROPIC_FILTER:
 101    case PIPE_CAP_POINT_SPRITE:
 102    case PIPE_CAP_OCCLUSION_QUERY:
 103    case PIPE_CAP_QUERY_TIME_ELAPSED:
 104    case PIPE_CAP_TEXTURE_SWIZZLE:
 105    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 106    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 107    case PIPE_CAP_SM3:
 108    case PIPE_CAP_PRIMITIVE_RESTART:
 109    case PIPE_CAP_INDEP_BLEND_ENABLE:
 110    case PIPE_CAP_INDEP_BLEND_FUNC:
 111    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
 112    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 113    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 114    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 115    case PIPE_CAP_TGSI_INSTANCEID:
 116    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 117    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 118    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 119    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 120    case PIPE_CAP_CONDITIONAL_RENDER:
 121    case PIPE_CAP_TEXTURE_BARRIER:
 122    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 123    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 124    case PIPE_CAP_COMPUTE:
 125    case PIPE_CAP_START_INSTANCE:
 126    case PIPE_CAP_QUERY_TIMESTAMP:
 127    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 128    case PIPE_CAP_CUBE_MAP_ARRAY:
 129    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 130    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 131    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 132    case PIPE_CAP_TEXTURE_QUERY_LOD:
 133    case PIPE_CAP_SAMPLE_SHADING:
 134    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 135    case PIPE_CAP_DRAW_INDIRECT:
 136    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 137    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 138    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 139    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 140    case PIPE_CAP_ACCELERATED:
 141    case PIPE_CAP_UMA:
 142    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 143    case PIPE_CAP_CLIP_HALFZ:
 144    case PIPE_CAP_TGSI_TEXCOORD:
 145    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 146    case PIPE_CAP_DOUBLES:
 147    case PIPE_CAP_INT64:
 148    case PIPE_CAP_INT64_DIVMOD:
 149    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 150    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 151    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 152    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 153    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 154    case PIPE_CAP_CULL_DISTANCE:
 155    case PIPE_CAP_PACKED_UNIFORMS:
 156    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 157    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 158    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 159    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 160    case PIPE_CAP_POST_DEPTH_COVERAGE:
 161    case PIPE_CAP_QUERY_SO_OVERFLOW:
 162    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 163    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 164    case PIPE_CAP_TGSI_TXQS:
 165    case PIPE_CAP_TGSI_FS_FBFETCH:
 166    case PIPE_CAP_TGSI_CLOCK:
 167    case PIPE_CAP_TGSI_BALLOT:
 168    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 169    case PIPE_CAP_CLEAR_TEXTURE:
 170    case PIPE_CAP_TGSI_VOTE:
 171    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 172    case PIPE_CAP_TEXTURE_GATHER_SM5:
 173    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 174    case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
 175    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 176    case PIPE_CAP_LOAD_CONSTBUF:
 177       return true;
 178
 179    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 180       return 1;
 181    case PIPE_CAP_MAX_RENDER_TARGETS:
 182       return BRW_MAX_DRAW_BUFFERS;
 183    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 184    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 185       return 15; /* 16384x16384 */
 186    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 187       return 12; /* 2048x2048 */
 188    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 189       return 4;
 190    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 191       return 2048;
 192    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 193       return BRW_MAX_SOL_BINDINGS / IRIS_MAX_SOL_BUFFERS;
 194    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 195       return BRW_MAX_SOL_BINDINGS;
 196    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 197       return 460;
 198    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 199       return 140;
 200    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 201       /* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */
 202       return 32;
 203    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 204       /* Choose a cacheline (64 bytes) so that we can safely have the CPU and
 205        * GPU writing the same SSBO on non-coherent systems (Atom CPUs).  With
 206        * UBOs, the GPU never writes, so there's no problem.  For an SSBO, the
 207        * GPU and the CPU can be updating disjoint regions of the buffer
 208        * simultaneously and that will break if the regions overlap the same
 209        * cacheline.
 210        */
 211       return 64;
 212    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 213       return 1 << 27;
 214    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 215       return 16; // XXX: u_screen says 256 is the minimum value...
 216    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 217       return true; // XXX: ?????
 218    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 219       return IRIS_MAX_TEXTURE_BUFFER_SIZE;
 220    case PIPE_CAP_MAX_VIEWPORTS:
 221       return 16;
 222    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 223       return 256;
 224    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 225       return 1024;
 226    case PIPE_CAP_MAX_GS_INVOCATIONS:
 227       return 32;
 228    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 229       return 4;
 230    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 231       return -32;
 232    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 233       return 31;
 234    case PIPE_CAP_MAX_VERTEX_STREAMS:
 235       return 4;
 236    case PIPE_CAP_VENDOR_ID:
 237       return 0x8086;
 238    case PIPE_CAP_DEVICE_ID:
 239       return screen->pci_id;
 240    case PIPE_CAP_VIDEO_MEMORY:
 241       return 0xffffffff; // XXX: bogus
 242    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 243       return 32;
 244    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 245       /* AMD_pinned_memory assumes the flexibility of using client memory
 246        * for any buffer (incl. vertex buffers) which rules out the prospect
 247        * of using snooped buffers, as using snooped buffers without
 248        * cogniscience is likely to be detrimental to performance and require
 249        * extensive checking in the driver for correctness, e.g. to prevent
 250        * illegal snoop <-> snoop transfers.
 251        */
 252       return devinfo->has_llc;
 253
 254    // XXX: don't hardcode 00:00:02.0 PCI here
 255    case PIPE_CAP_PCI_GROUP:
 256       return 0;
 257    case PIPE_CAP_PCI_BUS:
 258       return 0;
 259    case PIPE_CAP_PCI_DEVICE:
 260       return 2;
 261    case PIPE_CAP_PCI_FUNCTION:
 262       return 0;
 263
 264    default:
 265       return u_pipe_screen_get_param_defaults(pscreen, param);
 266    }
 267    return 0;
 268 }
 269
 270 static float
 271 iris_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 272 {
 273    switch (param) {
 274    case PIPE_CAPF_MAX_LINE_WIDTH:
 275    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 276       return 7.375f;
 277
 278    case PIPE_CAPF_MAX_POINT_WIDTH:
 279    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 280       return 255.0f;
 281
 282    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 283       return 16.0f;
 284    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 285       return 15.0f;
 286    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 287    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 288    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 289       return 0.0f;
 290    default:
 291       unreachable("unknown param");
 292    }
 293 }
 294
 295 static int
 296 iris_get_shader_param(struct pipe_screen *pscreen,
 297                       enum pipe_shader_type p_stage,
 298                       enum pipe_shader_cap param)
 299 {
 300    struct iris_screen *screen = (struct iris_screen *)pscreen;
 301    struct brw_compiler *compiler = screen->compiler;
 302    gl_shader_stage stage = stage_from_pipe(p_stage);
 303
 304    /* this is probably not totally correct.. but it's a start: */
 305    switch (param) {
 306    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 307       return stage == MESA_SHADER_FRAGMENT ? 1024 : 16384;
 308    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 309    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 310    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 311       return stage == MESA_SHADER_FRAGMENT ? 1024 : 0;
 312
 313    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 314       return UINT_MAX;
 315
 316    case PIPE_SHADER_CAP_MAX_INPUTS:
 317       return stage == MESA_SHADER_VERTEX ? 16 : 32;
 318    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 319       return 32;
 320    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 321       return 16 * 1024 * sizeof(float);
 322    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 323       return 16;
 324    case PIPE_SHADER_CAP_MAX_TEMPS:
 325       return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 326    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 327       return 0;
 328    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 329    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 330    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 331    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 332       /* Lie about these to avoid st/mesa's GLSL IR lowering of indirects,
 333        * which we don't want.  Our compiler backend will check brw_compiler's
 334        * options and call nir_lower_indirect_derefs appropriately anyway.
 335        */
 336       return true;
 337    case PIPE_SHADER_CAP_SUBROUTINES:
 338       return 0;
 339    case PIPE_SHADER_CAP_INTEGERS:
 340    case PIPE_SHADER_CAP_SCALAR_ISA:
 341       return 1;
 342    case PIPE_SHADER_CAP_INT64_ATOMICS:
 343    case PIPE_SHADER_CAP_FP16:
 344       return 0;
 345    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 346    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 347    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 348       return IRIS_MAX_TEXTURE_SAMPLERS;
 349    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 350       return IRIS_MAX_ABOS + IRIS_MAX_SSBOS;
 351    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 352    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 353       return 0;
 354    case PIPE_SHADER_CAP_PREFERRED_IR:
 355       return PIPE_SHADER_IR_NIR;
 356    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 357       return 1 << PIPE_SHADER_IR_NIR;
 358    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 359       return 32;
 360    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 361    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 362    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 363    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 364    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 365    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 366    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 367    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 368       return 0;
 369    default:
 370       unreachable("unknown shader param");
 371    }
 372 }
 373
 374 static int
 375 iris_get_compute_param(struct pipe_screen *pscreen,
 376                        enum pipe_shader_ir ir_type,
 377                        enum pipe_compute_cap param,
 378                        void *ret)
 379 {
 380    struct iris_screen *screen = (struct iris_screen *)pscreen;
 381    struct brw_compiler *compiler = screen->compiler;
 382    const struct gen_device_info *devinfo = &screen->devinfo;
 383
 384    // XXX: cherryview fusing
 385
 386    const unsigned max_threads = MIN2(64, devinfo->max_cs_threads);
 387    const uint32_t max_invocations = 32 * max_threads;
 388
 389 #define RET(x) do {                  \
 390    if (ret)                          \
 391       memcpy(ret, x, sizeof(x));     \
 392    return sizeof(x);                 \
 393 } while (0)
 394
 395    switch (param) {
 396    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 397       RET((uint32_t []){ 32 });
 398
 399    case PIPE_COMPUTE_CAP_IR_TARGET:
 400       if (ret)
 401          strcpy(ret, "gen");
 402       return 4;
 403
 404    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 405       RET((uint64_t []) { 3 });
 406
 407    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 408       RET(((uint64_t []) { 65535, 65535, 65535 }));
 409
 410    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 411       /* MaxComputeWorkGroupSize[0..2] */
 412       RET(((uint64_t []) {max_invocations, max_invocations, max_invocations}));
 413
 414    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 415       /* MaxComputeWorkGroupInvocations */
 416       RET((uint64_t []) { max_invocations });
 417
 418    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 419       /* MaxComputeSharedMemorySize */
 420       RET((uint64_t []) { 64 * 1024 });
 421
 422    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 423       RET((uint32_t []) { 1 });
 424
 425    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 426       RET((uint32_t []) { BRW_SUBGROUP_SIZE });
 427
 428    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 429    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 430    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 431    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 432    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 433    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 434    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 435       // XXX: I think these are for Clover...
 436       return 0;
 437
 438    default:
 439       unreachable("unknown compute param");
 440    }
 441 }
 442
 443 static uint64_t
 444 iris_get_timestamp(struct pipe_screen *pscreen)
 445 {
 446    struct iris_screen *screen = (struct iris_screen *) pscreen;
 447    const unsigned TIMESTAMP = 0x2358;
 448    uint64_t result;
 449
 450    iris_reg_read(screen->bufmgr, TIMESTAMP | 1, &result);
 451
 452    result = iris_timebase_scale(&screen->devinfo, result);
 453    result &= (1ull << TIMESTAMP_BITS) - 1;
 454
 455    return result;
 456 }
 457
 458 static void
 459 iris_destroy_screen(struct pipe_screen *pscreen)
 460 {
 461    struct iris_screen *screen = (struct iris_screen *) pscreen;
 462    iris_bo_unreference(screen->workaround_bo);
 463    u_transfer_helper_destroy(pscreen->transfer_helper);
 464    ralloc_free(screen);
 465 }
 466
 467 static void
 468 iris_query_memory_info(struct pipe_screen *pscreen,
 469                        struct pipe_memory_info *info)
 470 {
 471 }
 472
 473 static const void *
 474 iris_get_compiler_options(struct pipe_screen *pscreen,
 475                           enum pipe_shader_ir ir,
 476                           enum pipe_shader_type pstage)
 477 {
 478    struct iris_screen *screen = (struct iris_screen *) pscreen;
 479    gl_shader_stage stage = stage_from_pipe(pstage);
 480    assert(ir == PIPE_SHADER_IR_NIR);
 481
 482    return screen->compiler->glsl_compiler_options[stage].NirOptions;
 483 }
 484
 485 static int
 486 iris_getparam(struct iris_screen *screen, int param, int *value)
 487 {
 488    struct drm_i915_getparam gp = { .param = param, .value = value };
 489
 490    if (ioctl(screen->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1)
 491       return -errno;
 492
 493    return 0;
 494 }
 495
 496 static bool
 497 iris_getparam_boolean(struct iris_screen *screen, int param)
 498 {
 499    int value = 0;
 500    return (iris_getparam(screen, param, &value) == 0) && value;
 501 }
 502
 503 static int
 504 iris_getparam_integer(struct iris_screen *screen, int param)
 505 {
 506    int value = -1;
 507
 508    if (iris_getparam(screen, param, &value) == 0)
 509       return value;
 510
 511    return -1;
 512 }
 513
 514 static void
 515 iris_shader_debug_log(void *data, const char *fmt, ...)
 516 {
 517    struct pipe_debug_callback *dbg = data;
 518    unsigned id = 0;
 519    va_list args;
 520
 521    if (!dbg->debug_message)
 522       return;
 523
 524    va_start(args, fmt);
 525    dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_SHADER_INFO, fmt, args);
 526    va_end(args);
 527 }
 528
 529 static void
 530 iris_shader_perf_log(void *data, const char *fmt, ...)
 531 {
 532    struct pipe_debug_callback *dbg = data;
 533    unsigned id = 0;
 534    va_list args;
 535
 536    if (!dbg->debug_message)
 537       return;
 538
 539    va_start(args, fmt);
 540    dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args);
 541    va_end(args);
 542 }
 543
 544 struct pipe_screen *
 545 iris_screen_create(int fd)
 546 {
 547    struct iris_screen *screen = rzalloc(NULL, struct iris_screen);
 548    if (!screen)
 549       return NULL;
 550
 551    screen->fd = fd;
 552    screen->pci_id = iris_getparam_integer(screen, I915_PARAM_CHIPSET_ID);
 553
 554    if (!gen_get_device_info(screen->pci_id, &screen->devinfo))
 555       return NULL;
 556
 557    screen->devinfo.timestamp_frequency =
 558       iris_getparam_integer(screen, I915_PARAM_CS_TIMESTAMP_FREQUENCY);
 559
 560    screen->bufmgr = iris_bufmgr_init(&screen->devinfo, fd);
 561    if (!screen->bufmgr)
 562       return NULL;
 563
 564    screen->workaround_bo =
 565       iris_bo_alloc(screen->bufmgr, "workaround", 4096, IRIS_MEMZONE_OTHER);
 566    if (!screen->workaround_bo)
 567       return NULL;
 568
 569    brw_process_intel_debug_variable();
 570
 571    screen->precompile = env_var_as_boolean("shader_precompile", true);
 572
 573    bool hw_has_swizzling = false; // XXX: detect?
 574    isl_device_init(&screen->isl_dev, &screen->devinfo, hw_has_swizzling);
 575
 576    screen->compiler = brw_compiler_create(screen, &screen->devinfo);
 577    screen->compiler->shader_debug_log = iris_shader_debug_log;
 578    screen->compiler->shader_perf_log = iris_shader_perf_log;
 579    screen->compiler->supports_pull_constants = false;
 580
 581    slab_create_parent(&screen->transfer_pool,
 582                       sizeof(struct iris_transfer), 64);
 583
 584    screen->subslice_total =
 585       iris_getparam_integer(screen, I915_PARAM_SUBSLICE_TOTAL);
 586    assert(screen->subslice_total >= 1);
 587
 588    struct pipe_screen *pscreen = &screen->base;
 589
 590    iris_init_screen_fence_functions(pscreen);
 591    iris_init_screen_resource_functions(pscreen);
 592
 593    pscreen->destroy = iris_destroy_screen;
 594    pscreen->get_name = iris_get_name;
 595    pscreen->get_vendor = iris_get_vendor;
 596    pscreen->get_device_vendor = iris_get_device_vendor;
 597    pscreen->get_param = iris_get_param;
 598    pscreen->get_shader_param = iris_get_shader_param;
 599    pscreen->get_compute_param = iris_get_compute_param;
 600    pscreen->get_paramf = iris_get_paramf;
 601    pscreen->get_compiler_options = iris_get_compiler_options;
 602    pscreen->is_format_supported = iris_is_format_supported;
 603    pscreen->context_create = iris_create_context;
 604    pscreen->flush_frontbuffer = iris_flush_frontbuffer;
 605    pscreen->get_timestamp = iris_get_timestamp;
 606    pscreen->query_memory_info = iris_query_memory_info;
 607
 608    return pscreen;
 609 }