src/gallium/drivers/iris/iris_screen.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 /**
  24  * @file iris_screen.c
  25  *
  26  * Screen related driver hooks and capability lists.
  27  *
  28  * A program may use multiple rendering contexts (iris_context), but
  29  * they all share a common screen (iris_screen).  Global driver state
  30  * can be stored in the screen; it may be accessed by multiple threads.
  31  */
  32
  33 #include <stdio.h>
  34 #include <errno.h>
  35 #include <sys/ioctl.h>
  36 #include "pipe/p_defines.h"
  37 #include "pipe/p_state.h"
  38 #include "pipe/p_context.h"
  39 #include "pipe/p_screen.h"
  40 #include "util/debug.h"
  41 #include "util/u_inlines.h"
  42 #include "util/u_format.h"
  43 #include "util/u_transfer_helper.h"
  44 #include "util/u_upload_mgr.h"
  45 #include "util/ralloc.h"
  46 #include "util/xmlconfig.h"
  47 #include "drm-uapi/i915_drm.h"
  48 #include "iris_context.h"
  49 #include "iris_defines.h"
  50 #include "iris_fence.h"
  51 #include "iris_pipe.h"
  52 #include "iris_resource.h"
  53 #include "iris_screen.h"
  54 #include "intel/compiler/brw_compiler.h"
  55 #include "intel/common/gen_gem.h"
  56
  57 static void
  58 iris_flush_frontbuffer(struct pipe_screen *_screen,
  59                        struct pipe_resource *resource,
  60                        unsigned level, unsigned layer,
  61                        void *context_private, struct pipe_box *box)
  62 {
  63 }
  64
  65 static const char *
  66 iris_get_vendor(struct pipe_screen *pscreen)
  67 {
  68    return "Intel";
  69 }
  70
  71 static const char *
  72 iris_get_device_vendor(struct pipe_screen *pscreen)
  73 {
  74    return "Intel";
  75 }
  76
  77 static const char *
  78 iris_get_name(struct pipe_screen *pscreen)
  79 {
  80    struct iris_screen *screen = (struct iris_screen *)pscreen;
  81    static char buf[128];
  82    const char *chipset;
  83
  84    switch (screen->pci_id) {
  85 #undef CHIPSET
  86 #define CHIPSET(id, symbol, str) case id: chipset = str; break;
  87 #include "pci_ids/i965_pci_ids.h"
  88    default:
  89       chipset = "Unknown Intel Chipset";
  90       break;
  91    }
  92
  93    snprintf(buf, sizeof(buf), "Mesa %s", chipset);
  94    return buf;
  95 }
  96
  97 static uint64_t
  98 get_aperture_size(int fd)
  99 {
 100    struct drm_i915_gem_get_aperture aperture = {};
 101    gen_ioctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
 102    return aperture.aper_size;
 103 }
 104
 105 static int
 106 iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 107 {
 108    struct iris_screen *screen = (struct iris_screen *)pscreen;
 109    const struct gen_device_info *devinfo = &screen->devinfo;
 110
 111    switch (param) {
 112    case PIPE_CAP_NPOT_TEXTURES:
 113    case PIPE_CAP_ANISOTROPIC_FILTER:
 114    case PIPE_CAP_POINT_SPRITE:
 115    case PIPE_CAP_OCCLUSION_QUERY:
 116    case PIPE_CAP_QUERY_TIME_ELAPSED:
 117    case PIPE_CAP_TEXTURE_SWIZZLE:
 118    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 119    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 120    case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
 121    case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
 122    case PIPE_CAP_VERTEX_SHADER_SATURATE:
 123    case PIPE_CAP_PRIMITIVE_RESTART:
 124    case PIPE_CAP_INDEP_BLEND_ENABLE:
 125    case PIPE_CAP_INDEP_BLEND_FUNC:
 126    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
 127    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 128    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 129    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 130    case PIPE_CAP_TGSI_INSTANCEID:
 131    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 132    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 133    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 134    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 135    case PIPE_CAP_CONDITIONAL_RENDER:
 136    case PIPE_CAP_TEXTURE_BARRIER:
 137    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 138    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 139    case PIPE_CAP_COMPUTE:
 140    case PIPE_CAP_START_INSTANCE:
 141    case PIPE_CAP_QUERY_TIMESTAMP:
 142    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 143    case PIPE_CAP_CUBE_MAP_ARRAY:
 144    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 145    case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
 146    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 147    case PIPE_CAP_TEXTURE_QUERY_LOD:
 148    case PIPE_CAP_SAMPLE_SHADING:
 149    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 150    case PIPE_CAP_DRAW_INDIRECT:
 151    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 152    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 153    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 154    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 155    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 156    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 157    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 158    case PIPE_CAP_ACCELERATED:
 159    case PIPE_CAP_UMA:
 160    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 161    case PIPE_CAP_CLIP_HALFZ:
 162    case PIPE_CAP_TGSI_TEXCOORD:
 163    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 164    case PIPE_CAP_DOUBLES:
 165    case PIPE_CAP_INT64:
 166    case PIPE_CAP_INT64_DIVMOD:
 167    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 168    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 169    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 170    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 171    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 172    case PIPE_CAP_CULL_DISTANCE:
 173    case PIPE_CAP_PACKED_UNIFORMS:
 174    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 175    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 176    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 177    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 178    case PIPE_CAP_QUERY_SO_OVERFLOW:
 179    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 180    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 181    case PIPE_CAP_TGSI_TXQS:
 182    case PIPE_CAP_TGSI_CLOCK:
 183    case PIPE_CAP_TGSI_BALLOT:
 184    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 185    case PIPE_CAP_CLEAR_TEXTURE:
 186    case PIPE_CAP_TGSI_VOTE:
 187    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 188    case PIPE_CAP_TEXTURE_GATHER_SM5:
 189    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 190    case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
 191    case PIPE_CAP_LOAD_CONSTBUF:
 192    case PIPE_CAP_NIR_COMPACT_ARRAYS:
 193    case PIPE_CAP_DRAW_PARAMETERS:
 194    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 195    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 196    case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
 197    case PIPE_CAP_INVALIDATE_BUFFER:
 198    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 199    case PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED:
 200    case PIPE_CAP_TEXTURE_SHADOW_LOD:
 201    case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
 202       return true;
 203    case PIPE_CAP_FBFETCH:
 204       /* TODO: Support non-coherent FB fetch on Broadwell */
 205       return devinfo->gen >= 9 ? BRW_MAX_DRAW_BUFFERS : 0;
 206    case PIPE_CAP_FBFETCH_COHERENT:
 207    case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE:
 208    case PIPE_CAP_POST_DEPTH_COVERAGE:
 209    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 210    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 211    case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK:
 212    case PIPE_CAP_ATOMIC_FLOAT_MINMAX:
 213       return devinfo->gen >= 9;
 214    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 215       return 1;
 216    case PIPE_CAP_MAX_RENDER_TARGETS:
 217       return BRW_MAX_DRAW_BUFFERS;
 218    case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 219       return 16384;
 220    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 221       return IRIS_MAX_MIPLEVELS; /* 16384x16384 */
 222    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 223       return 12; /* 2048x2048 */
 224    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 225       return 4;
 226    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 227       return 2048;
 228    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 229       return BRW_MAX_SOL_BINDINGS / IRIS_MAX_SOL_BUFFERS;
 230    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 231       return BRW_MAX_SOL_BINDINGS;
 232    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 233    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 234       return 460;
 235    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 236       /* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */
 237       return 32;
 238    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 239       return IRIS_MAP_BUFFER_ALIGNMENT;
 240    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 241       /* Choose a cacheline (64 bytes) so that we can safely have the CPU and
 242        * GPU writing the same SSBO on non-coherent systems (Atom CPUs).  With
 243        * UBOs, the GPU never writes, so there's no problem.  For an SSBO, the
 244        * GPU and the CPU can be updating disjoint regions of the buffer
 245        * simultaneously and that will break if the regions overlap the same
 246        * cacheline.
 247        */
 248       return 64;
 249    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 250       return 1 << 27;
 251    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 252       return 16; // XXX: u_screen says 256 is the minimum value...
 253    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 254       return true;
 255    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 256       return IRIS_MAX_TEXTURE_BUFFER_SIZE;
 257    case PIPE_CAP_MAX_VIEWPORTS:
 258       return 16;
 259    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 260       return 256;
 261    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 262       return 1024;
 263    case PIPE_CAP_MAX_GS_INVOCATIONS:
 264       return 32;
 265    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 266       return 4;
 267    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 268       return -32;
 269    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 270       return 31;
 271    case PIPE_CAP_MAX_VERTEX_STREAMS:
 272       return 4;
 273    case PIPE_CAP_VENDOR_ID:
 274       return 0x8086;
 275    case PIPE_CAP_DEVICE_ID:
 276       return screen->pci_id;
 277    case PIPE_CAP_VIDEO_MEMORY: {
 278       /* Once a batch uses more than 75% of the maximum mappable size, we
 279        * assume that there's some fragmentation, and we start doing extra
 280        * flushing, etc.  That's the big cliff apps will care about.
 281        */
 282       const unsigned gpu_mappable_megabytes =
 283          (screen->aperture_bytes * 3 / 4) / (1024 * 1024);
 284
 285       const long system_memory_pages = sysconf(_SC_PHYS_PAGES);
 286       const long system_page_size = sysconf(_SC_PAGE_SIZE);
 287
 288       if (system_memory_pages <= 0 || system_page_size <= 0)
 289          return -1;
 290
 291       const uint64_t system_memory_bytes =
 292          (uint64_t) system_memory_pages * (uint64_t) system_page_size;
 293
 294       const unsigned system_memory_megabytes =
 295          (unsigned) (system_memory_bytes / (1024 * 1024));
 296
 297       return MIN2(system_memory_megabytes, gpu_mappable_megabytes);
 298    }
 299    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 300    case PIPE_CAP_MAX_VARYINGS:
 301       return 32;
 302    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 303       /* AMD_pinned_memory assumes the flexibility of using client memory
 304        * for any buffer (incl. vertex buffers) which rules out the prospect
 305        * of using snooped buffers, as using snooped buffers without
 306        * cogniscience is likely to be detrimental to performance and require
 307        * extensive checking in the driver for correctness, e.g. to prevent
 308        * illegal snoop <-> snoop transfers.
 309        */
 310       return devinfo->has_llc;
 311
 312    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 313       return PIPE_CONTEXT_PRIORITY_LOW |
 314              PIPE_CONTEXT_PRIORITY_MEDIUM |
 315              PIPE_CONTEXT_PRIORITY_HIGH;
 316
 317    // XXX: don't hardcode 00:00:02.0 PCI here
 318    case PIPE_CAP_PCI_GROUP:
 319       return 0;
 320    case PIPE_CAP_PCI_BUS:
 321       return 0;
 322    case PIPE_CAP_PCI_DEVICE:
 323       return 2;
 324    case PIPE_CAP_PCI_FUNCTION:
 325       return 0;
 326
 327    default:
 328       return u_pipe_screen_get_param_defaults(pscreen, param);
 329    }
 330    return 0;
 331 }
 332
 333 static float
 334 iris_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 335 {
 336    switch (param) {
 337    case PIPE_CAPF_MAX_LINE_WIDTH:
 338    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 339       return 7.375f;
 340
 341    case PIPE_CAPF_MAX_POINT_WIDTH:
 342    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 343       return 255.0f;
 344
 345    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 346       return 16.0f;
 347    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 348       return 15.0f;
 349    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 350    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 351    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 352       return 0.0f;
 353    default:
 354       unreachable("unknown param");
 355    }
 356 }
 357
 358 static int
 359 iris_get_shader_param(struct pipe_screen *pscreen,
 360                       enum pipe_shader_type p_stage,
 361                       enum pipe_shader_cap param)
 362 {
 363    gl_shader_stage stage = stage_from_pipe(p_stage);
 364
 365    /* this is probably not totally correct.. but it's a start: */
 366    switch (param) {
 367    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 368       return stage == MESA_SHADER_FRAGMENT ? 1024 : 16384;
 369    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 370    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 371    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 372       return stage == MESA_SHADER_FRAGMENT ? 1024 : 0;
 373
 374    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 375       return UINT_MAX;
 376
 377    case PIPE_SHADER_CAP_MAX_INPUTS:
 378       return stage == MESA_SHADER_VERTEX ? 16 : 32;
 379    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 380       return 32;
 381    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 382       return 16 * 1024 * sizeof(float);
 383    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 384       return 16;
 385    case PIPE_SHADER_CAP_MAX_TEMPS:
 386       return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 387    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 388       return 0;
 389    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 390    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 391    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 392    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 393       /* Lie about these to avoid st/mesa's GLSL IR lowering of indirects,
 394        * which we don't want.  Our compiler backend will check brw_compiler's
 395        * options and call nir_lower_indirect_derefs appropriately anyway.
 396        */
 397       return true;
 398    case PIPE_SHADER_CAP_SUBROUTINES:
 399       return 0;
 400    case PIPE_SHADER_CAP_INTEGERS:
 401    case PIPE_SHADER_CAP_SCALAR_ISA:
 402       return 1;
 403    case PIPE_SHADER_CAP_INT64_ATOMICS:
 404    case PIPE_SHADER_CAP_FP16:
 405       return 0;
 406    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 407    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 408    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 409       return IRIS_MAX_TEXTURE_SAMPLERS;
 410    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 411       return IRIS_MAX_ABOS + IRIS_MAX_SSBOS;
 412    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 413    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 414       return 0;
 415    case PIPE_SHADER_CAP_PREFERRED_IR:
 416       return PIPE_SHADER_IR_NIR;
 417    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 418       return 1 << PIPE_SHADER_IR_NIR;
 419    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 420    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 421       return 1;
 422    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 423    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 424    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 425    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 426    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 427    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 428    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 429       return 0;
 430    default:
 431       unreachable("unknown shader param");
 432    }
 433 }
 434
 435 static int
 436 iris_get_compute_param(struct pipe_screen *pscreen,
 437                        enum pipe_shader_ir ir_type,
 438                        enum pipe_compute_cap param,
 439                        void *ret)
 440 {
 441    struct iris_screen *screen = (struct iris_screen *)pscreen;
 442    const struct gen_device_info *devinfo = &screen->devinfo;
 443
 444    const unsigned max_threads = MIN2(64, devinfo->max_cs_threads);
 445    const uint32_t max_invocations = 32 * max_threads;
 446
 447 #define RET(x) do {                  \
 448    if (ret)                          \
 449       memcpy(ret, x, sizeof(x));     \
 450    return sizeof(x);                 \
 451 } while (0)
 452
 453    switch (param) {
 454    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 455       RET((uint32_t []){ 32 });
 456
 457    case PIPE_COMPUTE_CAP_IR_TARGET:
 458       if (ret)
 459          strcpy(ret, "gen");
 460       return 4;
 461
 462    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 463       RET((uint64_t []) { 3 });
 464
 465    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 466       RET(((uint64_t []) { 65535, 65535, 65535 }));
 467
 468    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 469       /* MaxComputeWorkGroupSize[0..2] */
 470       RET(((uint64_t []) {max_invocations, max_invocations, max_invocations}));
 471
 472    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 473       /* MaxComputeWorkGroupInvocations */
 474       RET((uint64_t []) { max_invocations });
 475
 476    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 477       /* MaxComputeSharedMemorySize */
 478       RET((uint64_t []) { 64 * 1024 });
 479
 480    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 481       RET((uint32_t []) { 1 });
 482
 483    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 484       RET((uint32_t []) { BRW_SUBGROUP_SIZE });
 485
 486    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 487    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 488    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 489    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 490    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 491    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 492    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 493       // XXX: I think these are for Clover...
 494       return 0;
 495
 496    default:
 497       unreachable("unknown compute param");
 498    }
 499 }
 500
 501 static uint64_t
 502 iris_get_timestamp(struct pipe_screen *pscreen)
 503 {
 504    struct iris_screen *screen = (struct iris_screen *) pscreen;
 505    const unsigned TIMESTAMP = 0x2358;
 506    uint64_t result;
 507
 508    iris_reg_read(screen->bufmgr, TIMESTAMP | 1, &result);
 509
 510    result = gen_device_info_timebase_scale(&screen->devinfo, result);
 511    result &= (1ull << TIMESTAMP_BITS) - 1;
 512
 513    return result;
 514 }
 515
 516 static void
 517 iris_destroy_screen(struct pipe_screen *pscreen)
 518 {
 519    struct iris_screen *screen = (struct iris_screen *) pscreen;
 520    iris_bo_unreference(screen->workaround_bo);
 521    u_transfer_helper_destroy(pscreen->transfer_helper);
 522    iris_bufmgr_destroy(screen->bufmgr);
 523    disk_cache_destroy(screen->disk_cache);
 524    ralloc_free(screen);
 525 }
 526
 527 static void
 528 iris_query_memory_info(struct pipe_screen *pscreen,
 529                        struct pipe_memory_info *info)
 530 {
 531 }
 532
 533 static const void *
 534 iris_get_compiler_options(struct pipe_screen *pscreen,
 535                           enum pipe_shader_ir ir,
 536                           enum pipe_shader_type pstage)
 537 {
 538    struct iris_screen *screen = (struct iris_screen *) pscreen;
 539    gl_shader_stage stage = stage_from_pipe(pstage);
 540    assert(ir == PIPE_SHADER_IR_NIR);
 541
 542    return screen->compiler->glsl_compiler_options[stage].NirOptions;
 543 }
 544
 545 static struct disk_cache *
 546 iris_get_disk_shader_cache(struct pipe_screen *pscreen)
 547 {
 548    struct iris_screen *screen = (struct iris_screen *) pscreen;
 549    return screen->disk_cache;
 550 }
 551
 552 static int
 553 iris_getparam(struct iris_screen *screen, int param, int *value)
 554 {
 555    struct drm_i915_getparam gp = { .param = param, .value = value };
 556
 557    if (ioctl(screen->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1)
 558       return -errno;
 559
 560    return 0;
 561 }
 562
 563 static int
 564 iris_getparam_integer(struct iris_screen *screen, int param)
 565 {
 566    int value = -1;
 567
 568    if (iris_getparam(screen, param, &value) == 0)
 569       return value;
 570
 571    return -1;
 572 }
 573
 574 static void
 575 iris_shader_debug_log(void *data, const char *fmt, ...)
 576 {
 577    struct pipe_debug_callback *dbg = data;
 578    unsigned id = 0;
 579    va_list args;
 580
 581    if (!dbg->debug_message)
 582       return;
 583
 584    va_start(args, fmt);
 585    dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_SHADER_INFO, fmt, args);
 586    va_end(args);
 587 }
 588
 589 static void
 590 iris_shader_perf_log(void *data, const char *fmt, ...)
 591 {
 592    struct pipe_debug_callback *dbg = data;
 593    unsigned id = 0;
 594    va_list args;
 595    va_start(args, fmt);
 596
 597    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
 598       va_list args_copy;
 599       va_copy(args_copy, args);
 600       vfprintf(stderr, fmt, args_copy);
 601       va_end(args_copy);
 602    }
 603
 604    if (dbg->debug_message) {
 605       dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args);
 606    }
 607
 608    va_end(args);
 609 }
 610
 611 struct pipe_screen *
 612 iris_screen_create(int fd, const struct pipe_screen_config *config)
 613 {
 614    struct iris_screen *screen = rzalloc(NULL, struct iris_screen);
 615    if (!screen)
 616       return NULL;
 617
 618    screen->fd = fd;
 619
 620    if (!gen_get_device_info_from_fd(fd, &screen->devinfo))
 621       return NULL;
 622    screen->pci_id = screen->devinfo.chipset_id;
 623    screen->no_hw = screen->devinfo.no_hw;
 624
 625    if (screen->devinfo.gen < 8 || screen->devinfo.is_cherryview)
 626       return NULL;
 627
 628    screen->aperture_bytes = get_aperture_size(fd);
 629
 630    if (getenv("INTEL_NO_HW") != NULL)
 631       screen->no_hw = true;
 632
 633    screen->bufmgr = iris_bufmgr_init(&screen->devinfo, fd);
 634    if (!screen->bufmgr)
 635       return NULL;
 636
 637    screen->workaround_bo =
 638       iris_bo_alloc(screen->bufmgr, "workaround", 4096, IRIS_MEMZONE_OTHER);
 639    if (!screen->workaround_bo)
 640       return NULL;
 641
 642    brw_process_intel_debug_variable();
 643
 644    screen->driconf.dual_color_blend_by_location =
 645       driQueryOptionb(config->options, "dual_color_blend_by_location");
 646
 647    screen->precompile = env_var_as_boolean("shader_precompile", true);
 648
 649    isl_device_init(&screen->isl_dev, &screen->devinfo, false);
 650
 651    screen->compiler = brw_compiler_create(screen, &screen->devinfo);
 652    screen->compiler->shader_debug_log = iris_shader_debug_log;
 653    screen->compiler->shader_perf_log = iris_shader_perf_log;
 654    screen->compiler->supports_pull_constants = false;
 655    screen->compiler->supports_shader_constants = true;
 656
 657    iris_disk_cache_init(screen);
 658
 659    slab_create_parent(&screen->transfer_pool,
 660                       sizeof(struct iris_transfer), 64);
 661
 662    screen->subslice_total =
 663       iris_getparam_integer(screen, I915_PARAM_SUBSLICE_TOTAL);
 664    assert(screen->subslice_total >= 1);
 665
 666    struct pipe_screen *pscreen = &screen->base;
 667
 668    iris_init_screen_fence_functions(pscreen);
 669    iris_init_screen_resource_functions(pscreen);
 670
 671    pscreen->destroy = iris_destroy_screen;
 672    pscreen->get_name = iris_get_name;
 673    pscreen->get_vendor = iris_get_vendor;
 674    pscreen->get_device_vendor = iris_get_device_vendor;
 675    pscreen->get_param = iris_get_param;
 676    pscreen->get_shader_param = iris_get_shader_param;
 677    pscreen->get_compute_param = iris_get_compute_param;
 678    pscreen->get_paramf = iris_get_paramf;
 679    pscreen->get_compiler_options = iris_get_compiler_options;
 680    pscreen->get_disk_shader_cache = iris_get_disk_shader_cache;
 681    pscreen->is_format_supported = iris_is_format_supported;
 682    pscreen->context_create = iris_create_context;
 683    pscreen->flush_frontbuffer = iris_flush_frontbuffer;
 684    pscreen->get_timestamp = iris_get_timestamp;
 685    pscreen->query_memory_info = iris_query_memory_info;
 686
 687    return pscreen;
 688 }