src/gallium/drivers/iris/iris_screen.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 /**
  24  * @file iris_screen.c
  25  *
  26  * Screen related driver hooks and capability lists.
  27  *
  28  * A program may use multiple rendering contexts (iris_context), but
  29  * they all share a common screen (iris_screen).  Global driver state
  30  * can be stored in the screen; it may be accessed by multiple threads.
  31  */
  32
  33 #include <stdio.h>
  34 #include <errno.h>
  35 #include <sys/ioctl.h>
  36 #include "pipe/p_defines.h"
  37 #include "pipe/p_state.h"
  38 #include "pipe/p_context.h"
  39 #include "pipe/p_screen.h"
  40 #include "util/debug.h"
  41 #include "util/u_inlines.h"
  42 #include "util/u_format.h"
  43 #include "util/u_transfer_helper.h"
  44 #include "util/u_upload_mgr.h"
  45 #include "util/ralloc.h"
  46 #include "util/xmlconfig.h"
  47 #include "drm-uapi/i915_drm.h"
  48 #include "iris_context.h"
  49 #include "iris_defines.h"
  50 #include "iris_fence.h"
  51 #include "iris_pipe.h"
  52 #include "iris_resource.h"
  53 #include "iris_screen.h"
  54 #include "intel/compiler/brw_compiler.h"
  55 #include "intel/common/gen_gem.h"
  56 #include "iris_monitor.h"
  57
  58 static void
  59 iris_flush_frontbuffer(struct pipe_screen *_screen,
  60                        struct pipe_resource *resource,
  61                        unsigned level, unsigned layer,
  62                        void *context_private, struct pipe_box *box)
  63 {
  64 }
  65
  66 static const char *
  67 iris_get_vendor(struct pipe_screen *pscreen)
  68 {
  69    return "Intel";
  70 }
  71
  72 static const char *
  73 iris_get_device_vendor(struct pipe_screen *pscreen)
  74 {
  75    return "Intel";
  76 }
  77
  78 static const char *
  79 iris_get_name(struct pipe_screen *pscreen)
  80 {
  81    struct iris_screen *screen = (struct iris_screen *)pscreen;
  82    static char buf[128];
  83    const char *chipset;
  84
  85    switch (screen->pci_id) {
  86 #undef CHIPSET
  87 #define CHIPSET(id, symbol, str) case id: chipset = str; break;
  88 #include "pci_ids/i965_pci_ids.h"
  89    default:
  90       chipset = "Unknown Intel Chipset";
  91       break;
  92    }
  93
  94    snprintf(buf, sizeof(buf), "Mesa %s", chipset);
  95    return buf;
  96 }
  97
  98 static uint64_t
  99 get_aperture_size(int fd)
 100 {
 101    struct drm_i915_gem_get_aperture aperture = {};
 102    gen_ioctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
 103    return aperture.aper_size;
 104 }
 105
 106 static int
 107 iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 108 {
 109    struct iris_screen *screen = (struct iris_screen *)pscreen;
 110    const struct gen_device_info *devinfo = &screen->devinfo;
 111
 112    switch (param) {
 113    case PIPE_CAP_NPOT_TEXTURES:
 114    case PIPE_CAP_ANISOTROPIC_FILTER:
 115    case PIPE_CAP_POINT_SPRITE:
 116    case PIPE_CAP_OCCLUSION_QUERY:
 117    case PIPE_CAP_QUERY_TIME_ELAPSED:
 118    case PIPE_CAP_TEXTURE_SWIZZLE:
 119    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 120    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 121    case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
 122    case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
 123    case PIPE_CAP_VERTEX_SHADER_SATURATE:
 124    case PIPE_CAP_PRIMITIVE_RESTART:
 125    case PIPE_CAP_INDEP_BLEND_ENABLE:
 126    case PIPE_CAP_INDEP_BLEND_FUNC:
 127    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
 128    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 129    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 130    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 131    case PIPE_CAP_TGSI_INSTANCEID:
 132    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 133    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 134    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 135    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 136    case PIPE_CAP_CONDITIONAL_RENDER:
 137    case PIPE_CAP_TEXTURE_BARRIER:
 138    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 139    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 140    case PIPE_CAP_COMPUTE:
 141    case PIPE_CAP_START_INSTANCE:
 142    case PIPE_CAP_QUERY_TIMESTAMP:
 143    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 144    case PIPE_CAP_CUBE_MAP_ARRAY:
 145    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 146    case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
 147    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 148    case PIPE_CAP_TEXTURE_QUERY_LOD:
 149    case PIPE_CAP_SAMPLE_SHADING:
 150    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 151    case PIPE_CAP_DRAW_INDIRECT:
 152    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 153    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 154    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 155    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 156    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 157    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 158    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 159    case PIPE_CAP_ACCELERATED:
 160    case PIPE_CAP_UMA:
 161    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 162    case PIPE_CAP_CLIP_HALFZ:
 163    case PIPE_CAP_TGSI_TEXCOORD:
 164    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 165    case PIPE_CAP_DOUBLES:
 166    case PIPE_CAP_INT64:
 167    case PIPE_CAP_INT64_DIVMOD:
 168    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 169    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 170    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 171    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 172    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 173    case PIPE_CAP_CULL_DISTANCE:
 174    case PIPE_CAP_PACKED_UNIFORMS:
 175    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 176    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 177    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 178    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 179    case PIPE_CAP_QUERY_SO_OVERFLOW:
 180    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 181    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 182    case PIPE_CAP_TGSI_TXQS:
 183    case PIPE_CAP_TGSI_CLOCK:
 184    case PIPE_CAP_TGSI_BALLOT:
 185    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 186    case PIPE_CAP_CLEAR_TEXTURE:
 187    case PIPE_CAP_TGSI_VOTE:
 188    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 189    case PIPE_CAP_TEXTURE_GATHER_SM5:
 190    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 191    case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
 192    case PIPE_CAP_LOAD_CONSTBUF:
 193    case PIPE_CAP_NIR_COMPACT_ARRAYS:
 194    case PIPE_CAP_DRAW_PARAMETERS:
 195    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 196    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 197    case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
 198    case PIPE_CAP_INVALIDATE_BUFFER:
 199    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 200    case PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED:
 201    case PIPE_CAP_TEXTURE_SHADOW_LOD:
 202    case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
 203       return true;
 204    case PIPE_CAP_FBFETCH:
 205       /* TODO: Support non-coherent FB fetch on Broadwell */
 206       return devinfo->gen >= 9 ? BRW_MAX_DRAW_BUFFERS : 0;
 207    case PIPE_CAP_FBFETCH_COHERENT:
 208    case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE:
 209    case PIPE_CAP_POST_DEPTH_COVERAGE:
 210    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 211    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 212    case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK:
 213    case PIPE_CAP_ATOMIC_FLOAT_MINMAX:
 214       return devinfo->gen >= 9;
 215    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 216       return 1;
 217    case PIPE_CAP_MAX_RENDER_TARGETS:
 218       return BRW_MAX_DRAW_BUFFERS;
 219    case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 220       return 16384;
 221    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 222       return IRIS_MAX_MIPLEVELS; /* 16384x16384 */
 223    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 224       return 12; /* 2048x2048 */
 225    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 226       return 4;
 227    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 228       return 2048;
 229    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 230       return BRW_MAX_SOL_BINDINGS / IRIS_MAX_SOL_BUFFERS;
 231    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 232       return BRW_MAX_SOL_BINDINGS;
 233    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 234    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 235       return 460;
 236    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 237       /* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */
 238       return 32;
 239    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 240       return IRIS_MAP_BUFFER_ALIGNMENT;
 241    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 242       /* Choose a cacheline (64 bytes) so that we can safely have the CPU and
 243        * GPU writing the same SSBO on non-coherent systems (Atom CPUs).  With
 244        * UBOs, the GPU never writes, so there's no problem.  For an SSBO, the
 245        * GPU and the CPU can be updating disjoint regions of the buffer
 246        * simultaneously and that will break if the regions overlap the same
 247        * cacheline.
 248        */
 249       return 64;
 250    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 251       return 1 << 27;
 252    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 253       return 16; // XXX: u_screen says 256 is the minimum value...
 254    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 255       return true;
 256    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 257       return IRIS_MAX_TEXTURE_BUFFER_SIZE;
 258    case PIPE_CAP_MAX_VIEWPORTS:
 259       return 16;
 260    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 261       return 256;
 262    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 263       return 1024;
 264    case PIPE_CAP_MAX_GS_INVOCATIONS:
 265       return 32;
 266    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 267       return 4;
 268    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 269       return -32;
 270    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 271       return 31;
 272    case PIPE_CAP_MAX_VERTEX_STREAMS:
 273       return 4;
 274    case PIPE_CAP_VENDOR_ID:
 275       return 0x8086;
 276    case PIPE_CAP_DEVICE_ID:
 277       return screen->pci_id;
 278    case PIPE_CAP_VIDEO_MEMORY: {
 279       /* Once a batch uses more than 75% of the maximum mappable size, we
 280        * assume that there's some fragmentation, and we start doing extra
 281        * flushing, etc.  That's the big cliff apps will care about.
 282        */
 283       const unsigned gpu_mappable_megabytes =
 284          (screen->aperture_bytes * 3 / 4) / (1024 * 1024);
 285
 286       const long system_memory_pages = sysconf(_SC_PHYS_PAGES);
 287       const long system_page_size = sysconf(_SC_PAGE_SIZE);
 288
 289       if (system_memory_pages <= 0 || system_page_size <= 0)
 290          return -1;
 291
 292       const uint64_t system_memory_bytes =
 293          (uint64_t) system_memory_pages * (uint64_t) system_page_size;
 294
 295       const unsigned system_memory_megabytes =
 296          (unsigned) (system_memory_bytes / (1024 * 1024));
 297
 298       return MIN2(system_memory_megabytes, gpu_mappable_megabytes);
 299    }
 300    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 301    case PIPE_CAP_MAX_VARYINGS:
 302       return 32;
 303    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 304       /* AMD_pinned_memory assumes the flexibility of using client memory
 305        * for any buffer (incl. vertex buffers) which rules out the prospect
 306        * of using snooped buffers, as using snooped buffers without
 307        * cogniscience is likely to be detrimental to performance and require
 308        * extensive checking in the driver for correctness, e.g. to prevent
 309        * illegal snoop <-> snoop transfers.
 310        */
 311       return devinfo->has_llc;
 312
 313    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 314       return PIPE_CONTEXT_PRIORITY_LOW |
 315              PIPE_CONTEXT_PRIORITY_MEDIUM |
 316              PIPE_CONTEXT_PRIORITY_HIGH;
 317
 318    // XXX: don't hardcode 00:00:02.0 PCI here
 319    case PIPE_CAP_PCI_GROUP:
 320       return 0;
 321    case PIPE_CAP_PCI_BUS:
 322       return 0;
 323    case PIPE_CAP_PCI_DEVICE:
 324       return 2;
 325    case PIPE_CAP_PCI_FUNCTION:
 326       return 0;
 327
 328    default:
 329       return u_pipe_screen_get_param_defaults(pscreen, param);
 330    }
 331    return 0;
 332 }
 333
 334 static float
 335 iris_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 336 {
 337    switch (param) {
 338    case PIPE_CAPF_MAX_LINE_WIDTH:
 339    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 340       return 7.375f;
 341
 342    case PIPE_CAPF_MAX_POINT_WIDTH:
 343    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 344       return 255.0f;
 345
 346    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 347       return 16.0f;
 348    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 349       return 15.0f;
 350    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 351    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 352    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 353       return 0.0f;
 354    default:
 355       unreachable("unknown param");
 356    }
 357 }
 358
 359 static int
 360 iris_get_shader_param(struct pipe_screen *pscreen,
 361                       enum pipe_shader_type p_stage,
 362                       enum pipe_shader_cap param)
 363 {
 364    gl_shader_stage stage = stage_from_pipe(p_stage);
 365
 366    /* this is probably not totally correct.. but it's a start: */
 367    switch (param) {
 368    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 369       return stage == MESA_SHADER_FRAGMENT ? 1024 : 16384;
 370    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 371    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 372    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 373       return stage == MESA_SHADER_FRAGMENT ? 1024 : 0;
 374
 375    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 376       return UINT_MAX;
 377
 378    case PIPE_SHADER_CAP_MAX_INPUTS:
 379       return stage == MESA_SHADER_VERTEX ? 16 : 32;
 380    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 381       return 32;
 382    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 383       return 16 * 1024 * sizeof(float);
 384    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 385       return 16;
 386    case PIPE_SHADER_CAP_MAX_TEMPS:
 387       return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 388    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 389       return 0;
 390    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 391    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 392    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 393    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 394       /* Lie about these to avoid st/mesa's GLSL IR lowering of indirects,
 395        * which we don't want.  Our compiler backend will check brw_compiler's
 396        * options and call nir_lower_indirect_derefs appropriately anyway.
 397        */
 398       return true;
 399    case PIPE_SHADER_CAP_SUBROUTINES:
 400       return 0;
 401    case PIPE_SHADER_CAP_INTEGERS:
 402    case PIPE_SHADER_CAP_SCALAR_ISA:
 403       return 1;
 404    case PIPE_SHADER_CAP_INT64_ATOMICS:
 405    case PIPE_SHADER_CAP_FP16:
 406       return 0;
 407    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 408    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 409    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 410       return IRIS_MAX_TEXTURE_SAMPLERS;
 411    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 412       return IRIS_MAX_ABOS + IRIS_MAX_SSBOS;
 413    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 414    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 415       return 0;
 416    case PIPE_SHADER_CAP_PREFERRED_IR:
 417       return PIPE_SHADER_IR_NIR;
 418    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 419       return 1 << PIPE_SHADER_IR_NIR;
 420    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 421    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 422       return 1;
 423    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 424    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 425    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 426    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 427    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 428    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 429    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 430       return 0;
 431    default:
 432       unreachable("unknown shader param");
 433    }
 434 }
 435
 436 static int
 437 iris_get_compute_param(struct pipe_screen *pscreen,
 438                        enum pipe_shader_ir ir_type,
 439                        enum pipe_compute_cap param,
 440                        void *ret)
 441 {
 442    struct iris_screen *screen = (struct iris_screen *)pscreen;
 443    const struct gen_device_info *devinfo = &screen->devinfo;
 444
 445    const unsigned max_threads = MIN2(64, devinfo->max_cs_threads);
 446    const uint32_t max_invocations = 32 * max_threads;
 447
 448 #define RET(x) do {                  \
 449    if (ret)                          \
 450       memcpy(ret, x, sizeof(x));     \
 451    return sizeof(x);                 \
 452 } while (0)
 453
 454    switch (param) {
 455    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 456       RET((uint32_t []){ 32 });
 457
 458    case PIPE_COMPUTE_CAP_IR_TARGET:
 459       if (ret)
 460          strcpy(ret, "gen");
 461       return 4;
 462
 463    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 464       RET((uint64_t []) { 3 });
 465
 466    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 467       RET(((uint64_t []) { 65535, 65535, 65535 }));
 468
 469    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 470       /* MaxComputeWorkGroupSize[0..2] */
 471       RET(((uint64_t []) {max_invocations, max_invocations, max_invocations}));
 472
 473    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 474       /* MaxComputeWorkGroupInvocations */
 475       RET((uint64_t []) { max_invocations });
 476
 477    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 478       /* MaxComputeSharedMemorySize */
 479       RET((uint64_t []) { 64 * 1024 });
 480
 481    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 482       RET((uint32_t []) { 1 });
 483
 484    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 485       RET((uint32_t []) { BRW_SUBGROUP_SIZE });
 486
 487    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 488    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 489    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 490    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 491    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 492    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 493    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 494       // XXX: I think these are for Clover...
 495       return 0;
 496
 497    default:
 498       unreachable("unknown compute param");
 499    }
 500 }
 501
 502 static uint64_t
 503 iris_get_timestamp(struct pipe_screen *pscreen)
 504 {
 505    struct iris_screen *screen = (struct iris_screen *) pscreen;
 506    const unsigned TIMESTAMP = 0x2358;
 507    uint64_t result;
 508
 509    iris_reg_read(screen->bufmgr, TIMESTAMP | 1, &result);
 510
 511    result = gen_device_info_timebase_scale(&screen->devinfo, result);
 512    result &= (1ull << TIMESTAMP_BITS) - 1;
 513
 514    return result;
 515 }
 516
 517 static void
 518 iris_destroy_screen(struct pipe_screen *pscreen)
 519 {
 520    struct iris_screen *screen = (struct iris_screen *) pscreen;
 521    iris_bo_unreference(screen->workaround_bo);
 522    u_transfer_helper_destroy(pscreen->transfer_helper);
 523    iris_bufmgr_destroy(screen->bufmgr);
 524    disk_cache_destroy(screen->disk_cache);
 525    ralloc_free(screen);
 526 }
 527
 528 static void
 529 iris_query_memory_info(struct pipe_screen *pscreen,
 530                        struct pipe_memory_info *info)
 531 {
 532 }
 533
 534 static const void *
 535 iris_get_compiler_options(struct pipe_screen *pscreen,
 536                           enum pipe_shader_ir ir,
 537                           enum pipe_shader_type pstage)
 538 {
 539    struct iris_screen *screen = (struct iris_screen *) pscreen;
 540    gl_shader_stage stage = stage_from_pipe(pstage);
 541    assert(ir == PIPE_SHADER_IR_NIR);
 542
 543    return screen->compiler->glsl_compiler_options[stage].NirOptions;
 544 }
 545
 546 static struct disk_cache *
 547 iris_get_disk_shader_cache(struct pipe_screen *pscreen)
 548 {
 549    struct iris_screen *screen = (struct iris_screen *) pscreen;
 550    return screen->disk_cache;
 551 }
 552
 553 static int
 554 iris_getparam(struct iris_screen *screen, int param, int *value)
 555 {
 556    struct drm_i915_getparam gp = { .param = param, .value = value };
 557
 558    if (ioctl(screen->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1)
 559       return -errno;
 560
 561    return 0;
 562 }
 563
 564 static int
 565 iris_getparam_integer(struct iris_screen *screen, int param)
 566 {
 567    int value = -1;
 568
 569    if (iris_getparam(screen, param, &value) == 0)
 570       return value;
 571
 572    return -1;
 573 }
 574
 575 static void
 576 iris_shader_debug_log(void *data, const char *fmt, ...)
 577 {
 578    struct pipe_debug_callback *dbg = data;
 579    unsigned id = 0;
 580    va_list args;
 581
 582    if (!dbg->debug_message)
 583       return;
 584
 585    va_start(args, fmt);
 586    dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_SHADER_INFO, fmt, args);
 587    va_end(args);
 588 }
 589
 590 static void
 591 iris_shader_perf_log(void *data, const char *fmt, ...)
 592 {
 593    struct pipe_debug_callback *dbg = data;
 594    unsigned id = 0;
 595    va_list args;
 596    va_start(args, fmt);
 597
 598    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
 599       va_list args_copy;
 600       va_copy(args_copy, args);
 601       vfprintf(stderr, fmt, args_copy);
 602       va_end(args_copy);
 603    }
 604
 605    if (dbg->debug_message) {
 606       dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args);
 607    }
 608
 609    va_end(args);
 610 }
 611
 612 struct pipe_screen *
 613 iris_screen_create(int fd, const struct pipe_screen_config *config)
 614 {
 615    struct iris_screen *screen = rzalloc(NULL, struct iris_screen);
 616    if (!screen)
 617       return NULL;
 618
 619    screen->fd = fd;
 620
 621    if (!gen_get_device_info_from_fd(fd, &screen->devinfo))
 622       return NULL;
 623    screen->pci_id = screen->devinfo.chipset_id;
 624    screen->no_hw = screen->devinfo.no_hw;
 625
 626    if (screen->devinfo.gen < 8 || screen->devinfo.is_cherryview)
 627       return NULL;
 628
 629    screen->aperture_bytes = get_aperture_size(fd);
 630
 631    if (getenv("INTEL_NO_HW") != NULL)
 632       screen->no_hw = true;
 633
 634    screen->bufmgr = iris_bufmgr_init(&screen->devinfo, fd);
 635    if (!screen->bufmgr)
 636       return NULL;
 637
 638    screen->workaround_bo =
 639       iris_bo_alloc(screen->bufmgr, "workaround", 4096, IRIS_MEMZONE_OTHER);
 640    if (!screen->workaround_bo)
 641       return NULL;
 642
 643    brw_process_intel_debug_variable();
 644
 645    screen->driconf.dual_color_blend_by_location =
 646       driQueryOptionb(config->options, "dual_color_blend_by_location");
 647
 648    screen->precompile = env_var_as_boolean("shader_precompile", true);
 649
 650    isl_device_init(&screen->isl_dev, &screen->devinfo, false);
 651
 652    screen->compiler = brw_compiler_create(screen, &screen->devinfo);
 653    screen->compiler->shader_debug_log = iris_shader_debug_log;
 654    screen->compiler->shader_perf_log = iris_shader_perf_log;
 655    screen->compiler->supports_pull_constants = false;
 656    screen->compiler->supports_shader_constants = true;
 657
 658    iris_disk_cache_init(screen);
 659
 660    slab_create_parent(&screen->transfer_pool,
 661                       sizeof(struct iris_transfer), 64);
 662
 663    screen->subslice_total =
 664       iris_getparam_integer(screen, I915_PARAM_SUBSLICE_TOTAL);
 665    assert(screen->subslice_total >= 1);
 666
 667    struct pipe_screen *pscreen = &screen->base;
 668
 669    iris_init_screen_fence_functions(pscreen);
 670    iris_init_screen_resource_functions(pscreen);
 671
 672    pscreen->destroy = iris_destroy_screen;
 673    pscreen->get_name = iris_get_name;
 674    pscreen->get_vendor = iris_get_vendor;
 675    pscreen->get_device_vendor = iris_get_device_vendor;
 676    pscreen->get_param = iris_get_param;
 677    pscreen->get_shader_param = iris_get_shader_param;
 678    pscreen->get_compute_param = iris_get_compute_param;
 679    pscreen->get_paramf = iris_get_paramf;
 680    pscreen->get_compiler_options = iris_get_compiler_options;
 681    pscreen->get_disk_shader_cache = iris_get_disk_shader_cache;
 682    pscreen->is_format_supported = iris_is_format_supported;
 683    pscreen->context_create = iris_create_context;
 684    pscreen->flush_frontbuffer = iris_flush_frontbuffer;
 685    pscreen->get_timestamp = iris_get_timestamp;
 686    pscreen->query_memory_info = iris_query_memory_info;
 687    pscreen->get_driver_query_group_info = iris_get_monitor_group_info;
 688    pscreen->get_driver_query_info = iris_get_monitor_info;
 689
 690    return pscreen;
 691 }