src/gallium/drivers/iris/iris_screen.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 /**
  24  * @file iris_screen.c
  25  *
  26  * Screen related driver hooks and capability lists.
  27  *
  28  * A program may use multiple rendering contexts (iris_context), but
  29  * they all share a common screen (iris_screen).  Global driver state
  30  * can be stored in the screen; it may be accessed by multiple threads.
  31  */
  32
  33 #include <stdio.h>
  34 #include <errno.h>
  35 #include <sys/ioctl.h>
  36 #include "pipe/p_defines.h"
  37 #include "pipe/p_state.h"
  38 #include "pipe/p_context.h"
  39 #include "pipe/p_screen.h"
  40 #include "util/debug.h"
  41 #include "util/u_inlines.h"
  42 #include "util/format/u_format.h"
  43 #include "util/u_transfer_helper.h"
  44 #include "util/u_upload_mgr.h"
  45 #include "util/ralloc.h"
  46 #include "util/xmlconfig.h"
  47 #include "drm-uapi/i915_drm.h"
  48 #include "iris_context.h"
  49 #include "iris_defines.h"
  50 #include "iris_fence.h"
  51 #include "iris_pipe.h"
  52 #include "iris_resource.h"
  53 #include "iris_screen.h"
  54 #include "intel/compiler/brw_compiler.h"
  55 #include "intel/common/gen_gem.h"
  56 #include "intel/common/gen_l3_config.h"
  57 #include "iris_monitor.h"
  58
  59 static void
  60 iris_flush_frontbuffer(struct pipe_screen *_screen,
  61                        struct pipe_resource *resource,
  62                        unsigned level, unsigned layer,
  63                        void *context_private, struct pipe_box *box)
  64 {
  65 }
  66
  67 static const char *
  68 iris_get_vendor(struct pipe_screen *pscreen)
  69 {
  70    return "Intel";
  71 }
  72
  73 static const char *
  74 iris_get_device_vendor(struct pipe_screen *pscreen)
  75 {
  76    return "Intel";
  77 }
  78
  79 static const char *
  80 iris_get_name(struct pipe_screen *pscreen)
  81 {
  82    struct iris_screen *screen = (struct iris_screen *)pscreen;
  83    static char buf[128];
  84    const char *name = gen_get_device_name(screen->pci_id);
  85
  86    if (!name)
  87       name = "Intel Unknown";
  88
  89    snprintf(buf, sizeof(buf), "Mesa %s", name);
  90    return buf;
  91 }
  92
  93 static uint64_t
  94 get_aperture_size(int fd)
  95 {
  96    struct drm_i915_gem_get_aperture aperture = {};
  97    gen_ioctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
  98    return aperture.aper_size;
  99 }
 100
 101 static int
 102 iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 103 {
 104    struct iris_screen *screen = (struct iris_screen *)pscreen;
 105    const struct gen_device_info *devinfo = &screen->devinfo;
 106
 107    switch (param) {
 108    case PIPE_CAP_NPOT_TEXTURES:
 109    case PIPE_CAP_ANISOTROPIC_FILTER:
 110    case PIPE_CAP_POINT_SPRITE:
 111    case PIPE_CAP_OCCLUSION_QUERY:
 112    case PIPE_CAP_QUERY_TIME_ELAPSED:
 113    case PIPE_CAP_TEXTURE_SWIZZLE:
 114    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 115    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 116    case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
 117    case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
 118    case PIPE_CAP_VERTEX_SHADER_SATURATE:
 119    case PIPE_CAP_PRIMITIVE_RESTART:
 120    case PIPE_CAP_INDEP_BLEND_ENABLE:
 121    case PIPE_CAP_INDEP_BLEND_FUNC:
 122    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
 123    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 124    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 125    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 126    case PIPE_CAP_TGSI_INSTANCEID:
 127    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 128    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 129    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 130    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 131    case PIPE_CAP_CONDITIONAL_RENDER:
 132    case PIPE_CAP_TEXTURE_BARRIER:
 133    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 134    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 135    case PIPE_CAP_COMPUTE:
 136    case PIPE_CAP_START_INSTANCE:
 137    case PIPE_CAP_QUERY_TIMESTAMP:
 138    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 139    case PIPE_CAP_CUBE_MAP_ARRAY:
 140    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 141    case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
 142    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 143    case PIPE_CAP_TEXTURE_QUERY_LOD:
 144    case PIPE_CAP_SAMPLE_SHADING:
 145    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 146    case PIPE_CAP_DRAW_INDIRECT:
 147    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 148    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 149    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 150    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 151    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 152    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 153    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 154    case PIPE_CAP_ACCELERATED:
 155    case PIPE_CAP_UMA:
 156    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 157    case PIPE_CAP_CLIP_HALFZ:
 158    case PIPE_CAP_TGSI_TEXCOORD:
 159    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 160    case PIPE_CAP_DOUBLES:
 161    case PIPE_CAP_INT64:
 162    case PIPE_CAP_INT64_DIVMOD:
 163    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 164    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 165    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 166    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 167    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 168    case PIPE_CAP_CULL_DISTANCE:
 169    case PIPE_CAP_PACKED_UNIFORMS:
 170    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 171    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 172    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 173    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 174    case PIPE_CAP_QUERY_SO_OVERFLOW:
 175    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 176    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 177    case PIPE_CAP_TGSI_TXQS:
 178    case PIPE_CAP_TGSI_CLOCK:
 179    case PIPE_CAP_TGSI_BALLOT:
 180    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 181    case PIPE_CAP_CLEAR_TEXTURE:
 182    case PIPE_CAP_TGSI_VOTE:
 183    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 184    case PIPE_CAP_TEXTURE_GATHER_SM5:
 185    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 186    case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
 187    case PIPE_CAP_LOAD_CONSTBUF:
 188    case PIPE_CAP_NIR_COMPACT_ARRAYS:
 189    case PIPE_CAP_DRAW_PARAMETERS:
 190    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 191    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 192    case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
 193    case PIPE_CAP_INVALIDATE_BUFFER:
 194    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 195    case PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED:
 196    case PIPE_CAP_TEXTURE_SHADOW_LOD:
 197    case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
 198    case PIPE_CAP_GL_SPIRV:
 199    case PIPE_CAP_GL_SPIRV_VARIABLE_POINTERS:
 200    case PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION:
 201    case PIPE_CAP_NATIVE_FENCE_FD:
 202       return true;
 203    case PIPE_CAP_FBFETCH:
 204       return BRW_MAX_DRAW_BUFFERS;
 205    case PIPE_CAP_FBFETCH_COHERENT:
 206    case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE:
 207    case PIPE_CAP_POST_DEPTH_COVERAGE:
 208    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 209    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 210    case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK:
 211    case PIPE_CAP_ATOMIC_FLOAT_MINMAX:
 212       return devinfo->gen >= 9;
 213    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 214       return 1;
 215    case PIPE_CAP_MAX_RENDER_TARGETS:
 216       return BRW_MAX_DRAW_BUFFERS;
 217    case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 218       return 16384;
 219    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 220       return IRIS_MAX_MIPLEVELS; /* 16384x16384 */
 221    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 222       return 12; /* 2048x2048 */
 223    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 224       return 4;
 225    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 226       return 2048;
 227    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 228       return BRW_MAX_SOL_BINDINGS / IRIS_MAX_SOL_BUFFERS;
 229    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 230       return BRW_MAX_SOL_BINDINGS;
 231    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 232    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 233       return 460;
 234    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 235       /* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */
 236       return 32;
 237    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 238       return IRIS_MAP_BUFFER_ALIGNMENT;
 239    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 240       /* Choose a cacheline (64 bytes) so that we can safely have the CPU and
 241        * GPU writing the same SSBO on non-coherent systems (Atom CPUs).  With
 242        * UBOs, the GPU never writes, so there's no problem.  For an SSBO, the
 243        * GPU and the CPU can be updating disjoint regions of the buffer
 244        * simultaneously and that will break if the regions overlap the same
 245        * cacheline.
 246        */
 247       return 64;
 248    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 249       return 1 << 27;
 250    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 251       return 16; // XXX: u_screen says 256 is the minimum value...
 252    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 253       return true;
 254    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 255       return IRIS_MAX_TEXTURE_BUFFER_SIZE;
 256    case PIPE_CAP_MAX_VIEWPORTS:
 257       return 16;
 258    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 259       return 256;
 260    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 261       return 1024;
 262    case PIPE_CAP_MAX_GS_INVOCATIONS:
 263       return 32;
 264    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 265       return 4;
 266    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 267       return -32;
 268    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 269       return 31;
 270    case PIPE_CAP_MAX_VERTEX_STREAMS:
 271       return 4;
 272    case PIPE_CAP_VENDOR_ID:
 273       return 0x8086;
 274    case PIPE_CAP_DEVICE_ID:
 275       return screen->pci_id;
 276    case PIPE_CAP_VIDEO_MEMORY: {
 277       /* Once a batch uses more than 75% of the maximum mappable size, we
 278        * assume that there's some fragmentation, and we start doing extra
 279        * flushing, etc.  That's the big cliff apps will care about.
 280        */
 281       const unsigned gpu_mappable_megabytes =
 282          (screen->aperture_bytes * 3 / 4) / (1024 * 1024);
 283
 284       const long system_memory_pages = sysconf(_SC_PHYS_PAGES);
 285       const long system_page_size = sysconf(_SC_PAGE_SIZE);
 286
 287       if (system_memory_pages <= 0 || system_page_size <= 0)
 288          return -1;
 289
 290       const uint64_t system_memory_bytes =
 291          (uint64_t) system_memory_pages * (uint64_t) system_page_size;
 292
 293       const unsigned system_memory_megabytes =
 294          (unsigned) (system_memory_bytes / (1024 * 1024));
 295
 296       return MIN2(system_memory_megabytes, gpu_mappable_megabytes);
 297    }
 298    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 299    case PIPE_CAP_MAX_VARYINGS:
 300       return 32;
 301    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 302       /* AMD_pinned_memory assumes the flexibility of using client memory
 303        * for any buffer (incl. vertex buffers) which rules out the prospect
 304        * of using snooped buffers, as using snooped buffers without
 305        * cogniscience is likely to be detrimental to performance and require
 306        * extensive checking in the driver for correctness, e.g. to prevent
 307        * illegal snoop <-> snoop transfers.
 308        */
 309       return devinfo->has_llc;
 310    case PIPE_CAP_THROTTLE:
 311       return screen->driconf.disable_throttling ? 0 : 1;
 312
 313    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 314       return PIPE_CONTEXT_PRIORITY_LOW |
 315              PIPE_CONTEXT_PRIORITY_MEDIUM |
 316              PIPE_CONTEXT_PRIORITY_HIGH;
 317
 318    // XXX: don't hardcode 00:00:02.0 PCI here
 319    case PIPE_CAP_PCI_GROUP:
 320       return 0;
 321    case PIPE_CAP_PCI_BUS:
 322       return 0;
 323    case PIPE_CAP_PCI_DEVICE:
 324       return 2;
 325    case PIPE_CAP_PCI_FUNCTION:
 326       return 0;
 327
 328    case PIPE_CAP_OPENCL_INTEGER_FUNCTIONS:
 329    case PIPE_CAP_INTEGER_MULTIPLY_32X16:
 330       return true;
 331
 332    default:
 333       return u_pipe_screen_get_param_defaults(pscreen, param);
 334    }
 335    return 0;
 336 }
 337
 338 static float
 339 iris_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 340 {
 341    switch (param) {
 342    case PIPE_CAPF_MAX_LINE_WIDTH:
 343    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 344       return 7.375f;
 345
 346    case PIPE_CAPF_MAX_POINT_WIDTH:
 347    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 348       return 255.0f;
 349
 350    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 351       return 16.0f;
 352    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 353       return 15.0f;
 354    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 355    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 356    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 357       return 0.0f;
 358    default:
 359       unreachable("unknown param");
 360    }
 361 }
 362
 363 static int
 364 iris_get_shader_param(struct pipe_screen *pscreen,
 365                       enum pipe_shader_type p_stage,
 366                       enum pipe_shader_cap param)
 367 {
 368    gl_shader_stage stage = stage_from_pipe(p_stage);
 369
 370    /* this is probably not totally correct.. but it's a start: */
 371    switch (param) {
 372    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 373       return stage == MESA_SHADER_FRAGMENT ? 1024 : 16384;
 374    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 375    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 376    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 377       return stage == MESA_SHADER_FRAGMENT ? 1024 : 0;
 378
 379    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 380       return UINT_MAX;
 381
 382    case PIPE_SHADER_CAP_MAX_INPUTS:
 383       return stage == MESA_SHADER_VERTEX ? 16 : 32;
 384    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 385       return 32;
 386    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 387       return 16 * 1024 * sizeof(float);
 388    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 389       return 16;
 390    case PIPE_SHADER_CAP_MAX_TEMPS:
 391       return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 392    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 393       return 0;
 394    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 395    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 396    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 397    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 398       /* Lie about these to avoid st/mesa's GLSL IR lowering of indirects,
 399        * which we don't want.  Our compiler backend will check brw_compiler's
 400        * options and call nir_lower_indirect_derefs appropriately anyway.
 401        */
 402       return true;
 403    case PIPE_SHADER_CAP_SUBROUTINES:
 404       return 0;
 405    case PIPE_SHADER_CAP_INTEGERS:
 406       return 1;
 407    case PIPE_SHADER_CAP_INT64_ATOMICS:
 408    case PIPE_SHADER_CAP_FP16:
 409       return 0;
 410    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 411    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 412    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 413       return IRIS_MAX_TEXTURE_SAMPLERS;
 414    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 415       return IRIS_MAX_ABOS + IRIS_MAX_SSBOS;
 416    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 417    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 418       return 0;
 419    case PIPE_SHADER_CAP_PREFERRED_IR:
 420       return PIPE_SHADER_IR_NIR;
 421    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 422       return 1 << PIPE_SHADER_IR_NIR;
 423    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 424    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 425       return 1;
 426    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 427    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 428    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 429    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 430    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 431    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 432    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 433       return 0;
 434    default:
 435       unreachable("unknown shader param");
 436    }
 437 }
 438
 439 static int
 440 iris_get_compute_param(struct pipe_screen *pscreen,
 441                        enum pipe_shader_ir ir_type,
 442                        enum pipe_compute_cap param,
 443                        void *ret)
 444 {
 445    struct iris_screen *screen = (struct iris_screen *)pscreen;
 446    const struct gen_device_info *devinfo = &screen->devinfo;
 447
 448    const unsigned max_threads = MIN2(64, devinfo->max_cs_threads);
 449    const uint32_t max_invocations = 32 * max_threads;
 450
 451 #define RET(x) do {                  \
 452    if (ret)                          \
 453       memcpy(ret, x, sizeof(x));     \
 454    return sizeof(x);                 \
 455 } while (0)
 456
 457    switch (param) {
 458    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 459       RET((uint32_t []){ 32 });
 460
 461    case PIPE_COMPUTE_CAP_IR_TARGET:
 462       if (ret)
 463          strcpy(ret, "gen");
 464       return 4;
 465
 466    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 467       RET((uint64_t []) { 3 });
 468
 469    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 470       RET(((uint64_t []) { 65535, 65535, 65535 }));
 471
 472    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 473       /* MaxComputeWorkGroupSize[0..2] */
 474       RET(((uint64_t []) {max_invocations, max_invocations, max_invocations}));
 475
 476    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 477       /* MaxComputeWorkGroupInvocations */
 478       RET((uint64_t []) { max_invocations });
 479
 480    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 481       /* MaxComputeSharedMemorySize */
 482       RET((uint64_t []) { 64 * 1024 });
 483
 484    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 485       RET((uint32_t []) { 1 });
 486
 487    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 488       RET((uint32_t []) { BRW_SUBGROUP_SIZE });
 489
 490    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 491    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 492    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 493    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 494    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 495    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 496    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 497       // XXX: I think these are for Clover...
 498       return 0;
 499
 500    default:
 501       unreachable("unknown compute param");
 502    }
 503 }
 504
 505 static uint64_t
 506 iris_get_timestamp(struct pipe_screen *pscreen)
 507 {
 508    struct iris_screen *screen = (struct iris_screen *) pscreen;
 509    const unsigned TIMESTAMP = 0x2358;
 510    uint64_t result;
 511
 512    iris_reg_read(screen->bufmgr, TIMESTAMP | 1, &result);
 513
 514    result = gen_device_info_timebase_scale(&screen->devinfo, result);
 515    result &= (1ull << TIMESTAMP_BITS) - 1;
 516
 517    return result;
 518 }
 519
 520 static void
 521 iris_destroy_screen(struct pipe_screen *pscreen)
 522 {
 523    struct iris_screen *screen = (struct iris_screen *) pscreen;
 524    iris_bo_unreference(screen->workaround_bo);
 525    u_transfer_helper_destroy(pscreen->transfer_helper);
 526    iris_bufmgr_destroy(screen->bufmgr);
 527    disk_cache_destroy(screen->disk_cache);
 528    close(screen->fd);
 529    ralloc_free(screen);
 530 }
 531
 532 static void
 533 iris_query_memory_info(struct pipe_screen *pscreen,
 534                        struct pipe_memory_info *info)
 535 {
 536 }
 537
 538 static const void *
 539 iris_get_compiler_options(struct pipe_screen *pscreen,
 540                           enum pipe_shader_ir ir,
 541                           enum pipe_shader_type pstage)
 542 {
 543    struct iris_screen *screen = (struct iris_screen *) pscreen;
 544    gl_shader_stage stage = stage_from_pipe(pstage);
 545    assert(ir == PIPE_SHADER_IR_NIR);
 546
 547    return screen->compiler->glsl_compiler_options[stage].NirOptions;
 548 }
 549
 550 static struct disk_cache *
 551 iris_get_disk_shader_cache(struct pipe_screen *pscreen)
 552 {
 553    struct iris_screen *screen = (struct iris_screen *) pscreen;
 554    return screen->disk_cache;
 555 }
 556
 557 static int
 558 iris_getparam(struct iris_screen *screen, int param, int *value)
 559 {
 560    struct drm_i915_getparam gp = { .param = param, .value = value };
 561
 562    if (ioctl(screen->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1)
 563       return -errno;
 564
 565    return 0;
 566 }
 567
 568 static int
 569 iris_getparam_integer(struct iris_screen *screen, int param)
 570 {
 571    int value = -1;
 572
 573    if (iris_getparam(screen, param, &value) == 0)
 574       return value;
 575
 576    return -1;
 577 }
 578
 579 static const struct gen_l3_config *
 580 iris_get_default_l3_config(const struct gen_device_info *devinfo,
 581                            bool compute)
 582 {
 583    bool wants_dc_cache = true;
 584    bool has_slm = compute;
 585    const struct gen_l3_weights w =
 586       gen_get_default_l3_weights(devinfo, wants_dc_cache, has_slm);
 587    return gen_get_l3_config(devinfo, w);
 588 }
 589
 590 static void
 591 iris_shader_debug_log(void *data, const char *fmt, ...)
 592 {
 593    struct pipe_debug_callback *dbg = data;
 594    unsigned id = 0;
 595    va_list args;
 596
 597    if (!dbg->debug_message)
 598       return;
 599
 600    va_start(args, fmt);
 601    dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_SHADER_INFO, fmt, args);
 602    va_end(args);
 603 }
 604
 605 static void
 606 iris_shader_perf_log(void *data, const char *fmt, ...)
 607 {
 608    struct pipe_debug_callback *dbg = data;
 609    unsigned id = 0;
 610    va_list args;
 611    va_start(args, fmt);
 612
 613    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
 614       va_list args_copy;
 615       va_copy(args_copy, args);
 616       vfprintf(stderr, fmt, args_copy);
 617       va_end(args_copy);
 618    }
 619
 620    if (dbg->debug_message) {
 621       dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args);
 622    }
 623
 624    va_end(args);
 625 }
 626
 627 struct pipe_screen *
 628 iris_screen_create(int fd, const struct pipe_screen_config *config)
 629 {
 630    struct iris_screen *screen = rzalloc(NULL, struct iris_screen);
 631    if (!screen)
 632       return NULL;
 633
 634    screen->fd = fd;
 635
 636    if (!gen_get_device_info_from_fd(fd, &screen->devinfo))
 637       return NULL;
 638    screen->pci_id = screen->devinfo.chipset_id;
 639    screen->no_hw = screen->devinfo.no_hw;
 640
 641    if (screen->devinfo.gen < 8 || screen->devinfo.is_cherryview)
 642       return NULL;
 643
 644    screen->aperture_bytes = get_aperture_size(fd);
 645
 646    if (getenv("INTEL_NO_HW") != NULL)
 647       screen->no_hw = true;
 648
 649    bool bo_reuse = false;
 650    int bo_reuse_mode = driQueryOptioni(config->options, "bo_reuse");
 651    switch (bo_reuse_mode) {
 652    case DRI_CONF_BO_REUSE_DISABLED:
 653       break;
 654    case DRI_CONF_BO_REUSE_ALL:
 655       bo_reuse = true;
 656       break;
 657    }
 658
 659    screen->bufmgr = iris_bufmgr_init(&screen->devinfo, fd, bo_reuse);
 660    if (!screen->bufmgr)
 661       return NULL;
 662
 663    screen->workaround_bo =
 664       iris_bo_alloc(screen->bufmgr, "workaround", 4096, IRIS_MEMZONE_OTHER);
 665    if (!screen->workaround_bo)
 666       return NULL;
 667
 668    brw_process_intel_debug_variable();
 669
 670    screen->driconf.dual_color_blend_by_location =
 671       driQueryOptionb(config->options, "dual_color_blend_by_location");
 672    screen->driconf.disable_throttling =
 673       driQueryOptionb(config->options, "disable_throttling");
 674    screen->driconf.always_flush_cache =
 675       driQueryOptionb(config->options, "always_flush_cache");
 676
 677    screen->precompile = env_var_as_boolean("shader_precompile", true);
 678
 679    isl_device_init(&screen->isl_dev, &screen->devinfo, false);
 680
 681    screen->compiler = brw_compiler_create(screen, &screen->devinfo);
 682    screen->compiler->shader_debug_log = iris_shader_debug_log;
 683    screen->compiler->shader_perf_log = iris_shader_perf_log;
 684    screen->compiler->supports_pull_constants = false;
 685    screen->compiler->supports_shader_constants = true;
 686    screen->compiler->compact_params = false;
 687
 688    screen->l3_config_3d = iris_get_default_l3_config(&screen->devinfo, false);
 689    screen->l3_config_cs = iris_get_default_l3_config(&screen->devinfo, true);
 690
 691    iris_disk_cache_init(screen);
 692
 693    slab_create_parent(&screen->transfer_pool,
 694                       sizeof(struct iris_transfer), 64);
 695
 696    screen->subslice_total =
 697       iris_getparam_integer(screen, I915_PARAM_SUBSLICE_TOTAL);
 698    assert(screen->subslice_total >= 1);
 699
 700    struct pipe_screen *pscreen = &screen->base;
 701
 702    iris_init_screen_fence_functions(pscreen);
 703    iris_init_screen_resource_functions(pscreen);
 704
 705    pscreen->destroy = iris_destroy_screen;
 706    pscreen->get_name = iris_get_name;
 707    pscreen->get_vendor = iris_get_vendor;
 708    pscreen->get_device_vendor = iris_get_device_vendor;
 709    pscreen->get_param = iris_get_param;
 710    pscreen->get_shader_param = iris_get_shader_param;
 711    pscreen->get_compute_param = iris_get_compute_param;
 712    pscreen->get_paramf = iris_get_paramf;
 713    pscreen->get_compiler_options = iris_get_compiler_options;
 714    pscreen->get_disk_shader_cache = iris_get_disk_shader_cache;
 715    pscreen->is_format_supported = iris_is_format_supported;
 716    pscreen->context_create = iris_create_context;
 717    pscreen->flush_frontbuffer = iris_flush_frontbuffer;
 718    pscreen->get_timestamp = iris_get_timestamp;
 719    pscreen->query_memory_info = iris_query_memory_info;
 720    pscreen->get_driver_query_group_info = iris_get_monitor_group_info;
 721    pscreen->get_driver_query_info = iris_get_monitor_info;
 722
 723    return pscreen;
 724 }