src/gallium/drivers/iris/iris_screen.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 /**
  24  * @file iris_screen.c
  25  *
  26  * Screen related driver hooks and capability lists.
  27  *
  28  * A program may use multiple rendering contexts (iris_context), but
  29  * they all share a common screen (iris_screen).  Global driver state
  30  * can be stored in the screen; it may be accessed by multiple threads.
  31  */
  32
  33 #include <stdio.h>
  34 #include <errno.h>
  35 #include <sys/ioctl.h>
  36 #include "pipe/p_defines.h"
  37 #include "pipe/p_state.h"
  38 #include "pipe/p_context.h"
  39 #include "pipe/p_screen.h"
  40 #include "util/debug.h"
  41 #include "util/u_inlines.h"
  42 #include "util/u_format.h"
  43 #include "util/u_transfer_helper.h"
  44 #include "util/u_upload_mgr.h"
  45 #include "util/ralloc.h"
  46 #include "util/xmlconfig.h"
  47 #include "drm-uapi/i915_drm.h"
  48 #include "iris_context.h"
  49 #include "iris_defines.h"
  50 #include "iris_fence.h"
  51 #include "iris_pipe.h"
  52 #include "iris_resource.h"
  53 #include "iris_screen.h"
  54 #include "intel/compiler/brw_compiler.h"
  55
  56 static void
  57 iris_flush_frontbuffer(struct pipe_screen *_screen,
  58                        struct pipe_resource *resource,
  59                        unsigned level, unsigned layer,
  60                        void *context_private, struct pipe_box *box)
  61 {
  62 }
  63
  64 static const char *
  65 iris_get_vendor(struct pipe_screen *pscreen)
  66 {
  67    return "Intel";
  68 }
  69
  70 static const char *
  71 iris_get_device_vendor(struct pipe_screen *pscreen)
  72 {
  73    return "Intel";
  74 }
  75
  76 static const char *
  77 iris_get_name(struct pipe_screen *pscreen)
  78 {
  79    struct iris_screen *screen = (struct iris_screen *)pscreen;
  80    static char buf[128];
  81    const char *chipset;
  82
  83    switch (screen->pci_id) {
  84 #undef CHIPSET
  85 #define CHIPSET(id, symbol, str) case id: chipset = str; break;
  86 #include "pci_ids/i965_pci_ids.h"
  87    default:
  88       chipset = "Unknown Intel Chipset";
  89       break;
  90    }
  91
  92    snprintf(buf, sizeof(buf), "Mesa %s", chipset);
  93    return buf;
  94 }
  95
  96 static uint64_t
  97 get_aperture_size(int fd)
  98 {
  99    struct drm_i915_gem_get_aperture aperture = {};
 100    drm_ioctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
 101    return aperture.aper_size;
 102 }
 103
 104 static int
 105 iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 106 {
 107    struct iris_screen *screen = (struct iris_screen *)pscreen;
 108    const struct gen_device_info *devinfo = &screen->devinfo;
 109
 110    switch (param) {
 111    case PIPE_CAP_NPOT_TEXTURES:
 112    case PIPE_CAP_ANISOTROPIC_FILTER:
 113    case PIPE_CAP_POINT_SPRITE:
 114    case PIPE_CAP_OCCLUSION_QUERY:
 115    case PIPE_CAP_QUERY_TIME_ELAPSED:
 116    case PIPE_CAP_TEXTURE_SWIZZLE:
 117    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 118    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 119    case PIPE_CAP_SM3:
 120    case PIPE_CAP_PRIMITIVE_RESTART:
 121    case PIPE_CAP_INDEP_BLEND_ENABLE:
 122    case PIPE_CAP_INDEP_BLEND_FUNC:
 123    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
 124    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 125    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 126    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 127    case PIPE_CAP_TGSI_INSTANCEID:
 128    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 129    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 130    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 131    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 132    case PIPE_CAP_CONDITIONAL_RENDER:
 133    case PIPE_CAP_TEXTURE_BARRIER:
 134    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 135    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 136    case PIPE_CAP_COMPUTE:
 137    case PIPE_CAP_START_INSTANCE:
 138    case PIPE_CAP_QUERY_TIMESTAMP:
 139    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 140    case PIPE_CAP_CUBE_MAP_ARRAY:
 141    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 142    case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
 143    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 144    case PIPE_CAP_TEXTURE_QUERY_LOD:
 145    case PIPE_CAP_SAMPLE_SHADING:
 146    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 147    case PIPE_CAP_DRAW_INDIRECT:
 148    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 149    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 150    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 151    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 152    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 153    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 154    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 155    case PIPE_CAP_ACCELERATED:
 156    case PIPE_CAP_UMA:
 157    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 158    case PIPE_CAP_CLIP_HALFZ:
 159    case PIPE_CAP_TGSI_TEXCOORD:
 160    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 161    case PIPE_CAP_DOUBLES:
 162    case PIPE_CAP_INT64:
 163    case PIPE_CAP_INT64_DIVMOD:
 164    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 165    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 166    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 167    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 168    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 169    case PIPE_CAP_CULL_DISTANCE:
 170    case PIPE_CAP_PACKED_UNIFORMS:
 171    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 172    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 173    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 174    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 175    case PIPE_CAP_QUERY_SO_OVERFLOW:
 176    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 177    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 178    case PIPE_CAP_TGSI_TXQS:
 179    case PIPE_CAP_TGSI_CLOCK:
 180    case PIPE_CAP_TGSI_BALLOT:
 181    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 182    case PIPE_CAP_CLEAR_TEXTURE:
 183    case PIPE_CAP_TGSI_VOTE:
 184    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 185    case PIPE_CAP_TEXTURE_GATHER_SM5:
 186    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 187    case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
 188    case PIPE_CAP_LOAD_CONSTBUF:
 189    case PIPE_CAP_NIR_COMPACT_ARRAYS:
 190    case PIPE_CAP_DRAW_PARAMETERS:
 191    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 192    case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
 193    case PIPE_CAP_INVALIDATE_BUFFER:
 194    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 195       return true;
 196    case PIPE_CAP_FBFETCH:
 197       /* TODO: Support non-coherent FB fetch on Broadwell */
 198       return devinfo->gen >= 9 ? BRW_MAX_DRAW_BUFFERS : 0;
 199    case PIPE_CAP_FBFETCH_COHERENT:
 200    case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE:
 201    case PIPE_CAP_POST_DEPTH_COVERAGE:
 202    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 203    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 204    case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK:
 205       return devinfo->gen >= 9;
 206    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 207       return 1;
 208    case PIPE_CAP_MAX_RENDER_TARGETS:
 209       return BRW_MAX_DRAW_BUFFERS;
 210    case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 211       return 16384;
 212    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 213       return IRIS_MAX_MIPLEVELS; /* 16384x16384 */
 214    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 215       return 12; /* 2048x2048 */
 216    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 217       return 4;
 218    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 219       return 2048;
 220    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 221       return BRW_MAX_SOL_BINDINGS / IRIS_MAX_SOL_BUFFERS;
 222    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 223       return BRW_MAX_SOL_BINDINGS;
 224    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 225       return 460;
 226    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 227       return 140;
 228    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 229       /* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */
 230       return 32;
 231    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 232       return IRIS_MAP_BUFFER_ALIGNMENT;
 233    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 234       /* Choose a cacheline (64 bytes) so that we can safely have the CPU and
 235        * GPU writing the same SSBO on non-coherent systems (Atom CPUs).  With
 236        * UBOs, the GPU never writes, so there's no problem.  For an SSBO, the
 237        * GPU and the CPU can be updating disjoint regions of the buffer
 238        * simultaneously and that will break if the regions overlap the same
 239        * cacheline.
 240        */
 241       return 64;
 242    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 243       return 1 << 27;
 244    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 245       return 16; // XXX: u_screen says 256 is the minimum value...
 246    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 247       return true; // XXX: ?????
 248    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 249       return IRIS_MAX_TEXTURE_BUFFER_SIZE;
 250    case PIPE_CAP_MAX_VIEWPORTS:
 251       return 16;
 252    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 253       return 256;
 254    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 255       return 1024;
 256    case PIPE_CAP_MAX_GS_INVOCATIONS:
 257       return 32;
 258    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 259       return 4;
 260    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 261       return -32;
 262    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 263       return 31;
 264    case PIPE_CAP_MAX_VERTEX_STREAMS:
 265       return 4;
 266    case PIPE_CAP_VENDOR_ID:
 267       return 0x8086;
 268    case PIPE_CAP_DEVICE_ID:
 269       return screen->pci_id;
 270    case PIPE_CAP_VIDEO_MEMORY: {
 271       /* Once a batch uses more than 75% of the maximum mappable size, we
 272        * assume that there's some fragmentation, and we start doing extra
 273        * flushing, etc.  That's the big cliff apps will care about.
 274        */
 275       const unsigned gpu_mappable_megabytes =
 276          (screen->aperture_bytes * 3 / 4) / (1024 * 1024);
 277
 278       const long system_memory_pages = sysconf(_SC_PHYS_PAGES);
 279       const long system_page_size = sysconf(_SC_PAGE_SIZE);
 280
 281       if (system_memory_pages <= 0 || system_page_size <= 0)
 282          return -1;
 283
 284       const uint64_t system_memory_bytes =
 285          (uint64_t) system_memory_pages * (uint64_t) system_page_size;
 286
 287       const unsigned system_memory_megabytes =
 288          (unsigned) (system_memory_bytes / (1024 * 1024));
 289
 290       return MIN2(system_memory_megabytes, gpu_mappable_megabytes);
 291    }
 292    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 293    case PIPE_CAP_MAX_VARYINGS:
 294       return 32;
 295    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 296       /* AMD_pinned_memory assumes the flexibility of using client memory
 297        * for any buffer (incl. vertex buffers) which rules out the prospect
 298        * of using snooped buffers, as using snooped buffers without
 299        * cogniscience is likely to be detrimental to performance and require
 300        * extensive checking in the driver for correctness, e.g. to prevent
 301        * illegal snoop <-> snoop transfers.
 302        */
 303       return devinfo->has_llc;
 304
 305    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 306       return PIPE_CONTEXT_PRIORITY_LOW |
 307              PIPE_CONTEXT_PRIORITY_MEDIUM |
 308              PIPE_CONTEXT_PRIORITY_HIGH;
 309
 310    // XXX: don't hardcode 00:00:02.0 PCI here
 311    case PIPE_CAP_PCI_GROUP:
 312       return 0;
 313    case PIPE_CAP_PCI_BUS:
 314       return 0;
 315    case PIPE_CAP_PCI_DEVICE:
 316       return 2;
 317    case PIPE_CAP_PCI_FUNCTION:
 318       return 0;
 319
 320    default:
 321       return u_pipe_screen_get_param_defaults(pscreen, param);
 322    }
 323    return 0;
 324 }
 325
 326 static float
 327 iris_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 328 {
 329    switch (param) {
 330    case PIPE_CAPF_MAX_LINE_WIDTH:
 331    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 332       return 7.375f;
 333
 334    case PIPE_CAPF_MAX_POINT_WIDTH:
 335    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 336       return 255.0f;
 337
 338    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 339       return 16.0f;
 340    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 341       return 15.0f;
 342    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 343    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 344    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 345       return 0.0f;
 346    default:
 347       unreachable("unknown param");
 348    }
 349 }
 350
 351 static int
 352 iris_get_shader_param(struct pipe_screen *pscreen,
 353                       enum pipe_shader_type p_stage,
 354                       enum pipe_shader_cap param)
 355 {
 356    gl_shader_stage stage = stage_from_pipe(p_stage);
 357
 358    /* this is probably not totally correct.. but it's a start: */
 359    switch (param) {
 360    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 361       return stage == MESA_SHADER_FRAGMENT ? 1024 : 16384;
 362    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 363    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 364    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 365       return stage == MESA_SHADER_FRAGMENT ? 1024 : 0;
 366
 367    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 368       return UINT_MAX;
 369
 370    case PIPE_SHADER_CAP_MAX_INPUTS:
 371       return stage == MESA_SHADER_VERTEX ? 16 : 32;
 372    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 373       return 32;
 374    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 375       return 16 * 1024 * sizeof(float);
 376    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 377       return 16;
 378    case PIPE_SHADER_CAP_MAX_TEMPS:
 379       return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 380    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 381       return 0;
 382    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 383    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 384    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 385    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 386       /* Lie about these to avoid st/mesa's GLSL IR lowering of indirects,
 387        * which we don't want.  Our compiler backend will check brw_compiler's
 388        * options and call nir_lower_indirect_derefs appropriately anyway.
 389        */
 390       return true;
 391    case PIPE_SHADER_CAP_SUBROUTINES:
 392       return 0;
 393    case PIPE_SHADER_CAP_INTEGERS:
 394    case PIPE_SHADER_CAP_SCALAR_ISA:
 395       return 1;
 396    case PIPE_SHADER_CAP_INT64_ATOMICS:
 397    case PIPE_SHADER_CAP_FP16:
 398       return 0;
 399    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 400    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 401    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 402       return IRIS_MAX_TEXTURE_SAMPLERS;
 403    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 404       return IRIS_MAX_ABOS + IRIS_MAX_SSBOS;
 405    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 406    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 407       return 0;
 408    case PIPE_SHADER_CAP_PREFERRED_IR:
 409       return PIPE_SHADER_IR_NIR;
 410    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 411       return 1 << PIPE_SHADER_IR_NIR;
 412    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 413       return 32;
 414    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 415    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 416       return 1;
 417    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 418    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 419    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 420    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 421    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 422    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 423       return 0;
 424    default:
 425       unreachable("unknown shader param");
 426    }
 427 }
 428
 429 static int
 430 iris_get_compute_param(struct pipe_screen *pscreen,
 431                        enum pipe_shader_ir ir_type,
 432                        enum pipe_compute_cap param,
 433                        void *ret)
 434 {
 435    struct iris_screen *screen = (struct iris_screen *)pscreen;
 436    const struct gen_device_info *devinfo = &screen->devinfo;
 437
 438    const unsigned max_threads = MIN2(64, devinfo->max_cs_threads);
 439    const uint32_t max_invocations = 32 * max_threads;
 440
 441 #define RET(x) do {                  \
 442    if (ret)                          \
 443       memcpy(ret, x, sizeof(x));     \
 444    return sizeof(x);                 \
 445 } while (0)
 446
 447    switch (param) {
 448    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 449       RET((uint32_t []){ 32 });
 450
 451    case PIPE_COMPUTE_CAP_IR_TARGET:
 452       if (ret)
 453          strcpy(ret, "gen");
 454       return 4;
 455
 456    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 457       RET((uint64_t []) { 3 });
 458
 459    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 460       RET(((uint64_t []) { 65535, 65535, 65535 }));
 461
 462    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 463       /* MaxComputeWorkGroupSize[0..2] */
 464       RET(((uint64_t []) {max_invocations, max_invocations, max_invocations}));
 465
 466    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 467       /* MaxComputeWorkGroupInvocations */
 468       RET((uint64_t []) { max_invocations });
 469
 470    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 471       /* MaxComputeSharedMemorySize */
 472       RET((uint64_t []) { 64 * 1024 });
 473
 474    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 475       RET((uint32_t []) { 1 });
 476
 477    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 478       RET((uint32_t []) { BRW_SUBGROUP_SIZE });
 479
 480    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 481    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 482    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 483    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 484    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 485    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 486    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 487       // XXX: I think these are for Clover...
 488       return 0;
 489
 490    default:
 491       unreachable("unknown compute param");
 492    }
 493 }
 494
 495 static uint64_t
 496 iris_get_timestamp(struct pipe_screen *pscreen)
 497 {
 498    struct iris_screen *screen = (struct iris_screen *) pscreen;
 499    const unsigned TIMESTAMP = 0x2358;
 500    uint64_t result;
 501
 502    iris_reg_read(screen->bufmgr, TIMESTAMP | 1, &result);
 503
 504    result = iris_timebase_scale(&screen->devinfo, result);
 505    result &= (1ull << TIMESTAMP_BITS) - 1;
 506
 507    return result;
 508 }
 509
 510 static void
 511 iris_destroy_screen(struct pipe_screen *pscreen)
 512 {
 513    struct iris_screen *screen = (struct iris_screen *) pscreen;
 514    iris_bo_unreference(screen->workaround_bo);
 515    u_transfer_helper_destroy(pscreen->transfer_helper);
 516    iris_bufmgr_destroy(screen->bufmgr);
 517    disk_cache_destroy(screen->disk_cache);
 518    ralloc_free(screen);
 519 }
 520
 521 static void
 522 iris_query_memory_info(struct pipe_screen *pscreen,
 523                        struct pipe_memory_info *info)
 524 {
 525 }
 526
 527 static const void *
 528 iris_get_compiler_options(struct pipe_screen *pscreen,
 529                           enum pipe_shader_ir ir,
 530                           enum pipe_shader_type pstage)
 531 {
 532    struct iris_screen *screen = (struct iris_screen *) pscreen;
 533    gl_shader_stage stage = stage_from_pipe(pstage);
 534    assert(ir == PIPE_SHADER_IR_NIR);
 535
 536    return screen->compiler->glsl_compiler_options[stage].NirOptions;
 537 }
 538
 539 static struct disk_cache *
 540 iris_get_disk_shader_cache(struct pipe_screen *pscreen)
 541 {
 542    struct iris_screen *screen = (struct iris_screen *) pscreen;
 543    return screen->disk_cache;
 544 }
 545
 546 static int
 547 iris_getparam(struct iris_screen *screen, int param, int *value)
 548 {
 549    struct drm_i915_getparam gp = { .param = param, .value = value };
 550
 551    if (ioctl(screen->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1)
 552       return -errno;
 553
 554    return 0;
 555 }
 556
 557 static int
 558 iris_getparam_integer(struct iris_screen *screen, int param)
 559 {
 560    int value = -1;
 561
 562    if (iris_getparam(screen, param, &value) == 0)
 563       return value;
 564
 565    return -1;
 566 }
 567
 568 static void
 569 iris_shader_debug_log(void *data, const char *fmt, ...)
 570 {
 571    struct pipe_debug_callback *dbg = data;
 572    unsigned id = 0;
 573    va_list args;
 574
 575    if (!dbg->debug_message)
 576       return;
 577
 578    va_start(args, fmt);
 579    dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_SHADER_INFO, fmt, args);
 580    va_end(args);
 581 }
 582
 583 static void
 584 iris_shader_perf_log(void *data, const char *fmt, ...)
 585 {
 586    struct pipe_debug_callback *dbg = data;
 587    unsigned id = 0;
 588    va_list args;
 589    va_start(args, fmt);
 590
 591    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
 592       va_list args_copy;
 593       va_copy(args_copy, args);
 594       vfprintf(stderr, fmt, args_copy);
 595       va_end(args_copy);
 596    }
 597
 598    if (dbg->debug_message) {
 599       dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args);
 600    }
 601
 602    va_end(args);
 603 }
 604
 605 struct pipe_screen *
 606 iris_screen_create(int fd, const struct pipe_screen_config *config)
 607 {
 608    struct iris_screen *screen = rzalloc(NULL, struct iris_screen);
 609    if (!screen)
 610       return NULL;
 611
 612    screen->fd = fd;
 613    screen->pci_id = iris_getparam_integer(screen, I915_PARAM_CHIPSET_ID);
 614
 615    if (!gen_get_device_info(screen->pci_id, &screen->devinfo))
 616       return NULL;
 617
 618    if (screen->devinfo.gen < 8 || screen->devinfo.is_cherryview)
 619       return NULL;
 620
 621    screen->devinfo.timestamp_frequency =
 622       iris_getparam_integer(screen, I915_PARAM_CS_TIMESTAMP_FREQUENCY);
 623
 624    screen->aperture_bytes = get_aperture_size(fd);
 625
 626    if (getenv("INTEL_NO_HW") != NULL)
 627       screen->no_hw = true;
 628
 629    screen->bufmgr = iris_bufmgr_init(&screen->devinfo, fd);
 630    if (!screen->bufmgr)
 631       return NULL;
 632
 633    screen->workaround_bo =
 634       iris_bo_alloc(screen->bufmgr, "workaround", 4096, IRIS_MEMZONE_OTHER);
 635    if (!screen->workaround_bo)
 636       return NULL;
 637
 638    brw_process_intel_debug_variable();
 639
 640    screen->driconf.dual_color_blend_by_location =
 641       driQueryOptionb(config->options, "dual_color_blend_by_location");
 642
 643    screen->precompile = env_var_as_boolean("shader_precompile", true);
 644
 645    isl_device_init(&screen->isl_dev, &screen->devinfo, false);
 646
 647    screen->compiler = brw_compiler_create(screen, &screen->devinfo);
 648    screen->compiler->shader_debug_log = iris_shader_debug_log;
 649    screen->compiler->shader_perf_log = iris_shader_perf_log;
 650    screen->compiler->supports_pull_constants = false;
 651    screen->compiler->supports_shader_constants = true;
 652
 653    iris_disk_cache_init(screen);
 654
 655    slab_create_parent(&screen->transfer_pool,
 656                       sizeof(struct iris_transfer), 64);
 657
 658    screen->subslice_total =
 659       iris_getparam_integer(screen, I915_PARAM_SUBSLICE_TOTAL);
 660    assert(screen->subslice_total >= 1);
 661
 662    struct pipe_screen *pscreen = &screen->base;
 663
 664    iris_init_screen_fence_functions(pscreen);
 665    iris_init_screen_resource_functions(pscreen);
 666
 667    pscreen->destroy = iris_destroy_screen;
 668    pscreen->get_name = iris_get_name;
 669    pscreen->get_vendor = iris_get_vendor;
 670    pscreen->get_device_vendor = iris_get_device_vendor;
 671    pscreen->get_param = iris_get_param;
 672    pscreen->get_shader_param = iris_get_shader_param;
 673    pscreen->get_compute_param = iris_get_compute_param;
 674    pscreen->get_paramf = iris_get_paramf;
 675    pscreen->get_compiler_options = iris_get_compiler_options;
 676    pscreen->get_disk_shader_cache = iris_get_disk_shader_cache;
 677    pscreen->is_format_supported = iris_is_format_supported;
 678    pscreen->context_create = iris_create_context;
 679    pscreen->flush_frontbuffer = iris_flush_frontbuffer;
 680    pscreen->get_timestamp = iris_get_timestamp;
 681    pscreen->query_memory_info = iris_query_memory_info;
 682
 683    return pscreen;
 684 }