src/gallium/drivers/iris/iris_screen.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 /**
  24  * @file iris_screen.c
  25  *
  26  * Screen related driver hooks and capability lists.
  27  *
  28  * A program may use multiple rendering contexts (iris_context), but
  29  * they all share a common screen (iris_screen).  Global driver state
  30  * can be stored in the screen; it may be accessed by multiple threads.
  31  */
  32
  33 #include <stdio.h>
  34 #include <errno.h>
  35 #include <sys/ioctl.h>
  36 #include "pipe/p_defines.h"
  37 #include "pipe/p_state.h"
  38 #include "pipe/p_context.h"
  39 #include "pipe/p_screen.h"
  40 #include "util/debug.h"
  41 #include "util/u_inlines.h"
  42 #include "util/format/u_format.h"
  43 #include "util/u_transfer_helper.h"
  44 #include "util/u_upload_mgr.h"
  45 #include "util/ralloc.h"
  46 #include "util/xmlconfig.h"
  47 #include "drm-uapi/i915_drm.h"
  48 #include "iris_context.h"
  49 #include "iris_defines.h"
  50 #include "iris_fence.h"
  51 #include "iris_pipe.h"
  52 #include "iris_resource.h"
  53 #include "iris_screen.h"
  54 #include "intel/compiler/brw_compiler.h"
  55 #include "intel/common/gen_gem.h"
  56 #include "intel/common/gen_l3_config.h"
  57 #include "iris_monitor.h"
  58
  59 static void
  60 iris_flush_frontbuffer(struct pipe_screen *_screen,
  61                        struct pipe_resource *resource,
  62                        unsigned level, unsigned layer,
  63                        void *context_private, struct pipe_box *box)
  64 {
  65 }
  66
  67 static const char *
  68 iris_get_vendor(struct pipe_screen *pscreen)
  69 {
  70    return "Intel";
  71 }
  72
  73 static const char *
  74 iris_get_device_vendor(struct pipe_screen *pscreen)
  75 {
  76    return "Intel";
  77 }
  78
  79 static const char *
  80 iris_get_name(struct pipe_screen *pscreen)
  81 {
  82    struct iris_screen *screen = (struct iris_screen *)pscreen;
  83    static char buf[128];
  84    const char *name = gen_get_device_name(screen->pci_id);
  85
  86    if (!name)
  87       name = "Intel Unknown";
  88
  89    snprintf(buf, sizeof(buf), "Mesa %s", name);
  90    return buf;
  91 }
  92
  93 static uint64_t
  94 get_aperture_size(int fd)
  95 {
  96    struct drm_i915_gem_get_aperture aperture = {};
  97    gen_ioctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
  98    return aperture.aper_size;
  99 }
 100
 101 static int
 102 iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 103 {
 104    struct iris_screen *screen = (struct iris_screen *)pscreen;
 105    const struct gen_device_info *devinfo = &screen->devinfo;
 106
 107    switch (param) {
 108    case PIPE_CAP_NPOT_TEXTURES:
 109    case PIPE_CAP_ANISOTROPIC_FILTER:
 110    case PIPE_CAP_POINT_SPRITE:
 111    case PIPE_CAP_OCCLUSION_QUERY:
 112    case PIPE_CAP_QUERY_TIME_ELAPSED:
 113    case PIPE_CAP_TEXTURE_SWIZZLE:
 114    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 115    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 116    case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
 117    case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
 118    case PIPE_CAP_VERTEX_SHADER_SATURATE:
 119    case PIPE_CAP_PRIMITIVE_RESTART:
 120    case PIPE_CAP_INDEP_BLEND_ENABLE:
 121    case PIPE_CAP_INDEP_BLEND_FUNC:
 122    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
 123    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 124    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 125    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 126    case PIPE_CAP_TGSI_INSTANCEID:
 127    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 128    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 129    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 130    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 131    case PIPE_CAP_CONDITIONAL_RENDER:
 132    case PIPE_CAP_TEXTURE_BARRIER:
 133    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 134    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 135    case PIPE_CAP_COMPUTE:
 136    case PIPE_CAP_START_INSTANCE:
 137    case PIPE_CAP_QUERY_TIMESTAMP:
 138    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 139    case PIPE_CAP_CUBE_MAP_ARRAY:
 140    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 141    case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
 142    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 143    case PIPE_CAP_TEXTURE_QUERY_LOD:
 144    case PIPE_CAP_SAMPLE_SHADING:
 145    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 146    case PIPE_CAP_DRAW_INDIRECT:
 147    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 148    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 149    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 150    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 151    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 152    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 153    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 154    case PIPE_CAP_ACCELERATED:
 155    case PIPE_CAP_UMA:
 156    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 157    case PIPE_CAP_CLIP_HALFZ:
 158    case PIPE_CAP_TGSI_TEXCOORD:
 159    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 160    case PIPE_CAP_DOUBLES:
 161    case PIPE_CAP_INT64:
 162    case PIPE_CAP_INT64_DIVMOD:
 163    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 164    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 165    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 166    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 167    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 168    case PIPE_CAP_CULL_DISTANCE:
 169    case PIPE_CAP_PACKED_UNIFORMS:
 170    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 171    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 172    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 173    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 174    case PIPE_CAP_QUERY_SO_OVERFLOW:
 175    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 176    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 177    case PIPE_CAP_TGSI_TXQS:
 178    case PIPE_CAP_TGSI_CLOCK:
 179    case PIPE_CAP_TGSI_BALLOT:
 180    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 181    case PIPE_CAP_CLEAR_TEXTURE:
 182    case PIPE_CAP_CLEAR_SCISSORED:
 183    case PIPE_CAP_TGSI_VOTE:
 184    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 185    case PIPE_CAP_TEXTURE_GATHER_SM5:
 186    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 187    case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
 188    case PIPE_CAP_LOAD_CONSTBUF:
 189    case PIPE_CAP_NIR_COMPACT_ARRAYS:
 190    case PIPE_CAP_DRAW_PARAMETERS:
 191    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 192    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 193    case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
 194    case PIPE_CAP_INVALIDATE_BUFFER:
 195    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 196    case PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED:
 197    case PIPE_CAP_TEXTURE_SHADOW_LOD:
 198    case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
 199    case PIPE_CAP_GL_SPIRV:
 200    case PIPE_CAP_GL_SPIRV_VARIABLE_POINTERS:
 201    case PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION:
 202    case PIPE_CAP_NATIVE_FENCE_FD:
 203    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 204       return true;
 205    case PIPE_CAP_FBFETCH:
 206       return BRW_MAX_DRAW_BUFFERS;
 207    case PIPE_CAP_FBFETCH_COHERENT:
 208    case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE:
 209    case PIPE_CAP_POST_DEPTH_COVERAGE:
 210    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 211    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 212    case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK:
 213    case PIPE_CAP_ATOMIC_FLOAT_MINMAX:
 214       return devinfo->gen >= 9;
 215    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 216       return devinfo->gen >= 12;
 217    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 218       return 1;
 219    case PIPE_CAP_MAX_RENDER_TARGETS:
 220       return BRW_MAX_DRAW_BUFFERS;
 221    case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 222       return 16384;
 223    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 224       return IRIS_MAX_MIPLEVELS; /* 16384x16384 */
 225    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 226       return 12; /* 2048x2048 */
 227    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 228       return 4;
 229    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 230       return 2048;
 231    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 232       return BRW_MAX_SOL_BINDINGS / IRIS_MAX_SOL_BUFFERS;
 233    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 234       return BRW_MAX_SOL_BINDINGS;
 235    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 236    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 237       return 460;
 238    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 239       /* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */
 240       return 32;
 241    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 242       return IRIS_MAP_BUFFER_ALIGNMENT;
 243    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 244       /* Choose a cacheline (64 bytes) so that we can safely have the CPU and
 245        * GPU writing the same SSBO on non-coherent systems (Atom CPUs).  With
 246        * UBOs, the GPU never writes, so there's no problem.  For an SSBO, the
 247        * GPU and the CPU can be updating disjoint regions of the buffer
 248        * simultaneously and that will break if the regions overlap the same
 249        * cacheline.
 250        */
 251       return 64;
 252    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 253       return 1 << 27;
 254    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 255       return 16; // XXX: u_screen says 256 is the minimum value...
 256    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 257       return true;
 258    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 259       return IRIS_MAX_TEXTURE_BUFFER_SIZE;
 260    case PIPE_CAP_MAX_VIEWPORTS:
 261       return 16;
 262    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 263       return 256;
 264    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 265       return 1024;
 266    case PIPE_CAP_MAX_GS_INVOCATIONS:
 267       return 32;
 268    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 269       return 4;
 270    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 271       return -32;
 272    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 273       return 31;
 274    case PIPE_CAP_MAX_VERTEX_STREAMS:
 275       return 4;
 276    case PIPE_CAP_VENDOR_ID:
 277       return 0x8086;
 278    case PIPE_CAP_DEVICE_ID:
 279       return screen->pci_id;
 280    case PIPE_CAP_VIDEO_MEMORY: {
 281       /* Once a batch uses more than 75% of the maximum mappable size, we
 282        * assume that there's some fragmentation, and we start doing extra
 283        * flushing, etc.  That's the big cliff apps will care about.
 284        */
 285       const unsigned gpu_mappable_megabytes =
 286          (screen->aperture_bytes * 3 / 4) / (1024 * 1024);
 287
 288       const long system_memory_pages = sysconf(_SC_PHYS_PAGES);
 289       const long system_page_size = sysconf(_SC_PAGE_SIZE);
 290
 291       if (system_memory_pages <= 0 || system_page_size <= 0)
 292          return -1;
 293
 294       const uint64_t system_memory_bytes =
 295          (uint64_t) system_memory_pages * (uint64_t) system_page_size;
 296
 297       const unsigned system_memory_megabytes =
 298          (unsigned) (system_memory_bytes / (1024 * 1024));
 299
 300       return MIN2(system_memory_megabytes, gpu_mappable_megabytes);
 301    }
 302    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 303    case PIPE_CAP_MAX_VARYINGS:
 304       return 32;
 305    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 306       /* AMD_pinned_memory assumes the flexibility of using client memory
 307        * for any buffer (incl. vertex buffers) which rules out the prospect
 308        * of using snooped buffers, as using snooped buffers without
 309        * cogniscience is likely to be detrimental to performance and require
 310        * extensive checking in the driver for correctness, e.g. to prevent
 311        * illegal snoop <-> snoop transfers.
 312        */
 313       return devinfo->has_llc;
 314    case PIPE_CAP_THROTTLE:
 315       return screen->driconf.disable_throttling ? 0 : 1;
 316
 317    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 318       return PIPE_CONTEXT_PRIORITY_LOW |
 319              PIPE_CONTEXT_PRIORITY_MEDIUM |
 320              PIPE_CONTEXT_PRIORITY_HIGH;
 321
 322    case PIPE_CAP_FRONTEND_NOOP:
 323       return true;
 324
 325    // XXX: don't hardcode 00:00:02.0 PCI here
 326    case PIPE_CAP_PCI_GROUP:
 327       return 0;
 328    case PIPE_CAP_PCI_BUS:
 329       return 0;
 330    case PIPE_CAP_PCI_DEVICE:
 331       return 2;
 332    case PIPE_CAP_PCI_FUNCTION:
 333       return 0;
 334
 335    case PIPE_CAP_OPENCL_INTEGER_FUNCTIONS:
 336    case PIPE_CAP_INTEGER_MULTIPLY_32X16:
 337       return true;
 338
 339    default:
 340       return u_pipe_screen_get_param_defaults(pscreen, param);
 341    }
 342    return 0;
 343 }
 344
 345 static float
 346 iris_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 347 {
 348    switch (param) {
 349    case PIPE_CAPF_MAX_LINE_WIDTH:
 350    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 351       return 7.375f;
 352
 353    case PIPE_CAPF_MAX_POINT_WIDTH:
 354    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 355       return 255.0f;
 356
 357    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 358       return 16.0f;
 359    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 360       return 15.0f;
 361    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 362    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 363    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 364       return 0.0f;
 365    default:
 366       unreachable("unknown param");
 367    }
 368 }
 369
 370 static int
 371 iris_get_shader_param(struct pipe_screen *pscreen,
 372                       enum pipe_shader_type p_stage,
 373                       enum pipe_shader_cap param)
 374 {
 375    gl_shader_stage stage = stage_from_pipe(p_stage);
 376
 377    /* this is probably not totally correct.. but it's a start: */
 378    switch (param) {
 379    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 380       return stage == MESA_SHADER_FRAGMENT ? 1024 : 16384;
 381    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 382    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 383    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 384       return stage == MESA_SHADER_FRAGMENT ? 1024 : 0;
 385
 386    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 387       return UINT_MAX;
 388
 389    case PIPE_SHADER_CAP_MAX_INPUTS:
 390       return stage == MESA_SHADER_VERTEX ? 16 : 32;
 391    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 392       return 32;
 393    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 394       return 16 * 1024 * sizeof(float);
 395    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 396       return 16;
 397    case PIPE_SHADER_CAP_MAX_TEMPS:
 398       return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 399    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 400       return 0;
 401    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 402    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 403    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 404    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 405       /* Lie about these to avoid st/mesa's GLSL IR lowering of indirects,
 406        * which we don't want.  Our compiler backend will check brw_compiler's
 407        * options and call nir_lower_indirect_derefs appropriately anyway.
 408        */
 409       return true;
 410    case PIPE_SHADER_CAP_SUBROUTINES:
 411       return 0;
 412    case PIPE_SHADER_CAP_INTEGERS:
 413       return 1;
 414    case PIPE_SHADER_CAP_INT64_ATOMICS:
 415    case PIPE_SHADER_CAP_FP16:
 416       return 0;
 417    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 418    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 419    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 420       return IRIS_MAX_TEXTURE_SAMPLERS;
 421    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 422       return IRIS_MAX_ABOS + IRIS_MAX_SSBOS;
 423    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 424    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 425       return 0;
 426    case PIPE_SHADER_CAP_PREFERRED_IR:
 427       return PIPE_SHADER_IR_NIR;
 428    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 429       return 1 << PIPE_SHADER_IR_NIR;
 430    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 431    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 432       return 1;
 433    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 434    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 435    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 436    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 437    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 438    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 439    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 440       return 0;
 441    default:
 442       unreachable("unknown shader param");
 443    }
 444 }
 445
 446 static int
 447 iris_get_compute_param(struct pipe_screen *pscreen,
 448                        enum pipe_shader_ir ir_type,
 449                        enum pipe_compute_cap param,
 450                        void *ret)
 451 {
 452    struct iris_screen *screen = (struct iris_screen *)pscreen;
 453    const struct gen_device_info *devinfo = &screen->devinfo;
 454
 455    const unsigned max_threads = MIN2(64, devinfo->max_cs_threads);
 456    const uint32_t max_invocations = 32 * max_threads;
 457
 458 #define RET(x) do {                  \
 459    if (ret)                          \
 460       memcpy(ret, x, sizeof(x));     \
 461    return sizeof(x);                 \
 462 } while (0)
 463
 464    switch (param) {
 465    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 466       RET((uint32_t []){ 32 });
 467
 468    case PIPE_COMPUTE_CAP_IR_TARGET:
 469       if (ret)
 470          strcpy(ret, "gen");
 471       return 4;
 472
 473    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 474       RET((uint64_t []) { 3 });
 475
 476    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 477       RET(((uint64_t []) { 65535, 65535, 65535 }));
 478
 479    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 480       /* MaxComputeWorkGroupSize[0..2] */
 481       RET(((uint64_t []) {max_invocations, max_invocations, max_invocations}));
 482
 483    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 484       /* MaxComputeWorkGroupInvocations */
 485       RET((uint64_t []) { max_invocations });
 486
 487    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 488       /* MaxComputeSharedMemorySize */
 489       RET((uint64_t []) { 64 * 1024 });
 490
 491    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 492       RET((uint32_t []) { 1 });
 493
 494    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 495       RET((uint32_t []) { BRW_SUBGROUP_SIZE });
 496
 497    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 498    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 499    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 500    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 501    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 502    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 503    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 504       // XXX: I think these are for Clover...
 505       return 0;
 506
 507    default:
 508       unreachable("unknown compute param");
 509    }
 510 }
 511
 512 static uint64_t
 513 iris_get_timestamp(struct pipe_screen *pscreen)
 514 {
 515    struct iris_screen *screen = (struct iris_screen *) pscreen;
 516    const unsigned TIMESTAMP = 0x2358;
 517    uint64_t result;
 518
 519    iris_reg_read(screen->bufmgr, TIMESTAMP | 1, &result);
 520
 521    result = gen_device_info_timebase_scale(&screen->devinfo, result);
 522    result &= (1ull << TIMESTAMP_BITS) - 1;
 523
 524    return result;
 525 }
 526
 527 void
 528 iris_screen_destroy(struct iris_screen *screen)
 529 {
 530    iris_bo_unreference(screen->workaround_bo);
 531    u_transfer_helper_destroy(screen->base.transfer_helper);
 532    iris_bufmgr_unref(screen->bufmgr);
 533    disk_cache_destroy(screen->disk_cache);
 534    ralloc_free(screen);
 535 }
 536
 537 static void
 538 iris_screen_unref(struct pipe_screen *pscreen)
 539 {
 540    iris_pscreen_unref(pscreen);
 541 }
 542
 543 static void
 544 iris_query_memory_info(struct pipe_screen *pscreen,
 545                        struct pipe_memory_info *info)
 546 {
 547 }
 548
 549 static const void *
 550 iris_get_compiler_options(struct pipe_screen *pscreen,
 551                           enum pipe_shader_ir ir,
 552                           enum pipe_shader_type pstage)
 553 {
 554    struct iris_screen *screen = (struct iris_screen *) pscreen;
 555    gl_shader_stage stage = stage_from_pipe(pstage);
 556    assert(ir == PIPE_SHADER_IR_NIR);
 557
 558    return screen->compiler->glsl_compiler_options[stage].NirOptions;
 559 }
 560
 561 static struct disk_cache *
 562 iris_get_disk_shader_cache(struct pipe_screen *pscreen)
 563 {
 564    struct iris_screen *screen = (struct iris_screen *) pscreen;
 565    return screen->disk_cache;
 566 }
 567
 568 static int
 569 iris_getparam(int fd, int param, int *value)
 570 {
 571    struct drm_i915_getparam gp = { .param = param, .value = value };
 572
 573    if (ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1)
 574       return -errno;
 575
 576    return 0;
 577 }
 578
 579 static int
 580 iris_getparam_integer(int fd, int param)
 581 {
 582    int value = -1;
 583
 584    if (iris_getparam(fd, param, &value) == 0)
 585       return value;
 586
 587    return -1;
 588 }
 589
 590 static const struct gen_l3_config *
 591 iris_get_default_l3_config(const struct gen_device_info *devinfo,
 592                            bool compute)
 593 {
 594    bool wants_dc_cache = true;
 595    bool has_slm = compute;
 596    const struct gen_l3_weights w =
 597       gen_get_default_l3_weights(devinfo, wants_dc_cache, has_slm);
 598    return gen_get_l3_config(devinfo, w);
 599 }
 600
 601 static void
 602 iris_shader_debug_log(void *data, const char *fmt, ...)
 603 {
 604    struct pipe_debug_callback *dbg = data;
 605    unsigned id = 0;
 606    va_list args;
 607
 608    if (!dbg->debug_message)
 609       return;
 610
 611    va_start(args, fmt);
 612    dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_SHADER_INFO, fmt, args);
 613    va_end(args);
 614 }
 615
 616 static void
 617 iris_shader_perf_log(void *data, const char *fmt, ...)
 618 {
 619    struct pipe_debug_callback *dbg = data;
 620    unsigned id = 0;
 621    va_list args;
 622    va_start(args, fmt);
 623
 624    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
 625       va_list args_copy;
 626       va_copy(args_copy, args);
 627       vfprintf(stderr, fmt, args_copy);
 628       va_end(args_copy);
 629    }
 630
 631    if (dbg->debug_message) {
 632       dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args);
 633    }
 634
 635    va_end(args);
 636 }
 637
 638 static void
 639 iris_detect_kernel_features(struct iris_screen *screen)
 640 {
 641    /* Kernel 5.2+ */
 642    if (gen_gem_supports_syncobj_wait(screen->fd))
 643       screen->kernel_features |= KERNEL_HAS_WAIT_FOR_SUBMIT;
 644 }
 645
 646 struct pipe_screen *
 647 iris_screen_create(int fd, const struct pipe_screen_config *config)
 648 {
 649    /* Here are the i915 features we need for Iris (in chronoligical order) :
 650     *    - I915_PARAM_HAS_EXEC_NO_RELOC     (3.10)
 651     *    - I915_PARAM_HAS_EXEC_HANDLE_LUT   (3.10)
 652     *    - I915_PARAM_HAS_EXEC_BATCH_FIRST  (4.13)
 653     *    - I915_PARAM_HAS_EXEC_FENCE_ARRAY  (4.14)
 654     *    - I915_PARAM_HAS_CONTEXT_ISOLATION (4.16)
 655     *
 656     * Checking the last feature availability will include all previous ones.
 657     */
 658    if (!iris_getparam_integer(fd, I915_PARAM_HAS_CONTEXT_ISOLATION)) {
 659       debug_error("Kernel is too old for Iris. Consider upgrading to kernel v4.16.\n");
 660       return NULL;
 661    }
 662
 663    struct iris_screen *screen = rzalloc(NULL, struct iris_screen);
 664    if (!screen)
 665       return NULL;
 666
 667    if (!gen_get_device_info_from_fd(fd, &screen->devinfo))
 668       return NULL;
 669    screen->pci_id = screen->devinfo.chipset_id;
 670    screen->no_hw = screen->devinfo.no_hw;
 671
 672    p_atomic_set(&screen->refcount, 1);
 673
 674    if (screen->devinfo.gen < 8 || screen->devinfo.is_cherryview)
 675       return NULL;
 676
 677    bool bo_reuse = false;
 678    int bo_reuse_mode = driQueryOptioni(config->options, "bo_reuse");
 679    switch (bo_reuse_mode) {
 680    case DRI_CONF_BO_REUSE_DISABLED:
 681       break;
 682    case DRI_CONF_BO_REUSE_ALL:
 683       bo_reuse = true;
 684       break;
 685    }
 686
 687    screen->bufmgr = iris_bufmgr_get_for_fd(&screen->devinfo, fd, bo_reuse);
 688    if (!screen->bufmgr)
 689       return NULL;
 690
 691    screen->fd = iris_bufmgr_get_fd(screen->bufmgr);
 692
 693    screen->aperture_bytes = get_aperture_size(fd);
 694
 695    if (getenv("INTEL_NO_HW") != NULL)
 696       screen->no_hw = true;
 697
 698    screen->workaround_bo =
 699       iris_bo_alloc(screen->bufmgr, "workaround", 4096, IRIS_MEMZONE_OTHER);
 700    if (!screen->workaround_bo)
 701       return NULL;
 702
 703    brw_process_intel_debug_variable();
 704
 705    screen->driconf.dual_color_blend_by_location =
 706       driQueryOptionb(config->options, "dual_color_blend_by_location");
 707    screen->driconf.disable_throttling =
 708       driQueryOptionb(config->options, "disable_throttling");
 709    screen->driconf.always_flush_cache =
 710       driQueryOptionb(config->options, "always_flush_cache");
 711
 712    screen->precompile = env_var_as_boolean("shader_precompile", true);
 713
 714    isl_device_init(&screen->isl_dev, &screen->devinfo, false);
 715
 716    screen->compiler = brw_compiler_create(screen, &screen->devinfo);
 717    screen->compiler->shader_debug_log = iris_shader_debug_log;
 718    screen->compiler->shader_perf_log = iris_shader_perf_log;
 719    screen->compiler->supports_pull_constants = false;
 720    screen->compiler->supports_shader_constants = true;
 721    screen->compiler->compact_params = false;
 722
 723    screen->l3_config_3d = iris_get_default_l3_config(&screen->devinfo, false);
 724    screen->l3_config_cs = iris_get_default_l3_config(&screen->devinfo, true);
 725
 726    iris_disk_cache_init(screen);
 727
 728    slab_create_parent(&screen->transfer_pool,
 729                       sizeof(struct iris_transfer), 64);
 730
 731    screen->subslice_total =
 732       iris_getparam_integer(screen->fd, I915_PARAM_SUBSLICE_TOTAL);
 733    assert(screen->subslice_total >= 1);
 734
 735    iris_detect_kernel_features(screen);
 736
 737    struct pipe_screen *pscreen = &screen->base;
 738
 739    iris_init_screen_fence_functions(pscreen);
 740    iris_init_screen_resource_functions(pscreen);
 741
 742    pscreen->destroy = iris_screen_unref;
 743    pscreen->get_name = iris_get_name;
 744    pscreen->get_vendor = iris_get_vendor;
 745    pscreen->get_device_vendor = iris_get_device_vendor;
 746    pscreen->get_param = iris_get_param;
 747    pscreen->get_shader_param = iris_get_shader_param;
 748    pscreen->get_compute_param = iris_get_compute_param;
 749    pscreen->get_paramf = iris_get_paramf;
 750    pscreen->get_compiler_options = iris_get_compiler_options;
 751    pscreen->get_disk_shader_cache = iris_get_disk_shader_cache;
 752    pscreen->is_format_supported = iris_is_format_supported;
 753    pscreen->context_create = iris_create_context;
 754    pscreen->flush_frontbuffer = iris_flush_frontbuffer;
 755    pscreen->get_timestamp = iris_get_timestamp;
 756    pscreen->query_memory_info = iris_query_memory_info;
 757    pscreen->get_driver_query_group_info = iris_get_monitor_group_info;
 758    pscreen->get_driver_query_info = iris_get_monitor_info;
 759
 760    return pscreen;
 761 }