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26 * ============================= GENXML CODE =============================
27 * [This file is compiled once per generation.]
28 * =======================================================================
30 * This is the main state upload code.
32 * Gallium uses Constant State Objects, or CSOs, for most state. Large,
33 * complex, or highly reusable state can be created once, and bound and
34 * rebound multiple times. This is modeled with the pipe->create_*_state()
35 * and pipe->bind_*_state() hooks. Highly dynamic or inexpensive state is
36 * streamed out on the fly, via pipe->set_*_state() hooks.
38 * OpenGL involves frequently mutating context state, which is mirrored in
39 * core Mesa by highly mutable data structures. However, most applications
40 * typically draw the same things over and over - from frame to frame, most
41 * of the same objects are still visible and need to be redrawn. So, rather
42 * than inventing new state all the time, applications usually mutate to swap
43 * between known states that we've seen before.
45 * Gallium isolates us from this mutation by tracking API state, and
46 * distilling it into a set of Constant State Objects, or CSOs. Large,
47 * complex, or typically reusable state can be created once, then reused
48 * multiple times. Drivers can create and store their own associated data.
49 * This create/bind model corresponds to the pipe->create_*_state() and
50 * pipe->bind_*_state() driver hooks.
52 * Some state is cheap to create, or expected to be highly dynamic. Rather
53 * than creating and caching piles of CSOs for these, Gallium simply streams
54 * them out, via the pipe->set_*_state() driver hooks.
56 * To reduce draw time overhead, we try to compute as much state at create
57 * time as possible. Wherever possible, we translate the Gallium pipe state
58 * to 3DSTATE commands, and store those commands in the CSO. At draw time,
59 * we can simply memcpy them into a batch buffer.
61 * No hardware matches the abstraction perfectly, so some commands require
62 * information from multiple CSOs. In this case, we can store two copies
63 * of the packet (one in each CSO), and simply | together their DWords at
64 * draw time. Sometimes the second set is trivial (one or two fields), so
65 * we simply pack it at draw time.
67 * There are two main components in the file below. First, the CSO hooks
68 * create/bind/track state. The second are the draw-time upload functions,
69 * iris_upload_render_state() and iris_upload_compute_state(), which read
70 * the context state and emit the commands into the actual batch.
81 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
87 #include "pipe/p_defines.h"
88 #include "pipe/p_state.h"
89 #include "pipe/p_context.h"
90 #include "pipe/p_screen.h"
91 #include "util/u_dual_blend.h"
92 #include "util/u_inlines.h"
93 #include "util/u_format.h"
94 #include "util/u_framebuffer.h"
95 #include "util/u_transfer.h"
96 #include "util/u_upload_mgr.h"
97 #include "util/u_viewport.h"
98 #include "drm-uapi/i915_drm.h"
100 #include "intel/compiler/brw_compiler.h"
101 #include "intel/common/gen_l3_config.h"
102 #include "intel/common/gen_sample_positions.h"
103 #include "iris_batch.h"
104 #include "iris_context.h"
105 #include "iris_defines.h"
106 #include "iris_pipe.h"
107 #include "iris_resource.h"
109 #include "iris_genx_macros.h"
110 #include "intel/common/gen_guardband.h"
113 #define MOCS_PTE 0x18
116 #define MOCS_PTE (1 << 1)
117 #define MOCS_WB (2 << 1)
121 mocs(const struct iris_bo
*bo
)
123 return bo
&& bo
->external
? MOCS_PTE
: MOCS_WB
;
127 * Statically assert that PIPE_* enums match the hardware packets.
128 * (As long as they match, we don't need to translate them.)
130 UNUSED
static void pipe_asserts()
132 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
134 /* pipe_logicop happens to match the hardware. */
135 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
136 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
137 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
138 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
139 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
140 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
141 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
142 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
143 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
144 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
145 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
146 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
147 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
148 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
149 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
150 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
152 /* pipe_blend_func happens to match the hardware. */
153 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
154 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
155 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
156 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
157 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
158 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
159 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
160 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
161 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
162 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
163 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
164 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
165 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
166 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
167 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
168 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
169 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
170 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
171 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
173 /* pipe_blend_func happens to match the hardware. */
174 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
175 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
176 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
177 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
178 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
180 /* pipe_stencil_op happens to match the hardware. */
181 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
182 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
183 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
184 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
185 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
186 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
187 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
188 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
190 /* pipe_sprite_coord_mode happens to match 3DSTATE_SBE */
191 PIPE_ASSERT(PIPE_SPRITE_COORD_UPPER_LEFT
== UPPERLEFT
);
192 PIPE_ASSERT(PIPE_SPRITE_COORD_LOWER_LEFT
== LOWERLEFT
);
197 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
199 static const unsigned map
[] = {
200 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
201 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
202 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
203 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
204 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
205 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
206 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
207 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
208 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
209 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
210 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
211 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
212 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
213 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
214 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
217 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
221 translate_compare_func(enum pipe_compare_func pipe_func
)
223 static const unsigned map
[] = {
224 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
225 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
226 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
227 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
228 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
229 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
230 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
231 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
233 return map
[pipe_func
];
237 translate_shadow_func(enum pipe_compare_func pipe_func
)
239 /* Gallium specifies the result of shadow comparisons as:
241 * 1 if ref <op> texel,
246 * 0 if texel <op> ref,
249 * So we need to flip the operator and also negate.
251 static const unsigned map
[] = {
252 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
253 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
254 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
255 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
256 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
257 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
258 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
259 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
261 return map
[pipe_func
];
265 translate_cull_mode(unsigned pipe_face
)
267 static const unsigned map
[4] = {
268 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
269 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
270 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
271 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
273 return map
[pipe_face
];
277 translate_fill_mode(unsigned pipe_polymode
)
279 static const unsigned map
[4] = {
280 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
281 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
282 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
283 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
285 return map
[pipe_polymode
];
289 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
291 static const unsigned map
[] = {
292 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
293 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
294 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
296 return map
[pipe_mip
];
300 translate_wrap(unsigned pipe_wrap
)
302 static const unsigned map
[] = {
303 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
304 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
305 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
306 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
307 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
308 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
310 /* These are unsupported. */
311 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1,
312 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1,
314 return map
[pipe_wrap
];
318 * Allocate space for some indirect state.
320 * Return a pointer to the map (to fill it out) and a state ref (for
321 * referring to the state in GPU commands).
324 upload_state(struct u_upload_mgr
*uploader
,
325 struct iris_state_ref
*ref
,
330 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
335 * Stream out temporary/short-lived state.
337 * This allocates space, pins the BO, and includes the BO address in the
338 * returned offset (which works because all state lives in 32-bit memory
342 stream_state(struct iris_batch
*batch
,
343 struct u_upload_mgr
*uploader
,
344 struct pipe_resource
**out_res
,
347 uint32_t *out_offset
)
351 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, out_res
, &ptr
);
353 struct iris_bo
*bo
= iris_resource_bo(*out_res
);
354 iris_use_pinned_bo(batch
, bo
, false);
356 *out_offset
+= iris_bo_offset_from_base_address(bo
);
358 iris_record_state_size(batch
->state_sizes
, *out_offset
, size
);
364 * stream_state() + memcpy.
367 emit_state(struct iris_batch
*batch
,
368 struct u_upload_mgr
*uploader
,
369 struct pipe_resource
**out_res
,
376 stream_state(batch
, uploader
, out_res
, size
, alignment
, &offset
);
379 memcpy(map
, data
, size
);
385 * Did field 'x' change between 'old_cso' and 'new_cso'?
387 * (If so, we may want to set some dirty flags.)
389 #define cso_changed(x) (!old_cso || (old_cso->x != new_cso->x))
390 #define cso_changed_memcmp(x) \
391 (!old_cso || memcmp(old_cso->x, new_cso->x, sizeof(old_cso->x)) != 0)
394 flush_before_state_base_change(struct iris_batch
*batch
)
396 /* Flush before emitting STATE_BASE_ADDRESS.
398 * This isn't documented anywhere in the PRM. However, it seems to be
399 * necessary prior to changing the surface state base adress. We've
400 * seen issues in Vulkan where we get GPU hangs when using multi-level
401 * command buffers which clear depth, reset state base address, and then
404 * Normally, in GL, we would trust the kernel to do sufficient stalls
405 * and flushes prior to executing our batch. However, it doesn't seem
406 * as if the kernel's flushing is always sufficient and we don't want to
409 * We make this an end-of-pipe sync instead of a normal flush because we
410 * do not know the current status of the GPU. On Haswell at least,
411 * having a fast-clear operation in flight at the same time as a normal
412 * rendering operation can cause hangs. Since the kernel's flushing is
413 * insufficient, we need to ensure that any rendering operations from
414 * other processes are definitely complete before we try to do our own
415 * rendering. It's a bit of a big hammer but it appears to work.
417 iris_emit_end_of_pipe_sync(batch
,
418 "change STATE_BASE_ADDRESS (flushes)",
419 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
420 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
421 PIPE_CONTROL_DATA_CACHE_FLUSH
);
425 flush_after_state_base_change(struct iris_batch
*batch
)
427 /* After re-setting the surface state base address, we have to do some
428 * cache flusing so that the sampler engine will pick up the new
429 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
430 * Shared Function > 3D Sampler > State > State Caching (page 96):
432 * Coherency with system memory in the state cache, like the texture
433 * cache is handled partially by software. It is expected that the
434 * command stream or shader will issue Cache Flush operation or
435 * Cache_Flush sampler message to ensure that the L1 cache remains
436 * coherent with system memory.
440 * Whenever the value of the Dynamic_State_Base_Addr,
441 * Surface_State_Base_Addr are altered, the L1 state cache must be
442 * invalidated to ensure the new surface or sampler state is fetched
443 * from system memory.
445 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
446 * which, according the PIPE_CONTROL instruction documentation in the
449 * Setting this bit is independent of any other bit in this packet.
450 * This bit controls the invalidation of the L1 and L2 state caches
451 * at the top of the pipe i.e. at the parsing time.
453 * Unfortunately, experimentation seems to indicate that state cache
454 * invalidation through a PIPE_CONTROL does nothing whatsoever in
455 * regards to surface state and binding tables. In stead, it seems that
456 * invalidating the texture cache is what is actually needed.
458 * XXX: As far as we have been able to determine through
459 * experimentation, shows that flush the texture cache appears to be
460 * sufficient. The theory here is that all of the sampling/rendering
461 * units cache the binding table in the texture cache. However, we have
462 * yet to be able to actually confirm this.
464 iris_emit_end_of_pipe_sync(batch
,
465 "change STATE_BASE_ADDRESS (invalidates)",
466 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
467 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
468 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
472 _iris_emit_lri(struct iris_batch
*batch
, uint32_t reg
, uint32_t val
)
474 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
475 lri
.RegisterOffset
= reg
;
479 #define iris_emit_lri(b, r, v) _iris_emit_lri(b, GENX(r##_num), v)
482 _iris_emit_lrr(struct iris_batch
*batch
, uint32_t dst
, uint32_t src
)
484 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
485 lrr
.SourceRegisterAddress
= src
;
486 lrr
.DestinationRegisterAddress
= dst
;
491 emit_pipeline_select(struct iris_batch
*batch
, uint32_t pipeline
)
493 #if GEN_GEN >= 8 && GEN_GEN < 10
494 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
496 * Software must clear the COLOR_CALC_STATE Valid field in
497 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
498 * with Pipeline Select set to GPGPU.
500 * The internal hardware docs recommend the same workaround for Gen9
503 if (pipeline
== GPGPU
)
504 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
508 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
509 * PIPELINE_SELECT [DevBWR+]":
513 * Software must ensure all the write caches are flushed through a
514 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
515 * command to invalidate read only caches prior to programming
516 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode."
518 iris_emit_pipe_control_flush(batch
,
519 "workaround: PIPELINE_SELECT flushes (1/2)",
520 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
521 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
522 PIPE_CONTROL_DATA_CACHE_FLUSH
|
523 PIPE_CONTROL_CS_STALL
);
525 iris_emit_pipe_control_flush(batch
,
526 "workaround: PIPELINE_SELECT flushes (2/2)",
527 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
528 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
529 PIPE_CONTROL_STATE_CACHE_INVALIDATE
|
530 PIPE_CONTROL_INSTRUCTION_INVALIDATE
);
532 iris_emit_cmd(batch
, GENX(PIPELINE_SELECT
), sel
) {
536 sel
.PipelineSelection
= pipeline
;
541 init_glk_barrier_mode(struct iris_batch
*batch
, uint32_t value
)
546 * "This chicken bit works around a hardware issue with barrier
547 * logic encountered when switching between GPGPU and 3D pipelines.
548 * To workaround the issue, this mode bit should be set after a
549 * pipeline is selected."
552 iris_pack_state(GENX(SLICE_COMMON_ECO_CHICKEN1
), ®_val
, reg
) {
553 reg
.GLKBarrierMode
= value
;
554 reg
.GLKBarrierModeMask
= 1;
556 iris_emit_lri(batch
, SLICE_COMMON_ECO_CHICKEN1
, reg_val
);
561 init_state_base_address(struct iris_batch
*batch
)
563 flush_before_state_base_change(batch
);
565 /* We program most base addresses once at context initialization time.
566 * Each base address points at a 4GB memory zone, and never needs to
567 * change. See iris_bufmgr.h for a description of the memory zones.
569 * The one exception is Surface State Base Address, which needs to be
570 * updated occasionally. See iris_binder.c for the details there.
572 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
573 sba
.GeneralStateMOCS
= MOCS_WB
;
574 sba
.StatelessDataPortAccessMOCS
= MOCS_WB
;
575 sba
.DynamicStateMOCS
= MOCS_WB
;
576 sba
.IndirectObjectMOCS
= MOCS_WB
;
577 sba
.InstructionMOCS
= MOCS_WB
;
578 sba
.SurfaceStateMOCS
= MOCS_WB
;
580 sba
.GeneralStateBaseAddressModifyEnable
= true;
581 sba
.DynamicStateBaseAddressModifyEnable
= true;
582 sba
.IndirectObjectBaseAddressModifyEnable
= true;
583 sba
.InstructionBaseAddressModifyEnable
= true;
584 sba
.GeneralStateBufferSizeModifyEnable
= true;
585 sba
.DynamicStateBufferSizeModifyEnable
= true;
587 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
588 sba
.BindlessSurfaceStateMOCS
= MOCS_WB
;
590 sba
.IndirectObjectBufferSizeModifyEnable
= true;
591 sba
.InstructionBuffersizeModifyEnable
= true;
593 sba
.InstructionBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SHADER_START
);
594 sba
.DynamicStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_DYNAMIC_START
);
596 sba
.GeneralStateBufferSize
= 0xfffff;
597 sba
.IndirectObjectBufferSize
= 0xfffff;
598 sba
.InstructionBufferSize
= 0xfffff;
599 sba
.DynamicStateBufferSize
= 0xfffff;
602 flush_after_state_base_change(batch
);
606 iris_emit_l3_config(struct iris_batch
*batch
, const struct gen_l3_config
*cfg
,
607 bool has_slm
, bool wants_dc_cache
)
612 #define L3_ALLOCATION_REG GENX(L3ALLOC)
613 #define L3_ALLOCATION_REG_num GENX(L3ALLOC_num)
615 #define L3_ALLOCATION_REG GENX(L3CNTLREG)
616 #define L3_ALLOCATION_REG_num GENX(L3CNTLREG_num)
619 iris_pack_state(L3_ALLOCATION_REG
, ®_val
, reg
) {
621 reg
.SLMEnable
= has_slm
;
624 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
625 * in L3CNTLREG register. The default setting of the bit is not the
626 * desirable behavior.
628 reg
.ErrorDetectionBehaviorControl
= true;
629 reg
.UseFullWays
= true;
631 reg
.URBAllocation
= cfg
->n
[GEN_L3P_URB
];
632 reg
.ROAllocation
= cfg
->n
[GEN_L3P_RO
];
633 reg
.DCAllocation
= cfg
->n
[GEN_L3P_DC
];
634 reg
.AllAllocation
= cfg
->n
[GEN_L3P_ALL
];
636 _iris_emit_lri(batch
, L3_ALLOCATION_REG_num
, reg_val
);
640 iris_emit_default_l3_config(struct iris_batch
*batch
,
641 const struct gen_device_info
*devinfo
,
644 bool wants_dc_cache
= true;
645 bool has_slm
= compute
;
646 const struct gen_l3_weights w
=
647 gen_get_default_l3_weights(devinfo
, wants_dc_cache
, has_slm
);
648 const struct gen_l3_config
*cfg
= gen_get_l3_config(devinfo
, w
);
649 iris_emit_l3_config(batch
, cfg
, has_slm
, wants_dc_cache
);
652 #if GEN_GEN == 9 || GEN_GEN == 10
654 iris_enable_obj_preemption(struct iris_batch
*batch
, bool enable
)
658 /* A fixed function pipe flush is required before modifying this field */
659 iris_emit_end_of_pipe_sync(batch
, enable
? "enable preemption"
660 : "disable preemption",
661 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
663 /* enable object level preemption */
664 iris_pack_state(GENX(CS_CHICKEN1
), ®_val
, reg
) {
665 reg
.ReplayMode
= enable
;
666 reg
.ReplayModeMask
= true;
668 iris_emit_lri(batch
, CS_CHICKEN1
, reg_val
);
674 iris_upload_slice_hashing_state(struct iris_batch
*batch
)
676 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
677 int subslices_delta
=
678 devinfo
->ppipe_subslices
[0] - devinfo
->ppipe_subslices
[1];
679 if (subslices_delta
== 0)
682 struct iris_context
*ice
= NULL
;
683 ice
= container_of(batch
, ice
, batches
[IRIS_BATCH_RENDER
]);
684 assert(&ice
->batches
[IRIS_BATCH_RENDER
] == batch
);
686 unsigned size
= GENX(SLICE_HASH_TABLE_length
) * 4;
687 uint32_t hash_address
;
688 struct pipe_resource
*tmp
= NULL
;
690 stream_state(batch
, ice
->state
.dynamic_uploader
, &tmp
,
691 size
, 64, &hash_address
);
692 pipe_resource_reference(&tmp
, NULL
);
694 struct GENX(SLICE_HASH_TABLE
) table0
= {
696 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
697 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
698 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
699 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
700 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
701 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
702 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
703 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
704 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
705 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
706 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
707 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
708 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
709 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
710 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
711 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 }
715 struct GENX(SLICE_HASH_TABLE
) table1
= {
717 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
718 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
719 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
720 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
721 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
722 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
723 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
724 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
725 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
726 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
727 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
728 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
729 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
730 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
731 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
732 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 }
736 const struct GENX(SLICE_HASH_TABLE
) *table
=
737 subslices_delta
< 0 ? &table0
: &table1
;
738 GENX(SLICE_HASH_TABLE_pack
)(NULL
, map
, table
);
740 iris_emit_cmd(batch
, GENX(3DSTATE_SLICE_TABLE_STATE_POINTERS
), ptr
) {
741 ptr
.SliceHashStatePointerValid
= true;
742 ptr
.SliceHashTableStatePointer
= hash_address
;
745 iris_emit_cmd(batch
, GENX(3DSTATE_3D_MODE
), mode
) {
746 mode
.SliceHashingTableEnable
= true;
752 * Upload the initial GPU state for a render context.
754 * This sets some invariant state that needs to be programmed a particular
755 * way, but we never actually change.
758 iris_init_render_context(struct iris_screen
*screen
,
759 struct iris_batch
*batch
,
760 struct iris_vtable
*vtbl
,
761 struct pipe_debug_callback
*dbg
)
763 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
766 emit_pipeline_select(batch
, _3D
);
768 iris_emit_default_l3_config(batch
, devinfo
, false);
770 init_state_base_address(batch
);
773 iris_pack_state(GENX(CS_DEBUG_MODE2
), ®_val
, reg
) {
774 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
775 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
777 iris_emit_lri(batch
, CS_DEBUG_MODE2
, reg_val
);
779 iris_pack_state(GENX(INSTPM
), ®_val
, reg
) {
780 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
781 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
783 iris_emit_lri(batch
, INSTPM
, reg_val
);
787 iris_pack_state(GENX(CACHE_MODE_1
), ®_val
, reg
) {
788 reg
.FloatBlendOptimizationEnable
= true;
789 reg
.FloatBlendOptimizationEnableMask
= true;
790 reg
.PartialResolveDisableInVC
= true;
791 reg
.PartialResolveDisableInVCMask
= true;
793 iris_emit_lri(batch
, CACHE_MODE_1
, reg_val
);
795 if (devinfo
->is_geminilake
)
796 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_3D_HULL
);
800 iris_pack_state(GENX(SAMPLER_MODE
), ®_val
, reg
) {
801 reg
.HeaderlessMessageforPreemptableContexts
= 1;
802 reg
.HeaderlessMessageforPreemptableContextsMask
= 1;
804 iris_emit_lri(batch
, SAMPLER_MODE
, reg_val
);
806 /* Bit 1 must be set in HALF_SLICE_CHICKEN7. */
807 iris_pack_state(GENX(HALF_SLICE_CHICKEN7
), ®_val
, reg
) {
808 reg
.EnabledTexelOffsetPrecisionFix
= 1;
809 reg
.EnabledTexelOffsetPrecisionFixMask
= 1;
811 iris_emit_lri(batch
, HALF_SLICE_CHICKEN7
, reg_val
);
813 /* Hardware specification recommends disabling repacking for the
814 * compatibility with decompression mechanism in display controller.
816 if (devinfo
->disable_ccs_repack
) {
817 iris_pack_state(GENX(CACHE_MODE_0
), ®_val
, reg
) {
818 reg
.DisableRepackingforCompression
= true;
819 reg
.DisableRepackingforCompressionMask
= true;
821 iris_emit_lri(batch
, CACHE_MODE_0
, reg_val
);
824 iris_upload_slice_hashing_state(batch
);
827 /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined, so we want to avoid
828 * changing it dynamically. We set it to the maximum size here, and
829 * instead include the render target dimensions in the viewport, so
830 * viewport extents clipping takes care of pruning stray geometry.
832 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
833 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
834 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
837 /* Set the initial MSAA sample positions. */
838 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
839 GEN_SAMPLE_POS_1X(pat
._1xSample
);
840 GEN_SAMPLE_POS_2X(pat
._2xSample
);
841 GEN_SAMPLE_POS_4X(pat
._4xSample
);
842 GEN_SAMPLE_POS_8X(pat
._8xSample
);
844 GEN_SAMPLE_POS_16X(pat
._16xSample
);
848 /* Use the legacy AA line coverage computation. */
849 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
851 /* Disable chromakeying (it's for media) */
852 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
854 /* We want regular rendering, not special HiZ operations. */
855 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
857 /* No polygon stippling offsets are necessary. */
858 /* TODO: may need to set an offset for origin-UL framebuffers */
859 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
861 /* Set a static partitioning of the push constant area. */
862 /* TODO: this may be a bad idea...could starve the push ringbuffers... */
863 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
864 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
865 alloc
._3DCommandSubOpcode
= 18 + i
;
866 alloc
.ConstantBufferOffset
= 6 * i
;
867 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
872 /* Gen11+ is enabled for us by the kernel. */
873 iris_enable_obj_preemption(batch
, true);
878 iris_init_compute_context(struct iris_screen
*screen
,
879 struct iris_batch
*batch
,
880 struct iris_vtable
*vtbl
,
881 struct pipe_debug_callback
*dbg
)
883 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
885 emit_pipeline_select(batch
, GPGPU
);
887 iris_emit_default_l3_config(batch
, devinfo
, true);
889 init_state_base_address(batch
);
892 if (devinfo
->is_geminilake
)
893 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_GPGPU
);
897 struct iris_vertex_buffer_state
{
898 /** The VERTEX_BUFFER_STATE hardware structure. */
899 uint32_t state
[GENX(VERTEX_BUFFER_STATE_length
)];
901 /** The resource to source vertex data from. */
902 struct pipe_resource
*resource
;
905 struct iris_depth_buffer_state
{
906 /* Depth/HiZ/Stencil related hardware packets. */
907 uint32_t packets
[GENX(3DSTATE_DEPTH_BUFFER_length
) +
908 GENX(3DSTATE_STENCIL_BUFFER_length
) +
909 GENX(3DSTATE_HIER_DEPTH_BUFFER_length
) +
910 GENX(3DSTATE_CLEAR_PARAMS_length
)];
914 * Generation-specific context state (ice->state.genx->...).
916 * Most state can go in iris_context directly, but these encode hardware
917 * packets which vary by generation.
919 struct iris_genx_state
{
920 struct iris_vertex_buffer_state vertex_buffers
[33];
921 uint32_t last_index_buffer
[GENX(3DSTATE_INDEX_BUFFER_length
)];
923 struct iris_depth_buffer_state depth_buffer
;
925 uint32_t so_buffers
[4 * GENX(3DSTATE_SO_BUFFER_length
)];
928 /* Is object level preemption enabled? */
929 bool object_preemption
;
934 struct brw_image_param image_param
[PIPE_MAX_SHADER_IMAGES
];
936 } shaders
[MESA_SHADER_STAGES
];
940 * The pipe->set_blend_color() driver hook.
942 * This corresponds to our COLOR_CALC_STATE.
945 iris_set_blend_color(struct pipe_context
*ctx
,
946 const struct pipe_blend_color
*state
)
948 struct iris_context
*ice
= (struct iris_context
*) ctx
;
950 /* Our COLOR_CALC_STATE is exactly pipe_blend_color, so just memcpy */
951 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
952 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
956 * Gallium CSO for blend state (see pipe_blend_state).
958 struct iris_blend_state
{
959 /** Partial 3DSTATE_PS_BLEND */
960 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
962 /** Partial BLEND_STATE */
963 uint32_t blend_state
[GENX(BLEND_STATE_length
) +
964 BRW_MAX_DRAW_BUFFERS
* GENX(BLEND_STATE_ENTRY_length
)];
966 bool alpha_to_coverage
; /* for shader key */
968 /** Bitfield of whether blending is enabled for RT[i] - for aux resolves */
969 uint8_t blend_enables
;
971 /** Bitfield of whether color writes are enabled for RT[i] */
972 uint8_t color_write_enables
;
974 /** Does RT[0] use dual color blending? */
975 bool dual_color_blending
;
978 static enum pipe_blendfactor
979 fix_blendfactor(enum pipe_blendfactor f
, bool alpha_to_one
)
982 if (f
== PIPE_BLENDFACTOR_SRC1_ALPHA
)
983 return PIPE_BLENDFACTOR_ONE
;
985 if (f
== PIPE_BLENDFACTOR_INV_SRC1_ALPHA
)
986 return PIPE_BLENDFACTOR_ZERO
;
993 * The pipe->create_blend_state() driver hook.
995 * Translates a pipe_blend_state into iris_blend_state.
998 iris_create_blend_state(struct pipe_context
*ctx
,
999 const struct pipe_blend_state
*state
)
1001 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
1002 uint32_t *blend_entry
= cso
->blend_state
+ GENX(BLEND_STATE_length
);
1004 cso
->blend_enables
= 0;
1005 cso
->color_write_enables
= 0;
1006 STATIC_ASSERT(BRW_MAX_DRAW_BUFFERS
<= 8);
1008 cso
->alpha_to_coverage
= state
->alpha_to_coverage
;
1010 bool indep_alpha_blend
= false;
1012 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
1013 const struct pipe_rt_blend_state
*rt
=
1014 &state
->rt
[state
->independent_blend_enable
? i
: 0];
1016 enum pipe_blendfactor src_rgb
=
1017 fix_blendfactor(rt
->rgb_src_factor
, state
->alpha_to_one
);
1018 enum pipe_blendfactor src_alpha
=
1019 fix_blendfactor(rt
->alpha_src_factor
, state
->alpha_to_one
);
1020 enum pipe_blendfactor dst_rgb
=
1021 fix_blendfactor(rt
->rgb_dst_factor
, state
->alpha_to_one
);
1022 enum pipe_blendfactor dst_alpha
=
1023 fix_blendfactor(rt
->alpha_dst_factor
, state
->alpha_to_one
);
1025 if (rt
->rgb_func
!= rt
->alpha_func
||
1026 src_rgb
!= src_alpha
|| dst_rgb
!= dst_alpha
)
1027 indep_alpha_blend
= true;
1029 if (rt
->blend_enable
)
1030 cso
->blend_enables
|= 1u << i
;
1033 cso
->color_write_enables
|= 1u << i
;
1035 iris_pack_state(GENX(BLEND_STATE_ENTRY
), blend_entry
, be
) {
1036 be
.LogicOpEnable
= state
->logicop_enable
;
1037 be
.LogicOpFunction
= state
->logicop_func
;
1039 be
.PreBlendSourceOnlyClampEnable
= false;
1040 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
1041 be
.PreBlendColorClampEnable
= true;
1042 be
.PostBlendColorClampEnable
= true;
1044 be
.ColorBufferBlendEnable
= rt
->blend_enable
;
1046 be
.ColorBlendFunction
= rt
->rgb_func
;
1047 be
.AlphaBlendFunction
= rt
->alpha_func
;
1048 be
.SourceBlendFactor
= src_rgb
;
1049 be
.SourceAlphaBlendFactor
= src_alpha
;
1050 be
.DestinationBlendFactor
= dst_rgb
;
1051 be
.DestinationAlphaBlendFactor
= dst_alpha
;
1053 be
.WriteDisableRed
= !(rt
->colormask
& PIPE_MASK_R
);
1054 be
.WriteDisableGreen
= !(rt
->colormask
& PIPE_MASK_G
);
1055 be
.WriteDisableBlue
= !(rt
->colormask
& PIPE_MASK_B
);
1056 be
.WriteDisableAlpha
= !(rt
->colormask
& PIPE_MASK_A
);
1058 blend_entry
+= GENX(BLEND_STATE_ENTRY_length
);
1061 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
1062 /* pb.HasWriteableRT is filled in at draw time.
1063 * pb.AlphaTestEnable is filled in at draw time.
1065 * pb.ColorBufferBlendEnable is filled in at draw time so we can avoid
1066 * setting it when dual color blending without an appropriate shader.
1069 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
1070 pb
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
1072 pb
.SourceBlendFactor
=
1073 fix_blendfactor(state
->rt
[0].rgb_src_factor
, state
->alpha_to_one
);
1074 pb
.SourceAlphaBlendFactor
=
1075 fix_blendfactor(state
->rt
[0].alpha_src_factor
, state
->alpha_to_one
);
1076 pb
.DestinationBlendFactor
=
1077 fix_blendfactor(state
->rt
[0].rgb_dst_factor
, state
->alpha_to_one
);
1078 pb
.DestinationAlphaBlendFactor
=
1079 fix_blendfactor(state
->rt
[0].alpha_dst_factor
, state
->alpha_to_one
);
1082 iris_pack_state(GENX(BLEND_STATE
), cso
->blend_state
, bs
) {
1083 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
1084 bs
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
1085 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
1086 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
1087 bs
.ColorDitherEnable
= state
->dither
;
1088 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
1091 cso
->dual_color_blending
= util_blend_state_is_dual(state
, 0);
1097 * The pipe->bind_blend_state() driver hook.
1099 * Bind a blending CSO and flag related dirty bits.
1102 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
1104 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1105 struct iris_blend_state
*cso
= state
;
1107 ice
->state
.cso_blend
= cso
;
1108 ice
->state
.blend_enables
= cso
? cso
->blend_enables
: 0;
1110 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
1111 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1112 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
1113 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_BLEND
];
1117 * Return true if the FS writes to any color outputs which are not disabled
1118 * via color masking.
1121 has_writeable_rt(const struct iris_blend_state
*cso_blend
,
1122 const struct shader_info
*fs_info
)
1127 unsigned rt_outputs
= fs_info
->outputs_written
>> FRAG_RESULT_DATA0
;
1129 if (fs_info
->outputs_written
& BITFIELD64_BIT(FRAG_RESULT_COLOR
))
1130 rt_outputs
= (1 << BRW_MAX_DRAW_BUFFERS
) - 1;
1132 return cso_blend
->color_write_enables
& rt_outputs
;
1136 * Gallium CSO for depth, stencil, and alpha testing state.
1138 struct iris_depth_stencil_alpha_state
{
1139 /** Partial 3DSTATE_WM_DEPTH_STENCIL. */
1140 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
1142 /** Outbound to BLEND_STATE, 3DSTATE_PS_BLEND, COLOR_CALC_STATE. */
1143 struct pipe_alpha_state alpha
;
1145 /** Outbound to resolve and cache set tracking. */
1146 bool depth_writes_enabled
;
1147 bool stencil_writes_enabled
;
1151 * The pipe->create_depth_stencil_alpha_state() driver hook.
1153 * We encode most of 3DSTATE_WM_DEPTH_STENCIL, and just save off the alpha
1154 * testing state since we need pieces of it in a variety of places.
1157 iris_create_zsa_state(struct pipe_context
*ctx
,
1158 const struct pipe_depth_stencil_alpha_state
*state
)
1160 struct iris_depth_stencil_alpha_state
*cso
=
1161 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
1163 bool two_sided_stencil
= state
->stencil
[1].enabled
;
1165 cso
->alpha
= state
->alpha
;
1166 cso
->depth_writes_enabled
= state
->depth
.writemask
;
1167 cso
->stencil_writes_enabled
=
1168 state
->stencil
[0].writemask
!= 0 ||
1169 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
1171 /* The state tracker needs to optimize away EQUAL writes for us. */
1172 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
1174 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
1175 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
1176 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
1177 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
1178 wmds
.StencilTestFunction
=
1179 translate_compare_func(state
->stencil
[0].func
);
1180 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
1181 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
1182 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
1183 wmds
.BackfaceStencilTestFunction
=
1184 translate_compare_func(state
->stencil
[1].func
);
1185 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
1186 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
1187 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
1188 wmds
.StencilBufferWriteEnable
=
1189 state
->stencil
[0].writemask
!= 0 ||
1190 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
1191 wmds
.DepthTestEnable
= state
->depth
.enabled
;
1192 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
1193 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
1194 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
1195 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
1196 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
1197 /* wmds.[Backface]StencilReferenceValue are merged later */
1204 * The pipe->bind_depth_stencil_alpha_state() driver hook.
1206 * Bind a depth/stencil/alpha CSO and flag related dirty bits.
1209 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
1211 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1212 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
1213 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
1216 if (cso_changed(alpha
.ref_value
))
1217 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
1219 if (cso_changed(alpha
.enabled
))
1220 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
| IRIS_DIRTY_BLEND_STATE
;
1222 if (cso_changed(alpha
.func
))
1223 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1225 if (cso_changed(depth_writes_enabled
))
1226 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
1228 ice
->state
.depth_writes_enabled
= new_cso
->depth_writes_enabled
;
1229 ice
->state
.stencil_writes_enabled
= new_cso
->stencil_writes_enabled
;
1232 ice
->state
.cso_zsa
= new_cso
;
1233 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1234 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1235 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_DEPTH_STENCIL_ALPHA
];
1239 * Gallium CSO for rasterizer state.
1241 struct iris_rasterizer_state
{
1242 uint32_t sf
[GENX(3DSTATE_SF_length
)];
1243 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
1244 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
1245 uint32_t wm
[GENX(3DSTATE_WM_length
)];
1246 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
1248 uint8_t num_clip_plane_consts
;
1249 bool clip_halfz
; /* for CC_VIEWPORT */
1250 bool depth_clip_near
; /* for CC_VIEWPORT */
1251 bool depth_clip_far
; /* for CC_VIEWPORT */
1252 bool flatshade
; /* for shader state */
1253 bool flatshade_first
; /* for stream output */
1254 bool clamp_fragment_color
; /* for shader state */
1255 bool light_twoside
; /* for shader state */
1256 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT and 3DSTATE_CLIP */
1257 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
1258 bool line_stipple_enable
;
1259 bool poly_stipple_enable
;
1261 bool force_persample_interp
;
1262 bool conservative_rasterization
;
1263 bool fill_mode_point_or_line
;
1264 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
1265 uint16_t sprite_coord_enable
;
1269 get_line_width(const struct pipe_rasterizer_state
*state
)
1271 float line_width
= state
->line_width
;
1273 /* From the OpenGL 4.4 spec:
1275 * "The actual width of non-antialiased lines is determined by rounding
1276 * the supplied width to the nearest integer, then clamping it to the
1277 * implementation-dependent maximum non-antialiased line width."
1279 if (!state
->multisample
&& !state
->line_smooth
)
1280 line_width
= roundf(state
->line_width
);
1282 if (!state
->multisample
&& state
->line_smooth
&& line_width
< 1.5f
) {
1283 /* For 1 pixel line thickness or less, the general anti-aliasing
1284 * algorithm gives up, and a garbage line is generated. Setting a
1285 * Line Width of 0.0 specifies the rasterization of the "thinnest"
1286 * (one-pixel-wide), non-antialiased lines.
1288 * Lines rendered with zero Line Width are rasterized using the
1289 * "Grid Intersection Quantization" rules as specified by the
1290 * "Zero-Width (Cosmetic) Line Rasterization" section of the docs.
1299 * The pipe->create_rasterizer_state() driver hook.
1302 iris_create_rasterizer_state(struct pipe_context
*ctx
,
1303 const struct pipe_rasterizer_state
*state
)
1305 struct iris_rasterizer_state
*cso
=
1306 malloc(sizeof(struct iris_rasterizer_state
));
1308 cso
->multisample
= state
->multisample
;
1309 cso
->force_persample_interp
= state
->force_persample_interp
;
1310 cso
->clip_halfz
= state
->clip_halfz
;
1311 cso
->depth_clip_near
= state
->depth_clip_near
;
1312 cso
->depth_clip_far
= state
->depth_clip_far
;
1313 cso
->flatshade
= state
->flatshade
;
1314 cso
->flatshade_first
= state
->flatshade_first
;
1315 cso
->clamp_fragment_color
= state
->clamp_fragment_color
;
1316 cso
->light_twoside
= state
->light_twoside
;
1317 cso
->rasterizer_discard
= state
->rasterizer_discard
;
1318 cso
->half_pixel_center
= state
->half_pixel_center
;
1319 cso
->sprite_coord_mode
= state
->sprite_coord_mode
;
1320 cso
->sprite_coord_enable
= state
->sprite_coord_enable
;
1321 cso
->line_stipple_enable
= state
->line_stipple_enable
;
1322 cso
->poly_stipple_enable
= state
->poly_stipple_enable
;
1323 cso
->conservative_rasterization
=
1324 state
->conservative_raster_mode
== PIPE_CONSERVATIVE_RASTER_POST_SNAP
;
1326 cso
->fill_mode_point_or_line
=
1327 state
->fill_front
== PIPE_POLYGON_MODE_LINE
||
1328 state
->fill_front
== PIPE_POLYGON_MODE_POINT
||
1329 state
->fill_back
== PIPE_POLYGON_MODE_LINE
||
1330 state
->fill_back
== PIPE_POLYGON_MODE_POINT
;
1332 if (state
->clip_plane_enable
!= 0)
1333 cso
->num_clip_plane_consts
= util_logbase2(state
->clip_plane_enable
) + 1;
1335 cso
->num_clip_plane_consts
= 0;
1337 float line_width
= get_line_width(state
);
1339 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
1340 sf
.StatisticsEnable
= true;
1341 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1342 sf
.LineEndCapAntialiasingRegionWidth
=
1343 state
->line_smooth
? _10pixels
: _05pixels
;
1344 sf
.LastPixelEnable
= state
->line_last_pixel
;
1345 sf
.LineWidth
= line_width
;
1346 sf
.SmoothPointEnable
= (state
->point_smooth
|| state
->multisample
) &&
1347 !state
->point_quad_rasterization
;
1348 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
1349 sf
.PointWidth
= state
->point_size
;
1351 if (state
->flatshade_first
) {
1352 sf
.TriangleFanProvokingVertexSelect
= 1;
1354 sf
.TriangleStripListProvokingVertexSelect
= 2;
1355 sf
.TriangleFanProvokingVertexSelect
= 2;
1356 sf
.LineStripListProvokingVertexSelect
= 1;
1360 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
1361 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
1362 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
1363 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
1364 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
1365 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
1366 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
1367 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
1368 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
1369 rr
.GlobalDepthOffsetConstant
= state
->offset_units
* 2;
1370 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
1371 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
1372 rr
.SmoothPointEnable
= state
->point_smooth
;
1373 rr
.AntialiasingEnable
= state
->line_smooth
;
1374 rr
.ScissorRectangleEnable
= state
->scissor
;
1376 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
1377 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
1378 rr
.ConservativeRasterizationEnable
=
1379 cso
->conservative_rasterization
;
1381 rr
.ViewportZClipTestEnable
= (state
->depth_clip_near
|| state
->depth_clip_far
);
1385 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
1386 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
1387 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
1389 cl
.EarlyCullEnable
= true;
1390 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
1391 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1392 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
1393 cl
.GuardbandClipTestEnable
= true;
1394 cl
.ClipEnable
= true;
1395 cl
.MinimumPointWidth
= 0.125;
1396 cl
.MaximumPointWidth
= 255.875;
1398 if (state
->flatshade_first
) {
1399 cl
.TriangleFanProvokingVertexSelect
= 1;
1401 cl
.TriangleStripListProvokingVertexSelect
= 2;
1402 cl
.TriangleFanProvokingVertexSelect
= 2;
1403 cl
.LineStripListProvokingVertexSelect
= 1;
1407 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
1408 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
1409 * filled in at draw time from the FS program.
1411 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1412 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1413 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1414 wm
.LineStippleEnable
= state
->line_stipple_enable
;
1415 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
1418 /* Remap from 0..255 back to 1..256 */
1419 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
1421 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
1422 if (state
->line_stipple_enable
) {
1423 line
.LineStipplePattern
= state
->line_stipple_pattern
;
1424 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
1425 line
.LineStippleRepeatCount
= line_stipple_factor
;
1433 * The pipe->bind_rasterizer_state() driver hook.
1435 * Bind a rasterizer CSO and flag related dirty bits.
1438 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
1440 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1441 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
1442 struct iris_rasterizer_state
*new_cso
= state
;
1445 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
1446 if (cso_changed_memcmp(line_stipple
))
1447 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
1449 if (cso_changed(half_pixel_center
))
1450 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1452 if (cso_changed(line_stipple_enable
) || cso_changed(poly_stipple_enable
))
1453 ice
->state
.dirty
|= IRIS_DIRTY_WM
;
1455 if (cso_changed(rasterizer_discard
))
1456 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
| IRIS_DIRTY_CLIP
;
1458 if (cso_changed(flatshade_first
))
1459 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
1461 if (cso_changed(depth_clip_near
) || cso_changed(depth_clip_far
) ||
1462 cso_changed(clip_halfz
))
1463 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1465 if (cso_changed(sprite_coord_enable
) ||
1466 cso_changed(sprite_coord_mode
) ||
1467 cso_changed(light_twoside
))
1468 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1470 if (cso_changed(conservative_rasterization
))
1471 ice
->state
.dirty
|= IRIS_DIRTY_FS
;
1474 ice
->state
.cso_rast
= new_cso
;
1475 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
1476 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1477 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_RASTERIZER
];
1481 * Return true if the given wrap mode requires the border color to exist.
1483 * (We can skip uploading it if the sampler isn't going to use it.)
1486 wrap_mode_needs_border_color(unsigned wrap_mode
)
1488 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
1492 * Gallium CSO for sampler state.
1494 struct iris_sampler_state
{
1495 union pipe_color_union border_color
;
1496 bool needs_border_color
;
1498 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
1502 * The pipe->create_sampler_state() driver hook.
1504 * We fill out SAMPLER_STATE (except for the border color pointer), and
1505 * store that on the CPU. It doesn't make sense to upload it to a GPU
1506 * buffer object yet, because 3DSTATE_SAMPLER_STATE_POINTERS requires
1507 * all bound sampler states to be in contiguous memor.
1510 iris_create_sampler_state(struct pipe_context
*ctx
,
1511 const struct pipe_sampler_state
*state
)
1513 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
1518 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
1519 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
1521 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
1522 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
1523 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
1525 memcpy(&cso
->border_color
, &state
->border_color
, sizeof(cso
->border_color
));
1527 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
1528 wrap_mode_needs_border_color(wrap_t
) ||
1529 wrap_mode_needs_border_color(wrap_r
);
1531 float min_lod
= state
->min_lod
;
1532 unsigned mag_img_filter
= state
->mag_img_filter
;
1534 // XXX: explain this code ported from ilo...I don't get it at all...
1535 if (state
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
&&
1536 state
->min_lod
> 0.0f
) {
1538 mag_img_filter
= state
->min_img_filter
;
1541 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
1542 samp
.TCXAddressControlMode
= wrap_s
;
1543 samp
.TCYAddressControlMode
= wrap_t
;
1544 samp
.TCZAddressControlMode
= wrap_r
;
1545 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
1546 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
1547 samp
.MinModeFilter
= state
->min_img_filter
;
1548 samp
.MagModeFilter
= mag_img_filter
;
1549 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
1550 samp
.MaximumAnisotropy
= RATIO21
;
1552 if (state
->max_anisotropy
>= 2) {
1553 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
1554 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
1555 samp
.AnisotropicAlgorithm
= EWAApproximation
;
1558 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
1559 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
1561 samp
.MaximumAnisotropy
=
1562 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
1565 /* Set address rounding bits if not using nearest filtering. */
1566 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1567 samp
.UAddressMinFilterRoundingEnable
= true;
1568 samp
.VAddressMinFilterRoundingEnable
= true;
1569 samp
.RAddressMinFilterRoundingEnable
= true;
1572 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1573 samp
.UAddressMagFilterRoundingEnable
= true;
1574 samp
.VAddressMagFilterRoundingEnable
= true;
1575 samp
.RAddressMagFilterRoundingEnable
= true;
1578 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
1579 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
1581 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
1583 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
1584 samp
.MinLOD
= CLAMP(min_lod
, 0, hw_max_lod
);
1585 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
1586 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
1588 /* .BorderColorPointer is filled in by iris_bind_sampler_states. */
1595 * The pipe->bind_sampler_states() driver hook.
1598 iris_bind_sampler_states(struct pipe_context
*ctx
,
1599 enum pipe_shader_type p_stage
,
1600 unsigned start
, unsigned count
,
1603 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1604 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1605 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1607 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
1611 for (int i
= 0; i
< count
; i
++) {
1612 if (shs
->samplers
[start
+ i
] != states
[i
]) {
1613 shs
->samplers
[start
+ i
] = states
[i
];
1619 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
1623 * Upload the sampler states into a contiguous area of GPU memory, for
1624 * for 3DSTATE_SAMPLER_STATE_POINTERS_*.
1626 * Also fill out the border color state pointers.
1629 iris_upload_sampler_states(struct iris_context
*ice
, gl_shader_stage stage
)
1631 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1632 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
1634 /* We assume the state tracker will call pipe->bind_sampler_states()
1635 * if the program's number of textures changes.
1637 unsigned count
= info
? util_last_bit(info
->textures_used
) : 0;
1642 /* Assemble the SAMPLER_STATEs into a contiguous table that lives
1643 * in the dynamic state memory zone, so we can point to it via the
1644 * 3DSTATE_SAMPLER_STATE_POINTERS_* commands.
1646 unsigned size
= count
* 4 * GENX(SAMPLER_STATE_length
);
1648 upload_state(ice
->state
.dynamic_uploader
, &shs
->sampler_table
, size
, 32);
1652 struct pipe_resource
*res
= shs
->sampler_table
.res
;
1653 shs
->sampler_table
.offset
+=
1654 iris_bo_offset_from_base_address(iris_resource_bo(res
));
1656 iris_record_state_size(ice
->state
.sizes
, shs
->sampler_table
.offset
, size
);
1658 /* Make sure all land in the same BO */
1659 iris_border_color_pool_reserve(ice
, IRIS_MAX_TEXTURE_SAMPLERS
);
1661 ice
->state
.need_border_colors
&= ~(1 << stage
);
1663 for (int i
= 0; i
< count
; i
++) {
1664 struct iris_sampler_state
*state
= shs
->samplers
[i
];
1665 struct iris_sampler_view
*tex
= shs
->textures
[i
];
1668 memset(map
, 0, 4 * GENX(SAMPLER_STATE_length
));
1669 } else if (!state
->needs_border_color
) {
1670 memcpy(map
, state
->sampler_state
, 4 * GENX(SAMPLER_STATE_length
));
1672 ice
->state
.need_border_colors
|= 1 << stage
;
1674 /* We may need to swizzle the border color for format faking.
1675 * A/LA formats are faked as R/RG with 000R or R00G swizzles.
1676 * This means we need to move the border color's A channel into
1677 * the R or G channels so that those read swizzles will move it
1680 union pipe_color_union
*color
= &state
->border_color
;
1681 union pipe_color_union tmp
;
1683 enum pipe_format internal_format
= tex
->res
->internal_format
;
1685 if (util_format_is_alpha(internal_format
)) {
1686 unsigned char swz
[4] = {
1687 PIPE_SWIZZLE_W
, PIPE_SWIZZLE_0
,
1688 PIPE_SWIZZLE_0
, PIPE_SWIZZLE_0
1690 util_format_apply_color_swizzle(&tmp
, color
, swz
, true);
1692 } else if (util_format_is_luminance_alpha(internal_format
) &&
1693 internal_format
!= PIPE_FORMAT_L8A8_SRGB
) {
1694 unsigned char swz
[4] = {
1695 PIPE_SWIZZLE_X
, PIPE_SWIZZLE_W
,
1696 PIPE_SWIZZLE_0
, PIPE_SWIZZLE_0
1698 util_format_apply_color_swizzle(&tmp
, color
, swz
, true);
1703 /* Stream out the border color and merge the pointer. */
1704 uint32_t offset
= iris_upload_border_color(ice
, color
);
1706 uint32_t dynamic
[GENX(SAMPLER_STATE_length
)];
1707 iris_pack_state(GENX(SAMPLER_STATE
), dynamic
, dyns
) {
1708 dyns
.BorderColorPointer
= offset
;
1711 for (uint32_t j
= 0; j
< GENX(SAMPLER_STATE_length
); j
++)
1712 map
[j
] = state
->sampler_state
[j
] | dynamic
[j
];
1715 map
+= GENX(SAMPLER_STATE_length
);
1719 static enum isl_channel_select
1720 fmt_swizzle(const struct iris_format_info
*fmt
, enum pipe_swizzle swz
)
1723 case PIPE_SWIZZLE_X
: return fmt
->swizzle
.r
;
1724 case PIPE_SWIZZLE_Y
: return fmt
->swizzle
.g
;
1725 case PIPE_SWIZZLE_Z
: return fmt
->swizzle
.b
;
1726 case PIPE_SWIZZLE_W
: return fmt
->swizzle
.a
;
1727 case PIPE_SWIZZLE_1
: return SCS_ONE
;
1728 case PIPE_SWIZZLE_0
: return SCS_ZERO
;
1729 default: unreachable("invalid swizzle");
1734 fill_buffer_surface_state(struct isl_device
*isl_dev
,
1735 struct iris_resource
*res
,
1737 enum isl_format format
,
1738 struct isl_swizzle swizzle
,
1742 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
1743 const unsigned cpp
= format
== ISL_FORMAT_RAW
? 1 : fmtl
->bpb
/ 8;
1745 /* The ARB_texture_buffer_specification says:
1747 * "The number of texels in the buffer texture's texel array is given by
1749 * floor(<buffer_size> / (<components> * sizeof(<base_type>)),
1751 * where <buffer_size> is the size of the buffer object, in basic
1752 * machine units and <components> and <base_type> are the element count
1753 * and base data type for elements, as specified in Table X.1. The
1754 * number of texels in the texel array is then clamped to the
1755 * implementation-dependent limit MAX_TEXTURE_BUFFER_SIZE_ARB."
1757 * We need to clamp the size in bytes to MAX_TEXTURE_BUFFER_SIZE * stride,
1758 * so that when ISL divides by stride to obtain the number of texels, that
1759 * texel count is clamped to MAX_TEXTURE_BUFFER_SIZE.
1761 unsigned final_size
=
1762 MIN3(size
, res
->bo
->size
- res
->offset
- offset
,
1763 IRIS_MAX_TEXTURE_BUFFER_SIZE
* cpp
);
1765 isl_buffer_fill_state(isl_dev
, map
,
1766 .address
= res
->bo
->gtt_offset
+ res
->offset
+ offset
,
1767 .size_B
= final_size
,
1771 .mocs
= mocs(res
->bo
));
1774 #define SURFACE_STATE_ALIGNMENT 64
1777 * Allocate several contiguous SURFACE_STATE structures, one for each
1778 * supported auxiliary surface mode.
1781 alloc_surface_states(struct u_upload_mgr
*mgr
,
1782 struct iris_state_ref
*ref
,
1783 unsigned aux_usages
)
1785 const unsigned surf_size
= 4 * GENX(RENDER_SURFACE_STATE_length
);
1787 /* If this changes, update this to explicitly align pointers */
1788 STATIC_ASSERT(surf_size
== SURFACE_STATE_ALIGNMENT
);
1790 assert(aux_usages
!= 0);
1793 upload_state(mgr
, ref
, util_bitcount(aux_usages
) * surf_size
,
1794 SURFACE_STATE_ALIGNMENT
);
1796 ref
->offset
+= iris_bo_offset_from_base_address(iris_resource_bo(ref
->res
));
1803 * Return an ISL surface for use with non-coherent render target reads.
1805 * In a few complex cases, we can't use the SURFACE_STATE for normal render
1806 * target writes. We need to make a separate one for sampling which refers
1807 * to the single slice of the texture being read.
1810 get_rt_read_isl_surf(const struct gen_device_info
*devinfo
,
1811 struct iris_resource
*res
,
1812 enum pipe_texture_target target
,
1813 struct isl_view
*view
,
1814 uint32_t *tile_x_sa
,
1815 uint32_t *tile_y_sa
,
1816 struct isl_surf
*surf
)
1821 const enum isl_dim_layout dim_layout
=
1822 iris_get_isl_dim_layout(devinfo
, res
->surf
.tiling
, target
);
1824 surf
->dim
= target_to_isl_surf_dim(target
);
1826 if (surf
->dim_layout
== dim_layout
)
1829 /* The layout of the specified texture target is not compatible with the
1830 * actual layout of the miptree structure in memory -- You're entering
1831 * dangerous territory, this can only possibly work if you only intended
1832 * to access a single level and slice of the texture, and the hardware
1833 * supports the tile offset feature in order to allow non-tile-aligned
1834 * base offsets, since we'll have to point the hardware to the first
1835 * texel of the level instead of relying on the usual base level/layer
1838 assert(view
->levels
== 1 && view
->array_len
== 1);
1839 assert(*tile_x_sa
== 0 && *tile_y_sa
== 0);
1841 res
->offset
+= iris_resource_get_tile_offsets(res
, view
->base_level
,
1842 view
->base_array_layer
,
1843 tile_x_sa
, tile_y_sa
);
1844 const unsigned l
= view
->base_level
;
1846 surf
->logical_level0_px
.width
= minify(surf
->logical_level0_px
.width
, l
);
1847 surf
->logical_level0_px
.height
= surf
->dim
<= ISL_SURF_DIM_1D
? 1 :
1848 minify(surf
->logical_level0_px
.height
, l
);
1849 surf
->logical_level0_px
.depth
= surf
->dim
<= ISL_SURF_DIM_2D
? 1 :
1850 minify(surf
->logical_level0_px
.depth
, l
);
1852 surf
->logical_level0_px
.array_len
= 1;
1854 surf
->dim_layout
= dim_layout
;
1856 view
->base_level
= 0;
1857 view
->base_array_layer
= 0;
1862 fill_surface_state(struct isl_device
*isl_dev
,
1864 struct iris_resource
*res
,
1865 struct isl_surf
*surf
,
1866 struct isl_view
*view
,
1871 struct isl_surf_fill_state_info f
= {
1874 .mocs
= mocs(res
->bo
),
1875 .address
= res
->bo
->gtt_offset
+ res
->offset
,
1876 .x_offset_sa
= tile_x_sa
,
1877 .y_offset_sa
= tile_y_sa
,
1880 assert(!iris_resource_unfinished_aux_import(res
));
1882 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
1883 f
.aux_surf
= &res
->aux
.surf
;
1884 f
.aux_usage
= aux_usage
;
1885 f
.aux_address
= res
->aux
.bo
->gtt_offset
+ res
->aux
.offset
;
1887 struct iris_bo
*clear_bo
= NULL
;
1888 uint64_t clear_offset
= 0;
1890 iris_resource_get_clear_color(res
, &clear_bo
, &clear_offset
);
1892 f
.clear_address
= clear_bo
->gtt_offset
+ clear_offset
;
1893 f
.use_clear_address
= isl_dev
->info
->gen
> 9;
1897 isl_surf_fill_state_s(isl_dev
, map
, &f
);
1901 * The pipe->create_sampler_view() driver hook.
1903 static struct pipe_sampler_view
*
1904 iris_create_sampler_view(struct pipe_context
*ctx
,
1905 struct pipe_resource
*tex
,
1906 const struct pipe_sampler_view
*tmpl
)
1908 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1909 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1910 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1911 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
1916 /* initialize base object */
1918 isv
->base
.context
= ctx
;
1919 isv
->base
.texture
= NULL
;
1920 pipe_reference_init(&isv
->base
.reference
, 1);
1921 pipe_resource_reference(&isv
->base
.texture
, tex
);
1923 if (util_format_is_depth_or_stencil(tmpl
->format
)) {
1924 struct iris_resource
*zres
, *sres
;
1925 const struct util_format_description
*desc
=
1926 util_format_description(tmpl
->format
);
1928 iris_get_depth_stencil_resources(tex
, &zres
, &sres
);
1930 tex
= util_format_has_depth(desc
) ? &zres
->base
: &sres
->base
;
1933 isv
->res
= (struct iris_resource
*) tex
;
1935 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
1936 &isv
->surface_state
,
1937 isv
->res
->aux
.sampler_usages
);
1941 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
1943 if (isv
->base
.target
== PIPE_TEXTURE_CUBE
||
1944 isv
->base
.target
== PIPE_TEXTURE_CUBE_ARRAY
)
1945 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
1947 const struct iris_format_info fmt
=
1948 iris_format_for_usage(devinfo
, tmpl
->format
, usage
);
1950 isv
->clear_color
= isv
->res
->aux
.clear_color
;
1952 isv
->view
= (struct isl_view
) {
1954 .swizzle
= (struct isl_swizzle
) {
1955 .r
= fmt_swizzle(&fmt
, tmpl
->swizzle_r
),
1956 .g
= fmt_swizzle(&fmt
, tmpl
->swizzle_g
),
1957 .b
= fmt_swizzle(&fmt
, tmpl
->swizzle_b
),
1958 .a
= fmt_swizzle(&fmt
, tmpl
->swizzle_a
),
1963 /* Fill out SURFACE_STATE for this view. */
1964 if (tmpl
->target
!= PIPE_BUFFER
) {
1965 isv
->view
.base_level
= tmpl
->u
.tex
.first_level
;
1966 isv
->view
.levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1;
1967 // XXX: do I need to port f9fd0cf4790cb2a530e75d1a2206dbb9d8af7cb2?
1968 isv
->view
.base_array_layer
= tmpl
->u
.tex
.first_layer
;
1969 isv
->view
.array_len
=
1970 tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1;
1972 if (iris_resource_unfinished_aux_import(isv
->res
))
1973 iris_resource_finish_aux_import(&screen
->base
, isv
->res
);
1975 unsigned aux_modes
= isv
->res
->aux
.sampler_usages
;
1977 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
1979 /* If we have a multisampled depth buffer, do not create a sampler
1980 * surface state with HiZ.
1982 fill_surface_state(&screen
->isl_dev
, map
, isv
->res
, &isv
->res
->surf
,
1983 &isv
->view
, aux_usage
, 0, 0);
1985 map
+= SURFACE_STATE_ALIGNMENT
;
1988 fill_buffer_surface_state(&screen
->isl_dev
, isv
->res
, map
,
1989 isv
->view
.format
, isv
->view
.swizzle
,
1990 tmpl
->u
.buf
.offset
, tmpl
->u
.buf
.size
);
1997 iris_sampler_view_destroy(struct pipe_context
*ctx
,
1998 struct pipe_sampler_view
*state
)
2000 struct iris_sampler_view
*isv
= (void *) state
;
2001 pipe_resource_reference(&state
->texture
, NULL
);
2002 pipe_resource_reference(&isv
->surface_state
.res
, NULL
);
2007 * The pipe->create_surface() driver hook.
2009 * In Gallium nomenclature, "surfaces" are a view of a resource that
2010 * can be bound as a render target or depth/stencil buffer.
2012 static struct pipe_surface
*
2013 iris_create_surface(struct pipe_context
*ctx
,
2014 struct pipe_resource
*tex
,
2015 const struct pipe_surface
*tmpl
)
2017 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2018 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2019 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2021 isl_surf_usage_flags_t usage
= 0;
2023 usage
= ISL_SURF_USAGE_STORAGE_BIT
;
2024 else if (util_format_is_depth_or_stencil(tmpl
->format
))
2025 usage
= ISL_SURF_USAGE_DEPTH_BIT
;
2027 usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
2029 const struct iris_format_info fmt
=
2030 iris_format_for_usage(devinfo
, tmpl
->format
, usage
);
2032 if ((usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) &&
2033 !isl_format_supports_rendering(devinfo
, fmt
.fmt
)) {
2034 /* Framebuffer validation will reject this invalid case, but it
2035 * hasn't had the opportunity yet. In the meantime, we need to
2036 * avoid hitting ISL asserts about unsupported formats below.
2041 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
2042 struct pipe_surface
*psurf
= &surf
->base
;
2043 struct iris_resource
*res
= (struct iris_resource
*) tex
;
2048 pipe_reference_init(&psurf
->reference
, 1);
2049 pipe_resource_reference(&psurf
->texture
, tex
);
2050 psurf
->context
= ctx
;
2051 psurf
->format
= tmpl
->format
;
2052 psurf
->width
= tex
->width0
;
2053 psurf
->height
= tex
->height0
;
2054 psurf
->texture
= tex
;
2055 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
2056 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
2057 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
2059 uint32_t array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1;
2061 struct isl_view
*view
= &surf
->view
;
2062 *view
= (struct isl_view
) {
2064 .base_level
= tmpl
->u
.tex
.level
,
2066 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
2067 .array_len
= array_len
,
2068 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2073 enum pipe_texture_target target
= (tex
->target
== PIPE_TEXTURE_3D
&&
2074 array_len
== 1) ? PIPE_TEXTURE_2D
:
2075 tex
->target
== PIPE_TEXTURE_1D_ARRAY
?
2076 PIPE_TEXTURE_2D_ARRAY
: tex
->target
;
2078 struct isl_view
*read_view
= &surf
->read_view
;
2079 *read_view
= (struct isl_view
) {
2081 .base_level
= tmpl
->u
.tex
.level
,
2083 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
2084 .array_len
= array_len
,
2085 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2086 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
,
2090 surf
->clear_color
= res
->aux
.clear_color
;
2092 /* Bail early for depth/stencil - we don't want SURFACE_STATE for them. */
2093 if (res
->surf
.usage
& (ISL_SURF_USAGE_DEPTH_BIT
|
2094 ISL_SURF_USAGE_STENCIL_BIT
))
2098 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
2099 &surf
->surface_state
,
2100 res
->aux
.possible_usages
);
2101 if (!unlikely(map
)) {
2102 pipe_resource_reference(&surf
->surface_state
.res
, NULL
);
2107 void *map_read
= alloc_surface_states(ice
->state
.surface_uploader
,
2108 &surf
->surface_state_read
,
2109 res
->aux
.possible_usages
);
2110 if (!unlikely(map_read
)) {
2111 pipe_resource_reference(&surf
->surface_state_read
.res
, NULL
);
2116 if (!isl_format_is_compressed(res
->surf
.format
)) {
2117 if (iris_resource_unfinished_aux_import(res
))
2118 iris_resource_finish_aux_import(&screen
->base
, res
);
2120 /* This is a normal surface. Fill out a SURFACE_STATE for each possible
2121 * auxiliary surface mode and return the pipe_surface.
2123 unsigned aux_modes
= res
->aux
.possible_usages
;
2126 uint32_t offset
= res
->offset
;
2128 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
2129 fill_surface_state(&screen
->isl_dev
, map
, res
, &res
->surf
,
2130 view
, aux_usage
, 0, 0);
2131 map
+= SURFACE_STATE_ALIGNMENT
;
2134 struct isl_surf surf
;
2135 uint32_t tile_x_sa
= 0, tile_y_sa
= 0;
2136 get_rt_read_isl_surf(devinfo
, res
, target
, read_view
,
2137 &tile_x_sa
, &tile_y_sa
, &surf
);
2138 fill_surface_state(&screen
->isl_dev
, map_read
, res
, &surf
, read_view
,
2139 aux_usage
, tile_x_sa
, tile_y_sa
);
2140 /* Restore offset because we change offset in case of handling
2141 * non_coherent fb fetch
2143 res
->offset
= offset
;
2144 map_read
+= SURFACE_STATE_ALIGNMENT
;
2151 /* The resource has a compressed format, which is not renderable, but we
2152 * have a renderable view format. We must be attempting to upload blocks
2153 * of compressed data via an uncompressed view.
2155 * In this case, we can assume there are no auxiliary buffers, a single
2156 * miplevel, and that the resource is single-sampled. Gallium may try
2157 * and create an uncompressed view with multiple layers, however.
2159 assert(!isl_format_is_compressed(fmt
.fmt
));
2160 assert(res
->aux
.possible_usages
== 1 << ISL_AUX_USAGE_NONE
);
2161 assert(res
->surf
.samples
== 1);
2162 assert(view
->levels
== 1);
2164 struct isl_surf isl_surf
;
2165 uint32_t offset_B
= 0, tile_x_sa
= 0, tile_y_sa
= 0;
2167 if (view
->base_level
> 0) {
2168 /* We can't rely on the hardware's miplevel selection with such
2169 * a substantial lie about the format, so we select a single image
2170 * using the Tile X/Y Offset fields. In this case, we can't handle
2171 * multiple array slices.
2173 * On Broadwell, HALIGN and VALIGN are specified in pixels and are
2174 * hard-coded to align to exactly the block size of the compressed
2175 * texture. This means that, when reinterpreted as a non-compressed
2176 * texture, the tile offsets may be anything and we can't rely on
2179 * Return NULL to force the state tracker to take fallback paths.
2181 if (view
->array_len
> 1 || GEN_GEN
== 8)
2184 const bool is_3d
= res
->surf
.dim
== ISL_SURF_DIM_3D
;
2185 isl_surf_get_image_surf(&screen
->isl_dev
, &res
->surf
,
2187 is_3d
? 0 : view
->base_array_layer
,
2188 is_3d
? view
->base_array_layer
: 0,
2190 &offset_B
, &tile_x_sa
, &tile_y_sa
);
2192 /* We use address and tile offsets to access a single level/layer
2193 * as a subimage, so reset level/layer so it doesn't offset again.
2195 view
->base_array_layer
= 0;
2196 view
->base_level
= 0;
2198 /* Level 0 doesn't require tile offsets, and the hardware can find
2199 * array slices using QPitch even with the format override, so we
2200 * can allow layers in this case. Copy the original ISL surface.
2202 memcpy(&isl_surf
, &res
->surf
, sizeof(isl_surf
));
2205 /* Scale down the image dimensions by the block size. */
2206 const struct isl_format_layout
*fmtl
=
2207 isl_format_get_layout(res
->surf
.format
);
2208 isl_surf
.format
= fmt
.fmt
;
2209 isl_surf
.logical_level0_px
= isl_surf_get_logical_level0_el(&isl_surf
);
2210 isl_surf
.phys_level0_sa
= isl_surf_get_phys_level0_el(&isl_surf
);
2211 tile_x_sa
/= fmtl
->bw
;
2212 tile_y_sa
/= fmtl
->bh
;
2214 psurf
->width
= isl_surf
.logical_level0_px
.width
;
2215 psurf
->height
= isl_surf
.logical_level0_px
.height
;
2217 struct isl_surf_fill_state_info f
= {
2220 .mocs
= mocs(res
->bo
),
2221 .address
= res
->bo
->gtt_offset
+ offset_B
,
2222 .x_offset_sa
= tile_x_sa
,
2223 .y_offset_sa
= tile_y_sa
,
2226 isl_surf_fill_state_s(&screen
->isl_dev
, map
, &f
);
2232 fill_default_image_param(struct brw_image_param
*param
)
2234 memset(param
, 0, sizeof(*param
));
2235 /* Set the swizzling shifts to all-ones to effectively disable swizzling --
2236 * See emit_address_calculation() in brw_fs_surface_builder.cpp for a more
2237 * detailed explanation of these parameters.
2239 param
->swizzling
[0] = 0xff;
2240 param
->swizzling
[1] = 0xff;
2244 fill_buffer_image_param(struct brw_image_param
*param
,
2245 enum pipe_format pfmt
,
2248 const unsigned cpp
= util_format_get_blocksize(pfmt
);
2250 fill_default_image_param(param
);
2251 param
->size
[0] = size
/ cpp
;
2252 param
->stride
[0] = cpp
;
2255 #define isl_surf_fill_image_param(x, ...)
2256 #define fill_default_image_param(x, ...)
2257 #define fill_buffer_image_param(x, ...)
2261 * The pipe->set_shader_images() driver hook.
2264 iris_set_shader_images(struct pipe_context
*ctx
,
2265 enum pipe_shader_type p_stage
,
2266 unsigned start_slot
, unsigned count
,
2267 const struct pipe_image_view
*p_images
)
2269 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2270 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2271 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2272 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2273 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2275 struct iris_genx_state
*genx
= ice
->state
.genx
;
2276 struct brw_image_param
*image_params
= genx
->shaders
[stage
].image_param
;
2279 shs
->bound_image_views
&= ~u_bit_consecutive(start_slot
, count
);
2281 for (unsigned i
= 0; i
< count
; i
++) {
2282 struct iris_image_view
*iv
= &shs
->image
[start_slot
+ i
];
2284 if (p_images
&& p_images
[i
].resource
) {
2285 const struct pipe_image_view
*img
= &p_images
[i
];
2286 struct iris_resource
*res
= (void *) img
->resource
;
2289 alloc_surface_states(ice
->state
.surface_uploader
,
2290 &iv
->surface_state
, 1 << ISL_AUX_USAGE_NONE
);
2294 util_copy_image_view(&iv
->base
, img
);
2296 shs
->bound_image_views
|= 1 << (start_slot
+ i
);
2298 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
2299 res
->bind_stages
|= 1 << stage
;
2301 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_STORAGE_BIT
;
2302 enum isl_format isl_fmt
=
2303 iris_format_for_usage(devinfo
, img
->format
, usage
).fmt
;
2305 bool untyped_fallback
= false;
2307 if (img
->shader_access
& PIPE_IMAGE_ACCESS_READ
) {
2308 /* On Gen8, try to use typed surfaces reads (which support a
2309 * limited number of formats), and if not possible, fall back
2312 untyped_fallback
= GEN_GEN
== 8 &&
2313 !isl_has_matching_typed_storage_image_format(devinfo
, isl_fmt
);
2315 if (untyped_fallback
)
2316 isl_fmt
= ISL_FORMAT_RAW
;
2318 isl_fmt
= isl_lower_storage_image_format(devinfo
, isl_fmt
);
2321 if (res
->base
.target
!= PIPE_BUFFER
) {
2322 struct isl_view view
= {
2324 .base_level
= img
->u
.tex
.level
,
2326 .base_array_layer
= img
->u
.tex
.first_layer
,
2327 .array_len
= img
->u
.tex
.last_layer
- img
->u
.tex
.first_layer
+ 1,
2328 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2332 if (untyped_fallback
) {
2333 fill_buffer_surface_state(&screen
->isl_dev
, res
, map
,
2334 isl_fmt
, ISL_SWIZZLE_IDENTITY
,
2337 /* Images don't support compression */
2338 unsigned aux_modes
= 1 << ISL_AUX_USAGE_NONE
;
2340 enum isl_aux_usage usage
= u_bit_scan(&aux_modes
);
2342 fill_surface_state(&screen
->isl_dev
, map
, res
, &res
->surf
,
2343 &view
, usage
, 0, 0);
2345 map
+= SURFACE_STATE_ALIGNMENT
;
2349 isl_surf_fill_image_param(&screen
->isl_dev
,
2350 &image_params
[start_slot
+ i
],
2353 util_range_add(&res
->valid_buffer_range
, img
->u
.buf
.offset
,
2354 img
->u
.buf
.offset
+ img
->u
.buf
.size
);
2356 fill_buffer_surface_state(&screen
->isl_dev
, res
, map
,
2357 isl_fmt
, ISL_SWIZZLE_IDENTITY
,
2358 img
->u
.buf
.offset
, img
->u
.buf
.size
);
2359 fill_buffer_image_param(&image_params
[start_slot
+ i
],
2360 img
->format
, img
->u
.buf
.size
);
2363 pipe_resource_reference(&iv
->base
.resource
, NULL
);
2364 pipe_resource_reference(&iv
->surface_state
.res
, NULL
);
2365 fill_default_image_param(&image_params
[start_slot
+ i
]);
2369 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2371 stage
== MESA_SHADER_COMPUTE
? IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES
2372 : IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
2374 /* Broadwell also needs brw_image_params re-uploaded */
2376 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
2377 shs
->sysvals_need_upload
= true;
2383 * The pipe->set_sampler_views() driver hook.
2386 iris_set_sampler_views(struct pipe_context
*ctx
,
2387 enum pipe_shader_type p_stage
,
2388 unsigned start
, unsigned count
,
2389 struct pipe_sampler_view
**views
)
2391 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2392 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2393 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2395 shs
->bound_sampler_views
&= ~u_bit_consecutive(start
, count
);
2397 for (unsigned i
= 0; i
< count
; i
++) {
2398 struct pipe_sampler_view
*pview
= views
? views
[i
] : NULL
;
2399 pipe_sampler_view_reference((struct pipe_sampler_view
**)
2400 &shs
->textures
[start
+ i
], pview
);
2401 struct iris_sampler_view
*view
= (void *) pview
;
2403 view
->res
->bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
2404 view
->res
->bind_stages
|= 1 << stage
;
2406 shs
->bound_sampler_views
|= 1 << (start
+ i
);
2410 ice
->state
.dirty
|= (IRIS_DIRTY_BINDINGS_VS
<< stage
);
2412 stage
== MESA_SHADER_COMPUTE
? IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES
2413 : IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
2417 * The pipe->set_tess_state() driver hook.
2420 iris_set_tess_state(struct pipe_context
*ctx
,
2421 const float default_outer_level
[4],
2422 const float default_inner_level
[2])
2424 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2425 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_TESS_CTRL
];
2427 memcpy(&ice
->state
.default_outer_level
[0], &default_outer_level
[0], 4 * sizeof(float));
2428 memcpy(&ice
->state
.default_inner_level
[0], &default_inner_level
[0], 2 * sizeof(float));
2430 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_TCS
;
2431 shs
->sysvals_need_upload
= true;
2435 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*p_surf
)
2437 struct iris_surface
*surf
= (void *) p_surf
;
2438 pipe_resource_reference(&p_surf
->texture
, NULL
);
2439 pipe_resource_reference(&surf
->surface_state
.res
, NULL
);
2440 pipe_resource_reference(&surf
->surface_state_read
.res
, NULL
);
2445 iris_set_clip_state(struct pipe_context
*ctx
,
2446 const struct pipe_clip_state
*state
)
2448 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2449 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_VERTEX
];
2450 struct iris_shader_state
*gshs
= &ice
->state
.shaders
[MESA_SHADER_GEOMETRY
];
2451 struct iris_shader_state
*tshs
= &ice
->state
.shaders
[MESA_SHADER_TESS_EVAL
];
2453 memcpy(&ice
->state
.clip_planes
, state
, sizeof(*state
));
2455 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
| IRIS_DIRTY_CONSTANTS_GS
|
2456 IRIS_DIRTY_CONSTANTS_TES
;
2457 shs
->sysvals_need_upload
= true;
2458 gshs
->sysvals_need_upload
= true;
2459 tshs
->sysvals_need_upload
= true;
2463 * The pipe->set_polygon_stipple() driver hook.
2466 iris_set_polygon_stipple(struct pipe_context
*ctx
,
2467 const struct pipe_poly_stipple
*state
)
2469 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2470 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
2471 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
2475 * The pipe->set_sample_mask() driver hook.
2478 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
2480 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2482 /* We only support 16x MSAA, so we have 16 bits of sample maks.
2483 * st/mesa may pass us 0xffffffff though, meaning "enable all samples".
2485 ice
->state
.sample_mask
= sample_mask
& 0xffff;
2486 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
2490 * The pipe->set_scissor_states() driver hook.
2492 * This corresponds to our SCISSOR_RECT state structures. It's an
2493 * exact match, so we just store them, and memcpy them out later.
2496 iris_set_scissor_states(struct pipe_context
*ctx
,
2497 unsigned start_slot
,
2498 unsigned num_scissors
,
2499 const struct pipe_scissor_state
*rects
)
2501 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2503 for (unsigned i
= 0; i
< num_scissors
; i
++) {
2504 if (rects
[i
].minx
== rects
[i
].maxx
|| rects
[i
].miny
== rects
[i
].maxy
) {
2505 /* If the scissor was out of bounds and got clamped to 0 width/height
2506 * at the bounds, the subtraction of 1 from maximums could produce a
2507 * negative number and thus not clip anything. Instead, just provide
2508 * a min > max scissor inside the bounds, which produces the expected
2511 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
2512 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,
2515 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
2516 .minx
= rects
[i
].minx
, .miny
= rects
[i
].miny
,
2517 .maxx
= rects
[i
].maxx
- 1, .maxy
= rects
[i
].maxy
- 1,
2522 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
2526 * The pipe->set_stencil_ref() driver hook.
2528 * This is added to 3DSTATE_WM_DEPTH_STENCIL dynamically at draw time.
2531 iris_set_stencil_ref(struct pipe_context
*ctx
,
2532 const struct pipe_stencil_ref
*state
)
2534 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2535 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
2537 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
2539 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
2543 viewport_extent(const struct pipe_viewport_state
*state
, int axis
, float sign
)
2545 return copysignf(state
->scale
[axis
], sign
) + state
->translate
[axis
];
2549 * The pipe->set_viewport_states() driver hook.
2551 * This corresponds to our SF_CLIP_VIEWPORT states. We can't calculate
2552 * the guardband yet, as we need the framebuffer dimensions, but we can
2553 * at least fill out the rest.
2556 iris_set_viewport_states(struct pipe_context
*ctx
,
2557 unsigned start_slot
,
2559 const struct pipe_viewport_state
*states
)
2561 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2563 memcpy(&ice
->state
.viewports
[start_slot
], states
, sizeof(*states
) * count
);
2565 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2567 if (ice
->state
.cso_rast
&& (!ice
->state
.cso_rast
->depth_clip_near
||
2568 !ice
->state
.cso_rast
->depth_clip_far
))
2569 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
2573 * The pipe->set_framebuffer_state() driver hook.
2575 * Sets the current draw FBO, including color render targets, depth,
2576 * and stencil buffers.
2579 iris_set_framebuffer_state(struct pipe_context
*ctx
,
2580 const struct pipe_framebuffer_state
*state
)
2582 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2583 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2584 struct isl_device
*isl_dev
= &screen
->isl_dev
;
2585 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
2586 struct iris_resource
*zres
;
2587 struct iris_resource
*stencil_res
;
2589 unsigned samples
= util_framebuffer_get_num_samples(state
);
2590 unsigned layers
= util_framebuffer_get_num_layers(state
);
2592 if (cso
->samples
!= samples
) {
2593 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
2595 /* We need to toggle 3DSTATE_PS::32 Pixel Dispatch Enable */
2596 if (GEN_GEN
>= 9 && (cso
->samples
== 16 || samples
== 16))
2597 ice
->state
.dirty
|= IRIS_DIRTY_FS
;
2600 if (cso
->nr_cbufs
!= state
->nr_cbufs
) {
2601 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
2604 if ((cso
->layers
== 0) != (layers
== 0)) {
2605 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
2608 if (cso
->width
!= state
->width
|| cso
->height
!= state
->height
) {
2609 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2612 if (cso
->zsbuf
|| state
->zsbuf
) {
2613 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
2616 util_copy_framebuffer_state(cso
, state
);
2617 cso
->samples
= samples
;
2618 cso
->layers
= layers
;
2620 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
2622 struct isl_view view
= {
2625 .base_array_layer
= 0,
2627 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2630 struct isl_depth_stencil_hiz_emit_info info
= { .view
= &view
};
2633 iris_get_depth_stencil_resources(cso
->zsbuf
->texture
, &zres
,
2636 view
.base_level
= cso
->zsbuf
->u
.tex
.level
;
2637 view
.base_array_layer
= cso
->zsbuf
->u
.tex
.first_layer
;
2639 cso
->zsbuf
->u
.tex
.last_layer
- cso
->zsbuf
->u
.tex
.first_layer
+ 1;
2642 view
.usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
2644 info
.depth_surf
= &zres
->surf
;
2645 info
.depth_address
= zres
->bo
->gtt_offset
+ zres
->offset
;
2646 info
.mocs
= mocs(zres
->bo
);
2648 view
.format
= zres
->surf
.format
;
2650 if (iris_resource_level_has_hiz(zres
, view
.base_level
)) {
2651 info
.hiz_usage
= ISL_AUX_USAGE_HIZ
;
2652 info
.hiz_surf
= &zres
->aux
.surf
;
2653 info
.hiz_address
= zres
->aux
.bo
->gtt_offset
+ zres
->aux
.offset
;
2658 view
.usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
2659 info
.stencil_surf
= &stencil_res
->surf
;
2660 info
.stencil_address
= stencil_res
->bo
->gtt_offset
+ stencil_res
->offset
;
2662 view
.format
= stencil_res
->surf
.format
;
2663 info
.mocs
= mocs(stencil_res
->bo
);
2668 isl_emit_depth_stencil_hiz_s(isl_dev
, cso_z
->packets
, &info
);
2670 /* Make a null surface for unbound buffers */
2671 void *null_surf_map
=
2672 upload_state(ice
->state
.surface_uploader
, &ice
->state
.null_fb
,
2673 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2674 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
,
2675 isl_extent3d(MAX2(cso
->width
, 1),
2676 MAX2(cso
->height
, 1),
2677 cso
->layers
? cso
->layers
: 1));
2678 ice
->state
.null_fb
.offset
+=
2679 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.null_fb
.res
));
2681 /* Render target change */
2682 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_FS
;
2684 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
2686 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_FRAMEBUFFER
];
2689 // XXX: we may want to flag IRIS_DIRTY_MULTISAMPLE (or SAMPLE_MASK?)
2690 // XXX: see commit 979fc1bc9bcc64027ff2cfafd285676f31b930a6
2692 /* The PIPE_CONTROL command description says:
2694 * "Whenever a Binding Table Index (BTI) used by a Render Target Message
2695 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2696 * Target Cache Flush by enabling this bit. When render target flush
2697 * is set due to new association of BTI, PS Scoreboard Stall bit must
2698 * be set in this packet."
2700 // XXX: does this need to happen at 3DSTATE_BTP_PS time?
2701 iris_emit_pipe_control_flush(&ice
->batches
[IRIS_BATCH_RENDER
],
2702 "workaround: RT BTI change [draw]",
2703 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
2704 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
2709 * The pipe->set_constant_buffer() driver hook.
2711 * This uploads any constant data in user buffers, and references
2712 * any UBO resources containing constant data.
2715 iris_set_constant_buffer(struct pipe_context
*ctx
,
2716 enum pipe_shader_type p_stage
, unsigned index
,
2717 const struct pipe_constant_buffer
*input
)
2719 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2720 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2721 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2722 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[index
];
2724 /* TODO: Only do this if the buffer changes? */
2725 pipe_resource_reference(&shs
->constbuf_surf_state
[index
].res
, NULL
);
2727 if (input
&& input
->buffer_size
&& (input
->buffer
|| input
->user_buffer
)) {
2728 shs
->bound_cbufs
|= 1u << index
;
2730 if (input
->user_buffer
) {
2732 pipe_resource_reference(&cbuf
->buffer
, NULL
);
2733 u_upload_alloc(ice
->ctx
.const_uploader
, 0, input
->buffer_size
, 64,
2734 &cbuf
->buffer_offset
, &cbuf
->buffer
, (void **) &map
);
2736 if (!cbuf
->buffer
) {
2737 /* Allocation was unsuccessful - just unbind */
2738 iris_set_constant_buffer(ctx
, p_stage
, index
, NULL
);
2743 memcpy(map
, input
->user_buffer
, input
->buffer_size
);
2744 } else if (input
->buffer
) {
2745 pipe_resource_reference(&cbuf
->buffer
, input
->buffer
);
2747 cbuf
->buffer_offset
= input
->buffer_offset
;
2751 MIN2(input
->buffer_size
,
2752 iris_resource_bo(cbuf
->buffer
)->size
- cbuf
->buffer_offset
);
2754 struct iris_resource
*res
= (void *) cbuf
->buffer
;
2755 res
->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
2756 res
->bind_stages
|= 1 << stage
;
2758 shs
->bound_cbufs
&= ~(1u << index
);
2759 pipe_resource_reference(&cbuf
->buffer
, NULL
);
2762 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
2766 upload_sysvals(struct iris_context
*ice
,
2767 gl_shader_stage stage
)
2769 UNUSED
struct iris_genx_state
*genx
= ice
->state
.genx
;
2770 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2772 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2773 if (!shader
|| shader
->num_system_values
== 0)
2776 assert(shader
->num_cbufs
> 0);
2778 unsigned sysval_cbuf_index
= shader
->num_cbufs
- 1;
2779 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[sysval_cbuf_index
];
2780 unsigned upload_size
= shader
->num_system_values
* sizeof(uint32_t);
2781 uint32_t *map
= NULL
;
2783 assert(sysval_cbuf_index
< PIPE_MAX_CONSTANT_BUFFERS
);
2784 u_upload_alloc(ice
->ctx
.const_uploader
, 0, upload_size
, 64,
2785 &cbuf
->buffer_offset
, &cbuf
->buffer
, (void **) &map
);
2787 for (int i
= 0; i
< shader
->num_system_values
; i
++) {
2788 uint32_t sysval
= shader
->system_values
[i
];
2791 if (BRW_PARAM_DOMAIN(sysval
) == BRW_PARAM_DOMAIN_IMAGE
) {
2793 unsigned img
= BRW_PARAM_IMAGE_IDX(sysval
);
2794 unsigned offset
= BRW_PARAM_IMAGE_OFFSET(sysval
);
2795 struct brw_image_param
*param
=
2796 &genx
->shaders
[stage
].image_param
[img
];
2798 assert(offset
< sizeof(struct brw_image_param
));
2799 value
= ((uint32_t *) param
)[offset
];
2801 } else if (sysval
== BRW_PARAM_BUILTIN_ZERO
) {
2803 } else if (BRW_PARAM_BUILTIN_IS_CLIP_PLANE(sysval
)) {
2804 int plane
= BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(sysval
);
2805 int comp
= BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(sysval
);
2806 value
= fui(ice
->state
.clip_planes
.ucp
[plane
][comp
]);
2807 } else if (sysval
== BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
) {
2808 if (stage
== MESA_SHADER_TESS_CTRL
) {
2809 value
= ice
->state
.vertices_per_patch
;
2811 assert(stage
== MESA_SHADER_TESS_EVAL
);
2812 const struct shader_info
*tcs_info
=
2813 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
2815 value
= tcs_info
->tess
.tcs_vertices_out
;
2817 value
= ice
->state
.vertices_per_patch
;
2819 } else if (sysval
>= BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
&&
2820 sysval
<= BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W
) {
2821 unsigned i
= sysval
- BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
;
2822 value
= fui(ice
->state
.default_outer_level
[i
]);
2823 } else if (sysval
== BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
) {
2824 value
= fui(ice
->state
.default_inner_level
[0]);
2825 } else if (sysval
== BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
) {
2826 value
= fui(ice
->state
.default_inner_level
[1]);
2828 assert(!"unhandled system value");
2834 cbuf
->buffer_size
= upload_size
;
2835 iris_upload_ubo_ssbo_surf_state(ice
, cbuf
,
2836 &shs
->constbuf_surf_state
[sysval_cbuf_index
], false);
2838 shs
->sysvals_need_upload
= false;
2842 * The pipe->set_shader_buffers() driver hook.
2844 * This binds SSBOs and ABOs. Unfortunately, we need to stream out
2845 * SURFACE_STATE here, as the buffer offset may change each time.
2848 iris_set_shader_buffers(struct pipe_context
*ctx
,
2849 enum pipe_shader_type p_stage
,
2850 unsigned start_slot
, unsigned count
,
2851 const struct pipe_shader_buffer
*buffers
,
2852 unsigned writable_bitmask
)
2854 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2855 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2856 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2858 unsigned modified_bits
= u_bit_consecutive(start_slot
, count
);
2860 shs
->bound_ssbos
&= ~modified_bits
;
2861 shs
->writable_ssbos
&= ~modified_bits
;
2862 shs
->writable_ssbos
|= writable_bitmask
<< start_slot
;
2864 for (unsigned i
= 0; i
< count
; i
++) {
2865 if (buffers
&& buffers
[i
].buffer
) {
2866 struct iris_resource
*res
= (void *) buffers
[i
].buffer
;
2867 struct pipe_shader_buffer
*ssbo
= &shs
->ssbo
[start_slot
+ i
];
2868 struct iris_state_ref
*surf_state
=
2869 &shs
->ssbo_surf_state
[start_slot
+ i
];
2870 pipe_resource_reference(&ssbo
->buffer
, &res
->base
);
2871 ssbo
->buffer_offset
= buffers
[i
].buffer_offset
;
2873 MIN2(buffers
[i
].buffer_size
, res
->bo
->size
- ssbo
->buffer_offset
);
2875 shs
->bound_ssbos
|= 1 << (start_slot
+ i
);
2877 iris_upload_ubo_ssbo_surf_state(ice
, ssbo
, surf_state
, true);
2879 res
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
2880 res
->bind_stages
|= 1 << stage
;
2882 util_range_add(&res
->valid_buffer_range
, ssbo
->buffer_offset
,
2883 ssbo
->buffer_offset
+ ssbo
->buffer_size
);
2885 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
].buffer
, NULL
);
2886 pipe_resource_reference(&shs
->ssbo_surf_state
[start_slot
+ i
].res
,
2891 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2895 iris_delete_state(struct pipe_context
*ctx
, void *state
)
2901 * The pipe->set_vertex_buffers() driver hook.
2903 * This translates pipe_vertex_buffer to our 3DSTATE_VERTEX_BUFFERS packet.
2906 iris_set_vertex_buffers(struct pipe_context
*ctx
,
2907 unsigned start_slot
, unsigned count
,
2908 const struct pipe_vertex_buffer
*buffers
)
2910 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2911 struct iris_genx_state
*genx
= ice
->state
.genx
;
2913 ice
->state
.bound_vertex_buffers
&= ~u_bit_consecutive64(start_slot
, count
);
2915 for (unsigned i
= 0; i
< count
; i
++) {
2916 const struct pipe_vertex_buffer
*buffer
= buffers
? &buffers
[i
] : NULL
;
2917 struct iris_vertex_buffer_state
*state
=
2918 &genx
->vertex_buffers
[start_slot
+ i
];
2921 pipe_resource_reference(&state
->resource
, NULL
);
2925 /* We may see user buffers that are NULL bindings. */
2926 assert(!(buffer
->is_user_buffer
&& buffer
->buffer
.user
!= NULL
));
2928 pipe_resource_reference(&state
->resource
, buffer
->buffer
.resource
);
2929 struct iris_resource
*res
= (void *) state
->resource
;
2932 ice
->state
.bound_vertex_buffers
|= 1ull << (start_slot
+ i
);
2933 res
->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
2936 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
2937 vb
.VertexBufferIndex
= start_slot
+ i
;
2938 vb
.AddressModifyEnable
= true;
2939 vb
.BufferPitch
= buffer
->stride
;
2941 vb
.BufferSize
= res
->bo
->size
- (int) buffer
->buffer_offset
;
2942 vb
.BufferStartingAddress
=
2943 ro_bo(NULL
, res
->bo
->gtt_offset
+ (int) buffer
->buffer_offset
);
2944 vb
.MOCS
= mocs(res
->bo
);
2946 vb
.NullVertexBuffer
= true;
2951 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
2955 * Gallium CSO for vertex elements.
2957 struct iris_vertex_element_state
{
2958 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
2959 uint32_t vf_instancing
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
2960 uint32_t edgeflag_ve
[GENX(VERTEX_ELEMENT_STATE_length
)];
2961 uint32_t edgeflag_vfi
[GENX(3DSTATE_VF_INSTANCING_length
)];
2966 * The pipe->create_vertex_elements() driver hook.
2968 * This translates pipe_vertex_element to our 3DSTATE_VERTEX_ELEMENTS
2969 * and 3DSTATE_VF_INSTANCING commands. The vertex_elements and vf_instancing
2970 * arrays are ready to be emitted at draw time if no EdgeFlag or SGVs are
2971 * needed. In these cases we will need information available at draw time.
2972 * We setup edgeflag_ve and edgeflag_vfi as alternatives last
2973 * 3DSTATE_VERTEX_ELEMENT and 3DSTATE_VF_INSTANCING that can be used at
2974 * draw time if we detect that EdgeFlag is needed by the Vertex Shader.
2977 iris_create_vertex_elements(struct pipe_context
*ctx
,
2979 const struct pipe_vertex_element
*state
)
2981 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2982 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2983 struct iris_vertex_element_state
*cso
=
2984 malloc(sizeof(struct iris_vertex_element_state
));
2988 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
) {
2990 1 + GENX(VERTEX_ELEMENT_STATE_length
) * MAX2(count
, 1) - 2;
2993 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
2994 uint32_t *vfi_pack_dest
= cso
->vf_instancing
;
2997 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
2999 ve
.SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
3000 ve
.Component0Control
= VFCOMP_STORE_0
;
3001 ve
.Component1Control
= VFCOMP_STORE_0
;
3002 ve
.Component2Control
= VFCOMP_STORE_0
;
3003 ve
.Component3Control
= VFCOMP_STORE_1_FP
;
3006 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
3010 for (int i
= 0; i
< count
; i
++) {
3011 const struct iris_format_info fmt
=
3012 iris_format_for_usage(devinfo
, state
[i
].src_format
, 0);
3013 unsigned comp
[4] = { VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
,
3014 VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
};
3016 switch (isl_format_get_num_channels(fmt
.fmt
)) {
3017 case 0: comp
[0] = VFCOMP_STORE_0
; /* fallthrough */
3018 case 1: comp
[1] = VFCOMP_STORE_0
; /* fallthrough */
3019 case 2: comp
[2] = VFCOMP_STORE_0
; /* fallthrough */
3021 comp
[3] = isl_format_has_int_channel(fmt
.fmt
) ? VFCOMP_STORE_1_INT
3022 : VFCOMP_STORE_1_FP
;
3025 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
3026 ve
.EdgeFlagEnable
= false;
3027 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
3029 ve
.SourceElementOffset
= state
[i
].src_offset
;
3030 ve
.SourceElementFormat
= fmt
.fmt
;
3031 ve
.Component0Control
= comp
[0];
3032 ve
.Component1Control
= comp
[1];
3033 ve
.Component2Control
= comp
[2];
3034 ve
.Component3Control
= comp
[3];
3037 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
3038 vi
.VertexElementIndex
= i
;
3039 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
3040 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
3043 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
3044 vfi_pack_dest
+= GENX(3DSTATE_VF_INSTANCING_length
);
3047 /* An alternative version of the last VE and VFI is stored so it
3048 * can be used at draw time in case Vertex Shader uses EdgeFlag
3051 const unsigned edgeflag_index
= count
- 1;
3052 const struct iris_format_info fmt
=
3053 iris_format_for_usage(devinfo
, state
[edgeflag_index
].src_format
, 0);
3054 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), cso
->edgeflag_ve
, ve
) {
3055 ve
.EdgeFlagEnable
= true ;
3056 ve
.VertexBufferIndex
= state
[edgeflag_index
].vertex_buffer_index
;
3058 ve
.SourceElementOffset
= state
[edgeflag_index
].src_offset
;
3059 ve
.SourceElementFormat
= fmt
.fmt
;
3060 ve
.Component0Control
= VFCOMP_STORE_SRC
;
3061 ve
.Component1Control
= VFCOMP_STORE_0
;
3062 ve
.Component2Control
= VFCOMP_STORE_0
;
3063 ve
.Component3Control
= VFCOMP_STORE_0
;
3065 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), cso
->edgeflag_vfi
, vi
) {
3066 /* The vi.VertexElementIndex of the EdgeFlag Vertex Element is filled
3067 * at draw time, as it should change if SGVs are emitted.
3069 vi
.InstancingEnable
= state
[edgeflag_index
].instance_divisor
> 0;
3070 vi
.InstanceDataStepRate
= state
[edgeflag_index
].instance_divisor
;
3078 * The pipe->bind_vertex_elements_state() driver hook.
3081 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
3083 struct iris_context
*ice
= (struct iris_context
*) ctx
;
3084 struct iris_vertex_element_state
*old_cso
= ice
->state
.cso_vertex_elements
;
3085 struct iris_vertex_element_state
*new_cso
= state
;
3087 /* 3DSTATE_VF_SGVs overrides the last VE, so if the count is changing,
3088 * we need to re-emit it to ensure we're overriding the right one.
3090 if (new_cso
&& cso_changed(count
))
3091 ice
->state
.dirty
|= IRIS_DIRTY_VF_SGVS
;
3093 ice
->state
.cso_vertex_elements
= state
;
3094 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
3098 * The pipe->create_stream_output_target() driver hook.
3100 * "Target" here refers to a destination buffer. We translate this into
3101 * a 3DSTATE_SO_BUFFER packet. We can handle most fields, but don't yet
3102 * know which buffer this represents, or whether we ought to zero the
3103 * write-offsets, or append. Those are handled in the set() hook.
3105 static struct pipe_stream_output_target
*
3106 iris_create_stream_output_target(struct pipe_context
*ctx
,
3107 struct pipe_resource
*p_res
,
3108 unsigned buffer_offset
,
3109 unsigned buffer_size
)
3111 struct iris_resource
*res
= (void *) p_res
;
3112 struct iris_stream_output_target
*cso
= calloc(1, sizeof(*cso
));
3116 res
->bind_history
|= PIPE_BIND_STREAM_OUTPUT
;
3118 pipe_reference_init(&cso
->base
.reference
, 1);
3119 pipe_resource_reference(&cso
->base
.buffer
, p_res
);
3120 cso
->base
.buffer_offset
= buffer_offset
;
3121 cso
->base
.buffer_size
= buffer_size
;
3122 cso
->base
.context
= ctx
;
3124 util_range_add(&res
->valid_buffer_range
, buffer_offset
,
3125 buffer_offset
+ buffer_size
);
3127 upload_state(ctx
->stream_uploader
, &cso
->offset
, sizeof(uint32_t), 4);
3133 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
3134 struct pipe_stream_output_target
*state
)
3136 struct iris_stream_output_target
*cso
= (void *) state
;
3138 pipe_resource_reference(&cso
->base
.buffer
, NULL
);
3139 pipe_resource_reference(&cso
->offset
.res
, NULL
);
3145 * The pipe->set_stream_output_targets() driver hook.
3147 * At this point, we know which targets are bound to a particular index,
3148 * and also whether we want to append or start over. We can finish the
3149 * 3DSTATE_SO_BUFFER packets we started earlier.
3152 iris_set_stream_output_targets(struct pipe_context
*ctx
,
3153 unsigned num_targets
,
3154 struct pipe_stream_output_target
**targets
,
3155 const unsigned *offsets
)
3157 struct iris_context
*ice
= (struct iris_context
*) ctx
;
3158 struct iris_genx_state
*genx
= ice
->state
.genx
;
3159 uint32_t *so_buffers
= genx
->so_buffers
;
3161 const bool active
= num_targets
> 0;
3162 if (ice
->state
.streamout_active
!= active
) {
3163 ice
->state
.streamout_active
= active
;
3164 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
3166 /* We only emit 3DSTATE_SO_DECL_LIST when streamout is active, because
3167 * it's a non-pipelined command. If we're switching streamout on, we
3168 * may have missed emitting it earlier, so do so now. (We're already
3169 * taking a stall to update 3DSTATE_SO_BUFFERS anyway...)
3172 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
;
3175 for (int i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
3176 struct iris_stream_output_target
*tgt
=
3177 (void *) ice
->state
.so_target
[i
];
3179 struct iris_resource
*res
= (void *) tgt
->base
.buffer
;
3181 flush
|= iris_flush_bits_for_history(res
);
3182 iris_dirty_for_history(ice
, res
);
3185 iris_emit_pipe_control_flush(&ice
->batches
[IRIS_BATCH_RENDER
],
3186 "make streamout results visible", flush
);
3190 for (int i
= 0; i
< 4; i
++) {
3191 pipe_so_target_reference(&ice
->state
.so_target
[i
],
3192 i
< num_targets
? targets
[i
] : NULL
);
3195 /* No need to update 3DSTATE_SO_BUFFER unless SOL is active. */
3199 for (unsigned i
= 0; i
< 4; i
++,
3200 so_buffers
+= GENX(3DSTATE_SO_BUFFER_length
)) {
3202 struct iris_stream_output_target
*tgt
= (void *) ice
->state
.so_target
[i
];
3203 unsigned offset
= offsets
[i
];
3206 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
)
3207 sob
.SOBufferIndex
= i
;
3211 struct iris_resource
*res
= (void *) tgt
->base
.buffer
;
3213 /* Note that offsets[i] will either be 0, causing us to zero
3214 * the value in the buffer, or 0xFFFFFFFF, which happens to mean
3215 * "continue appending at the existing offset."
3217 assert(offset
== 0 || offset
== 0xFFFFFFFF);
3219 /* We might be called by Begin (offset = 0), Pause, then Resume
3220 * (offset = 0xFFFFFFFF) before ever drawing (where these commands
3221 * will actually be sent to the GPU). In this case, we don't want
3222 * to append - we still want to do our initial zeroing.
3227 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
) {
3228 sob
.SurfaceBaseAddress
=
3229 rw_bo(NULL
, res
->bo
->gtt_offset
+ tgt
->base
.buffer_offset
);
3230 sob
.SOBufferEnable
= true;
3231 sob
.StreamOffsetWriteEnable
= true;
3232 sob
.StreamOutputBufferOffsetAddressEnable
= true;
3233 sob
.MOCS
= mocs(res
->bo
);
3235 sob
.SurfaceSize
= MAX2(tgt
->base
.buffer_size
/ 4, 1) - 1;
3237 sob
.SOBufferIndex
= i
;
3238 sob
.StreamOffset
= offset
;
3239 sob
.StreamOutputBufferOffsetAddress
=
3240 rw_bo(NULL
, iris_resource_bo(tgt
->offset
.res
)->gtt_offset
+
3241 tgt
->offset
.offset
);
3245 ice
->state
.dirty
|= IRIS_DIRTY_SO_BUFFERS
;
3249 * An iris-vtable helper for encoding the 3DSTATE_SO_DECL_LIST and
3250 * 3DSTATE_STREAMOUT packets.
3252 * 3DSTATE_SO_DECL_LIST is a list of shader outputs we want the streamout
3253 * hardware to record. We can create it entirely based on the shader, with
3254 * no dynamic state dependencies.
3256 * 3DSTATE_STREAMOUT is an annoying mix of shader-based information and
3257 * state-based settings. We capture the shader-related ones here, and merge
3258 * the rest in at draw time.
3261 iris_create_so_decl_list(const struct pipe_stream_output_info
*info
,
3262 const struct brw_vue_map
*vue_map
)
3264 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
3265 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3266 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3267 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3269 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
3271 memset(so_decl
, 0, sizeof(so_decl
));
3273 /* Construct the list of SO_DECLs to be emitted. The formatting of the
3274 * command feels strange -- each dword pair contains a SO_DECL per stream.
3276 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
3277 const struct pipe_stream_output
*output
= &info
->output
[i
];
3278 const int buffer
= output
->output_buffer
;
3279 const int varying
= output
->register_index
;
3280 const unsigned stream_id
= output
->stream
;
3281 assert(stream_id
< MAX_VERTEX_STREAMS
);
3283 buffer_mask
[stream_id
] |= 1 << buffer
;
3285 assert(vue_map
->varying_to_slot
[varying
] >= 0);
3287 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
3288 * array. Instead, it simply increments DstOffset for the following
3289 * input by the number of components that should be skipped.
3291 * Our hardware is unusual in that it requires us to program SO_DECLs
3292 * for fake "hole" components, rather than simply taking the offset
3293 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
3294 * program as many size = 4 holes as we can, then a final hole to
3295 * accommodate the final 1, 2, or 3 remaining.
3297 int skip_components
= output
->dst_offset
- next_offset
[buffer
];
3299 while (skip_components
> 0) {
3300 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3302 .OutputBufferSlot
= output
->output_buffer
,
3303 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
3305 skip_components
-= 4;
3308 next_offset
[buffer
] = output
->dst_offset
+ output
->num_components
;
3310 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3311 .OutputBufferSlot
= output
->output_buffer
,
3312 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
3314 ((1 << output
->num_components
) - 1) << output
->start_component
,
3317 if (decls
[stream_id
] > max_decls
)
3318 max_decls
= decls
[stream_id
];
3321 unsigned dwords
= GENX(3DSTATE_STREAMOUT_length
) + (3 + 2 * max_decls
);
3322 uint32_t *map
= ralloc_size(NULL
, sizeof(uint32_t) * dwords
);
3323 uint32_t *so_decl_map
= map
+ GENX(3DSTATE_STREAMOUT_length
);
3325 iris_pack_command(GENX(3DSTATE_STREAMOUT
), map
, sol
) {
3326 int urb_entry_read_offset
= 0;
3327 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
3328 urb_entry_read_offset
;
3330 /* We always read the whole vertex. This could be reduced at some
3331 * point by reading less and offsetting the register index in the
3334 sol
.Stream0VertexReadOffset
= urb_entry_read_offset
;
3335 sol
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
3336 sol
.Stream1VertexReadOffset
= urb_entry_read_offset
;
3337 sol
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
3338 sol
.Stream2VertexReadOffset
= urb_entry_read_offset
;
3339 sol
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
3340 sol
.Stream3VertexReadOffset
= urb_entry_read_offset
;
3341 sol
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
3343 /* Set buffer pitches; 0 means unbound. */
3344 sol
.Buffer0SurfacePitch
= 4 * info
->stride
[0];
3345 sol
.Buffer1SurfacePitch
= 4 * info
->stride
[1];
3346 sol
.Buffer2SurfacePitch
= 4 * info
->stride
[2];
3347 sol
.Buffer3SurfacePitch
= 4 * info
->stride
[3];
3350 iris_pack_command(GENX(3DSTATE_SO_DECL_LIST
), so_decl_map
, list
) {
3351 list
.DWordLength
= 3 + 2 * max_decls
- 2;
3352 list
.StreamtoBufferSelects0
= buffer_mask
[0];
3353 list
.StreamtoBufferSelects1
= buffer_mask
[1];
3354 list
.StreamtoBufferSelects2
= buffer_mask
[2];
3355 list
.StreamtoBufferSelects3
= buffer_mask
[3];
3356 list
.NumEntries0
= decls
[0];
3357 list
.NumEntries1
= decls
[1];
3358 list
.NumEntries2
= decls
[2];
3359 list
.NumEntries3
= decls
[3];
3362 for (int i
= 0; i
< max_decls
; i
++) {
3363 iris_pack_state(GENX(SO_DECL_ENTRY
), so_decl_map
+ 3 + i
* 2, entry
) {
3364 entry
.Stream0Decl
= so_decl
[0][i
];
3365 entry
.Stream1Decl
= so_decl
[1][i
];
3366 entry
.Stream2Decl
= so_decl
[2][i
];
3367 entry
.Stream3Decl
= so_decl
[3][i
];
3375 iris_compute_sbe_urb_read_interval(uint64_t fs_input_slots
,
3376 const struct brw_vue_map
*last_vue_map
,
3377 bool two_sided_color
,
3378 unsigned *out_offset
,
3379 unsigned *out_length
)
3381 /* The compiler computes the first URB slot without considering COL/BFC
3382 * swizzling (because it doesn't know whether it's enabled), so we need
3383 * to do that here too. This may result in a smaller offset, which
3386 const unsigned first_slot
=
3387 brw_compute_first_urb_slot_required(fs_input_slots
, last_vue_map
);
3389 /* This becomes the URB read offset (counted in pairs of slots). */
3390 assert(first_slot
% 2 == 0);
3391 *out_offset
= first_slot
/ 2;
3393 /* We need to adjust the inputs read to account for front/back color
3394 * swizzling, as it can make the URB length longer.
3396 for (int c
= 0; c
<= 1; c
++) {
3397 if (fs_input_slots
& (VARYING_BIT_COL0
<< c
)) {
3398 /* If two sided color is enabled, the fragment shader's gl_Color
3399 * (COL0) input comes from either the gl_FrontColor (COL0) or
3400 * gl_BackColor (BFC0) input varyings. Mark BFC as used, too.
3402 if (two_sided_color
)
3403 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
3405 /* If front color isn't written, we opt to give them back color
3406 * instead of an undefined value. Switch from COL to BFC.
3408 if (last_vue_map
->varying_to_slot
[VARYING_SLOT_COL0
+ c
] == -1) {
3409 fs_input_slots
&= ~(VARYING_BIT_COL0
<< c
);
3410 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
3415 /* Compute the minimum URB Read Length necessary for the FS inputs.
3417 * From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
3418 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
3420 * "This field should be set to the minimum length required to read the
3421 * maximum source attribute. The maximum source attribute is indicated
3422 * by the maximum value of the enabled Attribute # Source Attribute if
3423 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
3424 * enable is not set.
3425 * read_length = ceiling((max_source_attr + 1) / 2)
3427 * [errata] Corruption/Hang possible if length programmed larger than
3430 * Similar text exists for Ivy Bridge.
3432 * We find the last URB slot that's actually read by the FS.
3434 unsigned last_read_slot
= last_vue_map
->num_slots
- 1;
3435 while (last_read_slot
> first_slot
&& !(fs_input_slots
&
3436 (1ull << last_vue_map
->slot_to_varying
[last_read_slot
])))
3439 /* The URB read length is the difference of the two, counted in pairs. */
3440 *out_length
= DIV_ROUND_UP(last_read_slot
- first_slot
+ 1, 2);
3444 iris_emit_sbe_swiz(struct iris_batch
*batch
,
3445 const struct iris_context
*ice
,
3446 unsigned urb_read_offset
,
3447 unsigned sprite_coord_enables
)
3449 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = {};
3450 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
3451 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3452 const struct brw_vue_map
*vue_map
= ice
->shaders
.last_vue_map
;
3453 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3455 /* XXX: this should be generated when putting programs in place */
3457 for (int fs_attr
= 0; fs_attr
< VARYING_SLOT_MAX
; fs_attr
++) {
3458 const int input_index
= wm_prog_data
->urb_setup
[fs_attr
];
3459 if (input_index
< 0 || input_index
>= 16)
3462 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
=
3463 &attr_overrides
[input_index
];
3464 int slot
= vue_map
->varying_to_slot
[fs_attr
];
3466 /* Viewport and Layer are stored in the VUE header. We need to override
3467 * them to zero if earlier stages didn't write them, as GL requires that
3468 * they read back as zero when not explicitly set.
3471 case VARYING_SLOT_VIEWPORT
:
3472 case VARYING_SLOT_LAYER
:
3473 attr
->ComponentOverrideX
= true;
3474 attr
->ComponentOverrideW
= true;
3475 attr
->ConstantSource
= CONST_0000
;
3477 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
3478 attr
->ComponentOverrideY
= true;
3479 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
3480 attr
->ComponentOverrideZ
= true;
3483 case VARYING_SLOT_PRIMITIVE_ID
:
3484 /* Override if the previous shader stage didn't write gl_PrimitiveID. */
3486 attr
->ComponentOverrideX
= true;
3487 attr
->ComponentOverrideY
= true;
3488 attr
->ComponentOverrideZ
= true;
3489 attr
->ComponentOverrideW
= true;
3490 attr
->ConstantSource
= PRIM_ID
;
3498 if (sprite_coord_enables
& (1 << input_index
))
3501 /* If there was only a back color written but not front, use back
3502 * as the color instead of undefined.
3504 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
3505 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
3506 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
3507 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
3509 /* Not written by the previous stage - undefined. */
3511 attr
->ComponentOverrideX
= true;
3512 attr
->ComponentOverrideY
= true;
3513 attr
->ComponentOverrideZ
= true;
3514 attr
->ComponentOverrideW
= true;
3515 attr
->ConstantSource
= CONST_0001_FLOAT
;
3519 /* Compute the location of the attribute relative to the read offset,
3520 * which is counted in 256-bit increments (two 128-bit VUE slots).
3522 const int source_attr
= slot
- 2 * urb_read_offset
;
3523 assert(source_attr
>= 0 && source_attr
<= 32);
3524 attr
->SourceAttribute
= source_attr
;
3526 /* If we are doing two-sided color, and the VUE slot following this one
3527 * represents a back-facing color, then we need to instruct the SF unit
3528 * to do back-facing swizzling.
3530 if (cso_rast
->light_twoside
&&
3531 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
3532 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
3533 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
3534 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
)))
3535 attr
->SwizzleSelect
= INPUTATTR_FACING
;
3538 iris_emit_cmd(batch
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
3539 for (int i
= 0; i
< 16; i
++)
3540 sbes
.Attribute
[i
] = attr_overrides
[i
];
3545 iris_calculate_point_sprite_overrides(const struct brw_wm_prog_data
*prog_data
,
3546 const struct iris_rasterizer_state
*cso
)
3548 unsigned overrides
= 0;
3550 if (prog_data
->urb_setup
[VARYING_SLOT_PNTC
] != -1)
3551 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_PNTC
];
3553 for (int i
= 0; i
< 8; i
++) {
3554 if ((cso
->sprite_coord_enable
& (1 << i
)) &&
3555 prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
] != -1)
3556 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
];
3563 iris_emit_sbe(struct iris_batch
*batch
, const struct iris_context
*ice
)
3565 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3566 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
3567 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3568 const struct shader_info
*fs_info
=
3569 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
3571 unsigned urb_read_offset
, urb_read_length
;
3572 iris_compute_sbe_urb_read_interval(fs_info
->inputs_read
,
3573 ice
->shaders
.last_vue_map
,
3574 cso_rast
->light_twoside
,
3575 &urb_read_offset
, &urb_read_length
);
3577 unsigned sprite_coord_overrides
=
3578 iris_calculate_point_sprite_overrides(wm_prog_data
, cso_rast
);
3580 iris_emit_cmd(batch
, GENX(3DSTATE_SBE
), sbe
) {
3581 sbe
.AttributeSwizzleEnable
= true;
3582 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
3583 sbe
.PointSpriteTextureCoordinateOrigin
= cso_rast
->sprite_coord_mode
;
3584 sbe
.VertexURBEntryReadOffset
= urb_read_offset
;
3585 sbe
.VertexURBEntryReadLength
= urb_read_length
;
3586 sbe
.ForceVertexURBEntryReadOffset
= true;
3587 sbe
.ForceVertexURBEntryReadLength
= true;
3588 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
3589 sbe
.PointSpriteTextureCoordinateEnable
= sprite_coord_overrides
;
3591 for (int i
= 0; i
< 32; i
++) {
3592 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
3597 iris_emit_sbe_swiz(batch
, ice
, urb_read_offset
, sprite_coord_overrides
);
3600 /* ------------------------------------------------------------------- */
3603 * Populate VS program key fields based on the current state.
3606 iris_populate_vs_key(const struct iris_context
*ice
,
3607 const struct shader_info
*info
,
3608 gl_shader_stage last_stage
,
3609 struct brw_vs_prog_key
*key
)
3611 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3613 if (info
->clip_distance_array_size
== 0 &&
3614 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)) &&
3615 last_stage
== MESA_SHADER_VERTEX
)
3616 key
->nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
3620 * Populate TCS program key fields based on the current state.
3623 iris_populate_tcs_key(const struct iris_context
*ice
,
3624 struct brw_tcs_prog_key
*key
)
3629 * Populate TES program key fields based on the current state.
3632 iris_populate_tes_key(const struct iris_context
*ice
,
3633 const struct shader_info
*info
,
3634 gl_shader_stage last_stage
,
3635 struct brw_tes_prog_key
*key
)
3637 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3639 if (info
->clip_distance_array_size
== 0 &&
3640 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)) &&
3641 last_stage
== MESA_SHADER_TESS_EVAL
)
3642 key
->nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
3646 * Populate GS program key fields based on the current state.
3649 iris_populate_gs_key(const struct iris_context
*ice
,
3650 const struct shader_info
*info
,
3651 gl_shader_stage last_stage
,
3652 struct brw_gs_prog_key
*key
)
3654 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3656 if (info
->clip_distance_array_size
== 0 &&
3657 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)) &&
3658 last_stage
== MESA_SHADER_GEOMETRY
)
3659 key
->nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
3663 * Populate FS program key fields based on the current state.
3666 iris_populate_fs_key(const struct iris_context
*ice
,
3667 const struct shader_info
*info
,
3668 struct brw_wm_prog_key
*key
)
3670 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
3671 const struct pipe_framebuffer_state
*fb
= &ice
->state
.framebuffer
;
3672 const struct iris_depth_stencil_alpha_state
*zsa
= ice
->state
.cso_zsa
;
3673 const struct iris_rasterizer_state
*rast
= ice
->state
.cso_rast
;
3674 const struct iris_blend_state
*blend
= ice
->state
.cso_blend
;
3676 key
->nr_color_regions
= fb
->nr_cbufs
;
3678 key
->clamp_fragment_color
= rast
->clamp_fragment_color
;
3680 key
->alpha_to_coverage
= blend
->alpha_to_coverage
;
3682 key
->alpha_test_replicate_alpha
= fb
->nr_cbufs
> 1 && zsa
->alpha
.enabled
;
3684 key
->flat_shade
= rast
->flatshade
&&
3685 (info
->inputs_read
& (VARYING_BIT_COL0
| VARYING_BIT_COL1
));
3687 key
->persample_interp
= rast
->force_persample_interp
;
3688 key
->multisample_fbo
= rast
->multisample
&& fb
->samples
> 1;
3690 key
->coherent_fb_fetch
= GEN_GEN
>= 9;
3692 key
->force_dual_color_blend
=
3693 screen
->driconf
.dual_color_blend_by_location
&&
3694 (blend
->blend_enables
& 1) && blend
->dual_color_blending
;
3696 /* TODO: Respect glHint for key->high_quality_derivatives */
3700 iris_populate_cs_key(const struct iris_context
*ice
,
3701 struct brw_cs_prog_key
*key
)
3706 KSP(const struct iris_compiled_shader
*shader
)
3708 struct iris_resource
*res
= (void *) shader
->assembly
.res
;
3709 return iris_bo_offset_from_base_address(res
->bo
) + shader
->assembly
.offset
;
3712 /* Gen11 workaround table #2056 WABTPPrefetchDisable suggests to disable
3713 * prefetching of binding tables in A0 and B0 steppings. XXX: Revisit
3714 * this WA on C0 stepping.
3716 * TODO: Fill out SamplerCount for prefetching?
3719 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix, stage) \
3720 pkt.KernelStartPointer = KSP(shader); \
3721 pkt.BindingTableEntryCount = GEN_GEN == 11 ? 0 : \
3722 shader->bt.size_bytes / 4; \
3723 pkt.FloatingPointMode = prog_data->use_alt_mode; \
3725 pkt.DispatchGRFStartRegisterForURBData = \
3726 prog_data->dispatch_grf_start_reg; \
3727 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
3728 pkt.prefix##URBEntryReadOffset = 0; \
3730 pkt.StatisticsEnable = true; \
3731 pkt.Enable = true; \
3733 if (prog_data->total_scratch) { \
3734 struct iris_bo *bo = \
3735 iris_get_scratch_space(ice, prog_data->total_scratch, stage); \
3736 uint32_t scratch_addr = bo->gtt_offset; \
3737 pkt.PerThreadScratchSpace = ffs(prog_data->total_scratch) - 11; \
3738 pkt.ScratchSpaceBasePointer = rw_bo(NULL, scratch_addr); \
3742 * Encode most of 3DSTATE_VS based on the compiled shader.
3745 iris_store_vs_state(struct iris_context
*ice
,
3746 const struct gen_device_info
*devinfo
,
3747 struct iris_compiled_shader
*shader
)
3749 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3750 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3752 iris_pack_command(GENX(3DSTATE_VS
), shader
->derived_data
, vs
) {
3753 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
, MESA_SHADER_VERTEX
);
3754 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
3755 vs
.SIMD8DispatchEnable
= true;
3756 vs
.UserClipDistanceCullTestEnableBitmask
=
3757 vue_prog_data
->cull_distance_mask
;
3762 * Encode most of 3DSTATE_HS based on the compiled shader.
3765 iris_store_tcs_state(struct iris_context
*ice
,
3766 const struct gen_device_info
*devinfo
,
3767 struct iris_compiled_shader
*shader
)
3769 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3770 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3771 struct brw_tcs_prog_data
*tcs_prog_data
= (void *) prog_data
;
3773 iris_pack_command(GENX(3DSTATE_HS
), shader
->derived_data
, hs
) {
3774 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
, MESA_SHADER_TESS_CTRL
);
3776 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
3777 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
3778 hs
.IncludeVertexHandles
= true;
3781 hs
.DispatchMode
= vue_prog_data
->dispatch_mode
;
3782 hs
.IncludePrimitiveID
= tcs_prog_data
->include_primitive_id
;
3788 * Encode 3DSTATE_TE and most of 3DSTATE_DS based on the compiled shader.
3791 iris_store_tes_state(struct iris_context
*ice
,
3792 const struct gen_device_info
*devinfo
,
3793 struct iris_compiled_shader
*shader
)
3795 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3796 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3797 struct brw_tes_prog_data
*tes_prog_data
= (void *) prog_data
;
3799 uint32_t *te_state
= (void *) shader
->derived_data
;
3800 uint32_t *ds_state
= te_state
+ GENX(3DSTATE_TE_length
);
3802 iris_pack_command(GENX(3DSTATE_TE
), te_state
, te
) {
3803 te
.Partitioning
= tes_prog_data
->partitioning
;
3804 te
.OutputTopology
= tes_prog_data
->output_topology
;
3805 te
.TEDomain
= tes_prog_data
->domain
;
3807 te
.MaximumTessellationFactorOdd
= 63.0;
3808 te
.MaximumTessellationFactorNotOdd
= 64.0;
3811 iris_pack_command(GENX(3DSTATE_DS
), ds_state
, ds
) {
3812 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
, MESA_SHADER_TESS_EVAL
);
3814 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
3815 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
3816 ds
.ComputeWCoordinateEnable
=
3817 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
3819 ds
.UserClipDistanceCullTestEnableBitmask
=
3820 vue_prog_data
->cull_distance_mask
;
3826 * Encode most of 3DSTATE_GS based on the compiled shader.
3829 iris_store_gs_state(struct iris_context
*ice
,
3830 const struct gen_device_info
*devinfo
,
3831 struct iris_compiled_shader
*shader
)
3833 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3834 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3835 struct brw_gs_prog_data
*gs_prog_data
= (void *) prog_data
;
3837 iris_pack_command(GENX(3DSTATE_GS
), shader
->derived_data
, gs
) {
3838 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
, MESA_SHADER_GEOMETRY
);
3840 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
3841 gs
.OutputTopology
= gs_prog_data
->output_topology
;
3842 gs
.ControlDataHeaderSize
=
3843 gs_prog_data
->control_data_header_size_hwords
;
3844 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
3845 gs
.DispatchMode
= DISPATCH_MODE_SIMD8
;
3846 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
3847 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
3848 gs
.ReorderMode
= TRAILING
;
3849 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
3850 gs
.MaximumNumberofThreads
=
3851 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
3852 : (devinfo
->max_gs_threads
- 1);
3854 if (gs_prog_data
->static_vertex_count
!= -1) {
3855 gs
.StaticOutput
= true;
3856 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
3858 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
3860 gs
.UserClipDistanceCullTestEnableBitmask
=
3861 vue_prog_data
->cull_distance_mask
;
3863 const int urb_entry_write_offset
= 1;
3864 const uint32_t urb_entry_output_length
=
3865 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
3866 urb_entry_write_offset
;
3868 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
3869 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
3874 * Encode most of 3DSTATE_PS and 3DSTATE_PS_EXTRA based on the shader.
3877 iris_store_fs_state(struct iris_context
*ice
,
3878 const struct gen_device_info
*devinfo
,
3879 struct iris_compiled_shader
*shader
)
3881 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3882 struct brw_wm_prog_data
*wm_prog_data
= (void *) shader
->prog_data
;
3884 uint32_t *ps_state
= (void *) shader
->derived_data
;
3885 uint32_t *psx_state
= ps_state
+ GENX(3DSTATE_PS_length
);
3887 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
3888 ps
.VectorMaskEnable
= true;
3889 // XXX: WABTPPrefetchDisable, see above, drop at C0
3890 ps
.BindingTableEntryCount
= GEN_GEN
== 11 ? 0 :
3891 shader
->bt
.size_bytes
/ 4;
3892 ps
.FloatingPointMode
= prog_data
->use_alt_mode
;
3893 ps
.MaximumNumberofThreadsPerPSD
= 64 - (GEN_GEN
== 8 ? 2 : 1);
3895 ps
.PushConstantEnable
= prog_data
->ubo_ranges
[0].length
> 0;
3897 /* From the documentation for this packet:
3898 * "If the PS kernel does not need the Position XY Offsets to
3899 * compute a Position Value, then this field should be programmed
3900 * to POSOFFSET_NONE."
3902 * "SW Recommendation: If the PS kernel needs the Position Offsets
3903 * to compute a Position XY value, this field should match Position
3904 * ZW Interpolation Mode to ensure a consistent position.xyzw
3907 * We only require XY sample offsets. So, this recommendation doesn't
3908 * look useful at the moment. We might need this in future.
3910 ps
.PositionXYOffsetSelect
=
3911 wm_prog_data
->uses_pos_offset
? POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
3913 if (prog_data
->total_scratch
) {
3914 struct iris_bo
*bo
=
3915 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
3916 MESA_SHADER_FRAGMENT
);
3917 uint32_t scratch_addr
= bo
->gtt_offset
;
3918 ps
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
3919 ps
.ScratchSpaceBasePointer
= rw_bo(NULL
, scratch_addr
);
3923 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
3924 psx
.PixelShaderValid
= true;
3925 psx
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
3926 psx
.PixelShaderKillsPixel
= wm_prog_data
->uses_kill
;
3927 psx
.AttributeEnable
= wm_prog_data
->num_varying_inputs
!= 0;
3928 psx
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
3929 psx
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
3930 psx
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
3931 psx
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
3934 psx
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
3935 psx
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
3941 * Compute the size of the derived data (shader command packets).
3943 * This must match the data written by the iris_store_xs_state() functions.
3946 iris_store_cs_state(struct iris_context
*ice
,
3947 const struct gen_device_info
*devinfo
,
3948 struct iris_compiled_shader
*shader
)
3950 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3951 struct brw_cs_prog_data
*cs_prog_data
= (void *) shader
->prog_data
;
3952 void *map
= shader
->derived_data
;
3954 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), map
, desc
) {
3955 desc
.KernelStartPointer
= KSP(shader
);
3956 desc
.ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
;
3957 desc
.NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
;
3958 desc
.SharedLocalMemorySize
=
3959 encode_slm_size(GEN_GEN
, prog_data
->total_shared
);
3960 desc
.BarrierEnable
= cs_prog_data
->uses_barrier
;
3961 desc
.CrossThreadConstantDataReadLength
=
3962 cs_prog_data
->push
.cross_thread
.regs
;
3967 iris_derived_program_state_size(enum iris_program_cache_id cache_id
)
3969 assert(cache_id
<= IRIS_CACHE_BLORP
);
3971 static const unsigned dwords
[] = {
3972 [IRIS_CACHE_VS
] = GENX(3DSTATE_VS_length
),
3973 [IRIS_CACHE_TCS
] = GENX(3DSTATE_HS_length
),
3974 [IRIS_CACHE_TES
] = GENX(3DSTATE_TE_length
) + GENX(3DSTATE_DS_length
),
3975 [IRIS_CACHE_GS
] = GENX(3DSTATE_GS_length
),
3977 GENX(3DSTATE_PS_length
) + GENX(3DSTATE_PS_EXTRA_length
),
3978 [IRIS_CACHE_CS
] = GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3979 [IRIS_CACHE_BLORP
] = 0,
3982 return sizeof(uint32_t) * dwords
[cache_id
];
3986 * Create any state packets corresponding to the given shader stage
3987 * (i.e. 3DSTATE_VS) and save them as "derived data" in the shader variant.
3988 * This means that we can look up a program in the in-memory cache and
3989 * get most of the state packet without having to reconstruct it.
3992 iris_store_derived_program_state(struct iris_context
*ice
,
3993 enum iris_program_cache_id cache_id
,
3994 struct iris_compiled_shader
*shader
)
3996 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
3997 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
4001 iris_store_vs_state(ice
, devinfo
, shader
);
4003 case IRIS_CACHE_TCS
:
4004 iris_store_tcs_state(ice
, devinfo
, shader
);
4006 case IRIS_CACHE_TES
:
4007 iris_store_tes_state(ice
, devinfo
, shader
);
4010 iris_store_gs_state(ice
, devinfo
, shader
);
4013 iris_store_fs_state(ice
, devinfo
, shader
);
4016 iris_store_cs_state(ice
, devinfo
, shader
);
4017 case IRIS_CACHE_BLORP
:
4024 /* ------------------------------------------------------------------- */
4026 static const uint32_t push_constant_opcodes
[] = {
4027 [MESA_SHADER_VERTEX
] = 21,
4028 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
4029 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
4030 [MESA_SHADER_GEOMETRY
] = 22,
4031 [MESA_SHADER_FRAGMENT
] = 23,
4032 [MESA_SHADER_COMPUTE
] = 0,
4036 use_null_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
4038 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.unbound_tex
.res
);
4040 iris_use_pinned_bo(batch
, state_bo
, false);
4042 return ice
->state
.unbound_tex
.offset
;
4046 use_null_fb_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
4048 /* If set_framebuffer_state() was never called, fall back to 1x1x1 */
4049 if (!ice
->state
.null_fb
.res
)
4050 return use_null_surface(batch
, ice
);
4052 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.null_fb
.res
);
4054 iris_use_pinned_bo(batch
, state_bo
, false);
4056 return ice
->state
.null_fb
.offset
;
4060 surf_state_offset_for_aux(struct iris_resource
*res
,
4062 enum isl_aux_usage aux_usage
)
4064 return SURFACE_STATE_ALIGNMENT
*
4065 util_bitcount(aux_modes
& ((1 << aux_usage
) - 1));
4070 surf_state_update_clear_value(struct iris_batch
*batch
,
4071 struct iris_resource
*res
,
4072 struct iris_state_ref
*state
,
4074 enum isl_aux_usage aux_usage
)
4076 struct isl_device
*isl_dev
= &batch
->screen
->isl_dev
;
4077 struct iris_bo
*state_bo
= iris_resource_bo(state
->res
);
4078 uint64_t real_offset
= state
->offset
+ IRIS_MEMZONE_BINDER_START
;
4079 uint32_t offset_into_bo
= real_offset
- state_bo
->gtt_offset
;
4080 uint32_t clear_offset
= offset_into_bo
+
4081 isl_dev
->ss
.clear_value_offset
+
4082 surf_state_offset_for_aux(res
, aux_modes
, aux_usage
);
4083 uint32_t *color
= res
->aux
.clear_color
.u32
;
4085 assert(isl_dev
->ss
.clear_value_size
== 16);
4087 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
4088 iris_emit_pipe_control_write(batch
, "update fast clear value (Z)",
4089 PIPE_CONTROL_WRITE_IMMEDIATE
,
4090 state_bo
, clear_offset
, color
[0]);
4092 iris_emit_pipe_control_write(batch
, "update fast clear color (RG__)",
4093 PIPE_CONTROL_WRITE_IMMEDIATE
,
4094 state_bo
, clear_offset
,
4095 (uint64_t) color
[0] |
4096 (uint64_t) color
[1] << 32);
4097 iris_emit_pipe_control_write(batch
, "update fast clear color (__BA)",
4098 PIPE_CONTROL_WRITE_IMMEDIATE
,
4099 state_bo
, clear_offset
+ 8,
4100 (uint64_t) color
[2] |
4101 (uint64_t) color
[3] << 32);
4104 iris_emit_pipe_control_flush(batch
,
4105 "update fast clear: state cache invalidate",
4106 PIPE_CONTROL_FLUSH_ENABLE
|
4107 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
4112 update_clear_value(struct iris_context
*ice
,
4113 struct iris_batch
*batch
,
4114 struct iris_resource
*res
,
4115 struct iris_state_ref
*state
,
4116 unsigned all_aux_modes
,
4117 struct isl_view
*view
)
4119 UNUSED
struct isl_device
*isl_dev
= &batch
->screen
->isl_dev
;
4120 UNUSED
unsigned aux_modes
= all_aux_modes
;
4122 /* We only need to update the clear color in the surface state for gen8 and
4123 * gen9. Newer gens can read it directly from the clear color state buffer.
4126 /* Skip updating the ISL_AUX_USAGE_NONE surface state */
4127 aux_modes
&= ~(1 << ISL_AUX_USAGE_NONE
);
4130 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
4132 surf_state_update_clear_value(batch
, res
, state
, all_aux_modes
,
4136 pipe_resource_reference(&state
->res
, NULL
);
4138 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
4139 state
, all_aux_modes
);
4141 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
4142 fill_surface_state(isl_dev
, map
, res
, &res
->surf
, view
, aux_usage
, 0, 0);
4143 map
+= SURFACE_STATE_ALIGNMENT
;
4149 * Add a surface to the validation list, as well as the buffer containing
4150 * the corresponding SURFACE_STATE.
4152 * Returns the binding table entry (offset to SURFACE_STATE).
4155 use_surface(struct iris_context
*ice
,
4156 struct iris_batch
*batch
,
4157 struct pipe_surface
*p_surf
,
4159 enum isl_aux_usage aux_usage
,
4160 bool is_read_surface
)
4162 struct iris_surface
*surf
= (void *) p_surf
;
4163 struct iris_resource
*res
= (void *) p_surf
->texture
;
4164 uint32_t offset
= 0;
4166 iris_use_pinned_bo(batch
, iris_resource_bo(p_surf
->texture
), writeable
);
4167 if (GEN_GEN
== 8 && is_read_surface
) {
4168 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state_read
.res
), false);
4170 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state
.res
), false);
4174 iris_use_pinned_bo(batch
, res
->aux
.bo
, writeable
);
4175 if (res
->aux
.clear_color_bo
)
4176 iris_use_pinned_bo(batch
, res
->aux
.clear_color_bo
, false);
4178 if (memcmp(&res
->aux
.clear_color
, &surf
->clear_color
,
4179 sizeof(surf
->clear_color
)) != 0) {
4180 update_clear_value(ice
, batch
, res
, &surf
->surface_state
,
4181 res
->aux
.possible_usages
, &surf
->view
);
4183 update_clear_value(ice
, batch
, res
, &surf
->surface_state_read
,
4184 res
->aux
.possible_usages
, &surf
->read_view
);
4186 surf
->clear_color
= res
->aux
.clear_color
;
4190 offset
= (GEN_GEN
== 8 && is_read_surface
) ? surf
->surface_state_read
.offset
4191 : surf
->surface_state
.offset
;
4194 surf_state_offset_for_aux(res
, res
->aux
.possible_usages
, aux_usage
);
4198 use_sampler_view(struct iris_context
*ice
,
4199 struct iris_batch
*batch
,
4200 struct iris_sampler_view
*isv
)
4203 enum isl_aux_usage aux_usage
=
4204 iris_resource_texture_aux_usage(ice
, isv
->res
, isv
->view
.format
, 0);
4206 iris_use_pinned_bo(batch
, isv
->res
->bo
, false);
4207 iris_use_pinned_bo(batch
, iris_resource_bo(isv
->surface_state
.res
), false);
4209 if (isv
->res
->aux
.bo
) {
4210 iris_use_pinned_bo(batch
, isv
->res
->aux
.bo
, false);
4211 if (isv
->res
->aux
.clear_color_bo
)
4212 iris_use_pinned_bo(batch
, isv
->res
->aux
.clear_color_bo
, false);
4213 if (memcmp(&isv
->res
->aux
.clear_color
, &isv
->clear_color
,
4214 sizeof(isv
->clear_color
)) != 0) {
4215 update_clear_value(ice
, batch
, isv
->res
, &isv
->surface_state
,
4216 isv
->res
->aux
.sampler_usages
, &isv
->view
);
4217 isv
->clear_color
= isv
->res
->aux
.clear_color
;
4221 return isv
->surface_state
.offset
+
4222 surf_state_offset_for_aux(isv
->res
, isv
->res
->aux
.sampler_usages
,
4227 use_ubo_ssbo(struct iris_batch
*batch
,
4228 struct iris_context
*ice
,
4229 struct pipe_shader_buffer
*buf
,
4230 struct iris_state_ref
*surf_state
,
4233 if (!buf
->buffer
|| !surf_state
->res
)
4234 return use_null_surface(batch
, ice
);
4236 iris_use_pinned_bo(batch
, iris_resource_bo(buf
->buffer
), writable
);
4237 iris_use_pinned_bo(batch
, iris_resource_bo(surf_state
->res
), false);
4239 return surf_state
->offset
;
4243 use_image(struct iris_batch
*batch
, struct iris_context
*ice
,
4244 struct iris_shader_state
*shs
, int i
)
4246 struct iris_image_view
*iv
= &shs
->image
[i
];
4247 struct iris_resource
*res
= (void *) iv
->base
.resource
;
4250 return use_null_surface(batch
, ice
);
4252 bool write
= iv
->base
.shader_access
& PIPE_IMAGE_ACCESS_WRITE
;
4254 iris_use_pinned_bo(batch
, res
->bo
, write
);
4255 iris_use_pinned_bo(batch
, iris_resource_bo(iv
->surface_state
.res
), false);
4258 iris_use_pinned_bo(batch
, res
->aux
.bo
, write
);
4260 return iv
->surface_state
.offset
;
4263 #define push_bt_entry(addr) \
4264 assert(addr >= binder_addr); \
4265 assert(s < shader->bt.size_bytes / sizeof(uint32_t)); \
4266 if (!pin_only) bt_map[s++] = (addr) - binder_addr;
4268 #define bt_assert(section) \
4269 if (!pin_only && shader->bt.used_mask[section] != 0) \
4270 assert(shader->bt.offsets[section] == s);
4273 * Populate the binding table for a given shader stage.
4275 * This fills out the table of pointers to surfaces required by the shader,
4276 * and also adds those buffers to the validation list so the kernel can make
4277 * resident before running our batch.
4280 iris_populate_binding_table(struct iris_context
*ice
,
4281 struct iris_batch
*batch
,
4282 gl_shader_stage stage
,
4285 const struct iris_binder
*binder
= &ice
->state
.binder
;
4286 struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[stage
];
4287 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4291 struct iris_binding_table
*bt
= &shader
->bt
;
4292 UNUSED
struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4293 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4294 uint32_t binder_addr
= binder
->bo
->gtt_offset
;
4296 uint32_t *bt_map
= binder
->map
+ binder
->bt_offset
[stage
];
4299 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
4301 /* TCS passthrough doesn't need a binding table. */
4302 assert(stage
== MESA_SHADER_TESS_CTRL
);
4306 if (stage
== MESA_SHADER_COMPUTE
&&
4307 shader
->bt
.used_mask
[IRIS_SURFACE_GROUP_CS_WORK_GROUPS
]) {
4308 /* surface for gl_NumWorkGroups */
4309 struct iris_state_ref
*grid_data
= &ice
->state
.grid_size
;
4310 struct iris_state_ref
*grid_state
= &ice
->state
.grid_surf_state
;
4311 iris_use_pinned_bo(batch
, iris_resource_bo(grid_data
->res
), false);
4312 iris_use_pinned_bo(batch
, iris_resource_bo(grid_state
->res
), false);
4313 push_bt_entry(grid_state
->offset
);
4316 if (stage
== MESA_SHADER_FRAGMENT
) {
4317 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4318 /* Note that cso_fb->nr_cbufs == fs_key->nr_color_regions. */
4319 if (cso_fb
->nr_cbufs
) {
4320 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
4322 if (cso_fb
->cbufs
[i
]) {
4323 addr
= use_surface(ice
, batch
, cso_fb
->cbufs
[i
], true,
4324 ice
->state
.draw_aux_usage
[i
], false);
4326 addr
= use_null_fb_surface(batch
, ice
);
4328 push_bt_entry(addr
);
4330 } else if (GEN_GEN
< 11) {
4331 uint32_t addr
= use_null_fb_surface(batch
, ice
);
4332 push_bt_entry(addr
);
4336 #define foreach_surface_used(index, group) \
4338 for (int index = 0; index < bt->sizes[group]; index++) \
4339 if (iris_group_index_to_bti(bt, group, index) != \
4340 IRIS_SURFACE_NOT_USED)
4342 foreach_surface_used(i
, IRIS_SURFACE_GROUP_RENDER_TARGET_READ
) {
4343 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4345 if (cso_fb
->cbufs
[i
]) {
4346 addr
= use_surface(ice
, batch
, cso_fb
->cbufs
[i
],
4347 true, ice
->state
.draw_aux_usage
[i
], true);
4348 push_bt_entry(addr
);
4352 foreach_surface_used(i
, IRIS_SURFACE_GROUP_TEXTURE
) {
4353 struct iris_sampler_view
*view
= shs
->textures
[i
];
4354 uint32_t addr
= view
? use_sampler_view(ice
, batch
, view
)
4355 : use_null_surface(batch
, ice
);
4356 push_bt_entry(addr
);
4359 foreach_surface_used(i
, IRIS_SURFACE_GROUP_IMAGE
) {
4360 uint32_t addr
= use_image(batch
, ice
, shs
, i
);
4361 push_bt_entry(addr
);
4364 foreach_surface_used(i
, IRIS_SURFACE_GROUP_UBO
) {
4367 if (i
== bt
->sizes
[IRIS_SURFACE_GROUP_UBO
] - 1) {
4368 if (ish
->const_data
) {
4369 iris_use_pinned_bo(batch
, iris_resource_bo(ish
->const_data
), false);
4370 iris_use_pinned_bo(batch
, iris_resource_bo(ish
->const_data_state
.res
),
4372 addr
= ish
->const_data_state
.offset
;
4374 /* This can only happen with INTEL_DISABLE_COMPACT_BINDING_TABLE=1. */
4375 addr
= use_null_surface(batch
, ice
);
4378 addr
= use_ubo_ssbo(batch
, ice
, &shs
->constbuf
[i
],
4379 &shs
->constbuf_surf_state
[i
], false);
4382 push_bt_entry(addr
);
4385 foreach_surface_used(i
, IRIS_SURFACE_GROUP_SSBO
) {
4387 use_ubo_ssbo(batch
, ice
, &shs
->ssbo
[i
], &shs
->ssbo_surf_state
[i
],
4388 shs
->writable_ssbos
& (1u << i
));
4389 push_bt_entry(addr
);
4393 /* XXX: YUV surfaces not implemented yet */
4394 bt_assert(plane_start
[1], ...);
4395 bt_assert(plane_start
[2], ...);
4400 iris_use_optional_res(struct iris_batch
*batch
,
4401 struct pipe_resource
*res
,
4405 struct iris_bo
*bo
= iris_resource_bo(res
);
4406 iris_use_pinned_bo(batch
, bo
, writeable
);
4411 pin_depth_and_stencil_buffers(struct iris_batch
*batch
,
4412 struct pipe_surface
*zsbuf
,
4413 struct iris_depth_stencil_alpha_state
*cso_zsa
)
4418 struct iris_resource
*zres
, *sres
;
4419 iris_get_depth_stencil_resources(zsbuf
->texture
, &zres
, &sres
);
4422 iris_use_pinned_bo(batch
, zres
->bo
, cso_zsa
->depth_writes_enabled
);
4424 iris_use_pinned_bo(batch
, zres
->aux
.bo
,
4425 cso_zsa
->depth_writes_enabled
);
4430 iris_use_pinned_bo(batch
, sres
->bo
, cso_zsa
->stencil_writes_enabled
);
4434 /* ------------------------------------------------------------------- */
4437 * Pin any BOs which were installed by a previous batch, and restored
4438 * via the hardware logical context mechanism.
4440 * We don't need to re-emit all state every batch - the hardware context
4441 * mechanism will save and restore it for us. This includes pointers to
4442 * various BOs...which won't exist unless we ask the kernel to pin them
4443 * by adding them to the validation list.
4445 * We can skip buffers if we've re-emitted those packets, as we're
4446 * overwriting those stale pointers with new ones, and don't actually
4447 * refer to the old BOs.
4450 iris_restore_render_saved_bos(struct iris_context
*ice
,
4451 struct iris_batch
*batch
,
4452 const struct pipe_draw_info
*draw
)
4454 struct iris_genx_state
*genx
= ice
->state
.genx
;
4456 const uint64_t clean
= ~ice
->state
.dirty
;
4458 if (clean
& IRIS_DIRTY_CC_VIEWPORT
) {
4459 iris_use_optional_res(batch
, ice
->state
.last_res
.cc_vp
, false);
4462 if (clean
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
4463 iris_use_optional_res(batch
, ice
->state
.last_res
.sf_cl_vp
, false);
4466 if (clean
& IRIS_DIRTY_BLEND_STATE
) {
4467 iris_use_optional_res(batch
, ice
->state
.last_res
.blend
, false);
4470 if (clean
& IRIS_DIRTY_COLOR_CALC_STATE
) {
4471 iris_use_optional_res(batch
, ice
->state
.last_res
.color_calc
, false);
4474 if (clean
& IRIS_DIRTY_SCISSOR_RECT
) {
4475 iris_use_optional_res(batch
, ice
->state
.last_res
.scissor
, false);
4478 if (ice
->state
.streamout_active
&& (clean
& IRIS_DIRTY_SO_BUFFERS
)) {
4479 for (int i
= 0; i
< 4; i
++) {
4480 struct iris_stream_output_target
*tgt
=
4481 (void *) ice
->state
.so_target
[i
];
4483 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
4485 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
4491 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4492 if (!(clean
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
4495 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4496 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4501 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4503 for (int i
= 0; i
< 4; i
++) {
4504 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4506 if (range
->length
== 0)
4509 /* Range block is a binding table index, map back to UBO index. */
4510 unsigned block_index
= iris_bti_to_group_index(
4511 &shader
->bt
, IRIS_SURFACE_GROUP_UBO
, range
->block
);
4512 assert(block_index
!= IRIS_SURFACE_NOT_USED
);
4514 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[block_index
];
4515 struct iris_resource
*res
= (void *) cbuf
->buffer
;
4518 iris_use_pinned_bo(batch
, res
->bo
, false);
4520 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
4524 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4525 if (clean
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4526 /* Re-pin any buffers referred to by the binding table. */
4527 iris_populate_binding_table(ice
, batch
, stage
, true);
4531 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4532 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4533 struct pipe_resource
*res
= shs
->sampler_table
.res
;
4535 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4538 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4539 if (clean
& (IRIS_DIRTY_VS
<< stage
)) {
4540 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4543 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
4544 iris_use_pinned_bo(batch
, bo
, false);
4546 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4548 if (prog_data
->total_scratch
> 0) {
4549 struct iris_bo
*bo
=
4550 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
4551 iris_use_pinned_bo(batch
, bo
, true);
4557 if ((clean
& IRIS_DIRTY_DEPTH_BUFFER
) &&
4558 (clean
& IRIS_DIRTY_WM_DEPTH_STENCIL
)) {
4559 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4560 pin_depth_and_stencil_buffers(batch
, cso_fb
->zsbuf
, ice
->state
.cso_zsa
);
4563 iris_use_optional_res(batch
, ice
->state
.last_res
.index_buffer
, false);
4565 if (clean
& IRIS_DIRTY_VERTEX_BUFFERS
) {
4566 uint64_t bound
= ice
->state
.bound_vertex_buffers
;
4568 const int i
= u_bit_scan64(&bound
);
4569 struct pipe_resource
*res
= genx
->vertex_buffers
[i
].resource
;
4570 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4576 iris_restore_compute_saved_bos(struct iris_context
*ice
,
4577 struct iris_batch
*batch
,
4578 const struct pipe_grid_info
*grid
)
4580 const uint64_t clean
= ~ice
->state
.dirty
;
4582 const int stage
= MESA_SHADER_COMPUTE
;
4583 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4585 if (clean
& IRIS_DIRTY_BINDINGS_CS
) {
4586 /* Re-pin any buffers referred to by the binding table. */
4587 iris_populate_binding_table(ice
, batch
, stage
, true);
4590 struct pipe_resource
*sampler_res
= shs
->sampler_table
.res
;
4592 iris_use_pinned_bo(batch
, iris_resource_bo(sampler_res
), false);
4594 if ((clean
& IRIS_DIRTY_SAMPLER_STATES_CS
) &&
4595 (clean
& IRIS_DIRTY_BINDINGS_CS
) &&
4596 (clean
& IRIS_DIRTY_CONSTANTS_CS
) &&
4597 (clean
& IRIS_DIRTY_CS
)) {
4598 iris_use_optional_res(batch
, ice
->state
.last_res
.cs_desc
, false);
4601 if (clean
& IRIS_DIRTY_CS
) {
4602 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4605 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
4606 iris_use_pinned_bo(batch
, bo
, false);
4608 struct iris_bo
*curbe_bo
=
4609 iris_resource_bo(ice
->state
.last_res
.cs_thread_ids
);
4610 iris_use_pinned_bo(batch
, curbe_bo
, false);
4612 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4614 if (prog_data
->total_scratch
> 0) {
4615 struct iris_bo
*bo
=
4616 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
4617 iris_use_pinned_bo(batch
, bo
, true);
4624 * Possibly emit STATE_BASE_ADDRESS to update Surface State Base Address.
4627 iris_update_surface_base_address(struct iris_batch
*batch
,
4628 struct iris_binder
*binder
)
4630 if (batch
->last_surface_base_address
== binder
->bo
->gtt_offset
)
4633 flush_before_state_base_change(batch
);
4635 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
4636 sba
.SurfaceStateBaseAddressModifyEnable
= true;
4637 sba
.SurfaceStateBaseAddress
= ro_bo(binder
->bo
, 0);
4639 /* The hardware appears to pay attention to the MOCS fields even
4640 * if you don't set the "Address Modify Enable" bit for the base.
4642 sba
.GeneralStateMOCS
= MOCS_WB
;
4643 sba
.StatelessDataPortAccessMOCS
= MOCS_WB
;
4644 sba
.DynamicStateMOCS
= MOCS_WB
;
4645 sba
.IndirectObjectMOCS
= MOCS_WB
;
4646 sba
.InstructionMOCS
= MOCS_WB
;
4647 sba
.SurfaceStateMOCS
= MOCS_WB
;
4649 sba
.BindlessSurfaceStateMOCS
= MOCS_WB
;
4653 flush_after_state_base_change(batch
);
4655 batch
->last_surface_base_address
= binder
->bo
->gtt_offset
;
4659 iris_viewport_zmin_zmax(const struct pipe_viewport_state
*vp
, bool halfz
,
4660 bool window_space_position
, float *zmin
, float *zmax
)
4662 if (window_space_position
) {
4667 util_viewport_zmin_zmax(vp
, halfz
, zmin
, zmax
);
4671 iris_upload_dirty_render_state(struct iris_context
*ice
,
4672 struct iris_batch
*batch
,
4673 const struct pipe_draw_info
*draw
)
4675 const uint64_t dirty
= ice
->state
.dirty
;
4677 if (!(dirty
& IRIS_ALL_DIRTY_FOR_RENDER
))
4680 struct iris_genx_state
*genx
= ice
->state
.genx
;
4681 struct iris_binder
*binder
= &ice
->state
.binder
;
4682 struct brw_wm_prog_data
*wm_prog_data
= (void *)
4683 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
4685 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
4686 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4687 uint32_t cc_vp_address
;
4689 /* XXX: could avoid streaming for depth_clip [0,1] case. */
4690 uint32_t *cc_vp_map
=
4691 stream_state(batch
, ice
->state
.dynamic_uploader
,
4692 &ice
->state
.last_res
.cc_vp
,
4693 4 * ice
->state
.num_viewports
*
4694 GENX(CC_VIEWPORT_length
), 32, &cc_vp_address
);
4695 for (int i
= 0; i
< ice
->state
.num_viewports
; i
++) {
4697 iris_viewport_zmin_zmax(&ice
->state
.viewports
[i
], cso_rast
->clip_halfz
,
4698 ice
->state
.window_space_position
,
4700 if (cso_rast
->depth_clip_near
)
4702 if (cso_rast
->depth_clip_far
)
4705 iris_pack_state(GENX(CC_VIEWPORT
), cc_vp_map
, ccv
) {
4706 ccv
.MinimumDepth
= zmin
;
4707 ccv
.MaximumDepth
= zmax
;
4710 cc_vp_map
+= GENX(CC_VIEWPORT_length
);
4713 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
4714 ptr
.CCViewportPointer
= cc_vp_address
;
4718 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
4719 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4720 uint32_t sf_cl_vp_address
;
4722 stream_state(batch
, ice
->state
.dynamic_uploader
,
4723 &ice
->state
.last_res
.sf_cl_vp
,
4724 4 * ice
->state
.num_viewports
*
4725 GENX(SF_CLIP_VIEWPORT_length
), 64, &sf_cl_vp_address
);
4727 for (unsigned i
= 0; i
< ice
->state
.num_viewports
; i
++) {
4728 const struct pipe_viewport_state
*state
= &ice
->state
.viewports
[i
];
4729 float gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
4731 float vp_xmin
= viewport_extent(state
, 0, -1.0f
);
4732 float vp_xmax
= viewport_extent(state
, 0, 1.0f
);
4733 float vp_ymin
= viewport_extent(state
, 1, -1.0f
);
4734 float vp_ymax
= viewport_extent(state
, 1, 1.0f
);
4736 gen_calculate_guardband_size(cso_fb
->width
, cso_fb
->height
,
4737 state
->scale
[0], state
->scale
[1],
4738 state
->translate
[0], state
->translate
[1],
4739 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
4741 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), vp_map
, vp
) {
4742 vp
.ViewportMatrixElementm00
= state
->scale
[0];
4743 vp
.ViewportMatrixElementm11
= state
->scale
[1];
4744 vp
.ViewportMatrixElementm22
= state
->scale
[2];
4745 vp
.ViewportMatrixElementm30
= state
->translate
[0];
4746 vp
.ViewportMatrixElementm31
= state
->translate
[1];
4747 vp
.ViewportMatrixElementm32
= state
->translate
[2];
4748 vp
.XMinClipGuardband
= gb_xmin
;
4749 vp
.XMaxClipGuardband
= gb_xmax
;
4750 vp
.YMinClipGuardband
= gb_ymin
;
4751 vp
.YMaxClipGuardband
= gb_ymax
;
4752 vp
.XMinViewPort
= MAX2(vp_xmin
, 0);
4753 vp
.XMaxViewPort
= MIN2(vp_xmax
, cso_fb
->width
) - 1;
4754 vp
.YMinViewPort
= MAX2(vp_ymin
, 0);
4755 vp
.YMaxViewPort
= MIN2(vp_ymax
, cso_fb
->height
) - 1;
4758 vp_map
+= GENX(SF_CLIP_VIEWPORT_length
);
4761 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
4762 ptr
.SFClipViewportPointer
= sf_cl_vp_address
;
4766 if (dirty
& IRIS_DIRTY_URB
) {
4769 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
4770 if (!ice
->shaders
.prog
[i
]) {
4773 struct brw_vue_prog_data
*vue_prog_data
=
4774 (void *) ice
->shaders
.prog
[i
]->prog_data
;
4775 size
[i
] = vue_prog_data
->urb_entry_size
;
4777 assert(size
[i
] != 0);
4780 genX(emit_urb_setup
)(ice
, batch
, size
,
4781 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
] != NULL
,
4782 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] != NULL
);
4785 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
4786 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
4787 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4788 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
4789 const int header_dwords
= GENX(BLEND_STATE_length
);
4791 /* Always write at least one BLEND_STATE - the final RT message will
4792 * reference BLEND_STATE[0] even if there aren't color writes. There
4793 * may still be alpha testing, computed depth, and so on.
4795 const int rt_dwords
=
4796 MAX2(cso_fb
->nr_cbufs
, 1) * GENX(BLEND_STATE_ENTRY_length
);
4798 uint32_t blend_offset
;
4799 uint32_t *blend_map
=
4800 stream_state(batch
, ice
->state
.dynamic_uploader
,
4801 &ice
->state
.last_res
.blend
,
4802 4 * (header_dwords
+ rt_dwords
), 64, &blend_offset
);
4804 uint32_t blend_state_header
;
4805 iris_pack_state(GENX(BLEND_STATE
), &blend_state_header
, bs
) {
4806 bs
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
4807 bs
.AlphaTestFunction
= translate_compare_func(cso_zsa
->alpha
.func
);
4810 blend_map
[0] = blend_state_header
| cso_blend
->blend_state
[0];
4811 memcpy(&blend_map
[1], &cso_blend
->blend_state
[1], 4 * rt_dwords
);
4813 iris_emit_cmd(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
4814 ptr
.BlendStatePointer
= blend_offset
;
4815 ptr
.BlendStatePointerValid
= true;
4819 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
4820 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
4822 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
4826 stream_state(batch
, ice
->state
.dynamic_uploader
,
4827 &ice
->state
.last_res
.color_calc
,
4828 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
4830 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
4831 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
4832 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
4833 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
4834 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
4835 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
4836 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
4838 cc
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
4839 cc
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
4842 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
4843 ptr
.ColorCalcStatePointer
= cc_offset
;
4844 ptr
.ColorCalcStatePointerValid
= true;
4848 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4849 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
4852 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4853 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4858 if (shs
->sysvals_need_upload
)
4859 upload_sysvals(ice
, stage
);
4861 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4863 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
4864 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
4866 /* The Skylake PRM contains the following restriction:
4868 * "The driver must ensure The following case does not occur
4869 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
4870 * buffer 3 read length equal to zero committed followed by a
4871 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
4874 * To avoid this, we program the buffers in the highest slots.
4875 * This way, slot 0 is only used if slot 3 is also used.
4879 for (int i
= 3; i
>= 0; i
--) {
4880 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4882 if (range
->length
== 0)
4885 /* Range block is a binding table index, map back to UBO index. */
4886 unsigned block_index
= iris_bti_to_group_index(
4887 &shader
->bt
, IRIS_SURFACE_GROUP_UBO
, range
->block
);
4888 assert(block_index
!= IRIS_SURFACE_NOT_USED
);
4890 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[block_index
];
4891 struct iris_resource
*res
= (void *) cbuf
->buffer
;
4893 assert(cbuf
->buffer_offset
% 32 == 0);
4895 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
4896 pkt
.ConstantBody
.Buffer
[n
] =
4897 res
? ro_bo(res
->bo
, range
->start
* 32 + cbuf
->buffer_offset
)
4898 : ro_bo(batch
->screen
->workaround_bo
, 0);
4905 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4906 /* Gen9 requires 3DSTATE_BINDING_TABLE_POINTERS_XS to be re-emitted
4907 * in order to commit constants. TODO: Investigate "Disable Gather
4908 * at Set Shader" to go back to legacy mode...
4910 if (dirty
& ((IRIS_DIRTY_BINDINGS_VS
|
4911 (GEN_GEN
== 9 ? IRIS_DIRTY_CONSTANTS_VS
: 0)) << stage
)) {
4912 iris_emit_cmd(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), ptr
) {
4913 ptr
._3DCommandSubOpcode
= 38 + stage
;
4914 ptr
.PointertoVSBindingTable
= binder
->bt_offset
[stage
];
4919 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4920 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4921 iris_populate_binding_table(ice
, batch
, stage
, false);
4925 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4926 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)) ||
4927 !ice
->shaders
.prog
[stage
])
4930 iris_upload_sampler_states(ice
, stage
);
4932 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4933 struct pipe_resource
*res
= shs
->sampler_table
.res
;
4935 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4937 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
4938 ptr
._3DCommandSubOpcode
= 43 + stage
;
4939 ptr
.PointertoVSSamplerState
= shs
->sampler_table
.offset
;
4943 if (ice
->state
.need_border_colors
)
4944 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
4946 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
4947 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
4949 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
4950 if (ice
->state
.framebuffer
.samples
> 0)
4951 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
4955 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
4956 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
4957 ms
.SampleMask
= ice
->state
.sample_mask
;
4961 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4962 if (!(dirty
& (IRIS_DIRTY_VS
<< stage
)))
4965 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4968 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4969 struct iris_resource
*cache
= (void *) shader
->assembly
.res
;
4970 iris_use_pinned_bo(batch
, cache
->bo
, false);
4972 if (prog_data
->total_scratch
> 0) {
4973 struct iris_bo
*bo
=
4974 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
4975 iris_use_pinned_bo(batch
, bo
, true);
4978 if (stage
== MESA_SHADER_FRAGMENT
) {
4979 UNUSED
struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4980 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4982 uint32_t ps_state
[GENX(3DSTATE_PS_length
)] = {0};
4983 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
4984 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
4985 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
4986 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
4988 /* The docs for 3DSTATE_PS::32 Pixel Dispatch Enable say:
4990 * "When NUM_MULTISAMPLES = 16 or FORCE_SAMPLE_COUNT = 16,
4991 * SIMD32 Dispatch must not be enabled for PER_PIXEL dispatch
4994 * 16x MSAA only exists on Gen9+, so we can skip this on Gen8.
4996 if (GEN_GEN
>= 9 && cso_fb
->samples
== 16 &&
4997 !wm_prog_data
->persample_dispatch
) {
4998 assert(ps
._8PixelDispatchEnable
|| ps
._16PixelDispatchEnable
);
4999 ps
._32PixelDispatchEnable
= false;
5002 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
5003 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
5004 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
5005 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
5006 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
5007 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
5009 ps
.KernelStartPointer0
= KSP(shader
) +
5010 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
5011 ps
.KernelStartPointer1
= KSP(shader
) +
5012 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
5013 ps
.KernelStartPointer2
= KSP(shader
) +
5014 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
5017 uint32_t psx_state
[GENX(3DSTATE_PS_EXTRA_length
)] = {0};
5018 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
5020 if (!wm_prog_data
->uses_sample_mask
)
5021 psx
.InputCoverageMaskState
= ICMS_NONE
;
5022 else if (wm_prog_data
->post_depth_coverage
)
5023 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
5024 else if (wm_prog_data
->inner_coverage
&&
5025 cso
->conservative_rasterization
)
5026 psx
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
5028 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
5030 psx
.PixelShaderUsesInputCoverageMask
=
5031 wm_prog_data
->uses_sample_mask
;
5035 uint32_t *shader_ps
= (uint32_t *) shader
->derived_data
;
5036 uint32_t *shader_psx
= shader_ps
+ GENX(3DSTATE_PS_length
);
5037 iris_emit_merge(batch
, shader_ps
, ps_state
,
5038 GENX(3DSTATE_PS_length
));
5039 iris_emit_merge(batch
, shader_psx
, psx_state
,
5040 GENX(3DSTATE_PS_EXTRA_length
));
5042 iris_batch_emit(batch
, shader
->derived_data
,
5043 iris_derived_program_state_size(stage
));
5046 if (stage
== MESA_SHADER_TESS_EVAL
) {
5047 iris_emit_cmd(batch
, GENX(3DSTATE_HS
), hs
);
5048 iris_emit_cmd(batch
, GENX(3DSTATE_TE
), te
);
5049 iris_emit_cmd(batch
, GENX(3DSTATE_DS
), ds
);
5050 } else if (stage
== MESA_SHADER_GEOMETRY
) {
5051 iris_emit_cmd(batch
, GENX(3DSTATE_GS
), gs
);
5056 if (ice
->state
.streamout_active
) {
5057 if (dirty
& IRIS_DIRTY_SO_BUFFERS
) {
5058 iris_batch_emit(batch
, genx
->so_buffers
,
5059 4 * 4 * GENX(3DSTATE_SO_BUFFER_length
));
5060 for (int i
= 0; i
< 4; i
++) {
5061 struct iris_stream_output_target
*tgt
=
5062 (void *) ice
->state
.so_target
[i
];
5065 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
5067 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
5073 if ((dirty
& IRIS_DIRTY_SO_DECL_LIST
) && ice
->state
.streamout
) {
5074 uint32_t *decl_list
=
5075 ice
->state
.streamout
+ GENX(3DSTATE_STREAMOUT_length
);
5076 iris_batch_emit(batch
, decl_list
, 4 * ((decl_list
[0] & 0xff) + 2));
5079 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
5080 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
5082 uint32_t dynamic_sol
[GENX(3DSTATE_STREAMOUT_length
)];
5083 iris_pack_command(GENX(3DSTATE_STREAMOUT
), dynamic_sol
, sol
) {
5084 sol
.SOFunctionEnable
= true;
5085 sol
.SOStatisticsEnable
= true;
5087 sol
.RenderingDisable
= cso_rast
->rasterizer_discard
&&
5088 !ice
->state
.prims_generated_query_active
;
5089 sol
.ReorderMode
= cso_rast
->flatshade_first
? LEADING
: TRAILING
;
5092 assert(ice
->state
.streamout
);
5094 iris_emit_merge(batch
, ice
->state
.streamout
, dynamic_sol
,
5095 GENX(3DSTATE_STREAMOUT_length
));
5098 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
5099 iris_emit_cmd(batch
, GENX(3DSTATE_STREAMOUT
), sol
);
5103 if (dirty
& IRIS_DIRTY_CLIP
) {
5104 struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
5105 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5107 bool gs_or_tes
= ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] ||
5108 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
];
5109 bool points_or_lines
= cso_rast
->fill_mode_point_or_line
||
5110 (gs_or_tes
? ice
->shaders
.output_topology_is_points_or_lines
5111 : ice
->state
.prim_is_points_or_lines
);
5113 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
5114 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
5115 cl
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
5116 if (cso_rast
->rasterizer_discard
)
5117 cl
.ClipMode
= CLIPMODE_REJECT_ALL
;
5118 else if (ice
->state
.window_space_position
)
5119 cl
.ClipMode
= CLIPMODE_ACCEPT_ALL
;
5121 cl
.ClipMode
= CLIPMODE_NORMAL
;
5123 cl
.PerspectiveDivideDisable
= ice
->state
.window_space_position
;
5124 cl
.ViewportXYClipTestEnable
= !points_or_lines
;
5126 if (wm_prog_data
->barycentric_interp_modes
&
5127 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
5128 cl
.NonPerspectiveBarycentricEnable
= true;
5130 cl
.ForceZeroRTAIndexEnable
= cso_fb
->layers
== 0;
5131 cl
.MaximumVPIndex
= ice
->state
.num_viewports
- 1;
5133 iris_emit_merge(batch
, cso_rast
->clip
, dynamic_clip
,
5134 ARRAY_SIZE(cso_rast
->clip
));
5137 if (dirty
& IRIS_DIRTY_RASTER
) {
5138 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
5139 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
5141 uint32_t dynamic_sf
[GENX(3DSTATE_SF_length
)];
5142 iris_pack_command(GENX(3DSTATE_SF
), &dynamic_sf
, sf
) {
5143 sf
.ViewportTransformEnable
= !ice
->state
.window_space_position
;
5145 iris_emit_merge(batch
, cso
->sf
, dynamic_sf
,
5146 ARRAY_SIZE(dynamic_sf
));
5149 if (dirty
& IRIS_DIRTY_WM
) {
5150 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
5151 uint32_t dynamic_wm
[GENX(3DSTATE_WM_length
)];
5153 iris_pack_command(GENX(3DSTATE_WM
), &dynamic_wm
, wm
) {
5154 wm
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
5156 wm
.BarycentricInterpolationMode
=
5157 wm_prog_data
->barycentric_interp_modes
;
5159 if (wm_prog_data
->early_fragment_tests
)
5160 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
5161 else if (wm_prog_data
->has_side_effects
)
5162 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
5164 /* We could skip this bit if color writes are enabled. */
5165 if (wm_prog_data
->has_side_effects
|| wm_prog_data
->uses_kill
)
5166 wm
.ForceThreadDispatchEnable
= ForceON
;
5168 iris_emit_merge(batch
, cso
->wm
, dynamic_wm
, ARRAY_SIZE(cso
->wm
));
5171 if (dirty
& IRIS_DIRTY_SBE
) {
5172 iris_emit_sbe(batch
, ice
);
5175 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
5176 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
5177 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
5178 const struct shader_info
*fs_info
=
5179 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
5181 uint32_t dynamic_pb
[GENX(3DSTATE_PS_BLEND_length
)];
5182 iris_pack_command(GENX(3DSTATE_PS_BLEND
), &dynamic_pb
, pb
) {
5183 pb
.HasWriteableRT
= has_writeable_rt(cso_blend
, fs_info
);
5184 pb
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
5186 /* The dual source blending docs caution against using SRC1 factors
5187 * when the shader doesn't use a dual source render target write.
5188 * Empirically, this can lead to GPU hangs, and the results are
5189 * undefined anyway, so simply disable blending to avoid the hang.
5191 pb
.ColorBufferBlendEnable
= (cso_blend
->blend_enables
& 1) &&
5192 (!cso_blend
->dual_color_blending
|| wm_prog_data
->dual_src_blend
);
5195 iris_emit_merge(batch
, cso_blend
->ps_blend
, dynamic_pb
,
5196 ARRAY_SIZE(cso_blend
->ps_blend
));
5199 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
5200 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
5202 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
5203 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
5204 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
5205 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
5206 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
5208 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
, ARRAY_SIZE(cso
->wmds
));
5210 iris_batch_emit(batch
, cso
->wmds
, sizeof(cso
->wmds
));
5214 if (dirty
& IRIS_DIRTY_SCISSOR_RECT
) {
5215 uint32_t scissor_offset
=
5216 emit_state(batch
, ice
->state
.dynamic_uploader
,
5217 &ice
->state
.last_res
.scissor
,
5218 ice
->state
.scissors
,
5219 sizeof(struct pipe_scissor_state
) *
5220 ice
->state
.num_viewports
, 32);
5222 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
5223 ptr
.ScissorRectPointer
= scissor_offset
;
5227 if (dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
5228 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
5230 /* Do not emit the clear params yets. We need to update the clear value
5233 uint32_t clear_length
= GENX(3DSTATE_CLEAR_PARAMS_length
) * 4;
5234 uint32_t cso_z_size
= sizeof(cso_z
->packets
) - clear_length
;
5235 iris_batch_emit(batch
, cso_z
->packets
, cso_z_size
);
5237 union isl_color_value clear_value
= { .f32
= { 0, } };
5239 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5240 if (cso_fb
->zsbuf
) {
5241 struct iris_resource
*zres
, *sres
;
5242 iris_get_depth_stencil_resources(cso_fb
->zsbuf
->texture
,
5244 if (zres
&& zres
->aux
.bo
)
5245 clear_value
= iris_resource_get_clear_color(zres
, NULL
, NULL
);
5248 uint32_t clear_params
[GENX(3DSTATE_CLEAR_PARAMS_length
)];
5249 iris_pack_command(GENX(3DSTATE_CLEAR_PARAMS
), clear_params
, clear
) {
5250 clear
.DepthClearValueValid
= true;
5251 clear
.DepthClearValue
= clear_value
.f32
[0];
5253 iris_batch_emit(batch
, clear_params
, clear_length
);
5256 if (dirty
& (IRIS_DIRTY_DEPTH_BUFFER
| IRIS_DIRTY_WM_DEPTH_STENCIL
)) {
5257 /* Listen for buffer changes, and also write enable changes. */
5258 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5259 pin_depth_and_stencil_buffers(batch
, cso_fb
->zsbuf
, ice
->state
.cso_zsa
);
5262 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
5263 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
5264 for (int i
= 0; i
< 32; i
++) {
5265 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
5270 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
5271 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
5272 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
5275 if (dirty
& IRIS_DIRTY_VF_TOPOLOGY
) {
5276 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
5277 topo
.PrimitiveTopologyType
=
5278 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
5282 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
5283 int count
= util_bitcount64(ice
->state
.bound_vertex_buffers
);
5284 int dynamic_bound
= ice
->state
.bound_vertex_buffers
;
5286 if (ice
->state
.vs_uses_draw_params
) {
5287 assert(ice
->draw
.draw_params
.res
);
5289 struct iris_vertex_buffer_state
*state
=
5290 &(ice
->state
.genx
->vertex_buffers
[count
]);
5291 pipe_resource_reference(&state
->resource
, ice
->draw
.draw_params
.res
);
5292 struct iris_resource
*res
= (void *) state
->resource
;
5294 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
5295 vb
.VertexBufferIndex
= count
;
5296 vb
.AddressModifyEnable
= true;
5298 vb
.BufferSize
= res
->bo
->size
- ice
->draw
.draw_params
.offset
;
5299 vb
.BufferStartingAddress
=
5300 ro_bo(NULL
, res
->bo
->gtt_offset
+
5301 (int) ice
->draw
.draw_params
.offset
);
5302 vb
.MOCS
= mocs(res
->bo
);
5304 dynamic_bound
|= 1ull << count
;
5308 if (ice
->state
.vs_uses_derived_draw_params
) {
5309 struct iris_vertex_buffer_state
*state
=
5310 &(ice
->state
.genx
->vertex_buffers
[count
]);
5311 pipe_resource_reference(&state
->resource
,
5312 ice
->draw
.derived_draw_params
.res
);
5313 struct iris_resource
*res
= (void *) ice
->draw
.derived_draw_params
.res
;
5315 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
5316 vb
.VertexBufferIndex
= count
;
5317 vb
.AddressModifyEnable
= true;
5320 res
->bo
->size
- ice
->draw
.derived_draw_params
.offset
;
5321 vb
.BufferStartingAddress
=
5322 ro_bo(NULL
, res
->bo
->gtt_offset
+
5323 (int) ice
->draw
.derived_draw_params
.offset
);
5324 vb
.MOCS
= mocs(res
->bo
);
5326 dynamic_bound
|= 1ull << count
;
5331 /* The VF cache designers cut corners, and made the cache key's
5332 * <VertexBufferIndex, Memory Address> tuple only consider the bottom
5333 * 32 bits of the address. If you have two vertex buffers which get
5334 * placed exactly 4 GiB apart and use them in back-to-back draw calls,
5335 * you can get collisions (even within a single batch).
5337 * So, we need to do a VF cache invalidate if the buffer for a VB
5338 * slot slot changes [48:32] address bits from the previous time.
5340 unsigned flush_flags
= 0;
5342 uint64_t bound
= dynamic_bound
;
5344 const int i
= u_bit_scan64(&bound
);
5345 uint16_t high_bits
= 0;
5347 struct iris_resource
*res
=
5348 (void *) genx
->vertex_buffers
[i
].resource
;
5350 iris_use_pinned_bo(batch
, res
->bo
, false);
5352 high_bits
= res
->bo
->gtt_offset
>> 32ull;
5353 if (high_bits
!= ice
->state
.last_vbo_high_bits
[i
]) {
5354 flush_flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
|
5355 PIPE_CONTROL_CS_STALL
;
5356 ice
->state
.last_vbo_high_bits
[i
] = high_bits
;
5362 iris_emit_pipe_control_flush(batch
,
5363 "workaround: VF cache 32-bit key [VB]",
5367 const unsigned vb_dwords
= GENX(VERTEX_BUFFER_STATE_length
);
5370 iris_get_command_space(batch
, 4 * (1 + vb_dwords
* count
));
5371 _iris_pack_command(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), map
, vb
) {
5372 vb
.DWordLength
= (vb_dwords
* count
+ 1) - 2;
5376 bound
= dynamic_bound
;
5378 const int i
= u_bit_scan64(&bound
);
5379 memcpy(map
, genx
->vertex_buffers
[i
].state
,
5380 sizeof(uint32_t) * vb_dwords
);
5386 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
5387 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
5388 const unsigned entries
= MAX2(cso
->count
, 1);
5389 if (!(ice
->state
.vs_needs_sgvs_element
||
5390 ice
->state
.vs_uses_derived_draw_params
||
5391 ice
->state
.vs_needs_edge_flag
)) {
5392 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
5393 (1 + entries
* GENX(VERTEX_ELEMENT_STATE_length
)));
5395 uint32_t dynamic_ves
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
5396 const unsigned dyn_count
= cso
->count
+
5397 ice
->state
.vs_needs_sgvs_element
+
5398 ice
->state
.vs_uses_derived_draw_params
;
5400 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
),
5403 1 + GENX(VERTEX_ELEMENT_STATE_length
) * dyn_count
- 2;
5405 memcpy(&dynamic_ves
[1], &cso
->vertex_elements
[1],
5406 (cso
->count
- ice
->state
.vs_needs_edge_flag
) *
5407 GENX(VERTEX_ELEMENT_STATE_length
) * sizeof(uint32_t));
5408 uint32_t *ve_pack_dest
=
5409 &dynamic_ves
[1 + (cso
->count
- ice
->state
.vs_needs_edge_flag
) *
5410 GENX(VERTEX_ELEMENT_STATE_length
)];
5412 if (ice
->state
.vs_needs_sgvs_element
) {
5413 uint32_t base_ctrl
= ice
->state
.vs_uses_draw_params
?
5414 VFCOMP_STORE_SRC
: VFCOMP_STORE_0
;
5415 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
5417 ve
.VertexBufferIndex
=
5418 util_bitcount64(ice
->state
.bound_vertex_buffers
);
5419 ve
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
5420 ve
.Component0Control
= base_ctrl
;
5421 ve
.Component1Control
= base_ctrl
;
5422 ve
.Component2Control
= VFCOMP_STORE_0
;
5423 ve
.Component3Control
= VFCOMP_STORE_0
;
5425 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
5427 if (ice
->state
.vs_uses_derived_draw_params
) {
5428 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
5430 ve
.VertexBufferIndex
=
5431 util_bitcount64(ice
->state
.bound_vertex_buffers
) +
5432 ice
->state
.vs_uses_draw_params
;
5433 ve
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
5434 ve
.Component0Control
= VFCOMP_STORE_SRC
;
5435 ve
.Component1Control
= VFCOMP_STORE_SRC
;
5436 ve
.Component2Control
= VFCOMP_STORE_0
;
5437 ve
.Component3Control
= VFCOMP_STORE_0
;
5439 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
5441 if (ice
->state
.vs_needs_edge_flag
) {
5442 for (int i
= 0; i
< GENX(VERTEX_ELEMENT_STATE_length
); i
++)
5443 ve_pack_dest
[i
] = cso
->edgeflag_ve
[i
];
5446 iris_batch_emit(batch
, &dynamic_ves
, sizeof(uint32_t) *
5447 (1 + dyn_count
* GENX(VERTEX_ELEMENT_STATE_length
)));
5450 if (!ice
->state
.vs_needs_edge_flag
) {
5451 iris_batch_emit(batch
, cso
->vf_instancing
, sizeof(uint32_t) *
5452 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
5454 assert(cso
->count
> 0);
5455 const unsigned edgeflag_index
= cso
->count
- 1;
5456 uint32_t dynamic_vfi
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
5457 memcpy(&dynamic_vfi
[0], cso
->vf_instancing
, edgeflag_index
*
5458 GENX(3DSTATE_VF_INSTANCING_length
) * sizeof(uint32_t));
5460 uint32_t *vfi_pack_dest
= &dynamic_vfi
[0] +
5461 edgeflag_index
* GENX(3DSTATE_VF_INSTANCING_length
);
5462 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
5463 vi
.VertexElementIndex
= edgeflag_index
+
5464 ice
->state
.vs_needs_sgvs_element
+
5465 ice
->state
.vs_uses_derived_draw_params
;
5467 for (int i
= 0; i
< GENX(3DSTATE_VF_INSTANCING_length
); i
++)
5468 vfi_pack_dest
[i
] |= cso
->edgeflag_vfi
[i
];
5470 iris_batch_emit(batch
, &dynamic_vfi
[0], sizeof(uint32_t) *
5471 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
5475 if (dirty
& IRIS_DIRTY_VF_SGVS
) {
5476 const struct brw_vs_prog_data
*vs_prog_data
= (void *)
5477 ice
->shaders
.prog
[MESA_SHADER_VERTEX
]->prog_data
;
5478 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
5480 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgv
) {
5481 if (vs_prog_data
->uses_vertexid
) {
5482 sgv
.VertexIDEnable
= true;
5483 sgv
.VertexIDComponentNumber
= 2;
5484 sgv
.VertexIDElementOffset
=
5485 cso
->count
- ice
->state
.vs_needs_edge_flag
;
5488 if (vs_prog_data
->uses_instanceid
) {
5489 sgv
.InstanceIDEnable
= true;
5490 sgv
.InstanceIDComponentNumber
= 3;
5491 sgv
.InstanceIDElementOffset
=
5492 cso
->count
- ice
->state
.vs_needs_edge_flag
;
5497 if (dirty
& IRIS_DIRTY_VF
) {
5498 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
5499 if (draw
->primitive_restart
) {
5500 vf
.IndexedDrawCutIndexEnable
= true;
5501 vf
.CutIndex
= draw
->restart_index
;
5506 if (dirty
& IRIS_DIRTY_VF_STATISTICS
) {
5507 iris_emit_cmd(batch
, GENX(3DSTATE_VF_STATISTICS
), vf
) {
5508 vf
.StatisticsEnable
= true;
5512 if (ice
->state
.current_hash_scale
!= 1)
5513 genX(emit_hashing_mode
)(ice
, batch
, UINT_MAX
, UINT_MAX
, 1);
5515 /* TODO: Gen8 PMA fix */
5519 iris_upload_render_state(struct iris_context
*ice
,
5520 struct iris_batch
*batch
,
5521 const struct pipe_draw_info
*draw
)
5523 bool use_predicate
= ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
;
5525 /* Always pin the binder. If we're emitting new binding table pointers,
5526 * we need it. If not, we're probably inheriting old tables via the
5527 * context, and need it anyway. Since true zero-bindings cases are
5528 * practically non-existent, just pin it and avoid last_res tracking.
5530 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
5532 if (!batch
->contains_draw
) {
5533 iris_restore_render_saved_bos(ice
, batch
, draw
);
5534 batch
->contains_draw
= true;
5537 iris_upload_dirty_render_state(ice
, batch
, draw
);
5539 if (draw
->index_size
> 0) {
5542 if (draw
->has_user_indices
) {
5543 u_upload_data(ice
->ctx
.stream_uploader
, 0,
5544 draw
->count
* draw
->index_size
, 4, draw
->index
.user
,
5545 &offset
, &ice
->state
.last_res
.index_buffer
);
5547 struct iris_resource
*res
= (void *) draw
->index
.resource
;
5548 res
->bind_history
|= PIPE_BIND_INDEX_BUFFER
;
5550 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
,
5551 draw
->index
.resource
);
5555 struct iris_genx_state
*genx
= ice
->state
.genx
;
5556 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
5558 uint32_t ib_packet
[GENX(3DSTATE_INDEX_BUFFER_length
)];
5559 iris_pack_command(GENX(3DSTATE_INDEX_BUFFER
), ib_packet
, ib
) {
5560 ib
.IndexFormat
= draw
->index_size
>> 1;
5562 ib
.BufferSize
= bo
->size
- offset
;
5563 ib
.BufferStartingAddress
= ro_bo(NULL
, bo
->gtt_offset
+ offset
);
5566 if (memcmp(genx
->last_index_buffer
, ib_packet
, sizeof(ib_packet
)) != 0) {
5567 memcpy(genx
->last_index_buffer
, ib_packet
, sizeof(ib_packet
));
5568 iris_batch_emit(batch
, ib_packet
, sizeof(ib_packet
));
5569 iris_use_pinned_bo(batch
, bo
, false);
5572 /* The VF cache key only uses 32-bits, see vertex buffer comment above */
5573 uint16_t high_bits
= bo
->gtt_offset
>> 32ull;
5574 if (high_bits
!= ice
->state
.last_index_bo_high_bits
) {
5575 iris_emit_pipe_control_flush(batch
,
5576 "workaround: VF cache 32-bit key [IB]",
5577 PIPE_CONTROL_VF_CACHE_INVALIDATE
|
5578 PIPE_CONTROL_CS_STALL
);
5579 ice
->state
.last_index_bo_high_bits
= high_bits
;
5583 #define _3DPRIM_END_OFFSET 0x2420
5584 #define _3DPRIM_START_VERTEX 0x2430
5585 #define _3DPRIM_VERTEX_COUNT 0x2434
5586 #define _3DPRIM_INSTANCE_COUNT 0x2438
5587 #define _3DPRIM_START_INSTANCE 0x243C
5588 #define _3DPRIM_BASE_VERTEX 0x2440
5590 if (draw
->indirect
) {
5591 if (draw
->indirect
->indirect_draw_count
) {
5592 use_predicate
= true;
5594 struct iris_bo
*draw_count_bo
=
5595 iris_resource_bo(draw
->indirect
->indirect_draw_count
);
5596 unsigned draw_count_offset
=
5597 draw
->indirect
->indirect_draw_count_offset
;
5599 iris_emit_pipe_control_flush(batch
,
5600 "ensure indirect draw buffer is flushed",
5601 PIPE_CONTROL_FLUSH_ENABLE
);
5603 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
) {
5604 struct gen_mi_builder b
;
5605 gen_mi_builder_init(&b
, batch
);
5607 /* comparison = draw id < draw count */
5608 struct gen_mi_value comparison
=
5609 gen_mi_ult(&b
, gen_mi_imm(draw
->drawid
),
5610 gen_mi_mem32(ro_bo(draw_count_bo
,
5611 draw_count_offset
)));
5613 /* predicate = comparison & conditional rendering predicate */
5614 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_RESULT
),
5615 gen_mi_iand(&b
, comparison
,
5616 gen_mi_reg32(CS_GPR(15))));
5618 uint32_t mi_predicate
;
5620 /* Upload the id of the current primitive to MI_PREDICATE_SRC1. */
5621 ice
->vtbl
.load_register_imm64(batch
, MI_PREDICATE_SRC1
,
5623 /* Upload the current draw count from the draw parameters buffer
5624 * to MI_PREDICATE_SRC0.
5626 ice
->vtbl
.load_register_mem32(batch
, MI_PREDICATE_SRC0
,
5627 draw_count_bo
, draw_count_offset
);
5628 /* Zero the top 32-bits of MI_PREDICATE_SRC0 */
5629 ice
->vtbl
.load_register_imm32(batch
, MI_PREDICATE_SRC0
+ 4, 0);
5631 if (draw
->drawid
== 0) {
5632 mi_predicate
= MI_PREDICATE
| MI_PREDICATE_LOADOP_LOADINV
|
5633 MI_PREDICATE_COMBINEOP_SET
|
5634 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
;
5636 /* While draw_index < draw_count the predicate's result will be
5637 * (draw_index == draw_count) ^ TRUE = TRUE
5638 * When draw_index == draw_count the result is
5639 * (TRUE) ^ TRUE = FALSE
5640 * After this all results will be:
5641 * (FALSE) ^ FALSE = FALSE
5643 mi_predicate
= MI_PREDICATE
| MI_PREDICATE_LOADOP_LOAD
|
5644 MI_PREDICATE_COMBINEOP_XOR
|
5645 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
;
5647 iris_batch_emit(batch
, &mi_predicate
, sizeof(uint32_t));
5650 struct iris_bo
*bo
= iris_resource_bo(draw
->indirect
->buffer
);
5653 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5654 lrm
.RegisterAddress
= _3DPRIM_VERTEX_COUNT
;
5655 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 0);
5657 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5658 lrm
.RegisterAddress
= _3DPRIM_INSTANCE_COUNT
;
5659 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 4);
5661 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5662 lrm
.RegisterAddress
= _3DPRIM_START_VERTEX
;
5663 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 8);
5665 if (draw
->index_size
) {
5666 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5667 lrm
.RegisterAddress
= _3DPRIM_BASE_VERTEX
;
5668 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
5670 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5671 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
5672 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 16);
5675 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5676 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
5677 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
5679 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
5680 lri
.RegisterOffset
= _3DPRIM_BASE_VERTEX
;
5684 } else if (draw
->count_from_stream_output
) {
5685 struct iris_stream_output_target
*so
=
5686 (void *) draw
->count_from_stream_output
;
5688 /* XXX: Replace with actual cache tracking */
5689 iris_emit_pipe_control_flush(batch
,
5690 "draw count from stream output stall",
5691 PIPE_CONTROL_CS_STALL
);
5693 struct gen_mi_builder b
;
5694 gen_mi_builder_init(&b
, batch
);
5696 struct iris_address addr
=
5697 ro_bo(iris_resource_bo(so
->offset
.res
), so
->offset
.offset
);
5698 struct gen_mi_value offset
=
5699 gen_mi_iadd_imm(&b
, gen_mi_mem32(addr
), -so
->base
.buffer_offset
);
5701 gen_mi_store(&b
, gen_mi_reg32(_3DPRIM_VERTEX_COUNT
),
5702 gen_mi_udiv32_imm(&b
, offset
, so
->stride
));
5704 _iris_emit_lri(batch
, _3DPRIM_START_VERTEX
, 0);
5705 _iris_emit_lri(batch
, _3DPRIM_BASE_VERTEX
, 0);
5706 _iris_emit_lri(batch
, _3DPRIM_START_INSTANCE
, 0);
5707 _iris_emit_lri(batch
, _3DPRIM_INSTANCE_COUNT
, draw
->instance_count
);
5710 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
5711 prim
.VertexAccessType
= draw
->index_size
> 0 ? RANDOM
: SEQUENTIAL
;
5712 prim
.PredicateEnable
= use_predicate
;
5714 if (draw
->indirect
|| draw
->count_from_stream_output
) {
5715 prim
.IndirectParameterEnable
= true;
5717 prim
.StartInstanceLocation
= draw
->start_instance
;
5718 prim
.InstanceCount
= draw
->instance_count
;
5719 prim
.VertexCountPerInstance
= draw
->count
;
5721 prim
.StartVertexLocation
= draw
->start
;
5723 if (draw
->index_size
) {
5724 prim
.BaseVertexLocation
+= draw
->index_bias
;
5726 prim
.StartVertexLocation
+= draw
->index_bias
;
5733 iris_upload_compute_state(struct iris_context
*ice
,
5734 struct iris_batch
*batch
,
5735 const struct pipe_grid_info
*grid
)
5737 const uint64_t dirty
= ice
->state
.dirty
;
5738 struct iris_screen
*screen
= batch
->screen
;
5739 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
5740 struct iris_binder
*binder
= &ice
->state
.binder
;
5741 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_COMPUTE
];
5742 struct iris_compiled_shader
*shader
=
5743 ice
->shaders
.prog
[MESA_SHADER_COMPUTE
];
5744 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
5745 struct brw_cs_prog_data
*cs_prog_data
= (void *) prog_data
;
5747 /* Always pin the binder. If we're emitting new binding table pointers,
5748 * we need it. If not, we're probably inheriting old tables via the
5749 * context, and need it anyway. Since true zero-bindings cases are
5750 * practically non-existent, just pin it and avoid last_res tracking.
5752 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
5754 if ((dirty
& IRIS_DIRTY_CONSTANTS_CS
) && shs
->sysvals_need_upload
)
5755 upload_sysvals(ice
, MESA_SHADER_COMPUTE
);
5757 if (dirty
& IRIS_DIRTY_BINDINGS_CS
)
5758 iris_populate_binding_table(ice
, batch
, MESA_SHADER_COMPUTE
, false);
5760 if (dirty
& IRIS_DIRTY_SAMPLER_STATES_CS
)
5761 iris_upload_sampler_states(ice
, MESA_SHADER_COMPUTE
);
5763 iris_use_optional_res(batch
, shs
->sampler_table
.res
, false);
5764 iris_use_pinned_bo(batch
, iris_resource_bo(shader
->assembly
.res
), false);
5766 if (ice
->state
.need_border_colors
)
5767 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
5769 if (dirty
& IRIS_DIRTY_CS
) {
5770 /* The MEDIA_VFE_STATE documentation for Gen8+ says:
5772 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
5773 * the only bits that are changed are scoreboard related: Scoreboard
5774 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard Delta. For
5775 * these scoreboard related states, a MEDIA_STATE_FLUSH is
5778 iris_emit_pipe_control_flush(batch
,
5779 "workaround: stall before MEDIA_VFE_STATE",
5780 PIPE_CONTROL_CS_STALL
);
5782 iris_emit_cmd(batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
5783 if (prog_data
->total_scratch
) {
5784 struct iris_bo
*bo
=
5785 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
5786 MESA_SHADER_COMPUTE
);
5787 vfe
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
5788 vfe
.ScratchSpaceBasePointer
= rw_bo(bo
, 0);
5791 vfe
.MaximumNumberofThreads
=
5792 devinfo
->max_cs_threads
* screen
->subslice_total
- 1;
5794 vfe
.ResetGatewayTimer
=
5795 Resettingrelativetimerandlatchingtheglobaltimestamp
;
5798 vfe
.BypassGatewayControl
= true;
5800 vfe
.NumberofURBEntries
= 2;
5801 vfe
.URBEntryAllocationSize
= 2;
5803 vfe
.CURBEAllocationSize
=
5804 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
5805 cs_prog_data
->push
.cross_thread
.regs
, 2);
5809 /* TODO: Combine subgroup-id with cbuf0 so we can push regular uniforms */
5810 if (dirty
& IRIS_DIRTY_CS
) {
5811 uint32_t curbe_data_offset
= 0;
5812 assert(cs_prog_data
->push
.cross_thread
.dwords
== 0 &&
5813 cs_prog_data
->push
.per_thread
.dwords
== 1 &&
5814 cs_prog_data
->base
.param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
5815 uint32_t *curbe_data_map
=
5816 stream_state(batch
, ice
->state
.dynamic_uploader
,
5817 &ice
->state
.last_res
.cs_thread_ids
,
5818 ALIGN(cs_prog_data
->push
.total
.size
, 64), 64,
5819 &curbe_data_offset
);
5820 assert(curbe_data_map
);
5821 memset(curbe_data_map
, 0x5a, ALIGN(cs_prog_data
->push
.total
.size
, 64));
5822 iris_fill_cs_push_const_buffer(cs_prog_data
, curbe_data_map
);
5824 iris_emit_cmd(batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
5825 curbe
.CURBETotalDataLength
=
5826 ALIGN(cs_prog_data
->push
.total
.size
, 64);
5827 curbe
.CURBEDataStartAddress
= curbe_data_offset
;
5831 if (dirty
& (IRIS_DIRTY_SAMPLER_STATES_CS
|
5832 IRIS_DIRTY_BINDINGS_CS
|
5833 IRIS_DIRTY_CONSTANTS_CS
|
5835 uint32_t desc
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
5837 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), desc
, idd
) {
5838 idd
.SamplerStatePointer
= shs
->sampler_table
.offset
;
5839 idd
.BindingTablePointer
= binder
->bt_offset
[MESA_SHADER_COMPUTE
];
5842 for (int i
= 0; i
< GENX(INTERFACE_DESCRIPTOR_DATA_length
); i
++)
5843 desc
[i
] |= ((uint32_t *) shader
->derived_data
)[i
];
5845 iris_emit_cmd(batch
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
5846 load
.InterfaceDescriptorTotalLength
=
5847 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
5848 load
.InterfaceDescriptorDataStartAddress
=
5849 emit_state(batch
, ice
->state
.dynamic_uploader
,
5850 &ice
->state
.last_res
.cs_desc
, desc
, sizeof(desc
), 64);
5854 uint32_t group_size
= grid
->block
[0] * grid
->block
[1] * grid
->block
[2];
5855 uint32_t remainder
= group_size
& (cs_prog_data
->simd_size
- 1);
5856 uint32_t right_mask
;
5859 right_mask
= ~0u >> (32 - remainder
);
5861 right_mask
= ~0u >> (32 - cs_prog_data
->simd_size
);
5863 #define GPGPU_DISPATCHDIMX 0x2500
5864 #define GPGPU_DISPATCHDIMY 0x2504
5865 #define GPGPU_DISPATCHDIMZ 0x2508
5867 if (grid
->indirect
) {
5868 struct iris_state_ref
*grid_size
= &ice
->state
.grid_size
;
5869 struct iris_bo
*bo
= iris_resource_bo(grid_size
->res
);
5870 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5871 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMX
;
5872 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 0);
5874 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5875 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMY
;
5876 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 4);
5878 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5879 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMZ
;
5880 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 8);
5884 iris_emit_cmd(batch
, GENX(GPGPU_WALKER
), ggw
) {
5885 ggw
.IndirectParameterEnable
= grid
->indirect
!= NULL
;
5886 ggw
.SIMDSize
= cs_prog_data
->simd_size
/ 16;
5887 ggw
.ThreadDepthCounterMaximum
= 0;
5888 ggw
.ThreadHeightCounterMaximum
= 0;
5889 ggw
.ThreadWidthCounterMaximum
= cs_prog_data
->threads
- 1;
5890 ggw
.ThreadGroupIDXDimension
= grid
->grid
[0];
5891 ggw
.ThreadGroupIDYDimension
= grid
->grid
[1];
5892 ggw
.ThreadGroupIDZDimension
= grid
->grid
[2];
5893 ggw
.RightExecutionMask
= right_mask
;
5894 ggw
.BottomExecutionMask
= 0xffffffff;
5897 iris_emit_cmd(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
5899 if (!batch
->contains_draw
) {
5900 iris_restore_compute_saved_bos(ice
, batch
, grid
);
5901 batch
->contains_draw
= true;
5906 * State module teardown.
5909 iris_destroy_state(struct iris_context
*ice
)
5911 struct iris_genx_state
*genx
= ice
->state
.genx
;
5913 pipe_resource_reference(&ice
->draw
.draw_params
.res
, NULL
);
5914 pipe_resource_reference(&ice
->draw
.derived_draw_params
.res
, NULL
);
5916 uint64_t bound_vbs
= ice
->state
.bound_vertex_buffers
;
5918 const int i
= u_bit_scan64(&bound_vbs
);
5919 pipe_resource_reference(&genx
->vertex_buffers
[i
].resource
, NULL
);
5921 free(ice
->state
.genx
);
5923 for (int i
= 0; i
< 4; i
++) {
5924 pipe_so_target_reference(&ice
->state
.so_target
[i
], NULL
);
5927 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
5928 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
5930 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
5932 for (int stage
= 0; stage
< MESA_SHADER_STAGES
; stage
++) {
5933 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
5934 pipe_resource_reference(&shs
->sampler_table
.res
, NULL
);
5935 for (int i
= 0; i
< PIPE_MAX_CONSTANT_BUFFERS
; i
++) {
5936 pipe_resource_reference(&shs
->constbuf
[i
].buffer
, NULL
);
5937 pipe_resource_reference(&shs
->constbuf_surf_state
[i
].res
, NULL
);
5939 for (int i
= 0; i
< PIPE_MAX_SHADER_IMAGES
; i
++) {
5940 pipe_resource_reference(&shs
->image
[i
].base
.resource
, NULL
);
5941 pipe_resource_reference(&shs
->image
[i
].surface_state
.res
, NULL
);
5943 for (int i
= 0; i
< PIPE_MAX_SHADER_BUFFERS
; i
++) {
5944 pipe_resource_reference(&shs
->ssbo
[i
].buffer
, NULL
);
5945 pipe_resource_reference(&shs
->ssbo_surf_state
[i
].res
, NULL
);
5947 for (int i
= 0; i
< IRIS_MAX_TEXTURE_SAMPLERS
; i
++) {
5948 pipe_sampler_view_reference((struct pipe_sampler_view
**)
5949 &shs
->textures
[i
], NULL
);
5953 pipe_resource_reference(&ice
->state
.grid_size
.res
, NULL
);
5954 pipe_resource_reference(&ice
->state
.grid_surf_state
.res
, NULL
);
5956 pipe_resource_reference(&ice
->state
.null_fb
.res
, NULL
);
5957 pipe_resource_reference(&ice
->state
.unbound_tex
.res
, NULL
);
5959 pipe_resource_reference(&ice
->state
.last_res
.cc_vp
, NULL
);
5960 pipe_resource_reference(&ice
->state
.last_res
.sf_cl_vp
, NULL
);
5961 pipe_resource_reference(&ice
->state
.last_res
.color_calc
, NULL
);
5962 pipe_resource_reference(&ice
->state
.last_res
.scissor
, NULL
);
5963 pipe_resource_reference(&ice
->state
.last_res
.blend
, NULL
);
5964 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
, NULL
);
5965 pipe_resource_reference(&ice
->state
.last_res
.cs_thread_ids
, NULL
);
5966 pipe_resource_reference(&ice
->state
.last_res
.cs_desc
, NULL
);
5969 /* ------------------------------------------------------------------- */
5972 iris_rebind_buffer(struct iris_context
*ice
,
5973 struct iris_resource
*res
,
5974 uint64_t old_address
)
5976 struct pipe_context
*ctx
= &ice
->ctx
;
5977 struct iris_screen
*screen
= (void *) ctx
->screen
;
5978 struct iris_genx_state
*genx
= ice
->state
.genx
;
5980 assert(res
->base
.target
== PIPE_BUFFER
);
5982 /* Buffers can't be framebuffer attachments, nor display related,
5983 * and we don't have upstream Clover support.
5985 assert(!(res
->bind_history
& (PIPE_BIND_DEPTH_STENCIL
|
5986 PIPE_BIND_RENDER_TARGET
|
5987 PIPE_BIND_BLENDABLE
|
5988 PIPE_BIND_DISPLAY_TARGET
|
5990 PIPE_BIND_COMPUTE_RESOURCE
|
5991 PIPE_BIND_GLOBAL
)));
5993 if (res
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
5994 uint64_t bound_vbs
= ice
->state
.bound_vertex_buffers
;
5996 const int i
= u_bit_scan64(&bound_vbs
);
5997 struct iris_vertex_buffer_state
*state
= &genx
->vertex_buffers
[i
];
5999 /* Update the CPU struct */
6000 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_start
) == 32);
6001 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits
) == 64);
6002 uint64_t *addr
= (uint64_t *) &state
->state
[1];
6004 if (*addr
== old_address
) {
6005 *addr
= res
->bo
->gtt_offset
;
6006 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
6011 /* We don't need to handle PIPE_BIND_INDEX_BUFFER here: we re-emit
6012 * the 3DSTATE_INDEX_BUFFER packet whenever the address changes.
6014 * There is also no need to handle these:
6015 * - PIPE_BIND_COMMAND_ARGS_BUFFER (emitted for every indirect draw)
6016 * - PIPE_BIND_QUERY_BUFFER (no persistent state references)
6019 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
6020 /* XXX: be careful about resetting vs appending... */
6024 for (int s
= MESA_SHADER_VERTEX
; s
< MESA_SHADER_STAGES
; s
++) {
6025 struct iris_shader_state
*shs
= &ice
->state
.shaders
[s
];
6026 enum pipe_shader_type p_stage
= stage_to_pipe(s
);
6028 if (!(res
->bind_stages
& (1 << s
)))
6031 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
6032 /* Skip constant buffer 0, it's for regular uniforms, not UBOs */
6033 uint32_t bound_cbufs
= shs
->bound_cbufs
& ~1u;
6034 while (bound_cbufs
) {
6035 const int i
= u_bit_scan(&bound_cbufs
);
6036 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[i
];
6037 struct iris_state_ref
*surf_state
= &shs
->constbuf_surf_state
[i
];
6039 if (res
->bo
== iris_resource_bo(cbuf
->buffer
)) {
6040 pipe_resource_reference(&surf_state
->res
, NULL
);
6041 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< s
;
6046 if (res
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
6047 uint32_t bound_ssbos
= shs
->bound_ssbos
;
6048 while (bound_ssbos
) {
6049 const int i
= u_bit_scan(&bound_ssbos
);
6050 struct pipe_shader_buffer
*ssbo
= &shs
->ssbo
[i
];
6052 if (res
->bo
== iris_resource_bo(ssbo
->buffer
)) {
6053 struct pipe_shader_buffer buf
= {
6054 .buffer
= &res
->base
,
6055 .buffer_offset
= ssbo
->buffer_offset
,
6056 .buffer_size
= ssbo
->buffer_size
,
6058 iris_set_shader_buffers(ctx
, p_stage
, i
, 1, &buf
,
6059 (shs
->writable_ssbos
>> i
) & 1);
6064 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
6065 uint32_t bound_sampler_views
= shs
->bound_sampler_views
;
6066 while (bound_sampler_views
) {
6067 const int i
= u_bit_scan(&bound_sampler_views
);
6068 struct iris_sampler_view
*isv
= shs
->textures
[i
];
6070 if (res
->bo
== iris_resource_bo(isv
->base
.texture
)) {
6071 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
6072 &isv
->surface_state
,
6073 isv
->res
->aux
.sampler_usages
);
6075 fill_buffer_surface_state(&screen
->isl_dev
, isv
->res
, map
,
6076 isv
->view
.format
, isv
->view
.swizzle
,
6077 isv
->base
.u
.buf
.offset
,
6078 isv
->base
.u
.buf
.size
);
6079 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< s
;
6084 if (res
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
6085 uint32_t bound_image_views
= shs
->bound_image_views
;
6086 while (bound_image_views
) {
6087 const int i
= u_bit_scan(&bound_image_views
);
6088 struct iris_image_view
*iv
= &shs
->image
[i
];
6090 if (res
->bo
== iris_resource_bo(iv
->base
.resource
)) {
6091 iris_set_shader_images(ctx
, p_stage
, i
, 1, &iv
->base
);
6098 /* ------------------------------------------------------------------- */
6101 iris_load_register_reg32(struct iris_batch
*batch
, uint32_t dst
,
6104 _iris_emit_lrr(batch
, dst
, src
);
6108 iris_load_register_reg64(struct iris_batch
*batch
, uint32_t dst
,
6111 _iris_emit_lrr(batch
, dst
, src
);
6112 _iris_emit_lrr(batch
, dst
+ 4, src
+ 4);
6116 iris_load_register_imm32(struct iris_batch
*batch
, uint32_t reg
,
6119 _iris_emit_lri(batch
, reg
, val
);
6123 iris_load_register_imm64(struct iris_batch
*batch
, uint32_t reg
,
6126 _iris_emit_lri(batch
, reg
+ 0, val
& 0xffffffff);
6127 _iris_emit_lri(batch
, reg
+ 4, val
>> 32);
6131 * Emit MI_LOAD_REGISTER_MEM to load a 32-bit MMIO register from a buffer.
6134 iris_load_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
6135 struct iris_bo
*bo
, uint32_t offset
)
6137 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6138 lrm
.RegisterAddress
= reg
;
6139 lrm
.MemoryAddress
= ro_bo(bo
, offset
);
6144 * Load a 64-bit value from a buffer into a MMIO register via
6145 * two MI_LOAD_REGISTER_MEM commands.
6148 iris_load_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
6149 struct iris_bo
*bo
, uint32_t offset
)
6151 iris_load_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0);
6152 iris_load_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4);
6156 iris_store_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
6157 struct iris_bo
*bo
, uint32_t offset
,
6160 iris_emit_cmd(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
6161 srm
.RegisterAddress
= reg
;
6162 srm
.MemoryAddress
= rw_bo(bo
, offset
);
6163 srm
.PredicateEnable
= predicated
;
6168 iris_store_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
6169 struct iris_bo
*bo
, uint32_t offset
,
6172 iris_store_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0, predicated
);
6173 iris_store_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4, predicated
);
6177 iris_store_data_imm32(struct iris_batch
*batch
,
6178 struct iris_bo
*bo
, uint32_t offset
,
6181 iris_emit_cmd(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
6182 sdi
.Address
= rw_bo(bo
, offset
);
6183 sdi
.ImmediateData
= imm
;
6188 iris_store_data_imm64(struct iris_batch
*batch
,
6189 struct iris_bo
*bo
, uint32_t offset
,
6192 /* Can't use iris_emit_cmd because MI_STORE_DATA_IMM has a length of
6193 * 2 in genxml but it's actually variable length and we need 5 DWords.
6195 void *map
= iris_get_command_space(batch
, 4 * 5);
6196 _iris_pack_command(batch
, GENX(MI_STORE_DATA_IMM
), map
, sdi
) {
6197 sdi
.DWordLength
= 5 - 2;
6198 sdi
.Address
= rw_bo(bo
, offset
);
6199 sdi
.ImmediateData
= imm
;
6204 iris_copy_mem_mem(struct iris_batch
*batch
,
6205 struct iris_bo
*dst_bo
, uint32_t dst_offset
,
6206 struct iris_bo
*src_bo
, uint32_t src_offset
,
6209 /* MI_COPY_MEM_MEM operates on DWords. */
6210 assert(bytes
% 4 == 0);
6211 assert(dst_offset
% 4 == 0);
6212 assert(src_offset
% 4 == 0);
6214 for (unsigned i
= 0; i
< bytes
; i
+= 4) {
6215 iris_emit_cmd(batch
, GENX(MI_COPY_MEM_MEM
), cp
) {
6216 cp
.DestinationMemoryAddress
= rw_bo(dst_bo
, dst_offset
+ i
);
6217 cp
.SourceMemoryAddress
= ro_bo(src_bo
, src_offset
+ i
);
6222 /* ------------------------------------------------------------------- */
6225 flags_to_post_sync_op(uint32_t flags
)
6227 if (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
)
6228 return WriteImmediateData
;
6230 if (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
)
6231 return WritePSDepthCount
;
6233 if (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
)
6234 return WriteTimestamp
;
6240 * Do the given flags have a Post Sync or LRI Post Sync operation?
6242 static enum pipe_control_flags
6243 get_post_sync_flags(enum pipe_control_flags flags
)
6245 flags
&= PIPE_CONTROL_WRITE_IMMEDIATE
|
6246 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
6247 PIPE_CONTROL_WRITE_TIMESTAMP
|
6248 PIPE_CONTROL_LRI_POST_SYNC_OP
;
6250 /* Only one "Post Sync Op" is allowed, and it's mutually exclusive with
6251 * "LRI Post Sync Operation". So more than one bit set would be illegal.
6253 assert(util_bitcount(flags
) <= 1);
6258 #define IS_COMPUTE_PIPELINE(batch) (batch->name == IRIS_BATCH_COMPUTE)
6261 * Emit a series of PIPE_CONTROL commands, taking into account any
6262 * workarounds necessary to actually accomplish the caller's request.
6264 * Unless otherwise noted, spec quotations in this function come from:
6266 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
6267 * Restrictions for PIPE_CONTROL.
6269 * You should not use this function directly. Use the helpers in
6270 * iris_pipe_control.c instead, which may split the pipe control further.
6273 iris_emit_raw_pipe_control(struct iris_batch
*batch
,
6280 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
6281 enum pipe_control_flags post_sync_flags
= get_post_sync_flags(flags
);
6282 enum pipe_control_flags non_lri_post_sync_flags
=
6283 post_sync_flags
& ~PIPE_CONTROL_LRI_POST_SYNC_OP
;
6285 /* Recursive PIPE_CONTROL workarounds --------------------------------
6286 * (http://knowyourmeme.com/memes/xzibit-yo-dawg)
6288 * We do these first because we want to look at the original operation,
6289 * rather than any workarounds we set.
6291 if (GEN_GEN
== 9 && (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
)) {
6292 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
6293 * lists several workarounds:
6295 * "Project: SKL, KBL, BXT
6297 * If the VF Cache Invalidation Enable is set to a 1 in a
6298 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
6299 * sets to 0, with the VF Cache Invalidation Enable set to 0
6300 * needs to be sent prior to the PIPE_CONTROL with VF Cache
6301 * Invalidation Enable set to a 1."
6303 iris_emit_raw_pipe_control(batch
,
6304 "workaround: recursive VF cache invalidate",
6308 if (GEN_GEN
== 9 && IS_COMPUTE_PIPELINE(batch
) && post_sync_flags
) {
6309 /* Project: SKL / Argument: LRI Post Sync Operation [23]
6311 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
6312 * programmed prior to programming a PIPECONTROL command with "LRI
6313 * Post Sync Operation" in GPGPU mode of operation (i.e when
6314 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
6316 * The same text exists a few rows below for Post Sync Op.
6318 iris_emit_raw_pipe_control(batch
,
6319 "workaround: CS stall before gpgpu post-sync",
6320 PIPE_CONTROL_CS_STALL
, bo
, offset
, imm
);
6323 if (GEN_GEN
== 10 && (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
)) {
6325 * "Before sending a PIPE_CONTROL command with bit 12 set, SW must issue
6326 * another PIPE_CONTROL with Render Target Cache Flush Enable (bit 12)
6327 * = 0 and Pipe Control Flush Enable (bit 7) = 1"
6329 iris_emit_raw_pipe_control(batch
,
6330 "workaround: PC flush before RT flush",
6331 PIPE_CONTROL_FLUSH_ENABLE
, bo
, offset
, imm
);
6334 /* "Flush Types" workarounds ---------------------------------------------
6335 * We do these now because they may add post-sync operations or CS stalls.
6338 if (GEN_GEN
< 11 && flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) {
6339 /* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate
6341 * "'Post Sync Operation' must be enabled to 'Write Immediate Data' or
6342 * 'Write PS Depth Count' or 'Write Timestamp'."
6345 flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
6346 post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
6347 non_lri_post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
6348 bo
= batch
->screen
->workaround_bo
;
6352 /* #1130 from Gen10 workarounds page:
6354 * "Enable Depth Stall on every Post Sync Op if Render target Cache
6355 * Flush is not enabled in same PIPE CONTROL and Enable Pixel score
6356 * board stall if Render target cache flush is enabled."
6358 * Applicable to CNL B0 and C0 steppings only.
6360 * The wording here is unclear, and this workaround doesn't look anything
6361 * like the internal bug report recommendations, but leave it be for now...
6363 if (GEN_GEN
== 10) {
6364 if (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) {
6365 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
6366 } else if (flags
& non_lri_post_sync_flags
) {
6367 flags
|= PIPE_CONTROL_DEPTH_STALL
;
6371 if (flags
& PIPE_CONTROL_DEPTH_STALL
) {
6372 /* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable):
6374 * "This bit must be DISABLED for operations other than writing
6377 * This seems like nonsense. An Ivybridge workaround requires us to
6378 * emit a PIPE_CONTROL with a depth stall and write immediate post-sync
6379 * operation. Gen8+ requires us to emit depth stalls and depth cache
6380 * flushes together. So, it's hard to imagine this means anything other
6381 * than "we originally intended this to be used for PS_DEPTH_COUNT".
6383 * We ignore the supposed restriction and do nothing.
6387 if (flags
& (PIPE_CONTROL_RENDER_TARGET_FLUSH
|
6388 PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
6389 /* From the PIPE_CONTROL instruction table, bit 12 and bit 1:
6391 * "This bit must be DISABLED for End-of-pipe (Read) fences,
6392 * PS_DEPTH_COUNT or TIMESTAMP queries."
6394 * TODO: Implement end-of-pipe checking.
6396 assert(!(post_sync_flags
& (PIPE_CONTROL_WRITE_DEPTH_COUNT
|
6397 PIPE_CONTROL_WRITE_TIMESTAMP
)));
6400 if (GEN_GEN
< 11 && (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
6401 /* From the PIPE_CONTROL instruction table, bit 1:
6403 * "This bit is ignored if Depth Stall Enable is set.
6404 * Further, the render cache is not flushed even if Write Cache
6405 * Flush Enable bit is set."
6407 * We assert that the caller doesn't do this combination, to try and
6408 * prevent mistakes. It shouldn't hurt the GPU, though.
6410 * We skip this check on Gen11+ as the "Stall at Pixel Scoreboard"
6411 * and "Render Target Flush" combo is explicitly required for BTI
6412 * update workarounds.
6414 assert(!(flags
& (PIPE_CONTROL_DEPTH_STALL
|
6415 PIPE_CONTROL_RENDER_TARGET_FLUSH
)));
6418 /* PIPE_CONTROL page workarounds ------------------------------------- */
6420 if (GEN_GEN
<= 8 && (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
)) {
6421 /* From the PIPE_CONTROL page itself:
6424 * Restriction: Pipe_control with CS-stall bit set must be issued
6425 * before a pipe-control command that has the State Cache
6426 * Invalidate bit set."
6428 flags
|= PIPE_CONTROL_CS_STALL
;
6431 if (flags
& PIPE_CONTROL_FLUSH_LLC
) {
6432 /* From the PIPE_CONTROL instruction table, bit 26 (Flush LLC):
6435 * SW must always program Post-Sync Operation to "Write Immediate
6436 * Data" when Flush LLC is set."
6438 * For now, we just require the caller to do it.
6440 assert(flags
& PIPE_CONTROL_WRITE_IMMEDIATE
);
6443 /* "Post-Sync Operation" workarounds -------------------------------- */
6445 /* Project: All / Argument: Global Snapshot Count Reset [19]
6447 * "This bit must not be exercised on any product.
6448 * Requires stall bit ([20] of DW1) set."
6450 * We don't use this, so we just assert that it isn't used. The
6451 * PIPE_CONTROL instruction page indicates that they intended this
6452 * as a debug feature and don't think it is useful in production,
6453 * but it may actually be usable, should we ever want to.
6455 assert((flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) == 0);
6457 if (flags
& (PIPE_CONTROL_MEDIA_STATE_CLEAR
|
6458 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
)) {
6459 /* Project: All / Arguments:
6461 * - Generic Media State Clear [16]
6462 * - Indirect State Pointers Disable [16]
6464 * "Requires stall bit ([20] of DW1) set."
6466 * Also, the PIPE_CONTROL instruction table, bit 16 (Generic Media
6467 * State Clear) says:
6469 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
6470 * programmed prior to programming a PIPECONTROL command with "Media
6471 * State Clear" set in GPGPU mode of operation"
6473 * This is a subset of the earlier rule, so there's nothing to do.
6475 flags
|= PIPE_CONTROL_CS_STALL
;
6478 if (flags
& PIPE_CONTROL_STORE_DATA_INDEX
) {
6479 /* Project: All / Argument: Store Data Index
6481 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
6484 * For now, we just assert that the caller does this. We might want to
6485 * automatically add a write to the workaround BO...
6487 assert(non_lri_post_sync_flags
!= 0);
6490 if (flags
& PIPE_CONTROL_SYNC_GFDT
) {
6491 /* Project: All / Argument: Sync GFDT
6493 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
6494 * than '0' or 0x2520[13] must be set."
6496 * For now, we just assert that the caller does this.
6498 assert(non_lri_post_sync_flags
!= 0);
6501 if (flags
& PIPE_CONTROL_TLB_INVALIDATE
) {
6502 /* Project: IVB+ / Argument: TLB inv
6504 * "Requires stall bit ([20] of DW1) set."
6506 * Also, from the PIPE_CONTROL instruction table:
6509 * Post Sync Operation or CS stall must be set to ensure a TLB
6510 * invalidation occurs. Otherwise no cycle will occur to the TLB
6511 * cache to invalidate."
6513 * This is not a subset of the earlier rule, so there's nothing to do.
6515 flags
|= PIPE_CONTROL_CS_STALL
;
6518 if (GEN_GEN
== 9 && devinfo
->gt
== 4) {
6519 /* TODO: The big Skylake GT4 post sync op workaround */
6522 /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */
6524 if (IS_COMPUTE_PIPELINE(batch
)) {
6525 if (GEN_GEN
>= 9 && (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
)) {
6526 /* Project: SKL+ / Argument: Tex Invalidate
6527 * "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
6529 flags
|= PIPE_CONTROL_CS_STALL
;
6532 if (GEN_GEN
== 8 && (post_sync_flags
||
6533 (flags
& (PIPE_CONTROL_NOTIFY_ENABLE
|
6534 PIPE_CONTROL_DEPTH_STALL
|
6535 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
6536 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
6537 PIPE_CONTROL_DATA_CACHE_FLUSH
)))) {
6538 /* Project: BDW / Arguments:
6540 * - LRI Post Sync Operation [23]
6541 * - Post Sync Op [15:14]
6543 * - Depth Stall [13]
6544 * - Render Target Cache Flush [12]
6545 * - Depth Cache Flush [0]
6546 * - DC Flush Enable [5]
6548 * "Requires stall bit ([20] of DW) set for all GPGPU and Media
6551 flags
|= PIPE_CONTROL_CS_STALL
;
6553 /* Also, from the PIPE_CONTROL instruction table, bit 20:
6556 * This bit must be always set when PIPE_CONTROL command is
6557 * programmed by GPGPU and MEDIA workloads, except for the cases
6558 * when only Read Only Cache Invalidation bits are set (State
6559 * Cache Invalidation Enable, Instruction cache Invalidation
6560 * Enable, Texture Cache Invalidation Enable, Constant Cache
6561 * Invalidation Enable). This is to WA FFDOP CG issue, this WA
6562 * need not implemented when FF_DOP_CG is disable via "Fixed
6563 * Function DOP Clock Gate Disable" bit in RC_PSMI_CTRL register."
6565 * It sounds like we could avoid CS stalls in some cases, but we
6566 * don't currently bother. This list isn't exactly the list above,
6572 /* "Stall" workarounds ----------------------------------------------
6573 * These have to come after the earlier ones because we may have added
6574 * some additional CS stalls above.
6577 if (GEN_GEN
< 9 && (flags
& PIPE_CONTROL_CS_STALL
)) {
6578 /* Project: PRE-SKL, VLV, CHV
6580 * "[All Stepping][All SKUs]:
6582 * One of the following must also be set:
6584 * - Render Target Cache Flush Enable ([12] of DW1)
6585 * - Depth Cache Flush Enable ([0] of DW1)
6586 * - Stall at Pixel Scoreboard ([1] of DW1)
6587 * - Depth Stall ([13] of DW1)
6588 * - Post-Sync Operation ([13] of DW1)
6589 * - DC Flush Enable ([5] of DW1)"
6591 * If we don't already have one of those bits set, we choose to add
6592 * "Stall at Pixel Scoreboard". Some of the other bits require a
6593 * CS stall as a workaround (see above), which would send us into
6594 * an infinite recursion of PIPE_CONTROLs. "Stall at Pixel Scoreboard"
6595 * appears to be safe, so we choose that.
6597 const uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
6598 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
6599 PIPE_CONTROL_WRITE_IMMEDIATE
|
6600 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
6601 PIPE_CONTROL_WRITE_TIMESTAMP
|
6602 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
6603 PIPE_CONTROL_DEPTH_STALL
|
6604 PIPE_CONTROL_DATA_CACHE_FLUSH
;
6605 if (!(flags
& wa_bits
))
6606 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
6609 /* Emit --------------------------------------------------------------- */
6611 if (INTEL_DEBUG
& DEBUG_PIPE_CONTROL
) {
6613 " PC [%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%"PRIx64
"]: %s\n",
6614 (flags
& PIPE_CONTROL_FLUSH_ENABLE
) ? "PipeCon " : "",
6615 (flags
& PIPE_CONTROL_CS_STALL
) ? "CS " : "",
6616 (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
) ? "Scoreboard " : "",
6617 (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) ? "VF " : "",
6618 (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) ? "RT " : "",
6619 (flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
) ? "Const " : "",
6620 (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
) ? "TC " : "",
6621 (flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
) ? "DC " : "",
6622 (flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
) ? "ZFlush " : "",
6623 (flags
& PIPE_CONTROL_DEPTH_STALL
) ? "ZStall " : "",
6624 (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
) ? "State " : "",
6625 (flags
& PIPE_CONTROL_TLB_INVALIDATE
) ? "TLB " : "",
6626 (flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
) ? "Inst " : "",
6627 (flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
) ? "MediaClear " : "",
6628 (flags
& PIPE_CONTROL_NOTIFY_ENABLE
) ? "Notify " : "",
6629 (flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) ?
6631 (flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
) ?
6633 (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
) ? "WriteImm " : "",
6634 (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
) ? "WriteZCount " : "",
6635 (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
) ? "WriteTimestamp " : "",
6639 iris_emit_cmd(batch
, GENX(PIPE_CONTROL
), pc
) {
6640 pc
.LRIPostSyncOperation
= NoLRIOperation
;
6641 pc
.PipeControlFlushEnable
= flags
& PIPE_CONTROL_FLUSH_ENABLE
;
6642 pc
.DCFlushEnable
= flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
;
6643 pc
.StoreDataIndex
= 0;
6644 pc
.CommandStreamerStallEnable
= flags
& PIPE_CONTROL_CS_STALL
;
6645 pc
.GlobalSnapshotCountReset
=
6646 flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
;
6647 pc
.TLBInvalidate
= flags
& PIPE_CONTROL_TLB_INVALIDATE
;
6648 pc
.GenericMediaStateClear
= flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
;
6649 pc
.StallAtPixelScoreboard
= flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
;
6650 pc
.RenderTargetCacheFlushEnable
=
6651 flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
;
6652 pc
.DepthCacheFlushEnable
= flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
6653 pc
.StateCacheInvalidationEnable
=
6654 flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
6655 pc
.VFCacheInvalidationEnable
= flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
6656 pc
.ConstantCacheInvalidationEnable
=
6657 flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
6658 pc
.PostSyncOperation
= flags_to_post_sync_op(flags
);
6659 pc
.DepthStallEnable
= flags
& PIPE_CONTROL_DEPTH_STALL
;
6660 pc
.InstructionCacheInvalidateEnable
=
6661 flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
;
6662 pc
.NotifyEnable
= flags
& PIPE_CONTROL_NOTIFY_ENABLE
;
6663 pc
.IndirectStatePointersDisable
=
6664 flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
;
6665 pc
.TextureCacheInvalidationEnable
=
6666 flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
6667 pc
.Address
= rw_bo(bo
, offset
);
6668 pc
.ImmediateData
= imm
;
6673 genX(emit_urb_setup
)(struct iris_context
*ice
,
6674 struct iris_batch
*batch
,
6675 const unsigned size
[4],
6676 bool tess_present
, bool gs_present
)
6678 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
6679 const unsigned push_size_kB
= 32;
6680 unsigned entries
[4];
6683 ice
->shaders
.last_vs_entry_size
= size
[MESA_SHADER_VERTEX
];
6685 gen_get_urb_config(devinfo
, 1024 * push_size_kB
,
6686 1024 * ice
->shaders
.urb_size
,
6687 tess_present
, gs_present
,
6688 size
, entries
, start
);
6690 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
6691 iris_emit_cmd(batch
, GENX(3DSTATE_URB_VS
), urb
) {
6692 urb
._3DCommandSubOpcode
+= i
;
6693 urb
.VSURBStartingAddress
= start
[i
];
6694 urb
.VSURBEntryAllocationSize
= size
[i
] - 1;
6695 urb
.VSNumberofURBEntries
= entries
[i
];
6702 * Preemption on Gen9 has to be enabled or disabled in various cases.
6704 * See these workarounds for preemption:
6705 * - WaDisableMidObjectPreemptionForGSLineStripAdj
6706 * - WaDisableMidObjectPreemptionForTrifanOrPolygon
6707 * - WaDisableMidObjectPreemptionForLineLoop
6710 * We don't put this in the vtable because it's only used on Gen9.
6713 gen9_toggle_preemption(struct iris_context
*ice
,
6714 struct iris_batch
*batch
,
6715 const struct pipe_draw_info
*draw
)
6717 struct iris_genx_state
*genx
= ice
->state
.genx
;
6718 bool object_preemption
= true;
6720 /* WaDisableMidObjectPreemptionForGSLineStripAdj
6722 * "WA: Disable mid-draw preemption when draw-call is a linestrip_adj
6723 * and GS is enabled."
6725 if (draw
->mode
== PIPE_PRIM_LINE_STRIP_ADJACENCY
&&
6726 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
])
6727 object_preemption
= false;
6729 /* WaDisableMidObjectPreemptionForTrifanOrPolygon
6731 * "TriFan miscompare in Execlist Preemption test. Cut index that is
6732 * on a previous context. End the previous, the resume another context
6733 * with a tri-fan or polygon, and the vertex count is corrupted. If we
6734 * prempt again we will cause corruption.
6736 * WA: Disable mid-draw preemption when draw-call has a tri-fan."
6738 if (draw
->mode
== PIPE_PRIM_TRIANGLE_FAN
)
6739 object_preemption
= false;
6741 /* WaDisableMidObjectPreemptionForLineLoop
6743 * "VF Stats Counters Missing a vertex when preemption enabled.
6745 * WA: Disable mid-draw preemption when the draw uses a lineloop
6748 if (draw
->mode
== PIPE_PRIM_LINE_LOOP
)
6749 object_preemption
= false;
6753 * "VF is corrupting GAFS data when preempted on an instance boundary
6754 * and replayed with instancing enabled.
6756 * WA: Disable preemption when using instanceing."
6758 if (draw
->instance_count
> 1)
6759 object_preemption
= false;
6761 if (genx
->object_preemption
!= object_preemption
) {
6762 iris_enable_obj_preemption(batch
, object_preemption
);
6763 genx
->object_preemption
= object_preemption
;
6769 iris_lost_genx_state(struct iris_context
*ice
, struct iris_batch
*batch
)
6771 struct iris_genx_state
*genx
= ice
->state
.genx
;
6773 memset(genx
->last_index_buffer
, 0, sizeof(genx
->last_index_buffer
));
6777 iris_emit_mi_report_perf_count(struct iris_batch
*batch
,
6779 uint32_t offset_in_bytes
,
6782 iris_emit_cmd(batch
, GENX(MI_REPORT_PERF_COUNT
), mi_rpc
) {
6783 mi_rpc
.MemoryAddress
= rw_bo(bo
, offset_in_bytes
);
6784 mi_rpc
.ReportID
= report_id
;
6789 * Update the pixel hashing modes that determine the balancing of PS threads
6790 * across subslices and slices.
6792 * \param width Width bound of the rendering area (already scaled down if \p
6793 * scale is greater than 1).
6794 * \param height Height bound of the rendering area (already scaled down if \p
6795 * scale is greater than 1).
6796 * \param scale The number of framebuffer samples that could potentially be
6797 * affected by an individual channel of the PS thread. This is
6798 * typically one for single-sampled rendering, but for operations
6799 * like CCS resolves and fast clears a single PS invocation may
6800 * update a huge number of pixels, in which case a finer
6801 * balancing is desirable in order to maximally utilize the
6802 * bandwidth available. UINT_MAX can be used as shorthand for
6803 * "finest hashing mode available".
6806 genX(emit_hashing_mode
)(struct iris_context
*ice
, struct iris_batch
*batch
,
6807 unsigned width
, unsigned height
, unsigned scale
)
6810 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
6811 const unsigned slice_hashing
[] = {
6812 /* Because all Gen9 platforms with more than one slice require
6813 * three-way subslice hashing, a single "normal" 16x16 slice hashing
6814 * block is guaranteed to suffer from substantial imbalance, with one
6815 * subslice receiving twice as much work as the other two in the
6818 * The performance impact of that would be particularly severe when
6819 * three-way hashing is also in use for slice balancing (which is the
6820 * case for all Gen9 GT4 platforms), because one of the slices
6821 * receives one every three 16x16 blocks in either direction, which
6822 * is roughly the periodicity of the underlying subslice imbalance
6823 * pattern ("roughly" because in reality the hardware's
6824 * implementation of three-way hashing doesn't do exact modulo 3
6825 * arithmetic, which somewhat decreases the magnitude of this effect
6826 * in practice). This leads to a systematic subslice imbalance
6827 * within that slice regardless of the size of the primitive. The
6828 * 32x32 hashing mode guarantees that the subslice imbalance within a
6829 * single slice hashing block is minimal, largely eliminating this
6833 /* Finest slice hashing mode available. */
6836 const unsigned subslice_hashing
[] = {
6837 /* 16x16 would provide a slight cache locality benefit especially
6838 * visible in the sampler L1 cache efficiency of low-bandwidth
6839 * non-LLC platforms, but it comes at the cost of greater subslice
6840 * imbalance for primitives of dimensions approximately intermediate
6841 * between 16x4 and 16x16.
6844 /* Finest subslice hashing mode available. */
6847 /* Dimensions of the smallest hashing block of a given hashing mode. If
6848 * the rendering area is smaller than this there can't possibly be any
6849 * benefit from switching to this mode, so we optimize out the
6852 const unsigned min_size
[][2] = {
6856 const unsigned idx
= scale
> 1;
6858 if (width
> min_size
[idx
][0] || height
> min_size
[idx
][1]) {
6861 iris_pack_state(GENX(GT_MODE
), >_mode
, reg
) {
6862 reg
.SliceHashing
= (devinfo
->num_slices
> 1 ? slice_hashing
[idx
] : 0);
6863 reg
.SliceHashingMask
= (devinfo
->num_slices
> 1 ? -1 : 0);
6864 reg
.SubsliceHashing
= subslice_hashing
[idx
];
6865 reg
.SubsliceHashingMask
= -1;
6868 iris_emit_raw_pipe_control(batch
,
6869 "workaround: CS stall before GT_MODE LRI",
6870 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
6871 PIPE_CONTROL_CS_STALL
,
6874 iris_emit_lri(batch
, GT_MODE
, gt_mode
);
6876 ice
->state
.current_hash_scale
= scale
;
6882 genX(init_state
)(struct iris_context
*ice
)
6884 struct pipe_context
*ctx
= &ice
->ctx
;
6885 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
6887 ctx
->create_blend_state
= iris_create_blend_state
;
6888 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
6889 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
6890 ctx
->create_sampler_state
= iris_create_sampler_state
;
6891 ctx
->create_sampler_view
= iris_create_sampler_view
;
6892 ctx
->create_surface
= iris_create_surface
;
6893 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
6894 ctx
->bind_blend_state
= iris_bind_blend_state
;
6895 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
6896 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
6897 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
6898 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
6899 ctx
->delete_blend_state
= iris_delete_state
;
6900 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
6901 ctx
->delete_rasterizer_state
= iris_delete_state
;
6902 ctx
->delete_sampler_state
= iris_delete_state
;
6903 ctx
->delete_vertex_elements_state
= iris_delete_state
;
6904 ctx
->set_blend_color
= iris_set_blend_color
;
6905 ctx
->set_clip_state
= iris_set_clip_state
;
6906 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
6907 ctx
->set_shader_buffers
= iris_set_shader_buffers
;
6908 ctx
->set_shader_images
= iris_set_shader_images
;
6909 ctx
->set_sampler_views
= iris_set_sampler_views
;
6910 ctx
->set_tess_state
= iris_set_tess_state
;
6911 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
6912 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
6913 ctx
->set_sample_mask
= iris_set_sample_mask
;
6914 ctx
->set_scissor_states
= iris_set_scissor_states
;
6915 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
6916 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
6917 ctx
->set_viewport_states
= iris_set_viewport_states
;
6918 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
6919 ctx
->surface_destroy
= iris_surface_destroy
;
6920 ctx
->draw_vbo
= iris_draw_vbo
;
6921 ctx
->launch_grid
= iris_launch_grid
;
6922 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
6923 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
6924 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;
6926 ice
->vtbl
.destroy_state
= iris_destroy_state
;
6927 ice
->vtbl
.init_render_context
= iris_init_render_context
;
6928 ice
->vtbl
.init_compute_context
= iris_init_compute_context
;
6929 ice
->vtbl
.upload_render_state
= iris_upload_render_state
;
6930 ice
->vtbl
.update_surface_base_address
= iris_update_surface_base_address
;
6931 ice
->vtbl
.upload_compute_state
= iris_upload_compute_state
;
6932 ice
->vtbl
.emit_raw_pipe_control
= iris_emit_raw_pipe_control
;
6933 ice
->vtbl
.emit_mi_report_perf_count
= iris_emit_mi_report_perf_count
;
6934 ice
->vtbl
.rebind_buffer
= iris_rebind_buffer
;
6935 ice
->vtbl
.load_register_reg32
= iris_load_register_reg32
;
6936 ice
->vtbl
.load_register_reg64
= iris_load_register_reg64
;
6937 ice
->vtbl
.load_register_imm32
= iris_load_register_imm32
;
6938 ice
->vtbl
.load_register_imm64
= iris_load_register_imm64
;
6939 ice
->vtbl
.load_register_mem32
= iris_load_register_mem32
;
6940 ice
->vtbl
.load_register_mem64
= iris_load_register_mem64
;
6941 ice
->vtbl
.store_register_mem32
= iris_store_register_mem32
;
6942 ice
->vtbl
.store_register_mem64
= iris_store_register_mem64
;
6943 ice
->vtbl
.store_data_imm32
= iris_store_data_imm32
;
6944 ice
->vtbl
.store_data_imm64
= iris_store_data_imm64
;
6945 ice
->vtbl
.copy_mem_mem
= iris_copy_mem_mem
;
6946 ice
->vtbl
.derived_program_state_size
= iris_derived_program_state_size
;
6947 ice
->vtbl
.store_derived_program_state
= iris_store_derived_program_state
;
6948 ice
->vtbl
.create_so_decl_list
= iris_create_so_decl_list
;
6949 ice
->vtbl
.populate_vs_key
= iris_populate_vs_key
;
6950 ice
->vtbl
.populate_tcs_key
= iris_populate_tcs_key
;
6951 ice
->vtbl
.populate_tes_key
= iris_populate_tes_key
;
6952 ice
->vtbl
.populate_gs_key
= iris_populate_gs_key
;
6953 ice
->vtbl
.populate_fs_key
= iris_populate_fs_key
;
6954 ice
->vtbl
.populate_cs_key
= iris_populate_cs_key
;
6955 ice
->vtbl
.mocs
= mocs
;
6956 ice
->vtbl
.lost_genx_state
= iris_lost_genx_state
;
6958 ice
->state
.dirty
= ~0ull;
6960 ice
->state
.statistics_counters_enabled
= true;
6962 ice
->state
.sample_mask
= 0xffff;
6963 ice
->state
.num_viewports
= 1;
6964 ice
->state
.prim_mode
= PIPE_PRIM_MAX
;
6965 ice
->state
.genx
= calloc(1, sizeof(struct iris_genx_state
));
6966 ice
->draw
.derived_params
.drawid
= -1;
6968 /* Make a 1x1x1 null surface for unbound textures */
6969 void *null_surf_map
=
6970 upload_state(ice
->state
.surface_uploader
, &ice
->state
.unbound_tex
,
6971 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
6972 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
, isl_extent3d(1, 1, 1));
6973 ice
->state
.unbound_tex
.offset
+=
6974 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.unbound_tex
.res
));
6976 /* Default all scissor rectangles to be empty regions. */
6977 for (int i
= 0; i
< IRIS_MAX_VIEWPORTS
; i
++) {
6978 ice
->state
.scissors
[i
] = (struct pipe_scissor_state
) {
6979 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,