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gallium: add PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include <nvif/class.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
29
30 #include "nouveau_vp3_video.h"
31
32 #include "nvc0/nvc0_context.h"
33 #include "nvc0/nvc0_screen.h"
34
35 #include "nvc0/mme/com9097.mme.h"
36 #include "nvc0/mme/com90c0.mme.h"
37
38 #include "nv50/g80_texture.xml.h"
39
40 static boolean
41 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
42 enum pipe_format format,
43 enum pipe_texture_target target,
44 unsigned sample_count,
45 unsigned bindings)
46 {
47 const struct util_format_description *desc = util_format_description(format);
48
49 if (sample_count > 8)
50 return false;
51 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
52 return false;
53
54 /* Short-circuit the rest of the logic -- this is used by the state tracker
55 * to determine valid MS levels in a no-attachments scenario.
56 */
57 if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
58 return true;
59
60 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
61 if (util_format_get_blocksizebits(format) == 3 * 32)
62 return false;
63
64 if (bindings & PIPE_BIND_LINEAR)
65 if (util_format_is_depth_or_stencil(format) ||
66 (target != PIPE_TEXTURE_1D &&
67 target != PIPE_TEXTURE_2D &&
68 target != PIPE_TEXTURE_RECT) ||
69 sample_count > 1)
70 return false;
71
72 /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
73 */
74 if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
75 desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
76 /* The claim is that this should work on GM107 but it doesn't. Need to
77 * test further and figure out if it's a nouveau issue or a HW one.
78 nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
79 */
80 nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
81 return false;
82
83 /* shared is always supported */
84 bindings &= ~(PIPE_BIND_LINEAR |
85 PIPE_BIND_SHARED);
86
87 if (bindings & PIPE_BIND_SHADER_IMAGE) {
88 if (format == PIPE_FORMAT_B8G8R8A8_UNORM &&
89 nouveau_screen(pscreen)->class_3d < NVE4_3D_CLASS) {
90 /* This should work on Fermi, but for currently unknown reasons it
91 * does not and results in breaking reads from pbos. */
92 return false;
93 }
94 }
95
96 return (( nvc0_format_table[format].usage |
97 nvc0_vertex_format[format].usage) & bindings) == bindings;
98 }
99
100 static int
101 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
102 {
103 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
104 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
105
106 switch (param) {
107 /* non-boolean caps */
108 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
109 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
110 return 15;
111 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
112 return 12;
113 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
114 return 2048;
115 case PIPE_CAP_MIN_TEXEL_OFFSET:
116 return -8;
117 case PIPE_CAP_MAX_TEXEL_OFFSET:
118 return 7;
119 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
120 return -32;
121 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
122 return 31;
123 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
124 return 128 * 1024 * 1024;
125 case PIPE_CAP_GLSL_FEATURE_LEVEL:
126 return 430;
127 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
128 return 140;
129 case PIPE_CAP_MAX_RENDER_TARGETS:
130 return 8;
131 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
132 return 1;
133 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
134 return 4;
135 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
136 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
137 return 128;
138 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
139 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
140 return 1024;
141 case PIPE_CAP_MAX_VERTEX_STREAMS:
142 return 4;
143 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
144 return 2048;
145 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
146 return 256;
147 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
148 if (class_3d < GM107_3D_CLASS)
149 return 256; /* IMAGE bindings require alignment to 256 */
150 return 16;
151 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
152 return 16;
153 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
154 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
155 case PIPE_CAP_MAX_VIEWPORTS:
156 return NVC0_MAX_VIEWPORTS;
157 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
158 return 4;
159 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
160 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
161 case PIPE_CAP_ENDIANNESS:
162 return PIPE_ENDIAN_LITTLE;
163 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
164 return 30;
165 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
166 return NVC0_MAX_WINDOW_RECTANGLES;
167 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
168 return class_3d >= GM200_3D_CLASS ? 8 : 0;
169
170 /* supported caps */
171 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
172 case PIPE_CAP_TEXTURE_SWIZZLE:
173 case PIPE_CAP_NPOT_TEXTURES:
174 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
175 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
176 case PIPE_CAP_ANISOTROPIC_FILTER:
177 case PIPE_CAP_SEAMLESS_CUBE_MAP:
178 case PIPE_CAP_CUBE_MAP_ARRAY:
179 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
180 case PIPE_CAP_TEXTURE_MULTISAMPLE:
181 case PIPE_CAP_DEPTH_CLIP_DISABLE:
182 case PIPE_CAP_POINT_SPRITE:
183 case PIPE_CAP_TGSI_TEXCOORD:
184 case PIPE_CAP_SM3:
185 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
186 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
187 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
188 case PIPE_CAP_QUERY_TIMESTAMP:
189 case PIPE_CAP_QUERY_TIME_ELAPSED:
190 case PIPE_CAP_OCCLUSION_QUERY:
191 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
192 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
193 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
194 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
195 case PIPE_CAP_INDEP_BLEND_ENABLE:
196 case PIPE_CAP_INDEP_BLEND_FUNC:
197 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
198 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
199 case PIPE_CAP_PRIMITIVE_RESTART:
200 case PIPE_CAP_TGSI_INSTANCEID:
201 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
202 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
203 case PIPE_CAP_CONDITIONAL_RENDER:
204 case PIPE_CAP_TEXTURE_BARRIER:
205 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
206 case PIPE_CAP_START_INSTANCE:
207 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
208 case PIPE_CAP_DRAW_INDIRECT:
209 case PIPE_CAP_USER_VERTEX_BUFFERS:
210 case PIPE_CAP_TEXTURE_QUERY_LOD:
211 case PIPE_CAP_SAMPLE_SHADING:
212 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
213 case PIPE_CAP_TEXTURE_GATHER_SM5:
214 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
215 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
216 case PIPE_CAP_SAMPLER_VIEW_TARGET:
217 case PIPE_CAP_CLIP_HALFZ:
218 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
219 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
220 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
221 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
222 case PIPE_CAP_DEPTH_BOUNDS_TEST:
223 case PIPE_CAP_TGSI_TXQS:
224 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
225 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
226 case PIPE_CAP_SHAREABLE_SHADERS:
227 case PIPE_CAP_CLEAR_TEXTURE:
228 case PIPE_CAP_DRAW_PARAMETERS:
229 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
230 case PIPE_CAP_MULTI_DRAW_INDIRECT:
231 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
232 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
233 case PIPE_CAP_QUERY_BUFFER_OBJECT:
234 case PIPE_CAP_INVALIDATE_BUFFER:
235 case PIPE_CAP_STRING_MARKER:
236 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
237 case PIPE_CAP_CULL_DISTANCE:
238 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
239 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
240 case PIPE_CAP_TGSI_VOTE:
241 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
242 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
243 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
244 case PIPE_CAP_DOUBLES:
245 case PIPE_CAP_INT64:
246 case PIPE_CAP_TGSI_TEX_TXF_LZ:
247 case PIPE_CAP_TGSI_CLOCK:
248 case PIPE_CAP_COMPUTE:
249 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
250 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
251 case PIPE_CAP_QUERY_SO_OVERFLOW:
252 return 1;
253 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
254 return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
255 case PIPE_CAP_TGSI_FS_FBFETCH:
256 return class_3d >= NVE4_3D_CLASS; /* needs testing on fermi */
257 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
258 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
259 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
260 case PIPE_CAP_POST_DEPTH_COVERAGE:
261 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
262 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
263 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
264 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
265 return class_3d >= GM200_3D_CLASS;
266 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
267 return class_3d >= GP100_3D_CLASS;
268 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
269 case PIPE_CAP_TGSI_BALLOT:
270 case PIPE_CAP_BINDLESS_TEXTURE:
271 return class_3d >= NVE4_3D_CLASS;
272
273 /* unsupported caps */
274 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
275 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
276 case PIPE_CAP_SHADER_STENCIL_EXPORT:
277 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
278 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
279 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
280 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
281 case PIPE_CAP_FAKE_SW_MSAA:
282 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
283 case PIPE_CAP_VERTEXID_NOBASE:
284 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
285 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
286 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
287 case PIPE_CAP_GENERATE_MIPMAP:
288 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
289 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
290 case PIPE_CAP_QUERY_MEMORY_INFO:
291 case PIPE_CAP_PCI_GROUP:
292 case PIPE_CAP_PCI_BUS:
293 case PIPE_CAP_PCI_DEVICE:
294 case PIPE_CAP_PCI_FUNCTION:
295 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
296 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
297 case PIPE_CAP_NATIVE_FENCE_FD:
298 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
299 case PIPE_CAP_INT64_DIVMOD:
300 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
301 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
302 case PIPE_CAP_MEMOBJ:
303 case PIPE_CAP_LOAD_CONSTBUF:
304 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
305 case PIPE_CAP_TILE_RASTER_ORDER:
306 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
307 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
308 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
309 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
310 case PIPE_CAP_FENCE_SIGNAL:
311 case PIPE_CAP_CONSTBUF0_FLAGS:
312 case PIPE_CAP_PACKED_UNIFORMS:
313 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
314 return 0;
315
316 case PIPE_CAP_VENDOR_ID:
317 return 0x10de;
318 case PIPE_CAP_DEVICE_ID: {
319 uint64_t device_id;
320 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
321 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
322 return -1;
323 }
324 return device_id;
325 }
326 case PIPE_CAP_ACCELERATED:
327 return 1;
328 case PIPE_CAP_VIDEO_MEMORY:
329 return dev->vram_size >> 20;
330 case PIPE_CAP_UMA:
331 return 0;
332 }
333
334 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
335 return 0;
336 }
337
338 static int
339 nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
340 enum pipe_shader_type shader,
341 enum pipe_shader_cap param)
342 {
343 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
344
345 switch (shader) {
346 case PIPE_SHADER_VERTEX:
347 case PIPE_SHADER_GEOMETRY:
348 case PIPE_SHADER_FRAGMENT:
349 case PIPE_SHADER_COMPUTE:
350 case PIPE_SHADER_TESS_CTRL:
351 case PIPE_SHADER_TESS_EVAL:
352 break;
353 default:
354 return 0;
355 }
356
357 switch (param) {
358 case PIPE_SHADER_CAP_PREFERRED_IR:
359 return PIPE_SHADER_IR_TGSI;
360 case PIPE_SHADER_CAP_SUPPORTED_IRS:
361 return 1 << PIPE_SHADER_IR_TGSI;
362 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
363 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
364 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
365 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
366 return 16384;
367 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
368 return 16;
369 case PIPE_SHADER_CAP_MAX_INPUTS:
370 if (shader == PIPE_SHADER_VERTEX)
371 return 32;
372 /* NOTE: These only count our slots for GENERIC varyings.
373 * The address space may be larger, but the actual hard limit seems to be
374 * less than what the address space layout permits, so don't add TEXCOORD,
375 * COLOR, etc. here.
376 */
377 if (shader == PIPE_SHADER_FRAGMENT)
378 return 0x1f0 / 16;
379 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
380 * and excludes 0x60 per-patch inputs.
381 */
382 return 0x200 / 16;
383 case PIPE_SHADER_CAP_MAX_OUTPUTS:
384 return 32;
385 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
386 return NVC0_MAX_CONSTBUF_SIZE;
387 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
388 return NVC0_MAX_PIPE_CONSTBUFS;
389 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
390 return shader != PIPE_SHADER_FRAGMENT;
391 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
392 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
393 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
394 return 1;
395 case PIPE_SHADER_CAP_MAX_TEMPS:
396 return NVC0_CAP_MAX_PROGRAM_TEMPS;
397 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
398 return 1;
399 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
400 return 1;
401 case PIPE_SHADER_CAP_SUBROUTINES:
402 return 1;
403 case PIPE_SHADER_CAP_INTEGERS:
404 return 1;
405 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
406 return 1;
407 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
408 return 1;
409 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
410 return 1;
411 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
412 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
413 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
414 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
415 case PIPE_SHADER_CAP_INT64_ATOMICS:
416 case PIPE_SHADER_CAP_FP16:
417 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
418 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
419 return 0;
420 case PIPE_SHADER_CAP_SCALAR_ISA:
421 return 1;
422 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
423 return NVC0_MAX_BUFFERS;
424 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
425 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
426 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
427 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
428 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
429 return 32;
430 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
431 if (class_3d >= NVE4_3D_CLASS)
432 return NVC0_MAX_IMAGES;
433 if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
434 return NVC0_MAX_IMAGES;
435 return 0;
436 default:
437 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
438 return 0;
439 }
440 }
441
442 static float
443 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
444 {
445 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
446
447 switch (param) {
448 case PIPE_CAPF_MAX_LINE_WIDTH:
449 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
450 return 10.0f;
451 case PIPE_CAPF_MAX_POINT_WIDTH:
452 return 63.0f;
453 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
454 return 63.375f;
455 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
456 return 16.0f;
457 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
458 return 15.0f;
459 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
460 return 0.0f;
461 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
462 return class_3d >= GM200_3D_CLASS ? 0.75f : 0.0f;
463 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
464 return class_3d >= GM200_3D_CLASS ? 0.25f : 0.0f;
465 }
466
467 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
468 return 0.0f;
469 }
470
471 static int
472 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
473 enum pipe_shader_ir ir_type,
474 enum pipe_compute_cap param, void *data)
475 {
476 struct nvc0_screen *screen = nvc0_screen(pscreen);
477 const uint16_t obj_class = screen->compute->oclass;
478
479 #define RET(x) do { \
480 if (data) \
481 memcpy(data, x, sizeof(x)); \
482 return sizeof(x); \
483 } while (0)
484
485 switch (param) {
486 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
487 RET((uint64_t []) { 3 });
488 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
489 if (obj_class >= NVE4_COMPUTE_CLASS) {
490 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
491 } else {
492 RET(((uint64_t []) { 65535, 65535, 65535 }));
493 }
494 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
495 RET(((uint64_t []) { 1024, 1024, 64 }));
496 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
497 RET((uint64_t []) { 1024 });
498 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
499 if (obj_class >= NVE4_COMPUTE_CLASS) {
500 RET((uint64_t []) { 1024 });
501 } else {
502 RET((uint64_t []) { 512 });
503 }
504 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
505 RET((uint64_t []) { 1ULL << 40 });
506 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
507 switch (obj_class) {
508 case GM200_COMPUTE_CLASS:
509 RET((uint64_t []) { 96 << 10 });
510 break;
511 case GM107_COMPUTE_CLASS:
512 RET((uint64_t []) { 64 << 10 });
513 break;
514 default:
515 RET((uint64_t []) { 48 << 10 });
516 break;
517 }
518 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
519 RET((uint64_t []) { 512 << 10 });
520 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
521 RET((uint64_t []) { 4096 });
522 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
523 RET((uint32_t []) { 32 });
524 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
525 RET((uint64_t []) { 1ULL << 40 });
526 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
527 RET((uint32_t []) { 0 });
528 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
529 RET((uint32_t []) { screen->mp_count_compute });
530 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
531 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
532 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
533 RET((uint32_t []) { 64 });
534 default:
535 return 0;
536 }
537
538 #undef RET
539 }
540
541 static void
542 nvc0_screen_get_sample_pixel_grid(struct pipe_screen *pscreen,
543 unsigned sample_count,
544 unsigned *width, unsigned *height)
545 {
546 switch (sample_count) {
547 case 0:
548 case 1:
549 /* this could be 4x4, but the GL state tracker makes it difficult to
550 * create a 1x MSAA texture and smaller grids save CB space */
551 *width = 2;
552 *height = 4;
553 break;
554 case 2:
555 *width = 2;
556 *height = 4;
557 break;
558 case 4:
559 *width = 2;
560 *height = 2;
561 break;
562 case 8:
563 *width = 1;
564 *height = 2;
565 break;
566 default:
567 assert(0);
568 }
569 }
570
571 static void
572 nvc0_screen_destroy(struct pipe_screen *pscreen)
573 {
574 struct nvc0_screen *screen = nvc0_screen(pscreen);
575
576 if (!nouveau_drm_screen_unref(&screen->base))
577 return;
578
579 if (screen->base.fence.current) {
580 struct nouveau_fence *current = NULL;
581
582 /* nouveau_fence_wait will create a new current fence, so wait on the
583 * _current_ one, and remove both.
584 */
585 nouveau_fence_ref(screen->base.fence.current, &current);
586 nouveau_fence_wait(current, NULL);
587 nouveau_fence_ref(NULL, &current);
588 nouveau_fence_ref(NULL, &screen->base.fence.current);
589 }
590 if (screen->base.pushbuf)
591 screen->base.pushbuf->user_priv = NULL;
592
593 if (screen->blitter)
594 nvc0_blitter_destroy(screen);
595 if (screen->pm.prog) {
596 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
597 nvc0_program_destroy(NULL, screen->pm.prog);
598 FREE(screen->pm.prog);
599 }
600
601 nouveau_bo_ref(NULL, &screen->text);
602 nouveau_bo_ref(NULL, &screen->uniform_bo);
603 nouveau_bo_ref(NULL, &screen->tls);
604 nouveau_bo_ref(NULL, &screen->txc);
605 nouveau_bo_ref(NULL, &screen->fence.bo);
606 nouveau_bo_ref(NULL, &screen->poly_cache);
607
608 nouveau_heap_destroy(&screen->lib_code);
609 nouveau_heap_destroy(&screen->text_heap);
610
611 FREE(screen->default_tsc);
612 FREE(screen->tic.entries);
613
614 nouveau_object_del(&screen->eng3d);
615 nouveau_object_del(&screen->eng2d);
616 nouveau_object_del(&screen->m2mf);
617 nouveau_object_del(&screen->compute);
618 nouveau_object_del(&screen->nvsw);
619
620 nouveau_screen_fini(&screen->base);
621
622 FREE(screen);
623 }
624
625 static int
626 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
627 unsigned size, const uint32_t *data)
628 {
629 struct nouveau_pushbuf *push = screen->base.pushbuf;
630
631 size /= 4;
632
633 assert((pos + size) <= 0x800);
634
635 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
636 PUSH_DATA (push, (m - 0x3800) / 8);
637 PUSH_DATA (push, pos);
638 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
639 PUSH_DATA (push, pos);
640 PUSH_DATAp(push, data, size);
641
642 return pos + size;
643 }
644
645 static void
646 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
647 {
648 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
649 PUSH_DATA (push, 0xff);
650 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
651 PUSH_DATA (push, 0xff);
652 PUSH_DATA (push, 0xff);
653 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
654 PUSH_DATA (push, 0xff);
655 PUSH_DATA (push, 0xff);
656 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
657 PUSH_DATA (push, 0x3f);
658
659 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
660 PUSH_DATA (push, (3 << 16) | 3);
661 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
662 PUSH_DATA (push, (2 << 16) | 2);
663
664 if (obj_class < GM107_3D_CLASS) {
665 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
666 PUSH_DATA (push, 0);
667 }
668 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
669 PUSH_DATA (push, 0x10);
670 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
671 PUSH_DATA (push, 0x10);
672 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
673 PUSH_DATA (push, 0x10);
674 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
675 PUSH_DATA (push, 0x10);
676 PUSH_DATA (push, 0x10);
677 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
678 PUSH_DATA (push, 0x10);
679 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
680 PUSH_DATA (push, 0xe);
681
682 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
683 PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
684 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
685 PUSH_DATA (push, 0);
686 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
687 PUSH_DATA (push, 3);
688
689 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
690 PUSH_DATA (push, 0x3fffff);
691 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
692 PUSH_DATA (push, 1);
693 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
694 PUSH_DATA (push, 1);
695
696 if (obj_class < GM107_3D_CLASS) {
697 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
698 PUSH_DATA (push, 3);
699
700 if (obj_class >= NVE4_3D_CLASS) {
701 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
702 PUSH_DATA (push, 1);
703 }
704 }
705
706 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
707 * are supposed to do */
708 }
709
710 static void
711 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
712 {
713 struct nvc0_screen *screen = nvc0_screen(pscreen);
714 struct nouveau_pushbuf *push = screen->base.pushbuf;
715
716 /* we need to do it after possible flush in MARK_RING */
717 *sequence = ++screen->base.fence.sequence;
718
719 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
720 PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
721 PUSH_DATAh(push, screen->fence.bo->offset);
722 PUSH_DATA (push, screen->fence.bo->offset);
723 PUSH_DATA (push, *sequence);
724 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
725 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
726 }
727
728 static u32
729 nvc0_screen_fence_update(struct pipe_screen *pscreen)
730 {
731 struct nvc0_screen *screen = nvc0_screen(pscreen);
732 return screen->fence.map[0];
733 }
734
735 static int
736 nvc0_screen_init_compute(struct nvc0_screen *screen)
737 {
738 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
739
740 switch (screen->base.device->chipset & ~0xf) {
741 case 0xc0:
742 case 0xd0:
743 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
744 case 0xe0:
745 case 0xf0:
746 case 0x100:
747 case 0x110:
748 case 0x120:
749 case 0x130:
750 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
751 default:
752 return -1;
753 }
754 }
755
756 static int
757 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
758 uint32_t lpos, uint32_t lneg, uint32_t cstack)
759 {
760 struct nouveau_bo *bo = NULL;
761 int ret;
762 uint64_t size = (lpos + lneg) * 32 + cstack;
763
764 if (size >= (1 << 20)) {
765 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
766 return -1;
767 }
768
769 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
770 size = align(size, 0x8000);
771 size *= screen->mp_count;
772
773 size = align(size, 1 << 17);
774
775 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
776 NULL, &bo);
777 if (ret)
778 return ret;
779
780 /* Make sure that the pushbuf has acquired a reference to the old tls
781 * segment, as it may have commands that will reference it.
782 */
783 if (screen->tls)
784 PUSH_REFN(screen->base.pushbuf, screen->tls,
785 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RDWR);
786 nouveau_bo_ref(NULL, &screen->tls);
787 screen->tls = bo;
788 return 0;
789 }
790
791 int
792 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
793 {
794 struct nouveau_pushbuf *push = screen->base.pushbuf;
795 struct nouveau_bo *bo;
796 int ret;
797
798 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
799 1 << 17, size, NULL, &bo);
800 if (ret)
801 return ret;
802
803 /* Make sure that the pushbuf has acquired a reference to the old text
804 * segment, as it may have commands that will reference it.
805 */
806 if (screen->text)
807 PUSH_REFN(push, screen->text,
808 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD);
809 nouveau_bo_ref(NULL, &screen->text);
810 screen->text = bo;
811
812 nouveau_heap_destroy(&screen->lib_code);
813 nouveau_heap_destroy(&screen->text_heap);
814
815 /* XXX: getting a page fault at the end of the code buffer every few
816 * launches, don't use the last 256 bytes to work around them - prefetch ?
817 */
818 nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
819
820 /* update the code segment setup */
821 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
822 PUSH_DATAh(push, screen->text->offset);
823 PUSH_DATA (push, screen->text->offset);
824 if (screen->compute) {
825 BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
826 PUSH_DATAh(push, screen->text->offset);
827 PUSH_DATA (push, screen->text->offset);
828 }
829
830 return 0;
831 }
832
833 void
834 nvc0_screen_bind_cb_3d(struct nvc0_screen *screen, bool *can_serialize,
835 int stage, int index, int size, uint64_t addr)
836 {
837 assert(stage != 5);
838
839 struct nouveau_pushbuf *push = screen->base.pushbuf;
840
841 if (screen->base.class_3d >= GM107_3D_CLASS) {
842 struct nvc0_cb_binding *binding = &screen->cb_bindings[stage][index];
843
844 // TODO: Better figure out the conditions in which this is needed
845 bool serialize = binding->addr == addr && binding->size != size;
846 if (can_serialize)
847 serialize = serialize && *can_serialize;
848 if (serialize) {
849 IMMED_NVC0(push, NVC0_3D(SERIALIZE), 0);
850 if (can_serialize)
851 *can_serialize = false;
852 }
853
854 binding->addr = addr;
855 binding->size = size;
856 }
857
858 if (size >= 0) {
859 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
860 PUSH_DATA (push, size);
861 PUSH_DATAh(push, addr);
862 PUSH_DATA (push, addr);
863 }
864 IMMED_NVC0(push, NVC0_3D(CB_BIND(stage)), (index << 4) | (size >= 0));
865 }
866
867 #define FAIL_SCREEN_INIT(str, err) \
868 do { \
869 NOUVEAU_ERR(str, err); \
870 goto fail; \
871 } while(0)
872
873 struct nouveau_screen *
874 nvc0_screen_create(struct nouveau_device *dev)
875 {
876 struct nvc0_screen *screen;
877 struct pipe_screen *pscreen;
878 struct nouveau_object *chan;
879 struct nouveau_pushbuf *push;
880 uint64_t value;
881 uint32_t obj_class;
882 uint32_t flags;
883 int ret;
884 unsigned i;
885
886 switch (dev->chipset & ~0xf) {
887 case 0xc0:
888 case 0xd0:
889 case 0xe0:
890 case 0xf0:
891 case 0x100:
892 case 0x110:
893 case 0x120:
894 case 0x130:
895 break;
896 default:
897 return NULL;
898 }
899
900 screen = CALLOC_STRUCT(nvc0_screen);
901 if (!screen)
902 return NULL;
903 pscreen = &screen->base.base;
904 pscreen->destroy = nvc0_screen_destroy;
905
906 ret = nouveau_screen_init(&screen->base, dev);
907 if (ret)
908 FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
909 chan = screen->base.channel;
910 push = screen->base.pushbuf;
911 push->user_priv = screen;
912 push->rsvd_kick = 5;
913
914 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
915 PIPE_BIND_SHADER_BUFFER |
916 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
917 PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
918 screen->base.sysmem_bindings |=
919 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
920
921 if (screen->base.vram_domain & NOUVEAU_BO_GART) {
922 screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
923 screen->base.vidmem_bindings = 0;
924 }
925
926 pscreen->context_create = nvc0_create;
927 pscreen->is_format_supported = nvc0_screen_is_format_supported;
928 pscreen->get_param = nvc0_screen_get_param;
929 pscreen->get_shader_param = nvc0_screen_get_shader_param;
930 pscreen->get_paramf = nvc0_screen_get_paramf;
931 pscreen->get_sample_pixel_grid = nvc0_screen_get_sample_pixel_grid;
932 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
933 pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
934
935 nvc0_screen_init_resource_functions(pscreen);
936
937 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
938 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
939
940 flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
941 if (screen->base.drm->version >= 0x01000202)
942 flags |= NOUVEAU_BO_COHERENT;
943
944 ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
945 if (ret)
946 FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
947 nouveau_bo_map(screen->fence.bo, 0, NULL);
948 screen->fence.map = screen->fence.bo->map;
949 screen->base.fence.emit = nvc0_screen_fence_emit;
950 screen->base.fence.update = nvc0_screen_fence_update;
951
952
953 ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
954 NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
955 if (ret)
956 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
957
958 BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
959 PUSH_DATA (push, screen->nvsw->handle);
960
961 switch (dev->chipset & ~0xf) {
962 case 0x130:
963 case 0x120:
964 case 0x110:
965 case 0x100:
966 case 0xf0:
967 obj_class = NVF0_P2MF_CLASS;
968 break;
969 case 0xe0:
970 obj_class = NVE4_P2MF_CLASS;
971 break;
972 default:
973 obj_class = NVC0_M2MF_CLASS;
974 break;
975 }
976 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
977 &screen->m2mf);
978 if (ret)
979 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
980
981 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
982 PUSH_DATA (push, screen->m2mf->oclass);
983 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
984 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
985 PUSH_DATA (push, 0xa0b5);
986 }
987
988 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
989 &screen->eng2d);
990 if (ret)
991 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
992
993 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
994 PUSH_DATA (push, screen->eng2d->oclass);
995 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
996 PUSH_DATA (push, 0);
997 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
998 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
999 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
1000 PUSH_DATA (push, 0);
1001 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
1002 PUSH_DATA (push, 0);
1003 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
1004 PUSH_DATA (push, 0x3f);
1005 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
1006 PUSH_DATA (push, 1);
1007 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
1008 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
1009
1010 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
1011 PUSH_DATAh(push, screen->fence.bo->offset + 16);
1012 PUSH_DATA (push, screen->fence.bo->offset + 16);
1013
1014 switch (dev->chipset & ~0xf) {
1015 case 0x130:
1016 switch (dev->chipset) {
1017 case 0x130:
1018 case 0x13b:
1019 obj_class = GP100_3D_CLASS;
1020 break;
1021 default:
1022 obj_class = GP102_3D_CLASS;
1023 break;
1024 }
1025 break;
1026 case 0x120:
1027 obj_class = GM200_3D_CLASS;
1028 break;
1029 case 0x110:
1030 obj_class = GM107_3D_CLASS;
1031 break;
1032 case 0x100:
1033 case 0xf0:
1034 obj_class = NVF0_3D_CLASS;
1035 break;
1036 case 0xe0:
1037 switch (dev->chipset) {
1038 case 0xea:
1039 obj_class = NVEA_3D_CLASS;
1040 break;
1041 default:
1042 obj_class = NVE4_3D_CLASS;
1043 break;
1044 }
1045 break;
1046 case 0xd0:
1047 obj_class = NVC8_3D_CLASS;
1048 break;
1049 case 0xc0:
1050 default:
1051 switch (dev->chipset) {
1052 case 0xc8:
1053 obj_class = NVC8_3D_CLASS;
1054 break;
1055 case 0xc1:
1056 obj_class = NVC1_3D_CLASS;
1057 break;
1058 default:
1059 obj_class = NVC0_3D_CLASS;
1060 break;
1061 }
1062 break;
1063 }
1064 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
1065 &screen->eng3d);
1066 if (ret)
1067 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
1068 screen->base.class_3d = obj_class;
1069
1070 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
1071 PUSH_DATA (push, screen->eng3d->oclass);
1072
1073 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
1074 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
1075
1076 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
1077 /* kill shaders after about 1 second (at 100 MHz) */
1078 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
1079 PUSH_DATA (push, 0x17);
1080 }
1081
1082 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
1083 screen->base.drm->version >= 0x01000101);
1084 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
1085 for (i = 0; i < 8; ++i)
1086 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
1087
1088 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
1089 PUSH_DATA (push, 1);
1090
1091 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
1092 PUSH_DATA (push, 0);
1093 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
1094 PUSH_DATA (push, 0);
1095 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
1096 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
1097 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
1098 PUSH_DATA (push, 0);
1099 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
1100 PUSH_DATA (push, 1);
1101 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
1102 PUSH_DATA (push, 1);
1103 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
1104 PUSH_DATA (push, 1);
1105 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
1106 PUSH_DATA (push, 0);
1107 BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
1108 PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
1109 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
1110 IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
1111 } else {
1112 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
1113 PUSH_DATA (push, 15);
1114 }
1115 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
1116 PUSH_DATA (push, 8); /* 128 */
1117 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
1118 PUSH_DATA (push, 1);
1119 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
1120 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
1121 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
1122 }
1123
1124 nvc0_magic_3d_init(push, screen->eng3d->oclass);
1125
1126 ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1127 if (ret)
1128 FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1129
1130 /* 6 user uniform areas, 6 driver areas, and 1 for the runout */
1131 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 13 << 16, NULL,
1132 &screen->uniform_bo);
1133 if (ret)
1134 FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1135
1136 PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1137
1138 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1139 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1140 PUSH_DATA (push, 256);
1141 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1142 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1143 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1144 PUSH_DATA (push, 0);
1145 PUSH_DATAf(push, 0.0f);
1146 PUSH_DATAf(push, 0.0f);
1147 PUSH_DATAf(push, 0.0f);
1148 PUSH_DATAf(push, 0.0f);
1149 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1150 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1151 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1152
1153 if (screen->base.drm->version >= 0x01000101) {
1154 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1155 if (ret)
1156 FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1157 } else {
1158 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1159 value = (8 << 8) | 4;
1160 else
1161 value = (16 << 8) | 4;
1162 }
1163 screen->gpc_count = value & 0x000000ff;
1164 screen->mp_count = value >> 8;
1165 screen->mp_count_compute = screen->mp_count;
1166
1167 ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1168 if (ret)
1169 FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1170
1171 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1172 PUSH_DATAh(push, screen->tls->offset);
1173 PUSH_DATA (push, screen->tls->offset);
1174 PUSH_DATA (push, screen->tls->size >> 32);
1175 PUSH_DATA (push, screen->tls->size);
1176 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1177 PUSH_DATA (push, 0);
1178 /* Reduce likelihood of collision with real buffers by placing the hole at
1179 * the top of the 4G area. This will have to be dealt with for real
1180 * eventually by blocking off that area from the VM.
1181 */
1182 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1183 PUSH_DATA (push, 0xff << 24);
1184
1185 if (screen->eng3d->oclass < GM107_3D_CLASS) {
1186 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1187 &screen->poly_cache);
1188 if (ret)
1189 FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1190
1191 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1192 PUSH_DATAh(push, screen->poly_cache->offset);
1193 PUSH_DATA (push, screen->poly_cache->offset);
1194 PUSH_DATA (push, 3);
1195 }
1196
1197 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1198 &screen->txc);
1199 if (ret)
1200 FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1201
1202 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1203 PUSH_DATAh(push, screen->txc->offset);
1204 PUSH_DATA (push, screen->txc->offset);
1205 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1206 if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1207 screen->tic.maxwell = true;
1208 if (screen->eng3d->oclass == GM107_3D_CLASS) {
1209 screen->tic.maxwell =
1210 debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1211 IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1212 }
1213 }
1214
1215 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1216 PUSH_DATAh(push, screen->txc->offset + 65536);
1217 PUSH_DATA (push, screen->txc->offset + 65536);
1218 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1219
1220 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1221 PUSH_DATA (push, 0);
1222 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1223 PUSH_DATA (push, 0);
1224 PUSH_DATA (push, 0);
1225 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1226 PUSH_DATA (push, 0x3f);
1227
1228 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1229 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1230 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1231 for (i = 0; i < 8 * 2; ++i)
1232 PUSH_DATA(push, 0);
1233 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1234 PUSH_DATA (push, 0);
1235 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1236 PUSH_DATA (push, 0);
1237
1238 /* neither scissors, viewport nor stencil mask should affect clears */
1239 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1240 PUSH_DATA (push, 0);
1241
1242 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1243 PUSH_DATA (push, 1);
1244 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1245 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1246 PUSH_DATAf(push, 0.0f);
1247 PUSH_DATAf(push, 1.0f);
1248 }
1249 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1250 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1251
1252 /* We use scissors instead of exact view volume clipping,
1253 * so they're always enabled.
1254 */
1255 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1256 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1257 PUSH_DATA (push, 1);
1258 PUSH_DATA (push, 8192 << 16);
1259 PUSH_DATA (push, 8192 << 16);
1260 }
1261
1262 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1263
1264 i = 0;
1265 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1266 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1267 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1268 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1269 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1270 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1271 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1272 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1273 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1274 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1275 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1276 MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1277 MK_MACRO(NVC0_3D_MACRO_CONSERVATIVE_RASTER_STATE, mme9097_conservative_raster_state);
1278 MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1279
1280 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1281 PUSH_DATA (push, 1);
1282 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1283 PUSH_DATA (push, 1);
1284 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1285 PUSH_DATA (push, 0x40);
1286 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1287 PUSH_DATA (push, 0);
1288 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1289 PUSH_DATA (push, 0x30);
1290 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1291 PUSH_DATA (push, 3);
1292 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1293 PUSH_DATA (push, 0x20);
1294 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1295 PUSH_DATA (push, 0x00);
1296 screen->save_state.patch_vertices = 3;
1297
1298 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1299 PUSH_DATA (push, 0);
1300 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1301 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1302
1303 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1304
1305 if (nvc0_screen_init_compute(screen))
1306 goto fail;
1307
1308 /* XXX: Compute and 3D are somehow aliased on Fermi. */
1309 for (i = 0; i < 5; ++i) {
1310 unsigned j = 0;
1311 for (j = 0; j < 16; j++)
1312 screen->cb_bindings[i][j].size = -1;
1313
1314 /* TIC and TSC entries for each unit (nve4+ only) */
1315 /* auxiliary constants (6 user clip planes, base instance id) */
1316 nvc0_screen_bind_cb_3d(screen, NULL, i, 15, NVC0_CB_AUX_SIZE,
1317 screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1318 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1319 unsigned j;
1320 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1321 PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1322 for (j = 0; j < 8; ++j)
1323 PUSH_DATA(push, j);
1324 } else {
1325 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1326 PUSH_DATA (push, 0x54);
1327 }
1328
1329 /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1330 BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1331 PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1332 PUSH_DATA (push, 0); /* 0 */
1333 PUSH_DATA (push, 0);
1334 PUSH_DATA (push, 1); /* 1 */
1335 PUSH_DATA (push, 0);
1336 PUSH_DATA (push, 0); /* 2 */
1337 PUSH_DATA (push, 1);
1338 PUSH_DATA (push, 1); /* 3 */
1339 PUSH_DATA (push, 1);
1340 PUSH_DATA (push, 2); /* 4 */
1341 PUSH_DATA (push, 0);
1342 PUSH_DATA (push, 3); /* 5 */
1343 PUSH_DATA (push, 0);
1344 PUSH_DATA (push, 2); /* 6 */
1345 PUSH_DATA (push, 1);
1346 PUSH_DATA (push, 3); /* 7 */
1347 PUSH_DATA (push, 1);
1348 }
1349 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1350 PUSH_DATA (push, 0);
1351
1352 PUSH_KICK (push);
1353
1354 screen->tic.entries = CALLOC(
1355 NVC0_TIC_MAX_ENTRIES + NVC0_TSC_MAX_ENTRIES + NVE4_IMG_MAX_HANDLES,
1356 sizeof(void *));
1357 screen->tsc.entries = screen->tic.entries + NVC0_TIC_MAX_ENTRIES;
1358 screen->img.entries = (void *)(screen->tsc.entries + NVC0_TSC_MAX_ENTRIES);
1359
1360 if (!nvc0_blitter_create(screen))
1361 goto fail;
1362
1363 screen->default_tsc = CALLOC_STRUCT(nv50_tsc_entry);
1364 screen->default_tsc->tsc[0] = G80_TSC_0_SRGB_CONVERSION;
1365
1366 nouveau_fence_new(&screen->base, &screen->base.fence.current);
1367
1368 return &screen->base;
1369
1370 fail:
1371 screen->base.base.context_create = NULL;
1372 return &screen->base;
1373 }
1374
1375 int
1376 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1377 {
1378 int i = screen->tic.next;
1379
1380 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1381 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1382
1383 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1384
1385 if (screen->tic.entries[i])
1386 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1387
1388 screen->tic.entries[i] = entry;
1389 return i;
1390 }
1391
1392 int
1393 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1394 {
1395 int i = screen->tsc.next;
1396
1397 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1398 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1399
1400 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1401
1402 if (screen->tsc.entries[i])
1403 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1404
1405 screen->tsc.entries[i] = entry;
1406 return i;
1407 }