src/gallium/drivers/r600/r600_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "r600_pipe.h"
  24 #include "r600_public.h"
  25 #include "r600_isa.h"
  26 #include "evergreen_compute.h"
  27 #include "r600d.h"
  28
  29 #include "sb/sb_public.h"
  30
  31 #include <errno.h>
  32 #include "pipe/p_shader_tokens.h"
  33 #include "util/u_debug.h"
  34 #include "util/u_memory.h"
  35 #include "util/u_screen.h"
  36 #include "util/u_simple_shaders.h"
  37 #include "util/u_upload_mgr.h"
  38 #include "util/u_math.h"
  39 #include "vl/vl_decoder.h"
  40 #include "vl/vl_video_buffer.h"
  41 #include "radeon_video.h"
  42 #include "radeon_uvd.h"
  43 #include "util/os_time.h"
  44
  45 static const struct debug_named_value r600_debug_options[] = {
  46         /* features */
  47         { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
  48
  49         /* shader backend */
  50         { "nosb", DBG_NO_SB, "Disable sb backend for graphics shaders" },
  51         { "sbcl", DBG_SB_CS, "Enable sb backend for compute shaders" },
  52         { "sbdry", DBG_SB_DRY_RUN, "Don't use optimized bytecode (just print the dumps)" },
  53         { "sbstat", DBG_SB_STAT, "Print optimization statistics for shaders" },
  54         { "sbdump", DBG_SB_DUMP, "Print IR dumps after some optimization passes" },
  55         { "sbnofallback", DBG_SB_NO_FALLBACK, "Abort on errors instead of fallback" },
  56         { "sbdisasm", DBG_SB_DISASM, "Use sb disassembler for shader dumps" },
  57         { "sbsafemath", DBG_SB_SAFEMATH, "Disable unsafe math optimizations" },
  58
  59         DEBUG_NAMED_VALUE_END /* must be last */
  60 };
  61
  62 /*
  63  * pipe_context
  64  */
  65
  66 static void r600_destroy_context(struct pipe_context *context)
  67 {
  68         struct r600_context *rctx = (struct r600_context *)context;
  69         unsigned sh, i;
  70
  71         r600_isa_destroy(rctx->isa);
  72
  73         r600_sb_context_destroy(rctx->sb_context);
  74
  75         for (sh = 0; sh < (rctx->b.chip_class < EVERGREEN ? R600_NUM_HW_STAGES : EG_NUM_HW_STAGES); sh++) {
  76                 r600_resource_reference(&rctx->scratch_buffers[sh].buffer, NULL);
  77         }
  78         r600_resource_reference(&rctx->dummy_cmask, NULL);
  79         r600_resource_reference(&rctx->dummy_fmask, NULL);
  80
  81         if (rctx->append_fence)
  82                 pipe_resource_reference((struct pipe_resource**)&rctx->append_fence, NULL);
  83         for (sh = 0; sh < PIPE_SHADER_TYPES; sh++) {
  84                 rctx->b.b.set_constant_buffer(&rctx->b.b, sh, R600_BUFFER_INFO_CONST_BUFFER, NULL);
  85                 free(rctx->driver_consts[sh].constants);
  86         }
  87
  88         if (rctx->fixed_func_tcs_shader)
  89                 rctx->b.b.delete_tcs_state(&rctx->b.b, rctx->fixed_func_tcs_shader);
  90
  91         if (rctx->dummy_pixel_shader) {
  92                 rctx->b.b.delete_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
  93         }
  94         if (rctx->custom_dsa_flush) {
  95                 rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush);
  96         }
  97         if (rctx->custom_blend_resolve) {
  98                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_resolve);
  99         }
 100         if (rctx->custom_blend_decompress) {
 101                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_decompress);
 102         }
 103         if (rctx->custom_blend_fastclear) {
 104                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_fastclear);
 105         }
 106         util_unreference_framebuffer_state(&rctx->framebuffer.state);
 107
 108         for (sh = 0; sh < PIPE_SHADER_TYPES; ++sh)
 109                 for (i = 0; i < PIPE_MAX_CONSTANT_BUFFERS; ++i)
 110                         rctx->b.b.set_constant_buffer(context, sh, i, NULL);
 111
 112         if (rctx->blitter) {
 113                 util_blitter_destroy(rctx->blitter);
 114         }
 115         if (rctx->allocator_fetch_shader) {
 116                 u_suballocator_destroy(rctx->allocator_fetch_shader);
 117         }
 118
 119         r600_release_command_buffer(&rctx->start_cs_cmd);
 120
 121         FREE(rctx->start_compute_cs_cmd.buf);
 122
 123         r600_common_context_cleanup(&rctx->b);
 124
 125         r600_resource_reference(&rctx->trace_buf, NULL);
 126         r600_resource_reference(&rctx->last_trace_buf, NULL);
 127         radeon_clear_saved_cs(&rctx->last_gfx);
 128
 129         FREE(rctx);
 130 }
 131
 132 static struct pipe_context *r600_create_context(struct pipe_screen *screen,
 133                                                 void *priv, unsigned flags)
 134 {
 135         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 136         struct r600_screen* rscreen = (struct r600_screen *)screen;
 137         struct radeon_winsys *ws = rscreen->b.ws;
 138
 139         if (!rctx)
 140                 return NULL;
 141
 142         rctx->b.b.screen = screen;
 143         assert(!priv);
 144         rctx->b.b.priv = NULL; /* for threaded_context_unwrap_sync */
 145         rctx->b.b.destroy = r600_destroy_context;
 146         rctx->b.set_atom_dirty = (void *)r600_set_atom_dirty;
 147
 148         if (!r600_common_context_init(&rctx->b, &rscreen->b, flags))
 149                 goto fail;
 150
 151         rctx->screen = rscreen;
 152         LIST_INITHEAD(&rctx->texture_buffers);
 153
 154         r600_init_blit_functions(rctx);
 155
 156         if (rscreen->b.info.has_hw_decode) {
 157                 rctx->b.b.create_video_codec = r600_uvd_create_decoder;
 158                 rctx->b.b.create_video_buffer = r600_video_buffer_create;
 159         } else {
 160                 rctx->b.b.create_video_codec = vl_create_decoder;
 161                 rctx->b.b.create_video_buffer = vl_video_buffer_create;
 162         }
 163
 164         if (getenv("R600_TRACE"))
 165                 rctx->is_debug = true;
 166         r600_init_common_state_functions(rctx);
 167
 168         switch (rctx->b.chip_class) {
 169         case R600:
 170         case R700:
 171                 r600_init_state_functions(rctx);
 172                 r600_init_atom_start_cs(rctx);
 173                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 174                 rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx)
 175                                                                       : r600_create_resolve_blend(rctx);
 176                 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
 177                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 ||
 178                                            rctx->b.family == CHIP_RV620 ||
 179                                            rctx->b.family == CHIP_RS780 ||
 180                                            rctx->b.family == CHIP_RS880 ||
 181                                            rctx->b.family == CHIP_RV710);
 182                 break;
 183         case EVERGREEN:
 184         case CAYMAN:
 185                 evergreen_init_state_functions(rctx);
 186                 evergreen_init_atom_start_cs(rctx);
 187                 evergreen_init_atom_start_compute_cs(rctx);
 188                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 189                 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
 190                 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
 191                 rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx);
 192                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR ||
 193                                            rctx->b.family == CHIP_PALM ||
 194                                            rctx->b.family == CHIP_SUMO ||
 195                                            rctx->b.family == CHIP_SUMO2 ||
 196                                            rctx->b.family == CHIP_CAICOS ||
 197                                            rctx->b.family == CHIP_CAYMAN ||
 198                                            rctx->b.family == CHIP_ARUBA);
 199
 200                 rctx->append_fence = pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
 201                                                          PIPE_USAGE_DEFAULT, 32);
 202                 break;
 203         default:
 204                 R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
 205                 goto fail;
 206         }
 207
 208         rctx->b.gfx.cs = ws->cs_create(rctx->b.ctx, RING_GFX,
 209                                        r600_context_gfx_flush, rctx);
 210         rctx->b.gfx.flush = r600_context_gfx_flush;
 211
 212         rctx->allocator_fetch_shader =
 213                 u_suballocator_create(&rctx->b.b, 64 * 1024,
 214                                       0, PIPE_USAGE_DEFAULT, 0, FALSE);
 215         if (!rctx->allocator_fetch_shader)
 216                 goto fail;
 217
 218         rctx->isa = calloc(1, sizeof(struct r600_isa));
 219         if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
 220                 goto fail;
 221
 222         if (rscreen->b.debug_flags & DBG_FORCE_DMA)
 223                 rctx->b.b.resource_copy_region = rctx->b.dma_copy;
 224
 225         rctx->blitter = util_blitter_create(&rctx->b.b);
 226         if (rctx->blitter == NULL)
 227                 goto fail;
 228         util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
 229         rctx->blitter->draw_rectangle = r600_draw_rectangle;
 230
 231         r600_begin_new_cs(rctx);
 232
 233         rctx->dummy_pixel_shader =
 234                 util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
 235                                                      TGSI_SEMANTIC_GENERIC,
 236                                                      TGSI_INTERPOLATE_CONSTANT);
 237         rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
 238
 239         return &rctx->b.b;
 240
 241 fail:
 242         r600_destroy_context(&rctx->b.b);
 243         return NULL;
 244 }
 245
 246 /*
 247  * pipe_screen
 248  */
 249
 250 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 251 {
 252         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 253         enum radeon_family family = rscreen->b.family;
 254
 255         switch (param) {
 256         /* Supported features (boolean caps). */
 257         case PIPE_CAP_NPOT_TEXTURES:
 258         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 259         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 260         case PIPE_CAP_ANISOTROPIC_FILTER:
 261         case PIPE_CAP_POINT_SPRITE:
 262         case PIPE_CAP_OCCLUSION_QUERY:
 263         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 264         case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 265         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 266         case PIPE_CAP_TEXTURE_SWIZZLE:
 267         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 268         case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 269         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 270         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 271         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 272         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 273         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 274         case PIPE_CAP_SM3:
 275         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 276         case PIPE_CAP_PRIMITIVE_RESTART:
 277         case PIPE_CAP_CONDITIONAL_RENDER:
 278         case PIPE_CAP_TEXTURE_BARRIER:
 279         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 280         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 281         case PIPE_CAP_TGSI_INSTANCEID:
 282         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 283         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 284         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 285         case PIPE_CAP_START_INSTANCE:
 286         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 287         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 288         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 289         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 290         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 291         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 292         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 293         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 294         case PIPE_CAP_SAMPLE_SHADING:
 295         case PIPE_CAP_CLIP_HALFZ:
 296         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 297         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 298         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 299         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 300         case PIPE_CAP_TGSI_TXQS:
 301         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 302         case PIPE_CAP_INVALIDATE_BUFFER:
 303         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 304         case PIPE_CAP_QUERY_MEMORY_INFO:
 305         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 306         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 307         case PIPE_CAP_CLEAR_TEXTURE:
 308         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 309         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 310         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 311         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 312                 return 1;
 313
 314         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 315                 return rscreen->b.info.drm_major == 2 && rscreen->b.info.drm_minor >= 43;
 316
 317         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 318                 return !R600_BIG_ENDIAN && rscreen->b.info.has_userptr;
 319
 320         case PIPE_CAP_COMPUTE:
 321                 return rscreen->b.chip_class > R700;
 322
 323         case PIPE_CAP_TGSI_TEXCOORD:
 324                 return 0;
 325
 326         case PIPE_CAP_FAKE_SW_MSAA:
 327                 return 0;
 328
 329         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 330                 return MIN2(rscreen->b.info.max_alloc_size, INT_MAX);
 331
 332         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 333                 return R600_MAP_BUFFER_ALIGNMENT;
 334
 335         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 336                 return 256;
 337
 338         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 339                 return 1;
 340
 341         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 342                 if (family >= CHIP_CEDAR)
 343                    return 430;
 344                 /* pre-evergreen geom shaders need newer kernel */
 345                 if (rscreen->b.info.drm_minor >= 37)
 346                    return 330;
 347                 return 140;
 348
 349         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 350                 return 140;
 351
 352         /* Supported except the original R600. */
 353         case PIPE_CAP_INDEP_BLEND_ENABLE:
 354         case PIPE_CAP_INDEP_BLEND_FUNC:
 355                 /* R600 doesn't support per-MRT blends */
 356                 return family == CHIP_R600 ? 0 : 1;
 357
 358         /* Supported on Evergreen. */
 359         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 360         case PIPE_CAP_CUBE_MAP_ARRAY:
 361         case PIPE_CAP_TEXTURE_GATHER_SM5:
 362         case PIPE_CAP_TEXTURE_QUERY_LOD:
 363         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 364         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 365         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 366         case PIPE_CAP_TGSI_CLOCK:
 367         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 368         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 369                 return family >= CHIP_CEDAR ? 1 : 0;
 370         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 371                 return family >= CHIP_CEDAR ? 4 : 0;
 372         case PIPE_CAP_DRAW_INDIRECT:
 373                 /* kernel command checker support is also required */
 374                 return family >= CHIP_CEDAR && rscreen->b.info.drm_minor >= 41;
 375
 376         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 377                 return family >= CHIP_CEDAR ? 0 : 1;
 378
 379         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 380                 return 8;
 381
 382         case PIPE_CAP_MAX_GS_INVOCATIONS:
 383                 return 32;
 384
 385         /* shader buffer objects */
 386         case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 387                 return 1 << 27;
 388         case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
 389                 return 8;
 390
 391         /* Unsupported features. */
 392         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 393         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 394         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 395         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 396         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 397         case PIPE_CAP_USER_VERTEX_BUFFERS:
 398         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 399         case PIPE_CAP_VERTEXID_NOBASE:
 400         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 401         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 402         case PIPE_CAP_SHAREABLE_SHADERS:
 403         case PIPE_CAP_DRAW_PARAMETERS:
 404         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 405         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 406         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 407         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 408         case PIPE_CAP_GENERATE_MIPMAP:
 409         case PIPE_CAP_STRING_MARKER:
 410         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 411         case PIPE_CAP_TGSI_VOTE:
 412         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 413         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 414         case PIPE_CAP_NATIVE_FENCE_FD:
 415         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 416         case PIPE_CAP_TGSI_FS_FBFETCH:
 417         case PIPE_CAP_INT64:
 418         case PIPE_CAP_INT64_DIVMOD:
 419         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 420         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 421         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 422         case PIPE_CAP_TGSI_BALLOT:
 423         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 424         case PIPE_CAP_POST_DEPTH_COVERAGE:
 425         case PIPE_CAP_BINDLESS_TEXTURE:
 426         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 427         case PIPE_CAP_QUERY_SO_OVERFLOW:
 428         case PIPE_CAP_MEMOBJ:
 429         case PIPE_CAP_LOAD_CONSTBUF:
 430         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 431         case PIPE_CAP_TILE_RASTER_ORDER:
 432         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 433         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 434         case PIPE_CAP_FENCE_SIGNAL:
 435         case PIPE_CAP_CONSTBUF0_FLAGS:
 436         case PIPE_CAP_PACKED_UNIFORMS:
 437         case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 438         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 439         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 440         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 441         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 442         case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 443         case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 444         case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 445                 return 0;
 446
 447         case PIPE_CAP_DOUBLES:
 448                 if (rscreen->b.family == CHIP_ARUBA ||
 449                     rscreen->b.family == CHIP_CAYMAN ||
 450                     rscreen->b.family == CHIP_CYPRESS ||
 451                     rscreen->b.family == CHIP_HEMLOCK)
 452                         return 1;
 453                 return 0;
 454         case PIPE_CAP_CULL_DISTANCE:
 455                 return 1;
 456
 457         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 458                 if (family >= CHIP_CEDAR)
 459                         return 256;
 460                 return 0;
 461
 462         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 463                 if (family >= CHIP_CEDAR)
 464                         return 30;
 465                 else
 466                         return 0;
 467         /* Stream output. */
 468         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 469                 return rscreen->b.has_streamout ? 4 : 0;
 470         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 471         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 472                 return rscreen->b.has_streamout ? 1 : 0;
 473         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 474         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 475                 return 32*4;
 476
 477         /* Geometry shader output. */
 478         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 479                 return 1024;
 480         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 481                 return 16384;
 482         case PIPE_CAP_MAX_VERTEX_STREAMS:
 483                 return family >= CHIP_CEDAR ? 4 : 1;
 484
 485         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 486                 /* Should be 2047, but 2048 is a requirement for GL 4.4 */
 487                 return 2048;
 488
 489         /* Texturing. */
 490         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 491         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 492                 if (family >= CHIP_CEDAR)
 493                         return 15;
 494                 else
 495                         return 14;
 496         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 497                 /* textures support 8192, but layered rendering supports 2048 */
 498                 return 12;
 499         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 500                 /* textures support 8192, but layered rendering supports 2048 */
 501                 return 2048;
 502
 503         /* Render targets. */
 504         case PIPE_CAP_MAX_RENDER_TARGETS:
 505                 /* XXX some r6xx are buggy and can only do 4 */
 506                 return 8;
 507
 508         case PIPE_CAP_MAX_VIEWPORTS:
 509                 return R600_MAX_VIEWPORTS;
 510         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 511         case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
 512                 return 8;
 513
 514         /* Timer queries, present when the clock frequency is non zero. */
 515         case PIPE_CAP_QUERY_TIME_ELAPSED:
 516                 return rscreen->b.info.clock_crystal_freq != 0;
 517         case PIPE_CAP_QUERY_TIMESTAMP:
 518                 return rscreen->b.info.drm_minor >= 20 &&
 519                        rscreen->b.info.clock_crystal_freq != 0;
 520
 521         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 522         case PIPE_CAP_MIN_TEXEL_OFFSET:
 523                 return -8;
 524
 525         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 526         case PIPE_CAP_MAX_TEXEL_OFFSET:
 527                 return 7;
 528
 529         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 530                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 531         case PIPE_CAP_ENDIANNESS:
 532                 return PIPE_ENDIAN_LITTLE;
 533
 534         case PIPE_CAP_VENDOR_ID:
 535                 return ATI_VENDOR_ID;
 536         case PIPE_CAP_DEVICE_ID:
 537                 return rscreen->b.info.pci_id;
 538         case PIPE_CAP_ACCELERATED:
 539                 return 1;
 540         case PIPE_CAP_VIDEO_MEMORY:
 541                 return rscreen->b.info.vram_size >> 20;
 542         case PIPE_CAP_UMA:
 543                 return 0;
 544         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 545                 return rscreen->b.chip_class >= R700;
 546         case PIPE_CAP_PCI_GROUP:
 547                 return rscreen->b.info.pci_domain;
 548         case PIPE_CAP_PCI_BUS:
 549                 return rscreen->b.info.pci_bus;
 550         case PIPE_CAP_PCI_DEVICE:
 551                 return rscreen->b.info.pci_dev;
 552         case PIPE_CAP_PCI_FUNCTION:
 553                 return rscreen->b.info.pci_func;
 554
 555         case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
 556                 if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics)
 557                         return 8;
 558                 return 0;
 559         case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
 560                 if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics)
 561                         return EG_MAX_ATOMIC_BUFFERS;
 562                 return 0;
 563
 564         default:
 565                 return u_pipe_screen_get_param_defaults(pscreen, param);
 566         }
 567 }
 568
 569 static int r600_get_shader_param(struct pipe_screen* pscreen,
 570                                  enum pipe_shader_type shader,
 571                                  enum pipe_shader_cap param)
 572 {
 573         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 574
 575         switch(shader)
 576         {
 577         case PIPE_SHADER_FRAGMENT:
 578         case PIPE_SHADER_VERTEX:
 579         case PIPE_SHADER_COMPUTE:
 580                 break;
 581         case PIPE_SHADER_GEOMETRY:
 582                 if (rscreen->b.family >= CHIP_CEDAR)
 583                         break;
 584                 /* pre-evergreen geom shaders need newer kernel */
 585                 if (rscreen->b.info.drm_minor >= 37)
 586                         break;
 587                 return 0;
 588         case PIPE_SHADER_TESS_CTRL:
 589         case PIPE_SHADER_TESS_EVAL:
 590                 if (rscreen->b.family >= CHIP_CEDAR)
 591                         break;
 592         default:
 593                 return 0;
 594         }
 595
 596         switch (param) {
 597         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 598         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 599         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 600         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 601                 return 16384;
 602         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 603                 return 32;
 604         case PIPE_SHADER_CAP_MAX_INPUTS:
 605                 return shader == PIPE_SHADER_VERTEX ? 16 : 32;
 606         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 607                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 608         case PIPE_SHADER_CAP_MAX_TEMPS:
 609                 return 256; /* Max native temporaries. */
 610         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 611                 if (shader == PIPE_SHADER_COMPUTE) {
 612                         uint64_t max_const_buffer_size;
 613                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 614                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 615                                 &max_const_buffer_size);
 616                         return MIN2(max_const_buffer_size, INT_MAX);
 617
 618                 } else {
 619                         return R600_MAX_CONST_BUFFER_SIZE;
 620                 }
 621         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 622                 return R600_MAX_USER_CONST_BUFFERS;
 623         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 624                 return 1;
 625         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 626                 return 1;
 627         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 628         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 629         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 630         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 631                 return 1;
 632         case PIPE_SHADER_CAP_SUBROUTINES:
 633         case PIPE_SHADER_CAP_INT64_ATOMICS:
 634         case PIPE_SHADER_CAP_FP16:
 635                 return 0;
 636         case PIPE_SHADER_CAP_INTEGERS:
 637         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 638                 return 1;
 639         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 640         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 641                 return 16;
 642         case PIPE_SHADER_CAP_PREFERRED_IR:
 643                 return PIPE_SHADER_IR_TGSI;
 644         case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 645                 int ir = 0;
 646                 if (shader == PIPE_SHADER_COMPUTE)
 647                         ir = 1 << PIPE_SHADER_IR_NATIVE;
 648                 if (rscreen->b.family >= CHIP_CEDAR)
 649                         ir |= 1 << PIPE_SHADER_IR_TGSI;
 650                 return ir;
 651         }
 652         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 653                 if (rscreen->b.family == CHIP_ARUBA ||
 654                     rscreen->b.family == CHIP_CAYMAN ||
 655                     rscreen->b.family == CHIP_CYPRESS ||
 656                     rscreen->b.family == CHIP_HEMLOCK)
 657                         return 1;
 658                 return 0;
 659         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 660         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 661         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 662         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 663         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 664                 return 0;
 665         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 666         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 667                 if (rscreen->b.family >= CHIP_CEDAR &&
 668                     (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE))
 669                     return 8;
 670                 return 0;
 671         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 672                 if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics)
 673                         return 8;
 674                 return 0;
 675         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 676                 /* having to allocate the atomics out amongst shaders stages is messy,
 677                    so give compute 8 buffers and all the others one */
 678                 if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics) {
 679                         return EG_MAX_ATOMIC_BUFFERS;
 680                 }
 681                 return 0;
 682         case PIPE_SHADER_CAP_SCALAR_ISA:
 683                 return 0;
 684         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 685                 /* due to a bug in the shader compiler, some loops hang
 686                  * if they are not unrolled, see:
 687                  *    https://bugs.freedesktop.org/show_bug.cgi?id=86720
 688                  */
 689                 return 255;
 690         }
 691         return 0;
 692 }
 693
 694 static void r600_destroy_screen(struct pipe_screen* pscreen)
 695 {
 696         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 697
 698         if (!rscreen)
 699                 return;
 700
 701         if (!rscreen->b.ws->unref(rscreen->b.ws))
 702                 return;
 703
 704         if (rscreen->global_pool) {
 705                 compute_memory_pool_delete(rscreen->global_pool);
 706         }
 707
 708         r600_destroy_common_screen(&rscreen->b);
 709 }
 710
 711 static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
 712                                                   const struct pipe_resource *templ)
 713 {
 714         if (templ->target == PIPE_BUFFER &&
 715             (templ->bind & PIPE_BIND_GLOBAL))
 716                 return r600_compute_global_buffer_create(screen, templ);
 717
 718         return r600_resource_create_common(screen, templ);
 719 }
 720
 721 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws,
 722                                        const struct pipe_screen_config *config)
 723 {
 724         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 725
 726         if (!rscreen) {
 727                 return NULL;
 728         }
 729
 730         /* Set functions first. */
 731         rscreen->b.b.context_create = r600_create_context;
 732         rscreen->b.b.destroy = r600_destroy_screen;
 733         rscreen->b.b.get_param = r600_get_param;
 734         rscreen->b.b.get_shader_param = r600_get_shader_param;
 735         rscreen->b.b.resource_create = r600_resource_create;
 736
 737         if (!r600_common_screen_init(&rscreen->b, ws)) {
 738                 FREE(rscreen);
 739                 return NULL;
 740         }
 741
 742         if (rscreen->b.info.chip_class >= EVERGREEN) {
 743                 rscreen->b.b.is_format_supported = evergreen_is_format_supported;
 744         } else {
 745                 rscreen->b.b.is_format_supported = r600_is_format_supported;
 746         }
 747
 748         rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0);
 749         if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
 750                 rscreen->b.debug_flags |= DBG_COMPUTE;
 751         if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
 752                 rscreen->b.debug_flags |= DBG_ALL_SHADERS | DBG_FS;
 753         if (!debug_get_bool_option("R600_HYPERZ", TRUE))
 754                 rscreen->b.debug_flags |= DBG_NO_HYPERZ;
 755
 756         if (rscreen->b.family == CHIP_UNKNOWN) {
 757                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->b.info.pci_id);
 758                 FREE(rscreen);
 759                 return NULL;
 760         }
 761
 762         /* Figure out streamout kernel support. */
 763         switch (rscreen->b.chip_class) {
 764         case R600:
 765                 if (rscreen->b.family < CHIP_RS780) {
 766                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 767                 } else {
 768                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 23;
 769                 }
 770                 break;
 771         case R700:
 772                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 17;
 773                 break;
 774         case EVERGREEN:
 775         case CAYMAN:
 776                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 777                 break;
 778         default:
 779                 rscreen->b.has_streamout = FALSE;
 780                 break;
 781         }
 782
 783         /* MSAA support. */
 784         switch (rscreen->b.chip_class) {
 785         case R600:
 786         case R700:
 787                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 22;
 788                 rscreen->has_compressed_msaa_texturing = false;
 789                 break;
 790         case EVERGREEN:
 791                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 792                 rscreen->has_compressed_msaa_texturing = rscreen->b.info.drm_minor >= 24;
 793                 break;
 794         case CAYMAN:
 795                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 796                 rscreen->has_compressed_msaa_texturing = true;
 797                 break;
 798         default:
 799                 rscreen->has_msaa = FALSE;
 800                 rscreen->has_compressed_msaa_texturing = false;
 801         }
 802
 803         rscreen->b.has_cp_dma = rscreen->b.info.drm_minor >= 27 &&
 804                               !(rscreen->b.debug_flags & DBG_NO_CP_DMA);
 805
 806         rscreen->b.barrier_flags.cp_to_L2 =
 807                 R600_CONTEXT_INV_VERTEX_CACHE |
 808                 R600_CONTEXT_INV_TEX_CACHE |
 809                 R600_CONTEXT_INV_CONST_CACHE;
 810         rscreen->b.barrier_flags.compute_to_L2 = R600_CONTEXT_CS_PARTIAL_FLUSH | R600_CONTEXT_FLUSH_AND_INV;
 811
 812         rscreen->global_pool = compute_memory_pool_new(rscreen);
 813
 814         /* Create the auxiliary context. This must be done last. */
 815         rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL, 0);
 816
 817         rscreen->has_atomics = rscreen->b.info.drm_minor >= 44;
 818 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
 819         struct pipe_resource templ = {};
 820
 821         templ.width0 = 4;
 822         templ.height0 = 2048;
 823         templ.depth0 = 1;
 824         templ.array_size = 1;
 825         templ.target = PIPE_TEXTURE_2D;
 826         templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
 827         templ.usage = PIPE_USAGE_DEFAULT;
 828
 829         struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ));
 830         unsigned char *map = ws->buffer_map(res->buf, NULL, PIPE_TRANSFER_WRITE);
 831
 832         memset(map, 0, 256);
 833
 834         r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC);
 835         r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD);
 836         r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE);
 837         r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF);
 838         r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87);
 839
 840         ws->buffer_wait(res->buf, RADEON_USAGE_WRITE);
 841
 842         int i;
 843         for (i = 0; i < 256; i++) {
 844                 printf("%02X", map[i]);
 845                 if (i % 16 == 15)
 846                         printf("\n");
 847         }
 848 #endif
 849
 850         if (rscreen->b.debug_flags & DBG_TEST_DMA)
 851                 r600_test_dma(&rscreen->b);
 852
 853         r600_query_fix_enabled_rb_mask(&rscreen->b);
 854         return &rscreen->b.b;
 855 }