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gallium/radeon: mark shader rings as highest-priority buffers
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "r600d.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32
33 static uint32_t r600_translate_blend_function(int blend_func)
34 {
35 switch (blend_func) {
36 case PIPE_BLEND_ADD:
37 return V_028804_COMB_DST_PLUS_SRC;
38 case PIPE_BLEND_SUBTRACT:
39 return V_028804_COMB_SRC_MINUS_DST;
40 case PIPE_BLEND_REVERSE_SUBTRACT:
41 return V_028804_COMB_DST_MINUS_SRC;
42 case PIPE_BLEND_MIN:
43 return V_028804_COMB_MIN_DST_SRC;
44 case PIPE_BLEND_MAX:
45 return V_028804_COMB_MAX_DST_SRC;
46 default:
47 R600_ERR("Unknown blend function %d\n", blend_func);
48 assert(0);
49 break;
50 }
51 return 0;
52 }
53
54 static uint32_t r600_translate_blend_factor(int blend_fact)
55 {
56 switch (blend_fact) {
57 case PIPE_BLENDFACTOR_ONE:
58 return V_028804_BLEND_ONE;
59 case PIPE_BLENDFACTOR_SRC_COLOR:
60 return V_028804_BLEND_SRC_COLOR;
61 case PIPE_BLENDFACTOR_SRC_ALPHA:
62 return V_028804_BLEND_SRC_ALPHA;
63 case PIPE_BLENDFACTOR_DST_ALPHA:
64 return V_028804_BLEND_DST_ALPHA;
65 case PIPE_BLENDFACTOR_DST_COLOR:
66 return V_028804_BLEND_DST_COLOR;
67 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
68 return V_028804_BLEND_SRC_ALPHA_SATURATE;
69 case PIPE_BLENDFACTOR_CONST_COLOR:
70 return V_028804_BLEND_CONST_COLOR;
71 case PIPE_BLENDFACTOR_CONST_ALPHA:
72 return V_028804_BLEND_CONST_ALPHA;
73 case PIPE_BLENDFACTOR_ZERO:
74 return V_028804_BLEND_ZERO;
75 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
76 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
77 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
78 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
79 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
80 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
81 case PIPE_BLENDFACTOR_INV_DST_COLOR:
82 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
83 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
84 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
85 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
86 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
87 case PIPE_BLENDFACTOR_SRC1_COLOR:
88 return V_028804_BLEND_SRC1_COLOR;
89 case PIPE_BLENDFACTOR_SRC1_ALPHA:
90 return V_028804_BLEND_SRC1_ALPHA;
91 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
92 return V_028804_BLEND_INV_SRC1_COLOR;
93 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
94 return V_028804_BLEND_INV_SRC1_ALPHA;
95 default:
96 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
97 assert(0);
98 break;
99 }
100 return 0;
101 }
102
103 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
104 {
105 switch (dim) {
106 default:
107 case PIPE_TEXTURE_1D:
108 return V_038000_SQ_TEX_DIM_1D;
109 case PIPE_TEXTURE_1D_ARRAY:
110 return V_038000_SQ_TEX_DIM_1D_ARRAY;
111 case PIPE_TEXTURE_2D:
112 case PIPE_TEXTURE_RECT:
113 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
114 V_038000_SQ_TEX_DIM_2D;
115 case PIPE_TEXTURE_2D_ARRAY:
116 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
117 V_038000_SQ_TEX_DIM_2D_ARRAY;
118 case PIPE_TEXTURE_3D:
119 return V_038000_SQ_TEX_DIM_3D;
120 case PIPE_TEXTURE_CUBE:
121 case PIPE_TEXTURE_CUBE_ARRAY:
122 return V_038000_SQ_TEX_DIM_CUBEMAP;
123 }
124 }
125
126 static uint32_t r600_translate_dbformat(enum pipe_format format)
127 {
128 switch (format) {
129 case PIPE_FORMAT_Z16_UNORM:
130 return V_028010_DEPTH_16;
131 case PIPE_FORMAT_Z24X8_UNORM:
132 return V_028010_DEPTH_X8_24;
133 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
134 return V_028010_DEPTH_8_24;
135 case PIPE_FORMAT_Z32_FLOAT:
136 return V_028010_DEPTH_32_FLOAT;
137 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
138 return V_028010_DEPTH_X24_8_32_FLOAT;
139 default:
140 return ~0U;
141 }
142 }
143
144 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
145 {
146 return r600_translate_texformat(screen, format, NULL, NULL, NULL,
147 FALSE) != ~0U;
148 }
149
150 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
151 {
152 return r600_translate_colorformat(chip, format, FALSE) != ~0U &&
153 r600_translate_colorswap(format, FALSE) != ~0U;
154 }
155
156 static bool r600_is_zs_format_supported(enum pipe_format format)
157 {
158 return r600_translate_dbformat(format) != ~0U;
159 }
160
161 boolean r600_is_format_supported(struct pipe_screen *screen,
162 enum pipe_format format,
163 enum pipe_texture_target target,
164 unsigned sample_count,
165 unsigned usage)
166 {
167 struct r600_screen *rscreen = (struct r600_screen*)screen;
168 unsigned retval = 0;
169
170 if (target >= PIPE_MAX_TEXTURE_TYPES) {
171 R600_ERR("r600: unsupported texture type %d\n", target);
172 return FALSE;
173 }
174
175 if (!util_format_is_supported(format, usage))
176 return FALSE;
177
178 if (sample_count > 1) {
179 if (!rscreen->has_msaa)
180 return FALSE;
181
182 /* R11G11B10 is broken on R6xx. */
183 if (rscreen->b.chip_class == R600 &&
184 format == PIPE_FORMAT_R11G11B10_FLOAT)
185 return FALSE;
186
187 /* MSAA integer colorbuffers hang. */
188 if (util_format_is_pure_integer(format) &&
189 !util_format_is_depth_or_stencil(format))
190 return FALSE;
191
192 switch (sample_count) {
193 case 2:
194 case 4:
195 case 8:
196 break;
197 default:
198 return FALSE;
199 }
200 }
201
202 if (usage & PIPE_BIND_SAMPLER_VIEW) {
203 if (target == PIPE_BUFFER) {
204 if (r600_is_vertex_format_supported(format))
205 retval |= PIPE_BIND_SAMPLER_VIEW;
206 } else {
207 if (r600_is_sampler_format_supported(screen, format))
208 retval |= PIPE_BIND_SAMPLER_VIEW;
209 }
210 }
211
212 if ((usage & (PIPE_BIND_RENDER_TARGET |
213 PIPE_BIND_DISPLAY_TARGET |
214 PIPE_BIND_SCANOUT |
215 PIPE_BIND_SHARED |
216 PIPE_BIND_BLENDABLE)) &&
217 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
218 retval |= usage &
219 (PIPE_BIND_RENDER_TARGET |
220 PIPE_BIND_DISPLAY_TARGET |
221 PIPE_BIND_SCANOUT |
222 PIPE_BIND_SHARED);
223 if (!util_format_is_pure_integer(format) &&
224 !util_format_is_depth_or_stencil(format))
225 retval |= usage & PIPE_BIND_BLENDABLE;
226 }
227
228 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
229 r600_is_zs_format_supported(format)) {
230 retval |= PIPE_BIND_DEPTH_STENCIL;
231 }
232
233 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
234 r600_is_vertex_format_supported(format)) {
235 retval |= PIPE_BIND_VERTEX_BUFFER;
236 }
237
238 if (usage & PIPE_BIND_TRANSFER_READ)
239 retval |= PIPE_BIND_TRANSFER_READ;
240 if (usage & PIPE_BIND_TRANSFER_WRITE)
241 retval |= PIPE_BIND_TRANSFER_WRITE;
242
243 if ((usage & PIPE_BIND_LINEAR) &&
244 !util_format_is_compressed(format) &&
245 !(usage & PIPE_BIND_DEPTH_STENCIL))
246 retval |= PIPE_BIND_LINEAR;
247
248 return retval == usage;
249 }
250
251 static void r600_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
252 {
253 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
254 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
255 float offset_units = state->offset_units;
256 float offset_scale = state->offset_scale;
257 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
258
259 if (!state->offset_units_unscaled) {
260 switch (state->zs_format) {
261 case PIPE_FORMAT_Z24X8_UNORM:
262 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
263 offset_units *= 2.0f;
264 pa_su_poly_offset_db_fmt_cntl =
265 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
266 break;
267 case PIPE_FORMAT_Z16_UNORM:
268 offset_units *= 4.0f;
269 pa_su_poly_offset_db_fmt_cntl =
270 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
271 break;
272 default:
273 pa_su_poly_offset_db_fmt_cntl =
274 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
275 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
276 }
277 }
278
279 radeon_set_context_reg_seq(cs, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
280 radeon_emit(cs, fui(offset_scale));
281 radeon_emit(cs, fui(offset_units));
282 radeon_emit(cs, fui(offset_scale));
283 radeon_emit(cs, fui(offset_units));
284
285 radeon_set_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
286 pa_su_poly_offset_db_fmt_cntl);
287 }
288
289 static uint32_t r600_get_blend_control(const struct pipe_blend_state *state, unsigned i)
290 {
291 int j = state->independent_blend_enable ? i : 0;
292
293 unsigned eqRGB = state->rt[j].rgb_func;
294 unsigned srcRGB = state->rt[j].rgb_src_factor;
295 unsigned dstRGB = state->rt[j].rgb_dst_factor;
296
297 unsigned eqA = state->rt[j].alpha_func;
298 unsigned srcA = state->rt[j].alpha_src_factor;
299 unsigned dstA = state->rt[j].alpha_dst_factor;
300 uint32_t bc = 0;
301
302 if (!state->rt[j].blend_enable)
303 return 0;
304
305 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
306 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
307 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
308
309 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
310 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
311 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
312 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
313 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
314 }
315 return bc;
316 }
317
318 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
319 const struct pipe_blend_state *state,
320 int mode)
321 {
322 struct r600_context *rctx = (struct r600_context *)ctx;
323 uint32_t color_control = 0, target_mask = 0;
324 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
325
326 if (!blend) {
327 return NULL;
328 }
329
330 r600_init_command_buffer(&blend->buffer, 20);
331 r600_init_command_buffer(&blend->buffer_no_blend, 20);
332
333 /* R600 does not support per-MRT blends */
334 if (rctx->b.family > CHIP_R600)
335 color_control |= S_028808_PER_MRT_BLEND(1);
336
337 if (state->logicop_enable) {
338 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
339 } else {
340 color_control |= (0xcc << 16);
341 }
342 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
343 if (state->independent_blend_enable) {
344 for (int i = 0; i < 8; i++) {
345 if (state->rt[i].blend_enable) {
346 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
347 }
348 target_mask |= (state->rt[i].colormask << (4 * i));
349 }
350 } else {
351 for (int i = 0; i < 8; i++) {
352 if (state->rt[0].blend_enable) {
353 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
354 }
355 target_mask |= (state->rt[0].colormask << (4 * i));
356 }
357 }
358
359 if (target_mask)
360 color_control |= S_028808_SPECIAL_OP(mode);
361 else
362 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
363
364 /* only MRT0 has dual src blend */
365 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
366 blend->cb_target_mask = target_mask;
367 blend->cb_color_control = color_control;
368 blend->cb_color_control_no_blend = color_control & C_028808_TARGET_BLEND_ENABLE;
369 blend->alpha_to_one = state->alpha_to_one;
370
371 r600_store_context_reg(&blend->buffer, R_028D44_DB_ALPHA_TO_MASK,
372 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
373 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
374 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
375 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
376 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
377
378 /* Copy over the registers set so far into buffer_no_blend. */
379 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
380 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
381
382 /* Only add blend registers if blending is enabled. */
383 if (!G_028808_TARGET_BLEND_ENABLE(color_control)) {
384 return blend;
385 }
386
387 /* The first R600 does not support per-MRT blends */
388 r600_store_context_reg(&blend->buffer, R_028804_CB_BLEND_CONTROL,
389 r600_get_blend_control(state, 0));
390
391 if (rctx->b.family > CHIP_R600) {
392 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
393 for (int i = 0; i < 8; i++) {
394 r600_store_value(&blend->buffer, r600_get_blend_control(state, i));
395 }
396 }
397 return blend;
398 }
399
400 static void *r600_create_blend_state(struct pipe_context *ctx,
401 const struct pipe_blend_state *state)
402 {
403 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
404 }
405
406 static void *r600_create_dsa_state(struct pipe_context *ctx,
407 const struct pipe_depth_stencil_alpha_state *state)
408 {
409 unsigned db_depth_control, alpha_test_control, alpha_ref;
410 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
411
412 if (!dsa) {
413 return NULL;
414 }
415
416 r600_init_command_buffer(&dsa->buffer, 3);
417
418 dsa->valuemask[0] = state->stencil[0].valuemask;
419 dsa->valuemask[1] = state->stencil[1].valuemask;
420 dsa->writemask[0] = state->stencil[0].writemask;
421 dsa->writemask[1] = state->stencil[1].writemask;
422 dsa->zwritemask = state->depth.writemask;
423
424 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
425 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
426 S_028800_ZFUNC(state->depth.func);
427
428 /* stencil */
429 if (state->stencil[0].enabled) {
430 db_depth_control |= S_028800_STENCIL_ENABLE(1);
431 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
432 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
433 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
434 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
435
436 if (state->stencil[1].enabled) {
437 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
438 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
439 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
440 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
441 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
442 }
443 }
444
445 /* alpha */
446 alpha_test_control = 0;
447 alpha_ref = 0;
448 if (state->alpha.enabled) {
449 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
450 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
451 alpha_ref = fui(state->alpha.ref_value);
452 }
453 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
454 dsa->alpha_ref = alpha_ref;
455
456 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
457 return dsa;
458 }
459
460 static void *r600_create_rs_state(struct pipe_context *ctx,
461 const struct pipe_rasterizer_state *state)
462 {
463 struct r600_context *rctx = (struct r600_context *)ctx;
464 unsigned tmp, sc_mode_cntl, spi_interp;
465 float psize_min, psize_max;
466 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
467
468 if (!rs) {
469 return NULL;
470 }
471
472 r600_init_command_buffer(&rs->buffer, 30);
473
474 rs->scissor_enable = state->scissor;
475 rs->flatshade = state->flatshade;
476 rs->sprite_coord_enable = state->sprite_coord_enable;
477 rs->two_side = state->light_twoside;
478 rs->clip_plane_enable = state->clip_plane_enable;
479 rs->pa_sc_line_stipple = state->line_stipple_enable ?
480 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
481 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
482 rs->pa_cl_clip_cntl =
483 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
484 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
485 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
486 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
487 if (rctx->b.chip_class == R700) {
488 rs->pa_cl_clip_cntl |=
489 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
490 }
491 rs->multisample_enable = state->multisample;
492
493 /* offset */
494 rs->offset_units = state->offset_units;
495 rs->offset_scale = state->offset_scale * 16.0f;
496 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
497 rs->offset_units_unscaled = state->offset_units_unscaled;
498
499 if (state->point_size_per_vertex) {
500 psize_min = util_get_min_point_size(state);
501 psize_max = 8192;
502 } else {
503 /* Force the point size to be as if the vertex output was disabled. */
504 psize_min = state->point_size;
505 psize_max = state->point_size;
506 }
507
508 sc_mode_cntl = S_028A4C_MSAA_ENABLE(state->multisample) |
509 S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
510 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
511 S_028A4C_PS_ITER_SAMPLE(state->multisample && rctx->ps_iter_samples > 1);
512 if (rctx->b.family == CHIP_RV770) {
513 /* workaround possible rendering corruption on RV770 with hyperz together with sample shading */
514 sc_mode_cntl |= S_028A4C_TILE_COVER_DISABLE(state->multisample && rctx->ps_iter_samples > 1);
515 }
516 if (rctx->b.chip_class >= R700) {
517 sc_mode_cntl |= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
518 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
519 S_028A4C_R700_VPORT_SCISSOR_ENABLE(1);
520 } else {
521 sc_mode_cntl |= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
522 }
523
524 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
525 if (state->sprite_coord_enable) {
526 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
527 S_0286D4_PNT_SPRITE_OVRD_X(2) |
528 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
529 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
530 S_0286D4_PNT_SPRITE_OVRD_W(1);
531 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
532 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
533 }
534 }
535
536 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
537 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
538 tmp = r600_pack_float_12p4(state->point_size/2);
539 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
540 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
541 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
542 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
543 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
544 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
545 S_028A08_WIDTH(r600_pack_float_12p4(state->line_width/2)));
546
547 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
548 r600_store_context_reg(&rs->buffer, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
549 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
550 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
551 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
552 r600_store_context_reg(&rs->buffer, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
553
554 rs->pa_su_sc_mode_cntl = S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
555 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
556 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
557 S_028814_FACE(!state->front_ccw) |
558 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
559 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
560 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
561 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
562 state->fill_back != PIPE_POLYGON_MODE_FILL) |
563 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
564 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back));
565 if (rctx->b.chip_class == R700) {
566 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL, rs->pa_su_sc_mode_cntl);
567 }
568 if (rctx->b.chip_class == R600) {
569 r600_store_context_reg(&rs->buffer, R_028350_SX_MISC,
570 S_028350_MULTIPASS(state->rasterizer_discard));
571 }
572 return rs;
573 }
574
575 static unsigned r600_tex_filter(unsigned filter, unsigned max_aniso)
576 {
577 if (filter == PIPE_TEX_FILTER_LINEAR)
578 return max_aniso > 1 ? V_03C000_SQ_TEX_XY_FILTER_ANISO_BILINEAR
579 : V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
580 else
581 return max_aniso > 1 ? V_03C000_SQ_TEX_XY_FILTER_ANISO_POINT
582 : V_03C000_SQ_TEX_XY_FILTER_POINT;
583 }
584
585 static void *r600_create_sampler_state(struct pipe_context *ctx,
586 const struct pipe_sampler_state *state)
587 {
588 struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
589 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
590 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
591 : state->max_anisotropy;
592 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
593
594 if (!ss) {
595 return NULL;
596 }
597
598 ss->seamless_cube_map = state->seamless_cube_map;
599 ss->border_color_use = sampler_state_needs_border_color(state);
600
601 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
602 ss->tex_sampler_words[0] =
603 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
604 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
605 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
606 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter, max_aniso)) |
607 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter, max_aniso)) |
608 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
609 S_03C000_MAX_ANISO_RATIO(max_aniso_ratio) |
610 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
611 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
612 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
613 ss->tex_sampler_words[1] =
614 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
615 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
616 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
617 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
618 ss->tex_sampler_words[2] = S_03C008_TYPE(1);
619
620 if (ss->border_color_use) {
621 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
622 }
623 return ss;
624 }
625
626 static struct pipe_sampler_view *
627 texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
628 unsigned width0, unsigned height0)
629
630 {
631 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
632 int stride = util_format_get_blocksize(view->base.format);
633 unsigned format, num_format, format_comp, endian;
634 uint64_t offset = view->base.u.buf.first_element * stride;
635 unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride;
636
637 r600_vertex_data_type(view->base.format,
638 &format, &num_format, &format_comp,
639 &endian);
640
641 view->tex_resource = &tmp->resource;
642 view->skip_mip_address_reloc = true;
643
644 view->tex_resource_words[0] = offset;
645 view->tex_resource_words[1] = size - 1;
646 view->tex_resource_words[2] = S_038008_BASE_ADDRESS_HI(offset >> 32UL) |
647 S_038008_STRIDE(stride) |
648 S_038008_DATA_FORMAT(format) |
649 S_038008_NUM_FORMAT_ALL(num_format) |
650 S_038008_FORMAT_COMP_ALL(format_comp) |
651 S_038008_ENDIAN_SWAP(endian);
652 view->tex_resource_words[3] = 0;
653 /*
654 * in theory dword 4 is for number of elements, for use with resinfo,
655 * but it seems to utterly fail to work, the amd gpu shader analyser
656 * uses a const buffer to store the element sizes for buffer txq
657 */
658 view->tex_resource_words[4] = 0;
659 view->tex_resource_words[5] = 0;
660 view->tex_resource_words[6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_BUFFER);
661 return &view->base;
662 }
663
664 struct pipe_sampler_view *
665 r600_create_sampler_view_custom(struct pipe_context *ctx,
666 struct pipe_resource *texture,
667 const struct pipe_sampler_view *state,
668 unsigned width_first_level, unsigned height_first_level)
669 {
670 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
671 struct r600_texture *tmp = (struct r600_texture*)texture;
672 unsigned format, endian;
673 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
674 unsigned char swizzle[4], array_mode = 0;
675 unsigned width, height, depth, offset_level, last_level;
676 bool do_endian_swap = FALSE;
677
678 if (!view)
679 return NULL;
680
681 /* initialize base object */
682 view->base = *state;
683 view->base.texture = NULL;
684 pipe_reference(NULL, &texture->reference);
685 view->base.texture = texture;
686 view->base.reference.count = 1;
687 view->base.context = ctx;
688
689 if (texture->target == PIPE_BUFFER)
690 return texture_buffer_sampler_view(view, texture->width0, 1);
691
692 swizzle[0] = state->swizzle_r;
693 swizzle[1] = state->swizzle_g;
694 swizzle[2] = state->swizzle_b;
695 swizzle[3] = state->swizzle_a;
696
697 if (R600_BIG_ENDIAN)
698 do_endian_swap = !tmp->db_compatible;
699
700 format = r600_translate_texformat(ctx->screen, state->format,
701 swizzle,
702 &word4, &yuv_format, do_endian_swap);
703 assert(format != ~0);
704 if (format == ~0) {
705 FREE(view);
706 return NULL;
707 }
708
709 if (state->format == PIPE_FORMAT_X24S8_UINT ||
710 state->format == PIPE_FORMAT_S8X24_UINT ||
711 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
712 state->format == PIPE_FORMAT_S8_UINT)
713 view->is_stencil_sampler = true;
714
715 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
716 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
717 FREE(view);
718 return NULL;
719 }
720 tmp = tmp->flushed_depth_texture;
721 }
722
723 endian = r600_colorformat_endian_swap(format, do_endian_swap);
724
725 offset_level = state->u.tex.first_level;
726 last_level = state->u.tex.last_level - offset_level;
727 width = width_first_level;
728 height = height_first_level;
729 depth = u_minify(texture->depth0, offset_level);
730 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
731
732 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
733 height = 1;
734 depth = texture->array_size;
735 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
736 depth = texture->array_size;
737 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
738 depth = texture->array_size / 6;
739
740 switch (tmp->surface.level[offset_level].mode) {
741 default:
742 case RADEON_SURF_MODE_LINEAR_ALIGNED:
743 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
744 break;
745 case RADEON_SURF_MODE_1D:
746 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
747 break;
748 case RADEON_SURF_MODE_2D:
749 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
750 break;
751 }
752
753 view->tex_resource = &tmp->resource;
754 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
755 S_038000_TILE_MODE(array_mode) |
756 S_038000_TILE_TYPE(tmp->non_disp_tiling) |
757 S_038000_PITCH((pitch / 8) - 1) |
758 S_038000_TEX_WIDTH(width - 1));
759 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
760 S_038004_TEX_DEPTH(depth - 1) |
761 S_038004_DATA_FORMAT(format));
762 view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
763 if (offset_level >= tmp->surface.last_level) {
764 view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
765 } else {
766 view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
767 }
768 view->tex_resource_words[4] = (word4 |
769 S_038010_REQUEST_SIZE(1) |
770 S_038010_ENDIAN_SWAP(endian) |
771 S_038010_BASE_LEVEL(0));
772 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
773 S_038014_LAST_ARRAY(state->u.tex.last_layer));
774 if (texture->nr_samples > 1) {
775 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
776 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
777 } else {
778 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
779 }
780 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
781 S_038018_MAX_ANISO(4 /* max 16 samples */));
782 return &view->base;
783 }
784
785 static struct pipe_sampler_view *
786 r600_create_sampler_view(struct pipe_context *ctx,
787 struct pipe_resource *tex,
788 const struct pipe_sampler_view *state)
789 {
790 return r600_create_sampler_view_custom(ctx, tex, state,
791 u_minify(tex->width0, state->u.tex.first_level),
792 u_minify(tex->height0, state->u.tex.first_level));
793 }
794
795 static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
796 {
797 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
798 struct pipe_clip_state *state = &rctx->clip_state.state;
799
800 radeon_set_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4);
801 radeon_emit_array(cs, (unsigned*)state, 6*4);
802 }
803
804 static void r600_set_polygon_stipple(struct pipe_context *ctx,
805 const struct pipe_poly_stipple *state)
806 {
807 }
808
809 static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen,
810 unsigned size, unsigned alignment)
811 {
812 struct pipe_resource buffer;
813
814 memset(&buffer, 0, sizeof buffer);
815 buffer.target = PIPE_BUFFER;
816 buffer.format = PIPE_FORMAT_R8_UNORM;
817 buffer.bind = PIPE_BIND_CUSTOM;
818 buffer.usage = PIPE_USAGE_DEFAULT;
819 buffer.flags = 0;
820 buffer.width0 = size;
821 buffer.height0 = 1;
822 buffer.depth0 = 1;
823 buffer.array_size = 1;
824
825 return (struct r600_resource*)
826 r600_buffer_create(&rscreen->b.b, &buffer, alignment);
827 }
828
829 static void r600_init_color_surface(struct r600_context *rctx,
830 struct r600_surface *surf,
831 bool force_cmask_fmask)
832 {
833 struct r600_screen *rscreen = rctx->screen;
834 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
835 unsigned level = surf->base.u.tex.level;
836 unsigned pitch, slice;
837 unsigned color_info;
838 unsigned color_view;
839 unsigned format, swap, ntype, endian;
840 unsigned offset;
841 const struct util_format_description *desc;
842 int i;
843 bool blend_bypass = 0, blend_clamp = 1, do_endian_swap = FALSE;
844
845 if (rtex->db_compatible && !r600_can_sample_zs(rtex, false)) {
846 r600_init_flushed_depth_texture(&rctx->b.b, surf->base.texture, NULL);
847 rtex = rtex->flushed_depth_texture;
848 assert(rtex);
849 }
850
851 offset = rtex->surface.level[level].offset;
852 color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
853 S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
854
855 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
856 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
857 if (slice) {
858 slice = slice - 1;
859 }
860 color_info = 0;
861 switch (rtex->surface.level[level].mode) {
862 default:
863 case RADEON_SURF_MODE_LINEAR_ALIGNED:
864 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
865 break;
866 case RADEON_SURF_MODE_1D:
867 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
868 break;
869 case RADEON_SURF_MODE_2D:
870 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
871 break;
872 }
873
874 desc = util_format_description(surf->base.format);
875
876 for (i = 0; i < 4; i++) {
877 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
878 break;
879 }
880 }
881
882 ntype = V_0280A0_NUMBER_UNORM;
883 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
884 ntype = V_0280A0_NUMBER_SRGB;
885 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
886 if (desc->channel[i].normalized)
887 ntype = V_0280A0_NUMBER_SNORM;
888 else if (desc->channel[i].pure_integer)
889 ntype = V_0280A0_NUMBER_SINT;
890 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
891 if (desc->channel[i].normalized)
892 ntype = V_0280A0_NUMBER_UNORM;
893 else if (desc->channel[i].pure_integer)
894 ntype = V_0280A0_NUMBER_UINT;
895 }
896
897 if (R600_BIG_ENDIAN)
898 do_endian_swap = !rtex->db_compatible;
899
900 format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format,
901 do_endian_swap);
902 assert(format != ~0);
903
904 swap = r600_translate_colorswap(surf->base.format, do_endian_swap);
905 assert(swap != ~0);
906
907 endian = r600_colorformat_endian_swap(format, do_endian_swap);
908
909 /* set blend bypass according to docs if SINT/UINT or
910 8/24 COLOR variants */
911 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
912 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
913 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
914 blend_clamp = 0;
915 blend_bypass = 1;
916 }
917
918 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
919
920 color_info |= S_0280A0_FORMAT(format) |
921 S_0280A0_COMP_SWAP(swap) |
922 S_0280A0_BLEND_BYPASS(blend_bypass) |
923 S_0280A0_BLEND_CLAMP(blend_clamp) |
924 S_0280A0_NUMBER_TYPE(ntype) |
925 S_0280A0_ENDIAN(endian);
926
927 /* EXPORT_NORM is an optimzation that can be enabled for better
928 * performance in certain cases
929 */
930 if (rctx->b.chip_class == R600) {
931 /* EXPORT_NORM can be enabled if:
932 * - 11-bit or smaller UNORM/SNORM/SRGB
933 * - BLEND_CLAMP is enabled
934 * - BLEND_FLOAT32 is disabled
935 */
936 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
937 (desc->channel[i].size < 12 &&
938 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
939 ntype != V_0280A0_NUMBER_UINT &&
940 ntype != V_0280A0_NUMBER_SINT) &&
941 G_0280A0_BLEND_CLAMP(color_info) &&
942 !G_0280A0_BLEND_FLOAT32(color_info)) {
943 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
944 surf->export_16bpc = true;
945 }
946 } else {
947 /* EXPORT_NORM can be enabled if:
948 * - 11-bit or smaller UNORM/SNORM/SRGB
949 * - 16-bit or smaller FLOAT
950 */
951 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
952 ((desc->channel[i].size < 12 &&
953 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
954 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
955 (desc->channel[i].size < 17 &&
956 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
957 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
958 surf->export_16bpc = true;
959 }
960 }
961
962 /* These might not always be initialized to zero. */
963 surf->cb_color_base = offset >> 8;
964 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
965 S_028060_SLICE_TILE_MAX(slice);
966 surf->cb_color_fmask = surf->cb_color_base;
967 surf->cb_color_cmask = surf->cb_color_base;
968 surf->cb_color_mask = 0;
969
970 r600_resource_reference(&surf->cb_buffer_cmask, &rtex->resource);
971 r600_resource_reference(&surf->cb_buffer_fmask, &rtex->resource);
972
973 if (rtex->cmask.size) {
974 surf->cb_color_cmask = rtex->cmask.offset >> 8;
975 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask.slice_tile_max);
976
977 if (rtex->fmask.size) {
978 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
979 surf->cb_color_fmask = rtex->fmask.offset >> 8;
980 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(rtex->fmask.slice_tile_max);
981 } else { /* cmask only */
982 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
983 }
984 } else if (force_cmask_fmask) {
985 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
986 *
987 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
988 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
989 * because it's not an MSAA buffer.
990 */
991 struct r600_cmask_info cmask;
992 struct r600_fmask_info fmask;
993
994 r600_texture_get_cmask_info(&rscreen->b, rtex, &cmask);
995 r600_texture_get_fmask_info(&rscreen->b, rtex, 8, &fmask);
996
997 /* CMASK. */
998 if (!rctx->dummy_cmask ||
999 rctx->dummy_cmask->b.b.width0 < cmask.size ||
1000 rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
1001 struct pipe_transfer *transfer;
1002 void *ptr;
1003
1004 r600_resource_reference(&rctx->dummy_cmask, NULL);
1005 rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment);
1006
1007 /* Set the contents to 0xCC. */
1008 ptr = pipe_buffer_map(&rctx->b.b, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
1009 memset(ptr, 0xCC, cmask.size);
1010 pipe_buffer_unmap(&rctx->b.b, transfer);
1011 }
1012 r600_resource_reference(&surf->cb_buffer_cmask, rctx->dummy_cmask);
1013
1014 /* FMASK. */
1015 if (!rctx->dummy_fmask ||
1016 rctx->dummy_fmask->b.b.width0 < fmask.size ||
1017 rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1018 r600_resource_reference(&rctx->dummy_fmask, NULL);
1019 rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
1020
1021 }
1022 r600_resource_reference(&surf->cb_buffer_fmask, rctx->dummy_fmask);
1023
1024 /* Init the registers. */
1025 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1026 surf->cb_color_cmask = 0;
1027 surf->cb_color_fmask = 0;
1028 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1029 S_028100_FMASK_TILE_MAX(fmask.slice_tile_max);
1030 }
1031
1032 surf->cb_color_info = color_info;
1033 surf->cb_color_view = color_view;
1034 surf->color_initialized = true;
1035 }
1036
1037 static void r600_init_depth_surface(struct r600_context *rctx,
1038 struct r600_surface *surf)
1039 {
1040 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1041 unsigned level, pitch, slice, format, offset, array_mode;
1042
1043 level = surf->base.u.tex.level;
1044 offset = rtex->surface.level[level].offset;
1045 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1046 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1047 if (slice) {
1048 slice = slice - 1;
1049 }
1050 switch (rtex->surface.level[level].mode) {
1051 case RADEON_SURF_MODE_2D:
1052 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1053 break;
1054 case RADEON_SURF_MODE_1D:
1055 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1056 default:
1057 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1058 break;
1059 }
1060
1061 format = r600_translate_dbformat(surf->base.format);
1062 assert(format != ~0);
1063
1064 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1065 surf->db_depth_base = offset >> 8;
1066 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1067 S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1068 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1069 surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
1070
1071 /* use htile only for first level */
1072 if (rtex->htile_buffer && !level) {
1073 surf->db_htile_data_base = 0;
1074 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) |
1075 S_028D24_HTILE_HEIGHT(1) |
1076 S_028D24_FULL_CACHE(1);
1077 /* preload is not working properly on r6xx/r7xx */
1078 surf->db_depth_info |= S_028010_TILE_SURFACE_ENABLE(1);
1079 }
1080
1081 surf->depth_initialized = true;
1082 }
1083
1084 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1085 const struct pipe_framebuffer_state *state)
1086 {
1087 struct r600_context *rctx = (struct r600_context *)ctx;
1088 struct r600_surface *surf;
1089 struct r600_texture *rtex;
1090 unsigned i;
1091
1092 /* Flush TC when changing the framebuffer state, because the only
1093 * client not using TC that can change textures is the framebuffer.
1094 * Other places don't typically have to flush TC.
1095 */
1096 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE |
1097 R600_CONTEXT_FLUSH_AND_INV |
1098 R600_CONTEXT_FLUSH_AND_INV_CB |
1099 R600_CONTEXT_FLUSH_AND_INV_CB_META |
1100 R600_CONTEXT_FLUSH_AND_INV_DB |
1101 R600_CONTEXT_FLUSH_AND_INV_DB_META |
1102 R600_CONTEXT_INV_TEX_CACHE;
1103
1104 /* Set the new state. */
1105 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1106
1107 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1108 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1109 util_format_is_pure_integer(state->cbufs[0]->format);
1110 rctx->framebuffer.compressed_cb_mask = 0;
1111 rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 &&
1112 state->cbufs[0] && state->cbufs[1] &&
1113 state->cbufs[0]->texture->nr_samples > 1 &&
1114 state->cbufs[1]->texture->nr_samples <= 1;
1115 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1116
1117 /* Colorbuffers. */
1118 for (i = 0; i < state->nr_cbufs; i++) {
1119 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1120 bool force_cmask_fmask = rctx->b.chip_class == R600 &&
1121 rctx->framebuffer.is_msaa_resolve &&
1122 i == 1;
1123
1124 surf = (struct r600_surface*)state->cbufs[i];
1125 if (!surf)
1126 continue;
1127
1128 rtex = (struct r600_texture*)surf->base.texture;
1129 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1130
1131 if (!surf->color_initialized || force_cmask_fmask) {
1132 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1133 if (force_cmask_fmask) {
1134 /* re-initialize later without compression */
1135 surf->color_initialized = false;
1136 }
1137 }
1138
1139 if (!surf->export_16bpc) {
1140 rctx->framebuffer.export_16bpc = false;
1141 }
1142
1143 if (rtex->fmask.size && rtex->cmask.size) {
1144 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1145 }
1146 }
1147
1148 /* Update alpha-test state dependencies.
1149 * Alpha-test is done on the first colorbuffer only. */
1150 if (state->nr_cbufs) {
1151 bool alphatest_bypass = false;
1152
1153 surf = (struct r600_surface*)state->cbufs[0];
1154 if (surf) {
1155 alphatest_bypass = surf->alphatest_bypass;
1156 }
1157
1158 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1159 rctx->alphatest_state.bypass = alphatest_bypass;
1160 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1161 }
1162 }
1163
1164 /* ZS buffer. */
1165 if (state->zsbuf) {
1166 surf = (struct r600_surface*)state->zsbuf;
1167
1168 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1169
1170 if (!surf->depth_initialized) {
1171 r600_init_depth_surface(rctx, surf);
1172 }
1173
1174 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1175 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1176 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1177 }
1178
1179 if (rctx->db_state.rsurf != surf) {
1180 rctx->db_state.rsurf = surf;
1181 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1182 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1183 }
1184 } else if (rctx->db_state.rsurf) {
1185 rctx->db_state.rsurf = NULL;
1186 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1187 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1188 }
1189
1190 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1191 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1192 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1193 }
1194
1195 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1196 rctx->alphatest_state.bypass = false;
1197 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1198 }
1199
1200 /* Calculate the CS size. */
1201 rctx->framebuffer.atom.num_dw =
1202 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1203
1204 if (rctx->framebuffer.state.nr_cbufs) {
1205 rctx->framebuffer.atom.num_dw += 15 * rctx->framebuffer.state.nr_cbufs;
1206 rctx->framebuffer.atom.num_dw += 3 * (2 + rctx->framebuffer.state.nr_cbufs);
1207 }
1208 if (rctx->framebuffer.state.zsbuf) {
1209 rctx->framebuffer.atom.num_dw += 16;
1210 } else if (rctx->screen->b.info.drm_minor >= 18) {
1211 rctx->framebuffer.atom.num_dw += 3;
1212 }
1213 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770) {
1214 rctx->framebuffer.atom.num_dw += 2;
1215 }
1216
1217 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1218
1219 r600_set_sample_locations_constant_buffer(rctx);
1220 }
1221
1222 static uint32_t sample_locs_2x[] = {
1223 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1224 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1225 };
1226 static unsigned max_dist_2x = 4;
1227
1228 static uint32_t sample_locs_4x[] = {
1229 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1230 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1231 };
1232 static unsigned max_dist_4x = 6;
1233 static uint32_t sample_locs_8x[] = {
1234 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1235 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1236 };
1237 static unsigned max_dist_8x = 7;
1238
1239 static void r600_get_sample_position(struct pipe_context *ctx,
1240 unsigned sample_count,
1241 unsigned sample_index,
1242 float *out_value)
1243 {
1244 int offset, index;
1245 struct {
1246 int idx:4;
1247 } val;
1248 switch (sample_count) {
1249 case 1:
1250 default:
1251 out_value[0] = out_value[1] = 0.5;
1252 break;
1253 case 2:
1254 offset = 4 * (sample_index * 2);
1255 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1256 out_value[0] = (float)(val.idx + 8) / 16.0f;
1257 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1258 out_value[1] = (float)(val.idx + 8) / 16.0f;
1259 break;
1260 case 4:
1261 offset = 4 * (sample_index * 2);
1262 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1263 out_value[0] = (float)(val.idx + 8) / 16.0f;
1264 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1265 out_value[1] = (float)(val.idx + 8) / 16.0f;
1266 break;
1267 case 8:
1268 offset = 4 * (sample_index % 4 * 2);
1269 index = (sample_index / 4);
1270 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1271 out_value[0] = (float)(val.idx + 8) / 16.0f;
1272 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1273 out_value[1] = (float)(val.idx + 8) / 16.0f;
1274 break;
1275 }
1276 }
1277
1278 static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1279 {
1280 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1281 unsigned max_dist = 0;
1282
1283 if (rctx->b.family == CHIP_R600) {
1284 switch (nr_samples) {
1285 default:
1286 nr_samples = 0;
1287 break;
1288 case 2:
1289 radeon_set_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1290 max_dist = max_dist_2x;
1291 break;
1292 case 4:
1293 radeon_set_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1294 max_dist = max_dist_4x;
1295 break;
1296 case 8:
1297 radeon_set_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2);
1298 radeon_emit(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1299 radeon_emit(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1300 max_dist = max_dist_8x;
1301 break;
1302 }
1303 } else {
1304 switch (nr_samples) {
1305 default:
1306 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1307 radeon_emit(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1308 radeon_emit(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1309 nr_samples = 0;
1310 break;
1311 case 2:
1312 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1313 radeon_emit(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1314 radeon_emit(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1315 max_dist = max_dist_2x;
1316 break;
1317 case 4:
1318 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1319 radeon_emit(cs, sample_locs_4x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1320 radeon_emit(cs, sample_locs_4x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1321 max_dist = max_dist_4x;
1322 break;
1323 case 8:
1324 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1325 radeon_emit(cs, sample_locs_8x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1326 radeon_emit(cs, sample_locs_8x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1327 max_dist = max_dist_8x;
1328 break;
1329 }
1330 }
1331
1332 if (nr_samples > 1) {
1333 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1334 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1335 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1336 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1337 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1338 } else {
1339 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1340 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1341 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1342 }
1343 }
1344
1345 static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1346 {
1347 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1348 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1349 unsigned nr_cbufs = state->nr_cbufs;
1350 struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0];
1351 unsigned i, sbu = 0;
1352
1353 /* Colorbuffers. */
1354 radeon_set_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8);
1355 for (i = 0; i < nr_cbufs; i++) {
1356 radeon_emit(cs, cb[i] ? cb[i]->cb_color_info : 0);
1357 }
1358 /* set CB_COLOR1_INFO for possible dual-src blending */
1359 if (i == 1 && cb[0]) {
1360 radeon_emit(cs, cb[0]->cb_color_info);
1361 i++;
1362 }
1363 for (; i < 8; i++) {
1364 radeon_emit(cs, 0);
1365 }
1366
1367 if (nr_cbufs) {
1368 for (i = 0; i < nr_cbufs; i++) {
1369 unsigned reloc;
1370
1371 if (!cb[i])
1372 continue;
1373
1374 /* COLOR_BASE */
1375 radeon_set_context_reg(cs, R_028040_CB_COLOR0_BASE + i*4, cb[i]->cb_color_base);
1376
1377 reloc = radeon_add_to_buffer_list(&rctx->b,
1378 &rctx->b.gfx,
1379 (struct r600_resource*)cb[i]->base.texture,
1380 RADEON_USAGE_READWRITE,
1381 cb[i]->base.texture->nr_samples > 1 ?
1382 RADEON_PRIO_COLOR_BUFFER_MSAA :
1383 RADEON_PRIO_COLOR_BUFFER);
1384 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1385 radeon_emit(cs, reloc);
1386
1387 /* FMASK */
1388 radeon_set_context_reg(cs, R_0280E0_CB_COLOR0_FRAG + i*4, cb[i]->cb_color_fmask);
1389
1390 reloc = radeon_add_to_buffer_list(&rctx->b,
1391 &rctx->b.gfx,
1392 cb[i]->cb_buffer_fmask,
1393 RADEON_USAGE_READWRITE,
1394 cb[i]->base.texture->nr_samples > 1 ?
1395 RADEON_PRIO_COLOR_BUFFER_MSAA :
1396 RADEON_PRIO_COLOR_BUFFER);
1397 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1398 radeon_emit(cs, reloc);
1399
1400 /* CMASK */
1401 radeon_set_context_reg(cs, R_0280C0_CB_COLOR0_TILE + i*4, cb[i]->cb_color_cmask);
1402
1403 reloc = radeon_add_to_buffer_list(&rctx->b,
1404 &rctx->b.gfx,
1405 cb[i]->cb_buffer_cmask,
1406 RADEON_USAGE_READWRITE,
1407 cb[i]->base.texture->nr_samples > 1 ?
1408 RADEON_PRIO_COLOR_BUFFER_MSAA :
1409 RADEON_PRIO_COLOR_BUFFER);
1410 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1411 radeon_emit(cs, reloc);
1412 }
1413
1414 radeon_set_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs);
1415 for (i = 0; i < nr_cbufs; i++) {
1416 radeon_emit(cs, cb[i] ? cb[i]->cb_color_size : 0);
1417 }
1418
1419 radeon_set_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs);
1420 for (i = 0; i < nr_cbufs; i++) {
1421 radeon_emit(cs, cb[i] ? cb[i]->cb_color_view : 0);
1422 }
1423
1424 radeon_set_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs);
1425 for (i = 0; i < nr_cbufs; i++) {
1426 radeon_emit(cs, cb[i] ? cb[i]->cb_color_mask : 0);
1427 }
1428
1429 sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs);
1430 }
1431
1432 /* SURFACE_BASE_UPDATE */
1433 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1434 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1435 radeon_emit(cs, sbu);
1436 sbu = 0;
1437 }
1438
1439 /* Zbuffer. */
1440 if (state->zsbuf) {
1441 struct r600_surface *surf = (struct r600_surface*)state->zsbuf;
1442 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1443 &rctx->b.gfx,
1444 (struct r600_resource*)state->zsbuf->texture,
1445 RADEON_USAGE_READWRITE,
1446 surf->base.texture->nr_samples > 1 ?
1447 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1448 RADEON_PRIO_DEPTH_BUFFER);
1449
1450 radeon_set_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2);
1451 radeon_emit(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */
1452 radeon_emit(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */
1453 radeon_set_context_reg_seq(cs, R_02800C_DB_DEPTH_BASE, 2);
1454 radeon_emit(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */
1455 radeon_emit(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */
1456
1457 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1458 radeon_emit(cs, reloc);
1459
1460 radeon_set_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1461
1462 sbu |= SURFACE_BASE_UPDATE_DEPTH;
1463 } else if (rctx->screen->b.info.drm_minor >= 18) {
1464 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1465 * Older kernels are out of luck. */
1466 radeon_set_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID));
1467 }
1468
1469 /* SURFACE_BASE_UPDATE */
1470 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1471 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1472 radeon_emit(cs, sbu);
1473 sbu = 0;
1474 }
1475
1476 /* Framebuffer dimensions. */
1477 radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1478 radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1479 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1480 radeon_emit(cs, S_028244_BR_X(state->width) |
1481 S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1482
1483 if (rctx->framebuffer.is_msaa_resolve) {
1484 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1);
1485 } else {
1486 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1487 * will assure that the alpha-test will work even if there is
1488 * no colorbuffer bound. */
1489 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL,
1490 (1ull << MAX2(nr_cbufs, 1)) - 1);
1491 }
1492
1493 r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1494 }
1495
1496 static void r600_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1497 {
1498 struct r600_context *rctx = (struct r600_context *)ctx;
1499
1500 if (rctx->ps_iter_samples == min_samples)
1501 return;
1502
1503 rctx->ps_iter_samples = min_samples;
1504 if (rctx->framebuffer.nr_samples > 1) {
1505 r600_mark_atom_dirty(rctx, &rctx->rasterizer_state.atom);
1506 if (rctx->b.chip_class == R600)
1507 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1508 }
1509 }
1510
1511 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1512 {
1513 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1514 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1515
1516 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1517 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1518 if (rctx->b.chip_class == R600) {
1519 radeon_emit(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1520 radeon_emit(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1521 } else {
1522 radeon_emit(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1523 radeon_emit(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1524 }
1525 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1526 } else {
1527 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1528 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1529 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1530
1531 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1532 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1533 /* Always enable the first color output to make sure alpha-test works even without one. */
1534 radeon_emit(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1535 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1536 a->cb_color_control |
1537 S_028808_MULTIWRITE_ENABLE(multiwrite));
1538 }
1539 }
1540
1541 static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1542 {
1543 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1544 struct r600_db_state *a = (struct r600_db_state*)atom;
1545
1546 if (a->rsurf && a->rsurf->db_htile_surface) {
1547 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1548 unsigned reloc_idx;
1549
1550 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
1551 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1552 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1553 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rtex->htile_buffer,
1554 RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE);
1555 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1556 radeon_emit(cs, reloc_idx);
1557 } else {
1558 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, 0);
1559 }
1560 }
1561
1562 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1563 {
1564 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1565 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1566 unsigned db_render_control = 0;
1567 unsigned db_render_override =
1568 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1569 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1570
1571 if (rctx->b.chip_class >= R700) {
1572 switch (a->ps_conservative_z) {
1573 default: /* fall through */
1574 case TGSI_FS_DEPTH_LAYOUT_ANY:
1575 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_ANY_Z);
1576 break;
1577 case TGSI_FS_DEPTH_LAYOUT_GREATER:
1578 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_GREATER_THAN_Z);
1579 break;
1580 case TGSI_FS_DEPTH_LAYOUT_LESS:
1581 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_LESS_THAN_Z);
1582 break;
1583 }
1584 }
1585
1586 if (rctx->b.num_occlusion_queries > 0 &&
1587 !a->occlusion_queries_disabled) {
1588 if (rctx->b.chip_class >= R700) {
1589 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1590 }
1591 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1592 } else {
1593 db_render_control |= S_028D0C_ZPASS_INCREMENT_DISABLE(1);
1594 }
1595
1596 if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface) {
1597 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1598 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF);
1599 /* This is to fix a lockup when hyperz and alpha test are enabled at
1600 * the same time somehow GPU get confuse on which order to pick for
1601 * z test
1602 */
1603 if (rctx->alphatest_state.sx_alpha_test_control) {
1604 db_render_override |= S_028D10_FORCE_SHADER_Z_ORDER(1);
1605 }
1606 } else {
1607 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1608 }
1609 if (rctx->b.chip_class == R600 && rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0) {
1610 /* sample shading and hyperz causes lockups on R6xx chips */
1611 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1612 }
1613 if (a->flush_depthstencil_through_cb) {
1614 assert(a->copy_depth || a->copy_stencil);
1615
1616 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1617 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1618 S_028D0C_COPY_CENTROID(1) |
1619 S_028D0C_COPY_SAMPLE(a->copy_sample);
1620
1621 if (rctx->b.chip_class == R600)
1622 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1623
1624 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
1625 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
1626 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1627 } else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
1628 db_render_control |= S_028D0C_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
1629 S_028D0C_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
1630 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1631 }
1632 if (a->htile_clear) {
1633 db_render_control |= S_028D0C_DEPTH_CLEAR_ENABLE(1);
1634 }
1635
1636 /* RV770 workaround for a hang with 8x MSAA. */
1637 if (rctx->b.family == CHIP_RV770 && a->log_samples == 3) {
1638 db_render_override |= S_028D10_MAX_TILES_IN_DTT(6);
1639 }
1640
1641 radeon_set_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1642 radeon_emit(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1643 radeon_emit(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1644 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1645 }
1646
1647 static void r600_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
1648 {
1649 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1650 struct r600_config_state *a = (struct r600_config_state*)atom;
1651
1652 radeon_set_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1);
1653 radeon_set_config_reg(cs, R_008C08_SQ_GPR_RESOURCE_MGMT_2, a->sq_gpr_resource_mgmt_2);
1654 }
1655
1656 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1657 {
1658 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1659 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1660
1661 while (dirty_mask) {
1662 struct pipe_vertex_buffer *vb;
1663 struct r600_resource *rbuffer;
1664 unsigned offset;
1665 unsigned buffer_index = u_bit_scan(&dirty_mask);
1666
1667 vb = &rctx->vertex_buffer_state.vb[buffer_index];
1668 rbuffer = (struct r600_resource*)vb->buffer;
1669 assert(rbuffer);
1670
1671 offset = vb->buffer_offset;
1672
1673 /* fetch resources start at index 320 (OFFSET_FS) */
1674 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1675 radeon_emit(cs, (R600_FETCH_CONSTANTS_OFFSET_FS + buffer_index) * 7);
1676 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1677 radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* RESOURCEi_WORD1 */
1678 radeon_emit(cs, /* RESOURCEi_WORD2 */
1679 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1680 S_038008_STRIDE(vb->stride));
1681 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1682 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1683 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1684 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1685
1686 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1687 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1688 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER));
1689 }
1690 }
1691
1692 static void r600_emit_constant_buffers(struct r600_context *rctx,
1693 struct r600_constbuf_state *state,
1694 unsigned buffer_id_base,
1695 unsigned reg_alu_constbuf_size,
1696 unsigned reg_alu_const_cache)
1697 {
1698 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1699 uint32_t dirty_mask = state->dirty_mask;
1700
1701 while (dirty_mask) {
1702 struct pipe_constant_buffer *cb;
1703 struct r600_resource *rbuffer;
1704 unsigned offset;
1705 unsigned buffer_index = ffs(dirty_mask) - 1;
1706 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
1707 cb = &state->cb[buffer_index];
1708 rbuffer = (struct r600_resource*)cb->buffer;
1709 assert(rbuffer);
1710
1711 offset = cb->buffer_offset;
1712
1713 if (!gs_ring_buffer) {
1714 radeon_set_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1715 DIV_ROUND_UP(cb->buffer_size, 256));
1716 radeon_set_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1717 }
1718
1719 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1720 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1721 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1722
1723 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1724 radeon_emit(cs, (buffer_id_base + buffer_index) * 7);
1725 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1726 radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* RESOURCEi_WORD1 */
1727 radeon_emit(cs, /* RESOURCEi_WORD2 */
1728 S_038008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
1729 S_038008_STRIDE(gs_ring_buffer ? 4 : 16));
1730 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1731 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1732 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1733 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1734
1735 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1736 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1737 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1738
1739 dirty_mask &= ~(1 << buffer_index);
1740 }
1741 state->dirty_mask = 0;
1742 }
1743
1744 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1745 {
1746 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
1747 R600_FETCH_CONSTANTS_OFFSET_VS,
1748 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1749 R_028980_ALU_CONST_CACHE_VS_0);
1750 }
1751
1752 static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1753 {
1754 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
1755 R600_FETCH_CONSTANTS_OFFSET_GS,
1756 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1757 R_0289C0_ALU_CONST_CACHE_GS_0);
1758 }
1759
1760 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1761 {
1762 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
1763 R600_FETCH_CONSTANTS_OFFSET_PS,
1764 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1765 R_028940_ALU_CONST_CACHE_PS_0);
1766 }
1767
1768 static void r600_emit_sampler_views(struct r600_context *rctx,
1769 struct r600_samplerview_state *state,
1770 unsigned resource_id_base)
1771 {
1772 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1773 uint32_t dirty_mask = state->dirty_mask;
1774
1775 while (dirty_mask) {
1776 struct r600_pipe_sampler_view *rview;
1777 unsigned resource_index = u_bit_scan(&dirty_mask);
1778 unsigned reloc;
1779
1780 rview = state->views[resource_index];
1781 assert(rview);
1782
1783 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1784 radeon_emit(cs, (resource_id_base + resource_index) * 7);
1785 radeon_emit_array(cs, rview->tex_resource_words, 7);
1786
1787 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
1788 RADEON_USAGE_READ,
1789 r600_get_sampler_view_priority(rview->tex_resource));
1790 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1791 radeon_emit(cs, reloc);
1792 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1793 radeon_emit(cs, reloc);
1794 }
1795 state->dirty_mask = 0;
1796 }
1797
1798
1799 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1800 {
1801 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, R600_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS);
1802 }
1803
1804 static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1805 {
1806 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, R600_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS);
1807 }
1808
1809 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1810 {
1811 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS);
1812 }
1813
1814 static void r600_emit_sampler_states(struct r600_context *rctx,
1815 struct r600_textures_info *texinfo,
1816 unsigned resource_id_base,
1817 unsigned border_color_reg)
1818 {
1819 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1820 uint32_t dirty_mask = texinfo->states.dirty_mask;
1821
1822 while (dirty_mask) {
1823 struct r600_pipe_sampler_state *rstate;
1824 struct r600_pipe_sampler_view *rview;
1825 unsigned i = u_bit_scan(&dirty_mask);
1826
1827 rstate = texinfo->states.states[i];
1828 assert(rstate);
1829 rview = texinfo->views.views[i];
1830
1831 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1832 * filtering between layers.
1833 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
1834 */
1835 if (rview) {
1836 enum pipe_texture_target target = rview->base.texture->target;
1837 if (target == PIPE_TEXTURE_1D_ARRAY ||
1838 target == PIPE_TEXTURE_2D_ARRAY) {
1839 rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1840 texinfo->is_array_sampler[i] = true;
1841 } else {
1842 rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
1843 texinfo->is_array_sampler[i] = false;
1844 }
1845 }
1846
1847 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
1848 radeon_emit(cs, (resource_id_base + i) * 3);
1849 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
1850
1851 if (rstate->border_color_use) {
1852 unsigned offset;
1853
1854 offset = border_color_reg;
1855 offset += i * 16;
1856 radeon_set_config_reg_seq(cs, offset, 4);
1857 radeon_emit_array(cs, rstate->border_color.ui, 4);
1858 }
1859 }
1860 texinfo->states.dirty_mask = 0;
1861 }
1862
1863 static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1864 {
1865 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
1866 }
1867
1868 static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1869 {
1870 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED);
1871 }
1872
1873 static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1874 {
1875 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
1876 }
1877
1878 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
1879 {
1880 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1881 unsigned tmp;
1882
1883 tmp = S_009508_DISABLE_CUBE_ANISO(1) |
1884 S_009508_SYNC_GRADIENT(1) |
1885 S_009508_SYNC_WALKER(1) |
1886 S_009508_SYNC_ALIGNER(1);
1887 if (!rctx->seamless_cube_map.enabled) {
1888 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
1889 }
1890 radeon_set_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
1891 }
1892
1893 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
1894 {
1895 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
1896 uint8_t mask = s->sample_mask;
1897
1898 radeon_set_context_reg(rctx->b.gfx.cs, R_028C48_PA_SC_AA_MASK,
1899 mask | (mask << 8) | (mask << 16) | (mask << 24));
1900 }
1901
1902 static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
1903 {
1904 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1905 struct r600_cso_state *state = (struct r600_cso_state*)a;
1906 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
1907
1908 radeon_set_context_reg(cs, R_028894_SQ_PGM_START_FS, shader->offset >> 8);
1909 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1910 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
1911 RADEON_USAGE_READ,
1912 RADEON_PRIO_INTERNAL_SHADER));
1913 }
1914
1915 static void r600_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
1916 {
1917 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1918 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
1919
1920 uint32_t v2 = 0, primid = 0;
1921
1922 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
1923 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
1924 primid = 1;
1925 }
1926
1927 if (state->geom_enable) {
1928 uint32_t cut_val;
1929
1930 if (rctx->gs_shader->gs_max_out_vertices <= 128)
1931 cut_val = V_028A40_GS_CUT_128;
1932 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
1933 cut_val = V_028A40_GS_CUT_256;
1934 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
1935 cut_val = V_028A40_GS_CUT_512;
1936 else
1937 cut_val = V_028A40_GS_CUT_1024;
1938
1939 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1940 S_028A40_CUT_MODE(cut_val);
1941
1942 if (rctx->gs_shader->current->shader.gs_prim_id_input)
1943 primid = 1;
1944 }
1945
1946 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
1947 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
1948 }
1949
1950 static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
1951 {
1952 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1953 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
1954 struct r600_resource *rbuffer;
1955
1956 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1957 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1958 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1959
1960 if (state->enable) {
1961 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
1962 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, 0);
1963 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1964 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1965 RADEON_USAGE_READWRITE,
1966 RADEON_PRIO_SHADER_RINGS));
1967 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
1968 state->esgs_ring.buffer_size >> 8);
1969
1970 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
1971 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, 0);
1972 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1973 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1974 RADEON_USAGE_READWRITE,
1975 RADEON_PRIO_SHADER_RINGS));
1976 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
1977 state->gsvs_ring.buffer_size >> 8);
1978 } else {
1979 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
1980 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
1981 }
1982
1983 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1984 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1985 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1986 }
1987
1988 /* Adjust GPR allocation on R6xx/R7xx */
1989 bool r600_adjust_gprs(struct r600_context *rctx)
1990 {
1991 unsigned num_gprs[R600_NUM_HW_STAGES];
1992 unsigned new_gprs[R600_NUM_HW_STAGES];
1993 unsigned cur_gprs[R600_NUM_HW_STAGES];
1994 unsigned def_gprs[R600_NUM_HW_STAGES];
1995 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
1996 unsigned max_gprs;
1997 unsigned tmp, tmp2;
1998 unsigned i;
1999 bool need_recalc = false, use_default = true;
2000
2001 /* hardware will reserve twice num_clause_temp_gprs */
2002 max_gprs = def_num_clause_temp_gprs * 2;
2003 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2004 def_gprs[i] = rctx->default_gprs[i];
2005 max_gprs += def_gprs[i];
2006 }
2007
2008 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2009 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2010 cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2011 cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2012
2013 num_gprs[R600_HW_STAGE_PS] = rctx->ps_shader->current->shader.bc.ngpr;
2014 if (rctx->gs_shader) {
2015 num_gprs[R600_HW_STAGE_ES] = rctx->vs_shader->current->shader.bc.ngpr;
2016 num_gprs[R600_HW_STAGE_GS] = rctx->gs_shader->current->shader.bc.ngpr;
2017 num_gprs[R600_HW_STAGE_VS] = rctx->gs_shader->current->gs_copy_shader->shader.bc.ngpr;
2018 } else {
2019 num_gprs[R600_HW_STAGE_ES] = 0;
2020 num_gprs[R600_HW_STAGE_GS] = 0;
2021 num_gprs[R600_HW_STAGE_VS] = rctx->vs_shader->current->shader.bc.ngpr;
2022 }
2023
2024 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2025 new_gprs[i] = num_gprs[i];
2026 if (new_gprs[i] > cur_gprs[i])
2027 need_recalc = true;
2028 if (new_gprs[i] > def_gprs[i])
2029 use_default = false;
2030 }
2031
2032 /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */
2033 if (!need_recalc)
2034 return true;
2035
2036 /* try to use switch back to default */
2037 if (!use_default) {
2038 /* always privilege vs stage so that at worst we have the
2039 * pixel stage producing wrong output (not the vertex
2040 * stage) */
2041 new_gprs[R600_HW_STAGE_PS] = max_gprs - def_num_clause_temp_gprs * 2;
2042 for (i = R600_HW_STAGE_VS; i < R600_NUM_HW_STAGES; i++)
2043 new_gprs[R600_HW_STAGE_PS] -= new_gprs[i];
2044 } else {
2045 for (i = 0; i < R600_NUM_HW_STAGES; i++)
2046 new_gprs[i] = def_gprs[i];
2047 }
2048
2049 /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <=
2050 * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup
2051 * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS
2052 * it will lockup. So in this case just discard the draw command
2053 * and don't change the current gprs repartitions.
2054 */
2055 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2056 if (num_gprs[i] > new_gprs[i]) {
2057 R600_ERR("shaders require too many register (%d + %d + %d + %d) "
2058 "for a combined maximum of %d\n",
2059 num_gprs[R600_HW_STAGE_PS], num_gprs[R600_HW_STAGE_VS], num_gprs[R600_HW_STAGE_ES], num_gprs[R600_HW_STAGE_GS], max_gprs);
2060 return false;
2061 }
2062 }
2063
2064 /* in some case we endup recomputing the current value */
2065 tmp = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
2066 S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) |
2067 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
2068
2069 tmp2 = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) |
2070 S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]);
2071 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp || rctx->config_state.sq_gpr_resource_mgmt_2 != tmp2) {
2072 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp;
2073 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp2;
2074 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
2075 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
2076 }
2077 return true;
2078 }
2079
2080 void r600_init_atom_start_cs(struct r600_context *rctx)
2081 {
2082 int ps_prio;
2083 int vs_prio;
2084 int gs_prio;
2085 int es_prio;
2086 int num_ps_gprs;
2087 int num_vs_gprs;
2088 int num_gs_gprs;
2089 int num_es_gprs;
2090 int num_temp_gprs;
2091 int num_ps_threads;
2092 int num_vs_threads;
2093 int num_gs_threads;
2094 int num_es_threads;
2095 int num_ps_stack_entries;
2096 int num_vs_stack_entries;
2097 int num_gs_stack_entries;
2098 int num_es_stack_entries;
2099 enum radeon_family family;
2100 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2101 uint32_t tmp, i;
2102
2103 r600_init_command_buffer(cb, 256);
2104
2105 /* R6xx requires this packet at the start of each command buffer */
2106 if (rctx->b.chip_class == R600) {
2107 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2108 r600_store_value(cb, 0);
2109 }
2110 /* All asics require this one */
2111 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2112 r600_store_value(cb, 0x80000000);
2113 r600_store_value(cb, 0x80000000);
2114
2115 /* We're setting config registers here. */
2116 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2117 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2118
2119 /* This enables pipeline stat & streamout queries.
2120 * They are only disabled by blits.
2121 */
2122 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2123 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2124
2125 family = rctx->b.family;
2126 ps_prio = 0;
2127 vs_prio = 1;
2128 gs_prio = 2;
2129 es_prio = 3;
2130 switch (family) {
2131 case CHIP_R600:
2132 num_ps_gprs = 192;
2133 num_vs_gprs = 56;
2134 num_temp_gprs = 4;
2135 num_gs_gprs = 0;
2136 num_es_gprs = 0;
2137 num_ps_threads = 136;
2138 num_vs_threads = 48;
2139 num_gs_threads = 4;
2140 num_es_threads = 4;
2141 num_ps_stack_entries = 128;
2142 num_vs_stack_entries = 128;
2143 num_gs_stack_entries = 0;
2144 num_es_stack_entries = 0;
2145 break;
2146 case CHIP_RV630:
2147 case CHIP_RV635:
2148 num_ps_gprs = 84;
2149 num_vs_gprs = 36;
2150 num_temp_gprs = 4;
2151 num_gs_gprs = 0;
2152 num_es_gprs = 0;
2153 num_ps_threads = 144;
2154 num_vs_threads = 40;
2155 num_gs_threads = 4;
2156 num_es_threads = 4;
2157 num_ps_stack_entries = 40;
2158 num_vs_stack_entries = 40;
2159 num_gs_stack_entries = 32;
2160 num_es_stack_entries = 16;
2161 break;
2162 case CHIP_RV610:
2163 case CHIP_RV620:
2164 case CHIP_RS780:
2165 case CHIP_RS880:
2166 default:
2167 num_ps_gprs = 84;
2168 num_vs_gprs = 36;
2169 num_temp_gprs = 4;
2170 num_gs_gprs = 0;
2171 num_es_gprs = 0;
2172 /* use limits 40 VS and at least 16 ES/GS */
2173 num_ps_threads = 120;
2174 num_vs_threads = 40;
2175 num_gs_threads = 16;
2176 num_es_threads = 16;
2177 num_ps_stack_entries = 40;
2178 num_vs_stack_entries = 40;
2179 num_gs_stack_entries = 32;
2180 num_es_stack_entries = 16;
2181 break;
2182 case CHIP_RV670:
2183 num_ps_gprs = 144;
2184 num_vs_gprs = 40;
2185 num_temp_gprs = 4;
2186 num_gs_gprs = 0;
2187 num_es_gprs = 0;
2188 num_ps_threads = 136;
2189 num_vs_threads = 48;
2190 num_gs_threads = 4;
2191 num_es_threads = 4;
2192 num_ps_stack_entries = 40;
2193 num_vs_stack_entries = 40;
2194 num_gs_stack_entries = 32;
2195 num_es_stack_entries = 16;
2196 break;
2197 case CHIP_RV770:
2198 num_ps_gprs = 130;
2199 num_vs_gprs = 56;
2200 num_temp_gprs = 4;
2201 num_gs_gprs = 31;
2202 num_es_gprs = 31;
2203 num_ps_threads = 180;
2204 num_vs_threads = 60;
2205 num_gs_threads = 4;
2206 num_es_threads = 4;
2207 num_ps_stack_entries = 128;
2208 num_vs_stack_entries = 128;
2209 num_gs_stack_entries = 128;
2210 num_es_stack_entries = 128;
2211 break;
2212 case CHIP_RV730:
2213 case CHIP_RV740:
2214 num_ps_gprs = 84;
2215 num_vs_gprs = 36;
2216 num_temp_gprs = 4;
2217 num_gs_gprs = 0;
2218 num_es_gprs = 0;
2219 num_ps_threads = 180;
2220 num_vs_threads = 60;
2221 num_gs_threads = 4;
2222 num_es_threads = 4;
2223 num_ps_stack_entries = 128;
2224 num_vs_stack_entries = 128;
2225 num_gs_stack_entries = 0;
2226 num_es_stack_entries = 0;
2227 break;
2228 case CHIP_RV710:
2229 num_ps_gprs = 192;
2230 num_vs_gprs = 56;
2231 num_temp_gprs = 4;
2232 num_gs_gprs = 0;
2233 num_es_gprs = 0;
2234 num_ps_threads = 136;
2235 num_vs_threads = 48;
2236 num_gs_threads = 4;
2237 num_es_threads = 4;
2238 num_ps_stack_entries = 128;
2239 num_vs_stack_entries = 128;
2240 num_gs_stack_entries = 0;
2241 num_es_stack_entries = 0;
2242 break;
2243 }
2244
2245 rctx->default_gprs[R600_HW_STAGE_PS] = num_ps_gprs;
2246 rctx->default_gprs[R600_HW_STAGE_VS] = num_vs_gprs;
2247 rctx->default_gprs[R600_HW_STAGE_GS] = 0;
2248 rctx->default_gprs[R600_HW_STAGE_ES] = 0;
2249
2250 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2251
2252 /* SQ_CONFIG */
2253 tmp = 0;
2254 switch (family) {
2255 case CHIP_RV610:
2256 case CHIP_RV620:
2257 case CHIP_RS780:
2258 case CHIP_RS880:
2259 case CHIP_RV710:
2260 break;
2261 default:
2262 tmp |= S_008C00_VC_ENABLE(1);
2263 break;
2264 }
2265 tmp |= S_008C00_DX9_CONSTS(0);
2266 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2267 tmp |= S_008C00_PS_PRIO(ps_prio);
2268 tmp |= S_008C00_VS_PRIO(vs_prio);
2269 tmp |= S_008C00_GS_PRIO(gs_prio);
2270 tmp |= S_008C00_ES_PRIO(es_prio);
2271 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2272
2273 /* SQ_GPR_RESOURCE_MGMT_2 */
2274 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2275 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2276 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2277 r600_store_value(cb, tmp);
2278
2279 /* SQ_THREAD_RESOURCE_MGMT */
2280 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2281 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2282 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2283 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2284 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2285
2286 /* SQ_STACK_RESOURCE_MGMT_1 */
2287 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2288 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2289 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2290
2291 /* SQ_STACK_RESOURCE_MGMT_2 */
2292 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2293 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2294 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2295
2296 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2297
2298 if (rctx->b.chip_class >= R700) {
2299 r600_store_context_reg(cb, R_028A50_VGT_ENHANCE, 4);
2300 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2301 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2302 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2303 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2304 } else {
2305 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2306 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2307 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2308 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2309 }
2310 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2311 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2312 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2313 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2314 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2315 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2316 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2317 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2318 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2319 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2320
2321 /* to avoid GPU doing any preloading of constant from random address */
2322 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2323 for (i = 0; i < 16; i++)
2324 r600_store_value(cb, 0);
2325
2326 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2327 for (i = 0; i < 16; i++)
2328 r600_store_value(cb, 0);
2329
2330 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2331 for (i = 0; i < 16; i++)
2332 r600_store_value(cb, 0);
2333
2334 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2335 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2336 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2337 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2338 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2339 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2340 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2341 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2342 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2343 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2344 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2345 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2346 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2347 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2348
2349 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2350 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2351 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2352
2353 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2354 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2355 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2356
2357 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2358
2359 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2360
2361 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2362
2363 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2364 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2365 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2366 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2367
2368 r600_store_context_reg_seq(cb, R_028D28_DB_SRESULTS_COMPARE_STATE0, 3);
2369 r600_store_value(cb, 0); /* R_028D28_DB_SRESULTS_COMPARE_STATE0 */
2370 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2371 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2372
2373 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2374 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2375
2376 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS);
2377 for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) {
2378 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2379 r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2380 }
2381
2382 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2383 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2384
2385 if (rctx->b.chip_class >= R700) {
2386 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2387 }
2388
2389 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2390 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2391 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2392 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2393 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2394
2395 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2396 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2397 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2398
2399 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2400 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2401 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2402
2403 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 5);
2404 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2405 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2406 r600_store_value(cb, 0); /* R_0288D4_SQ_PGM_CF_OFFSET_GS */
2407 r600_store_value(cb, 0); /* R_0288D8_SQ_PGM_CF_OFFSET_ES */
2408 r600_store_value(cb, 0); /* R_0288DC_SQ_PGM_CF_OFFSET_FS */
2409
2410 r600_store_context_reg(cb, R_0288E0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2411
2412 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2413 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2414 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2415
2416 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2417
2418 if (rctx->b.chip_class == R700)
2419 r600_store_context_reg(cb, R_028350_SX_MISC, 0);
2420 if (rctx->b.chip_class == R700 && rctx->screen->b.has_streamout)
2421 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2422
2423 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2424 if (rctx->screen->b.has_streamout) {
2425 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2426 }
2427
2428 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2429 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2430 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (64 * 4), 0x1000FFF);
2431 }
2432
2433 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2434 {
2435 struct r600_context *rctx = (struct r600_context *)ctx;
2436 struct r600_command_buffer *cb = &shader->command_buffer;
2437 struct r600_shader *rshader = &shader->shader;
2438 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2439 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
2440 unsigned tmp, sid, ufi = 0;
2441 int need_linear = 0;
2442 unsigned z_export = 0, stencil_export = 0, mask_export = 0;
2443 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2444
2445 if (!cb->buf) {
2446 r600_init_command_buffer(cb, 64);
2447 } else {
2448 cb->num_dw = 0;
2449 }
2450
2451 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, rshader->ninput);
2452 for (i = 0; i < rshader->ninput; i++) {
2453 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2454 pos_index = i;
2455 if (rshader->input[i].name == TGSI_SEMANTIC_FACE && face_index == -1)
2456 face_index = i;
2457 if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID)
2458 fixed_pt_position_index = i;
2459
2460 sid = rshader->input[i].spi_sid;
2461
2462 tmp = S_028644_SEMANTIC(sid);
2463
2464 /* D3D 9 behaviour. GL is undefined */
2465 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR && rshader->input[i].sid == 0)
2466 tmp |= S_028644_DEFAULT_VAL(3);
2467
2468 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2469 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2470 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2471 rctx->rasterizer && rctx->rasterizer->flatshade))
2472 tmp |= S_028644_FLAT_SHADE(1);
2473
2474 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2475 sprite_coord_enable & (1 << rshader->input[i].sid)) {
2476 tmp |= S_028644_PT_SPRITE_TEX(1);
2477 }
2478
2479 if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID)
2480 tmp |= S_028644_SEL_CENTROID(1);
2481
2482 if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE)
2483 tmp |= S_028644_SEL_SAMPLE(1);
2484
2485 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2486 need_linear = 1;
2487 tmp |= S_028644_SEL_LINEAR(1);
2488 }
2489
2490 r600_store_value(cb, tmp);
2491 }
2492
2493 db_shader_control = 0;
2494 for (i = 0; i < rshader->noutput; i++) {
2495 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2496 z_export = 1;
2497 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2498 stencil_export = 1;
2499 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK &&
2500 rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0)
2501 mask_export = 1;
2502 }
2503 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2504 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2505 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
2506 if (rshader->uses_kill)
2507 db_shader_control |= S_02880C_KILL_ENABLE(1);
2508
2509 exports_ps = 0;
2510 for (i = 0; i < rshader->noutput; i++) {
2511 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2512 rshader->output[i].name == TGSI_SEMANTIC_STENCIL ||
2513 rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
2514 exports_ps |= 1;
2515 }
2516 }
2517 num_cout = rshader->nr_ps_color_exports;
2518 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2519 if (!exports_ps) {
2520 /* always at least export 1 component per pixel */
2521 exports_ps = 2;
2522 }
2523
2524 shader->nr_ps_color_outputs = num_cout;
2525
2526 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2527 S_0286CC_PERSP_GRADIENT_ENA(1)|
2528 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2529 spi_input_z = 0;
2530 if (pos_index != -1) {
2531 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2532 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
2533 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2534 S_0286CC_BARYC_SAMPLE_CNTL(1)) |
2535 S_0286CC_POSITION_SAMPLE(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE);
2536 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
2537 }
2538
2539 spi_ps_in_control_1 = 0;
2540 if (face_index != -1) {
2541 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2542 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2543 }
2544 if (fixed_pt_position_index != -1) {
2545 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
2546 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
2547 }
2548
2549 /* HW bug in original R600 */
2550 if (rctx->b.family == CHIP_R600)
2551 ufi = 1;
2552
2553 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
2554 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
2555 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
2556
2557 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
2558
2559 r600_store_context_reg_seq(cb, R_028850_SQ_PGM_RESOURCES_PS, 2);
2560 r600_store_value(cb, /* R_028850_SQ_PGM_RESOURCES_PS*/
2561 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2562 S_028850_STACK_SIZE(rshader->bc.nstack) |
2563 S_028850_UNCACHED_FIRST_INST(ufi));
2564 r600_store_value(cb, exports_ps); /* R_028854_SQ_PGM_EXPORTS_PS */
2565
2566 r600_store_context_reg(cb, R_028840_SQ_PGM_START_PS, 0);
2567 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2568
2569 /* only set some bits here, the other bits are set in the dsa state */
2570 shader->db_shader_control = db_shader_control;
2571 shader->ps_depth_export = z_export | stencil_export | mask_export;
2572
2573 shader->sprite_coord_enable = sprite_coord_enable;
2574 if (rctx->rasterizer)
2575 shader->flatshade = rctx->rasterizer->flatshade;
2576 }
2577
2578 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2579 {
2580 struct r600_command_buffer *cb = &shader->command_buffer;
2581 struct r600_shader *rshader = &shader->shader;
2582 unsigned spi_vs_out_id[10] = {};
2583 unsigned i, tmp, nparams = 0;
2584
2585 for (i = 0; i < rshader->noutput; i++) {
2586 if (rshader->output[i].spi_sid) {
2587 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2588 spi_vs_out_id[nparams / 4] |= tmp;
2589 nparams++;
2590 }
2591 }
2592
2593 r600_init_command_buffer(cb, 32);
2594
2595 r600_store_context_reg_seq(cb, R_028614_SPI_VS_OUT_ID_0, 10);
2596 for (i = 0; i < 10; i++) {
2597 r600_store_value(cb, spi_vs_out_id[i]);
2598 }
2599
2600 /* Certain attributes (position, psize, etc.) don't count as params.
2601 * VS is required to export at least one param and r600_shader_from_tgsi()
2602 * takes care of adding a dummy export.
2603 */
2604 if (nparams < 1)
2605 nparams = 1;
2606
2607 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
2608 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2609 r600_store_context_reg(cb, R_028868_SQ_PGM_RESOURCES_VS,
2610 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2611 S_028868_STACK_SIZE(rshader->bc.nstack));
2612 if (rshader->vs_position_window_space) {
2613 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
2614 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
2615 } else {
2616 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
2617 S_028818_VTX_W0_FMT(1) |
2618 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2619 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2620 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2621
2622 }
2623 r600_store_context_reg(cb, R_028858_SQ_PGM_START_VS, 0);
2624 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2625
2626 shader->pa_cl_vs_out_cntl =
2627 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2628 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2629 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2630 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
2631 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
2632 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer) |
2633 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport);
2634 }
2635
2636 #define RV610_GSVS_ALIGN 32
2637 #define R600_GSVS_ALIGN 16
2638
2639 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2640 {
2641 struct r600_context *rctx = (struct r600_context *)ctx;
2642 struct r600_command_buffer *cb = &shader->command_buffer;
2643 struct r600_shader *rshader = &shader->shader;
2644 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
2645 unsigned gsvs_itemsize =
2646 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2;
2647
2648 /* some r600s needs gsvs itemsize aligned to cacheline size
2649 this was fixed in rs780 and above. */
2650 switch (rctx->b.family) {
2651 case CHIP_RV610:
2652 gsvs_itemsize = align(gsvs_itemsize, RV610_GSVS_ALIGN);
2653 break;
2654 case CHIP_R600:
2655 case CHIP_RV630:
2656 case CHIP_RV670:
2657 case CHIP_RV620:
2658 case CHIP_RV635:
2659 gsvs_itemsize = align(gsvs_itemsize, R600_GSVS_ALIGN);
2660 break;
2661 default:
2662 break;
2663 }
2664
2665 r600_init_command_buffer(cb, 64);
2666
2667 /* VGT_GS_MODE is written by r600_emit_shader_stages */
2668 r600_store_context_reg(cb, R_028AB8_VGT_VTX_CNT_EN, 1);
2669
2670 if (rctx->b.chip_class >= R700) {
2671 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
2672 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
2673 }
2674 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
2675 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
2676
2677 r600_store_context_reg(cb, R_0288C8_SQ_GS_VERT_ITEMSIZE,
2678 cp_shader->ring_item_sizes[0] >> 2);
2679
2680 r600_store_context_reg(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE,
2681 (rshader->ring_item_sizes[0]) >> 2);
2682
2683 r600_store_context_reg(cb, R_0288AC_SQ_GSVS_RING_ITEMSIZE,
2684 gsvs_itemsize);
2685
2686 /* FIXME calculate these values somehow ??? */
2687 r600_store_config_reg_seq(cb, R_0088C8_VGT_GS_PER_ES, 2);
2688 r600_store_value(cb, 0x80); /* GS_PER_ES */
2689 r600_store_value(cb, 0x100); /* ES_PER_GS */
2690 r600_store_config_reg_seq(cb, R_0088E8_VGT_GS_PER_VS, 1);
2691 r600_store_value(cb, 0x2); /* GS_PER_VS */
2692
2693 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_GS,
2694 S_02887C_NUM_GPRS(rshader->bc.ngpr) |
2695 S_02887C_STACK_SIZE(rshader->bc.nstack));
2696 r600_store_context_reg(cb, R_02886C_SQ_PGM_START_GS, 0);
2697 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2698 }
2699
2700 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2701 {
2702 struct r600_command_buffer *cb = &shader->command_buffer;
2703 struct r600_shader *rshader = &shader->shader;
2704
2705 r600_init_command_buffer(cb, 32);
2706
2707 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
2708 S_028890_NUM_GPRS(rshader->bc.ngpr) |
2709 S_028890_STACK_SIZE(rshader->bc.nstack));
2710 r600_store_context_reg(cb, R_028880_SQ_PGM_START_ES, 0);
2711 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2712 }
2713
2714
2715 void *r600_create_resolve_blend(struct r600_context *rctx)
2716 {
2717 struct pipe_blend_state blend;
2718 unsigned i;
2719
2720 memset(&blend, 0, sizeof(blend));
2721 blend.independent_blend_enable = true;
2722 for (i = 0; i < 2; i++) {
2723 blend.rt[i].colormask = 0xf;
2724 blend.rt[i].blend_enable = 1;
2725 blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2726 blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2727 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2728 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2729 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2730 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2731 }
2732 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2733 }
2734
2735 void *r700_create_resolve_blend(struct r600_context *rctx)
2736 {
2737 struct pipe_blend_state blend;
2738
2739 memset(&blend, 0, sizeof(blend));
2740 blend.independent_blend_enable = true;
2741 blend.rt[0].colormask = 0xf;
2742 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2743 }
2744
2745 void *r600_create_decompress_blend(struct r600_context *rctx)
2746 {
2747 struct pipe_blend_state blend;
2748
2749 memset(&blend, 0, sizeof(blend));
2750 blend.independent_blend_enable = true;
2751 blend.rt[0].colormask = 0xf;
2752 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2753 }
2754
2755 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2756 {
2757 struct pipe_depth_stencil_alpha_state dsa;
2758 boolean quirk = false;
2759
2760 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
2761 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
2762 quirk = true;
2763
2764 memset(&dsa, 0, sizeof(dsa));
2765
2766 if (quirk) {
2767 dsa.depth.enabled = 1;
2768 dsa.depth.func = PIPE_FUNC_LEQUAL;
2769 dsa.stencil[0].enabled = 1;
2770 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2771 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2772 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2773 dsa.stencil[0].writemask = 0xff;
2774 }
2775
2776 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
2777 }
2778
2779 void r600_update_db_shader_control(struct r600_context * rctx)
2780 {
2781 bool dual_export;
2782 unsigned db_shader_control;
2783 uint8_t ps_conservative_z;
2784
2785 if (!rctx->ps_shader) {
2786 return;
2787 }
2788
2789 dual_export = rctx->framebuffer.export_16bpc &&
2790 !rctx->ps_shader->current->ps_depth_export;
2791
2792 db_shader_control = rctx->ps_shader->current->db_shader_control |
2793 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2794
2795 ps_conservative_z = rctx->ps_shader->current->shader.ps_conservative_z;
2796
2797 /* When alpha test is enabled we can't trust the hw to make the proper
2798 * decision on the order in which ztest should be run related to fragment
2799 * shader execution.
2800 *
2801 * If alpha test is enabled perform z test after fragment. RE_Z (early
2802 * z test but no write to the zbuffer) seems to cause lockup on r6xx/r7xx
2803 */
2804 if (rctx->alphatest_state.sx_alpha_test_control) {
2805 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
2806 } else {
2807 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2808 }
2809
2810 if (db_shader_control != rctx->db_misc_state.db_shader_control ||
2811 ps_conservative_z != rctx->db_misc_state.ps_conservative_z) {
2812 rctx->db_misc_state.db_shader_control = db_shader_control;
2813 rctx->db_misc_state.ps_conservative_z = ps_conservative_z;
2814 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
2815 }
2816 }
2817
2818 static inline unsigned r600_array_mode(unsigned mode)
2819 {
2820 switch (mode) {
2821 default:
2822 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_0280A0_ARRAY_LINEAR_ALIGNED;
2823 break;
2824 case RADEON_SURF_MODE_1D: return V_0280A0_ARRAY_1D_TILED_THIN1;
2825 break;
2826 case RADEON_SURF_MODE_2D: return V_0280A0_ARRAY_2D_TILED_THIN1;
2827 }
2828 }
2829
2830 static boolean r600_dma_copy_tile(struct r600_context *rctx,
2831 struct pipe_resource *dst,
2832 unsigned dst_level,
2833 unsigned dst_x,
2834 unsigned dst_y,
2835 unsigned dst_z,
2836 struct pipe_resource *src,
2837 unsigned src_level,
2838 unsigned src_x,
2839 unsigned src_y,
2840 unsigned src_z,
2841 unsigned copy_height,
2842 unsigned pitch,
2843 unsigned bpp)
2844 {
2845 struct radeon_winsys_cs *cs = rctx->b.dma.cs;
2846 struct r600_texture *rsrc = (struct r600_texture*)src;
2847 struct r600_texture *rdst = (struct r600_texture*)dst;
2848 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
2849 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
2850 uint64_t base, addr;
2851
2852 dst_mode = rdst->surface.level[dst_level].mode;
2853 src_mode = rsrc->surface.level[src_level].mode;
2854 assert(dst_mode != src_mode);
2855
2856 y = 0;
2857 lbpp = util_logbase2(bpp);
2858 pitch_tile_max = ((pitch / bpp) / 8) - 1;
2859
2860 if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) {
2861 /* T2L */
2862 array_mode = r600_array_mode(src_mode);
2863 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8);
2864 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2865 /* linear height must be the same as the slice tile max height, it's ok even
2866 * if the linear destination/source have smaller heigh as the size of the
2867 * dma packet will be using the copy_height which is always smaller or equal
2868 * to the linear height
2869 */
2870 height = rsrc->surface.level[src_level].npix_y;
2871 detile = 1;
2872 x = src_x;
2873 y = src_y;
2874 z = src_z;
2875 base = rsrc->surface.level[src_level].offset;
2876 addr = rdst->surface.level[dst_level].offset;
2877 addr += rdst->surface.level[dst_level].slice_size * dst_z;
2878 addr += dst_y * pitch + dst_x * bpp;
2879 } else {
2880 /* L2T */
2881 array_mode = r600_array_mode(dst_mode);
2882 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8);
2883 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2884 /* linear height must be the same as the slice tile max height, it's ok even
2885 * if the linear destination/source have smaller heigh as the size of the
2886 * dma packet will be using the copy_height which is always smaller or equal
2887 * to the linear height
2888 */
2889 height = rdst->surface.level[dst_level].npix_y;
2890 detile = 0;
2891 x = dst_x;
2892 y = dst_y;
2893 z = dst_z;
2894 base = rdst->surface.level[dst_level].offset;
2895 addr = rsrc->surface.level[src_level].offset;
2896 addr += rsrc->surface.level[src_level].slice_size * src_z;
2897 addr += src_y * pitch + src_x * bpp;
2898 }
2899 /* check that we are in dw/base alignment constraint */
2900 if (addr % 4 || base % 256) {
2901 return FALSE;
2902 }
2903
2904 /* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for number
2905 * line in the blit. Compute max 8 line we can copy in the size limit
2906 */
2907 cheight = ((R600_DMA_COPY_MAX_SIZE_DW * 4) / pitch) & 0xfffffff8;
2908 ncopy = (copy_height / cheight) + !!(copy_height % cheight);
2909 r600_need_dma_space(&rctx->b, ncopy * 7, &rdst->resource, &rsrc->resource);
2910
2911 for (i = 0; i < ncopy; i++) {
2912 cheight = cheight > copy_height ? copy_height : cheight;
2913 size = (cheight * pitch) / 4;
2914 /* emit reloc before writing cs so that cs is always in consistent state */
2915 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource, RADEON_USAGE_READ,
2916 RADEON_PRIO_SDMA_TEXTURE);
2917 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource, RADEON_USAGE_WRITE,
2918 RADEON_PRIO_SDMA_TEXTURE);
2919 radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, 1, 0, size));
2920 radeon_emit(cs, base >> 8);
2921 radeon_emit(cs, (detile << 31) | (array_mode << 27) |
2922 (lbpp << 24) | ((height - 1) << 10) |
2923 pitch_tile_max);
2924 radeon_emit(cs, (slice_tile_max << 12) | (z << 0));
2925 radeon_emit(cs, (x << 3) | (y << 17));
2926 radeon_emit(cs, addr & 0xfffffffc);
2927 radeon_emit(cs, (addr >> 32UL) & 0xff);
2928 copy_height -= cheight;
2929 addr += cheight * pitch;
2930 y += cheight;
2931 }
2932 r600_dma_emit_wait_idle(&rctx->b);
2933 return TRUE;
2934 }
2935
2936 static void r600_dma_copy(struct pipe_context *ctx,
2937 struct pipe_resource *dst,
2938 unsigned dst_level,
2939 unsigned dstx, unsigned dsty, unsigned dstz,
2940 struct pipe_resource *src,
2941 unsigned src_level,
2942 const struct pipe_box *src_box)
2943 {
2944 struct r600_context *rctx = (struct r600_context *)ctx;
2945 struct r600_texture *rsrc = (struct r600_texture*)src;
2946 struct r600_texture *rdst = (struct r600_texture*)dst;
2947 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
2948 unsigned src_w, dst_w;
2949 unsigned src_x, src_y;
2950 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
2951
2952 if (rctx->b.dma.cs == NULL) {
2953 goto fallback;
2954 }
2955
2956 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
2957 if (dst_x % 4 || src_box->x % 4 || src_box->width % 4)
2958 goto fallback;
2959
2960 r600_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
2961 return;
2962 }
2963
2964 if (src_box->depth > 1 ||
2965 !r600_prepare_for_dma_blit(&rctx->b, rdst, dst_level, dstx, dsty,
2966 dstz, rsrc, src_level, src_box))
2967 goto fallback;
2968
2969 src_x = util_format_get_nblocksx(src->format, src_box->x);
2970 dst_x = util_format_get_nblocksx(src->format, dst_x);
2971 src_y = util_format_get_nblocksy(src->format, src_box->y);
2972 dst_y = util_format_get_nblocksy(src->format, dst_y);
2973
2974 bpp = rdst->surface.bpe;
2975 dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
2976 src_pitch = rsrc->surface.level[src_level].pitch_bytes;
2977 src_w = rsrc->surface.level[src_level].npix_x;
2978 dst_w = rdst->surface.level[dst_level].npix_x;
2979 copy_height = src_box->height / rsrc->surface.blk_h;
2980
2981 dst_mode = rdst->surface.level[dst_level].mode;
2982 src_mode = rsrc->surface.level[src_level].mode;
2983
2984 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
2985 /* strict requirement on r6xx/r7xx */
2986 goto fallback;
2987 }
2988 /* lot of constraint on alignment this should capture them all */
2989 if (src_pitch % 8 || src_box->y % 8 || dst_y % 8) {
2990 goto fallback;
2991 }
2992
2993 if (src_mode == dst_mode) {
2994 uint64_t dst_offset, src_offset, size;
2995
2996 /* simple dma blit would do NOTE code here assume :
2997 * src_box.x/y == 0
2998 * dst_x/y == 0
2999 * dst_pitch == src_pitch
3000 */
3001 src_offset= rsrc->surface.level[src_level].offset;
3002 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
3003 src_offset += src_y * src_pitch + src_x * bpp;
3004 dst_offset = rdst->surface.level[dst_level].offset;
3005 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
3006 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3007 size = src_box->height * src_pitch;
3008 /* must be dw aligned */
3009 if (dst_offset % 4 || src_offset % 4 || size % 4) {
3010 goto fallback;
3011 }
3012 r600_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset, size);
3013 } else {
3014 if (!r600_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3015 src, src_level, src_x, src_y, src_box->z,
3016 copy_height, dst_pitch, bpp)) {
3017 goto fallback;
3018 }
3019 }
3020 return;
3021
3022 fallback:
3023 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3024 src, src_level, src_box);
3025 }
3026
3027 void r600_init_state_functions(struct r600_context *rctx)
3028 {
3029 unsigned id = 1;
3030 unsigned i;
3031 /* !!!
3032 * To avoid GPU lockup registers must be emited in a specific order
3033 * (no kidding ...). The order below is important and have been
3034 * partialy infered from analyzing fglrx command stream.
3035 *
3036 * Don't reorder atom without carefully checking the effect (GPU lockup
3037 * or piglit regression).
3038 * !!!
3039 */
3040
3041 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0);
3042
3043 /* shader const */
3044 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
3045 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
3046 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
3047
3048 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
3049 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
3050 */
3051 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
3052 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
3053 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0);
3054 /* resource */
3055 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0);
3056 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0);
3057 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
3058 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
3059
3060 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
3061
3062 r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
3063 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
3064 rctx->sample_mask.sample_mask = ~0;
3065
3066 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3067 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3068 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3069 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
3070 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
3071 r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
3072 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 7);
3073 r600_init_atom(rctx, &rctx->db_state.atom, id++, r600_emit_db_state, 11);
3074 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3075 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 9);
3076 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3077 r600_add_atom(rctx, &rctx->b.scissors.atom, id++);
3078 r600_add_atom(rctx, &rctx->b.viewports.atom, id++);
3079 r600_init_atom(rctx, &rctx->config_state.atom, id++, r600_emit_config_state, 3);
3080 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3081 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, r600_emit_vertex_fetch_shader, 5);
3082 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
3083 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
3084 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
3085 for (i = 0; i < R600_NUM_HW_STAGES; i++)
3086 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
3087 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, r600_emit_shader_stages, 0);
3088 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, r600_emit_gs_rings, 0);
3089
3090 rctx->b.b.create_blend_state = r600_create_blend_state;
3091 rctx->b.b.create_depth_stencil_alpha_state = r600_create_dsa_state;
3092 rctx->b.b.create_rasterizer_state = r600_create_rs_state;
3093 rctx->b.b.create_sampler_state = r600_create_sampler_state;
3094 rctx->b.b.create_sampler_view = r600_create_sampler_view;
3095 rctx->b.b.set_framebuffer_state = r600_set_framebuffer_state;
3096 rctx->b.b.set_polygon_stipple = r600_set_polygon_stipple;
3097 rctx->b.b.set_min_samples = r600_set_min_samples;
3098 rctx->b.b.get_sample_position = r600_get_sample_position;
3099 rctx->b.dma_copy = r600_dma_copy;
3100 }
3101 /* this function must be last */