radeonsi: parse and dump status registers on GPU hang
[mesa.git] / src / gallium / drivers / radeonsi / si_debug.c
1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Marek Olšák <maraeo@gmail.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "sid_tables.h"
31
32
33 static void si_dump_shader(struct si_shader_selector *sel, const char *name,
34 FILE *f)
35 {
36 if (!sel || !sel->current)
37 return;
38
39 fprintf(f, "%s shader disassembly:\n", name);
40 si_dump_shader_key(sel->type, &sel->current->key, f);
41 fprintf(f, "%s\n\n", sel->current->binary.disasm_string);
42 }
43
44 /* Parsed IBs are difficult to read without colors. Use "less -R file" to
45 * read them, or use "aha -b -f file" to convert them to html.
46 */
47 #define COLOR_RESET "\033[0m"
48 #define COLOR_RED "\033[31m"
49 #define COLOR_GREEN "\033[1;32m"
50 #define COLOR_YELLOW "\033[1;33m"
51 #define COLOR_CYAN "\033[1;36m"
52
53 #define INDENT_PKT 8
54
55 static void print_spaces(FILE *f, unsigned num)
56 {
57 fprintf(f, "%*s", num, "");
58 }
59
60 static void print_value(FILE *file, uint32_t value, int bits)
61 {
62 /* Guess if it's int or float */
63 if (value <= (1 << 15))
64 fprintf(file, "%u\n", value);
65 else {
66 float f = uif(value);
67
68 if (fabs(f) < 100000 && f*10 == floor(f*10))
69 fprintf(file, "%.1ff\n", f);
70 else
71 /* Don't print more leading zeros than there are bits. */
72 fprintf(file, "0x%0*x\n", bits / 4, value);
73 }
74 }
75
76 static void print_named_value(FILE *file, const char *name, uint32_t value,
77 int bits)
78 {
79 print_spaces(file, INDENT_PKT);
80 fprintf(file, COLOR_YELLOW "%s" COLOR_RESET " <- ", name);
81 print_value(file, value, bits);
82 }
83
84 static void si_dump_reg(FILE *file, unsigned offset, uint32_t value,
85 uint32_t field_mask)
86 {
87 int r, f;
88
89 for (r = 0; r < ARRAY_SIZE(reg_table); r++) {
90 const struct si_reg *reg = &reg_table[r];
91
92 if (reg->offset == offset) {
93 bool first_field = true;
94
95 print_spaces(file, INDENT_PKT);
96 fprintf(file, COLOR_YELLOW "%s" COLOR_RESET " <- ",
97 reg->name);
98
99 if (!reg->num_fields) {
100 print_value(file, value, 32);
101 return;
102 }
103
104 for (f = 0; f < reg->num_fields; f++) {
105 const struct si_field *field = &reg->fields[f];
106 uint32_t val = (value & field->mask) >>
107 (ffs(field->mask) - 1);
108
109 if (!(field->mask & field_mask))
110 continue;
111
112 /* Indent the field. */
113 if (!first_field)
114 print_spaces(file,
115 INDENT_PKT + strlen(reg->name) + 4);
116
117 /* Print the field. */
118 fprintf(file, "%s = ", field->name);
119
120 if (val < field->num_values && field->values[val])
121 fprintf(file, "%s\n", field->values[val]);
122 else
123 print_value(file, val,
124 util_bitcount(field->mask));
125
126 first_field = false;
127 }
128 return;
129 }
130 }
131
132 fprintf(file, COLOR_YELLOW "0x%05x" COLOR_RESET " = 0x%08x", offset, value);
133 }
134
135 static void si_parse_set_reg_packet(FILE *f, uint32_t *ib, unsigned count,
136 unsigned reg_offset)
137 {
138 unsigned reg = (ib[1] << 2) + reg_offset;
139 int i;
140
141 for (i = 0; i < count; i++)
142 si_dump_reg(f, reg + i*4, ib[2+i], ~0);
143 }
144
145 static uint32_t *si_parse_packet3(FILE *f, uint32_t *ib, int *num_dw)
146 {
147 unsigned count = PKT_COUNT_G(ib[0]);
148 unsigned op = PKT3_IT_OPCODE_G(ib[0]);
149 const char *predicate = PKT3_PREDICATE(ib[0]) ? "(predicate)" : "";
150 int i;
151
152 /* Print the name first. */
153 for (i = 0; i < ARRAY_SIZE(packet3_table); i++)
154 if (packet3_table[i].op == op)
155 break;
156
157 if (i < ARRAY_SIZE(packet3_table))
158 if (op == PKT3_SET_CONTEXT_REG ||
159 op == PKT3_SET_CONFIG_REG ||
160 op == PKT3_SET_UCONFIG_REG ||
161 op == PKT3_SET_SH_REG)
162 fprintf(f, COLOR_CYAN "%s%s" COLOR_CYAN ":\n",
163 packet3_table[i].name, predicate);
164 else
165 fprintf(f, COLOR_GREEN "%s%s" COLOR_RESET ":\n",
166 packet3_table[i].name, predicate);
167 else
168 fprintf(f, COLOR_RED "PKT3_UNKNOWN 0x%x%s" COLOR_RESET ":\n",
169 op, predicate);
170
171 /* Print the contents. */
172 switch (op) {
173 case PKT3_SET_CONTEXT_REG:
174 si_parse_set_reg_packet(f, ib, count, SI_CONTEXT_REG_OFFSET);
175 break;
176 case PKT3_SET_CONFIG_REG:
177 si_parse_set_reg_packet(f, ib, count, SI_CONFIG_REG_OFFSET);
178 break;
179 case PKT3_SET_UCONFIG_REG:
180 si_parse_set_reg_packet(f, ib, count, CIK_UCONFIG_REG_OFFSET);
181 break;
182 case PKT3_SET_SH_REG:
183 si_parse_set_reg_packet(f, ib, count, SI_SH_REG_OFFSET);
184 break;
185 case PKT3_DRAW_PREAMBLE:
186 si_dump_reg(f, R_030908_VGT_PRIMITIVE_TYPE, ib[1], ~0);
187 si_dump_reg(f, R_028AA8_IA_MULTI_VGT_PARAM, ib[2], ~0);
188 si_dump_reg(f, R_028B58_VGT_LS_HS_CONFIG, ib[3], ~0);
189 break;
190 case PKT3_ACQUIRE_MEM:
191 si_dump_reg(f, R_0301F0_CP_COHER_CNTL, ib[1], ~0);
192 si_dump_reg(f, R_0301F4_CP_COHER_SIZE, ib[2], ~0);
193 si_dump_reg(f, R_030230_CP_COHER_SIZE_HI, ib[3], ~0);
194 si_dump_reg(f, R_0301F8_CP_COHER_BASE, ib[4], ~0);
195 si_dump_reg(f, R_0301E4_CP_COHER_BASE_HI, ib[5], ~0);
196 print_named_value(f, "POLL_INTERVAL", ib[6], 16);
197 break;
198 case PKT3_SURFACE_SYNC:
199 si_dump_reg(f, R_0085F0_CP_COHER_CNTL, ib[1], ~0);
200 si_dump_reg(f, R_0085F4_CP_COHER_SIZE, ib[2], ~0);
201 si_dump_reg(f, R_0085F8_CP_COHER_BASE, ib[3], ~0);
202 print_named_value(f, "POLL_INTERVAL", ib[4], 16);
203 break;
204 case PKT3_EVENT_WRITE:
205 si_dump_reg(f, R_028A90_VGT_EVENT_INITIATOR, ib[1],
206 S_028A90_EVENT_TYPE(~0));
207 print_named_value(f, "EVENT_INDEX", (ib[1] >> 8) & 0xf, 4);
208 print_named_value(f, "INV_L2", (ib[1] >> 20) & 0x1, 1);
209 if (count > 0) {
210 print_named_value(f, "ADDRESS_LO", ib[2], 32);
211 print_named_value(f, "ADDRESS_HI", ib[3], 16);
212 }
213 break;
214 case PKT3_DRAW_INDEX_AUTO:
215 si_dump_reg(f, R_030930_VGT_NUM_INDICES, ib[1], ~0);
216 si_dump_reg(f, R_0287F0_VGT_DRAW_INITIATOR, ib[2], ~0);
217 break;
218 case PKT3_DRAW_INDEX_2:
219 si_dump_reg(f, R_028A78_VGT_DMA_MAX_SIZE, ib[1], ~0);
220 si_dump_reg(f, R_0287E8_VGT_DMA_BASE, ib[2], ~0);
221 si_dump_reg(f, R_0287E4_VGT_DMA_BASE_HI, ib[3], ~0);
222 si_dump_reg(f, R_030930_VGT_NUM_INDICES, ib[4], ~0);
223 si_dump_reg(f, R_0287F0_VGT_DRAW_INITIATOR, ib[5], ~0);
224 break;
225 case PKT3_INDEX_TYPE:
226 si_dump_reg(f, R_028A7C_VGT_DMA_INDEX_TYPE, ib[1], ~0);
227 break;
228 case PKT3_NUM_INSTANCES:
229 si_dump_reg(f, R_030934_VGT_NUM_INSTANCES, ib[1], ~0);
230 break;
231 case PKT3_NOP:
232 if (ib[0] == 0xffff1000) {
233 count = -1; /* One dword NOP. */
234 break;
235 }
236 /* fall through, print all dwords */
237 default:
238 for (i = 0; i < count+1; i++) {
239 print_spaces(f, INDENT_PKT);
240 fprintf(f, "0x%08x\n", ib[1+i]);
241 }
242 }
243
244 ib += count + 2;
245 *num_dw -= count + 2;
246 return ib;
247 }
248
249 static void si_parse_ib(FILE *f, uint32_t *ib, int num_dw)
250 {
251 fprintf(f, "------------------ IB begin ------------------\n");
252
253 while (num_dw > 0) {
254 unsigned type = PKT_TYPE_G(ib[0]);
255
256 switch (type) {
257 case 3:
258 ib = si_parse_packet3(f, ib, &num_dw);
259 break;
260 case 2:
261 /* type-2 nop */
262 if (ib[0] == 0x80000000) {
263 fprintf(f, COLOR_GREEN "NOP (type 2)" COLOR_RESET "\n");
264 ib++;
265 break;
266 }
267 /* fall through */
268 default:
269 fprintf(f, "Unknown packet type %i\n", type);
270 return;
271 }
272 }
273
274 fprintf(f, "------------------- IB end -------------------\n");
275 if (num_dw < 0) {
276 printf("Packet ends after the end of IB.\n");
277 exit(0);
278 }
279 }
280
281 static void si_dump_mmapped_reg(struct si_context *sctx, FILE *f,
282 unsigned offset)
283 {
284 struct radeon_winsys *ws = sctx->b.ws;
285 uint32_t value;
286
287 ws->read_registers(ws, offset, 1, &value);
288 si_dump_reg(f, offset, value, ~0);
289 }
290
291 static void si_dump_debug_registers(struct si_context *sctx, FILE *f)
292 {
293 if (sctx->screen->b.info.drm_major == 2 &&
294 sctx->screen->b.info.drm_minor < 42)
295 return; /* no radeon support */
296
297 fprintf(f, "Memory-mapped registers:\n");
298 si_dump_mmapped_reg(sctx, f, R_008010_GRBM_STATUS);
299
300 /* No other registers can be read on DRM < 3.1.0. */
301 if (sctx->screen->b.info.drm_major < 3 ||
302 sctx->screen->b.info.drm_minor < 1) {
303 fprintf(f, "\n");
304 return;
305 }
306
307 si_dump_mmapped_reg(sctx, f, R_008008_GRBM_STATUS2);
308 si_dump_mmapped_reg(sctx, f, R_008014_GRBM_STATUS_SE0);
309 si_dump_mmapped_reg(sctx, f, R_008018_GRBM_STATUS_SE1);
310 si_dump_mmapped_reg(sctx, f, R_008038_GRBM_STATUS_SE2);
311 si_dump_mmapped_reg(sctx, f, R_00803C_GRBM_STATUS_SE3);
312 si_dump_mmapped_reg(sctx, f, R_00D034_SDMA0_STATUS_REG);
313 si_dump_mmapped_reg(sctx, f, R_00D834_SDMA1_STATUS_REG);
314 si_dump_mmapped_reg(sctx, f, R_000E50_SRBM_STATUS);
315 si_dump_mmapped_reg(sctx, f, R_000E4C_SRBM_STATUS2);
316 si_dump_mmapped_reg(sctx, f, R_000E54_SRBM_STATUS3);
317 si_dump_mmapped_reg(sctx, f, R_008680_CP_STAT);
318 si_dump_mmapped_reg(sctx, f, R_008674_CP_STALLED_STAT1);
319 si_dump_mmapped_reg(sctx, f, R_008678_CP_STALLED_STAT2);
320 si_dump_mmapped_reg(sctx, f, R_008670_CP_STALLED_STAT3);
321 si_dump_mmapped_reg(sctx, f, R_008210_CP_CPC_STATUS);
322 si_dump_mmapped_reg(sctx, f, R_008214_CP_CPC_BUSY_STAT);
323 si_dump_mmapped_reg(sctx, f, R_008218_CP_CPC_STALLED_STAT1);
324 si_dump_mmapped_reg(sctx, f, R_00821C_CP_CPF_STATUS);
325 si_dump_mmapped_reg(sctx, f, R_008220_CP_CPF_BUSY_STAT);
326 si_dump_mmapped_reg(sctx, f, R_008224_CP_CPF_STALLED_STAT1);
327 fprintf(f, "\n");
328 }
329
330 static void si_dump_debug_state(struct pipe_context *ctx, FILE *f,
331 unsigned flags)
332 {
333 struct si_context *sctx = (struct si_context*)ctx;
334
335 if (flags & PIPE_DEBUG_DEVICE_IS_HUNG)
336 si_dump_debug_registers(sctx, f);
337
338 si_dump_shader(sctx->vs_shader, "Vertex", f);
339 si_dump_shader(sctx->tcs_shader, "Tessellation control", f);
340 si_dump_shader(sctx->tes_shader, "Tessellation evaluation", f);
341 si_dump_shader(sctx->gs_shader, "Geometry", f);
342 si_dump_shader(sctx->ps_shader, "Fragment", f);
343
344 if (sctx->last_ib) {
345 si_parse_ib(f, sctx->last_ib, sctx->last_ib_dw_size);
346 free(sctx->last_ib); /* dump only once */
347 sctx->last_ib = NULL;
348 }
349
350 fprintf(f, "Done.\n");
351 }
352
353 void si_init_debug_functions(struct si_context *sctx)
354 {
355 sctx->b.b.dump_debug_state = si_dump_debug_state;
356 }