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radeonsi: fix num banks selection on SI for dma setup (v2)
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "../radeon/r600_cs.h"
31
32 #include "tgsi/tgsi_parse.h"
33 #include "tgsi/tgsi_scan.h"
34 #include "util/u_format.h"
35 #include "util/u_format_s3tc.h"
36 #include "util/u_framebuffer.h"
37 #include "util/u_helpers.h"
38 #include "util/u_memory.h"
39
40 static void si_init_atom(struct r600_atom *atom, struct r600_atom **list_elem,
41 void (*emit)(struct si_context *ctx, struct r600_atom *state),
42 unsigned num_dw)
43 {
44 atom->emit = (void*)emit;
45 atom->num_dw = num_dw;
46 atom->dirty = false;
47 *list_elem = atom;
48 }
49
50 uint32_t cik_num_banks(struct si_screen *sscreen, unsigned bpe, unsigned tile_split)
51 {
52 unsigned index, tileb;
53
54 tileb = 8 * 8 * bpe;
55 tileb = MIN2(tile_split, tileb);
56
57 for (index = 0; tileb > 64; index++) {
58 tileb >>= 1;
59 }
60
61 if ((sscreen->b.chip_class == CIK) &&
62 sscreen->b.info.cik_macrotile_mode_array_valid) {
63 assert(index < 16);
64
65 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
66 }
67
68 if ((sscreen->b.chip_class == SI) &&
69 sscreen->b.info.si_tile_mode_array_valid) {
70 assert(index < 16);
71
72 return (sscreen->b.info.si_tile_mode_array[index] >> 20) & 0x3;
73 }
74
75 /* The old way. */
76 switch (sscreen->b.tiling_info.num_banks) {
77 case 2:
78 return V_02803C_ADDR_SURF_2_BANK;
79 case 4:
80 return V_02803C_ADDR_SURF_4_BANK;
81 case 8:
82 default:
83 return V_02803C_ADDR_SURF_8_BANK;
84 case 16:
85 return V_02803C_ADDR_SURF_16_BANK;
86 }
87 }
88
89 unsigned cik_tile_split(unsigned tile_split)
90 {
91 switch (tile_split) {
92 case 64:
93 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
94 break;
95 case 128:
96 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
97 break;
98 case 256:
99 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
100 break;
101 case 512:
102 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
103 break;
104 default:
105 case 1024:
106 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
107 break;
108 case 2048:
109 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
110 break;
111 case 4096:
112 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
113 break;
114 }
115 return tile_split;
116 }
117
118 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
119 {
120 switch (macro_tile_aspect) {
121 default:
122 case 1:
123 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
124 break;
125 case 2:
126 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
127 break;
128 case 4:
129 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
130 break;
131 case 8:
132 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
133 break;
134 }
135 return macro_tile_aspect;
136 }
137
138 unsigned cik_bank_wh(unsigned bankwh)
139 {
140 switch (bankwh) {
141 default:
142 case 1:
143 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
144 break;
145 case 2:
146 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
147 break;
148 case 4:
149 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
150 break;
151 case 8:
152 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
153 break;
154 }
155 return bankwh;
156 }
157
158 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
159 {
160 if (sscreen->b.info.si_tile_mode_array_valid) {
161 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
162
163 return G_009910_PIPE_CONFIG(gb_tile_mode);
164 }
165
166 /* This is probably broken for a lot of chips, but it's only used
167 * if the kernel cannot return the tile mode array for CIK. */
168 switch (sscreen->b.info.r600_num_tile_pipes) {
169 case 16:
170 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
171 case 8:
172 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
173 case 4:
174 default:
175 if (sscreen->b.info.r600_num_backends == 4)
176 return V_02803C_X_ADDR_SURF_P4_16X16;
177 else
178 return V_02803C_X_ADDR_SURF_P4_8X16;
179 case 2:
180 return V_02803C_ADDR_SURF_P2;
181 }
182 }
183
184 static unsigned si_map_swizzle(unsigned swizzle)
185 {
186 switch (swizzle) {
187 case UTIL_FORMAT_SWIZZLE_Y:
188 return V_008F0C_SQ_SEL_Y;
189 case UTIL_FORMAT_SWIZZLE_Z:
190 return V_008F0C_SQ_SEL_Z;
191 case UTIL_FORMAT_SWIZZLE_W:
192 return V_008F0C_SQ_SEL_W;
193 case UTIL_FORMAT_SWIZZLE_0:
194 return V_008F0C_SQ_SEL_0;
195 case UTIL_FORMAT_SWIZZLE_1:
196 return V_008F0C_SQ_SEL_1;
197 default: /* UTIL_FORMAT_SWIZZLE_X */
198 return V_008F0C_SQ_SEL_X;
199 }
200 }
201
202 static uint32_t S_FIXED(float value, uint32_t frac_bits)
203 {
204 return value * (1 << frac_bits);
205 }
206
207 /* 12.4 fixed-point */
208 static unsigned si_pack_float_12p4(float x)
209 {
210 return x <= 0 ? 0 :
211 x >= 4096 ? 0xffff : x * 16;
212 }
213
214 /*
215 * inferred framebuffer and blender state
216 */
217 static void si_update_fb_blend_state(struct si_context *sctx)
218 {
219 struct si_pm4_state *pm4;
220 struct si_state_blend *blend = sctx->queued.named.blend;
221 uint32_t mask;
222
223 if (blend == NULL)
224 return;
225
226 pm4 = si_pm4_alloc_state(sctx);
227 if (pm4 == NULL)
228 return;
229
230 mask = (1ULL << ((unsigned)sctx->framebuffer.state.nr_cbufs * 4)) - 1;
231 mask &= blend->cb_target_mask;
232 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
233
234 si_pm4_set_state(sctx, fb_blend, pm4);
235 }
236
237 /*
238 * Blender functions
239 */
240
241 static uint32_t si_translate_blend_function(int blend_func)
242 {
243 switch (blend_func) {
244 case PIPE_BLEND_ADD:
245 return V_028780_COMB_DST_PLUS_SRC;
246 case PIPE_BLEND_SUBTRACT:
247 return V_028780_COMB_SRC_MINUS_DST;
248 case PIPE_BLEND_REVERSE_SUBTRACT:
249 return V_028780_COMB_DST_MINUS_SRC;
250 case PIPE_BLEND_MIN:
251 return V_028780_COMB_MIN_DST_SRC;
252 case PIPE_BLEND_MAX:
253 return V_028780_COMB_MAX_DST_SRC;
254 default:
255 R600_ERR("Unknown blend function %d\n", blend_func);
256 assert(0);
257 break;
258 }
259 return 0;
260 }
261
262 static uint32_t si_translate_blend_factor(int blend_fact)
263 {
264 switch (blend_fact) {
265 case PIPE_BLENDFACTOR_ONE:
266 return V_028780_BLEND_ONE;
267 case PIPE_BLENDFACTOR_SRC_COLOR:
268 return V_028780_BLEND_SRC_COLOR;
269 case PIPE_BLENDFACTOR_SRC_ALPHA:
270 return V_028780_BLEND_SRC_ALPHA;
271 case PIPE_BLENDFACTOR_DST_ALPHA:
272 return V_028780_BLEND_DST_ALPHA;
273 case PIPE_BLENDFACTOR_DST_COLOR:
274 return V_028780_BLEND_DST_COLOR;
275 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
276 return V_028780_BLEND_SRC_ALPHA_SATURATE;
277 case PIPE_BLENDFACTOR_CONST_COLOR:
278 return V_028780_BLEND_CONSTANT_COLOR;
279 case PIPE_BLENDFACTOR_CONST_ALPHA:
280 return V_028780_BLEND_CONSTANT_ALPHA;
281 case PIPE_BLENDFACTOR_ZERO:
282 return V_028780_BLEND_ZERO;
283 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
284 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
285 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
286 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
287 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
288 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
289 case PIPE_BLENDFACTOR_INV_DST_COLOR:
290 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
291 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
292 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
293 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
294 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
295 case PIPE_BLENDFACTOR_SRC1_COLOR:
296 return V_028780_BLEND_SRC1_COLOR;
297 case PIPE_BLENDFACTOR_SRC1_ALPHA:
298 return V_028780_BLEND_SRC1_ALPHA;
299 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
300 return V_028780_BLEND_INV_SRC1_COLOR;
301 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
302 return V_028780_BLEND_INV_SRC1_ALPHA;
303 default:
304 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
305 assert(0);
306 break;
307 }
308 return 0;
309 }
310
311 static void *si_create_blend_state_mode(struct pipe_context *ctx,
312 const struct pipe_blend_state *state,
313 unsigned mode)
314 {
315 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
316 struct si_pm4_state *pm4 = &blend->pm4;
317
318 uint32_t color_control = 0;
319
320 if (blend == NULL)
321 return NULL;
322
323 blend->alpha_to_one = state->alpha_to_one;
324
325 if (state->logicop_enable) {
326 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
327 } else {
328 color_control |= S_028808_ROP3(0xcc);
329 }
330
331 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
332 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
333 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
334 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
335 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
336 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
337
338 blend->cb_target_mask = 0;
339 for (int i = 0; i < 8; i++) {
340 /* state->rt entries > 0 only written if independent blending */
341 const int j = state->independent_blend_enable ? i : 0;
342
343 unsigned eqRGB = state->rt[j].rgb_func;
344 unsigned srcRGB = state->rt[j].rgb_src_factor;
345 unsigned dstRGB = state->rt[j].rgb_dst_factor;
346 unsigned eqA = state->rt[j].alpha_func;
347 unsigned srcA = state->rt[j].alpha_src_factor;
348 unsigned dstA = state->rt[j].alpha_dst_factor;
349
350 unsigned blend_cntl = 0;
351
352 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
353 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
354
355 if (!state->rt[j].blend_enable) {
356 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
357 continue;
358 }
359
360 blend_cntl |= S_028780_ENABLE(1);
361 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
362 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
363 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
364
365 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
366 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
367 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
368 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
369 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
370 }
371 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
372 }
373
374 if (blend->cb_target_mask) {
375 color_control |= S_028808_MODE(mode);
376 } else {
377 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
378 }
379 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
380
381 return blend;
382 }
383
384 static void *si_create_blend_state(struct pipe_context *ctx,
385 const struct pipe_blend_state *state)
386 {
387 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
388 }
389
390 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
391 {
392 struct si_context *sctx = (struct si_context *)ctx;
393 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
394 si_update_fb_blend_state(sctx);
395 }
396
397 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
398 {
399 struct si_context *sctx = (struct si_context *)ctx;
400 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
401 }
402
403 static void si_set_blend_color(struct pipe_context *ctx,
404 const struct pipe_blend_color *state)
405 {
406 struct si_context *sctx = (struct si_context *)ctx;
407 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
408
409 if (pm4 == NULL)
410 return;
411
412 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
413 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
414 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
415 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
416
417 si_pm4_set_state(sctx, blend_color, pm4);
418 }
419
420 /*
421 * Clipping, scissors and viewport
422 */
423
424 static void si_set_clip_state(struct pipe_context *ctx,
425 const struct pipe_clip_state *state)
426 {
427 struct si_context *sctx = (struct si_context *)ctx;
428 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
429 struct pipe_constant_buffer cb;
430
431 if (pm4 == NULL)
432 return;
433
434 for (int i = 0; i < 6; i++) {
435 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
436 fui(state->ucp[i][0]));
437 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
438 fui(state->ucp[i][1]));
439 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
440 fui(state->ucp[i][2]));
441 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
442 fui(state->ucp[i][3]));
443 }
444
445 cb.buffer = NULL;
446 cb.user_buffer = state->ucp;
447 cb.buffer_offset = 0;
448 cb.buffer_size = 4*4*8;
449 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, NUM_PIPE_CONST_BUFFERS, &cb);
450 pipe_resource_reference(&cb.buffer, NULL);
451
452 si_pm4_set_state(sctx, clip, pm4);
453 }
454
455 static void si_set_scissor_states(struct pipe_context *ctx,
456 unsigned start_slot,
457 unsigned num_scissors,
458 const struct pipe_scissor_state *state)
459 {
460 struct si_context *sctx = (struct si_context *)ctx;
461 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
462
463 if (pm4 == NULL)
464 return;
465
466 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL,
467 S_028250_TL_X(state->minx) | S_028250_TL_Y(state->miny) |
468 S_028250_WINDOW_OFFSET_DISABLE(1));
469 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR,
470 S_028254_BR_X(state->maxx) | S_028254_BR_Y(state->maxy));
471
472 si_pm4_set_state(sctx, scissor, pm4);
473 }
474
475 static void si_set_viewport_states(struct pipe_context *ctx,
476 unsigned start_slot,
477 unsigned num_viewports,
478 const struct pipe_viewport_state *state)
479 {
480 struct si_context *sctx = (struct si_context *)ctx;
481 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
482 struct si_pm4_state *pm4 = &viewport->pm4;
483
484 if (viewport == NULL)
485 return;
486
487 viewport->viewport = *state;
488 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
489 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
490 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
491 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
492 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
493 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
494
495 si_pm4_set_state(sctx, viewport, viewport);
496 }
497
498 /*
499 * inferred state between framebuffer and rasterizer
500 */
501 static void si_update_fb_rs_state(struct si_context *sctx)
502 {
503 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
504 struct si_pm4_state *pm4;
505 float offset_units;
506
507 if (!rs || !sctx->framebuffer.state.zsbuf)
508 return;
509
510 offset_units = sctx->queued.named.rasterizer->offset_units;
511 switch (sctx->framebuffer.state.zsbuf->texture->format) {
512 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
513 case PIPE_FORMAT_X8Z24_UNORM:
514 case PIPE_FORMAT_Z24X8_UNORM:
515 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
516 offset_units *= 2.0f;
517 break;
518 case PIPE_FORMAT_Z32_FLOAT:
519 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
520 offset_units *= 1.0f;
521 break;
522 case PIPE_FORMAT_Z16_UNORM:
523 offset_units *= 4.0f;
524 break;
525 default:
526 return;
527 }
528
529 pm4 = si_pm4_alloc_state(sctx);
530
531 if (pm4 == NULL)
532 return;
533
534 /* FIXME some of those reg can be computed with cso */
535 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
536 fui(sctx->queued.named.rasterizer->offset_scale));
537 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
538 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
539 fui(sctx->queued.named.rasterizer->offset_scale));
540 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
541
542 si_pm4_set_state(sctx, fb_rs, pm4);
543 }
544
545 /*
546 * Rasterizer
547 */
548
549 static uint32_t si_translate_fill(uint32_t func)
550 {
551 switch(func) {
552 case PIPE_POLYGON_MODE_FILL:
553 return V_028814_X_DRAW_TRIANGLES;
554 case PIPE_POLYGON_MODE_LINE:
555 return V_028814_X_DRAW_LINES;
556 case PIPE_POLYGON_MODE_POINT:
557 return V_028814_X_DRAW_POINTS;
558 default:
559 assert(0);
560 return V_028814_X_DRAW_POINTS;
561 }
562 }
563
564 static void *si_create_rs_state(struct pipe_context *ctx,
565 const struct pipe_rasterizer_state *state)
566 {
567 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
568 struct si_pm4_state *pm4 = &rs->pm4;
569 unsigned tmp;
570 unsigned prov_vtx = 1, polygon_dual_mode;
571 float psize_min, psize_max;
572
573 if (rs == NULL) {
574 return NULL;
575 }
576
577 rs->two_side = state->light_twoside;
578 rs->multisample_enable = state->multisample;
579 rs->clip_plane_enable = state->clip_plane_enable;
580 rs->line_stipple_enable = state->line_stipple_enable;
581
582 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
583 state->fill_back != PIPE_POLYGON_MODE_FILL);
584
585 if (state->flatshade_first)
586 prov_vtx = 0;
587
588 rs->flatshade = state->flatshade;
589 rs->sprite_coord_enable = state->sprite_coord_enable;
590 rs->pa_sc_line_stipple = state->line_stipple_enable ?
591 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
592 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
593 rs->pa_su_sc_mode_cntl =
594 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
595 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
596 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
597 S_028814_FACE(!state->front_ccw) |
598 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
599 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
600 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
601 S_028814_POLY_MODE(polygon_dual_mode) |
602 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
603 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
604 rs->pa_cl_clip_cntl =
605 S_028810_PS_UCP_MODE(3) |
606 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
607 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
608 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
609 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
610
611 /* offset */
612 rs->offset_units = state->offset_units;
613 rs->offset_scale = state->offset_scale * 12.0f;
614
615 tmp = S_0286D4_FLAT_SHADE_ENA(1);
616 if (state->sprite_coord_enable) {
617 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
618 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
619 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
620 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
621 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
622 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
623 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
624 }
625 }
626 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
627
628 /* point size 12.4 fixed point */
629 tmp = (unsigned)(state->point_size * 8.0);
630 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
631
632 if (state->point_size_per_vertex) {
633 psize_min = util_get_min_point_size(state);
634 psize_max = 8192;
635 } else {
636 /* Force the point size to be as if the vertex output was disabled. */
637 psize_min = state->point_size;
638 psize_max = state->point_size;
639 }
640 /* Divide by two, because 0.5 = 1 pixel. */
641 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
642 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
643 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
644
645 tmp = (unsigned)state->line_width * 8;
646 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
647 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
648 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
649 S_028A48_MSAA_ENABLE(state->multisample) |
650 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor));
651
652 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
653 S_028BE4_PIX_CENTER(state->half_pixel_center) |
654 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
655
656 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
657
658 return rs;
659 }
660
661 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
662 {
663 struct si_context *sctx = (struct si_context *)ctx;
664 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
665
666 if (state == NULL)
667 return;
668
669 // TODO
670 sctx->sprite_coord_enable = rs->sprite_coord_enable;
671 sctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
672 sctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
673
674 si_pm4_bind_state(sctx, rasterizer, rs);
675 si_update_fb_rs_state(sctx);
676 }
677
678 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
679 {
680 struct si_context *sctx = (struct si_context *)ctx;
681 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
682 }
683
684 /*
685 * infeered state between dsa and stencil ref
686 */
687 static void si_update_dsa_stencil_ref(struct si_context *sctx)
688 {
689 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
690 struct pipe_stencil_ref *ref = &sctx->stencil_ref;
691 struct si_state_dsa *dsa = sctx->queued.named.dsa;
692
693 if (pm4 == NULL)
694 return;
695
696 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
697 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
698 S_028430_STENCILMASK(dsa->valuemask[0]) |
699 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
700 S_028430_STENCILOPVAL(1));
701 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
702 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
703 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
704 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
705 S_028434_STENCILOPVAL_BF(1));
706
707 si_pm4_set_state(sctx, dsa_stencil_ref, pm4);
708 }
709
710 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
711 const struct pipe_stencil_ref *state)
712 {
713 struct si_context *sctx = (struct si_context *)ctx;
714 sctx->stencil_ref = *state;
715 si_update_dsa_stencil_ref(sctx);
716 }
717
718
719 /*
720 * DSA
721 */
722
723 static uint32_t si_translate_stencil_op(int s_op)
724 {
725 switch (s_op) {
726 case PIPE_STENCIL_OP_KEEP:
727 return V_02842C_STENCIL_KEEP;
728 case PIPE_STENCIL_OP_ZERO:
729 return V_02842C_STENCIL_ZERO;
730 case PIPE_STENCIL_OP_REPLACE:
731 return V_02842C_STENCIL_REPLACE_TEST;
732 case PIPE_STENCIL_OP_INCR:
733 return V_02842C_STENCIL_ADD_CLAMP;
734 case PIPE_STENCIL_OP_DECR:
735 return V_02842C_STENCIL_SUB_CLAMP;
736 case PIPE_STENCIL_OP_INCR_WRAP:
737 return V_02842C_STENCIL_ADD_WRAP;
738 case PIPE_STENCIL_OP_DECR_WRAP:
739 return V_02842C_STENCIL_SUB_WRAP;
740 case PIPE_STENCIL_OP_INVERT:
741 return V_02842C_STENCIL_INVERT;
742 default:
743 R600_ERR("Unknown stencil op %d", s_op);
744 assert(0);
745 break;
746 }
747 return 0;
748 }
749
750 static void *si_create_dsa_state(struct pipe_context *ctx,
751 const struct pipe_depth_stencil_alpha_state *state)
752 {
753 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
754 struct si_pm4_state *pm4 = &dsa->pm4;
755 unsigned db_depth_control;
756 unsigned db_render_control;
757 uint32_t db_stencil_control = 0;
758
759 if (dsa == NULL) {
760 return NULL;
761 }
762
763 dsa->valuemask[0] = state->stencil[0].valuemask;
764 dsa->valuemask[1] = state->stencil[1].valuemask;
765 dsa->writemask[0] = state->stencil[0].writemask;
766 dsa->writemask[1] = state->stencil[1].writemask;
767
768 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
769 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
770 S_028800_ZFUNC(state->depth.func);
771
772 /* stencil */
773 if (state->stencil[0].enabled) {
774 db_depth_control |= S_028800_STENCIL_ENABLE(1);
775 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
776 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
777 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
778 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
779
780 if (state->stencil[1].enabled) {
781 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
782 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
783 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
784 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
785 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
786 }
787 }
788
789 /* alpha */
790 if (state->alpha.enabled) {
791 dsa->alpha_func = state->alpha.func;
792 dsa->alpha_ref = state->alpha.ref_value;
793
794 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
795 SI_SGPR_ALPHA_REF * 4, fui(dsa->alpha_ref));
796 } else {
797 dsa->alpha_func = PIPE_FUNC_ALWAYS;
798 }
799
800 /* misc */
801 db_render_control = 0;
802 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
803 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
804 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
805
806 return dsa;
807 }
808
809 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
810 {
811 struct si_context *sctx = (struct si_context *)ctx;
812 struct si_state_dsa *dsa = state;
813
814 if (state == NULL)
815 return;
816
817 si_pm4_bind_state(sctx, dsa, dsa);
818 si_update_dsa_stencil_ref(sctx);
819 }
820
821 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
822 {
823 struct si_context *sctx = (struct si_context *)ctx;
824 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
825 }
826
827 static void *si_create_db_flush_dsa(struct si_context *sctx, bool copy_depth,
828 bool copy_stencil, int sample)
829 {
830 struct pipe_depth_stencil_alpha_state dsa;
831 struct si_state_dsa *state;
832
833 memset(&dsa, 0, sizeof(dsa));
834
835 state = sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
836 if (copy_depth || copy_stencil) {
837 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
838 S_028000_DEPTH_COPY(copy_depth) |
839 S_028000_STENCIL_COPY(copy_stencil) |
840 S_028000_COPY_CENTROID(1) |
841 S_028000_COPY_SAMPLE(sample));
842 } else {
843 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
844 S_028000_DEPTH_COMPRESS_DISABLE(1) |
845 S_028000_STENCIL_COMPRESS_DISABLE(1));
846 }
847
848 return state;
849 }
850
851 /*
852 * format translation
853 */
854 static uint32_t si_translate_colorformat(enum pipe_format format)
855 {
856 const struct util_format_description *desc = util_format_description(format);
857
858 #define HAS_SIZE(x,y,z,w) \
859 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
860 desc->channel[2].size == (z) && desc->channel[3].size == (w))
861
862 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
863 return V_028C70_COLOR_10_11_11;
864
865 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
866 return V_028C70_COLOR_INVALID;
867
868 switch (desc->nr_channels) {
869 case 1:
870 switch (desc->channel[0].size) {
871 case 8:
872 return V_028C70_COLOR_8;
873 case 16:
874 return V_028C70_COLOR_16;
875 case 32:
876 return V_028C70_COLOR_32;
877 }
878 break;
879 case 2:
880 if (desc->channel[0].size == desc->channel[1].size) {
881 switch (desc->channel[0].size) {
882 case 8:
883 return V_028C70_COLOR_8_8;
884 case 16:
885 return V_028C70_COLOR_16_16;
886 case 32:
887 return V_028C70_COLOR_32_32;
888 }
889 } else if (HAS_SIZE(8,24,0,0)) {
890 return V_028C70_COLOR_24_8;
891 } else if (HAS_SIZE(24,8,0,0)) {
892 return V_028C70_COLOR_8_24;
893 }
894 break;
895 case 3:
896 if (HAS_SIZE(5,6,5,0)) {
897 return V_028C70_COLOR_5_6_5;
898 } else if (HAS_SIZE(32,8,24,0)) {
899 return V_028C70_COLOR_X24_8_32_FLOAT;
900 }
901 break;
902 case 4:
903 if (desc->channel[0].size == desc->channel[1].size &&
904 desc->channel[0].size == desc->channel[2].size &&
905 desc->channel[0].size == desc->channel[3].size) {
906 switch (desc->channel[0].size) {
907 case 4:
908 return V_028C70_COLOR_4_4_4_4;
909 case 8:
910 return V_028C70_COLOR_8_8_8_8;
911 case 16:
912 return V_028C70_COLOR_16_16_16_16;
913 case 32:
914 return V_028C70_COLOR_32_32_32_32;
915 }
916 } else if (HAS_SIZE(5,5,5,1)) {
917 return V_028C70_COLOR_1_5_5_5;
918 } else if (HAS_SIZE(10,10,10,2)) {
919 return V_028C70_COLOR_2_10_10_10;
920 }
921 break;
922 }
923 return V_028C70_COLOR_INVALID;
924 }
925
926 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
927 {
928 if (SI_BIG_ENDIAN) {
929 switch(colorformat) {
930 /* 8-bit buffers. */
931 case V_028C70_COLOR_8:
932 return V_028C70_ENDIAN_NONE;
933
934 /* 16-bit buffers. */
935 case V_028C70_COLOR_5_6_5:
936 case V_028C70_COLOR_1_5_5_5:
937 case V_028C70_COLOR_4_4_4_4:
938 case V_028C70_COLOR_16:
939 case V_028C70_COLOR_8_8:
940 return V_028C70_ENDIAN_8IN16;
941
942 /* 32-bit buffers. */
943 case V_028C70_COLOR_8_8_8_8:
944 case V_028C70_COLOR_2_10_10_10:
945 case V_028C70_COLOR_8_24:
946 case V_028C70_COLOR_24_8:
947 case V_028C70_COLOR_16_16:
948 return V_028C70_ENDIAN_8IN32;
949
950 /* 64-bit buffers. */
951 case V_028C70_COLOR_16_16_16_16:
952 return V_028C70_ENDIAN_8IN16;
953
954 case V_028C70_COLOR_32_32:
955 return V_028C70_ENDIAN_8IN32;
956
957 /* 128-bit buffers. */
958 case V_028C70_COLOR_32_32_32_32:
959 return V_028C70_ENDIAN_8IN32;
960 default:
961 return V_028C70_ENDIAN_NONE; /* Unsupported. */
962 }
963 } else {
964 return V_028C70_ENDIAN_NONE;
965 }
966 }
967
968 /* Returns the size in bits of the widest component of a CB format */
969 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
970 {
971 switch(colorformat) {
972 case V_028C70_COLOR_4_4_4_4:
973 return 4;
974
975 case V_028C70_COLOR_1_5_5_5:
976 case V_028C70_COLOR_5_5_5_1:
977 return 5;
978
979 case V_028C70_COLOR_5_6_5:
980 return 6;
981
982 case V_028C70_COLOR_8:
983 case V_028C70_COLOR_8_8:
984 case V_028C70_COLOR_8_8_8_8:
985 return 8;
986
987 case V_028C70_COLOR_10_10_10_2:
988 case V_028C70_COLOR_2_10_10_10:
989 return 10;
990
991 case V_028C70_COLOR_10_11_11:
992 case V_028C70_COLOR_11_11_10:
993 return 11;
994
995 case V_028C70_COLOR_16:
996 case V_028C70_COLOR_16_16:
997 case V_028C70_COLOR_16_16_16_16:
998 return 16;
999
1000 case V_028C70_COLOR_8_24:
1001 case V_028C70_COLOR_24_8:
1002 return 24;
1003
1004 case V_028C70_COLOR_32:
1005 case V_028C70_COLOR_32_32:
1006 case V_028C70_COLOR_32_32_32_32:
1007 case V_028C70_COLOR_X24_8_32_FLOAT:
1008 return 32;
1009 }
1010
1011 assert(!"Unknown maximum component size");
1012 return 0;
1013 }
1014
1015 static uint32_t si_translate_dbformat(enum pipe_format format)
1016 {
1017 switch (format) {
1018 case PIPE_FORMAT_Z16_UNORM:
1019 return V_028040_Z_16;
1020 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1021 case PIPE_FORMAT_X8Z24_UNORM:
1022 case PIPE_FORMAT_Z24X8_UNORM:
1023 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1024 return V_028040_Z_24; /* deprecated on SI */
1025 case PIPE_FORMAT_Z32_FLOAT:
1026 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1027 return V_028040_Z_32_FLOAT;
1028 default:
1029 return V_028040_Z_INVALID;
1030 }
1031 }
1032
1033 /*
1034 * Texture translation
1035 */
1036
1037 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1038 enum pipe_format format,
1039 const struct util_format_description *desc,
1040 int first_non_void)
1041 {
1042 struct si_screen *sscreen = (struct si_screen*)screen;
1043 bool enable_s3tc = sscreen->b.info.drm_minor >= 31;
1044 boolean uniform = TRUE;
1045 int i;
1046
1047 /* Colorspace (return non-RGB formats directly). */
1048 switch (desc->colorspace) {
1049 /* Depth stencil formats */
1050 case UTIL_FORMAT_COLORSPACE_ZS:
1051 switch (format) {
1052 case PIPE_FORMAT_Z16_UNORM:
1053 return V_008F14_IMG_DATA_FORMAT_16;
1054 case PIPE_FORMAT_X24S8_UINT:
1055 case PIPE_FORMAT_Z24X8_UNORM:
1056 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1057 return V_008F14_IMG_DATA_FORMAT_8_24;
1058 case PIPE_FORMAT_X8Z24_UNORM:
1059 case PIPE_FORMAT_S8X24_UINT:
1060 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1061 return V_008F14_IMG_DATA_FORMAT_24_8;
1062 case PIPE_FORMAT_S8_UINT:
1063 return V_008F14_IMG_DATA_FORMAT_8;
1064 case PIPE_FORMAT_Z32_FLOAT:
1065 return V_008F14_IMG_DATA_FORMAT_32;
1066 case PIPE_FORMAT_X32_S8X24_UINT:
1067 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1068 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1069 default:
1070 goto out_unknown;
1071 }
1072
1073 case UTIL_FORMAT_COLORSPACE_YUV:
1074 goto out_unknown; /* TODO */
1075
1076 case UTIL_FORMAT_COLORSPACE_SRGB:
1077 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1078 goto out_unknown;
1079 break;
1080
1081 default:
1082 break;
1083 }
1084
1085 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1086 if (!enable_s3tc)
1087 goto out_unknown;
1088
1089 switch (format) {
1090 case PIPE_FORMAT_RGTC1_SNORM:
1091 case PIPE_FORMAT_LATC1_SNORM:
1092 case PIPE_FORMAT_RGTC1_UNORM:
1093 case PIPE_FORMAT_LATC1_UNORM:
1094 return V_008F14_IMG_DATA_FORMAT_BC4;
1095 case PIPE_FORMAT_RGTC2_SNORM:
1096 case PIPE_FORMAT_LATC2_SNORM:
1097 case PIPE_FORMAT_RGTC2_UNORM:
1098 case PIPE_FORMAT_LATC2_UNORM:
1099 return V_008F14_IMG_DATA_FORMAT_BC5;
1100 default:
1101 goto out_unknown;
1102 }
1103 }
1104
1105 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1106
1107 if (!enable_s3tc)
1108 goto out_unknown;
1109
1110 if (!util_format_s3tc_enabled) {
1111 goto out_unknown;
1112 }
1113
1114 switch (format) {
1115 case PIPE_FORMAT_DXT1_RGB:
1116 case PIPE_FORMAT_DXT1_RGBA:
1117 case PIPE_FORMAT_DXT1_SRGB:
1118 case PIPE_FORMAT_DXT1_SRGBA:
1119 return V_008F14_IMG_DATA_FORMAT_BC1;
1120 case PIPE_FORMAT_DXT3_RGBA:
1121 case PIPE_FORMAT_DXT3_SRGBA:
1122 return V_008F14_IMG_DATA_FORMAT_BC2;
1123 case PIPE_FORMAT_DXT5_RGBA:
1124 case PIPE_FORMAT_DXT5_SRGBA:
1125 return V_008F14_IMG_DATA_FORMAT_BC3;
1126 default:
1127 goto out_unknown;
1128 }
1129 }
1130
1131 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1132 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1133 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1134 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1135 }
1136
1137 /* R8G8Bx_SNORM - TODO CxV8U8 */
1138
1139 /* See whether the components are of the same size. */
1140 for (i = 1; i < desc->nr_channels; i++) {
1141 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1142 }
1143
1144 /* Non-uniform formats. */
1145 if (!uniform) {
1146 switch(desc->nr_channels) {
1147 case 3:
1148 if (desc->channel[0].size == 5 &&
1149 desc->channel[1].size == 6 &&
1150 desc->channel[2].size == 5) {
1151 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1152 }
1153 goto out_unknown;
1154 case 4:
1155 if (desc->channel[0].size == 5 &&
1156 desc->channel[1].size == 5 &&
1157 desc->channel[2].size == 5 &&
1158 desc->channel[3].size == 1) {
1159 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1160 }
1161 if (desc->channel[0].size == 10 &&
1162 desc->channel[1].size == 10 &&
1163 desc->channel[2].size == 10 &&
1164 desc->channel[3].size == 2) {
1165 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1166 }
1167 goto out_unknown;
1168 }
1169 goto out_unknown;
1170 }
1171
1172 if (first_non_void < 0 || first_non_void > 3)
1173 goto out_unknown;
1174
1175 /* uniform formats */
1176 switch (desc->channel[first_non_void].size) {
1177 case 4:
1178 switch (desc->nr_channels) {
1179 #if 0 /* Not supported for render targets */
1180 case 2:
1181 return V_008F14_IMG_DATA_FORMAT_4_4;
1182 #endif
1183 case 4:
1184 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1185 }
1186 break;
1187 case 8:
1188 switch (desc->nr_channels) {
1189 case 1:
1190 return V_008F14_IMG_DATA_FORMAT_8;
1191 case 2:
1192 return V_008F14_IMG_DATA_FORMAT_8_8;
1193 case 4:
1194 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1195 }
1196 break;
1197 case 16:
1198 switch (desc->nr_channels) {
1199 case 1:
1200 return V_008F14_IMG_DATA_FORMAT_16;
1201 case 2:
1202 return V_008F14_IMG_DATA_FORMAT_16_16;
1203 case 4:
1204 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1205 }
1206 break;
1207 case 32:
1208 switch (desc->nr_channels) {
1209 case 1:
1210 return V_008F14_IMG_DATA_FORMAT_32;
1211 case 2:
1212 return V_008F14_IMG_DATA_FORMAT_32_32;
1213 #if 0 /* Not supported for render targets */
1214 case 3:
1215 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1216 #endif
1217 case 4:
1218 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1219 }
1220 }
1221
1222 out_unknown:
1223 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1224 return ~0;
1225 }
1226
1227 static unsigned si_tex_wrap(unsigned wrap)
1228 {
1229 switch (wrap) {
1230 default:
1231 case PIPE_TEX_WRAP_REPEAT:
1232 return V_008F30_SQ_TEX_WRAP;
1233 case PIPE_TEX_WRAP_CLAMP:
1234 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1235 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1236 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1237 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1238 return V_008F30_SQ_TEX_CLAMP_BORDER;
1239 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1240 return V_008F30_SQ_TEX_MIRROR;
1241 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1242 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1243 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1244 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1245 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1246 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1247 }
1248 }
1249
1250 static unsigned si_tex_filter(unsigned filter)
1251 {
1252 switch (filter) {
1253 default:
1254 case PIPE_TEX_FILTER_NEAREST:
1255 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1256 case PIPE_TEX_FILTER_LINEAR:
1257 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1258 }
1259 }
1260
1261 static unsigned si_tex_mipfilter(unsigned filter)
1262 {
1263 switch (filter) {
1264 case PIPE_TEX_MIPFILTER_NEAREST:
1265 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1266 case PIPE_TEX_MIPFILTER_LINEAR:
1267 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1268 default:
1269 case PIPE_TEX_MIPFILTER_NONE:
1270 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1271 }
1272 }
1273
1274 static unsigned si_tex_compare(unsigned compare)
1275 {
1276 switch (compare) {
1277 default:
1278 case PIPE_FUNC_NEVER:
1279 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1280 case PIPE_FUNC_LESS:
1281 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1282 case PIPE_FUNC_EQUAL:
1283 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1284 case PIPE_FUNC_LEQUAL:
1285 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1286 case PIPE_FUNC_GREATER:
1287 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1288 case PIPE_FUNC_NOTEQUAL:
1289 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1290 case PIPE_FUNC_GEQUAL:
1291 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1292 case PIPE_FUNC_ALWAYS:
1293 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1294 }
1295 }
1296
1297 static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
1298 {
1299 switch (dim) {
1300 default:
1301 case PIPE_TEXTURE_1D:
1302 return V_008F1C_SQ_RSRC_IMG_1D;
1303 case PIPE_TEXTURE_1D_ARRAY:
1304 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1305 case PIPE_TEXTURE_2D:
1306 case PIPE_TEXTURE_RECT:
1307 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1308 V_008F1C_SQ_RSRC_IMG_2D;
1309 case PIPE_TEXTURE_2D_ARRAY:
1310 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1311 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1312 case PIPE_TEXTURE_3D:
1313 return V_008F1C_SQ_RSRC_IMG_3D;
1314 case PIPE_TEXTURE_CUBE:
1315 return V_008F1C_SQ_RSRC_IMG_CUBE;
1316 }
1317 }
1318
1319 /*
1320 * Format support testing
1321 */
1322
1323 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1324 {
1325 return si_translate_texformat(screen, format, util_format_description(format),
1326 util_format_get_first_non_void_channel(format)) != ~0U;
1327 }
1328
1329 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1330 const struct util_format_description *desc,
1331 int first_non_void)
1332 {
1333 unsigned type = desc->channel[first_non_void].type;
1334 int i;
1335
1336 if (type == UTIL_FORMAT_TYPE_FIXED)
1337 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1338
1339 if (desc->nr_channels == 4 &&
1340 desc->channel[0].size == 10 &&
1341 desc->channel[1].size == 10 &&
1342 desc->channel[2].size == 10 &&
1343 desc->channel[3].size == 2)
1344 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1345
1346 /* See whether the components are of the same size. */
1347 for (i = 0; i < desc->nr_channels; i++) {
1348 if (desc->channel[first_non_void].size != desc->channel[i].size)
1349 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1350 }
1351
1352 switch (desc->channel[first_non_void].size) {
1353 case 8:
1354 switch (desc->nr_channels) {
1355 case 1:
1356 return V_008F0C_BUF_DATA_FORMAT_8;
1357 case 2:
1358 return V_008F0C_BUF_DATA_FORMAT_8_8;
1359 case 3:
1360 case 4:
1361 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1362 }
1363 break;
1364 case 16:
1365 switch (desc->nr_channels) {
1366 case 1:
1367 return V_008F0C_BUF_DATA_FORMAT_16;
1368 case 2:
1369 return V_008F0C_BUF_DATA_FORMAT_16_16;
1370 case 3:
1371 case 4:
1372 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1373 }
1374 break;
1375 case 32:
1376 /* From the Southern Islands ISA documentation about MTBUF:
1377 * 'Memory reads of data in memory that is 32 or 64 bits do not
1378 * undergo any format conversion.'
1379 */
1380 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1381 !desc->channel[first_non_void].pure_integer)
1382 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1383
1384 switch (desc->nr_channels) {
1385 case 1:
1386 return V_008F0C_BUF_DATA_FORMAT_32;
1387 case 2:
1388 return V_008F0C_BUF_DATA_FORMAT_32_32;
1389 case 3:
1390 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1391 case 4:
1392 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1393 }
1394 break;
1395 }
1396
1397 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1398 }
1399
1400 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1401 const struct util_format_description *desc,
1402 int first_non_void)
1403 {
1404 switch (desc->channel[first_non_void].type) {
1405 case UTIL_FORMAT_TYPE_SIGNED:
1406 if (desc->channel[first_non_void].normalized)
1407 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1408 else if (desc->channel[first_non_void].pure_integer)
1409 return V_008F0C_BUF_NUM_FORMAT_SINT;
1410 else
1411 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1412 break;
1413 case UTIL_FORMAT_TYPE_UNSIGNED:
1414 if (desc->channel[first_non_void].normalized)
1415 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1416 else if (desc->channel[first_non_void].pure_integer)
1417 return V_008F0C_BUF_NUM_FORMAT_UINT;
1418 else
1419 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1420 break;
1421 case UTIL_FORMAT_TYPE_FLOAT:
1422 default:
1423 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1424 }
1425 }
1426
1427 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1428 {
1429 const struct util_format_description *desc;
1430 int first_non_void;
1431 unsigned data_format;
1432
1433 desc = util_format_description(format);
1434 first_non_void = util_format_get_first_non_void_channel(format);
1435 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1436 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1437 }
1438
1439 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1440 {
1441 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1442 r600_translate_colorswap(format) != ~0U;
1443 }
1444
1445 static bool si_is_zs_format_supported(enum pipe_format format)
1446 {
1447 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1448 }
1449
1450 boolean si_is_format_supported(struct pipe_screen *screen,
1451 enum pipe_format format,
1452 enum pipe_texture_target target,
1453 unsigned sample_count,
1454 unsigned usage)
1455 {
1456 struct si_screen *sscreen = (struct si_screen *)screen;
1457 unsigned retval = 0;
1458
1459 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1460 R600_ERR("r600: unsupported texture type %d\n", target);
1461 return FALSE;
1462 }
1463
1464 if (!util_format_is_supported(format, usage))
1465 return FALSE;
1466
1467 if (sample_count > 1) {
1468 if (HAVE_LLVM < 0x0304)
1469 return FALSE;
1470
1471 /* 2D tiling on CIK is supported since DRM 2.35.0 */
1472 if (sscreen->b.chip_class >= CIK && sscreen->b.info.drm_minor < 35)
1473 return FALSE;
1474
1475 switch (sample_count) {
1476 case 2:
1477 case 4:
1478 case 8:
1479 break;
1480 default:
1481 return FALSE;
1482 }
1483 }
1484
1485 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1486 if (target == PIPE_BUFFER) {
1487 if (si_is_vertex_format_supported(screen, format))
1488 retval |= PIPE_BIND_SAMPLER_VIEW;
1489 } else {
1490 if (si_is_sampler_format_supported(screen, format))
1491 retval |= PIPE_BIND_SAMPLER_VIEW;
1492 }
1493 }
1494
1495 if ((usage & (PIPE_BIND_RENDER_TARGET |
1496 PIPE_BIND_DISPLAY_TARGET |
1497 PIPE_BIND_SCANOUT |
1498 PIPE_BIND_SHARED)) &&
1499 si_is_colorbuffer_format_supported(format)) {
1500 retval |= usage &
1501 (PIPE_BIND_RENDER_TARGET |
1502 PIPE_BIND_DISPLAY_TARGET |
1503 PIPE_BIND_SCANOUT |
1504 PIPE_BIND_SHARED);
1505 }
1506
1507 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1508 si_is_zs_format_supported(format)) {
1509 retval |= PIPE_BIND_DEPTH_STENCIL;
1510 }
1511
1512 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1513 si_is_vertex_format_supported(screen, format)) {
1514 retval |= PIPE_BIND_VERTEX_BUFFER;
1515 }
1516
1517 if (usage & PIPE_BIND_TRANSFER_READ)
1518 retval |= PIPE_BIND_TRANSFER_READ;
1519 if (usage & PIPE_BIND_TRANSFER_WRITE)
1520 retval |= PIPE_BIND_TRANSFER_WRITE;
1521
1522 return retval == usage;
1523 }
1524
1525 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1526 {
1527 unsigned tile_mode_index = 0;
1528
1529 if (stencil) {
1530 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1531 } else {
1532 tile_mode_index = rtex->surface.tiling_index[level];
1533 }
1534 return tile_mode_index;
1535 }
1536
1537 /*
1538 * framebuffer handling
1539 */
1540
1541 static void si_initialize_color_surface(struct si_context *sctx,
1542 struct r600_surface *surf)
1543 {
1544 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1545 unsigned level = surf->base.u.tex.level;
1546 uint64_t offset = rtex->surface.level[level].offset;
1547 unsigned pitch, slice;
1548 unsigned color_info, color_attrib, color_pitch, color_view;
1549 unsigned tile_mode_index;
1550 unsigned format, swap, ntype, endian;
1551 const struct util_format_description *desc;
1552 int i;
1553 unsigned blend_clamp = 0, blend_bypass = 0;
1554 unsigned max_comp_size;
1555
1556 /* Layered rendering doesn't work with LINEAR_GENERAL.
1557 * (LINEAR_ALIGNED and others work) */
1558 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1559 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
1560 offset += rtex->surface.level[level].slice_size *
1561 surf->base.u.tex.first_layer;
1562 color_view = 0;
1563 } else {
1564 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1565 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1566 }
1567
1568 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1569 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1570 if (slice) {
1571 slice = slice - 1;
1572 }
1573
1574 tile_mode_index = si_tile_mode_index(rtex, level, false);
1575
1576 desc = util_format_description(surf->base.format);
1577 for (i = 0; i < 4; i++) {
1578 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1579 break;
1580 }
1581 }
1582 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1583 ntype = V_028C70_NUMBER_FLOAT;
1584 } else {
1585 ntype = V_028C70_NUMBER_UNORM;
1586 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1587 ntype = V_028C70_NUMBER_SRGB;
1588 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1589 if (desc->channel[i].pure_integer) {
1590 ntype = V_028C70_NUMBER_SINT;
1591 } else {
1592 assert(desc->channel[i].normalized);
1593 ntype = V_028C70_NUMBER_SNORM;
1594 }
1595 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1596 if (desc->channel[i].pure_integer) {
1597 ntype = V_028C70_NUMBER_UINT;
1598 } else {
1599 assert(desc->channel[i].normalized);
1600 ntype = V_028C70_NUMBER_UNORM;
1601 }
1602 }
1603 }
1604
1605 format = si_translate_colorformat(surf->base.format);
1606 if (format == V_028C70_COLOR_INVALID) {
1607 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1608 }
1609 assert(format != V_028C70_COLOR_INVALID);
1610 swap = r600_translate_colorswap(surf->base.format);
1611 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1612 endian = V_028C70_ENDIAN_NONE;
1613 } else {
1614 endian = si_colorformat_endian_swap(format);
1615 }
1616
1617 /* blend clamp should be set for all NORM/SRGB types */
1618 if (ntype == V_028C70_NUMBER_UNORM ||
1619 ntype == V_028C70_NUMBER_SNORM ||
1620 ntype == V_028C70_NUMBER_SRGB)
1621 blend_clamp = 1;
1622
1623 /* set blend bypass according to docs if SINT/UINT or
1624 8/24 COLOR variants */
1625 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1626 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1627 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1628 blend_clamp = 0;
1629 blend_bypass = 1;
1630 }
1631
1632 color_info = S_028C70_FORMAT(format) |
1633 S_028C70_COMP_SWAP(swap) |
1634 S_028C70_BLEND_CLAMP(blend_clamp) |
1635 S_028C70_BLEND_BYPASS(blend_bypass) |
1636 S_028C70_NUMBER_TYPE(ntype) |
1637 S_028C70_ENDIAN(endian);
1638
1639 color_pitch = S_028C64_TILE_MAX(pitch);
1640
1641 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1642 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1643
1644 if (rtex->resource.b.b.nr_samples > 1) {
1645 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1646
1647 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1648 S_028C74_NUM_FRAGMENTS(log_samples);
1649
1650 if (rtex->fmask.size) {
1651 color_info |= S_028C70_COMPRESSION(1);
1652 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1653
1654 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
1655
1656 if (sctx->b.chip_class == SI) {
1657 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1658 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1659 }
1660 if (sctx->b.chip_class >= CIK) {
1661 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch / 8 - 1);
1662 }
1663 }
1664 }
1665
1666 offset += r600_resource_va(sctx->b.b.screen, surf->base.texture);
1667
1668 surf->cb_color_base = offset >> 8;
1669 surf->cb_color_pitch = color_pitch;
1670 surf->cb_color_slice = S_028C68_TILE_MAX(slice);
1671 surf->cb_color_view = color_view;
1672 surf->cb_color_info = color_info;
1673 surf->cb_color_attrib = color_attrib;
1674
1675 if (rtex->fmask.size) {
1676 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
1677 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1678 } else {
1679 /* This must be set for fast clear to work without FMASK. */
1680 surf->cb_color_fmask = surf->cb_color_base;
1681 surf->cb_color_fmask_slice = surf->cb_color_slice;
1682 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1683
1684 if (sctx->b.chip_class == SI) {
1685 unsigned bankh = util_logbase2(rtex->surface.bankh);
1686 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1687 }
1688
1689 if (sctx->b.chip_class >= CIK) {
1690 surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch);
1691 }
1692 }
1693
1694 /* Determine pixel shader export format */
1695 max_comp_size = si_colorformat_max_comp_size(format);
1696 if (ntype == V_028C70_NUMBER_SRGB ||
1697 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1698 max_comp_size <= 10) ||
1699 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1700 surf->export_16bpc = true;
1701 }
1702
1703 surf->color_initialized = true;
1704 }
1705
1706 static void si_init_depth_surface(struct si_context *sctx,
1707 struct r600_surface *surf)
1708 {
1709 struct si_screen *sscreen = sctx->screen;
1710 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1711 unsigned level = surf->base.u.tex.level;
1712 unsigned pitch, slice, format, tile_mode_index, array_mode;
1713 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1714 uint32_t z_info, s_info, db_depth_info;
1715 uint64_t z_offs, s_offs;
1716 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
1717
1718 switch (sctx->framebuffer.state.zsbuf->texture->format) {
1719 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1720 case PIPE_FORMAT_X8Z24_UNORM:
1721 case PIPE_FORMAT_Z24X8_UNORM:
1722 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1723 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1724 break;
1725 case PIPE_FORMAT_Z32_FLOAT:
1726 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1727 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1728 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1729 break;
1730 case PIPE_FORMAT_Z16_UNORM:
1731 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1732 break;
1733 default:
1734 assert(0);
1735 }
1736
1737 format = si_translate_dbformat(rtex->resource.b.b.format);
1738
1739 if (format == V_028040_Z_INVALID) {
1740 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1741 }
1742 assert(format != V_028040_Z_INVALID);
1743
1744 s_offs = z_offs = r600_resource_va(sctx->b.b.screen, surf->base.texture);
1745 z_offs += rtex->surface.level[level].offset;
1746 s_offs += rtex->surface.stencil_level[level].offset;
1747
1748 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1749 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1750 if (slice) {
1751 slice = slice - 1;
1752 }
1753
1754 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1755
1756 z_info = S_028040_FORMAT(format);
1757 if (rtex->resource.b.b.nr_samples > 1) {
1758 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1759 }
1760
1761 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1762 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
1763 else
1764 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1765
1766 if (sctx->b.chip_class >= CIK) {
1767 switch (rtex->surface.level[level].mode) {
1768 case RADEON_SURF_MODE_2D:
1769 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
1770 break;
1771 case RADEON_SURF_MODE_1D:
1772 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1773 case RADEON_SURF_MODE_LINEAR:
1774 default:
1775 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
1776 break;
1777 }
1778 tile_split = rtex->surface.tile_split;
1779 stile_split = rtex->surface.stencil_tile_split;
1780 macro_aspect = rtex->surface.mtilea;
1781 bankw = rtex->surface.bankw;
1782 bankh = rtex->surface.bankh;
1783 tile_split = cik_tile_split(tile_split);
1784 stile_split = cik_tile_split(stile_split);
1785 macro_aspect = cik_macro_tile_aspect(macro_aspect);
1786 bankw = cik_bank_wh(bankw);
1787 bankh = cik_bank_wh(bankh);
1788 nbanks = cik_num_banks(sscreen, rtex->surface.bpe, rtex->surface.tile_split);
1789 tile_mode_index = si_tile_mode_index(rtex, level, false);
1790 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
1791
1792 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
1793 S_02803C_PIPE_CONFIG(pipe_config) |
1794 S_02803C_BANK_WIDTH(bankw) |
1795 S_02803C_BANK_HEIGHT(bankh) |
1796 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
1797 S_02803C_NUM_BANKS(nbanks);
1798 z_info |= S_028040_TILE_SPLIT(tile_split);
1799 s_info |= S_028044_TILE_SPLIT(stile_split);
1800 } else {
1801 tile_mode_index = si_tile_mode_index(rtex, level, false);
1802 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1803 tile_mode_index = si_tile_mode_index(rtex, level, true);
1804 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1805 }
1806
1807 /* HiZ aka depth buffer htile */
1808 /* use htile only for first level */
1809 if (rtex->htile_buffer && !level) {
1810 const struct util_format_description *fmt_desc;
1811
1812 z_info |= S_028040_TILE_SURFACE_ENABLE(1);
1813
1814 /* This is optimal for the clear value of 1.0 and using
1815 * the LESS and LEQUAL test functions. Set this to 0
1816 * for the opposite case. This can only be changed when
1817 * clearing. */
1818 z_info |= S_028040_ZRANGE_PRECISION(1);
1819
1820 fmt_desc = util_format_description(rtex->resource.b.b.format);
1821 if (!util_format_has_stencil(fmt_desc)) {
1822 /* Use all of the htile_buffer for depth */
1823 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
1824 }
1825
1826 uint64_t va = r600_resource_va(&sctx->screen->b.b, &rtex->htile_buffer->b.b);
1827 db_htile_data_base = va >> 8;
1828 db_htile_surface = S_028ABC_FULL_CACHE(1);
1829 } else {
1830 db_htile_data_base = 0;
1831 db_htile_surface = 0;
1832 }
1833
1834 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1835 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1836 surf->db_htile_data_base = db_htile_data_base;
1837 surf->db_depth_info = db_depth_info;
1838 surf->db_z_info = z_info;
1839 surf->db_stencil_info = s_info;
1840 surf->db_depth_base = z_offs >> 8;
1841 surf->db_stencil_base = s_offs >> 8;
1842 surf->db_depth_size = S_028058_PITCH_TILE_MAX(pitch);
1843 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(slice);
1844 surf->db_htile_surface = db_htile_surface;
1845 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
1846
1847 surf->depth_initialized = true;
1848 }
1849
1850 static void si_set_framebuffer_state(struct pipe_context *ctx,
1851 const struct pipe_framebuffer_state *state)
1852 {
1853 struct si_context *sctx = (struct si_context *)ctx;
1854 struct r600_surface *surf = NULL;
1855 struct r600_texture *rtex;
1856 int i;
1857
1858 if (sctx->framebuffer.state.nr_cbufs) {
1859 sctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
1860 R600_CONTEXT_FLUSH_AND_INV_CB_META;
1861 }
1862 if (sctx->framebuffer.state.zsbuf) {
1863 sctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB |
1864 R600_CONTEXT_FLUSH_AND_INV_DB_META;
1865 }
1866
1867 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
1868
1869 sctx->framebuffer.export_16bpc = 0;
1870 sctx->framebuffer.compressed_cb_mask = 0;
1871 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1872 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
1873 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1874 util_format_is_pure_integer(state->cbufs[0]->format);
1875
1876 for (i = 0; i < state->nr_cbufs; i++) {
1877 if (!state->cbufs[i])
1878 continue;
1879
1880 surf = (struct r600_surface*)state->cbufs[i];
1881 rtex = (struct r600_texture*)surf->base.texture;
1882
1883 if (!surf->color_initialized) {
1884 si_initialize_color_surface(sctx, surf);
1885 }
1886
1887 if (surf->export_16bpc) {
1888 sctx->framebuffer.export_16bpc |= 1 << i;
1889 }
1890
1891 if (rtex->fmask.size && rtex->cmask.size) {
1892 sctx->framebuffer.compressed_cb_mask |= 1 << i;
1893 }
1894 }
1895 /* Set the 16BPC export for possible dual-src blending. */
1896 if (i == 1 && surf && surf->export_16bpc) {
1897 sctx->framebuffer.export_16bpc |= 1 << 1;
1898 }
1899
1900 assert(!(sctx->framebuffer.export_16bpc & ~0xff));
1901
1902 if (state->zsbuf) {
1903 surf = (struct r600_surface*)state->zsbuf;
1904
1905 if (!surf->depth_initialized) {
1906 si_init_depth_surface(sctx, surf);
1907 }
1908 }
1909
1910 si_update_fb_rs_state(sctx);
1911 si_update_fb_blend_state(sctx);
1912
1913 sctx->framebuffer.atom.num_dw = state->nr_cbufs*15 + (8 - state->nr_cbufs)*3;
1914 sctx->framebuffer.atom.num_dw += state->zsbuf ? 23 : 4;
1915 sctx->framebuffer.atom.num_dw += 3; /* WINDOW_SCISSOR_BR */
1916 sctx->framebuffer.atom.num_dw += 25; /* MSAA */
1917 sctx->framebuffer.atom.dirty = true;
1918 }
1919
1920 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
1921 {
1922 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
1923 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
1924 unsigned i, nr_cbufs = state->nr_cbufs;
1925 struct r600_texture *tex = NULL;
1926 struct r600_surface *cb = NULL;
1927
1928 /* Colorbuffers. */
1929 for (i = 0; i < nr_cbufs; i++) {
1930 cb = (struct r600_surface*)state->cbufs[i];
1931 if (!cb) {
1932 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1933 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1934 continue;
1935 }
1936
1937 tex = (struct r600_texture *)cb->base.texture;
1938 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
1939 &tex->resource, RADEON_USAGE_READWRITE,
1940 tex->surface.nsamples > 1 ?
1941 RADEON_PRIO_COLOR_BUFFER_MSAA :
1942 RADEON_PRIO_COLOR_BUFFER);
1943
1944 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
1945 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
1946 tex->cmask_buffer, RADEON_USAGE_READWRITE,
1947 RADEON_PRIO_COLOR_META);
1948 }
1949
1950 r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
1951 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1952 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1953 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1954 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1955 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1956 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
1957 radeon_emit(cs, 0); /* R_028C78 unused */
1958 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
1959 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1960 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
1961 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1962 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1963 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1964 }
1965 /* set CB_COLOR1_INFO for possible dual-src blending */
1966 if (i == 1 && state->cbufs[0]) {
1967 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1968 cb->cb_color_info | tex->cb_color_info);
1969 i++;
1970 }
1971 for (; i < 8 ; i++) {
1972 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1973 }
1974
1975 /* ZS buffer. */
1976 if (state->zsbuf) {
1977 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
1978 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
1979
1980 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
1981 &rtex->resource, RADEON_USAGE_READWRITE,
1982 zb->base.texture->nr_samples > 1 ?
1983 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1984 RADEON_PRIO_DEPTH_BUFFER);
1985
1986 if (zb->db_htile_data_base) {
1987 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
1988 rtex->htile_buffer, RADEON_USAGE_READWRITE,
1989 RADEON_PRIO_DEPTH_META);
1990 }
1991
1992 r600_write_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
1993 r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
1994
1995 r600_write_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
1996 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1997 radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */
1998 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1999 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2000 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2001 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2002 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2003 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2004 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2005
2006 r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2007 r600_write_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2008 zb->pa_su_poly_offset_db_fmt_cntl);
2009 } else {
2010 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2011 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2012 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2013 }
2014
2015 /* Framebuffer dimensions. */
2016 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2017 r600_write_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2018 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2019
2020 cayman_emit_msaa_state(cs, sctx->framebuffer.nr_samples);
2021 }
2022
2023 /*
2024 * shaders
2025 */
2026
2027 /* Compute the key for the hw shader variant */
2028 static INLINE void si_shader_selector_key(struct pipe_context *ctx,
2029 struct si_pipe_shader_selector *sel,
2030 union si_shader_key *key)
2031 {
2032 struct si_context *sctx = (struct si_context *)ctx;
2033 memset(key, 0, sizeof(*key));
2034
2035 if ((sel->type == PIPE_SHADER_VERTEX || sel->type == PIPE_SHADER_GEOMETRY) &&
2036 sctx->queued.named.rasterizer) {
2037 if (sctx->queued.named.rasterizer->clip_plane_enable & 0xf0)
2038 key->vs.ucps_enabled |= 0x2;
2039 if (sctx->queued.named.rasterizer->clip_plane_enable & 0xf)
2040 key->vs.ucps_enabled |= 0x1;
2041 }
2042
2043 if (sel->type == PIPE_SHADER_VERTEX) {
2044 unsigned i;
2045 if (!sctx->vertex_elements)
2046 return;
2047
2048 for (i = 0; i < sctx->vertex_elements->count; ++i)
2049 key->vs.instance_divisors[i] = sctx->vertex_elements->elements[i].instance_divisor;
2050
2051 key->vs.as_es = sctx->gs_shader != NULL;
2052 } else if (sel->type == PIPE_SHADER_FRAGMENT) {
2053 if (sel->fs_write_all)
2054 key->ps.nr_cbufs = sctx->framebuffer.state.nr_cbufs;
2055 key->ps.export_16bpc = sctx->framebuffer.export_16bpc;
2056
2057 if (sctx->queued.named.rasterizer) {
2058 key->ps.color_two_side = sctx->queued.named.rasterizer->two_side;
2059 key->ps.flatshade = sctx->queued.named.rasterizer->flatshade;
2060
2061 if (sctx->queued.named.blend) {
2062 key->ps.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
2063 sctx->queued.named.rasterizer->multisample_enable &&
2064 !sctx->framebuffer.cb0_is_integer;
2065 }
2066 }
2067 if (sctx->queued.named.dsa) {
2068 key->ps.alpha_func = sctx->queued.named.dsa->alpha_func;
2069
2070 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
2071 if (sctx->framebuffer.cb0_is_integer)
2072 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2073 } else {
2074 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2075 }
2076 }
2077 }
2078
2079 /* Select the hw shader variant depending on the current state. */
2080 int si_shader_select(struct pipe_context *ctx,
2081 struct si_pipe_shader_selector *sel)
2082 {
2083 union si_shader_key key;
2084 struct si_pipe_shader * shader = NULL;
2085 int r;
2086
2087 si_shader_selector_key(ctx, sel, &key);
2088
2089 /* Check if we don't need to change anything.
2090 * This path is also used for most shaders that don't need multiple
2091 * variants, it will cost just a computation of the key and this
2092 * test. */
2093 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
2094 return 0;
2095 }
2096
2097 /* lookup if we have other variants in the list */
2098 if (sel->num_shaders > 1) {
2099 struct si_pipe_shader *p = sel->current, *c = p->next_variant;
2100
2101 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
2102 p = c;
2103 c = c->next_variant;
2104 }
2105
2106 if (c) {
2107 p->next_variant = c->next_variant;
2108 shader = c;
2109 }
2110 }
2111
2112 if (shader) {
2113 shader->next_variant = sel->current;
2114 sel->current = shader;
2115 } else {
2116 shader = CALLOC(1, sizeof(struct si_pipe_shader));
2117 shader->selector = sel;
2118 shader->key = key;
2119
2120 shader->next_variant = sel->current;
2121 sel->current = shader;
2122 r = si_pipe_shader_create(ctx, shader);
2123 if (unlikely(r)) {
2124 R600_ERR("Failed to build shader variant (type=%u) %d\n",
2125 sel->type, r);
2126 sel->current = NULL;
2127 FREE(shader);
2128 return r;
2129 }
2130 sel->num_shaders++;
2131 }
2132
2133 return 0;
2134 }
2135
2136 static void *si_create_shader_state(struct pipe_context *ctx,
2137 const struct pipe_shader_state *state,
2138 unsigned pipe_shader_type)
2139 {
2140 struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector);
2141 int r;
2142
2143 sel->type = pipe_shader_type;
2144 sel->tokens = tgsi_dup_tokens(state->tokens);
2145 sel->so = state->stream_output;
2146
2147 if (pipe_shader_type == PIPE_SHADER_FRAGMENT) {
2148 struct tgsi_shader_info info;
2149
2150 tgsi_scan_shader(state->tokens, &info);
2151 sel->fs_write_all = info.color0_writes_all_cbufs;
2152 }
2153
2154 r = si_shader_select(ctx, sel);
2155 if (r) {
2156 free(sel);
2157 return NULL;
2158 }
2159
2160 return sel;
2161 }
2162
2163 static void *si_create_fs_state(struct pipe_context *ctx,
2164 const struct pipe_shader_state *state)
2165 {
2166 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
2167 }
2168
2169 #if HAVE_LLVM >= 0x0305
2170
2171 static void *si_create_gs_state(struct pipe_context *ctx,
2172 const struct pipe_shader_state *state)
2173 {
2174 return si_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
2175 }
2176
2177 #endif
2178
2179 static void *si_create_vs_state(struct pipe_context *ctx,
2180 const struct pipe_shader_state *state)
2181 {
2182 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
2183 }
2184
2185 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2186 {
2187 struct si_context *sctx = (struct si_context *)ctx;
2188 struct si_pipe_shader_selector *sel = state;
2189
2190 if (sctx->vs_shader == sel)
2191 return;
2192
2193 if (!sel || !sel->current)
2194 return;
2195
2196 sctx->vs_shader = sel;
2197 }
2198
2199 #if HAVE_LLVM >= 0x0305
2200
2201 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2202 {
2203 struct si_context *sctx = (struct si_context *)ctx;
2204 struct si_pipe_shader_selector *sel = state;
2205
2206 if (sctx->gs_shader == sel)
2207 return;
2208
2209 sctx->gs_shader = sel;
2210 }
2211
2212 #endif
2213
2214 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2215 {
2216 struct si_context *sctx = (struct si_context *)ctx;
2217 struct si_pipe_shader_selector *sel = state;
2218
2219 /* skip if supplied shader is one already in use */
2220 if (sctx->ps_shader == sel)
2221 return;
2222
2223 /* use dummy shader if supplied shader is corrupt */
2224 if (!sel || !sel->current)
2225 sel = sctx->dummy_pixel_shader;
2226
2227 sctx->ps_shader = sel;
2228 }
2229
2230 static void si_delete_shader_selector(struct pipe_context *ctx,
2231 struct si_pipe_shader_selector *sel)
2232 {
2233 struct si_context *sctx = (struct si_context *)ctx;
2234 struct si_pipe_shader *p = sel->current, *c;
2235
2236 while (p) {
2237 c = p->next_variant;
2238 if (sel->type == PIPE_SHADER_GEOMETRY)
2239 si_pm4_delete_state(sctx, gs, p->pm4);
2240 else if (sel->type == PIPE_SHADER_FRAGMENT)
2241 si_pm4_delete_state(sctx, ps, p->pm4);
2242 else if (p->key.vs.as_es)
2243 si_pm4_delete_state(sctx, es, p->pm4);
2244 else
2245 si_pm4_delete_state(sctx, vs, p->pm4);
2246 si_pipe_shader_destroy(ctx, p);
2247 free(p);
2248 p = c;
2249 }
2250
2251 free(sel->tokens);
2252 free(sel);
2253 }
2254
2255 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
2256 {
2257 struct si_context *sctx = (struct si_context *)ctx;
2258 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2259
2260 if (sctx->vs_shader == sel) {
2261 sctx->vs_shader = NULL;
2262 }
2263
2264 si_delete_shader_selector(ctx, sel);
2265 }
2266
2267 #if HAVE_LLVM >= 0x0305
2268
2269 static void si_delete_gs_shader(struct pipe_context *ctx, void *state)
2270 {
2271 struct si_context *sctx = (struct si_context *)ctx;
2272 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2273
2274 if (sctx->gs_shader == sel) {
2275 sctx->gs_shader = NULL;
2276 }
2277
2278 si_delete_shader_selector(ctx, sel);
2279 }
2280
2281 #endif
2282
2283 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
2284 {
2285 struct si_context *sctx = (struct si_context *)ctx;
2286 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2287
2288 if (sctx->ps_shader == sel) {
2289 sctx->ps_shader = NULL;
2290 }
2291
2292 si_delete_shader_selector(ctx, sel);
2293 }
2294
2295 /*
2296 * Samplers
2297 */
2298
2299 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
2300 struct pipe_resource *texture,
2301 const struct pipe_sampler_view *state)
2302 {
2303 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
2304 struct r600_texture *tmp = (struct r600_texture*)texture;
2305 const struct util_format_description *desc;
2306 unsigned format, num_format;
2307 uint32_t pitch = 0;
2308 unsigned char state_swizzle[4], swizzle[4];
2309 unsigned height, depth, width;
2310 enum pipe_format pipe_format = state->format;
2311 struct radeon_surface_level *surflevel;
2312 int first_non_void;
2313 uint64_t va;
2314
2315 if (view == NULL)
2316 return NULL;
2317
2318 /* initialize base object */
2319 view->base = *state;
2320 view->base.texture = NULL;
2321 pipe_resource_reference(&view->base.texture, texture);
2322 view->base.reference.count = 1;
2323 view->base.context = ctx;
2324 view->resource = &tmp->resource;
2325
2326 /* Buffer resource. */
2327 if (texture->target == PIPE_BUFFER) {
2328 unsigned stride;
2329
2330 desc = util_format_description(state->format);
2331 first_non_void = util_format_get_first_non_void_channel(state->format);
2332 stride = desc->block.bits / 8;
2333 va = r600_resource_va(ctx->screen, texture) + state->u.buf.first_element*stride;
2334 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2335 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2336
2337 view->state[0] = va;
2338 view->state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2339 S_008F04_STRIDE(stride);
2340 view->state[2] = state->u.buf.last_element + 1 - state->u.buf.first_element;
2341 view->state[3] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2342 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2343 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2344 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2345 S_008F0C_NUM_FORMAT(num_format) |
2346 S_008F0C_DATA_FORMAT(format);
2347 return &view->base;
2348 }
2349
2350 state_swizzle[0] = state->swizzle_r;
2351 state_swizzle[1] = state->swizzle_g;
2352 state_swizzle[2] = state->swizzle_b;
2353 state_swizzle[3] = state->swizzle_a;
2354
2355 surflevel = tmp->surface.level;
2356
2357 /* Texturing with separate depth and stencil. */
2358 if (tmp->is_depth && !tmp->is_flushing_texture) {
2359 switch (pipe_format) {
2360 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2361 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2362 break;
2363 case PIPE_FORMAT_X8Z24_UNORM:
2364 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2365 /* Z24 is always stored like this. */
2366 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2367 break;
2368 case PIPE_FORMAT_X24S8_UINT:
2369 case PIPE_FORMAT_S8X24_UINT:
2370 case PIPE_FORMAT_X32_S8X24_UINT:
2371 pipe_format = PIPE_FORMAT_S8_UINT;
2372 surflevel = tmp->surface.stencil_level;
2373 break;
2374 default:;
2375 }
2376 }
2377
2378 desc = util_format_description(pipe_format);
2379
2380 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2381 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2382 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2383
2384 switch (pipe_format) {
2385 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2386 case PIPE_FORMAT_X24S8_UINT:
2387 case PIPE_FORMAT_X32_S8X24_UINT:
2388 case PIPE_FORMAT_X8Z24_UNORM:
2389 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2390 break;
2391 default:
2392 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2393 }
2394 } else {
2395 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2396 }
2397
2398 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2399
2400 switch (pipe_format) {
2401 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2402 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2403 break;
2404 default:
2405 if (first_non_void < 0) {
2406 if (util_format_is_compressed(pipe_format)) {
2407 switch (pipe_format) {
2408 case PIPE_FORMAT_DXT1_SRGB:
2409 case PIPE_FORMAT_DXT1_SRGBA:
2410 case PIPE_FORMAT_DXT3_SRGBA:
2411 case PIPE_FORMAT_DXT5_SRGBA:
2412 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2413 break;
2414 case PIPE_FORMAT_RGTC1_SNORM:
2415 case PIPE_FORMAT_LATC1_SNORM:
2416 case PIPE_FORMAT_RGTC2_SNORM:
2417 case PIPE_FORMAT_LATC2_SNORM:
2418 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2419 break;
2420 default:
2421 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2422 break;
2423 }
2424 } else {
2425 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2426 }
2427 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2428 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2429 } else {
2430 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2431
2432 switch (desc->channel[first_non_void].type) {
2433 case UTIL_FORMAT_TYPE_FLOAT:
2434 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2435 break;
2436 case UTIL_FORMAT_TYPE_SIGNED:
2437 if (desc->channel[first_non_void].normalized)
2438 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2439 else if (desc->channel[first_non_void].pure_integer)
2440 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2441 else
2442 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2443 break;
2444 case UTIL_FORMAT_TYPE_UNSIGNED:
2445 if (desc->channel[first_non_void].normalized)
2446 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2447 else if (desc->channel[first_non_void].pure_integer)
2448 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2449 else
2450 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2451 }
2452 }
2453 }
2454
2455 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2456 if (format == ~0) {
2457 format = 0;
2458 }
2459
2460 /* not supported any more */
2461 //endian = si_colorformat_endian_swap(format);
2462
2463 width = surflevel[0].npix_x;
2464 height = surflevel[0].npix_y;
2465 depth = surflevel[0].npix_z;
2466 pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
2467
2468 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2469 height = 1;
2470 depth = texture->array_size;
2471 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2472 depth = texture->array_size;
2473 }
2474
2475 va = r600_resource_va(ctx->screen, texture);
2476 va += surflevel[0].offset;
2477 va += tmp->mipmap_shift * surflevel[texture->last_level].slice_size * tmp->surface.array_size;
2478
2479 view->state[0] = va >> 8;
2480 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2481 S_008F14_DATA_FORMAT(format) |
2482 S_008F14_NUM_FORMAT(num_format));
2483 view->state[2] = (S_008F18_WIDTH(width - 1) |
2484 S_008F18_HEIGHT(height - 1));
2485 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2486 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2487 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2488 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2489 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2490 0 : state->u.tex.first_level - tmp->mipmap_shift) |
2491 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2492 util_logbase2(texture->nr_samples) :
2493 state->u.tex.last_level - tmp->mipmap_shift) |
2494 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) |
2495 S_008F1C_POW2_PAD(texture->last_level > 0) |
2496 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples)));
2497 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2498 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2499 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2500 view->state[6] = 0;
2501 view->state[7] = 0;
2502
2503 /* Initialize the sampler view for FMASK. */
2504 if (tmp->fmask.size) {
2505 uint64_t va = r600_resource_va(ctx->screen, texture) + tmp->fmask.offset;
2506 uint32_t fmask_format;
2507
2508 switch (texture->nr_samples) {
2509 case 2:
2510 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2511 break;
2512 case 4:
2513 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2514 break;
2515 case 8:
2516 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2517 break;
2518 default:
2519 assert(0);
2520 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2521 }
2522
2523 view->fmask_state[0] = va >> 8;
2524 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2525 S_008F14_DATA_FORMAT(fmask_format) |
2526 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2527 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2528 S_008F18_HEIGHT(height - 1);
2529 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2530 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2531 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2532 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2533 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2534 S_008F1C_TYPE(si_tex_dim(texture->target, 0));
2535 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2536 S_008F20_PITCH(tmp->fmask.pitch - 1);
2537 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2538 S_008F24_LAST_ARRAY(state->u.tex.last_layer);
2539 view->fmask_state[6] = 0;
2540 view->fmask_state[7] = 0;
2541 }
2542
2543 return &view->base;
2544 }
2545
2546 static void si_sampler_view_destroy(struct pipe_context *ctx,
2547 struct pipe_sampler_view *state)
2548 {
2549 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
2550
2551 pipe_resource_reference(&state->texture, NULL);
2552 FREE(resource);
2553 }
2554
2555 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2556 {
2557 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2558 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2559 (linear_filter &&
2560 (wrap == PIPE_TEX_WRAP_CLAMP ||
2561 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2562 }
2563
2564 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2565 {
2566 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2567 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2568
2569 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2570 state->border_color.ui[2] || state->border_color.ui[3]) &&
2571 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2572 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2573 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2574 }
2575
2576 static void *si_create_sampler_state(struct pipe_context *ctx,
2577 const struct pipe_sampler_state *state)
2578 {
2579 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
2580 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2581 unsigned border_color_type;
2582
2583 if (rstate == NULL) {
2584 return NULL;
2585 }
2586
2587 if (sampler_state_needs_border_color(state))
2588 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2589 else
2590 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2591
2592 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2593 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2594 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2595 (state->max_anisotropy & 0x7) << 9 | /* XXX */
2596 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2597 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2598 aniso_flag_offset << 16 | /* XXX */
2599 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2600 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2601 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2602 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2603 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) |
2604 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) |
2605 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2606 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2607
2608 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2609 memcpy(rstate->border_color, state->border_color.ui,
2610 sizeof(rstate->border_color));
2611 }
2612
2613 return rstate;
2614 }
2615
2616 /* XXX consider moving this function to si_descriptors.c for gcc to inline
2617 * the si_set_sampler_view calls. LTO might help too. */
2618 static void si_set_sampler_views(struct pipe_context *ctx,
2619 unsigned shader, unsigned start,
2620 unsigned count,
2621 struct pipe_sampler_view **views)
2622 {
2623 struct si_context *sctx = (struct si_context *)ctx;
2624 struct si_textures_info *samplers = &sctx->samplers[shader];
2625 struct si_pipe_sampler_view **rviews = (struct si_pipe_sampler_view **)views;
2626 int i;
2627
2628 if (shader >= SI_NUM_SHADERS)
2629 return;
2630
2631 assert(start == 0);
2632
2633 for (i = 0; i < count; i++) {
2634 if (!views[i]) {
2635 samplers->depth_texture_mask &= ~(1 << i);
2636 samplers->compressed_colortex_mask &= ~(1 << i);
2637 si_set_sampler_view(sctx, shader, i, NULL, NULL);
2638 si_set_sampler_view(sctx, shader, FMASK_TEX_OFFSET + i,
2639 NULL, NULL);
2640 continue;
2641 }
2642
2643 si_set_sampler_view(sctx, shader, i, views[i], rviews[i]->state);
2644
2645 if (views[i]->texture->target != PIPE_BUFFER) {
2646 struct r600_texture *rtex =
2647 (struct r600_texture*)views[i]->texture;
2648
2649 if (rtex->is_depth && !rtex->is_flushing_texture) {
2650 samplers->depth_texture_mask |= 1 << i;
2651 } else {
2652 samplers->depth_texture_mask &= ~(1 << i);
2653 }
2654 if (rtex->cmask.size || rtex->fmask.size) {
2655 samplers->compressed_colortex_mask |= 1 << i;
2656 } else {
2657 samplers->compressed_colortex_mask &= ~(1 << i);
2658 }
2659
2660 if (rtex->fmask.size) {
2661 si_set_sampler_view(sctx, shader, FMASK_TEX_OFFSET + i,
2662 views[i], rviews[i]->fmask_state);
2663 } else {
2664 si_set_sampler_view(sctx, shader, FMASK_TEX_OFFSET + i,
2665 NULL, NULL);
2666 }
2667 }
2668 }
2669 for (; i < samplers->n_views; i++) {
2670 samplers->depth_texture_mask &= ~(1 << i);
2671 samplers->compressed_colortex_mask &= ~(1 << i);
2672 si_set_sampler_view(sctx, shader, i, NULL, NULL);
2673 si_set_sampler_view(sctx, shader, FMASK_TEX_OFFSET + i,
2674 NULL, NULL);
2675 }
2676
2677 samplers->n_views = count;
2678 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
2679 }
2680
2681 static void si_set_sampler_states(struct si_context *sctx,
2682 struct si_pm4_state *pm4,
2683 unsigned count, void **states,
2684 struct si_textures_info *samplers,
2685 unsigned user_data_reg)
2686 {
2687 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
2688 uint32_t *border_color_table = NULL;
2689 int i, j;
2690
2691 if (!count)
2692 goto out;
2693
2694 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
2695
2696 si_pm4_sh_data_begin(pm4);
2697 for (i = 0; i < count; i++) {
2698 if (rstates[i] &&
2699 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2700 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2701 if (!sctx->border_color_table ||
2702 ((sctx->border_color_offset + count - i) &
2703 C_008F3C_BORDER_COLOR_PTR)) {
2704 r600_resource_reference(&sctx->border_color_table, NULL);
2705 sctx->border_color_offset = 0;
2706
2707 sctx->border_color_table =
2708 si_resource_create_custom(&sctx->screen->b.b,
2709 PIPE_USAGE_STAGING,
2710 4096 * 4 * 4);
2711 }
2712
2713 if (!border_color_table) {
2714 border_color_table =
2715 sctx->b.ws->buffer_map(sctx->border_color_table->cs_buf,
2716 sctx->b.rings.gfx.cs,
2717 PIPE_TRANSFER_WRITE |
2718 PIPE_TRANSFER_UNSYNCHRONIZED);
2719 }
2720
2721 for (j = 0; j < 4; j++) {
2722 border_color_table[4 * sctx->border_color_offset + j] =
2723 util_le32_to_cpu(rstates[i]->border_color[j]);
2724 }
2725
2726 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2727 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(sctx->border_color_offset++);
2728 }
2729
2730 for (j = 0; j < Elements(rstates[i]->val); ++j) {
2731 si_pm4_sh_data_add(pm4, rstates[i] ? rstates[i]->val[j] : 0);
2732 }
2733 }
2734 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_SAMPLER);
2735
2736 if (border_color_table) {
2737 uint64_t va_offset =
2738 r600_resource_va(&sctx->screen->b.b,
2739 (void*)sctx->border_color_table);
2740
2741 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2742 if (sctx->b.chip_class >= CIK)
2743 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
2744 sctx->b.ws->buffer_unmap(sctx->border_color_table->cs_buf);
2745 si_pm4_add_bo(pm4, sctx->border_color_table, RADEON_USAGE_READ,
2746 RADEON_PRIO_SHADER_DATA);
2747 }
2748
2749 memcpy(samplers->samplers, states, sizeof(void*) * count);
2750
2751 out:
2752 samplers->n_samplers = count;
2753 }
2754
2755 static void si_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2756 {
2757 struct si_context *sctx = (struct si_context *)ctx;
2758 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
2759
2760 si_set_sampler_states(sctx, pm4, count, states,
2761 &sctx->samplers[PIPE_SHADER_VERTEX],
2762 R_00B130_SPI_SHADER_USER_DATA_VS_0);
2763 #if HAVE_LLVM >= 0x0305
2764 si_set_sampler_states(sctx, pm4, count, states,
2765 &sctx->samplers[PIPE_SHADER_VERTEX],
2766 R_00B330_SPI_SHADER_USER_DATA_ES_0);
2767 #endif
2768 si_pm4_set_state(sctx, vs_sampler, pm4);
2769 }
2770
2771 static void si_bind_gs_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2772 {
2773 struct si_context *sctx = (struct si_context *)ctx;
2774 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
2775
2776 si_set_sampler_states(sctx, pm4, count, states,
2777 &sctx->samplers[PIPE_SHADER_GEOMETRY],
2778 R_00B230_SPI_SHADER_USER_DATA_GS_0);
2779 si_pm4_set_state(sctx, gs_sampler, pm4);
2780 }
2781
2782 static void si_bind_ps_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2783 {
2784 struct si_context *sctx = (struct si_context *)ctx;
2785 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
2786
2787 si_set_sampler_states(sctx, pm4, count, states,
2788 &sctx->samplers[PIPE_SHADER_FRAGMENT],
2789 R_00B030_SPI_SHADER_USER_DATA_PS_0);
2790 si_pm4_set_state(sctx, ps_sampler, pm4);
2791 }
2792
2793
2794 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
2795 unsigned start, unsigned count,
2796 void **states)
2797 {
2798 assert(start == 0);
2799
2800 switch (shader) {
2801 case PIPE_SHADER_VERTEX:
2802 si_bind_vs_sampler_states(ctx, count, states);
2803 break;
2804 case PIPE_SHADER_GEOMETRY:
2805 si_bind_gs_sampler_states(ctx, count, states);
2806 break;
2807 case PIPE_SHADER_FRAGMENT:
2808 si_bind_ps_sampler_states(ctx, count, states);
2809 break;
2810 default:
2811 ;
2812 }
2813 }
2814
2815
2816
2817 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2818 {
2819 struct si_context *sctx = (struct si_context *)ctx;
2820 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
2821 uint16_t mask = sample_mask;
2822
2823 if (pm4 == NULL)
2824 return;
2825
2826 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16));
2827 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16));
2828
2829 si_pm4_set_state(sctx, sample_mask, pm4);
2830 }
2831
2832 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2833 {
2834 free(state);
2835 }
2836
2837 /*
2838 * Vertex elements & buffers
2839 */
2840
2841 static void *si_create_vertex_elements(struct pipe_context *ctx,
2842 unsigned count,
2843 const struct pipe_vertex_element *elements)
2844 {
2845 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2846 int i;
2847
2848 assert(count < PIPE_MAX_ATTRIBS);
2849 if (!v)
2850 return NULL;
2851
2852 v->count = count;
2853 for (i = 0; i < count; ++i) {
2854 const struct util_format_description *desc;
2855 unsigned data_format, num_format;
2856 int first_non_void;
2857
2858 desc = util_format_description(elements[i].src_format);
2859 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2860 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2861 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2862
2863 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2864 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2865 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2866 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2867 S_008F0C_NUM_FORMAT(num_format) |
2868 S_008F0C_DATA_FORMAT(data_format);
2869 }
2870 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2871
2872 return v;
2873 }
2874
2875 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2876 {
2877 struct si_context *sctx = (struct si_context *)ctx;
2878 struct si_vertex_element *v = (struct si_vertex_element*)state;
2879
2880 sctx->vertex_elements = v;
2881 }
2882
2883 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2884 {
2885 struct si_context *sctx = (struct si_context *)ctx;
2886
2887 if (sctx->vertex_elements == state)
2888 sctx->vertex_elements = NULL;
2889 FREE(state);
2890 }
2891
2892 static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned start_slot, unsigned count,
2893 const struct pipe_vertex_buffer *buffers)
2894 {
2895 struct si_context *sctx = (struct si_context *)ctx;
2896
2897 util_set_vertex_buffers_count(sctx->vertex_buffer, &sctx->nr_vertex_buffers, buffers, start_slot, count);
2898 }
2899
2900 static void si_set_index_buffer(struct pipe_context *ctx,
2901 const struct pipe_index_buffer *ib)
2902 {
2903 struct si_context *sctx = (struct si_context *)ctx;
2904
2905 if (ib) {
2906 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
2907 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
2908 } else {
2909 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
2910 }
2911 }
2912
2913 /*
2914 * Misc
2915 */
2916 static void si_set_polygon_stipple(struct pipe_context *ctx,
2917 const struct pipe_poly_stipple *state)
2918 {
2919 }
2920
2921 static void si_texture_barrier(struct pipe_context *ctx)
2922 {
2923 struct si_context *sctx = (struct si_context *)ctx;
2924
2925 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
2926 R600_CONTEXT_FLUSH_AND_INV_CB;
2927 }
2928
2929 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
2930 {
2931 struct pipe_blend_state blend;
2932
2933 memset(&blend, 0, sizeof(blend));
2934 blend.independent_blend_enable = true;
2935 blend.rt[0].colormask = 0xf;
2936 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
2937 }
2938
2939 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
2940 {
2941 /* XXX Turn this into a proper state. Right now the queries are
2942 * enabled in draw_vbo, which snoops r600_common_context to see
2943 * if any occlusion queries are active. */
2944 }
2945
2946 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
2947 bool include_draw_vbo)
2948 {
2949 si_need_cs_space((struct si_context*)ctx, num_dw, include_draw_vbo);
2950 }
2951
2952 void si_init_state_functions(struct si_context *sctx)
2953 {
2954 int i;
2955
2956 si_init_atom(&sctx->framebuffer.atom, &sctx->atoms.framebuffer, si_emit_framebuffer_state, 0);
2957
2958 sctx->b.b.create_blend_state = si_create_blend_state;
2959 sctx->b.b.bind_blend_state = si_bind_blend_state;
2960 sctx->b.b.delete_blend_state = si_delete_blend_state;
2961 sctx->b.b.set_blend_color = si_set_blend_color;
2962
2963 sctx->b.b.create_rasterizer_state = si_create_rs_state;
2964 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
2965 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
2966
2967 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
2968 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
2969 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
2970
2971 for (i = 0; i < 8; i++) {
2972 sctx->custom_dsa_flush_depth_stencil[i] = si_create_db_flush_dsa(sctx, true, true, i);
2973 sctx->custom_dsa_flush_depth[i] = si_create_db_flush_dsa(sctx, true, false, i);
2974 sctx->custom_dsa_flush_stencil[i] = si_create_db_flush_dsa(sctx, false, true, i);
2975 }
2976 sctx->custom_dsa_flush_inplace = si_create_db_flush_dsa(sctx, false, false, 0);
2977 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
2978 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
2979 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
2980
2981 sctx->b.b.set_clip_state = si_set_clip_state;
2982 sctx->b.b.set_scissor_states = si_set_scissor_states;
2983 sctx->b.b.set_viewport_states = si_set_viewport_states;
2984 sctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref;
2985
2986 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
2987 sctx->b.b.get_sample_position = cayman_get_sample_position;
2988
2989 sctx->b.b.create_vs_state = si_create_vs_state;
2990 sctx->b.b.create_fs_state = si_create_fs_state;
2991 sctx->b.b.bind_vs_state = si_bind_vs_shader;
2992 sctx->b.b.bind_fs_state = si_bind_ps_shader;
2993 sctx->b.b.delete_vs_state = si_delete_vs_shader;
2994 sctx->b.b.delete_fs_state = si_delete_ps_shader;
2995 #if HAVE_LLVM >= 0x0305
2996 sctx->b.b.create_gs_state = si_create_gs_state;
2997 sctx->b.b.bind_gs_state = si_bind_gs_shader;
2998 sctx->b.b.delete_gs_state = si_delete_gs_shader;
2999 #endif
3000
3001 sctx->b.b.create_sampler_state = si_create_sampler_state;
3002 sctx->b.b.bind_sampler_states = si_bind_sampler_states;
3003 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3004
3005 sctx->b.b.create_sampler_view = si_create_sampler_view;
3006 sctx->b.b.set_sampler_views = si_set_sampler_views;
3007 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3008
3009 sctx->b.b.set_sample_mask = si_set_sample_mask;
3010
3011 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3012 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3013 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3014 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3015 sctx->b.b.set_index_buffer = si_set_index_buffer;
3016
3017 sctx->b.b.texture_barrier = si_texture_barrier;
3018 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3019 sctx->b.dma_copy = si_dma_copy;
3020 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3021 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3022
3023 sctx->b.b.draw_vbo = si_draw_vbo;
3024 }
3025
3026 void si_init_config(struct si_context *sctx)
3027 {
3028 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
3029
3030 if (pm4 == NULL)
3031 return;
3032
3033 si_cmd_context_control(pm4);
3034
3035 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
3036
3037 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
3038 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
3039 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
3040 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
3041 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
3042 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
3043 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
3044 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
3045 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
3046 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
3047 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
3048 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
3049
3050 /* FIXME calculate these values somehow ??? */
3051 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, 0x80);
3052 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3053 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3054
3055 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
3056 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3057 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0);
3058 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3059
3060 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, 0);
3061 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, 0);
3062 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, 0);
3063 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT, 0);
3064
3065 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3066 if (sctx->b.chip_class == SI) {
3067 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
3068 S_028AA8_SWITCH_ON_EOP(1) |
3069 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
3070 S_028AA8_PRIMGROUP_SIZE(63));
3071 }
3072 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
3073 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3074 if (sctx->b.chip_class < CIK)
3075 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3076 S_008A14_CLIP_VTX_REORDER_ENA(1));
3077
3078 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3079 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3080
3081 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3082
3083 if (sctx->b.chip_class >= CIK) {
3084 switch (sctx->screen->b.family) {
3085 case CHIP_BONAIRE:
3086 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012);
3087 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3088 break;
3089 case CHIP_HAWAII:
3090 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x3a00161a);
3091 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x0000002e);
3092 break;
3093 case CHIP_KAVERI:
3094 /* XXX todo */
3095 case CHIP_KABINI:
3096 /* XXX todo */
3097 default:
3098 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3099 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3100 break;
3101 }
3102 } else {
3103 switch (sctx->screen->b.family) {
3104 case CHIP_TAHITI:
3105 case CHIP_PITCAIRN:
3106 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a);
3107 break;
3108 case CHIP_VERDE:
3109 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a);
3110 break;
3111 case CHIP_OLAND:
3112 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082);
3113 break;
3114 case CHIP_HAINAN:
3115 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3116 break;
3117 default:
3118 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3119 break;
3120 }
3121 }
3122
3123 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3124 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3125 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3126 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3127 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3128 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3129 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3130
3131 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3132 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3133 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
3134 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
3135 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
3136 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
3137 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
3138 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
3139 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
3140 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
3141 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
3142 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
3143 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
3144 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000);
3145 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3146 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3147 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3148 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3149 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3150 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
3151 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3152 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3153
3154 if (sctx->b.chip_class >= CIK) {
3155 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3156 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0));
3157 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3158 }
3159
3160 si_pm4_set_state(sctx, init, pm4);
3161 }