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vc4: Move all of our fixed function fragment color handling to NIR.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "util/u_format.h"
27 #include "util/u_hash.h"
28 #include "util/u_math.h"
29 #include "util/u_memory.h"
30 #include "util/ralloc.h"
31 #include "util/hash_table.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_info.h"
34 #include "tgsi/tgsi_lowering.h"
35 #include "tgsi/tgsi_parse.h"
36 #include "glsl/nir/nir.h"
37 #include "glsl/nir/nir_builder.h"
38 #include "nir/tgsi_to_nir.h"
39 #include "vc4_context.h"
40 #include "vc4_qpu.h"
41 #include "vc4_qir.h"
42 #ifdef USE_VC4_SIMULATOR
43 #include "simpenrose/simpenrose.h"
44 #endif
45
46 static struct qreg
47 ntq_get_src(struct vc4_compile *c, nir_src src, int i);
48
49 static void
50 resize_qreg_array(struct vc4_compile *c,
51 struct qreg **regs,
52 uint32_t *size,
53 uint32_t decl_size)
54 {
55 if (*size >= decl_size)
56 return;
57
58 uint32_t old_size = *size;
59 *size = MAX2(*size * 2, decl_size);
60 *regs = reralloc(c, *regs, struct qreg, *size);
61 if (!*regs) {
62 fprintf(stderr, "Malloc failure\n");
63 abort();
64 }
65
66 for (uint32_t i = old_size; i < *size; i++)
67 (*regs)[i] = c->undef;
68 }
69
70 static struct qreg
71 indirect_uniform_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
72 {
73 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
74 uint32_t offset = intr->const_index[0];
75 struct vc4_compiler_ubo_range *range = NULL;
76 unsigned i;
77 for (i = 0; i < c->num_uniform_ranges; i++) {
78 range = &c->ubo_ranges[i];
79 if (offset >= range->src_offset &&
80 offset < range->src_offset + range->size) {
81 break;
82 }
83 }
84 /* The driver-location-based offset always has to be within a declared
85 * uniform range.
86 */
87 assert(range);
88 if (!range->used) {
89 range->used = true;
90 range->dst_offset = c->next_ubo_dst_offset;
91 c->next_ubo_dst_offset += range->size;
92 c->num_ubo_ranges++;
93 };
94
95 offset -= range->src_offset;
96
97 /* Adjust for where we stored the TGSI register base. */
98 indirect_offset = qir_ADD(c, indirect_offset,
99 qir_uniform_ui(c, (range->dst_offset +
100 offset)));
101
102 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
103 indirect_offset = qir_MAX(c, indirect_offset, qir_uniform_ui(c, 0));
104 indirect_offset = qir_MIN(c, indirect_offset,
105 qir_uniform_ui(c, (range->dst_offset +
106 range->size - 4)));
107
108 qir_TEX_DIRECT(c, indirect_offset, qir_uniform(c, QUNIFORM_UBO_ADDR, 0));
109 c->num_texture_samples++;
110 return qir_TEX_RESULT(c);
111 }
112
113 nir_ssa_def *vc4_nir_get_state_uniform(struct nir_builder *b,
114 enum quniform_contents contents)
115 {
116 nir_intrinsic_instr *intr =
117 nir_intrinsic_instr_create(b->shader,
118 nir_intrinsic_load_uniform);
119 intr->const_index[0] = VC4_NIR_STATE_UNIFORM_OFFSET + contents;
120 intr->num_components = 1;
121 nir_ssa_dest_init(&intr->instr, &intr->dest, 1, NULL);
122 nir_builder_instr_insert(b, &intr->instr);
123 return &intr->dest.ssa;
124 }
125
126 nir_ssa_def *
127 vc4_nir_get_swizzled_channel(nir_builder *b, nir_ssa_def **srcs, int swiz)
128 {
129 switch (swiz) {
130 default:
131 case UTIL_FORMAT_SWIZZLE_NONE:
132 fprintf(stderr, "warning: unknown swizzle\n");
133 /* FALLTHROUGH */
134 case UTIL_FORMAT_SWIZZLE_0:
135 return nir_imm_float(b, 0.0);
136 case UTIL_FORMAT_SWIZZLE_1:
137 return nir_imm_float(b, 1.0);
138 case UTIL_FORMAT_SWIZZLE_X:
139 case UTIL_FORMAT_SWIZZLE_Y:
140 case UTIL_FORMAT_SWIZZLE_Z:
141 case UTIL_FORMAT_SWIZZLE_W:
142 return srcs[swiz];
143 }
144 }
145
146 static struct qreg *
147 ntq_init_ssa_def(struct vc4_compile *c, nir_ssa_def *def)
148 {
149 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
150 def->num_components);
151 _mesa_hash_table_insert(c->def_ht, def, qregs);
152 return qregs;
153 }
154
155 static struct qreg *
156 ntq_get_dest(struct vc4_compile *c, nir_dest *dest)
157 {
158 if (dest->is_ssa) {
159 struct qreg *qregs = ntq_init_ssa_def(c, &dest->ssa);
160 for (int i = 0; i < dest->ssa.num_components; i++)
161 qregs[i] = c->undef;
162 return qregs;
163 } else {
164 nir_register *reg = dest->reg.reg;
165 assert(dest->reg.base_offset == 0);
166 assert(reg->num_array_elems == 0);
167 struct hash_entry *entry =
168 _mesa_hash_table_search(c->def_ht, reg);
169 return entry->data;
170 }
171 }
172
173 static struct qreg
174 ntq_get_src(struct vc4_compile *c, nir_src src, int i)
175 {
176 struct hash_entry *entry;
177 if (src.is_ssa) {
178 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
179 assert(i < src.ssa->num_components);
180 } else {
181 nir_register *reg = src.reg.reg;
182 entry = _mesa_hash_table_search(c->def_ht, reg);
183 assert(reg->num_array_elems == 0);
184 assert(src.reg.base_offset == 0);
185 assert(i < reg->num_components);
186 }
187
188 struct qreg *qregs = entry->data;
189 return qregs[i];
190 }
191
192 static struct qreg
193 ntq_get_alu_src(struct vc4_compile *c, nir_alu_instr *instr,
194 unsigned src)
195 {
196 assert(util_is_power_of_two(instr->dest.write_mask));
197 unsigned chan = ffs(instr->dest.write_mask) - 1;
198 struct qreg r = ntq_get_src(c, instr->src[src].src,
199 instr->src[src].swizzle[chan]);
200
201 assert(!instr->src[src].abs);
202 assert(!instr->src[src].negate);
203
204 return r;
205 };
206
207 static struct qreg
208 get_swizzled_channel(struct vc4_compile *c,
209 struct qreg *srcs, int swiz)
210 {
211 switch (swiz) {
212 default:
213 case UTIL_FORMAT_SWIZZLE_NONE:
214 fprintf(stderr, "warning: unknown swizzle\n");
215 /* FALLTHROUGH */
216 case UTIL_FORMAT_SWIZZLE_0:
217 return qir_uniform_f(c, 0.0);
218 case UTIL_FORMAT_SWIZZLE_1:
219 return qir_uniform_f(c, 1.0);
220 case UTIL_FORMAT_SWIZZLE_X:
221 case UTIL_FORMAT_SWIZZLE_Y:
222 case UTIL_FORMAT_SWIZZLE_Z:
223 case UTIL_FORMAT_SWIZZLE_W:
224 return srcs[swiz];
225 }
226 }
227
228 static inline struct qreg
229 qir_SAT(struct vc4_compile *c, struct qreg val)
230 {
231 return qir_FMAX(c,
232 qir_FMIN(c, val, qir_uniform_f(c, 1.0)),
233 qir_uniform_f(c, 0.0));
234 }
235
236 static struct qreg
237 ntq_rcp(struct vc4_compile *c, struct qreg x)
238 {
239 struct qreg r = qir_RCP(c, x);
240
241 /* Apply a Newton-Raphson step to improve the accuracy. */
242 r = qir_FMUL(c, r, qir_FSUB(c,
243 qir_uniform_f(c, 2.0),
244 qir_FMUL(c, x, r)));
245
246 return r;
247 }
248
249 static struct qreg
250 ntq_rsq(struct vc4_compile *c, struct qreg x)
251 {
252 struct qreg r = qir_RSQ(c, x);
253
254 /* Apply a Newton-Raphson step to improve the accuracy. */
255 r = qir_FMUL(c, r, qir_FSUB(c,
256 qir_uniform_f(c, 1.5),
257 qir_FMUL(c,
258 qir_uniform_f(c, 0.5),
259 qir_FMUL(c, x,
260 qir_FMUL(c, r, r)))));
261
262 return r;
263 }
264
265 static struct qreg
266 qir_srgb_decode(struct vc4_compile *c, struct qreg srgb)
267 {
268 struct qreg low = qir_FMUL(c, srgb, qir_uniform_f(c, 1.0 / 12.92));
269 struct qreg high = qir_POW(c,
270 qir_FMUL(c,
271 qir_FADD(c,
272 srgb,
273 qir_uniform_f(c, 0.055)),
274 qir_uniform_f(c, 1.0 / 1.055)),
275 qir_uniform_f(c, 2.4));
276
277 qir_SF(c, qir_FSUB(c, srgb, qir_uniform_f(c, 0.04045)));
278 return qir_SEL_X_Y_NS(c, low, high);
279 }
280
281 static struct qreg
282 ntq_umul(struct vc4_compile *c, struct qreg src0, struct qreg src1)
283 {
284 struct qreg src0_hi = qir_SHR(c, src0,
285 qir_uniform_ui(c, 24));
286 struct qreg src1_hi = qir_SHR(c, src1,
287 qir_uniform_ui(c, 24));
288
289 struct qreg hilo = qir_MUL24(c, src0_hi, src1);
290 struct qreg lohi = qir_MUL24(c, src0, src1_hi);
291 struct qreg lolo = qir_MUL24(c, src0, src1);
292
293 return qir_ADD(c, lolo, qir_SHL(c,
294 qir_ADD(c, hilo, lohi),
295 qir_uniform_ui(c, 24)));
296 }
297
298 static void
299 ntq_emit_tex(struct vc4_compile *c, nir_tex_instr *instr)
300 {
301 struct qreg s, t, r, lod, proj, compare;
302 bool is_txb = false, is_txl = false, has_proj = false;
303 unsigned unit = instr->sampler_index;
304
305 for (unsigned i = 0; i < instr->num_srcs; i++) {
306 switch (instr->src[i].src_type) {
307 case nir_tex_src_coord:
308 s = ntq_get_src(c, instr->src[i].src, 0);
309 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D)
310 t = qir_uniform_f(c, 0.5);
311 else
312 t = ntq_get_src(c, instr->src[i].src, 1);
313 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
314 r = ntq_get_src(c, instr->src[i].src, 2);
315 break;
316 case nir_tex_src_bias:
317 lod = ntq_get_src(c, instr->src[i].src, 0);
318 is_txb = true;
319 break;
320 case nir_tex_src_lod:
321 lod = ntq_get_src(c, instr->src[i].src, 0);
322 is_txl = true;
323 break;
324 case nir_tex_src_comparitor:
325 compare = ntq_get_src(c, instr->src[i].src, 0);
326 break;
327 case nir_tex_src_projector:
328 proj = qir_RCP(c, ntq_get_src(c, instr->src[i].src, 0));
329 s = qir_FMUL(c, s, proj);
330 t = qir_FMUL(c, t, proj);
331 has_proj = true;
332 break;
333 default:
334 unreachable("unknown texture source");
335 }
336 }
337
338 struct qreg texture_u[] = {
339 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
340 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
341 qir_uniform(c, QUNIFORM_CONSTANT, 0),
342 qir_uniform(c, QUNIFORM_CONSTANT, 0),
343 };
344 uint32_t next_texture_u = 0;
345
346 /* There is no native support for GL texture rectangle coordinates, so
347 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
348 * 1]).
349 */
350 if (instr->sampler_dim == GLSL_SAMPLER_DIM_RECT) {
351 s = qir_FMUL(c, s,
352 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_X, unit));
353 t = qir_FMUL(c, t,
354 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_Y, unit));
355 }
356
357 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE || is_txl) {
358 texture_u[2] = qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2,
359 unit | (is_txl << 16));
360 }
361
362 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
363 struct qreg ma = qir_FMAXABS(c, qir_FMAXABS(c, s, t), r);
364 struct qreg rcp_ma = qir_RCP(c, ma);
365 s = qir_FMUL(c, s, rcp_ma);
366 t = qir_FMUL(c, t, rcp_ma);
367 r = qir_FMUL(c, r, rcp_ma);
368
369 qir_TEX_R(c, r, texture_u[next_texture_u++]);
370 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
371 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
372 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
373 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
374 qir_TEX_R(c, qir_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR, unit),
375 texture_u[next_texture_u++]);
376 }
377
378 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
379 s = qir_SAT(c, s);
380 }
381
382 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
383 t = qir_SAT(c, t);
384 }
385
386 qir_TEX_T(c, t, texture_u[next_texture_u++]);
387
388 if (is_txl || is_txb)
389 qir_TEX_B(c, lod, texture_u[next_texture_u++]);
390
391 qir_TEX_S(c, s, texture_u[next_texture_u++]);
392
393 c->num_texture_samples++;
394 struct qreg tex = qir_TEX_RESULT(c);
395
396 enum pipe_format format = c->key->tex[unit].format;
397
398 struct qreg unpacked[4];
399 if (util_format_is_depth_or_stencil(format)) {
400 struct qreg depthf = qir_ITOF(c, qir_SHR(c, tex,
401 qir_uniform_ui(c, 8)));
402 struct qreg normalized = qir_FMUL(c, depthf,
403 qir_uniform_f(c, 1.0f/0xffffff));
404
405 struct qreg depth_output;
406
407 struct qreg one = qir_uniform_f(c, 1.0f);
408 if (c->key->tex[unit].compare_mode) {
409 if (has_proj)
410 compare = qir_FMUL(c, compare, proj);
411
412 switch (c->key->tex[unit].compare_func) {
413 case PIPE_FUNC_NEVER:
414 depth_output = qir_uniform_f(c, 0.0f);
415 break;
416 case PIPE_FUNC_ALWAYS:
417 depth_output = one;
418 break;
419 case PIPE_FUNC_EQUAL:
420 qir_SF(c, qir_FSUB(c, compare, normalized));
421 depth_output = qir_SEL_X_0_ZS(c, one);
422 break;
423 case PIPE_FUNC_NOTEQUAL:
424 qir_SF(c, qir_FSUB(c, compare, normalized));
425 depth_output = qir_SEL_X_0_ZC(c, one);
426 break;
427 case PIPE_FUNC_GREATER:
428 qir_SF(c, qir_FSUB(c, compare, normalized));
429 depth_output = qir_SEL_X_0_NC(c, one);
430 break;
431 case PIPE_FUNC_GEQUAL:
432 qir_SF(c, qir_FSUB(c, normalized, compare));
433 depth_output = qir_SEL_X_0_NS(c, one);
434 break;
435 case PIPE_FUNC_LESS:
436 qir_SF(c, qir_FSUB(c, compare, normalized));
437 depth_output = qir_SEL_X_0_NS(c, one);
438 break;
439 case PIPE_FUNC_LEQUAL:
440 qir_SF(c, qir_FSUB(c, normalized, compare));
441 depth_output = qir_SEL_X_0_NC(c, one);
442 break;
443 }
444 } else {
445 depth_output = normalized;
446 }
447
448 for (int i = 0; i < 4; i++)
449 unpacked[i] = depth_output;
450 } else {
451 for (int i = 0; i < 4; i++)
452 unpacked[i] = qir_UNPACK_8_F(c, tex, i);
453 }
454
455 const uint8_t *format_swiz = vc4_get_format_swizzle(format);
456 struct qreg texture_output[4];
457 for (int i = 0; i < 4; i++) {
458 texture_output[i] = get_swizzled_channel(c, unpacked,
459 format_swiz[i]);
460 }
461
462 if (util_format_is_srgb(format)) {
463 for (int i = 0; i < 3; i++)
464 texture_output[i] = qir_srgb_decode(c,
465 texture_output[i]);
466 }
467
468 struct qreg *dest = ntq_get_dest(c, &instr->dest);
469 for (int i = 0; i < 4; i++) {
470 dest[i] = get_swizzled_channel(c, texture_output,
471 c->key->tex[unit].swizzle[i]);
472 }
473 }
474
475 /**
476 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
477 * to zero).
478 */
479 static struct qreg
480 ntq_ffract(struct vc4_compile *c, struct qreg src)
481 {
482 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
483 struct qreg diff = qir_FSUB(c, src, trunc);
484 qir_SF(c, diff);
485 return qir_SEL_X_Y_NS(c,
486 qir_FADD(c, diff, qir_uniform_f(c, 1.0)),
487 diff);
488 }
489
490 /**
491 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
492 * zero).
493 */
494 static struct qreg
495 ntq_ffloor(struct vc4_compile *c, struct qreg src)
496 {
497 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
498
499 /* This will be < 0 if we truncated and the truncation was of a value
500 * that was < 0 in the first place.
501 */
502 qir_SF(c, qir_FSUB(c, src, trunc));
503
504 return qir_SEL_X_Y_NS(c,
505 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)),
506 trunc);
507 }
508
509 /**
510 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
511 * zero).
512 */
513 static struct qreg
514 ntq_fceil(struct vc4_compile *c, struct qreg src)
515 {
516 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
517
518 /* This will be < 0 if we truncated and the truncation was of a value
519 * that was > 0 in the first place.
520 */
521 qir_SF(c, qir_FSUB(c, trunc, src));
522
523 return qir_SEL_X_Y_NS(c,
524 qir_FADD(c, trunc, qir_uniform_f(c, 1.0)),
525 trunc);
526 }
527
528 static struct qreg
529 ntq_fsin(struct vc4_compile *c, struct qreg src)
530 {
531 float coeff[] = {
532 -2.0 * M_PI,
533 pow(2.0 * M_PI, 3) / (3 * 2 * 1),
534 -pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
535 pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
536 -pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
537 };
538
539 struct qreg scaled_x =
540 qir_FMUL(c,
541 src,
542 qir_uniform_f(c, 1.0 / (M_PI * 2.0)));
543
544 struct qreg x = qir_FADD(c,
545 ntq_ffract(c, scaled_x),
546 qir_uniform_f(c, -0.5));
547 struct qreg x2 = qir_FMUL(c, x, x);
548 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
549 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
550 x = qir_FMUL(c, x, x2);
551 sum = qir_FADD(c,
552 sum,
553 qir_FMUL(c,
554 x,
555 qir_uniform_f(c, coeff[i])));
556 }
557 return sum;
558 }
559
560 static struct qreg
561 ntq_fcos(struct vc4_compile *c, struct qreg src)
562 {
563 float coeff[] = {
564 -1.0f,
565 pow(2.0 * M_PI, 2) / (2 * 1),
566 -pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
567 pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
568 -pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
569 pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
570 };
571
572 struct qreg scaled_x =
573 qir_FMUL(c, src,
574 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
575 struct qreg x_frac = qir_FADD(c,
576 ntq_ffract(c, scaled_x),
577 qir_uniform_f(c, -0.5));
578
579 struct qreg sum = qir_uniform_f(c, coeff[0]);
580 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
581 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
582 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
583 if (i != 1)
584 x = qir_FMUL(c, x, x2);
585
586 struct qreg mul = qir_FMUL(c,
587 x,
588 qir_uniform_f(c, coeff[i]));
589 if (i == 0)
590 sum = mul;
591 else
592 sum = qir_FADD(c, sum, mul);
593 }
594 return sum;
595 }
596
597 static struct qreg
598 ntq_fsign(struct vc4_compile *c, struct qreg src)
599 {
600 qir_SF(c, src);
601 return qir_SEL_X_Y_NC(c,
602 qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0)),
603 qir_uniform_f(c, -1.0));
604 }
605
606 static struct qreg
607 get_channel_from_vpm(struct vc4_compile *c,
608 struct qreg *vpm_reads,
609 uint8_t swiz,
610 const struct util_format_description *desc)
611 {
612 const struct util_format_channel_description *chan =
613 &desc->channel[swiz];
614 struct qreg temp;
615
616 if (swiz > UTIL_FORMAT_SWIZZLE_W)
617 return get_swizzled_channel(c, vpm_reads, swiz);
618 else if (chan->size == 32 &&
619 chan->type == UTIL_FORMAT_TYPE_FLOAT) {
620 return get_swizzled_channel(c, vpm_reads, swiz);
621 } else if (chan->size == 32 &&
622 chan->type == UTIL_FORMAT_TYPE_SIGNED) {
623 if (chan->normalized) {
624 return qir_FMUL(c,
625 qir_ITOF(c, vpm_reads[swiz]),
626 qir_uniform_f(c,
627 1.0 / 0x7fffffff));
628 } else {
629 return qir_ITOF(c, vpm_reads[swiz]);
630 }
631 } else if (chan->size == 8 &&
632 (chan->type == UTIL_FORMAT_TYPE_UNSIGNED ||
633 chan->type == UTIL_FORMAT_TYPE_SIGNED)) {
634 struct qreg vpm = vpm_reads[0];
635 if (chan->type == UTIL_FORMAT_TYPE_SIGNED) {
636 temp = qir_XOR(c, vpm, qir_uniform_ui(c, 0x80808080));
637 if (chan->normalized) {
638 return qir_FSUB(c, qir_FMUL(c,
639 qir_UNPACK_8_F(c, temp, swiz),
640 qir_uniform_f(c, 2.0)),
641 qir_uniform_f(c, 1.0));
642 } else {
643 return qir_FADD(c,
644 qir_ITOF(c,
645 qir_UNPACK_8_I(c, temp,
646 swiz)),
647 qir_uniform_f(c, -128.0));
648 }
649 } else {
650 if (chan->normalized) {
651 return qir_UNPACK_8_F(c, vpm, swiz);
652 } else {
653 return qir_ITOF(c, qir_UNPACK_8_I(c, vpm, swiz));
654 }
655 }
656 } else if (chan->size == 16 &&
657 (chan->type == UTIL_FORMAT_TYPE_UNSIGNED ||
658 chan->type == UTIL_FORMAT_TYPE_SIGNED)) {
659 struct qreg vpm = vpm_reads[swiz / 2];
660
661 /* Note that UNPACK_16F eats a half float, not ints, so we use
662 * UNPACK_16_I for all of these.
663 */
664 if (chan->type == UTIL_FORMAT_TYPE_SIGNED) {
665 temp = qir_ITOF(c, qir_UNPACK_16_I(c, vpm, swiz % 2));
666 if (chan->normalized) {
667 return qir_FMUL(c, temp,
668 qir_uniform_f(c, 1/32768.0f));
669 } else {
670 return temp;
671 }
672 } else {
673 /* UNPACK_16I sign-extends, so we have to emit ANDs. */
674 temp = vpm;
675 if (swiz == 1 || swiz == 3)
676 temp = qir_UNPACK_16_I(c, temp, 1);
677 temp = qir_AND(c, temp, qir_uniform_ui(c, 0xffff));
678 temp = qir_ITOF(c, temp);
679
680 if (chan->normalized) {
681 return qir_FMUL(c, temp,
682 qir_uniform_f(c, 1 / 65535.0));
683 } else {
684 return temp;
685 }
686 }
687 } else {
688 return c->undef;
689 }
690 }
691
692 static void
693 emit_vertex_input(struct vc4_compile *c, int attr)
694 {
695 enum pipe_format format = c->vs_key->attr_formats[attr];
696 uint32_t attr_size = util_format_get_blocksize(format);
697 struct qreg vpm_reads[4];
698
699 c->vattr_sizes[attr] = align(attr_size, 4);
700 for (int i = 0; i < align(attr_size, 4) / 4; i++) {
701 struct qreg vpm = { QFILE_VPM, attr * 4 + i };
702 vpm_reads[i] = qir_MOV(c, vpm);
703 c->num_inputs++;
704 }
705
706 bool format_warned = false;
707 const struct util_format_description *desc =
708 util_format_description(format);
709
710 for (int i = 0; i < 4; i++) {
711 uint8_t swiz = desc->swizzle[i];
712 struct qreg result = get_channel_from_vpm(c, vpm_reads,
713 swiz, desc);
714
715 if (result.file == QFILE_NULL) {
716 if (!format_warned) {
717 fprintf(stderr,
718 "vtx element %d unsupported type: %s\n",
719 attr, util_format_name(format));
720 format_warned = true;
721 }
722 result = qir_uniform_f(c, 0.0);
723 }
724 c->inputs[attr * 4 + i] = result;
725 }
726 }
727
728 static void
729 emit_fragcoord_input(struct vc4_compile *c, int attr)
730 {
731 c->inputs[attr * 4 + 0] = qir_FRAG_X(c);
732 c->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
733 c->inputs[attr * 4 + 2] =
734 qir_FMUL(c,
735 qir_ITOF(c, qir_FRAG_Z(c)),
736 qir_uniform_f(c, 1.0 / 0xffffff));
737 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
738 }
739
740 static struct qreg
741 emit_fragment_varying(struct vc4_compile *c, uint8_t semantic,
742 uint8_t index, uint8_t swizzle)
743 {
744 uint32_t i = c->num_input_semantics++;
745 struct qreg vary = {
746 QFILE_VARY,
747 i
748 };
749
750 if (c->num_input_semantics >= c->input_semantics_array_size) {
751 c->input_semantics_array_size =
752 MAX2(4, c->input_semantics_array_size * 2);
753
754 c->input_semantics = reralloc(c, c->input_semantics,
755 struct vc4_varying_semantic,
756 c->input_semantics_array_size);
757 }
758
759 c->input_semantics[i].semantic = semantic;
760 c->input_semantics[i].index = index;
761 c->input_semantics[i].swizzle = swizzle;
762
763 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
764 }
765
766 static void
767 emit_fragment_input(struct vc4_compile *c, int attr,
768 unsigned semantic_name, unsigned semantic_index)
769 {
770 for (int i = 0; i < 4; i++) {
771 c->inputs[attr * 4 + i] =
772 emit_fragment_varying(c,
773 semantic_name,
774 semantic_index,
775 i);
776 c->num_inputs++;
777 }
778 }
779
780 static void
781 add_output(struct vc4_compile *c,
782 uint32_t decl_offset,
783 uint8_t semantic_name,
784 uint8_t semantic_index,
785 uint8_t semantic_swizzle)
786 {
787 uint32_t old_array_size = c->outputs_array_size;
788 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
789 decl_offset + 1);
790
791 if (old_array_size != c->outputs_array_size) {
792 c->output_semantics = reralloc(c,
793 c->output_semantics,
794 struct vc4_varying_semantic,
795 c->outputs_array_size);
796 }
797
798 c->output_semantics[decl_offset].semantic = semantic_name;
799 c->output_semantics[decl_offset].index = semantic_index;
800 c->output_semantics[decl_offset].swizzle = semantic_swizzle;
801 }
802
803 static void
804 declare_uniform_range(struct vc4_compile *c, uint32_t start, uint32_t size)
805 {
806 unsigned array_id = c->num_uniform_ranges++;
807 if (array_id >= c->ubo_ranges_array_size) {
808 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
809 array_id + 1);
810 c->ubo_ranges = reralloc(c, c->ubo_ranges,
811 struct vc4_compiler_ubo_range,
812 c->ubo_ranges_array_size);
813 }
814
815 c->ubo_ranges[array_id].dst_offset = 0;
816 c->ubo_ranges[array_id].src_offset = start;
817 c->ubo_ranges[array_id].size = size;
818 c->ubo_ranges[array_id].used = false;
819 }
820
821 static void
822 ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
823 {
824 /* Vectors are special in that they have non-scalarized writemasks,
825 * and just take the first swizzle channel for each argument in order
826 * into each writemask channel.
827 */
828 if (instr->op == nir_op_vec2 ||
829 instr->op == nir_op_vec3 ||
830 instr->op == nir_op_vec4) {
831 struct qreg srcs[4];
832 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
833 srcs[i] = ntq_get_src(c, instr->src[i].src,
834 instr->src[i].swizzle[0]);
835 struct qreg *dest = ntq_get_dest(c, &instr->dest.dest);
836 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
837 dest[i] = srcs[i];
838 return;
839 }
840
841 if (instr->op == nir_op_pack_unorm_4x8) {
842 struct qreg result;
843 for (int i = 0; i < 4; i++) {
844 struct qreg src = ntq_get_src(c, instr->src[0].src,
845 instr->src[0].swizzle[i]);
846 if (i == 0)
847 result = qir_PACK_8888_F(c, src);
848 else
849 result = qir_PACK_8_F(c, result, src, i);
850 }
851 struct qreg *dest = ntq_get_dest(c, &instr->dest.dest);
852 *dest = result;
853 return;
854 }
855
856 if (instr->op == nir_op_unpack_unorm_4x8) {
857 struct qreg src = ntq_get_src(c, instr->src[0].src,
858 instr->src[0].swizzle[0]);
859 struct qreg *dest = ntq_get_dest(c, &instr->dest.dest);
860 for (int i = 0; i < 4; i++) {
861 if (instr->dest.write_mask & (1 << i))
862 dest[i] = qir_UNPACK_8_F(c, src, i);
863 }
864 return;
865 }
866
867 /* General case: We can just grab the one used channel per src. */
868 struct qreg src[nir_op_infos[instr->op].num_inputs];
869 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
870 src[i] = ntq_get_alu_src(c, instr, i);
871 }
872
873 /* Pick the channel to store the output in. */
874 assert(!instr->dest.saturate);
875 struct qreg *dest = ntq_get_dest(c, &instr->dest.dest);
876 assert(util_is_power_of_two(instr->dest.write_mask));
877 dest += ffs(instr->dest.write_mask) - 1;
878
879 switch (instr->op) {
880 case nir_op_fmov:
881 case nir_op_imov:
882 *dest = qir_MOV(c, src[0]);
883 break;
884 case nir_op_fmul:
885 *dest = qir_FMUL(c, src[0], src[1]);
886 break;
887 case nir_op_fadd:
888 *dest = qir_FADD(c, src[0], src[1]);
889 break;
890 case nir_op_fsub:
891 *dest = qir_FSUB(c, src[0], src[1]);
892 break;
893 case nir_op_fmin:
894 *dest = qir_FMIN(c, src[0], src[1]);
895 break;
896 case nir_op_fmax:
897 *dest = qir_FMAX(c, src[0], src[1]);
898 break;
899
900 case nir_op_f2i:
901 case nir_op_f2u:
902 *dest = qir_FTOI(c, src[0]);
903 break;
904 case nir_op_i2f:
905 case nir_op_u2f:
906 *dest = qir_ITOF(c, src[0]);
907 break;
908 case nir_op_b2f:
909 *dest = qir_AND(c, src[0], qir_uniform_f(c, 1.0));
910 break;
911 case nir_op_b2i:
912 *dest = qir_AND(c, src[0], qir_uniform_ui(c, 1));
913 break;
914 case nir_op_i2b:
915 case nir_op_f2b:
916 qir_SF(c, src[0]);
917 *dest = qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
918 break;
919
920 case nir_op_iadd:
921 *dest = qir_ADD(c, src[0], src[1]);
922 break;
923 case nir_op_ushr:
924 *dest = qir_SHR(c, src[0], src[1]);
925 break;
926 case nir_op_isub:
927 *dest = qir_SUB(c, src[0], src[1]);
928 break;
929 case nir_op_ishr:
930 *dest = qir_ASR(c, src[0], src[1]);
931 break;
932 case nir_op_ishl:
933 *dest = qir_SHL(c, src[0], src[1]);
934 break;
935 case nir_op_imin:
936 *dest = qir_MIN(c, src[0], src[1]);
937 break;
938 case nir_op_imax:
939 *dest = qir_MAX(c, src[0], src[1]);
940 break;
941 case nir_op_iand:
942 *dest = qir_AND(c, src[0], src[1]);
943 break;
944 case nir_op_ior:
945 *dest = qir_OR(c, src[0], src[1]);
946 break;
947 case nir_op_ixor:
948 *dest = qir_XOR(c, src[0], src[1]);
949 break;
950 case nir_op_inot:
951 *dest = qir_NOT(c, src[0]);
952 break;
953
954 case nir_op_imul:
955 *dest = ntq_umul(c, src[0], src[1]);
956 break;
957
958 case nir_op_seq:
959 qir_SF(c, qir_FSUB(c, src[0], src[1]));
960 *dest = qir_SEL_X_0_ZS(c, qir_uniform_f(c, 1.0));
961 break;
962 case nir_op_sne:
963 qir_SF(c, qir_FSUB(c, src[0], src[1]));
964 *dest = qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0));
965 break;
966 case nir_op_sge:
967 qir_SF(c, qir_FSUB(c, src[0], src[1]));
968 *dest = qir_SEL_X_0_NC(c, qir_uniform_f(c, 1.0));
969 break;
970 case nir_op_slt:
971 qir_SF(c, qir_FSUB(c, src[0], src[1]));
972 *dest = qir_SEL_X_0_NS(c, qir_uniform_f(c, 1.0));
973 break;
974 case nir_op_feq:
975 qir_SF(c, qir_FSUB(c, src[0], src[1]));
976 *dest = qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
977 break;
978 case nir_op_fne:
979 qir_SF(c, qir_FSUB(c, src[0], src[1]));
980 *dest = qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
981 break;
982 case nir_op_fge:
983 qir_SF(c, qir_FSUB(c, src[0], src[1]));
984 *dest = qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
985 break;
986 case nir_op_flt:
987 qir_SF(c, qir_FSUB(c, src[0], src[1]));
988 *dest = qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
989 break;
990 case nir_op_ieq:
991 qir_SF(c, qir_SUB(c, src[0], src[1]));
992 *dest = qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
993 break;
994 case nir_op_ine:
995 qir_SF(c, qir_SUB(c, src[0], src[1]));
996 *dest = qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
997 break;
998 case nir_op_ige:
999 qir_SF(c, qir_SUB(c, src[0], src[1]));
1000 *dest = qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
1001 break;
1002 case nir_op_ilt:
1003 qir_SF(c, qir_SUB(c, src[0], src[1]));
1004 *dest = qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
1005 break;
1006
1007 case nir_op_bcsel:
1008 qir_SF(c, src[0]);
1009 *dest = qir_SEL_X_Y_NS(c, src[1], src[2]);
1010 break;
1011 case nir_op_fcsel:
1012 qir_SF(c, src[0]);
1013 *dest = qir_SEL_X_Y_ZC(c, src[1], src[2]);
1014 break;
1015
1016 case nir_op_frcp:
1017 *dest = ntq_rcp(c, src[0]);
1018 break;
1019 case nir_op_frsq:
1020 *dest = ntq_rsq(c, src[0]);
1021 break;
1022 case nir_op_fexp2:
1023 *dest = qir_EXP2(c, src[0]);
1024 break;
1025 case nir_op_flog2:
1026 *dest = qir_LOG2(c, src[0]);
1027 break;
1028
1029 case nir_op_ftrunc:
1030 *dest = qir_ITOF(c, qir_FTOI(c, src[0]));
1031 break;
1032 case nir_op_fceil:
1033 *dest = ntq_fceil(c, src[0]);
1034 break;
1035 case nir_op_ffract:
1036 *dest = ntq_ffract(c, src[0]);
1037 break;
1038 case nir_op_ffloor:
1039 *dest = ntq_ffloor(c, src[0]);
1040 break;
1041
1042 case nir_op_fsin:
1043 *dest = ntq_fsin(c, src[0]);
1044 break;
1045 case nir_op_fcos:
1046 *dest = ntq_fcos(c, src[0]);
1047 break;
1048
1049 case nir_op_fsign:
1050 *dest = ntq_fsign(c, src[0]);
1051 break;
1052
1053 case nir_op_fabs:
1054 *dest = qir_FMAXABS(c, src[0], src[0]);
1055 break;
1056 case nir_op_iabs:
1057 *dest = qir_MAX(c, src[0],
1058 qir_SUB(c, qir_uniform_ui(c, 0), src[0]));
1059 break;
1060
1061 default:
1062 fprintf(stderr, "unknown NIR ALU inst: ");
1063 nir_print_instr(&instr->instr, stderr);
1064 fprintf(stderr, "\n");
1065 abort();
1066 }
1067 }
1068
1069 static void
1070 clip_distance_discard(struct vc4_compile *c)
1071 {
1072 for (int i = 0; i < PIPE_MAX_CLIP_PLANES; i++) {
1073 if (!(c->key->ucp_enables & (1 << i)))
1074 continue;
1075
1076 struct qreg dist = emit_fragment_varying(c,
1077 TGSI_SEMANTIC_CLIPDIST,
1078 i,
1079 TGSI_SWIZZLE_X);
1080
1081 qir_SF(c, dist);
1082
1083 if (c->discard.file == QFILE_NULL)
1084 c->discard = qir_uniform_ui(c, 0);
1085
1086 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_ui(c, ~0),
1087 c->discard);
1088 }
1089 }
1090
1091 static void
1092 emit_frag_end(struct vc4_compile *c)
1093 {
1094 clip_distance_discard(c);
1095
1096 struct qreg color;
1097 if (c->output_color_index != -1) {
1098 color = c->outputs[c->output_color_index];
1099 } else {
1100 color = qir_uniform_ui(c, 0);
1101 }
1102
1103 if (c->discard.file != QFILE_NULL)
1104 qir_TLB_DISCARD_SETUP(c, c->discard);
1105
1106 if (c->fs_key->stencil_enabled) {
1107 qir_TLB_STENCIL_SETUP(c, qir_uniform(c, QUNIFORM_STENCIL, 0));
1108 if (c->fs_key->stencil_twoside) {
1109 qir_TLB_STENCIL_SETUP(c, qir_uniform(c, QUNIFORM_STENCIL, 1));
1110 }
1111 if (c->fs_key->stencil_full_writemasks) {
1112 qir_TLB_STENCIL_SETUP(c, qir_uniform(c, QUNIFORM_STENCIL, 2));
1113 }
1114 }
1115
1116 if (c->fs_key->depth_enabled) {
1117 struct qreg z;
1118 if (c->output_position_index != -1) {
1119 z = qir_FTOI(c, qir_FMUL(c, c->outputs[c->output_position_index + 2],
1120 qir_uniform_f(c, 0xffffff)));
1121 } else {
1122 z = qir_FRAG_Z(c);
1123 }
1124 qir_TLB_Z_WRITE(c, z);
1125 }
1126
1127 qir_TLB_COLOR_WRITE(c, color);
1128 }
1129
1130 static void
1131 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1132 {
1133 struct qreg xyi[2];
1134
1135 for (int i = 0; i < 2; i++) {
1136 struct qreg scale =
1137 qir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1138
1139 xyi[i] = qir_FTOI(c, qir_FMUL(c,
1140 qir_FMUL(c,
1141 c->outputs[c->output_position_index + i],
1142 scale),
1143 rcp_w));
1144 }
1145
1146 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
1147 }
1148
1149 static void
1150 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1151 {
1152 struct qreg zscale = qir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1153 struct qreg zoffset = qir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1154
1155 qir_VPM_WRITE(c, qir_FADD(c, qir_FMUL(c, qir_FMUL(c,
1156 c->outputs[c->output_position_index + 2],
1157 zscale),
1158 rcp_w),
1159 zoffset));
1160 }
1161
1162 static void
1163 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1164 {
1165 qir_VPM_WRITE(c, rcp_w);
1166 }
1167
1168 static void
1169 emit_point_size_write(struct vc4_compile *c)
1170 {
1171 struct qreg point_size;
1172
1173 if (c->output_point_size_index != -1)
1174 point_size = c->outputs[c->output_point_size_index + 3];
1175 else
1176 point_size = qir_uniform_f(c, 1.0);
1177
1178 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1179 * BCM21553).
1180 */
1181 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1182
1183 qir_VPM_WRITE(c, point_size);
1184 }
1185
1186 /**
1187 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1188 *
1189 * The simulator insists that there be at least one vertex attribute, so
1190 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1191 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1192 * to consume it here.
1193 */
1194 static void
1195 emit_stub_vpm_read(struct vc4_compile *c)
1196 {
1197 if (c->num_inputs)
1198 return;
1199
1200 c->vattr_sizes[0] = 4;
1201 struct qreg vpm = { QFILE_VPM, 0 };
1202 (void)qir_MOV(c, vpm);
1203 c->num_inputs++;
1204 }
1205
1206 static void
1207 emit_ucp_clipdistance(struct vc4_compile *c)
1208 {
1209 unsigned cv;
1210 if (c->output_clipvertex_index != -1)
1211 cv = c->output_clipvertex_index;
1212 else if (c->output_position_index != -1)
1213 cv = c->output_position_index;
1214 else
1215 return;
1216
1217 for (int plane = 0; plane < PIPE_MAX_CLIP_PLANES; plane++) {
1218 if (!(c->key->ucp_enables & (1 << plane)))
1219 continue;
1220
1221 /* Pick the next outputs[] that hasn't been written to, since
1222 * there are no other program writes left to be processed at
1223 * this point. If something had been declared but not written
1224 * (like a w component), we'll just smash over the top of it.
1225 */
1226 uint32_t output_index = c->num_outputs++;
1227 add_output(c, output_index,
1228 TGSI_SEMANTIC_CLIPDIST,
1229 plane,
1230 TGSI_SWIZZLE_X);
1231
1232
1233 struct qreg dist = qir_uniform_f(c, 0.0);
1234 for (int i = 0; i < 4; i++) {
1235 struct qreg pos_chan = c->outputs[cv + i];
1236 struct qreg ucp =
1237 qir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1238 plane * 4 + i);
1239 dist = qir_FADD(c, dist, qir_FMUL(c, pos_chan, ucp));
1240 }
1241
1242 c->outputs[output_index] = dist;
1243 }
1244 }
1245
1246 static void
1247 emit_vert_end(struct vc4_compile *c,
1248 struct vc4_varying_semantic *fs_inputs,
1249 uint32_t num_fs_inputs)
1250 {
1251 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1252
1253 emit_stub_vpm_read(c);
1254 emit_ucp_clipdistance(c);
1255
1256 emit_scaled_viewport_write(c, rcp_w);
1257 emit_zs_write(c, rcp_w);
1258 emit_rcp_wc_write(c, rcp_w);
1259 if (c->vs_key->per_vertex_point_size)
1260 emit_point_size_write(c);
1261
1262 for (int i = 0; i < num_fs_inputs; i++) {
1263 struct vc4_varying_semantic *input = &fs_inputs[i];
1264 int j;
1265
1266 for (j = 0; j < c->num_outputs; j++) {
1267 struct vc4_varying_semantic *output =
1268 &c->output_semantics[j];
1269
1270 if (input->semantic == output->semantic &&
1271 input->index == output->index &&
1272 input->swizzle == output->swizzle) {
1273 qir_VPM_WRITE(c, c->outputs[j]);
1274 break;
1275 }
1276 }
1277 /* Emit padding if we didn't find a declared VS output for
1278 * this FS input.
1279 */
1280 if (j == c->num_outputs)
1281 qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));
1282 }
1283 }
1284
1285 static void
1286 emit_coord_end(struct vc4_compile *c)
1287 {
1288 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1289
1290 emit_stub_vpm_read(c);
1291
1292 for (int i = 0; i < 4; i++)
1293 qir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
1294
1295 emit_scaled_viewport_write(c, rcp_w);
1296 emit_zs_write(c, rcp_w);
1297 emit_rcp_wc_write(c, rcp_w);
1298 if (c->vs_key->per_vertex_point_size)
1299 emit_point_size_write(c);
1300 }
1301
1302 static void
1303 vc4_optimize_nir(struct nir_shader *s)
1304 {
1305 bool progress;
1306
1307 do {
1308 progress = false;
1309
1310 nir_lower_vars_to_ssa(s);
1311 nir_lower_alu_to_scalar(s);
1312
1313 progress = nir_copy_prop(s) || progress;
1314 progress = nir_opt_dce(s) || progress;
1315 progress = nir_opt_cse(s) || progress;
1316 progress = nir_opt_peephole_select(s) || progress;
1317 progress = nir_opt_algebraic(s) || progress;
1318 progress = nir_opt_constant_folding(s) || progress;
1319 progress = nir_opt_undef(s) || progress;
1320 } while (progress);
1321 }
1322
1323 static int
1324 driver_location_compare(const void *in_a, const void *in_b)
1325 {
1326 const nir_variable *const *a = in_a;
1327 const nir_variable *const *b = in_b;
1328
1329 return (*a)->data.driver_location - (*b)->data.driver_location;
1330 }
1331
1332 static void
1333 ntq_setup_inputs(struct vc4_compile *c)
1334 {
1335 unsigned num_entries = 0;
1336 foreach_list_typed(nir_variable, var, node, &c->s->inputs)
1337 num_entries++;
1338
1339 nir_variable *vars[num_entries];
1340
1341 unsigned i = 0;
1342 foreach_list_typed(nir_variable, var, node, &c->s->inputs)
1343 vars[i++] = var;
1344
1345 /* Sort the variables so that we emit the input setup in
1346 * driver_location order. This is required for VPM reads, whose data
1347 * is fetched into the VPM in driver_location (TGSI register index)
1348 * order.
1349 */
1350 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1351
1352 for (unsigned i = 0; i < num_entries; i++) {
1353 nir_variable *var = vars[i];
1354 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1355 /* XXX: map loc slots to semantics */
1356 unsigned semantic_name = var->data.location;
1357 unsigned semantic_index = var->data.index;
1358 unsigned loc = var->data.driver_location;
1359
1360 assert(array_len == 1);
1361 (void)array_len;
1362 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1363 (loc + 1) * 4);
1364
1365 if (c->stage == QSTAGE_FRAG) {
1366 if (semantic_name == TGSI_SEMANTIC_POSITION) {
1367 emit_fragcoord_input(c, loc);
1368 } else if (semantic_name == TGSI_SEMANTIC_FACE) {
1369 c->inputs[loc * 4 + 0] = qir_FRAG_REV_FLAG(c);
1370 } else if (semantic_name == TGSI_SEMANTIC_GENERIC &&
1371 (c->fs_key->point_sprite_mask &
1372 (1 << semantic_index))) {
1373 c->inputs[loc * 4 + 0] = c->point_x;
1374 c->inputs[loc * 4 + 1] = c->point_y;
1375 } else {
1376 emit_fragment_input(c, loc,
1377 semantic_name,
1378 semantic_index);
1379 }
1380 } else {
1381 emit_vertex_input(c, loc);
1382 }
1383 }
1384 }
1385
1386 static void
1387 ntq_setup_outputs(struct vc4_compile *c)
1388 {
1389 foreach_list_typed(nir_variable, var, node, &c->s->outputs) {
1390 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1391 /* XXX: map loc slots to semantics */
1392 unsigned semantic_name = var->data.location;
1393 unsigned semantic_index = var->data.index;
1394 unsigned loc = var->data.driver_location * 4;
1395
1396 assert(array_len == 1);
1397 (void)array_len;
1398
1399 /* NIR hack to pass through
1400 * TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS */
1401 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1402 semantic_index == -1)
1403 semantic_index = 0;
1404
1405 for (int i = 0; i < 4; i++) {
1406 add_output(c,
1407 loc + i,
1408 semantic_name,
1409 semantic_index,
1410 i);
1411 }
1412
1413 switch (semantic_name) {
1414 case TGSI_SEMANTIC_POSITION:
1415 c->output_position_index = loc;
1416 break;
1417 case TGSI_SEMANTIC_CLIPVERTEX:
1418 c->output_clipvertex_index = loc;
1419 break;
1420 case TGSI_SEMANTIC_COLOR:
1421 c->output_color_index = loc;
1422 break;
1423 case TGSI_SEMANTIC_PSIZE:
1424 c->output_point_size_index = loc;
1425 break;
1426 }
1427
1428 }
1429 }
1430
1431 static void
1432 ntq_setup_uniforms(struct vc4_compile *c)
1433 {
1434 foreach_list_typed(nir_variable, var, node, &c->s->uniforms) {
1435 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1436 unsigned array_elem_size = 4 * sizeof(float);
1437
1438 declare_uniform_range(c, var->data.driver_location * array_elem_size,
1439 array_len * array_elem_size);
1440
1441 }
1442 }
1443
1444 /**
1445 * Sets up the mapping from nir_register to struct qreg *.
1446 *
1447 * Each nir_register gets a struct qreg per 32-bit component being stored.
1448 */
1449 static void
1450 ntq_setup_registers(struct vc4_compile *c, struct exec_list *list)
1451 {
1452 foreach_list_typed(nir_register, nir_reg, node, list) {
1453 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1454 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1455 array_len *
1456 nir_reg->num_components);
1457
1458 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1459
1460 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1461 qregs[i] = qir_uniform_ui(c, 0);
1462 }
1463 }
1464
1465 static void
1466 ntq_emit_load_const(struct vc4_compile *c, nir_load_const_instr *instr)
1467 {
1468 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1469 for (int i = 0; i < instr->def.num_components; i++)
1470 qregs[i] = qir_uniform_ui(c, instr->value.u[i]);
1471
1472 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1473 }
1474
1475 static void
1476 ntq_emit_ssa_undef(struct vc4_compile *c, nir_ssa_undef_instr *instr)
1477 {
1478 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1479
1480 /* QIR needs there to be *some* value, so pick 0 (same as for
1481 * ntq_setup_registers().
1482 */
1483 for (int i = 0; i < instr->def.num_components; i++)
1484 qregs[i] = qir_uniform_ui(c, 0);
1485 }
1486
1487 static void
1488 ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
1489 {
1490 const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
1491 struct qreg *dest = NULL;
1492
1493 if (info->has_dest) {
1494 dest = ntq_get_dest(c, &instr->dest);
1495 }
1496
1497 switch (instr->intrinsic) {
1498 case nir_intrinsic_load_uniform:
1499 assert(instr->num_components == 1);
1500 if (instr->const_index[0] < VC4_NIR_STATE_UNIFORM_OFFSET) {
1501 *dest = qir_uniform(c, QUNIFORM_UNIFORM,
1502 instr->const_index[0]);
1503 } else {
1504 *dest = qir_uniform(c, instr->const_index[0] -
1505 VC4_NIR_STATE_UNIFORM_OFFSET,
1506 0);
1507 }
1508 break;
1509
1510 case nir_intrinsic_load_uniform_indirect:
1511 *dest = indirect_uniform_load(c, instr);
1512
1513 break;
1514
1515 case nir_intrinsic_load_input:
1516 assert(instr->num_components == 1);
1517 if (instr->const_index[0] == VC4_NIR_TLB_COLOR_READ_INPUT) {
1518 *dest = qir_TLB_COLOR_READ(c);
1519 } else {
1520 *dest = c->inputs[instr->const_index[0]];
1521 }
1522 break;
1523
1524 case nir_intrinsic_store_output:
1525 assert(instr->num_components == 1);
1526 c->outputs[instr->const_index[0]] =
1527 qir_MOV(c, ntq_get_src(c, instr->src[0], 0));
1528 c->num_outputs = MAX2(c->num_outputs, instr->const_index[0] + 1);
1529 break;
1530
1531 case nir_intrinsic_discard:
1532 c->discard = qir_uniform_ui(c, ~0);
1533 break;
1534
1535 case nir_intrinsic_discard_if:
1536 if (c->discard.file == QFILE_NULL)
1537 c->discard = qir_uniform_ui(c, 0);
1538 c->discard = qir_OR(c, c->discard,
1539 ntq_get_src(c, instr->src[0], 0));
1540 break;
1541
1542 default:
1543 fprintf(stderr, "Unknown intrinsic: ");
1544 nir_print_instr(&instr->instr, stderr);
1545 fprintf(stderr, "\n");
1546 break;
1547 }
1548 }
1549
1550 static void
1551 ntq_emit_if(struct vc4_compile *c, nir_if *if_stmt)
1552 {
1553 fprintf(stderr, "general IF statements not handled.\n");
1554 }
1555
1556 static void
1557 ntq_emit_instr(struct vc4_compile *c, nir_instr *instr)
1558 {
1559 switch (instr->type) {
1560 case nir_instr_type_alu:
1561 ntq_emit_alu(c, nir_instr_as_alu(instr));
1562 break;
1563
1564 case nir_instr_type_intrinsic:
1565 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
1566 break;
1567
1568 case nir_instr_type_load_const:
1569 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
1570 break;
1571
1572 case nir_instr_type_ssa_undef:
1573 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
1574 break;
1575
1576 case nir_instr_type_tex:
1577 ntq_emit_tex(c, nir_instr_as_tex(instr));
1578 break;
1579
1580 default:
1581 fprintf(stderr, "Unknown NIR instr type: ");
1582 nir_print_instr(instr, stderr);
1583 fprintf(stderr, "\n");
1584 abort();
1585 }
1586 }
1587
1588 static void
1589 ntq_emit_block(struct vc4_compile *c, nir_block *block)
1590 {
1591 nir_foreach_instr(block, instr) {
1592 ntq_emit_instr(c, instr);
1593 }
1594 }
1595
1596 static void
1597 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list)
1598 {
1599 foreach_list_typed(nir_cf_node, node, node, list) {
1600 switch (node->type) {
1601 /* case nir_cf_node_loop: */
1602 case nir_cf_node_block:
1603 ntq_emit_block(c, nir_cf_node_as_block(node));
1604 break;
1605
1606 case nir_cf_node_if:
1607 ntq_emit_if(c, nir_cf_node_as_if(node));
1608 break;
1609
1610 default:
1611 assert(0);
1612 }
1613 }
1614 }
1615
1616 static void
1617 ntq_emit_impl(struct vc4_compile *c, nir_function_impl *impl)
1618 {
1619 ntq_setup_registers(c, &impl->registers);
1620 ntq_emit_cf_list(c, &impl->body);
1621 }
1622
1623 static void
1624 nir_to_qir(struct vc4_compile *c)
1625 {
1626 ntq_setup_inputs(c);
1627 ntq_setup_outputs(c);
1628 ntq_setup_uniforms(c);
1629 ntq_setup_registers(c, &c->s->registers);
1630
1631 /* Find the main function and emit the body. */
1632 nir_foreach_overload(c->s, overload) {
1633 assert(strcmp(overload->function->name, "main") == 0);
1634 assert(overload->impl);
1635 ntq_emit_impl(c, overload->impl);
1636 }
1637 }
1638
1639 static const nir_shader_compiler_options nir_options = {
1640 .lower_ffma = true,
1641 .lower_flrp = true,
1642 .lower_fpow = true,
1643 .lower_fsat = true,
1644 .lower_fsqrt = true,
1645 .lower_negate = true,
1646 };
1647
1648 static bool
1649 count_nir_instrs_in_block(nir_block *block, void *state)
1650 {
1651 int *count = (int *) state;
1652 nir_foreach_instr(block, instr) {
1653 *count = *count + 1;
1654 }
1655 return true;
1656 }
1657
1658 static int
1659 count_nir_instrs(nir_shader *nir)
1660 {
1661 int count = 0;
1662 nir_foreach_overload(nir, overload) {
1663 if (!overload->impl)
1664 continue;
1665 nir_foreach_block(overload->impl, count_nir_instrs_in_block, &count);
1666 }
1667 return count;
1668 }
1669
1670 static struct vc4_compile *
1671 vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage,
1672 struct vc4_key *key)
1673 {
1674 struct vc4_compile *c = qir_compile_init();
1675
1676 c->stage = stage;
1677 c->shader_state = &key->shader_state->base;
1678 c->program_id = key->shader_state->program_id;
1679 c->variant_id = key->shader_state->compiled_variant_count++;
1680
1681 c->key = key;
1682 switch (stage) {
1683 case QSTAGE_FRAG:
1684 c->fs_key = (struct vc4_fs_key *)key;
1685 if (c->fs_key->is_points) {
1686 c->point_x = emit_fragment_varying(c, ~0, ~0, 0);
1687 c->point_y = emit_fragment_varying(c, ~0, ~0, 0);
1688 } else if (c->fs_key->is_lines) {
1689 c->line_x = emit_fragment_varying(c, ~0, ~0, 0);
1690 }
1691 break;
1692 case QSTAGE_VERT:
1693 c->vs_key = (struct vc4_vs_key *)key;
1694 break;
1695 case QSTAGE_COORD:
1696 c->vs_key = (struct vc4_vs_key *)key;
1697 break;
1698 }
1699
1700 const struct tgsi_token *tokens = key->shader_state->base.tokens;
1701 if (c->fs_key && c->fs_key->light_twoside) {
1702 if (!key->shader_state->twoside_tokens) {
1703 const struct tgsi_lowering_config lowering_config = {
1704 .color_two_side = true,
1705 };
1706 struct tgsi_shader_info info;
1707 key->shader_state->twoside_tokens =
1708 tgsi_transform_lowering(&lowering_config,
1709 key->shader_state->base.tokens,
1710 &info);
1711
1712 /* If no transformation occurred, then NULL is
1713 * returned and we just use our original tokens.
1714 */
1715 if (!key->shader_state->twoside_tokens) {
1716 key->shader_state->twoside_tokens =
1717 key->shader_state->base.tokens;
1718 }
1719 }
1720 tokens = key->shader_state->twoside_tokens;
1721 }
1722
1723 if (vc4_debug & VC4_DEBUG_TGSI) {
1724 fprintf(stderr, "%s prog %d/%d TGSI:\n",
1725 qir_get_stage_name(c->stage),
1726 c->program_id, c->variant_id);
1727 tgsi_dump(tokens, 0);
1728 }
1729
1730 c->s = tgsi_to_nir(tokens, &nir_options);
1731 nir_opt_global_to_local(c->s);
1732 nir_convert_to_ssa(c->s);
1733 if (stage == QSTAGE_FRAG)
1734 vc4_nir_lower_blend(c);
1735 vc4_nir_lower_io(c);
1736 nir_lower_idiv(c->s);
1737 nir_lower_load_const_to_scalar(c->s);
1738
1739 vc4_optimize_nir(c->s);
1740
1741 nir_remove_dead_variables(c->s);
1742
1743 nir_convert_from_ssa(c->s, true);
1744
1745 if (vc4_debug & VC4_DEBUG_SHADERDB) {
1746 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d NIR instructions\n",
1747 qir_get_stage_name(c->stage),
1748 c->program_id, c->variant_id,
1749 count_nir_instrs(c->s));
1750 }
1751
1752 if (vc4_debug & VC4_DEBUG_NIR) {
1753 fprintf(stderr, "%s prog %d/%d NIR:\n",
1754 qir_get_stage_name(c->stage),
1755 c->program_id, c->variant_id);
1756 nir_print_shader(c->s, stderr);
1757 }
1758
1759 nir_to_qir(c);
1760
1761 switch (stage) {
1762 case QSTAGE_FRAG:
1763 emit_frag_end(c);
1764 break;
1765 case QSTAGE_VERT:
1766 emit_vert_end(c,
1767 vc4->prog.fs->input_semantics,
1768 vc4->prog.fs->num_inputs);
1769 break;
1770 case QSTAGE_COORD:
1771 emit_coord_end(c);
1772 break;
1773 }
1774
1775 if (vc4_debug & VC4_DEBUG_QIR) {
1776 fprintf(stderr, "%s prog %d/%d pre-opt QIR:\n",
1777 qir_get_stage_name(c->stage),
1778 c->program_id, c->variant_id);
1779 qir_dump(c);
1780 }
1781
1782 qir_optimize(c);
1783 qir_lower_uniforms(c);
1784
1785 if (vc4_debug & VC4_DEBUG_QIR) {
1786 fprintf(stderr, "%s prog %d/%d QIR:\n",
1787 qir_get_stage_name(c->stage),
1788 c->program_id, c->variant_id);
1789 qir_dump(c);
1790 }
1791 qir_reorder_uniforms(c);
1792 vc4_generate_code(vc4, c);
1793
1794 if (vc4_debug & VC4_DEBUG_SHADERDB) {
1795 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d instructions\n",
1796 qir_get_stage_name(c->stage),
1797 c->program_id, c->variant_id,
1798 c->qpu_inst_count);
1799 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
1800 qir_get_stage_name(c->stage),
1801 c->program_id, c->variant_id,
1802 c->num_uniforms);
1803 }
1804
1805 ralloc_free(c->s);
1806
1807 return c;
1808 }
1809
1810 static void *
1811 vc4_shader_state_create(struct pipe_context *pctx,
1812 const struct pipe_shader_state *cso)
1813 {
1814 struct vc4_context *vc4 = vc4_context(pctx);
1815 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
1816 if (!so)
1817 return NULL;
1818
1819 so->base.tokens = tgsi_dup_tokens(cso->tokens);
1820 so->program_id = vc4->next_uncompiled_program_id++;
1821
1822 return so;
1823 }
1824
1825 static void
1826 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
1827 struct vc4_compile *c)
1828 {
1829 int count = c->num_uniforms;
1830 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
1831
1832 uinfo->count = count;
1833 uinfo->data = ralloc_array(shader, uint32_t, count);
1834 memcpy(uinfo->data, c->uniform_data,
1835 count * sizeof(*uinfo->data));
1836 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
1837 memcpy(uinfo->contents, c->uniform_contents,
1838 count * sizeof(*uinfo->contents));
1839 uinfo->num_texture_samples = c->num_texture_samples;
1840
1841 vc4_set_shader_uniform_dirty_flags(shader);
1842 }
1843
1844 static struct vc4_compiled_shader *
1845 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
1846 struct vc4_key *key)
1847 {
1848 struct hash_table *ht;
1849 uint32_t key_size;
1850 if (stage == QSTAGE_FRAG) {
1851 ht = vc4->fs_cache;
1852 key_size = sizeof(struct vc4_fs_key);
1853 } else {
1854 ht = vc4->vs_cache;
1855 key_size = sizeof(struct vc4_vs_key);
1856 }
1857
1858 struct vc4_compiled_shader *shader;
1859 struct hash_entry *entry = _mesa_hash_table_search(ht, key);
1860 if (entry)
1861 return entry->data;
1862
1863 struct vc4_compile *c = vc4_shader_ntq(vc4, stage, key);
1864 shader = rzalloc(NULL, struct vc4_compiled_shader);
1865
1866 shader->program_id = vc4->next_compiled_program_id++;
1867 if (stage == QSTAGE_FRAG) {
1868 bool input_live[c->num_input_semantics];
1869
1870 memset(input_live, 0, sizeof(input_live));
1871 list_for_each_entry(struct qinst, inst, &c->instructions, link) {
1872 for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
1873 if (inst->src[i].file == QFILE_VARY)
1874 input_live[inst->src[i].index] = true;
1875 }
1876 }
1877
1878 shader->input_semantics = ralloc_array(shader,
1879 struct vc4_varying_semantic,
1880 c->num_input_semantics);
1881
1882 for (int i = 0; i < c->num_input_semantics; i++) {
1883 struct vc4_varying_semantic *sem = &c->input_semantics[i];
1884
1885 if (!input_live[i])
1886 continue;
1887
1888 /* Skip non-VS-output inputs. */
1889 if (sem->semantic == (uint8_t)~0)
1890 continue;
1891
1892 if (sem->semantic == TGSI_SEMANTIC_COLOR ||
1893 sem->semantic == TGSI_SEMANTIC_BCOLOR) {
1894 shader->color_inputs |= (1 << shader->num_inputs);
1895 }
1896
1897 shader->input_semantics[shader->num_inputs] = *sem;
1898 shader->num_inputs++;
1899 }
1900 } else {
1901 shader->num_inputs = c->num_inputs;
1902
1903 shader->vattr_offsets[0] = 0;
1904 for (int i = 0; i < 8; i++) {
1905 shader->vattr_offsets[i + 1] =
1906 shader->vattr_offsets[i] + c->vattr_sizes[i];
1907
1908 if (c->vattr_sizes[i])
1909 shader->vattrs_live |= (1 << i);
1910 }
1911 }
1912
1913 copy_uniform_state_to_shader(shader, c);
1914 shader->bo = vc4_bo_alloc_shader(vc4->screen, c->qpu_insts,
1915 c->qpu_inst_count * sizeof(uint64_t));
1916
1917 /* Copy the compiler UBO range state to the compiled shader, dropping
1918 * out arrays that were never referenced by an indirect load.
1919 *
1920 * (Note that QIR dead code elimination of an array access still
1921 * leaves that array alive, though)
1922 */
1923 if (c->num_ubo_ranges) {
1924 shader->num_ubo_ranges = c->num_ubo_ranges;
1925 shader->ubo_ranges = ralloc_array(shader, struct vc4_ubo_range,
1926 c->num_ubo_ranges);
1927 uint32_t j = 0;
1928 for (int i = 0; i < c->num_uniform_ranges; i++) {
1929 struct vc4_compiler_ubo_range *range =
1930 &c->ubo_ranges[i];
1931 if (!range->used)
1932 continue;
1933
1934 shader->ubo_ranges[j].dst_offset = range->dst_offset;
1935 shader->ubo_ranges[j].src_offset = range->src_offset;
1936 shader->ubo_ranges[j].size = range->size;
1937 shader->ubo_size += c->ubo_ranges[i].size;
1938 j++;
1939 }
1940 }
1941 if (shader->ubo_size) {
1942 if (vc4_debug & VC4_DEBUG_SHADERDB) {
1943 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d UBO uniforms\n",
1944 qir_get_stage_name(c->stage),
1945 c->program_id, c->variant_id,
1946 shader->ubo_size / 4);
1947 }
1948 }
1949
1950 qir_compile_destroy(c);
1951
1952 struct vc4_key *dup_key;
1953 dup_key = ralloc_size(shader, key_size);
1954 memcpy(dup_key, key, key_size);
1955 _mesa_hash_table_insert(ht, dup_key, shader);
1956
1957 return shader;
1958 }
1959
1960 static void
1961 vc4_setup_shared_key(struct vc4_context *vc4, struct vc4_key *key,
1962 struct vc4_texture_stateobj *texstate)
1963 {
1964 for (int i = 0; i < texstate->num_textures; i++) {
1965 struct pipe_sampler_view *sampler = texstate->textures[i];
1966 struct pipe_sampler_state *sampler_state =
1967 texstate->samplers[i];
1968
1969 if (sampler) {
1970 key->tex[i].format = sampler->format;
1971 key->tex[i].swizzle[0] = sampler->swizzle_r;
1972 key->tex[i].swizzle[1] = sampler->swizzle_g;
1973 key->tex[i].swizzle[2] = sampler->swizzle_b;
1974 key->tex[i].swizzle[3] = sampler->swizzle_a;
1975 key->tex[i].compare_mode = sampler_state->compare_mode;
1976 key->tex[i].compare_func = sampler_state->compare_func;
1977 key->tex[i].wrap_s = sampler_state->wrap_s;
1978 key->tex[i].wrap_t = sampler_state->wrap_t;
1979 }
1980 }
1981
1982 key->ucp_enables = vc4->rasterizer->base.clip_plane_enable;
1983 }
1984
1985 static void
1986 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
1987 {
1988 struct vc4_fs_key local_key;
1989 struct vc4_fs_key *key = &local_key;
1990
1991 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
1992 VC4_DIRTY_BLEND |
1993 VC4_DIRTY_FRAMEBUFFER |
1994 VC4_DIRTY_ZSA |
1995 VC4_DIRTY_RASTERIZER |
1996 VC4_DIRTY_FRAGTEX |
1997 VC4_DIRTY_TEXSTATE |
1998 VC4_DIRTY_UNCOMPILED_FS))) {
1999 return;
2000 }
2001
2002 memset(key, 0, sizeof(*key));
2003 vc4_setup_shared_key(vc4, &key->base, &vc4->fragtex);
2004 key->base.shader_state = vc4->prog.bind_fs;
2005 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
2006 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
2007 prim_mode <= PIPE_PRIM_LINE_STRIP);
2008 key->blend = vc4->blend->rt[0];
2009 if (vc4->blend->logicop_enable) {
2010 key->logicop_func = vc4->blend->logicop_func;
2011 } else {
2012 key->logicop_func = PIPE_LOGICOP_COPY;
2013 }
2014 if (vc4->framebuffer.cbufs[0])
2015 key->color_format = vc4->framebuffer.cbufs[0]->format;
2016
2017 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
2018 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
2019 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
2020 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
2021 key->stencil_enabled);
2022 if (vc4->zsa->base.alpha.enabled) {
2023 key->alpha_test = true;
2024 key->alpha_test_func = vc4->zsa->base.alpha.func;
2025 }
2026
2027 if (key->is_points) {
2028 key->point_sprite_mask =
2029 vc4->rasterizer->base.sprite_coord_enable;
2030 key->point_coord_upper_left =
2031 (vc4->rasterizer->base.sprite_coord_mode ==
2032 PIPE_SPRITE_COORD_UPPER_LEFT);
2033 }
2034
2035 key->light_twoside = vc4->rasterizer->base.light_twoside;
2036
2037 struct vc4_compiled_shader *old_fs = vc4->prog.fs;
2038 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
2039 if (vc4->prog.fs == old_fs)
2040 return;
2041
2042 vc4->dirty |= VC4_DIRTY_COMPILED_FS;
2043 if (vc4->rasterizer->base.flatshade &&
2044 old_fs && vc4->prog.fs->color_inputs != old_fs->color_inputs) {
2045 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
2046 }
2047 }
2048
2049 static void
2050 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
2051 {
2052 struct vc4_vs_key local_key;
2053 struct vc4_vs_key *key = &local_key;
2054
2055 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2056 VC4_DIRTY_RASTERIZER |
2057 VC4_DIRTY_VERTTEX |
2058 VC4_DIRTY_TEXSTATE |
2059 VC4_DIRTY_VTXSTATE |
2060 VC4_DIRTY_UNCOMPILED_VS |
2061 VC4_DIRTY_COMPILED_FS))) {
2062 return;
2063 }
2064
2065 memset(key, 0, sizeof(*key));
2066 vc4_setup_shared_key(vc4, &key->base, &vc4->verttex);
2067 key->base.shader_state = vc4->prog.bind_vs;
2068 key->compiled_fs_id = vc4->prog.fs->program_id;
2069
2070 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
2071 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
2072
2073 key->per_vertex_point_size =
2074 (prim_mode == PIPE_PRIM_POINTS &&
2075 vc4->rasterizer->base.point_size_per_vertex);
2076
2077 struct vc4_compiled_shader *vs =
2078 vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
2079 if (vs != vc4->prog.vs) {
2080 vc4->prog.vs = vs;
2081 vc4->dirty |= VC4_DIRTY_COMPILED_VS;
2082 }
2083
2084 key->is_coord = true;
2085 struct vc4_compiled_shader *cs =
2086 vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
2087 if (cs != vc4->prog.cs) {
2088 vc4->prog.cs = cs;
2089 vc4->dirty |= VC4_DIRTY_COMPILED_CS;
2090 }
2091 }
2092
2093 void
2094 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
2095 {
2096 vc4_update_compiled_fs(vc4, prim_mode);
2097 vc4_update_compiled_vs(vc4, prim_mode);
2098 }
2099
2100 static uint32_t
2101 fs_cache_hash(const void *key)
2102 {
2103 return _mesa_hash_data(key, sizeof(struct vc4_fs_key));
2104 }
2105
2106 static uint32_t
2107 vs_cache_hash(const void *key)
2108 {
2109 return _mesa_hash_data(key, sizeof(struct vc4_vs_key));
2110 }
2111
2112 static bool
2113 fs_cache_compare(const void *key1, const void *key2)
2114 {
2115 return memcmp(key1, key2, sizeof(struct vc4_fs_key)) == 0;
2116 }
2117
2118 static bool
2119 vs_cache_compare(const void *key1, const void *key2)
2120 {
2121 return memcmp(key1, key2, sizeof(struct vc4_vs_key)) == 0;
2122 }
2123
2124 static void
2125 delete_from_cache_if_matches(struct hash_table *ht,
2126 struct hash_entry *entry,
2127 struct vc4_uncompiled_shader *so)
2128 {
2129 const struct vc4_key *key = entry->key;
2130
2131 if (key->shader_state == so) {
2132 struct vc4_compiled_shader *shader = entry->data;
2133 _mesa_hash_table_remove(ht, entry);
2134 vc4_bo_unreference(&shader->bo);
2135 ralloc_free(shader);
2136 }
2137 }
2138
2139 static void
2140 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
2141 {
2142 struct vc4_context *vc4 = vc4_context(pctx);
2143 struct vc4_uncompiled_shader *so = hwcso;
2144
2145 struct hash_entry *entry;
2146 hash_table_foreach(vc4->fs_cache, entry)
2147 delete_from_cache_if_matches(vc4->fs_cache, entry, so);
2148 hash_table_foreach(vc4->vs_cache, entry)
2149 delete_from_cache_if_matches(vc4->vs_cache, entry, so);
2150
2151 if (so->twoside_tokens != so->base.tokens)
2152 free((void *)so->twoside_tokens);
2153 free((void *)so->base.tokens);
2154 free(so);
2155 }
2156
2157 static void
2158 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2159 {
2160 struct vc4_context *vc4 = vc4_context(pctx);
2161 vc4->prog.bind_fs = hwcso;
2162 vc4->dirty |= VC4_DIRTY_UNCOMPILED_FS;
2163 }
2164
2165 static void
2166 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2167 {
2168 struct vc4_context *vc4 = vc4_context(pctx);
2169 vc4->prog.bind_vs = hwcso;
2170 vc4->dirty |= VC4_DIRTY_UNCOMPILED_VS;
2171 }
2172
2173 void
2174 vc4_program_init(struct pipe_context *pctx)
2175 {
2176 struct vc4_context *vc4 = vc4_context(pctx);
2177
2178 pctx->create_vs_state = vc4_shader_state_create;
2179 pctx->delete_vs_state = vc4_shader_state_delete;
2180
2181 pctx->create_fs_state = vc4_shader_state_create;
2182 pctx->delete_fs_state = vc4_shader_state_delete;
2183
2184 pctx->bind_fs_state = vc4_fp_state_bind;
2185 pctx->bind_vs_state = vc4_vp_state_bind;
2186
2187 vc4->fs_cache = _mesa_hash_table_create(pctx, fs_cache_hash,
2188 fs_cache_compare);
2189 vc4->vs_cache = _mesa_hash_table_create(pctx, vs_cache_hash,
2190 vs_cache_compare);
2191 }
2192
2193 void
2194 vc4_program_fini(struct pipe_context *pctx)
2195 {
2196 struct vc4_context *vc4 = vc4_context(pctx);
2197
2198 struct hash_entry *entry;
2199 hash_table_foreach(vc4->fs_cache, entry) {
2200 struct vc4_compiled_shader *shader = entry->data;
2201 vc4_bo_unreference(&shader->bo);
2202 ralloc_free(shader);
2203 _mesa_hash_table_remove(vc4->fs_cache, entry);
2204 }
2205
2206 hash_table_foreach(vc4->vs_cache, entry) {
2207 struct vc4_compiled_shader *shader = entry->data;
2208 vc4_bo_unreference(&shader->bo);
2209 ralloc_free(shader);
2210 _mesa_hash_table_remove(vc4->vs_cache, entry);
2211 }
2212 }