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vc4: Fix sin(0.0) and cos(0.0) accuracy to fix SDL rendering rotation.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "util/u_format.h"
27 #include "util/crc32.h"
28 #include "util/u_math.h"
29 #include "util/u_memory.h"
30 #include "util/ralloc.h"
31 #include "util/hash_table.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "compiler/nir/nir.h"
35 #include "compiler/nir/nir_builder.h"
36 #include "compiler/nir_types.h"
37 #include "nir/tgsi_to_nir.h"
38 #include "vc4_context.h"
39 #include "vc4_qpu.h"
40 #include "vc4_qir.h"
41 #include "mesa/state_tracker/st_glsl_types.h"
42
43 static struct qreg
44 ntq_get_src(struct vc4_compile *c, nir_src src, int i);
45 static void
46 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list);
47
48 static int
49 type_size(const struct glsl_type *type)
50 {
51 return glsl_count_attribute_slots(type, false);
52 }
53
54 static int
55 uniforms_type_size(const struct glsl_type *type)
56 {
57 return st_glsl_storage_type_size(type, false);
58 }
59
60 static void
61 resize_qreg_array(struct vc4_compile *c,
62 struct qreg **regs,
63 uint32_t *size,
64 uint32_t decl_size)
65 {
66 if (*size >= decl_size)
67 return;
68
69 uint32_t old_size = *size;
70 *size = MAX2(*size * 2, decl_size);
71 *regs = reralloc(c, *regs, struct qreg, *size);
72 if (!*regs) {
73 fprintf(stderr, "Malloc failure\n");
74 abort();
75 }
76
77 for (uint32_t i = old_size; i < *size; i++)
78 (*regs)[i] = c->undef;
79 }
80
81 static void
82 ntq_emit_thrsw(struct vc4_compile *c)
83 {
84 if (!c->fs_threaded)
85 return;
86
87 /* Always thread switch after each texture operation for now.
88 *
89 * We could do better by batching a bunch of texture fetches up and
90 * then doing one thread switch and collecting all their results
91 * afterward.
92 */
93 qir_emit_nondef(c, qir_inst(QOP_THRSW, c->undef,
94 c->undef, c->undef));
95 c->last_thrsw_at_top_level = (c->execute.file == QFILE_NULL);
96 }
97
98 static struct qreg
99 indirect_uniform_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
100 {
101 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
102 uint32_t offset = nir_intrinsic_base(intr);
103 struct vc4_compiler_ubo_range *range = NULL;
104 unsigned i;
105 for (i = 0; i < c->num_uniform_ranges; i++) {
106 range = &c->ubo_ranges[i];
107 if (offset >= range->src_offset &&
108 offset < range->src_offset + range->size) {
109 break;
110 }
111 }
112 /* The driver-location-based offset always has to be within a declared
113 * uniform range.
114 */
115 assert(range);
116 if (!range->used) {
117 range->used = true;
118 range->dst_offset = c->next_ubo_dst_offset;
119 c->next_ubo_dst_offset += range->size;
120 c->num_ubo_ranges++;
121 }
122
123 offset -= range->src_offset;
124
125 /* Adjust for where we stored the TGSI register base. */
126 indirect_offset = qir_ADD(c, indirect_offset,
127 qir_uniform_ui(c, (range->dst_offset +
128 offset)));
129
130 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
131 indirect_offset = qir_MAX(c, indirect_offset, qir_uniform_ui(c, 0));
132 indirect_offset = qir_MIN_NOIMM(c, indirect_offset,
133 qir_uniform_ui(c, (range->dst_offset +
134 range->size - 4)));
135
136 qir_ADD_dest(c, qir_reg(QFILE_TEX_S_DIRECT, 0),
137 indirect_offset,
138 qir_uniform(c, QUNIFORM_UBO_ADDR, 0));
139
140 c->num_texture_samples++;
141
142 ntq_emit_thrsw(c);
143
144 return qir_TEX_RESULT(c);
145 }
146
147 static struct qreg
148 vc4_ubo_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
149 {
150 nir_const_value *buffer_index =
151 nir_src_as_const_value(intr->src[0]);
152 assert(buffer_index->u32[0] == 1);
153 assert(c->stage == QSTAGE_FRAG);
154
155 struct qreg offset = ntq_get_src(c, intr->src[1], 0);
156
157 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
158 offset = qir_MAX(c, offset, qir_uniform_ui(c, 0));
159 offset = qir_MIN_NOIMM(c, offset,
160 qir_uniform_ui(c, c->fs_key->ubo_1_size - 4));
161
162 qir_ADD_dest(c, qir_reg(QFILE_TEX_S_DIRECT, 0),
163 offset,
164 qir_uniform(c, QUNIFORM_UBO_ADDR, buffer_index->u32[0]));
165
166 c->num_texture_samples++;
167
168 ntq_emit_thrsw(c);
169
170 return qir_TEX_RESULT(c);
171 }
172
173 nir_ssa_def *
174 vc4_nir_get_swizzled_channel(nir_builder *b, nir_ssa_def **srcs, int swiz)
175 {
176 switch (swiz) {
177 default:
178 case PIPE_SWIZZLE_NONE:
179 fprintf(stderr, "warning: unknown swizzle\n");
180 /* FALLTHROUGH */
181 case PIPE_SWIZZLE_0:
182 return nir_imm_float(b, 0.0);
183 case PIPE_SWIZZLE_1:
184 return nir_imm_float(b, 1.0);
185 case PIPE_SWIZZLE_X:
186 case PIPE_SWIZZLE_Y:
187 case PIPE_SWIZZLE_Z:
188 case PIPE_SWIZZLE_W:
189 return srcs[swiz];
190 }
191 }
192
193 static struct qreg *
194 ntq_init_ssa_def(struct vc4_compile *c, nir_ssa_def *def)
195 {
196 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
197 def->num_components);
198 _mesa_hash_table_insert(c->def_ht, def, qregs);
199 return qregs;
200 }
201
202 /**
203 * This function is responsible for getting QIR results into the associated
204 * storage for a NIR instruction.
205 *
206 * If it's a NIR SSA def, then we just set the associated hash table entry to
207 * the new result.
208 *
209 * If it's a NIR reg, then we need to update the existing qreg assigned to the
210 * NIR destination with the incoming value. To do that without introducing
211 * new MOVs, we require that the incoming qreg either be a uniform, or be
212 * SSA-defined by the previous QIR instruction in the block and rewritable by
213 * this function. That lets us sneak ahead and insert the SF flag beforehand
214 * (knowing that the previous instruction doesn't depend on flags) and rewrite
215 * its destination to be the NIR reg's destination
216 */
217 static void
218 ntq_store_dest(struct vc4_compile *c, nir_dest *dest, int chan,
219 struct qreg result)
220 {
221 struct qinst *last_inst = NULL;
222 if (!list_empty(&c->cur_block->instructions))
223 last_inst = (struct qinst *)c->cur_block->instructions.prev;
224
225 assert(result.file == QFILE_UNIF ||
226 (result.file == QFILE_TEMP &&
227 last_inst && last_inst == c->defs[result.index]));
228
229 if (dest->is_ssa) {
230 assert(chan < dest->ssa.num_components);
231
232 struct qreg *qregs;
233 struct hash_entry *entry =
234 _mesa_hash_table_search(c->def_ht, &dest->ssa);
235
236 if (entry)
237 qregs = entry->data;
238 else
239 qregs = ntq_init_ssa_def(c, &dest->ssa);
240
241 qregs[chan] = result;
242 } else {
243 nir_register *reg = dest->reg.reg;
244 assert(dest->reg.base_offset == 0);
245 assert(reg->num_array_elems == 0);
246 struct hash_entry *entry =
247 _mesa_hash_table_search(c->def_ht, reg);
248 struct qreg *qregs = entry->data;
249
250 /* Insert a MOV if the source wasn't an SSA def in the
251 * previous instruction.
252 */
253 if (result.file == QFILE_UNIF) {
254 result = qir_MOV(c, result);
255 last_inst = c->defs[result.index];
256 }
257
258 /* We know they're both temps, so just rewrite index. */
259 c->defs[last_inst->dst.index] = NULL;
260 last_inst->dst.index = qregs[chan].index;
261
262 /* If we're in control flow, then make this update of the reg
263 * conditional on the execution mask.
264 */
265 if (c->execute.file != QFILE_NULL) {
266 last_inst->dst.index = qregs[chan].index;
267
268 /* Set the flags to the current exec mask. To insert
269 * the SF, we temporarily remove our SSA instruction.
270 */
271 list_del(&last_inst->link);
272 qir_SF(c, c->execute);
273 list_addtail(&last_inst->link,
274 &c->cur_block->instructions);
275
276 last_inst->cond = QPU_COND_ZS;
277 last_inst->cond_is_exec_mask = true;
278 }
279 }
280 }
281
282 static struct qreg *
283 ntq_get_dest(struct vc4_compile *c, nir_dest *dest)
284 {
285 if (dest->is_ssa) {
286 struct qreg *qregs = ntq_init_ssa_def(c, &dest->ssa);
287 for (int i = 0; i < dest->ssa.num_components; i++)
288 qregs[i] = c->undef;
289 return qregs;
290 } else {
291 nir_register *reg = dest->reg.reg;
292 assert(dest->reg.base_offset == 0);
293 assert(reg->num_array_elems == 0);
294 struct hash_entry *entry =
295 _mesa_hash_table_search(c->def_ht, reg);
296 return entry->data;
297 }
298 }
299
300 static struct qreg
301 ntq_get_src(struct vc4_compile *c, nir_src src, int i)
302 {
303 struct hash_entry *entry;
304 if (src.is_ssa) {
305 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
306 assert(i < src.ssa->num_components);
307 } else {
308 nir_register *reg = src.reg.reg;
309 entry = _mesa_hash_table_search(c->def_ht, reg);
310 assert(reg->num_array_elems == 0);
311 assert(src.reg.base_offset == 0);
312 assert(i < reg->num_components);
313 }
314
315 struct qreg *qregs = entry->data;
316 return qregs[i];
317 }
318
319 static struct qreg
320 ntq_get_alu_src(struct vc4_compile *c, nir_alu_instr *instr,
321 unsigned src)
322 {
323 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
324 unsigned chan = ffs(instr->dest.write_mask) - 1;
325 struct qreg r = ntq_get_src(c, instr->src[src].src,
326 instr->src[src].swizzle[chan]);
327
328 assert(!instr->src[src].abs);
329 assert(!instr->src[src].negate);
330
331 return r;
332 };
333
334 static inline struct qreg
335 qir_SAT(struct vc4_compile *c, struct qreg val)
336 {
337 return qir_FMAX(c,
338 qir_FMIN(c, val, qir_uniform_f(c, 1.0)),
339 qir_uniform_f(c, 0.0));
340 }
341
342 static struct qreg
343 ntq_rcp(struct vc4_compile *c, struct qreg x)
344 {
345 struct qreg r = qir_RCP(c, x);
346
347 /* Apply a Newton-Raphson step to improve the accuracy. */
348 r = qir_FMUL(c, r, qir_FSUB(c,
349 qir_uniform_f(c, 2.0),
350 qir_FMUL(c, x, r)));
351
352 return r;
353 }
354
355 static struct qreg
356 ntq_rsq(struct vc4_compile *c, struct qreg x)
357 {
358 struct qreg r = qir_RSQ(c, x);
359
360 /* Apply a Newton-Raphson step to improve the accuracy. */
361 r = qir_FMUL(c, r, qir_FSUB(c,
362 qir_uniform_f(c, 1.5),
363 qir_FMUL(c,
364 qir_uniform_f(c, 0.5),
365 qir_FMUL(c, x,
366 qir_FMUL(c, r, r)))));
367
368 return r;
369 }
370
371 static struct qreg
372 ntq_umul(struct vc4_compile *c, struct qreg src0, struct qreg src1)
373 {
374 struct qreg src0_hi = qir_SHR(c, src0,
375 qir_uniform_ui(c, 24));
376 struct qreg src1_hi = qir_SHR(c, src1,
377 qir_uniform_ui(c, 24));
378
379 struct qreg hilo = qir_MUL24(c, src0_hi, src1);
380 struct qreg lohi = qir_MUL24(c, src0, src1_hi);
381 struct qreg lolo = qir_MUL24(c, src0, src1);
382
383 return qir_ADD(c, lolo, qir_SHL(c,
384 qir_ADD(c, hilo, lohi),
385 qir_uniform_ui(c, 24)));
386 }
387
388 static struct qreg
389 ntq_scale_depth_texture(struct vc4_compile *c, struct qreg src)
390 {
391 struct qreg depthf = qir_ITOF(c, qir_SHR(c, src,
392 qir_uniform_ui(c, 8)));
393 return qir_FMUL(c, depthf, qir_uniform_f(c, 1.0f/0xffffff));
394 }
395
396 /**
397 * Emits a lowered TXF_MS from an MSAA texture.
398 *
399 * The addressing math has been lowered in NIR, and now we just need to read
400 * it like a UBO.
401 */
402 static void
403 ntq_emit_txf(struct vc4_compile *c, nir_tex_instr *instr)
404 {
405 uint32_t tile_width = 32;
406 uint32_t tile_height = 32;
407 uint32_t tile_size = (tile_height * tile_width *
408 VC4_MAX_SAMPLES * sizeof(uint32_t));
409
410 unsigned unit = instr->texture_index;
411 uint32_t w = align(c->key->tex[unit].msaa_width, tile_width);
412 uint32_t w_tiles = w / tile_width;
413 uint32_t h = align(c->key->tex[unit].msaa_height, tile_height);
414 uint32_t h_tiles = h / tile_height;
415 uint32_t size = w_tiles * h_tiles * tile_size;
416
417 struct qreg addr;
418 assert(instr->num_srcs == 1);
419 assert(instr->src[0].src_type == nir_tex_src_coord);
420 addr = ntq_get_src(c, instr->src[0].src, 0);
421
422 /* Perform the clamping required by kernel validation. */
423 addr = qir_MAX(c, addr, qir_uniform_ui(c, 0));
424 addr = qir_MIN_NOIMM(c, addr, qir_uniform_ui(c, size - 4));
425
426 qir_ADD_dest(c, qir_reg(QFILE_TEX_S_DIRECT, 0),
427 addr, qir_uniform(c, QUNIFORM_TEXTURE_MSAA_ADDR, unit));
428
429 ntq_emit_thrsw(c);
430
431 struct qreg tex = qir_TEX_RESULT(c);
432 c->num_texture_samples++;
433
434 enum pipe_format format = c->key->tex[unit].format;
435 if (util_format_is_depth_or_stencil(format)) {
436 struct qreg scaled = ntq_scale_depth_texture(c, tex);
437 for (int i = 0; i < 4; i++)
438 ntq_store_dest(c, &instr->dest, i, qir_MOV(c, scaled));
439 } else {
440 for (int i = 0; i < 4; i++)
441 ntq_store_dest(c, &instr->dest, i,
442 qir_UNPACK_8_F(c, tex, i));
443 }
444 }
445
446 static void
447 ntq_emit_tex(struct vc4_compile *c, nir_tex_instr *instr)
448 {
449 struct qreg s, t, r, lod, compare;
450 bool is_txb = false, is_txl = false;
451 unsigned unit = instr->texture_index;
452
453 if (instr->op == nir_texop_txf) {
454 ntq_emit_txf(c, instr);
455 return;
456 }
457
458 for (unsigned i = 0; i < instr->num_srcs; i++) {
459 switch (instr->src[i].src_type) {
460 case nir_tex_src_coord:
461 s = ntq_get_src(c, instr->src[i].src, 0);
462 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D)
463 t = qir_uniform_f(c, 0.5);
464 else
465 t = ntq_get_src(c, instr->src[i].src, 1);
466 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
467 r = ntq_get_src(c, instr->src[i].src, 2);
468 break;
469 case nir_tex_src_bias:
470 lod = ntq_get_src(c, instr->src[i].src, 0);
471 is_txb = true;
472 break;
473 case nir_tex_src_lod:
474 lod = ntq_get_src(c, instr->src[i].src, 0);
475 is_txl = true;
476 break;
477 case nir_tex_src_comparator:
478 compare = ntq_get_src(c, instr->src[i].src, 0);
479 break;
480 default:
481 unreachable("unknown texture source");
482 }
483 }
484
485 if (c->stage != QSTAGE_FRAG && !is_txl) {
486 /* From the GLSL 1.20 spec:
487 *
488 * "If it is mip-mapped and running on the vertex shader,
489 * then the base texture is used."
490 */
491 is_txl = true;
492 lod = qir_uniform_ui(c, 0);
493 }
494
495 if (c->key->tex[unit].force_first_level) {
496 lod = qir_uniform(c, QUNIFORM_TEXTURE_FIRST_LEVEL, unit);
497 is_txl = true;
498 is_txb = false;
499 }
500
501 struct qreg texture_u[] = {
502 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
503 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
504 qir_uniform(c, QUNIFORM_CONSTANT, 0),
505 qir_uniform(c, QUNIFORM_CONSTANT, 0),
506 };
507 uint32_t next_texture_u = 0;
508
509 /* There is no native support for GL texture rectangle coordinates, so
510 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
511 * 1]).
512 */
513 if (instr->sampler_dim == GLSL_SAMPLER_DIM_RECT) {
514 s = qir_FMUL(c, s,
515 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_X, unit));
516 t = qir_FMUL(c, t,
517 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_Y, unit));
518 }
519
520 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE || is_txl) {
521 texture_u[2] = qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2,
522 unit | (is_txl << 16));
523 }
524
525 struct qinst *tmu;
526 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
527 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_R, 0), r);
528 tmu->src[qir_get_tex_uniform_src(tmu)] =
529 texture_u[next_texture_u++];
530 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
531 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
532 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
533 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
534 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_R, 0),
535 qir_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR,
536 unit));
537 tmu->src[qir_get_tex_uniform_src(tmu)] =
538 texture_u[next_texture_u++];
539 }
540
541 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
542 s = qir_SAT(c, s);
543 }
544
545 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
546 t = qir_SAT(c, t);
547 }
548
549 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_T, 0), t);
550 tmu->src[qir_get_tex_uniform_src(tmu)] =
551 texture_u[next_texture_u++];
552
553 if (is_txl || is_txb) {
554 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_B, 0), lod);
555 tmu->src[qir_get_tex_uniform_src(tmu)] =
556 texture_u[next_texture_u++];
557 }
558
559 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_S, 0), s);
560 tmu->src[qir_get_tex_uniform_src(tmu)] = texture_u[next_texture_u++];
561
562 c->num_texture_samples++;
563
564 ntq_emit_thrsw(c);
565
566 struct qreg tex = qir_TEX_RESULT(c);
567
568 enum pipe_format format = c->key->tex[unit].format;
569
570 struct qreg *dest = ntq_get_dest(c, &instr->dest);
571 if (util_format_is_depth_or_stencil(format)) {
572 struct qreg normalized = ntq_scale_depth_texture(c, tex);
573 struct qreg depth_output;
574
575 struct qreg u0 = qir_uniform_f(c, 0.0f);
576 struct qreg u1 = qir_uniform_f(c, 1.0f);
577 if (c->key->tex[unit].compare_mode) {
578 /* From the GL_ARB_shadow spec:
579 *
580 * "Let Dt (D subscript t) be the depth texture
581 * value, in the range [0, 1]. Let R be the
582 * interpolated texture coordinate clamped to the
583 * range [0, 1]."
584 */
585 compare = qir_SAT(c, compare);
586
587 switch (c->key->tex[unit].compare_func) {
588 case PIPE_FUNC_NEVER:
589 depth_output = qir_uniform_f(c, 0.0f);
590 break;
591 case PIPE_FUNC_ALWAYS:
592 depth_output = u1;
593 break;
594 case PIPE_FUNC_EQUAL:
595 qir_SF(c, qir_FSUB(c, compare, normalized));
596 depth_output = qir_SEL(c, QPU_COND_ZS, u1, u0);
597 break;
598 case PIPE_FUNC_NOTEQUAL:
599 qir_SF(c, qir_FSUB(c, compare, normalized));
600 depth_output = qir_SEL(c, QPU_COND_ZC, u1, u0);
601 break;
602 case PIPE_FUNC_GREATER:
603 qir_SF(c, qir_FSUB(c, compare, normalized));
604 depth_output = qir_SEL(c, QPU_COND_NC, u1, u0);
605 break;
606 case PIPE_FUNC_GEQUAL:
607 qir_SF(c, qir_FSUB(c, normalized, compare));
608 depth_output = qir_SEL(c, QPU_COND_NS, u1, u0);
609 break;
610 case PIPE_FUNC_LESS:
611 qir_SF(c, qir_FSUB(c, compare, normalized));
612 depth_output = qir_SEL(c, QPU_COND_NS, u1, u0);
613 break;
614 case PIPE_FUNC_LEQUAL:
615 qir_SF(c, qir_FSUB(c, normalized, compare));
616 depth_output = qir_SEL(c, QPU_COND_NC, u1, u0);
617 break;
618 }
619 } else {
620 depth_output = normalized;
621 }
622
623 for (int i = 0; i < 4; i++)
624 dest[i] = depth_output;
625 } else {
626 for (int i = 0; i < 4; i++)
627 dest[i] = qir_UNPACK_8_F(c, tex, i);
628 }
629 }
630
631 /**
632 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
633 * to zero).
634 */
635 static struct qreg
636 ntq_ffract(struct vc4_compile *c, struct qreg src)
637 {
638 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
639 struct qreg diff = qir_FSUB(c, src, trunc);
640 qir_SF(c, diff);
641
642 qir_FADD_dest(c, diff,
643 diff, qir_uniform_f(c, 1.0))->cond = QPU_COND_NS;
644
645 return qir_MOV(c, diff);
646 }
647
648 /**
649 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
650 * zero).
651 */
652 static struct qreg
653 ntq_ffloor(struct vc4_compile *c, struct qreg src)
654 {
655 struct qreg result = qir_ITOF(c, qir_FTOI(c, src));
656
657 /* This will be < 0 if we truncated and the truncation was of a value
658 * that was < 0 in the first place.
659 */
660 qir_SF(c, qir_FSUB(c, src, result));
661
662 struct qinst *sub = qir_FSUB_dest(c, result,
663 result, qir_uniform_f(c, 1.0));
664 sub->cond = QPU_COND_NS;
665
666 return qir_MOV(c, result);
667 }
668
669 /**
670 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
671 * zero).
672 */
673 static struct qreg
674 ntq_fceil(struct vc4_compile *c, struct qreg src)
675 {
676 struct qreg result = qir_ITOF(c, qir_FTOI(c, src));
677
678 /* This will be < 0 if we truncated and the truncation was of a value
679 * that was > 0 in the first place.
680 */
681 qir_SF(c, qir_FSUB(c, result, src));
682
683 qir_FADD_dest(c, result,
684 result, qir_uniform_f(c, 1.0))->cond = QPU_COND_NS;
685
686 return qir_MOV(c, result);
687 }
688
689 static struct qreg
690 ntq_shrink_sincos_input_range(struct vc4_compile *c, struct qreg x)
691 {
692 /* Since we're using a Taylor approximation, we want to have a small
693 * number of coefficients and take advantage of sin/cos repeating
694 * every 2pi. We keep our x as close to 0 as we can, since the series
695 * will be less accurate as |x| increases. (Also, be careful of
696 * shifting the input x value to be tricky with sin/cos relations,
697 * because getting accurate values for x==0 is very important for SDL
698 * rendering)
699 */
700 struct qreg scaled_x =
701 qir_FMUL(c, x,
702 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
703 /* Note: FTOI truncates toward 0. */
704 struct qreg x_frac = qir_FSUB(c, scaled_x,
705 qir_ITOF(c, qir_FTOI(c, scaled_x)));
706 /* Map [0.5, 1] to [-0.5, 0] */
707 qir_SF(c, qir_FSUB(c, x_frac, qir_uniform_f(c, 0.5)));
708 qir_FSUB_dest(c, x_frac, x_frac, qir_uniform_f(c, 1.0))->cond = QPU_COND_NC;
709 /* Map [-1, -0.5] to [0, 0.5] */
710 qir_SF(c, qir_FADD(c, x_frac, qir_uniform_f(c, 0.5)));
711 qir_FADD_dest(c, x_frac, x_frac, qir_uniform_f(c, 1.0))->cond = QPU_COND_NS;
712
713 return x_frac;
714 }
715
716 static struct qreg
717 ntq_fsin(struct vc4_compile *c, struct qreg src)
718 {
719 float coeff[] = {
720 2.0 * M_PI,
721 -pow(2.0 * M_PI, 3) / (3 * 2 * 1),
722 pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
723 -pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
724 pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
725 };
726
727 struct qreg x = ntq_shrink_sincos_input_range(c, src);
728 struct qreg x2 = qir_FMUL(c, x, x);
729 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
730 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
731 x = qir_FMUL(c, x, x2);
732 sum = qir_FADD(c,
733 sum,
734 qir_FMUL(c,
735 x,
736 qir_uniform_f(c, coeff[i])));
737 }
738 return sum;
739 }
740
741 static struct qreg
742 ntq_fcos(struct vc4_compile *c, struct qreg src)
743 {
744 float coeff[] = {
745 1.0f,
746 -pow(2.0 * M_PI, 2) / (2 * 1),
747 pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
748 -pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
749 pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
750 -pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
751 };
752
753 struct qreg x_frac = ntq_shrink_sincos_input_range(c, src);
754 struct qreg sum = qir_uniform_f(c, coeff[0]);
755 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
756 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
757 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
758 if (i != 1)
759 x = qir_FMUL(c, x, x2);
760
761 struct qreg mul = qir_FMUL(c,
762 x,
763 qir_uniform_f(c, coeff[i]));
764 if (i == 0)
765 sum = mul;
766 else
767 sum = qir_FADD(c, sum, mul);
768 }
769 return sum;
770 }
771
772 static struct qreg
773 ntq_fsign(struct vc4_compile *c, struct qreg src)
774 {
775 struct qreg t = qir_get_temp(c);
776
777 qir_SF(c, src);
778 qir_MOV_dest(c, t, qir_uniform_f(c, 0.0));
779 qir_MOV_dest(c, t, qir_uniform_f(c, 1.0))->cond = QPU_COND_ZC;
780 qir_MOV_dest(c, t, qir_uniform_f(c, -1.0))->cond = QPU_COND_NS;
781 return qir_MOV(c, t);
782 }
783
784 static void
785 emit_vertex_input(struct vc4_compile *c, int attr)
786 {
787 enum pipe_format format = c->vs_key->attr_formats[attr];
788 uint32_t attr_size = util_format_get_blocksize(format);
789
790 c->vattr_sizes[attr] = align(attr_size, 4);
791 for (int i = 0; i < align(attr_size, 4) / 4; i++) {
792 c->inputs[attr * 4 + i] =
793 qir_MOV(c, qir_reg(QFILE_VPM, attr * 4 + i));
794 c->num_inputs++;
795 }
796 }
797
798 static void
799 emit_fragcoord_input(struct vc4_compile *c, int attr)
800 {
801 c->inputs[attr * 4 + 0] = qir_ITOF(c, qir_reg(QFILE_FRAG_X, 0));
802 c->inputs[attr * 4 + 1] = qir_ITOF(c, qir_reg(QFILE_FRAG_Y, 0));
803 c->inputs[attr * 4 + 2] =
804 qir_FMUL(c,
805 qir_ITOF(c, qir_FRAG_Z(c)),
806 qir_uniform_f(c, 1.0 / 0xffffff));
807 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
808 }
809
810 static struct qreg
811 emit_fragment_varying(struct vc4_compile *c, gl_varying_slot slot,
812 uint8_t swizzle)
813 {
814 uint32_t i = c->num_input_slots++;
815 struct qreg vary = {
816 QFILE_VARY,
817 i
818 };
819
820 if (c->num_input_slots >= c->input_slots_array_size) {
821 c->input_slots_array_size =
822 MAX2(4, c->input_slots_array_size * 2);
823
824 c->input_slots = reralloc(c, c->input_slots,
825 struct vc4_varying_slot,
826 c->input_slots_array_size);
827 }
828
829 c->input_slots[i].slot = slot;
830 c->input_slots[i].swizzle = swizzle;
831
832 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
833 }
834
835 static void
836 emit_fragment_input(struct vc4_compile *c, int attr, gl_varying_slot slot)
837 {
838 for (int i = 0; i < 4; i++) {
839 c->inputs[attr * 4 + i] =
840 emit_fragment_varying(c, slot, i);
841 c->num_inputs++;
842 }
843 }
844
845 static void
846 add_output(struct vc4_compile *c,
847 uint32_t decl_offset,
848 uint8_t slot,
849 uint8_t swizzle)
850 {
851 uint32_t old_array_size = c->outputs_array_size;
852 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
853 decl_offset + 1);
854
855 if (old_array_size != c->outputs_array_size) {
856 c->output_slots = reralloc(c,
857 c->output_slots,
858 struct vc4_varying_slot,
859 c->outputs_array_size);
860 }
861
862 c->output_slots[decl_offset].slot = slot;
863 c->output_slots[decl_offset].swizzle = swizzle;
864 }
865
866 static void
867 declare_uniform_range(struct vc4_compile *c, uint32_t start, uint32_t size)
868 {
869 unsigned array_id = c->num_uniform_ranges++;
870 if (array_id >= c->ubo_ranges_array_size) {
871 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
872 array_id + 1);
873 c->ubo_ranges = reralloc(c, c->ubo_ranges,
874 struct vc4_compiler_ubo_range,
875 c->ubo_ranges_array_size);
876 }
877
878 c->ubo_ranges[array_id].dst_offset = 0;
879 c->ubo_ranges[array_id].src_offset = start;
880 c->ubo_ranges[array_id].size = size;
881 c->ubo_ranges[array_id].used = false;
882 }
883
884 static bool
885 ntq_src_is_only_ssa_def_user(nir_src *src)
886 {
887 if (!src->is_ssa)
888 return false;
889
890 if (!list_empty(&src->ssa->if_uses))
891 return false;
892
893 return (src->ssa->uses.next == &src->use_link &&
894 src->ssa->uses.next->next == &src->ssa->uses);
895 }
896
897 /**
898 * In general, emits a nir_pack_unorm_4x8 as a series of MOVs with the pack
899 * bit set.
900 *
901 * However, as an optimization, it tries to find the instructions generating
902 * the sources to be packed and just emit the pack flag there, if possible.
903 */
904 static void
905 ntq_emit_pack_unorm_4x8(struct vc4_compile *c, nir_alu_instr *instr)
906 {
907 struct qreg result = qir_get_temp(c);
908 struct nir_alu_instr *vec4 = NULL;
909
910 /* If packing from a vec4 op (as expected), identify it so that we can
911 * peek back at what generated its sources.
912 */
913 if (instr->src[0].src.is_ssa &&
914 instr->src[0].src.ssa->parent_instr->type == nir_instr_type_alu &&
915 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr)->op ==
916 nir_op_vec4) {
917 vec4 = nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
918 }
919
920 /* If the pack is replicating the same channel 4 times, use the 8888
921 * pack flag. This is common for blending using the alpha
922 * channel.
923 */
924 if (instr->src[0].swizzle[0] == instr->src[0].swizzle[1] &&
925 instr->src[0].swizzle[0] == instr->src[0].swizzle[2] &&
926 instr->src[0].swizzle[0] == instr->src[0].swizzle[3]) {
927 struct qreg rep = ntq_get_src(c,
928 instr->src[0].src,
929 instr->src[0].swizzle[0]);
930 ntq_store_dest(c, &instr->dest.dest, 0, qir_PACK_8888_F(c, rep));
931 return;
932 }
933
934 for (int i = 0; i < 4; i++) {
935 int swiz = instr->src[0].swizzle[i];
936 struct qreg src;
937 if (vec4) {
938 src = ntq_get_src(c, vec4->src[swiz].src,
939 vec4->src[swiz].swizzle[0]);
940 } else {
941 src = ntq_get_src(c, instr->src[0].src, swiz);
942 }
943
944 if (vec4 &&
945 ntq_src_is_only_ssa_def_user(&vec4->src[swiz].src) &&
946 src.file == QFILE_TEMP &&
947 c->defs[src.index] &&
948 qir_is_mul(c->defs[src.index]) &&
949 !c->defs[src.index]->dst.pack) {
950 struct qinst *rewrite = c->defs[src.index];
951 c->defs[src.index] = NULL;
952 rewrite->dst = result;
953 rewrite->dst.pack = QPU_PACK_MUL_8A + i;
954 continue;
955 }
956
957 qir_PACK_8_F(c, result, src, i);
958 }
959
960 ntq_store_dest(c, &instr->dest.dest, 0, qir_MOV(c, result));
961 }
962
963 /** Handles sign-extended bitfield extracts for 16 bits. */
964 static struct qreg
965 ntq_emit_ibfe(struct vc4_compile *c, struct qreg base, struct qreg offset,
966 struct qreg bits)
967 {
968 assert(bits.file == QFILE_UNIF &&
969 c->uniform_contents[bits.index] == QUNIFORM_CONSTANT &&
970 c->uniform_data[bits.index] == 16);
971
972 assert(offset.file == QFILE_UNIF &&
973 c->uniform_contents[offset.index] == QUNIFORM_CONSTANT);
974 int offset_bit = c->uniform_data[offset.index];
975 assert(offset_bit % 16 == 0);
976
977 return qir_UNPACK_16_I(c, base, offset_bit / 16);
978 }
979
980 /** Handles unsigned bitfield extracts for 8 bits. */
981 static struct qreg
982 ntq_emit_ubfe(struct vc4_compile *c, struct qreg base, struct qreg offset,
983 struct qreg bits)
984 {
985 assert(bits.file == QFILE_UNIF &&
986 c->uniform_contents[bits.index] == QUNIFORM_CONSTANT &&
987 c->uniform_data[bits.index] == 8);
988
989 assert(offset.file == QFILE_UNIF &&
990 c->uniform_contents[offset.index] == QUNIFORM_CONSTANT);
991 int offset_bit = c->uniform_data[offset.index];
992 assert(offset_bit % 8 == 0);
993
994 return qir_UNPACK_8_I(c, base, offset_bit / 8);
995 }
996
997 /**
998 * If compare_instr is a valid comparison instruction, emits the
999 * compare_instr's comparison and returns the sel_instr's return value based
1000 * on the compare_instr's result.
1001 */
1002 static bool
1003 ntq_emit_comparison(struct vc4_compile *c, struct qreg *dest,
1004 nir_alu_instr *compare_instr,
1005 nir_alu_instr *sel_instr)
1006 {
1007 enum qpu_cond cond;
1008
1009 switch (compare_instr->op) {
1010 case nir_op_feq:
1011 case nir_op_ieq:
1012 case nir_op_seq:
1013 cond = QPU_COND_ZS;
1014 break;
1015 case nir_op_fne:
1016 case nir_op_ine:
1017 case nir_op_sne:
1018 cond = QPU_COND_ZC;
1019 break;
1020 case nir_op_fge:
1021 case nir_op_ige:
1022 case nir_op_uge:
1023 case nir_op_sge:
1024 cond = QPU_COND_NC;
1025 break;
1026 case nir_op_flt:
1027 case nir_op_ilt:
1028 case nir_op_slt:
1029 cond = QPU_COND_NS;
1030 break;
1031 default:
1032 return false;
1033 }
1034
1035 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
1036 struct qreg src1 = ntq_get_alu_src(c, compare_instr, 1);
1037
1038 unsigned unsized_type =
1039 nir_alu_type_get_base_type(nir_op_infos[compare_instr->op].input_types[0]);
1040 if (unsized_type == nir_type_float)
1041 qir_SF(c, qir_FSUB(c, src0, src1));
1042 else
1043 qir_SF(c, qir_SUB(c, src0, src1));
1044
1045 switch (sel_instr->op) {
1046 case nir_op_seq:
1047 case nir_op_sne:
1048 case nir_op_sge:
1049 case nir_op_slt:
1050 *dest = qir_SEL(c, cond,
1051 qir_uniform_f(c, 1.0), qir_uniform_f(c, 0.0));
1052 break;
1053
1054 case nir_op_bcsel:
1055 *dest = qir_SEL(c, cond,
1056 ntq_get_alu_src(c, sel_instr, 1),
1057 ntq_get_alu_src(c, sel_instr, 2));
1058 break;
1059
1060 default:
1061 *dest = qir_SEL(c, cond,
1062 qir_uniform_ui(c, ~0), qir_uniform_ui(c, 0));
1063 break;
1064 }
1065
1066 /* Make the temporary for nir_store_dest(). */
1067 *dest = qir_MOV(c, *dest);
1068
1069 return true;
1070 }
1071
1072 /**
1073 * Attempts to fold a comparison generating a boolean result into the
1074 * condition code for selecting between two values, instead of comparing the
1075 * boolean result against 0 to generate the condition code.
1076 */
1077 static struct qreg ntq_emit_bcsel(struct vc4_compile *c, nir_alu_instr *instr,
1078 struct qreg *src)
1079 {
1080 if (!instr->src[0].src.is_ssa)
1081 goto out;
1082 if (instr->src[0].src.ssa->parent_instr->type != nir_instr_type_alu)
1083 goto out;
1084 nir_alu_instr *compare =
1085 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
1086 if (!compare)
1087 goto out;
1088
1089 struct qreg dest;
1090 if (ntq_emit_comparison(c, &dest, compare, instr))
1091 return dest;
1092
1093 out:
1094 qir_SF(c, src[0]);
1095 return qir_MOV(c, qir_SEL(c, QPU_COND_NS, src[1], src[2]));
1096 }
1097
1098 static struct qreg
1099 ntq_fddx(struct vc4_compile *c, struct qreg src)
1100 {
1101 /* Make sure that we have a bare temp to use for MUL rotation, so it
1102 * can be allocated to an accumulator.
1103 */
1104 if (src.pack || src.file != QFILE_TEMP)
1105 src = qir_MOV(c, src);
1106
1107 struct qreg from_left = qir_ROT_MUL(c, src, 1);
1108 struct qreg from_right = qir_ROT_MUL(c, src, 15);
1109
1110 /* Distinguish left/right pixels of the quad. */
1111 qir_SF(c, qir_AND(c, qir_reg(QFILE_QPU_ELEMENT, 0),
1112 qir_uniform_ui(c, 1)));
1113
1114 return qir_MOV(c, qir_SEL(c, QPU_COND_ZS,
1115 qir_FSUB(c, from_right, src),
1116 qir_FSUB(c, src, from_left)));
1117 }
1118
1119 static struct qreg
1120 ntq_fddy(struct vc4_compile *c, struct qreg src)
1121 {
1122 if (src.pack || src.file != QFILE_TEMP)
1123 src = qir_MOV(c, src);
1124
1125 struct qreg from_bottom = qir_ROT_MUL(c, src, 2);
1126 struct qreg from_top = qir_ROT_MUL(c, src, 14);
1127
1128 /* Distinguish top/bottom pixels of the quad. */
1129 qir_SF(c, qir_AND(c,
1130 qir_reg(QFILE_QPU_ELEMENT, 0),
1131 qir_uniform_ui(c, 2)));
1132
1133 return qir_MOV(c, qir_SEL(c, QPU_COND_ZS,
1134 qir_FSUB(c, from_top, src),
1135 qir_FSUB(c, src, from_bottom)));
1136 }
1137
1138 static void
1139 ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
1140 {
1141 /* This should always be lowered to ALU operations for VC4. */
1142 assert(!instr->dest.saturate);
1143
1144 /* Vectors are special in that they have non-scalarized writemasks,
1145 * and just take the first swizzle channel for each argument in order
1146 * into each writemask channel.
1147 */
1148 if (instr->op == nir_op_vec2 ||
1149 instr->op == nir_op_vec3 ||
1150 instr->op == nir_op_vec4) {
1151 struct qreg srcs[4];
1152 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1153 srcs[i] = ntq_get_src(c, instr->src[i].src,
1154 instr->src[i].swizzle[0]);
1155 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1156 ntq_store_dest(c, &instr->dest.dest, i,
1157 qir_MOV(c, srcs[i]));
1158 return;
1159 }
1160
1161 if (instr->op == nir_op_pack_unorm_4x8) {
1162 ntq_emit_pack_unorm_4x8(c, instr);
1163 return;
1164 }
1165
1166 if (instr->op == nir_op_unpack_unorm_4x8) {
1167 struct qreg src = ntq_get_src(c, instr->src[0].src,
1168 instr->src[0].swizzle[0]);
1169 for (int i = 0; i < 4; i++) {
1170 if (instr->dest.write_mask & (1 << i))
1171 ntq_store_dest(c, &instr->dest.dest, i,
1172 qir_UNPACK_8_F(c, src, i));
1173 }
1174 return;
1175 }
1176
1177 /* General case: We can just grab the one used channel per src. */
1178 struct qreg src[nir_op_infos[instr->op].num_inputs];
1179 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
1180 src[i] = ntq_get_alu_src(c, instr, i);
1181 }
1182
1183 struct qreg result;
1184
1185 switch (instr->op) {
1186 case nir_op_fmov:
1187 case nir_op_imov:
1188 result = qir_MOV(c, src[0]);
1189 break;
1190 case nir_op_fmul:
1191 result = qir_FMUL(c, src[0], src[1]);
1192 break;
1193 case nir_op_fadd:
1194 result = qir_FADD(c, src[0], src[1]);
1195 break;
1196 case nir_op_fsub:
1197 result = qir_FSUB(c, src[0], src[1]);
1198 break;
1199 case nir_op_fmin:
1200 result = qir_FMIN(c, src[0], src[1]);
1201 break;
1202 case nir_op_fmax:
1203 result = qir_FMAX(c, src[0], src[1]);
1204 break;
1205
1206 case nir_op_f2i32:
1207 case nir_op_f2u32:
1208 result = qir_FTOI(c, src[0]);
1209 break;
1210 case nir_op_i2f32:
1211 case nir_op_u2f32:
1212 result = qir_ITOF(c, src[0]);
1213 break;
1214 case nir_op_b2f:
1215 result = qir_AND(c, src[0], qir_uniform_f(c, 1.0));
1216 break;
1217 case nir_op_b2i:
1218 result = qir_AND(c, src[0], qir_uniform_ui(c, 1));
1219 break;
1220 case nir_op_i2b:
1221 case nir_op_f2b:
1222 qir_SF(c, src[0]);
1223 result = qir_MOV(c, qir_SEL(c, QPU_COND_ZC,
1224 qir_uniform_ui(c, ~0),
1225 qir_uniform_ui(c, 0)));
1226 break;
1227
1228 case nir_op_iadd:
1229 result = qir_ADD(c, src[0], src[1]);
1230 break;
1231 case nir_op_ushr:
1232 result = qir_SHR(c, src[0], src[1]);
1233 break;
1234 case nir_op_isub:
1235 result = qir_SUB(c, src[0], src[1]);
1236 break;
1237 case nir_op_ishr:
1238 result = qir_ASR(c, src[0], src[1]);
1239 break;
1240 case nir_op_ishl:
1241 result = qir_SHL(c, src[0], src[1]);
1242 break;
1243 case nir_op_imin:
1244 result = qir_MIN(c, src[0], src[1]);
1245 break;
1246 case nir_op_imax:
1247 result = qir_MAX(c, src[0], src[1]);
1248 break;
1249 case nir_op_iand:
1250 result = qir_AND(c, src[0], src[1]);
1251 break;
1252 case nir_op_ior:
1253 result = qir_OR(c, src[0], src[1]);
1254 break;
1255 case nir_op_ixor:
1256 result = qir_XOR(c, src[0], src[1]);
1257 break;
1258 case nir_op_inot:
1259 result = qir_NOT(c, src[0]);
1260 break;
1261
1262 case nir_op_imul:
1263 result = ntq_umul(c, src[0], src[1]);
1264 break;
1265
1266 case nir_op_seq:
1267 case nir_op_sne:
1268 case nir_op_sge:
1269 case nir_op_slt:
1270 case nir_op_feq:
1271 case nir_op_fne:
1272 case nir_op_fge:
1273 case nir_op_flt:
1274 case nir_op_ieq:
1275 case nir_op_ine:
1276 case nir_op_ige:
1277 case nir_op_uge:
1278 case nir_op_ilt:
1279 if (!ntq_emit_comparison(c, &result, instr, instr)) {
1280 fprintf(stderr, "Bad comparison instruction\n");
1281 }
1282 break;
1283
1284 case nir_op_bcsel:
1285 result = ntq_emit_bcsel(c, instr, src);
1286 break;
1287 case nir_op_fcsel:
1288 qir_SF(c, src[0]);
1289 result = qir_MOV(c, qir_SEL(c, QPU_COND_ZC, src[1], src[2]));
1290 break;
1291
1292 case nir_op_frcp:
1293 result = ntq_rcp(c, src[0]);
1294 break;
1295 case nir_op_frsq:
1296 result = ntq_rsq(c, src[0]);
1297 break;
1298 case nir_op_fexp2:
1299 result = qir_EXP2(c, src[0]);
1300 break;
1301 case nir_op_flog2:
1302 result = qir_LOG2(c, src[0]);
1303 break;
1304
1305 case nir_op_ftrunc:
1306 result = qir_ITOF(c, qir_FTOI(c, src[0]));
1307 break;
1308 case nir_op_fceil:
1309 result = ntq_fceil(c, src[0]);
1310 break;
1311 case nir_op_ffract:
1312 result = ntq_ffract(c, src[0]);
1313 break;
1314 case nir_op_ffloor:
1315 result = ntq_ffloor(c, src[0]);
1316 break;
1317
1318 case nir_op_fsin:
1319 result = ntq_fsin(c, src[0]);
1320 break;
1321 case nir_op_fcos:
1322 result = ntq_fcos(c, src[0]);
1323 break;
1324
1325 case nir_op_fsign:
1326 result = ntq_fsign(c, src[0]);
1327 break;
1328
1329 case nir_op_fabs:
1330 result = qir_FMAXABS(c, src[0], src[0]);
1331 break;
1332 case nir_op_iabs:
1333 result = qir_MAX(c, src[0],
1334 qir_SUB(c, qir_uniform_ui(c, 0), src[0]));
1335 break;
1336
1337 case nir_op_ibitfield_extract:
1338 result = ntq_emit_ibfe(c, src[0], src[1], src[2]);
1339 break;
1340
1341 case nir_op_ubitfield_extract:
1342 result = ntq_emit_ubfe(c, src[0], src[1], src[2]);
1343 break;
1344
1345 case nir_op_usadd_4x8:
1346 result = qir_V8ADDS(c, src[0], src[1]);
1347 break;
1348
1349 case nir_op_ussub_4x8:
1350 result = qir_V8SUBS(c, src[0], src[1]);
1351 break;
1352
1353 case nir_op_umin_4x8:
1354 result = qir_V8MIN(c, src[0], src[1]);
1355 break;
1356
1357 case nir_op_umax_4x8:
1358 result = qir_V8MAX(c, src[0], src[1]);
1359 break;
1360
1361 case nir_op_umul_unorm_4x8:
1362 result = qir_V8MULD(c, src[0], src[1]);
1363 break;
1364
1365 case nir_op_fddx:
1366 case nir_op_fddx_coarse:
1367 case nir_op_fddx_fine:
1368 result = ntq_fddx(c, src[0]);
1369 break;
1370
1371 case nir_op_fddy:
1372 case nir_op_fddy_coarse:
1373 case nir_op_fddy_fine:
1374 result = ntq_fddy(c, src[0]);
1375 break;
1376
1377 default:
1378 fprintf(stderr, "unknown NIR ALU inst: ");
1379 nir_print_instr(&instr->instr, stderr);
1380 fprintf(stderr, "\n");
1381 abort();
1382 }
1383
1384 /* We have a scalar result, so the instruction should only have a
1385 * single channel written to.
1386 */
1387 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
1388 ntq_store_dest(c, &instr->dest.dest,
1389 ffs(instr->dest.write_mask) - 1, result);
1390 }
1391
1392 static void
1393 emit_frag_end(struct vc4_compile *c)
1394 {
1395 struct qreg color;
1396 if (c->output_color_index != -1) {
1397 color = c->outputs[c->output_color_index];
1398 } else {
1399 color = qir_uniform_ui(c, 0);
1400 }
1401
1402 uint32_t discard_cond = QPU_COND_ALWAYS;
1403 if (c->s->info.fs.uses_discard) {
1404 qir_SF(c, c->discard);
1405 discard_cond = QPU_COND_ZS;
1406 }
1407
1408 if (c->fs_key->stencil_enabled) {
1409 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1410 qir_uniform(c, QUNIFORM_STENCIL, 0));
1411 if (c->fs_key->stencil_twoside) {
1412 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1413 qir_uniform(c, QUNIFORM_STENCIL, 1));
1414 }
1415 if (c->fs_key->stencil_full_writemasks) {
1416 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1417 qir_uniform(c, QUNIFORM_STENCIL, 2));
1418 }
1419 }
1420
1421 if (c->output_sample_mask_index != -1) {
1422 qir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1423 }
1424
1425 if (c->fs_key->depth_enabled) {
1426 if (c->output_position_index != -1) {
1427 qir_FTOI_dest(c, qir_reg(QFILE_TLB_Z_WRITE, 0),
1428 qir_FMUL(c,
1429 c->outputs[c->output_position_index],
1430 qir_uniform_f(c, 0xffffff)))->cond = discard_cond;
1431 } else {
1432 qir_MOV_dest(c, qir_reg(QFILE_TLB_Z_WRITE, 0),
1433 qir_FRAG_Z(c))->cond = discard_cond;
1434 }
1435 }
1436
1437 if (!c->msaa_per_sample_output) {
1438 qir_MOV_dest(c, qir_reg(QFILE_TLB_COLOR_WRITE, 0),
1439 color)->cond = discard_cond;
1440 } else {
1441 for (int i = 0; i < VC4_MAX_SAMPLES; i++) {
1442 qir_MOV_dest(c, qir_reg(QFILE_TLB_COLOR_WRITE_MS, 0),
1443 c->sample_colors[i])->cond = discard_cond;
1444 }
1445 }
1446 }
1447
1448 static void
1449 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1450 {
1451 struct qreg packed = qir_get_temp(c);
1452
1453 for (int i = 0; i < 2; i++) {
1454 struct qreg scale =
1455 qir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1456
1457 struct qreg packed_chan = packed;
1458 packed_chan.pack = QPU_PACK_A_16A + i;
1459
1460 qir_FTOI_dest(c, packed_chan,
1461 qir_FMUL(c,
1462 qir_FMUL(c,
1463 c->outputs[c->output_position_index + i],
1464 scale),
1465 rcp_w));
1466 }
1467
1468 qir_VPM_WRITE(c, packed);
1469 }
1470
1471 static void
1472 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1473 {
1474 struct qreg zscale = qir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1475 struct qreg zoffset = qir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1476
1477 qir_VPM_WRITE(c, qir_FADD(c, qir_FMUL(c, qir_FMUL(c,
1478 c->outputs[c->output_position_index + 2],
1479 zscale),
1480 rcp_w),
1481 zoffset));
1482 }
1483
1484 static void
1485 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1486 {
1487 qir_VPM_WRITE(c, rcp_w);
1488 }
1489
1490 static void
1491 emit_point_size_write(struct vc4_compile *c)
1492 {
1493 struct qreg point_size;
1494
1495 if (c->output_point_size_index != -1)
1496 point_size = c->outputs[c->output_point_size_index];
1497 else
1498 point_size = qir_uniform_f(c, 1.0);
1499
1500 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1501 * BCM21553).
1502 */
1503 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1504
1505 qir_VPM_WRITE(c, point_size);
1506 }
1507
1508 /**
1509 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1510 *
1511 * The simulator insists that there be at least one vertex attribute, so
1512 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1513 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1514 * to consume it here.
1515 */
1516 static void
1517 emit_stub_vpm_read(struct vc4_compile *c)
1518 {
1519 if (c->num_inputs)
1520 return;
1521
1522 c->vattr_sizes[0] = 4;
1523 (void)qir_MOV(c, qir_reg(QFILE_VPM, 0));
1524 c->num_inputs++;
1525 }
1526
1527 static void
1528 emit_vert_end(struct vc4_compile *c,
1529 struct vc4_varying_slot *fs_inputs,
1530 uint32_t num_fs_inputs)
1531 {
1532 struct qreg rcp_w = ntq_rcp(c, c->outputs[c->output_position_index + 3]);
1533
1534 emit_stub_vpm_read(c);
1535
1536 emit_scaled_viewport_write(c, rcp_w);
1537 emit_zs_write(c, rcp_w);
1538 emit_rcp_wc_write(c, rcp_w);
1539 if (c->vs_key->per_vertex_point_size)
1540 emit_point_size_write(c);
1541
1542 for (int i = 0; i < num_fs_inputs; i++) {
1543 struct vc4_varying_slot *input = &fs_inputs[i];
1544 int j;
1545
1546 for (j = 0; j < c->num_outputs; j++) {
1547 struct vc4_varying_slot *output =
1548 &c->output_slots[j];
1549
1550 if (input->slot == output->slot &&
1551 input->swizzle == output->swizzle) {
1552 qir_VPM_WRITE(c, c->outputs[j]);
1553 break;
1554 }
1555 }
1556 /* Emit padding if we didn't find a declared VS output for
1557 * this FS input.
1558 */
1559 if (j == c->num_outputs)
1560 qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));
1561 }
1562 }
1563
1564 static void
1565 emit_coord_end(struct vc4_compile *c)
1566 {
1567 struct qreg rcp_w = ntq_rcp(c, c->outputs[c->output_position_index + 3]);
1568
1569 emit_stub_vpm_read(c);
1570
1571 for (int i = 0; i < 4; i++)
1572 qir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
1573
1574 emit_scaled_viewport_write(c, rcp_w);
1575 emit_zs_write(c, rcp_w);
1576 emit_rcp_wc_write(c, rcp_w);
1577 if (c->vs_key->per_vertex_point_size)
1578 emit_point_size_write(c);
1579 }
1580
1581 static void
1582 vc4_optimize_nir(struct nir_shader *s)
1583 {
1584 bool progress;
1585
1586 do {
1587 progress = false;
1588
1589 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1590 NIR_PASS(progress, s, nir_lower_alu_to_scalar);
1591 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1592 NIR_PASS(progress, s, nir_copy_prop);
1593 NIR_PASS(progress, s, nir_opt_remove_phis);
1594 NIR_PASS(progress, s, nir_opt_dce);
1595 NIR_PASS(progress, s, nir_opt_dead_cf);
1596 NIR_PASS(progress, s, nir_opt_cse);
1597 NIR_PASS(progress, s, nir_opt_peephole_select, 8);
1598 NIR_PASS(progress, s, nir_opt_algebraic);
1599 NIR_PASS(progress, s, nir_opt_constant_folding);
1600 NIR_PASS(progress, s, nir_opt_undef);
1601 NIR_PASS(progress, s, nir_opt_loop_unroll,
1602 nir_var_shader_in |
1603 nir_var_shader_out |
1604 nir_var_local);
1605 } while (progress);
1606 }
1607
1608 static int
1609 driver_location_compare(const void *in_a, const void *in_b)
1610 {
1611 const nir_variable *const *a = in_a;
1612 const nir_variable *const *b = in_b;
1613
1614 return (*a)->data.driver_location - (*b)->data.driver_location;
1615 }
1616
1617 static void
1618 ntq_setup_inputs(struct vc4_compile *c)
1619 {
1620 unsigned num_entries = 0;
1621 nir_foreach_variable(var, &c->s->inputs)
1622 num_entries++;
1623
1624 nir_variable *vars[num_entries];
1625
1626 unsigned i = 0;
1627 nir_foreach_variable(var, &c->s->inputs)
1628 vars[i++] = var;
1629
1630 /* Sort the variables so that we emit the input setup in
1631 * driver_location order. This is required for VPM reads, whose data
1632 * is fetched into the VPM in driver_location (TGSI register index)
1633 * order.
1634 */
1635 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1636
1637 for (unsigned i = 0; i < num_entries; i++) {
1638 nir_variable *var = vars[i];
1639 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1640 unsigned loc = var->data.driver_location;
1641
1642 assert(array_len == 1);
1643 (void)array_len;
1644 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1645 (loc + 1) * 4);
1646
1647 if (c->stage == QSTAGE_FRAG) {
1648 if (var->data.location == VARYING_SLOT_POS) {
1649 emit_fragcoord_input(c, loc);
1650 } else if (var->data.location == VARYING_SLOT_PNTC ||
1651 (var->data.location >= VARYING_SLOT_VAR0 &&
1652 (c->fs_key->point_sprite_mask &
1653 (1 << (var->data.location -
1654 VARYING_SLOT_VAR0))))) {
1655 c->inputs[loc * 4 + 0] = c->point_x;
1656 c->inputs[loc * 4 + 1] = c->point_y;
1657 } else {
1658 emit_fragment_input(c, loc, var->data.location);
1659 }
1660 } else {
1661 emit_vertex_input(c, loc);
1662 }
1663 }
1664 }
1665
1666 static void
1667 ntq_setup_outputs(struct vc4_compile *c)
1668 {
1669 nir_foreach_variable(var, &c->s->outputs) {
1670 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1671 unsigned loc = var->data.driver_location * 4;
1672
1673 assert(array_len == 1);
1674 (void)array_len;
1675
1676 for (int i = 0; i < 4; i++)
1677 add_output(c, loc + i, var->data.location, i);
1678
1679 if (c->stage == QSTAGE_FRAG) {
1680 switch (var->data.location) {
1681 case FRAG_RESULT_COLOR:
1682 case FRAG_RESULT_DATA0:
1683 c->output_color_index = loc;
1684 break;
1685 case FRAG_RESULT_DEPTH:
1686 c->output_position_index = loc;
1687 break;
1688 case FRAG_RESULT_SAMPLE_MASK:
1689 c->output_sample_mask_index = loc;
1690 break;
1691 }
1692 } else {
1693 switch (var->data.location) {
1694 case VARYING_SLOT_POS:
1695 c->output_position_index = loc;
1696 break;
1697 case VARYING_SLOT_PSIZ:
1698 c->output_point_size_index = loc;
1699 break;
1700 }
1701 }
1702 }
1703 }
1704
1705 static void
1706 ntq_setup_uniforms(struct vc4_compile *c)
1707 {
1708 nir_foreach_variable(var, &c->s->uniforms) {
1709 uint32_t vec4_count = uniforms_type_size(var->type);
1710 unsigned vec4_size = 4 * sizeof(float);
1711
1712 declare_uniform_range(c, var->data.driver_location * vec4_size,
1713 vec4_count * vec4_size);
1714
1715 }
1716 }
1717
1718 /**
1719 * Sets up the mapping from nir_register to struct qreg *.
1720 *
1721 * Each nir_register gets a struct qreg per 32-bit component being stored.
1722 */
1723 static void
1724 ntq_setup_registers(struct vc4_compile *c, struct exec_list *list)
1725 {
1726 foreach_list_typed(nir_register, nir_reg, node, list) {
1727 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1728 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1729 array_len *
1730 nir_reg->num_components);
1731
1732 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1733
1734 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1735 qregs[i] = qir_get_temp(c);
1736 }
1737 }
1738
1739 static void
1740 ntq_emit_load_const(struct vc4_compile *c, nir_load_const_instr *instr)
1741 {
1742 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1743 for (int i = 0; i < instr->def.num_components; i++)
1744 qregs[i] = qir_uniform_ui(c, instr->value.u32[i]);
1745
1746 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1747 }
1748
1749 static void
1750 ntq_emit_ssa_undef(struct vc4_compile *c, nir_ssa_undef_instr *instr)
1751 {
1752 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1753
1754 /* QIR needs there to be *some* value, so pick 0 (same as for
1755 * ntq_setup_registers().
1756 */
1757 for (int i = 0; i < instr->def.num_components; i++)
1758 qregs[i] = qir_uniform_ui(c, 0);
1759 }
1760
1761 static void
1762 ntq_emit_color_read(struct vc4_compile *c, nir_intrinsic_instr *instr)
1763 {
1764 assert(nir_src_as_const_value(instr->src[0])->u32[0] == 0);
1765
1766 /* Reads of the per-sample color need to be done in
1767 * order.
1768 */
1769 int sample_index = (nir_intrinsic_base(instr) -
1770 VC4_NIR_TLB_COLOR_READ_INPUT);
1771 for (int i = 0; i <= sample_index; i++) {
1772 if (c->color_reads[i].file == QFILE_NULL) {
1773 c->color_reads[i] =
1774 qir_TLB_COLOR_READ(c);
1775 }
1776 }
1777 ntq_store_dest(c, &instr->dest, 0,
1778 qir_MOV(c, c->color_reads[sample_index]));
1779 }
1780
1781 static void
1782 ntq_emit_load_input(struct vc4_compile *c, nir_intrinsic_instr *instr)
1783 {
1784 assert(instr->num_components == 1);
1785
1786 nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]);
1787 assert(const_offset && "vc4 doesn't support indirect inputs");
1788
1789 if (c->stage == QSTAGE_FRAG &&
1790 nir_intrinsic_base(instr) >= VC4_NIR_TLB_COLOR_READ_INPUT) {
1791 ntq_emit_color_read(c, instr);
1792 return;
1793 }
1794
1795 uint32_t offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1796 int comp = nir_intrinsic_component(instr);
1797 ntq_store_dest(c, &instr->dest, 0,
1798 qir_MOV(c, c->inputs[offset * 4 + comp]));
1799 }
1800
1801 static void
1802 ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
1803 {
1804 nir_const_value *const_offset;
1805 unsigned offset;
1806
1807 switch (instr->intrinsic) {
1808 case nir_intrinsic_load_uniform:
1809 assert(instr->num_components == 1);
1810 const_offset = nir_src_as_const_value(instr->src[0]);
1811 if (const_offset) {
1812 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1813 assert(offset % 4 == 0);
1814 /* We need dwords */
1815 offset = offset / 4;
1816 ntq_store_dest(c, &instr->dest, 0,
1817 qir_uniform(c, QUNIFORM_UNIFORM,
1818 offset));
1819 } else {
1820 ntq_store_dest(c, &instr->dest, 0,
1821 indirect_uniform_load(c, instr));
1822 }
1823 break;
1824
1825 case nir_intrinsic_load_ubo:
1826 assert(instr->num_components == 1);
1827 ntq_store_dest(c, &instr->dest, 0, vc4_ubo_load(c, instr));
1828 break;
1829
1830 case nir_intrinsic_load_user_clip_plane:
1831 for (int i = 0; i < instr->num_components; i++) {
1832 ntq_store_dest(c, &instr->dest, i,
1833 qir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1834 nir_intrinsic_ucp_id(instr) *
1835 4 + i));
1836 }
1837 break;
1838
1839 case nir_intrinsic_load_blend_const_color_r_float:
1840 case nir_intrinsic_load_blend_const_color_g_float:
1841 case nir_intrinsic_load_blend_const_color_b_float:
1842 case nir_intrinsic_load_blend_const_color_a_float:
1843 ntq_store_dest(c, &instr->dest, 0,
1844 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_X +
1845 (instr->intrinsic -
1846 nir_intrinsic_load_blend_const_color_r_float),
1847 0));
1848 break;
1849
1850 case nir_intrinsic_load_blend_const_color_rgba8888_unorm:
1851 ntq_store_dest(c, &instr->dest, 0,
1852 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_RGBA,
1853 0));
1854 break;
1855
1856 case nir_intrinsic_load_blend_const_color_aaaa8888_unorm:
1857 ntq_store_dest(c, &instr->dest, 0,
1858 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_AAAA,
1859 0));
1860 break;
1861
1862 case nir_intrinsic_load_alpha_ref_float:
1863 ntq_store_dest(c, &instr->dest, 0,
1864 qir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1865 break;
1866
1867 case nir_intrinsic_load_sample_mask_in:
1868 ntq_store_dest(c, &instr->dest, 0,
1869 qir_uniform(c, QUNIFORM_SAMPLE_MASK, 0));
1870 break;
1871
1872 case nir_intrinsic_load_front_face:
1873 /* The register contains 0 (front) or 1 (back), and we need to
1874 * turn it into a NIR bool where true means front.
1875 */
1876 ntq_store_dest(c, &instr->dest, 0,
1877 qir_ADD(c,
1878 qir_uniform_ui(c, -1),
1879 qir_reg(QFILE_FRAG_REV_FLAG, 0)));
1880 break;
1881
1882 case nir_intrinsic_load_input:
1883 ntq_emit_load_input(c, instr);
1884 break;
1885
1886 case nir_intrinsic_store_output:
1887 const_offset = nir_src_as_const_value(instr->src[1]);
1888 assert(const_offset && "vc4 doesn't support indirect outputs");
1889 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1890
1891 /* MSAA color outputs are the only case where we have an
1892 * output that's not lowered to being a store of a single 32
1893 * bit value.
1894 */
1895 if (c->stage == QSTAGE_FRAG && instr->num_components == 4) {
1896 assert(offset == c->output_color_index);
1897 for (int i = 0; i < 4; i++) {
1898 c->sample_colors[i] =
1899 qir_MOV(c, ntq_get_src(c, instr->src[0],
1900 i));
1901 }
1902 } else {
1903 offset = offset * 4 + nir_intrinsic_component(instr);
1904 assert(instr->num_components == 1);
1905 c->outputs[offset] =
1906 qir_MOV(c, ntq_get_src(c, instr->src[0], 0));
1907 c->num_outputs = MAX2(c->num_outputs, offset + 1);
1908 }
1909 break;
1910
1911 case nir_intrinsic_discard:
1912 if (c->execute.file != QFILE_NULL) {
1913 qir_SF(c, c->execute);
1914 qir_MOV_cond(c, QPU_COND_ZS, c->discard,
1915 qir_uniform_ui(c, ~0));
1916 } else {
1917 qir_MOV_dest(c, c->discard, qir_uniform_ui(c, ~0));
1918 }
1919 break;
1920
1921 case nir_intrinsic_discard_if: {
1922 /* true (~0) if we're discarding */
1923 struct qreg cond = ntq_get_src(c, instr->src[0], 0);
1924
1925 if (c->execute.file != QFILE_NULL) {
1926 /* execute == 0 means the channel is active. Invert
1927 * the condition so that we can use zero as "executing
1928 * and discarding."
1929 */
1930 qir_SF(c, qir_AND(c, c->execute, qir_NOT(c, cond)));
1931 qir_MOV_cond(c, QPU_COND_ZS, c->discard, cond);
1932 } else {
1933 qir_OR_dest(c, c->discard, c->discard,
1934 ntq_get_src(c, instr->src[0], 0));
1935 }
1936
1937 break;
1938 }
1939
1940 default:
1941 fprintf(stderr, "Unknown intrinsic: ");
1942 nir_print_instr(&instr->instr, stderr);
1943 fprintf(stderr, "\n");
1944 break;
1945 }
1946 }
1947
1948 /* Clears (activates) the execute flags for any channels whose jump target
1949 * matches this block.
1950 */
1951 static void
1952 ntq_activate_execute_for_block(struct vc4_compile *c)
1953 {
1954 qir_SF(c, qir_SUB(c,
1955 c->execute,
1956 qir_uniform_ui(c, c->cur_block->index)));
1957 qir_MOV_cond(c, QPU_COND_ZS, c->execute, qir_uniform_ui(c, 0));
1958 }
1959
1960 static void
1961 ntq_emit_if(struct vc4_compile *c, nir_if *if_stmt)
1962 {
1963 if (!c->vc4->screen->has_control_flow) {
1964 fprintf(stderr,
1965 "IF statement support requires updated kernel.\n");
1966 return;
1967 }
1968
1969 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
1970 bool empty_else_block =
1971 (nir_else_block == nir_if_last_else_block(if_stmt) &&
1972 exec_list_is_empty(&nir_else_block->instr_list));
1973
1974 struct qblock *then_block = qir_new_block(c);
1975 struct qblock *after_block = qir_new_block(c);
1976 struct qblock *else_block;
1977 if (empty_else_block)
1978 else_block = after_block;
1979 else
1980 else_block = qir_new_block(c);
1981
1982 bool was_top_level = false;
1983 if (c->execute.file == QFILE_NULL) {
1984 c->execute = qir_MOV(c, qir_uniform_ui(c, 0));
1985 was_top_level = true;
1986 }
1987
1988 /* Set ZS for executing (execute == 0) and jumping (if->condition ==
1989 * 0) channels, and then update execute flags for those to point to
1990 * the ELSE block.
1991 */
1992 qir_SF(c, qir_OR(c,
1993 c->execute,
1994 ntq_get_src(c, if_stmt->condition, 0)));
1995 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1996 qir_uniform_ui(c, else_block->index));
1997
1998 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1999 * through.
2000 */
2001 qir_SF(c, c->execute);
2002 qir_BRANCH(c, QPU_COND_BRANCH_ALL_ZC);
2003 qir_link_blocks(c->cur_block, else_block);
2004 qir_link_blocks(c->cur_block, then_block);
2005
2006 /* Process the THEN block. */
2007 qir_set_emit_block(c, then_block);
2008 ntq_emit_cf_list(c, &if_stmt->then_list);
2009
2010 if (!empty_else_block) {
2011 /* Handle the end of the THEN block. First, all currently
2012 * active channels update their execute flags to point to
2013 * ENDIF
2014 */
2015 qir_SF(c, c->execute);
2016 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
2017 qir_uniform_ui(c, after_block->index));
2018
2019 /* If everything points at ENDIF, then jump there immediately. */
2020 qir_SF(c, qir_SUB(c, c->execute, qir_uniform_ui(c, after_block->index)));
2021 qir_BRANCH(c, QPU_COND_BRANCH_ALL_ZS);
2022 qir_link_blocks(c->cur_block, after_block);
2023 qir_link_blocks(c->cur_block, else_block);
2024
2025 qir_set_emit_block(c, else_block);
2026 ntq_activate_execute_for_block(c);
2027 ntq_emit_cf_list(c, &if_stmt->else_list);
2028 }
2029
2030 qir_link_blocks(c->cur_block, after_block);
2031
2032 qir_set_emit_block(c, after_block);
2033 if (was_top_level) {
2034 c->execute = c->undef;
2035 c->last_top_block = c->cur_block;
2036 } else {
2037 ntq_activate_execute_for_block(c);
2038 }
2039 }
2040
2041 static void
2042 ntq_emit_jump(struct vc4_compile *c, nir_jump_instr *jump)
2043 {
2044 struct qblock *jump_block;
2045 switch (jump->type) {
2046 case nir_jump_break:
2047 jump_block = c->loop_break_block;
2048 break;
2049 case nir_jump_continue:
2050 jump_block = c->loop_cont_block;
2051 break;
2052 default:
2053 unreachable("Unsupported jump type\n");
2054 }
2055
2056 qir_SF(c, c->execute);
2057 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
2058 qir_uniform_ui(c, jump_block->index));
2059
2060 /* Jump to the destination block if everyone has taken the jump. */
2061 qir_SF(c, qir_SUB(c, c->execute, qir_uniform_ui(c, jump_block->index)));
2062 qir_BRANCH(c, QPU_COND_BRANCH_ALL_ZS);
2063 struct qblock *new_block = qir_new_block(c);
2064 qir_link_blocks(c->cur_block, jump_block);
2065 qir_link_blocks(c->cur_block, new_block);
2066 qir_set_emit_block(c, new_block);
2067 }
2068
2069 static void
2070 ntq_emit_instr(struct vc4_compile *c, nir_instr *instr)
2071 {
2072 switch (instr->type) {
2073 case nir_instr_type_alu:
2074 ntq_emit_alu(c, nir_instr_as_alu(instr));
2075 break;
2076
2077 case nir_instr_type_intrinsic:
2078 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
2079 break;
2080
2081 case nir_instr_type_load_const:
2082 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
2083 break;
2084
2085 case nir_instr_type_ssa_undef:
2086 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
2087 break;
2088
2089 case nir_instr_type_tex:
2090 ntq_emit_tex(c, nir_instr_as_tex(instr));
2091 break;
2092
2093 case nir_instr_type_jump:
2094 ntq_emit_jump(c, nir_instr_as_jump(instr));
2095 break;
2096
2097 default:
2098 fprintf(stderr, "Unknown NIR instr type: ");
2099 nir_print_instr(instr, stderr);
2100 fprintf(stderr, "\n");
2101 abort();
2102 }
2103 }
2104
2105 static void
2106 ntq_emit_block(struct vc4_compile *c, nir_block *block)
2107 {
2108 nir_foreach_instr(instr, block) {
2109 ntq_emit_instr(c, instr);
2110 }
2111 }
2112
2113 static void ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list);
2114
2115 static void
2116 ntq_emit_loop(struct vc4_compile *c, nir_loop *loop)
2117 {
2118 if (!c->vc4->screen->has_control_flow) {
2119 fprintf(stderr,
2120 "loop support requires updated kernel.\n");
2121 ntq_emit_cf_list(c, &loop->body);
2122 return;
2123 }
2124
2125 bool was_top_level = false;
2126 if (c->execute.file == QFILE_NULL) {
2127 c->execute = qir_MOV(c, qir_uniform_ui(c, 0));
2128 was_top_level = true;
2129 }
2130
2131 struct qblock *save_loop_cont_block = c->loop_cont_block;
2132 struct qblock *save_loop_break_block = c->loop_break_block;
2133
2134 c->loop_cont_block = qir_new_block(c);
2135 c->loop_break_block = qir_new_block(c);
2136
2137 qir_link_blocks(c->cur_block, c->loop_cont_block);
2138 qir_set_emit_block(c, c->loop_cont_block);
2139 ntq_activate_execute_for_block(c);
2140
2141 ntq_emit_cf_list(c, &loop->body);
2142
2143 /* If anything had explicitly continued, or is here at the end of the
2144 * loop, then we need to loop again. SF updates are masked by the
2145 * instruction's condition, so we can do the OR of the two conditions
2146 * within SF.
2147 */
2148 qir_SF(c, c->execute);
2149 struct qinst *cont_check =
2150 qir_SUB_dest(c,
2151 c->undef,
2152 c->execute,
2153 qir_uniform_ui(c, c->loop_cont_block->index));
2154 cont_check->cond = QPU_COND_ZC;
2155 cont_check->sf = true;
2156
2157 qir_BRANCH(c, QPU_COND_BRANCH_ANY_ZS);
2158 qir_link_blocks(c->cur_block, c->loop_cont_block);
2159 qir_link_blocks(c->cur_block, c->loop_break_block);
2160
2161 qir_set_emit_block(c, c->loop_break_block);
2162 if (was_top_level) {
2163 c->execute = c->undef;
2164 c->last_top_block = c->cur_block;
2165 } else {
2166 ntq_activate_execute_for_block(c);
2167 }
2168
2169 c->loop_break_block = save_loop_break_block;
2170 c->loop_cont_block = save_loop_cont_block;
2171 }
2172
2173 static void
2174 ntq_emit_function(struct vc4_compile *c, nir_function_impl *func)
2175 {
2176 fprintf(stderr, "FUNCTIONS not handled.\n");
2177 abort();
2178 }
2179
2180 static void
2181 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list)
2182 {
2183 foreach_list_typed(nir_cf_node, node, node, list) {
2184 switch (node->type) {
2185 case nir_cf_node_block:
2186 ntq_emit_block(c, nir_cf_node_as_block(node));
2187 break;
2188
2189 case nir_cf_node_if:
2190 ntq_emit_if(c, nir_cf_node_as_if(node));
2191 break;
2192
2193 case nir_cf_node_loop:
2194 ntq_emit_loop(c, nir_cf_node_as_loop(node));
2195 break;
2196
2197 case nir_cf_node_function:
2198 ntq_emit_function(c, nir_cf_node_as_function(node));
2199 break;
2200
2201 default:
2202 fprintf(stderr, "Unknown NIR node type\n");
2203 abort();
2204 }
2205 }
2206 }
2207
2208 static void
2209 ntq_emit_impl(struct vc4_compile *c, nir_function_impl *impl)
2210 {
2211 ntq_setup_registers(c, &impl->registers);
2212 ntq_emit_cf_list(c, &impl->body);
2213 }
2214
2215 static void
2216 nir_to_qir(struct vc4_compile *c)
2217 {
2218 if (c->stage == QSTAGE_FRAG && c->s->info.fs.uses_discard)
2219 c->discard = qir_MOV(c, qir_uniform_ui(c, 0));
2220
2221 ntq_setup_inputs(c);
2222 ntq_setup_outputs(c);
2223 ntq_setup_uniforms(c);
2224 ntq_setup_registers(c, &c->s->registers);
2225
2226 /* Find the main function and emit the body. */
2227 nir_foreach_function(function, c->s) {
2228 assert(strcmp(function->name, "main") == 0);
2229 assert(function->impl);
2230 ntq_emit_impl(c, function->impl);
2231 }
2232 }
2233
2234 static const nir_shader_compiler_options nir_options = {
2235 .lower_all_io_to_temps = true,
2236 .lower_extract_byte = true,
2237 .lower_extract_word = true,
2238 .lower_fdiv = true,
2239 .lower_ffma = true,
2240 .lower_flrp32 = true,
2241 .lower_fpow = true,
2242 .lower_fsat = true,
2243 .lower_fsqrt = true,
2244 .lower_ldexp = true,
2245 .lower_negate = true,
2246 .native_integers = true,
2247 .max_unroll_iterations = 32,
2248 };
2249
2250 const void *
2251 vc4_screen_get_compiler_options(struct pipe_screen *pscreen,
2252 enum pipe_shader_ir ir,
2253 enum pipe_shader_type shader)
2254 {
2255 return &nir_options;
2256 }
2257
2258 static int
2259 count_nir_instrs(nir_shader *nir)
2260 {
2261 int count = 0;
2262 nir_foreach_function(function, nir) {
2263 if (!function->impl)
2264 continue;
2265 nir_foreach_block(block, function->impl) {
2266 nir_foreach_instr(instr, block)
2267 count++;
2268 }
2269 }
2270 return count;
2271 }
2272
2273 static struct vc4_compile *
2274 vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage,
2275 struct vc4_key *key, bool fs_threaded)
2276 {
2277 struct vc4_compile *c = qir_compile_init();
2278
2279 c->vc4 = vc4;
2280 c->stage = stage;
2281 c->shader_state = &key->shader_state->base;
2282 c->program_id = key->shader_state->program_id;
2283 c->variant_id =
2284 p_atomic_inc_return(&key->shader_state->compiled_variant_count);
2285 c->fs_threaded = fs_threaded;
2286
2287 c->key = key;
2288 switch (stage) {
2289 case QSTAGE_FRAG:
2290 c->fs_key = (struct vc4_fs_key *)key;
2291 if (c->fs_key->is_points) {
2292 c->point_x = emit_fragment_varying(c, ~0, 0);
2293 c->point_y = emit_fragment_varying(c, ~0, 0);
2294 } else if (c->fs_key->is_lines) {
2295 c->line_x = emit_fragment_varying(c, ~0, 0);
2296 }
2297 break;
2298 case QSTAGE_VERT:
2299 c->vs_key = (struct vc4_vs_key *)key;
2300 break;
2301 case QSTAGE_COORD:
2302 c->vs_key = (struct vc4_vs_key *)key;
2303 break;
2304 }
2305
2306 c->s = nir_shader_clone(c, key->shader_state->base.ir.nir);
2307
2308 if (stage == QSTAGE_FRAG) {
2309 if (c->fs_key->alpha_test_func != COMPARE_FUNC_ALWAYS) {
2310 NIR_PASS_V(c->s, nir_lower_alpha_test,
2311 c->fs_key->alpha_test_func,
2312 c->fs_key->sample_alpha_to_one &&
2313 c->fs_key->msaa);
2314 }
2315 NIR_PASS_V(c->s, vc4_nir_lower_blend, c);
2316 }
2317
2318 struct nir_lower_tex_options tex_options = {
2319 /* We would need to implement txs, but we don't want the
2320 * int/float conversions
2321 */
2322 .lower_rect = false,
2323
2324 .lower_txp = ~0,
2325
2326 /* Apply swizzles to all samplers. */
2327 .swizzle_result = ~0,
2328 };
2329
2330 /* Lower the format swizzle and ARB_texture_swizzle-style swizzle.
2331 * The format swizzling applies before sRGB decode, and
2332 * ARB_texture_swizzle is the last thing before returning the sample.
2333 */
2334 for (int i = 0; i < ARRAY_SIZE(key->tex); i++) {
2335 enum pipe_format format = c->key->tex[i].format;
2336
2337 if (!format)
2338 continue;
2339
2340 const uint8_t *format_swizzle = vc4_get_format_swizzle(format);
2341
2342 for (int j = 0; j < 4; j++) {
2343 uint8_t arb_swiz = c->key->tex[i].swizzle[j];
2344
2345 if (arb_swiz <= 3) {
2346 tex_options.swizzles[i][j] =
2347 format_swizzle[arb_swiz];
2348 } else {
2349 tex_options.swizzles[i][j] = arb_swiz;
2350 }
2351 }
2352
2353 if (util_format_is_srgb(format))
2354 tex_options.lower_srgb |= (1 << i);
2355 }
2356
2357 NIR_PASS_V(c->s, nir_lower_tex, &tex_options);
2358
2359 if (c->fs_key && c->fs_key->light_twoside)
2360 NIR_PASS_V(c->s, nir_lower_two_sided_color);
2361
2362 if (c->vs_key && c->vs_key->clamp_color)
2363 NIR_PASS_V(c->s, nir_lower_clamp_color_outputs);
2364
2365 if (c->key->ucp_enables) {
2366 if (stage == QSTAGE_FRAG) {
2367 NIR_PASS_V(c->s, nir_lower_clip_fs, c->key->ucp_enables);
2368 } else {
2369 NIR_PASS_V(c->s, nir_lower_clip_vs, c->key->ucp_enables);
2370 NIR_PASS_V(c->s, nir_lower_io_to_scalar,
2371 nir_var_shader_out);
2372 }
2373 }
2374
2375 /* FS input scalarizing must happen after nir_lower_two_sided_color,
2376 * which only handles a vec4 at a time. Similarly, VS output
2377 * scalarizing must happen after nir_lower_clip_vs.
2378 */
2379 if (c->stage == QSTAGE_FRAG)
2380 NIR_PASS_V(c->s, nir_lower_io_to_scalar, nir_var_shader_in);
2381 else
2382 NIR_PASS_V(c->s, nir_lower_io_to_scalar, nir_var_shader_out);
2383
2384 NIR_PASS_V(c->s, vc4_nir_lower_io, c);
2385 NIR_PASS_V(c->s, vc4_nir_lower_txf_ms, c);
2386 NIR_PASS_V(c->s, nir_lower_idiv);
2387
2388 vc4_optimize_nir(c->s);
2389
2390 NIR_PASS_V(c->s, nir_convert_from_ssa, true);
2391
2392 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2393 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d NIR instructions\n",
2394 qir_get_stage_name(c->stage),
2395 c->program_id, c->variant_id,
2396 count_nir_instrs(c->s));
2397 }
2398
2399 if (vc4_debug & VC4_DEBUG_NIR) {
2400 fprintf(stderr, "%s prog %d/%d NIR:\n",
2401 qir_get_stage_name(c->stage),
2402 c->program_id, c->variant_id);
2403 nir_print_shader(c->s, stderr);
2404 }
2405
2406 nir_to_qir(c);
2407
2408 switch (stage) {
2409 case QSTAGE_FRAG:
2410 /* FS threading requires that the thread execute
2411 * QPU_SIG_LAST_THREAD_SWITCH exactly once before terminating
2412 * (with no other THRSW afterwards, obviously). If we didn't
2413 * fetch a texture at a top level block, this wouldn't be
2414 * true.
2415 */
2416 if (c->fs_threaded && !c->last_thrsw_at_top_level) {
2417 c->failed = true;
2418 return c;
2419 }
2420
2421 emit_frag_end(c);
2422 break;
2423 case QSTAGE_VERT:
2424 emit_vert_end(c,
2425 c->vs_key->fs_inputs->input_slots,
2426 c->vs_key->fs_inputs->num_inputs);
2427 break;
2428 case QSTAGE_COORD:
2429 emit_coord_end(c);
2430 break;
2431 }
2432
2433 if (vc4_debug & VC4_DEBUG_QIR) {
2434 fprintf(stderr, "%s prog %d/%d pre-opt QIR:\n",
2435 qir_get_stage_name(c->stage),
2436 c->program_id, c->variant_id);
2437 qir_dump(c);
2438 fprintf(stderr, "\n");
2439 }
2440
2441 qir_optimize(c);
2442 qir_lower_uniforms(c);
2443
2444 qir_schedule_instructions(c);
2445 qir_emit_uniform_stream_resets(c);
2446
2447 if (vc4_debug & VC4_DEBUG_QIR) {
2448 fprintf(stderr, "%s prog %d/%d QIR:\n",
2449 qir_get_stage_name(c->stage),
2450 c->program_id, c->variant_id);
2451 qir_dump(c);
2452 fprintf(stderr, "\n");
2453 }
2454
2455 qir_reorder_uniforms(c);
2456 vc4_generate_code(vc4, c);
2457
2458 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2459 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d instructions\n",
2460 qir_get_stage_name(c->stage),
2461 c->program_id, c->variant_id,
2462 c->qpu_inst_count);
2463 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
2464 qir_get_stage_name(c->stage),
2465 c->program_id, c->variant_id,
2466 c->num_uniforms);
2467 }
2468
2469 ralloc_free(c->s);
2470
2471 return c;
2472 }
2473
2474 static void *
2475 vc4_shader_state_create(struct pipe_context *pctx,
2476 const struct pipe_shader_state *cso)
2477 {
2478 struct vc4_context *vc4 = vc4_context(pctx);
2479 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
2480 if (!so)
2481 return NULL;
2482
2483 so->program_id = vc4->next_uncompiled_program_id++;
2484
2485 nir_shader *s;
2486
2487 if (cso->type == PIPE_SHADER_IR_NIR) {
2488 /* The backend takes ownership of the NIR shader on state
2489 * creation.
2490 */
2491 s = cso->ir.nir;
2492
2493 NIR_PASS_V(s, nir_lower_io, nir_var_all & ~nir_var_uniform,
2494 type_size,
2495 (nir_lower_io_options)0);
2496 NIR_PASS_V(s, nir_lower_io, nir_var_uniform,
2497 uniforms_type_size,
2498 (nir_lower_io_options)0);
2499 } else {
2500 assert(cso->type == PIPE_SHADER_IR_TGSI);
2501
2502 if (vc4_debug & VC4_DEBUG_TGSI) {
2503 fprintf(stderr, "prog %d TGSI:\n",
2504 so->program_id);
2505 tgsi_dump(cso->tokens, 0);
2506 fprintf(stderr, "\n");
2507 }
2508 s = tgsi_to_nir(cso->tokens, &nir_options);
2509 }
2510
2511 NIR_PASS_V(s, nir_opt_global_to_local);
2512 NIR_PASS_V(s, nir_lower_regs_to_ssa);
2513 NIR_PASS_V(s, nir_normalize_cubemap_coords);
2514
2515 NIR_PASS_V(s, nir_lower_load_const_to_scalar);
2516
2517 vc4_optimize_nir(s);
2518
2519 NIR_PASS_V(s, nir_remove_dead_variables, nir_var_local);
2520
2521 /* Garbage collect dead instructions */
2522 nir_sweep(s);
2523
2524 so->base.type = PIPE_SHADER_IR_NIR;
2525 so->base.ir.nir = s;
2526
2527 if (vc4_debug & VC4_DEBUG_NIR) {
2528 fprintf(stderr, "%s prog %d NIR:\n",
2529 gl_shader_stage_name(s->info.stage),
2530 so->program_id);
2531 nir_print_shader(s, stderr);
2532 fprintf(stderr, "\n");
2533 }
2534
2535 return so;
2536 }
2537
2538 static void
2539 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
2540 struct vc4_compile *c)
2541 {
2542 int count = c->num_uniforms;
2543 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2544
2545 uinfo->count = count;
2546 uinfo->data = ralloc_array(shader, uint32_t, count);
2547 memcpy(uinfo->data, c->uniform_data,
2548 count * sizeof(*uinfo->data));
2549 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
2550 memcpy(uinfo->contents, c->uniform_contents,
2551 count * sizeof(*uinfo->contents));
2552 uinfo->num_texture_samples = c->num_texture_samples;
2553
2554 vc4_set_shader_uniform_dirty_flags(shader);
2555 }
2556
2557 static void
2558 vc4_setup_compiled_fs_inputs(struct vc4_context *vc4, struct vc4_compile *c,
2559 struct vc4_compiled_shader *shader)
2560 {
2561 struct vc4_fs_inputs inputs;
2562
2563 memset(&inputs, 0, sizeof(inputs));
2564 inputs.input_slots = ralloc_array(shader,
2565 struct vc4_varying_slot,
2566 c->num_input_slots);
2567
2568 bool input_live[c->num_input_slots];
2569
2570 memset(input_live, 0, sizeof(input_live));
2571 qir_for_each_inst_inorder(inst, c) {
2572 for (int i = 0; i < qir_get_nsrc(inst); i++) {
2573 if (inst->src[i].file == QFILE_VARY)
2574 input_live[inst->src[i].index] = true;
2575 }
2576 }
2577
2578 for (int i = 0; i < c->num_input_slots; i++) {
2579 struct vc4_varying_slot *slot = &c->input_slots[i];
2580
2581 if (!input_live[i])
2582 continue;
2583
2584 /* Skip non-VS-output inputs. */
2585 if (slot->slot == (uint8_t)~0)
2586 continue;
2587
2588 if (slot->slot == VARYING_SLOT_COL0 ||
2589 slot->slot == VARYING_SLOT_COL1 ||
2590 slot->slot == VARYING_SLOT_BFC0 ||
2591 slot->slot == VARYING_SLOT_BFC1) {
2592 shader->color_inputs |= (1 << inputs.num_inputs);
2593 }
2594
2595 inputs.input_slots[inputs.num_inputs] = *slot;
2596 inputs.num_inputs++;
2597 }
2598 shader->num_inputs = inputs.num_inputs;
2599
2600 /* Add our set of inputs to the set of all inputs seen. This way, we
2601 * can have a single pointer that identifies an FS inputs set,
2602 * allowing VS to avoid recompiling when the FS is recompiled (or a
2603 * new one is bound using separate shader objects) but the inputs
2604 * don't change.
2605 */
2606 struct set_entry *entry = _mesa_set_search(vc4->fs_inputs_set, &inputs);
2607 if (entry) {
2608 shader->fs_inputs = entry->key;
2609 ralloc_free(inputs.input_slots);
2610 } else {
2611 struct vc4_fs_inputs *alloc_inputs;
2612
2613 alloc_inputs = rzalloc(vc4->fs_inputs_set, struct vc4_fs_inputs);
2614 memcpy(alloc_inputs, &inputs, sizeof(inputs));
2615 ralloc_steal(alloc_inputs, inputs.input_slots);
2616 _mesa_set_add(vc4->fs_inputs_set, alloc_inputs);
2617
2618 shader->fs_inputs = alloc_inputs;
2619 }
2620 }
2621
2622 static struct vc4_compiled_shader *
2623 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
2624 struct vc4_key *key)
2625 {
2626 struct hash_table *ht;
2627 uint32_t key_size;
2628 bool try_threading;
2629
2630 if (stage == QSTAGE_FRAG) {
2631 ht = vc4->fs_cache;
2632 key_size = sizeof(struct vc4_fs_key);
2633 try_threading = vc4->screen->has_threaded_fs;
2634 } else {
2635 ht = vc4->vs_cache;
2636 key_size = sizeof(struct vc4_vs_key);
2637 try_threading = false;
2638 }
2639
2640 struct vc4_compiled_shader *shader;
2641 struct hash_entry *entry = _mesa_hash_table_search(ht, key);
2642 if (entry)
2643 return entry->data;
2644
2645 struct vc4_compile *c = vc4_shader_ntq(vc4, stage, key, try_threading);
2646 /* If the FS failed to compile threaded, fall back to single threaded. */
2647 if (try_threading && c->failed) {
2648 qir_compile_destroy(c);
2649 c = vc4_shader_ntq(vc4, stage, key, false);
2650 }
2651
2652 shader = rzalloc(NULL, struct vc4_compiled_shader);
2653
2654 shader->program_id = vc4->next_compiled_program_id++;
2655 if (stage == QSTAGE_FRAG) {
2656 vc4_setup_compiled_fs_inputs(vc4, c, shader);
2657
2658 /* Note: the temporary clone in c->s has been freed. */
2659 nir_shader *orig_shader = key->shader_state->base.ir.nir;
2660 if (orig_shader->info.outputs_written & (1 << FRAG_RESULT_DEPTH))
2661 shader->disable_early_z = true;
2662 } else {
2663 shader->num_inputs = c->num_inputs;
2664
2665 shader->vattr_offsets[0] = 0;
2666 for (int i = 0; i < 8; i++) {
2667 shader->vattr_offsets[i + 1] =
2668 shader->vattr_offsets[i] + c->vattr_sizes[i];
2669
2670 if (c->vattr_sizes[i])
2671 shader->vattrs_live |= (1 << i);
2672 }
2673 }
2674
2675 shader->failed = c->failed;
2676 if (c->failed) {
2677 shader->failed = true;
2678 } else {
2679 copy_uniform_state_to_shader(shader, c);
2680 shader->bo = vc4_bo_alloc_shader(vc4->screen, c->qpu_insts,
2681 c->qpu_inst_count *
2682 sizeof(uint64_t));
2683 }
2684
2685 shader->fs_threaded = c->fs_threaded;
2686
2687 /* Copy the compiler UBO range state to the compiled shader, dropping
2688 * out arrays that were never referenced by an indirect load.
2689 *
2690 * (Note that QIR dead code elimination of an array access still
2691 * leaves that array alive, though)
2692 */
2693 if (c->num_ubo_ranges) {
2694 shader->num_ubo_ranges = c->num_ubo_ranges;
2695 shader->ubo_ranges = ralloc_array(shader, struct vc4_ubo_range,
2696 c->num_ubo_ranges);
2697 uint32_t j = 0;
2698 for (int i = 0; i < c->num_uniform_ranges; i++) {
2699 struct vc4_compiler_ubo_range *range =
2700 &c->ubo_ranges[i];
2701 if (!range->used)
2702 continue;
2703
2704 shader->ubo_ranges[j].dst_offset = range->dst_offset;
2705 shader->ubo_ranges[j].src_offset = range->src_offset;
2706 shader->ubo_ranges[j].size = range->size;
2707 shader->ubo_size += c->ubo_ranges[i].size;
2708 j++;
2709 }
2710 }
2711 if (shader->ubo_size) {
2712 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2713 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d UBO uniforms\n",
2714 qir_get_stage_name(c->stage),
2715 c->program_id, c->variant_id,
2716 shader->ubo_size / 4);
2717 }
2718 }
2719
2720 if ((vc4_debug & VC4_DEBUG_SHADERDB) && stage == QSTAGE_FRAG) {
2721 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d FS threads\n",
2722 qir_get_stage_name(c->stage),
2723 c->program_id, c->variant_id,
2724 1 + shader->fs_threaded);
2725 }
2726
2727 qir_compile_destroy(c);
2728
2729 struct vc4_key *dup_key;
2730 dup_key = rzalloc_size(shader, key_size); /* TODO: don't use rzalloc */
2731 memcpy(dup_key, key, key_size);
2732 _mesa_hash_table_insert(ht, dup_key, shader);
2733
2734 return shader;
2735 }
2736
2737 static void
2738 vc4_setup_shared_key(struct vc4_context *vc4, struct vc4_key *key,
2739 struct vc4_texture_stateobj *texstate)
2740 {
2741 for (int i = 0; i < texstate->num_textures; i++) {
2742 struct pipe_sampler_view *sampler = texstate->textures[i];
2743 struct vc4_sampler_view *vc4_sampler = vc4_sampler_view(sampler);
2744 struct pipe_sampler_state *sampler_state =
2745 texstate->samplers[i];
2746
2747 if (!sampler)
2748 continue;
2749
2750 key->tex[i].format = sampler->format;
2751 key->tex[i].swizzle[0] = sampler->swizzle_r;
2752 key->tex[i].swizzle[1] = sampler->swizzle_g;
2753 key->tex[i].swizzle[2] = sampler->swizzle_b;
2754 key->tex[i].swizzle[3] = sampler->swizzle_a;
2755
2756 if (sampler->texture->nr_samples > 1) {
2757 key->tex[i].msaa_width = sampler->texture->width0;
2758 key->tex[i].msaa_height = sampler->texture->height0;
2759 } else if (sampler){
2760 key->tex[i].compare_mode = sampler_state->compare_mode;
2761 key->tex[i].compare_func = sampler_state->compare_func;
2762 key->tex[i].wrap_s = sampler_state->wrap_s;
2763 key->tex[i].wrap_t = sampler_state->wrap_t;
2764 key->tex[i].force_first_level =
2765 vc4_sampler->force_first_level;
2766 }
2767 }
2768
2769 key->ucp_enables = vc4->rasterizer->base.clip_plane_enable;
2770 }
2771
2772 static void
2773 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
2774 {
2775 struct vc4_job *job = vc4->job;
2776 struct vc4_fs_key local_key;
2777 struct vc4_fs_key *key = &local_key;
2778
2779 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2780 VC4_DIRTY_BLEND |
2781 VC4_DIRTY_FRAMEBUFFER |
2782 VC4_DIRTY_ZSA |
2783 VC4_DIRTY_RASTERIZER |
2784 VC4_DIRTY_SAMPLE_MASK |
2785 VC4_DIRTY_FRAGTEX |
2786 VC4_DIRTY_UNCOMPILED_FS |
2787 VC4_DIRTY_UBO_1_SIZE))) {
2788 return;
2789 }
2790
2791 memset(key, 0, sizeof(*key));
2792 vc4_setup_shared_key(vc4, &key->base, &vc4->fragtex);
2793 key->base.shader_state = vc4->prog.bind_fs;
2794 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
2795 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
2796 prim_mode <= PIPE_PRIM_LINE_STRIP);
2797 key->blend = vc4->blend->rt[0];
2798 if (vc4->blend->logicop_enable) {
2799 key->logicop_func = vc4->blend->logicop_func;
2800 } else {
2801 key->logicop_func = PIPE_LOGICOP_COPY;
2802 }
2803 if (job->msaa) {
2804 key->msaa = vc4->rasterizer->base.multisample;
2805 key->sample_coverage = (vc4->sample_mask != (1 << VC4_MAX_SAMPLES) - 1);
2806 key->sample_alpha_to_coverage = vc4->blend->alpha_to_coverage;
2807 key->sample_alpha_to_one = vc4->blend->alpha_to_one;
2808 }
2809
2810 if (vc4->framebuffer.cbufs[0])
2811 key->color_format = vc4->framebuffer.cbufs[0]->format;
2812
2813 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
2814 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
2815 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
2816 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
2817 key->stencil_enabled);
2818 if (vc4->zsa->base.alpha.enabled)
2819 key->alpha_test_func = vc4->zsa->base.alpha.func;
2820 else
2821 key->alpha_test_func = COMPARE_FUNC_ALWAYS;
2822
2823 if (key->is_points) {
2824 key->point_sprite_mask =
2825 vc4->rasterizer->base.sprite_coord_enable;
2826 key->point_coord_upper_left =
2827 (vc4->rasterizer->base.sprite_coord_mode ==
2828 PIPE_SPRITE_COORD_UPPER_LEFT);
2829 }
2830
2831 key->ubo_1_size = vc4->constbuf[PIPE_SHADER_FRAGMENT].cb[1].buffer_size;
2832 key->light_twoside = vc4->rasterizer->base.light_twoside;
2833
2834 struct vc4_compiled_shader *old_fs = vc4->prog.fs;
2835 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
2836 if (vc4->prog.fs == old_fs)
2837 return;
2838
2839 vc4->dirty |= VC4_DIRTY_COMPILED_FS;
2840
2841 if (vc4->rasterizer->base.flatshade &&
2842 (!old_fs || vc4->prog.fs->color_inputs != old_fs->color_inputs)) {
2843 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
2844 }
2845
2846 if (!old_fs || vc4->prog.fs->fs_inputs != old_fs->fs_inputs)
2847 vc4->dirty |= VC4_DIRTY_FS_INPUTS;
2848 }
2849
2850 static void
2851 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
2852 {
2853 struct vc4_vs_key local_key;
2854 struct vc4_vs_key *key = &local_key;
2855
2856 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2857 VC4_DIRTY_RASTERIZER |
2858 VC4_DIRTY_VERTTEX |
2859 VC4_DIRTY_VTXSTATE |
2860 VC4_DIRTY_UNCOMPILED_VS |
2861 VC4_DIRTY_FS_INPUTS))) {
2862 return;
2863 }
2864
2865 memset(key, 0, sizeof(*key));
2866 vc4_setup_shared_key(vc4, &key->base, &vc4->verttex);
2867 key->base.shader_state = vc4->prog.bind_vs;
2868 key->fs_inputs = vc4->prog.fs->fs_inputs;
2869 key->clamp_color = vc4->rasterizer->base.clamp_vertex_color;
2870
2871 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
2872 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
2873
2874 key->per_vertex_point_size =
2875 (prim_mode == PIPE_PRIM_POINTS &&
2876 vc4->rasterizer->base.point_size_per_vertex);
2877
2878 struct vc4_compiled_shader *vs =
2879 vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
2880 if (vs != vc4->prog.vs) {
2881 vc4->prog.vs = vs;
2882 vc4->dirty |= VC4_DIRTY_COMPILED_VS;
2883 }
2884
2885 key->is_coord = true;
2886 /* Coord shaders don't care what the FS inputs are. */
2887 key->fs_inputs = NULL;
2888 struct vc4_compiled_shader *cs =
2889 vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
2890 if (cs != vc4->prog.cs) {
2891 vc4->prog.cs = cs;
2892 vc4->dirty |= VC4_DIRTY_COMPILED_CS;
2893 }
2894 }
2895
2896 bool
2897 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
2898 {
2899 vc4_update_compiled_fs(vc4, prim_mode);
2900 vc4_update_compiled_vs(vc4, prim_mode);
2901
2902 return !(vc4->prog.cs->failed ||
2903 vc4->prog.vs->failed ||
2904 vc4->prog.fs->failed);
2905 }
2906
2907 static uint32_t
2908 fs_cache_hash(const void *key)
2909 {
2910 return _mesa_hash_data(key, sizeof(struct vc4_fs_key));
2911 }
2912
2913 static uint32_t
2914 vs_cache_hash(const void *key)
2915 {
2916 return _mesa_hash_data(key, sizeof(struct vc4_vs_key));
2917 }
2918
2919 static bool
2920 fs_cache_compare(const void *key1, const void *key2)
2921 {
2922 return memcmp(key1, key2, sizeof(struct vc4_fs_key)) == 0;
2923 }
2924
2925 static bool
2926 vs_cache_compare(const void *key1, const void *key2)
2927 {
2928 return memcmp(key1, key2, sizeof(struct vc4_vs_key)) == 0;
2929 }
2930
2931 static uint32_t
2932 fs_inputs_hash(const void *key)
2933 {
2934 const struct vc4_fs_inputs *inputs = key;
2935
2936 return _mesa_hash_data(inputs->input_slots,
2937 sizeof(*inputs->input_slots) *
2938 inputs->num_inputs);
2939 }
2940
2941 static bool
2942 fs_inputs_compare(const void *key1, const void *key2)
2943 {
2944 const struct vc4_fs_inputs *inputs1 = key1;
2945 const struct vc4_fs_inputs *inputs2 = key2;
2946
2947 return (inputs1->num_inputs == inputs2->num_inputs &&
2948 memcmp(inputs1->input_slots,
2949 inputs2->input_slots,
2950 sizeof(*inputs1->input_slots) *
2951 inputs1->num_inputs) == 0);
2952 }
2953
2954 static void
2955 delete_from_cache_if_matches(struct hash_table *ht,
2956 struct vc4_compiled_shader **last_compile,
2957 struct hash_entry *entry,
2958 struct vc4_uncompiled_shader *so)
2959 {
2960 const struct vc4_key *key = entry->key;
2961
2962 if (key->shader_state == so) {
2963 struct vc4_compiled_shader *shader = entry->data;
2964 _mesa_hash_table_remove(ht, entry);
2965 vc4_bo_unreference(&shader->bo);
2966
2967 if (shader == *last_compile)
2968 *last_compile = NULL;
2969
2970 ralloc_free(shader);
2971 }
2972 }
2973
2974 static void
2975 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
2976 {
2977 struct vc4_context *vc4 = vc4_context(pctx);
2978 struct vc4_uncompiled_shader *so = hwcso;
2979
2980 struct hash_entry *entry;
2981 hash_table_foreach(vc4->fs_cache, entry) {
2982 delete_from_cache_if_matches(vc4->fs_cache, &vc4->prog.fs,
2983 entry, so);
2984 }
2985 hash_table_foreach(vc4->vs_cache, entry) {
2986 delete_from_cache_if_matches(vc4->vs_cache, &vc4->prog.vs,
2987 entry, so);
2988 }
2989
2990 ralloc_free(so->base.ir.nir);
2991 free(so);
2992 }
2993
2994 static void
2995 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2996 {
2997 struct vc4_context *vc4 = vc4_context(pctx);
2998 vc4->prog.bind_fs = hwcso;
2999 vc4->dirty |= VC4_DIRTY_UNCOMPILED_FS;
3000 }
3001
3002 static void
3003 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
3004 {
3005 struct vc4_context *vc4 = vc4_context(pctx);
3006 vc4->prog.bind_vs = hwcso;
3007 vc4->dirty |= VC4_DIRTY_UNCOMPILED_VS;
3008 }
3009
3010 void
3011 vc4_program_init(struct pipe_context *pctx)
3012 {
3013 struct vc4_context *vc4 = vc4_context(pctx);
3014
3015 pctx->create_vs_state = vc4_shader_state_create;
3016 pctx->delete_vs_state = vc4_shader_state_delete;
3017
3018 pctx->create_fs_state = vc4_shader_state_create;
3019 pctx->delete_fs_state = vc4_shader_state_delete;
3020
3021 pctx->bind_fs_state = vc4_fp_state_bind;
3022 pctx->bind_vs_state = vc4_vp_state_bind;
3023
3024 vc4->fs_cache = _mesa_hash_table_create(pctx, fs_cache_hash,
3025 fs_cache_compare);
3026 vc4->vs_cache = _mesa_hash_table_create(pctx, vs_cache_hash,
3027 vs_cache_compare);
3028 vc4->fs_inputs_set = _mesa_set_create(pctx, fs_inputs_hash,
3029 fs_inputs_compare);
3030 }
3031
3032 void
3033 vc4_program_fini(struct pipe_context *pctx)
3034 {
3035 struct vc4_context *vc4 = vc4_context(pctx);
3036
3037 struct hash_entry *entry;
3038 hash_table_foreach(vc4->fs_cache, entry) {
3039 struct vc4_compiled_shader *shader = entry->data;
3040 vc4_bo_unreference(&shader->bo);
3041 ralloc_free(shader);
3042 _mesa_hash_table_remove(vc4->fs_cache, entry);
3043 }
3044
3045 hash_table_foreach(vc4->vs_cache, entry) {
3046 struct vc4_compiled_shader *shader = entry->data;
3047 vc4_bo_unreference(&shader->bo);
3048 ralloc_free(shader);
3049 _mesa_hash_table_remove(vc4->vs_cache, entry);
3050 }
3051 }