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vc4: Add support for NIR loops and break/continue.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "util/u_format.h"
27 #include "util/u_hash.h"
28 #include "util/u_math.h"
29 #include "util/u_memory.h"
30 #include "util/ralloc.h"
31 #include "util/hash_table.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "compiler/nir/nir.h"
35 #include "compiler/nir/nir_builder.h"
36 #include "nir/tgsi_to_nir.h"
37 #include "vc4_context.h"
38 #include "vc4_qpu.h"
39 #include "vc4_qir.h"
40 #ifdef USE_VC4_SIMULATOR
41 #include "simpenrose/simpenrose.h"
42 #endif
43
44 static struct qreg
45 ntq_get_src(struct vc4_compile *c, nir_src src, int i);
46 static void
47 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list);
48
49 static void
50 resize_qreg_array(struct vc4_compile *c,
51 struct qreg **regs,
52 uint32_t *size,
53 uint32_t decl_size)
54 {
55 if (*size >= decl_size)
56 return;
57
58 uint32_t old_size = *size;
59 *size = MAX2(*size * 2, decl_size);
60 *regs = reralloc(c, *regs, struct qreg, *size);
61 if (!*regs) {
62 fprintf(stderr, "Malloc failure\n");
63 abort();
64 }
65
66 for (uint32_t i = old_size; i < *size; i++)
67 (*regs)[i] = c->undef;
68 }
69
70 static struct qreg
71 indirect_uniform_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
72 {
73 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
74 uint32_t offset = intr->const_index[0];
75 struct vc4_compiler_ubo_range *range = NULL;
76 unsigned i;
77 for (i = 0; i < c->num_uniform_ranges; i++) {
78 range = &c->ubo_ranges[i];
79 if (offset >= range->src_offset &&
80 offset < range->src_offset + range->size) {
81 break;
82 }
83 }
84 /* The driver-location-based offset always has to be within a declared
85 * uniform range.
86 */
87 assert(range);
88 if (!range->used) {
89 range->used = true;
90 range->dst_offset = c->next_ubo_dst_offset;
91 c->next_ubo_dst_offset += range->size;
92 c->num_ubo_ranges++;
93 }
94
95 offset -= range->src_offset;
96
97 /* Adjust for where we stored the TGSI register base. */
98 indirect_offset = qir_ADD(c, indirect_offset,
99 qir_uniform_ui(c, (range->dst_offset +
100 offset)));
101
102 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
103 indirect_offset = qir_MAX(c, indirect_offset, qir_uniform_ui(c, 0));
104 indirect_offset = qir_MIN(c, indirect_offset,
105 qir_uniform_ui(c, (range->dst_offset +
106 range->size - 4)));
107
108 qir_TEX_DIRECT(c, indirect_offset, qir_uniform(c, QUNIFORM_UBO_ADDR, 0));
109 c->num_texture_samples++;
110 return qir_TEX_RESULT(c);
111 }
112
113 nir_ssa_def *vc4_nir_get_state_uniform(struct nir_builder *b,
114 enum quniform_contents contents)
115 {
116 nir_intrinsic_instr *intr =
117 nir_intrinsic_instr_create(b->shader,
118 nir_intrinsic_load_uniform);
119 intr->const_index[0] = (VC4_NIR_STATE_UNIFORM_OFFSET + contents) * 4;
120 intr->num_components = 1;
121 intr->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
122 nir_ssa_dest_init(&intr->instr, &intr->dest, 1, 32, NULL);
123 nir_builder_instr_insert(b, &intr->instr);
124 return &intr->dest.ssa;
125 }
126
127 nir_ssa_def *
128 vc4_nir_get_swizzled_channel(nir_builder *b, nir_ssa_def **srcs, int swiz)
129 {
130 switch (swiz) {
131 default:
132 case PIPE_SWIZZLE_NONE:
133 fprintf(stderr, "warning: unknown swizzle\n");
134 /* FALLTHROUGH */
135 case PIPE_SWIZZLE_0:
136 return nir_imm_float(b, 0.0);
137 case PIPE_SWIZZLE_1:
138 return nir_imm_float(b, 1.0);
139 case PIPE_SWIZZLE_X:
140 case PIPE_SWIZZLE_Y:
141 case PIPE_SWIZZLE_Z:
142 case PIPE_SWIZZLE_W:
143 return srcs[swiz];
144 }
145 }
146
147 static struct qreg *
148 ntq_init_ssa_def(struct vc4_compile *c, nir_ssa_def *def)
149 {
150 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
151 def->num_components);
152 _mesa_hash_table_insert(c->def_ht, def, qregs);
153 return qregs;
154 }
155
156 static void
157 ntq_store_dest(struct vc4_compile *c, nir_dest *dest, int chan,
158 struct qreg result)
159 {
160 if (dest->is_ssa) {
161 assert(chan < dest->ssa.num_components);
162
163 struct qreg *qregs;
164 struct hash_entry *entry =
165 _mesa_hash_table_search(c->def_ht, &dest->ssa);
166
167 if (entry)
168 qregs = entry->data;
169 else
170 qregs = ntq_init_ssa_def(c, &dest->ssa);
171
172 qregs[chan] = result;
173 } else {
174 nir_register *reg = dest->reg.reg;
175 assert(dest->reg.base_offset == 0);
176 assert(reg->num_array_elems == 0);
177 struct hash_entry *entry =
178 _mesa_hash_table_search(c->def_ht, reg);
179 struct qreg *qregs = entry->data;
180
181 /* Conditionally move the result to the destination if the
182 * channel is active.
183 */
184 if (c->execute.file != QFILE_NULL) {
185 qir_SF(c, c->execute);
186 qir_MOV_cond(c, QPU_COND_ZS, qregs[chan], result);
187 } else {
188 qir_MOV_dest(c, qregs[chan], result);
189 }
190 }
191 }
192
193 static struct qreg *
194 ntq_get_dest(struct vc4_compile *c, nir_dest *dest)
195 {
196 if (dest->is_ssa) {
197 struct qreg *qregs = ntq_init_ssa_def(c, &dest->ssa);
198 for (int i = 0; i < dest->ssa.num_components; i++)
199 qregs[i] = c->undef;
200 return qregs;
201 } else {
202 nir_register *reg = dest->reg.reg;
203 assert(dest->reg.base_offset == 0);
204 assert(reg->num_array_elems == 0);
205 struct hash_entry *entry =
206 _mesa_hash_table_search(c->def_ht, reg);
207 return entry->data;
208 }
209 }
210
211 static struct qreg
212 ntq_get_src(struct vc4_compile *c, nir_src src, int i)
213 {
214 struct hash_entry *entry;
215 if (src.is_ssa) {
216 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
217 assert(i < src.ssa->num_components);
218 } else {
219 nir_register *reg = src.reg.reg;
220 entry = _mesa_hash_table_search(c->def_ht, reg);
221 assert(reg->num_array_elems == 0);
222 assert(src.reg.base_offset == 0);
223 assert(i < reg->num_components);
224 }
225
226 struct qreg *qregs = entry->data;
227 return qregs[i];
228 }
229
230 static struct qreg
231 ntq_get_alu_src(struct vc4_compile *c, nir_alu_instr *instr,
232 unsigned src)
233 {
234 assert(util_is_power_of_two(instr->dest.write_mask));
235 unsigned chan = ffs(instr->dest.write_mask) - 1;
236 struct qreg r = ntq_get_src(c, instr->src[src].src,
237 instr->src[src].swizzle[chan]);
238
239 assert(!instr->src[src].abs);
240 assert(!instr->src[src].negate);
241
242 return r;
243 };
244
245 static inline struct qreg
246 qir_SAT(struct vc4_compile *c, struct qreg val)
247 {
248 return qir_FMAX(c,
249 qir_FMIN(c, val, qir_uniform_f(c, 1.0)),
250 qir_uniform_f(c, 0.0));
251 }
252
253 static struct qreg
254 ntq_rcp(struct vc4_compile *c, struct qreg x)
255 {
256 struct qreg r = qir_RCP(c, x);
257
258 /* Apply a Newton-Raphson step to improve the accuracy. */
259 r = qir_FMUL(c, r, qir_FSUB(c,
260 qir_uniform_f(c, 2.0),
261 qir_FMUL(c, x, r)));
262
263 return r;
264 }
265
266 static struct qreg
267 ntq_rsq(struct vc4_compile *c, struct qreg x)
268 {
269 struct qreg r = qir_RSQ(c, x);
270
271 /* Apply a Newton-Raphson step to improve the accuracy. */
272 r = qir_FMUL(c, r, qir_FSUB(c,
273 qir_uniform_f(c, 1.5),
274 qir_FMUL(c,
275 qir_uniform_f(c, 0.5),
276 qir_FMUL(c, x,
277 qir_FMUL(c, r, r)))));
278
279 return r;
280 }
281
282 static struct qreg
283 ntq_umul(struct vc4_compile *c, struct qreg src0, struct qreg src1)
284 {
285 struct qreg src0_hi = qir_SHR(c, src0,
286 qir_uniform_ui(c, 24));
287 struct qreg src1_hi = qir_SHR(c, src1,
288 qir_uniform_ui(c, 24));
289
290 struct qreg hilo = qir_MUL24(c, src0_hi, src1);
291 struct qreg lohi = qir_MUL24(c, src0, src1_hi);
292 struct qreg lolo = qir_MUL24(c, src0, src1);
293
294 return qir_ADD(c, lolo, qir_SHL(c,
295 qir_ADD(c, hilo, lohi),
296 qir_uniform_ui(c, 24)));
297 }
298
299 static struct qreg
300 ntq_scale_depth_texture(struct vc4_compile *c, struct qreg src)
301 {
302 struct qreg depthf = qir_ITOF(c, qir_SHR(c, src,
303 qir_uniform_ui(c, 8)));
304 return qir_FMUL(c, depthf, qir_uniform_f(c, 1.0f/0xffffff));
305 }
306
307 /**
308 * Emits a lowered TXF_MS from an MSAA texture.
309 *
310 * The addressing math has been lowered in NIR, and now we just need to read
311 * it like a UBO.
312 */
313 static void
314 ntq_emit_txf(struct vc4_compile *c, nir_tex_instr *instr)
315 {
316 uint32_t tile_width = 32;
317 uint32_t tile_height = 32;
318 uint32_t tile_size = (tile_height * tile_width *
319 VC4_MAX_SAMPLES * sizeof(uint32_t));
320
321 unsigned unit = instr->texture_index;
322 uint32_t w = align(c->key->tex[unit].msaa_width, tile_width);
323 uint32_t w_tiles = w / tile_width;
324 uint32_t h = align(c->key->tex[unit].msaa_height, tile_height);
325 uint32_t h_tiles = h / tile_height;
326 uint32_t size = w_tiles * h_tiles * tile_size;
327
328 struct qreg addr;
329 assert(instr->num_srcs == 1);
330 assert(instr->src[0].src_type == nir_tex_src_coord);
331 addr = ntq_get_src(c, instr->src[0].src, 0);
332
333 /* Perform the clamping required by kernel validation. */
334 addr = qir_MAX(c, addr, qir_uniform_ui(c, 0));
335 addr = qir_MIN(c, addr, qir_uniform_ui(c, size - 4));
336
337 qir_TEX_DIRECT(c, addr, qir_uniform(c, QUNIFORM_TEXTURE_MSAA_ADDR, unit));
338
339 struct qreg tex = qir_TEX_RESULT(c);
340 c->num_texture_samples++;
341
342 struct qreg dest[4];
343 enum pipe_format format = c->key->tex[unit].format;
344 if (util_format_is_depth_or_stencil(format)) {
345 struct qreg scaled = ntq_scale_depth_texture(c, tex);
346 for (int i = 0; i < 4; i++)
347 dest[i] = scaled;
348 } else {
349 for (int i = 0; i < 4; i++)
350 dest[i] = qir_UNPACK_8_F(c, tex, i);
351 }
352
353 for (int i = 0; i < 4; i++)
354 ntq_store_dest(c, &instr->dest, i, dest[i]);
355 }
356
357 static void
358 ntq_emit_tex(struct vc4_compile *c, nir_tex_instr *instr)
359 {
360 struct qreg s, t, r, lod, compare;
361 bool is_txb = false, is_txl = false;
362 unsigned unit = instr->texture_index;
363
364 if (instr->op == nir_texop_txf) {
365 ntq_emit_txf(c, instr);
366 return;
367 }
368
369 for (unsigned i = 0; i < instr->num_srcs; i++) {
370 switch (instr->src[i].src_type) {
371 case nir_tex_src_coord:
372 s = ntq_get_src(c, instr->src[i].src, 0);
373 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D)
374 t = qir_uniform_f(c, 0.5);
375 else
376 t = ntq_get_src(c, instr->src[i].src, 1);
377 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
378 r = ntq_get_src(c, instr->src[i].src, 2);
379 break;
380 case nir_tex_src_bias:
381 lod = ntq_get_src(c, instr->src[i].src, 0);
382 is_txb = true;
383 break;
384 case nir_tex_src_lod:
385 lod = ntq_get_src(c, instr->src[i].src, 0);
386 is_txl = true;
387 break;
388 case nir_tex_src_comparitor:
389 compare = ntq_get_src(c, instr->src[i].src, 0);
390 break;
391 default:
392 unreachable("unknown texture source");
393 }
394 }
395
396 struct qreg texture_u[] = {
397 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
398 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
399 qir_uniform(c, QUNIFORM_CONSTANT, 0),
400 qir_uniform(c, QUNIFORM_CONSTANT, 0),
401 };
402 uint32_t next_texture_u = 0;
403
404 /* There is no native support for GL texture rectangle coordinates, so
405 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
406 * 1]).
407 */
408 if (instr->sampler_dim == GLSL_SAMPLER_DIM_RECT) {
409 s = qir_FMUL(c, s,
410 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_X, unit));
411 t = qir_FMUL(c, t,
412 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_Y, unit));
413 }
414
415 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE || is_txl) {
416 texture_u[2] = qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2,
417 unit | (is_txl << 16));
418 }
419
420 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
421 qir_TEX_R(c, r, texture_u[next_texture_u++]);
422 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
423 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
424 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
425 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
426 qir_TEX_R(c, qir_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR, unit),
427 texture_u[next_texture_u++]);
428 }
429
430 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
431 s = qir_SAT(c, s);
432 }
433
434 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
435 t = qir_SAT(c, t);
436 }
437
438 qir_TEX_T(c, t, texture_u[next_texture_u++]);
439
440 if (is_txl || is_txb)
441 qir_TEX_B(c, lod, texture_u[next_texture_u++]);
442
443 qir_TEX_S(c, s, texture_u[next_texture_u++]);
444
445 c->num_texture_samples++;
446 struct qreg tex = qir_TEX_RESULT(c);
447
448 enum pipe_format format = c->key->tex[unit].format;
449
450 struct qreg *dest = ntq_get_dest(c, &instr->dest);
451 if (util_format_is_depth_or_stencil(format)) {
452 struct qreg normalized = ntq_scale_depth_texture(c, tex);
453 struct qreg depth_output;
454
455 struct qreg u0 = qir_uniform_f(c, 0.0f);
456 struct qreg u1 = qir_uniform_f(c, 1.0f);
457 if (c->key->tex[unit].compare_mode) {
458 switch (c->key->tex[unit].compare_func) {
459 case PIPE_FUNC_NEVER:
460 depth_output = qir_uniform_f(c, 0.0f);
461 break;
462 case PIPE_FUNC_ALWAYS:
463 depth_output = u1;
464 break;
465 case PIPE_FUNC_EQUAL:
466 qir_SF(c, qir_FSUB(c, compare, normalized));
467 depth_output = qir_SEL(c, QPU_COND_ZS, u1, u0);
468 break;
469 case PIPE_FUNC_NOTEQUAL:
470 qir_SF(c, qir_FSUB(c, compare, normalized));
471 depth_output = qir_SEL(c, QPU_COND_ZC, u1, u0);
472 break;
473 case PIPE_FUNC_GREATER:
474 qir_SF(c, qir_FSUB(c, compare, normalized));
475 depth_output = qir_SEL(c, QPU_COND_NC, u1, u0);
476 break;
477 case PIPE_FUNC_GEQUAL:
478 qir_SF(c, qir_FSUB(c, normalized, compare));
479 depth_output = qir_SEL(c, QPU_COND_NS, u1, u0);
480 break;
481 case PIPE_FUNC_LESS:
482 qir_SF(c, qir_FSUB(c, compare, normalized));
483 depth_output = qir_SEL(c, QPU_COND_NS, u1, u0);
484 break;
485 case PIPE_FUNC_LEQUAL:
486 qir_SF(c, qir_FSUB(c, normalized, compare));
487 depth_output = qir_SEL(c, QPU_COND_NC, u1, u0);
488 break;
489 }
490 } else {
491 depth_output = normalized;
492 }
493
494 for (int i = 0; i < 4; i++)
495 dest[i] = depth_output;
496 } else {
497 for (int i = 0; i < 4; i++)
498 dest[i] = qir_UNPACK_8_F(c, tex, i);
499 }
500 }
501
502 /**
503 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
504 * to zero).
505 */
506 static struct qreg
507 ntq_ffract(struct vc4_compile *c, struct qreg src)
508 {
509 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
510 struct qreg diff = qir_FSUB(c, src, trunc);
511 qir_SF(c, diff);
512 return qir_SEL(c, QPU_COND_NS,
513 qir_FADD(c, diff, qir_uniform_f(c, 1.0)), diff);
514 }
515
516 /**
517 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
518 * zero).
519 */
520 static struct qreg
521 ntq_ffloor(struct vc4_compile *c, struct qreg src)
522 {
523 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
524
525 /* This will be < 0 if we truncated and the truncation was of a value
526 * that was < 0 in the first place.
527 */
528 qir_SF(c, qir_FSUB(c, src, trunc));
529
530 return qir_SEL(c, QPU_COND_NS,
531 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)), trunc);
532 }
533
534 /**
535 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
536 * zero).
537 */
538 static struct qreg
539 ntq_fceil(struct vc4_compile *c, struct qreg src)
540 {
541 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
542
543 /* This will be < 0 if we truncated and the truncation was of a value
544 * that was > 0 in the first place.
545 */
546 qir_SF(c, qir_FSUB(c, trunc, src));
547
548 return qir_SEL(c, QPU_COND_NS,
549 qir_FADD(c, trunc, qir_uniform_f(c, 1.0)), trunc);
550 }
551
552 static struct qreg
553 ntq_fsin(struct vc4_compile *c, struct qreg src)
554 {
555 float coeff[] = {
556 -2.0 * M_PI,
557 pow(2.0 * M_PI, 3) / (3 * 2 * 1),
558 -pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
559 pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
560 -pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
561 };
562
563 struct qreg scaled_x =
564 qir_FMUL(c,
565 src,
566 qir_uniform_f(c, 1.0 / (M_PI * 2.0)));
567
568 struct qreg x = qir_FADD(c,
569 ntq_ffract(c, scaled_x),
570 qir_uniform_f(c, -0.5));
571 struct qreg x2 = qir_FMUL(c, x, x);
572 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
573 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
574 x = qir_FMUL(c, x, x2);
575 sum = qir_FADD(c,
576 sum,
577 qir_FMUL(c,
578 x,
579 qir_uniform_f(c, coeff[i])));
580 }
581 return sum;
582 }
583
584 static struct qreg
585 ntq_fcos(struct vc4_compile *c, struct qreg src)
586 {
587 float coeff[] = {
588 -1.0f,
589 pow(2.0 * M_PI, 2) / (2 * 1),
590 -pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
591 pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
592 -pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
593 pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
594 };
595
596 struct qreg scaled_x =
597 qir_FMUL(c, src,
598 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
599 struct qreg x_frac = qir_FADD(c,
600 ntq_ffract(c, scaled_x),
601 qir_uniform_f(c, -0.5));
602
603 struct qreg sum = qir_uniform_f(c, coeff[0]);
604 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
605 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
606 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
607 if (i != 1)
608 x = qir_FMUL(c, x, x2);
609
610 struct qreg mul = qir_FMUL(c,
611 x,
612 qir_uniform_f(c, coeff[i]));
613 if (i == 0)
614 sum = mul;
615 else
616 sum = qir_FADD(c, sum, mul);
617 }
618 return sum;
619 }
620
621 static struct qreg
622 ntq_fsign(struct vc4_compile *c, struct qreg src)
623 {
624 struct qreg t = qir_get_temp(c);
625
626 qir_SF(c, src);
627 qir_MOV_dest(c, t, qir_uniform_f(c, 0.0));
628 qir_MOV_dest(c, t, qir_uniform_f(c, 1.0))->cond = QPU_COND_ZC;
629 qir_MOV_dest(c, t, qir_uniform_f(c, -1.0))->cond = QPU_COND_NS;
630 return t;
631 }
632
633 static void
634 emit_vertex_input(struct vc4_compile *c, int attr)
635 {
636 enum pipe_format format = c->vs_key->attr_formats[attr];
637 uint32_t attr_size = util_format_get_blocksize(format);
638
639 c->vattr_sizes[attr] = align(attr_size, 4);
640 for (int i = 0; i < align(attr_size, 4) / 4; i++) {
641 c->inputs[attr * 4 + i] =
642 qir_MOV(c, qir_reg(QFILE_VPM, attr * 4 + i));
643 c->num_inputs++;
644 }
645 }
646
647 static void
648 emit_fragcoord_input(struct vc4_compile *c, int attr)
649 {
650 c->inputs[attr * 4 + 0] = qir_ITOF(c, qir_reg(QFILE_FRAG_X, 0));
651 c->inputs[attr * 4 + 1] = qir_ITOF(c, qir_reg(QFILE_FRAG_Y, 0));
652 c->inputs[attr * 4 + 2] =
653 qir_FMUL(c,
654 qir_ITOF(c, qir_FRAG_Z(c)),
655 qir_uniform_f(c, 1.0 / 0xffffff));
656 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
657 }
658
659 static struct qreg
660 emit_fragment_varying(struct vc4_compile *c, gl_varying_slot slot,
661 uint8_t swizzle)
662 {
663 uint32_t i = c->num_input_slots++;
664 struct qreg vary = {
665 QFILE_VARY,
666 i
667 };
668
669 if (c->num_input_slots >= c->input_slots_array_size) {
670 c->input_slots_array_size =
671 MAX2(4, c->input_slots_array_size * 2);
672
673 c->input_slots = reralloc(c, c->input_slots,
674 struct vc4_varying_slot,
675 c->input_slots_array_size);
676 }
677
678 c->input_slots[i].slot = slot;
679 c->input_slots[i].swizzle = swizzle;
680
681 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
682 }
683
684 static void
685 emit_fragment_input(struct vc4_compile *c, int attr, gl_varying_slot slot)
686 {
687 for (int i = 0; i < 4; i++) {
688 c->inputs[attr * 4 + i] =
689 emit_fragment_varying(c, slot, i);
690 c->num_inputs++;
691 }
692 }
693
694 static void
695 add_output(struct vc4_compile *c,
696 uint32_t decl_offset,
697 uint8_t slot,
698 uint8_t swizzle)
699 {
700 uint32_t old_array_size = c->outputs_array_size;
701 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
702 decl_offset + 1);
703
704 if (old_array_size != c->outputs_array_size) {
705 c->output_slots = reralloc(c,
706 c->output_slots,
707 struct vc4_varying_slot,
708 c->outputs_array_size);
709 }
710
711 c->output_slots[decl_offset].slot = slot;
712 c->output_slots[decl_offset].swizzle = swizzle;
713 }
714
715 static void
716 declare_uniform_range(struct vc4_compile *c, uint32_t start, uint32_t size)
717 {
718 unsigned array_id = c->num_uniform_ranges++;
719 if (array_id >= c->ubo_ranges_array_size) {
720 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
721 array_id + 1);
722 c->ubo_ranges = reralloc(c, c->ubo_ranges,
723 struct vc4_compiler_ubo_range,
724 c->ubo_ranges_array_size);
725 }
726
727 c->ubo_ranges[array_id].dst_offset = 0;
728 c->ubo_ranges[array_id].src_offset = start;
729 c->ubo_ranges[array_id].size = size;
730 c->ubo_ranges[array_id].used = false;
731 }
732
733 static bool
734 ntq_src_is_only_ssa_def_user(nir_src *src)
735 {
736 if (!src->is_ssa)
737 return false;
738
739 if (!list_empty(&src->ssa->if_uses))
740 return false;
741
742 return (src->ssa->uses.next == &src->use_link &&
743 src->ssa->uses.next->next == &src->ssa->uses);
744 }
745
746 /**
747 * In general, emits a nir_pack_unorm_4x8 as a series of MOVs with the pack
748 * bit set.
749 *
750 * However, as an optimization, it tries to find the instructions generating
751 * the sources to be packed and just emit the pack flag there, if possible.
752 */
753 static void
754 ntq_emit_pack_unorm_4x8(struct vc4_compile *c, nir_alu_instr *instr)
755 {
756 struct qreg result = qir_get_temp(c);
757 struct nir_alu_instr *vec4 = NULL;
758
759 /* If packing from a vec4 op (as expected), identify it so that we can
760 * peek back at what generated its sources.
761 */
762 if (instr->src[0].src.is_ssa &&
763 instr->src[0].src.ssa->parent_instr->type == nir_instr_type_alu &&
764 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr)->op ==
765 nir_op_vec4) {
766 vec4 = nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
767 }
768
769 /* If the pack is replicating the same channel 4 times, use the 8888
770 * pack flag. This is common for blending using the alpha
771 * channel.
772 */
773 if (instr->src[0].swizzle[0] == instr->src[0].swizzle[1] &&
774 instr->src[0].swizzle[0] == instr->src[0].swizzle[2] &&
775 instr->src[0].swizzle[0] == instr->src[0].swizzle[3]) {
776 struct qreg rep = ntq_get_src(c,
777 instr->src[0].src,
778 instr->src[0].swizzle[0]);
779 ntq_store_dest(c, &instr->dest.dest, 0, qir_PACK_8888_F(c, rep));
780 return;
781 }
782
783 for (int i = 0; i < 4; i++) {
784 int swiz = instr->src[0].swizzle[i];
785 struct qreg src;
786 if (vec4) {
787 src = ntq_get_src(c, vec4->src[swiz].src,
788 vec4->src[swiz].swizzle[0]);
789 } else {
790 src = ntq_get_src(c, instr->src[0].src, swiz);
791 }
792
793 if (vec4 &&
794 ntq_src_is_only_ssa_def_user(&vec4->src[swiz].src) &&
795 src.file == QFILE_TEMP &&
796 c->defs[src.index] &&
797 qir_is_mul(c->defs[src.index]) &&
798 !c->defs[src.index]->dst.pack) {
799 struct qinst *rewrite = c->defs[src.index];
800 c->defs[src.index] = NULL;
801 rewrite->dst = result;
802 rewrite->dst.pack = QPU_PACK_MUL_8A + i;
803 continue;
804 }
805
806 qir_PACK_8_F(c, result, src, i);
807 }
808
809 ntq_store_dest(c, &instr->dest.dest, 0, result);
810 }
811
812 /** Handles sign-extended bitfield extracts for 16 bits. */
813 static struct qreg
814 ntq_emit_ibfe(struct vc4_compile *c, struct qreg base, struct qreg offset,
815 struct qreg bits)
816 {
817 assert(bits.file == QFILE_UNIF &&
818 c->uniform_contents[bits.index] == QUNIFORM_CONSTANT &&
819 c->uniform_data[bits.index] == 16);
820
821 assert(offset.file == QFILE_UNIF &&
822 c->uniform_contents[offset.index] == QUNIFORM_CONSTANT);
823 int offset_bit = c->uniform_data[offset.index];
824 assert(offset_bit % 16 == 0);
825
826 return qir_UNPACK_16_I(c, base, offset_bit / 16);
827 }
828
829 /** Handles unsigned bitfield extracts for 8 bits. */
830 static struct qreg
831 ntq_emit_ubfe(struct vc4_compile *c, struct qreg base, struct qreg offset,
832 struct qreg bits)
833 {
834 assert(bits.file == QFILE_UNIF &&
835 c->uniform_contents[bits.index] == QUNIFORM_CONSTANT &&
836 c->uniform_data[bits.index] == 8);
837
838 assert(offset.file == QFILE_UNIF &&
839 c->uniform_contents[offset.index] == QUNIFORM_CONSTANT);
840 int offset_bit = c->uniform_data[offset.index];
841 assert(offset_bit % 8 == 0);
842
843 return qir_UNPACK_8_I(c, base, offset_bit / 8);
844 }
845
846 /**
847 * If compare_instr is a valid comparison instruction, emits the
848 * compare_instr's comparison and returns the sel_instr's return value based
849 * on the compare_instr's result.
850 */
851 static bool
852 ntq_emit_comparison(struct vc4_compile *c, struct qreg *dest,
853 nir_alu_instr *compare_instr,
854 nir_alu_instr *sel_instr)
855 {
856 enum qpu_cond cond;
857
858 switch (compare_instr->op) {
859 case nir_op_feq:
860 case nir_op_ieq:
861 case nir_op_seq:
862 cond = QPU_COND_ZS;
863 break;
864 case nir_op_fne:
865 case nir_op_ine:
866 case nir_op_sne:
867 cond = QPU_COND_ZC;
868 break;
869 case nir_op_fge:
870 case nir_op_ige:
871 case nir_op_uge:
872 case nir_op_sge:
873 cond = QPU_COND_NC;
874 break;
875 case nir_op_flt:
876 case nir_op_ilt:
877 case nir_op_slt:
878 cond = QPU_COND_NS;
879 break;
880 default:
881 return false;
882 }
883
884 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
885 struct qreg src1 = ntq_get_alu_src(c, compare_instr, 1);
886
887 unsigned unsized_type =
888 nir_alu_type_get_base_type(nir_op_infos[compare_instr->op].input_types[0]);
889 if (unsized_type == nir_type_float)
890 qir_SF(c, qir_FSUB(c, src0, src1));
891 else
892 qir_SF(c, qir_SUB(c, src0, src1));
893
894 switch (sel_instr->op) {
895 case nir_op_seq:
896 case nir_op_sne:
897 case nir_op_sge:
898 case nir_op_slt:
899 *dest = qir_SEL(c, cond,
900 qir_uniform_f(c, 1.0), qir_uniform_f(c, 0.0));
901 break;
902
903 case nir_op_bcsel:
904 *dest = qir_SEL(c, cond,
905 ntq_get_alu_src(c, sel_instr, 1),
906 ntq_get_alu_src(c, sel_instr, 2));
907 break;
908
909 default:
910 *dest = qir_SEL(c, cond,
911 qir_uniform_ui(c, ~0), qir_uniform_ui(c, 0));
912 break;
913 }
914
915 return true;
916 }
917
918 /**
919 * Attempts to fold a comparison generating a boolean result into the
920 * condition code for selecting between two values, instead of comparing the
921 * boolean result against 0 to generate the condition code.
922 */
923 static struct qreg ntq_emit_bcsel(struct vc4_compile *c, nir_alu_instr *instr,
924 struct qreg *src)
925 {
926 if (!instr->src[0].src.is_ssa)
927 goto out;
928 nir_alu_instr *compare =
929 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
930 if (!compare)
931 goto out;
932
933 struct qreg dest;
934 if (ntq_emit_comparison(c, &dest, compare, instr))
935 return dest;
936
937 out:
938 qir_SF(c, src[0]);
939 return qir_SEL(c, QPU_COND_NS, src[1], src[2]);
940 }
941
942 static void
943 ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
944 {
945 /* This should always be lowered to ALU operations for VC4. */
946 assert(!instr->dest.saturate);
947
948 /* Vectors are special in that they have non-scalarized writemasks,
949 * and just take the first swizzle channel for each argument in order
950 * into each writemask channel.
951 */
952 if (instr->op == nir_op_vec2 ||
953 instr->op == nir_op_vec3 ||
954 instr->op == nir_op_vec4) {
955 struct qreg srcs[4];
956 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
957 srcs[i] = ntq_get_src(c, instr->src[i].src,
958 instr->src[i].swizzle[0]);
959 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
960 ntq_store_dest(c, &instr->dest.dest, i, srcs[i]);
961 return;
962 }
963
964 if (instr->op == nir_op_pack_unorm_4x8) {
965 ntq_emit_pack_unorm_4x8(c, instr);
966 return;
967 }
968
969 if (instr->op == nir_op_unpack_unorm_4x8) {
970 struct qreg src = ntq_get_src(c, instr->src[0].src,
971 instr->src[0].swizzle[0]);
972 for (int i = 0; i < 4; i++) {
973 if (instr->dest.write_mask & (1 << i))
974 ntq_store_dest(c, &instr->dest.dest, i,
975 qir_UNPACK_8_F(c, src, i));
976 }
977 return;
978 }
979
980 /* General case: We can just grab the one used channel per src. */
981 struct qreg src[nir_op_infos[instr->op].num_inputs];
982 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
983 src[i] = ntq_get_alu_src(c, instr, i);
984 }
985
986 struct qreg result;
987
988 switch (instr->op) {
989 case nir_op_fmov:
990 case nir_op_imov:
991 result = qir_MOV(c, src[0]);
992 break;
993 case nir_op_fmul:
994 result = qir_FMUL(c, src[0], src[1]);
995 break;
996 case nir_op_fadd:
997 result = qir_FADD(c, src[0], src[1]);
998 break;
999 case nir_op_fsub:
1000 result = qir_FSUB(c, src[0], src[1]);
1001 break;
1002 case nir_op_fmin:
1003 result = qir_FMIN(c, src[0], src[1]);
1004 break;
1005 case nir_op_fmax:
1006 result = qir_FMAX(c, src[0], src[1]);
1007 break;
1008
1009 case nir_op_f2i:
1010 case nir_op_f2u:
1011 result = qir_FTOI(c, src[0]);
1012 break;
1013 case nir_op_i2f:
1014 case nir_op_u2f:
1015 result = qir_ITOF(c, src[0]);
1016 break;
1017 case nir_op_b2f:
1018 result = qir_AND(c, src[0], qir_uniform_f(c, 1.0));
1019 break;
1020 case nir_op_b2i:
1021 result = qir_AND(c, src[0], qir_uniform_ui(c, 1));
1022 break;
1023 case nir_op_i2b:
1024 case nir_op_f2b:
1025 qir_SF(c, src[0]);
1026 result = qir_SEL(c, QPU_COND_ZC,
1027 qir_uniform_ui(c, ~0),
1028 qir_uniform_ui(c, 0));
1029 break;
1030
1031 case nir_op_iadd:
1032 result = qir_ADD(c, src[0], src[1]);
1033 break;
1034 case nir_op_ushr:
1035 result = qir_SHR(c, src[0], src[1]);
1036 break;
1037 case nir_op_isub:
1038 result = qir_SUB(c, src[0], src[1]);
1039 break;
1040 case nir_op_ishr:
1041 result = qir_ASR(c, src[0], src[1]);
1042 break;
1043 case nir_op_ishl:
1044 result = qir_SHL(c, src[0], src[1]);
1045 break;
1046 case nir_op_imin:
1047 result = qir_MIN(c, src[0], src[1]);
1048 break;
1049 case nir_op_imax:
1050 result = qir_MAX(c, src[0], src[1]);
1051 break;
1052 case nir_op_iand:
1053 result = qir_AND(c, src[0], src[1]);
1054 break;
1055 case nir_op_ior:
1056 result = qir_OR(c, src[0], src[1]);
1057 break;
1058 case nir_op_ixor:
1059 result = qir_XOR(c, src[0], src[1]);
1060 break;
1061 case nir_op_inot:
1062 result = qir_NOT(c, src[0]);
1063 break;
1064
1065 case nir_op_imul:
1066 result = ntq_umul(c, src[0], src[1]);
1067 break;
1068
1069 case nir_op_seq:
1070 case nir_op_sne:
1071 case nir_op_sge:
1072 case nir_op_slt:
1073 case nir_op_feq:
1074 case nir_op_fne:
1075 case nir_op_fge:
1076 case nir_op_flt:
1077 case nir_op_ieq:
1078 case nir_op_ine:
1079 case nir_op_ige:
1080 case nir_op_uge:
1081 case nir_op_ilt:
1082 if (!ntq_emit_comparison(c, &result, instr, instr)) {
1083 fprintf(stderr, "Bad comparison instruction\n");
1084 }
1085 break;
1086
1087 case nir_op_bcsel:
1088 result = ntq_emit_bcsel(c, instr, src);
1089 break;
1090 case nir_op_fcsel:
1091 qir_SF(c, src[0]);
1092 result = qir_SEL(c, QPU_COND_ZC, src[1], src[2]);
1093 break;
1094
1095 case nir_op_frcp:
1096 result = ntq_rcp(c, src[0]);
1097 break;
1098 case nir_op_frsq:
1099 result = ntq_rsq(c, src[0]);
1100 break;
1101 case nir_op_fexp2:
1102 result = qir_EXP2(c, src[0]);
1103 break;
1104 case nir_op_flog2:
1105 result = qir_LOG2(c, src[0]);
1106 break;
1107
1108 case nir_op_ftrunc:
1109 result = qir_ITOF(c, qir_FTOI(c, src[0]));
1110 break;
1111 case nir_op_fceil:
1112 result = ntq_fceil(c, src[0]);
1113 break;
1114 case nir_op_ffract:
1115 result = ntq_ffract(c, src[0]);
1116 break;
1117 case nir_op_ffloor:
1118 result = ntq_ffloor(c, src[0]);
1119 break;
1120
1121 case nir_op_fsin:
1122 result = ntq_fsin(c, src[0]);
1123 break;
1124 case nir_op_fcos:
1125 result = ntq_fcos(c, src[0]);
1126 break;
1127
1128 case nir_op_fsign:
1129 result = ntq_fsign(c, src[0]);
1130 break;
1131
1132 case nir_op_fabs:
1133 result = qir_FMAXABS(c, src[0], src[0]);
1134 break;
1135 case nir_op_iabs:
1136 result = qir_MAX(c, src[0],
1137 qir_SUB(c, qir_uniform_ui(c, 0), src[0]));
1138 break;
1139
1140 case nir_op_ibitfield_extract:
1141 result = ntq_emit_ibfe(c, src[0], src[1], src[2]);
1142 break;
1143
1144 case nir_op_ubitfield_extract:
1145 result = ntq_emit_ubfe(c, src[0], src[1], src[2]);
1146 break;
1147
1148 case nir_op_usadd_4x8:
1149 result = qir_V8ADDS(c, src[0], src[1]);
1150 break;
1151
1152 case nir_op_ussub_4x8:
1153 result = qir_V8SUBS(c, src[0], src[1]);
1154 break;
1155
1156 case nir_op_umin_4x8:
1157 result = qir_V8MIN(c, src[0], src[1]);
1158 break;
1159
1160 case nir_op_umax_4x8:
1161 result = qir_V8MAX(c, src[0], src[1]);
1162 break;
1163
1164 case nir_op_umul_unorm_4x8:
1165 result = qir_V8MULD(c, src[0], src[1]);
1166 break;
1167
1168 default:
1169 fprintf(stderr, "unknown NIR ALU inst: ");
1170 nir_print_instr(&instr->instr, stderr);
1171 fprintf(stderr, "\n");
1172 abort();
1173 }
1174
1175 /* We have a scalar result, so the instruction should only have a
1176 * single channel written to.
1177 */
1178 assert(util_is_power_of_two(instr->dest.write_mask));
1179 ntq_store_dest(c, &instr->dest.dest,
1180 ffs(instr->dest.write_mask) - 1, result);
1181 }
1182
1183 static void
1184 emit_frag_end(struct vc4_compile *c)
1185 {
1186 struct qreg color;
1187 if (c->output_color_index != -1) {
1188 color = c->outputs[c->output_color_index];
1189 } else {
1190 color = qir_uniform_ui(c, 0);
1191 }
1192
1193 uint32_t discard_cond = QPU_COND_ALWAYS;
1194 if (c->discard.file != QFILE_NULL) {
1195 qir_SF(c, c->discard);
1196 discard_cond = QPU_COND_ZS;
1197 }
1198
1199 if (c->fs_key->stencil_enabled) {
1200 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1201 qir_uniform(c, QUNIFORM_STENCIL, 0));
1202 if (c->fs_key->stencil_twoside) {
1203 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1204 qir_uniform(c, QUNIFORM_STENCIL, 1));
1205 }
1206 if (c->fs_key->stencil_full_writemasks) {
1207 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1208 qir_uniform(c, QUNIFORM_STENCIL, 2));
1209 }
1210 }
1211
1212 if (c->output_sample_mask_index != -1) {
1213 qir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1214 }
1215
1216 if (c->fs_key->depth_enabled) {
1217 if (c->output_position_index != -1) {
1218 qir_FTOI_dest(c, qir_reg(QFILE_TLB_Z_WRITE, 0),
1219 qir_FMUL(c,
1220 c->outputs[c->output_position_index + 2],
1221 qir_uniform_f(c, 0xffffff)))->cond = discard_cond;
1222 } else {
1223 qir_MOV_dest(c, qir_reg(QFILE_TLB_Z_WRITE, 0),
1224 qir_FRAG_Z(c))->cond = discard_cond;
1225 }
1226 }
1227
1228 if (!c->msaa_per_sample_output) {
1229 qir_MOV_dest(c, qir_reg(QFILE_TLB_COLOR_WRITE, 0),
1230 color)->cond = discard_cond;
1231 } else {
1232 for (int i = 0; i < VC4_MAX_SAMPLES; i++) {
1233 qir_MOV_dest(c, qir_reg(QFILE_TLB_COLOR_WRITE_MS, 0),
1234 c->sample_colors[i])->cond = discard_cond;
1235 }
1236 }
1237 }
1238
1239 static void
1240 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1241 {
1242 struct qreg packed = qir_get_temp(c);
1243
1244 for (int i = 0; i < 2; i++) {
1245 struct qreg scale =
1246 qir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1247
1248 struct qreg packed_chan = packed;
1249 packed_chan.pack = QPU_PACK_A_16A + i;
1250
1251 qir_FTOI_dest(c, packed_chan,
1252 qir_FMUL(c,
1253 qir_FMUL(c,
1254 c->outputs[c->output_position_index + i],
1255 scale),
1256 rcp_w));
1257 }
1258
1259 qir_VPM_WRITE(c, packed);
1260 }
1261
1262 static void
1263 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1264 {
1265 struct qreg zscale = qir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1266 struct qreg zoffset = qir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1267
1268 qir_VPM_WRITE(c, qir_FADD(c, qir_FMUL(c, qir_FMUL(c,
1269 c->outputs[c->output_position_index + 2],
1270 zscale),
1271 rcp_w),
1272 zoffset));
1273 }
1274
1275 static void
1276 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1277 {
1278 qir_VPM_WRITE(c, rcp_w);
1279 }
1280
1281 static void
1282 emit_point_size_write(struct vc4_compile *c)
1283 {
1284 struct qreg point_size;
1285
1286 if (c->output_point_size_index != -1)
1287 point_size = c->outputs[c->output_point_size_index];
1288 else
1289 point_size = qir_uniform_f(c, 1.0);
1290
1291 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1292 * BCM21553).
1293 */
1294 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1295
1296 qir_VPM_WRITE(c, point_size);
1297 }
1298
1299 /**
1300 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1301 *
1302 * The simulator insists that there be at least one vertex attribute, so
1303 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1304 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1305 * to consume it here.
1306 */
1307 static void
1308 emit_stub_vpm_read(struct vc4_compile *c)
1309 {
1310 if (c->num_inputs)
1311 return;
1312
1313 c->vattr_sizes[0] = 4;
1314 (void)qir_MOV(c, qir_reg(QFILE_VPM, 0));
1315 c->num_inputs++;
1316 }
1317
1318 static void
1319 emit_vert_end(struct vc4_compile *c,
1320 struct vc4_varying_slot *fs_inputs,
1321 uint32_t num_fs_inputs)
1322 {
1323 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1324
1325 emit_stub_vpm_read(c);
1326
1327 emit_scaled_viewport_write(c, rcp_w);
1328 emit_zs_write(c, rcp_w);
1329 emit_rcp_wc_write(c, rcp_w);
1330 if (c->vs_key->per_vertex_point_size)
1331 emit_point_size_write(c);
1332
1333 for (int i = 0; i < num_fs_inputs; i++) {
1334 struct vc4_varying_slot *input = &fs_inputs[i];
1335 int j;
1336
1337 for (j = 0; j < c->num_outputs; j++) {
1338 struct vc4_varying_slot *output =
1339 &c->output_slots[j];
1340
1341 if (input->slot == output->slot &&
1342 input->swizzle == output->swizzle) {
1343 qir_VPM_WRITE(c, c->outputs[j]);
1344 break;
1345 }
1346 }
1347 /* Emit padding if we didn't find a declared VS output for
1348 * this FS input.
1349 */
1350 if (j == c->num_outputs)
1351 qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));
1352 }
1353 }
1354
1355 static void
1356 emit_coord_end(struct vc4_compile *c)
1357 {
1358 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1359
1360 emit_stub_vpm_read(c);
1361
1362 for (int i = 0; i < 4; i++)
1363 qir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
1364
1365 emit_scaled_viewport_write(c, rcp_w);
1366 emit_zs_write(c, rcp_w);
1367 emit_rcp_wc_write(c, rcp_w);
1368 if (c->vs_key->per_vertex_point_size)
1369 emit_point_size_write(c);
1370 }
1371
1372 static void
1373 vc4_optimize_nir(struct nir_shader *s)
1374 {
1375 bool progress;
1376
1377 do {
1378 progress = false;
1379
1380 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1381 NIR_PASS_V(s, nir_lower_alu_to_scalar);
1382 NIR_PASS_V(s, nir_lower_phis_to_scalar);
1383
1384 NIR_PASS(progress, s, nir_copy_prop);
1385 NIR_PASS(progress, s, nir_opt_remove_phis);
1386 NIR_PASS(progress, s, nir_opt_dce);
1387 NIR_PASS(progress, s, nir_opt_dead_cf);
1388 NIR_PASS(progress, s, nir_opt_cse);
1389 NIR_PASS(progress, s, nir_opt_peephole_select);
1390 NIR_PASS(progress, s, nir_opt_algebraic);
1391 NIR_PASS(progress, s, nir_opt_constant_folding);
1392 NIR_PASS(progress, s, nir_opt_undef);
1393 } while (progress);
1394 }
1395
1396 static int
1397 driver_location_compare(const void *in_a, const void *in_b)
1398 {
1399 const nir_variable *const *a = in_a;
1400 const nir_variable *const *b = in_b;
1401
1402 return (*a)->data.driver_location - (*b)->data.driver_location;
1403 }
1404
1405 static void
1406 ntq_setup_inputs(struct vc4_compile *c)
1407 {
1408 unsigned num_entries = 0;
1409 nir_foreach_variable(var, &c->s->inputs)
1410 num_entries++;
1411
1412 nir_variable *vars[num_entries];
1413
1414 unsigned i = 0;
1415 nir_foreach_variable(var, &c->s->inputs)
1416 vars[i++] = var;
1417
1418 /* Sort the variables so that we emit the input setup in
1419 * driver_location order. This is required for VPM reads, whose data
1420 * is fetched into the VPM in driver_location (TGSI register index)
1421 * order.
1422 */
1423 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1424
1425 for (unsigned i = 0; i < num_entries; i++) {
1426 nir_variable *var = vars[i];
1427 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1428 unsigned loc = var->data.driver_location;
1429
1430 assert(array_len == 1);
1431 (void)array_len;
1432 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1433 (loc + 1) * 4);
1434
1435 if (c->stage == QSTAGE_FRAG) {
1436 if (var->data.location == VARYING_SLOT_POS) {
1437 emit_fragcoord_input(c, loc);
1438 } else if (var->data.location >= VARYING_SLOT_VAR0 &&
1439 (c->fs_key->point_sprite_mask &
1440 (1 << (var->data.location -
1441 VARYING_SLOT_VAR0)))) {
1442 c->inputs[loc * 4 + 0] = c->point_x;
1443 c->inputs[loc * 4 + 1] = c->point_y;
1444 } else {
1445 emit_fragment_input(c, loc, var->data.location);
1446 }
1447 } else {
1448 emit_vertex_input(c, loc);
1449 }
1450 }
1451 }
1452
1453 static void
1454 ntq_setup_outputs(struct vc4_compile *c)
1455 {
1456 nir_foreach_variable(var, &c->s->outputs) {
1457 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1458 unsigned loc = var->data.driver_location * 4;
1459
1460 assert(array_len == 1);
1461 (void)array_len;
1462
1463 for (int i = 0; i < 4; i++)
1464 add_output(c, loc + i, var->data.location, i);
1465
1466 if (c->stage == QSTAGE_FRAG) {
1467 switch (var->data.location) {
1468 case FRAG_RESULT_COLOR:
1469 case FRAG_RESULT_DATA0:
1470 c->output_color_index = loc;
1471 break;
1472 case FRAG_RESULT_DEPTH:
1473 c->output_position_index = loc;
1474 break;
1475 case FRAG_RESULT_SAMPLE_MASK:
1476 c->output_sample_mask_index = loc;
1477 break;
1478 }
1479 } else {
1480 switch (var->data.location) {
1481 case VARYING_SLOT_POS:
1482 c->output_position_index = loc;
1483 break;
1484 case VARYING_SLOT_PSIZ:
1485 c->output_point_size_index = loc;
1486 break;
1487 }
1488 }
1489 }
1490 }
1491
1492 static void
1493 ntq_setup_uniforms(struct vc4_compile *c)
1494 {
1495 nir_foreach_variable(var, &c->s->uniforms) {
1496 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1497 unsigned array_elem_size = 4 * sizeof(float);
1498
1499 declare_uniform_range(c, var->data.driver_location * array_elem_size,
1500 array_len * array_elem_size);
1501
1502 }
1503 }
1504
1505 /**
1506 * Sets up the mapping from nir_register to struct qreg *.
1507 *
1508 * Each nir_register gets a struct qreg per 32-bit component being stored.
1509 */
1510 static void
1511 ntq_setup_registers(struct vc4_compile *c, struct exec_list *list)
1512 {
1513 foreach_list_typed(nir_register, nir_reg, node, list) {
1514 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1515 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1516 array_len *
1517 nir_reg->num_components);
1518
1519 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1520
1521 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1522 qregs[i] = qir_get_temp(c);
1523 }
1524 }
1525
1526 static void
1527 ntq_emit_load_const(struct vc4_compile *c, nir_load_const_instr *instr)
1528 {
1529 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1530 for (int i = 0; i < instr->def.num_components; i++)
1531 qregs[i] = qir_uniform_ui(c, instr->value.u32[i]);
1532
1533 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1534 }
1535
1536 static void
1537 ntq_emit_ssa_undef(struct vc4_compile *c, nir_ssa_undef_instr *instr)
1538 {
1539 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1540
1541 /* QIR needs there to be *some* value, so pick 0 (same as for
1542 * ntq_setup_registers().
1543 */
1544 for (int i = 0; i < instr->def.num_components; i++)
1545 qregs[i] = qir_uniform_ui(c, 0);
1546 }
1547
1548 static void
1549 ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
1550 {
1551 nir_const_value *const_offset;
1552 unsigned offset;
1553
1554 switch (instr->intrinsic) {
1555 case nir_intrinsic_load_uniform:
1556 assert(instr->num_components == 1);
1557 const_offset = nir_src_as_const_value(instr->src[0]);
1558 if (const_offset) {
1559 offset = instr->const_index[0] + const_offset->u32[0];
1560 assert(offset % 4 == 0);
1561 /* We need dwords */
1562 offset = offset / 4;
1563 if (offset < VC4_NIR_STATE_UNIFORM_OFFSET) {
1564 ntq_store_dest(c, &instr->dest, 0,
1565 qir_uniform(c, QUNIFORM_UNIFORM,
1566 offset));
1567 } else {
1568 ntq_store_dest(c, &instr->dest, 0,
1569 qir_uniform(c, offset -
1570 VC4_NIR_STATE_UNIFORM_OFFSET,
1571 0));
1572 }
1573 } else {
1574 ntq_store_dest(c, &instr->dest, 0,
1575 indirect_uniform_load(c, instr));
1576 }
1577 break;
1578
1579 case nir_intrinsic_load_user_clip_plane:
1580 for (int i = 0; i < instr->num_components; i++) {
1581 ntq_store_dest(c, &instr->dest, i,
1582 qir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1583 instr->const_index[0] * 4 +
1584 i));
1585 }
1586 break;
1587
1588 case nir_intrinsic_load_sample_mask_in:
1589 ntq_store_dest(c, &instr->dest, 0,
1590 qir_uniform(c, QUNIFORM_SAMPLE_MASK, 0));
1591 break;
1592
1593 case nir_intrinsic_load_front_face:
1594 /* The register contains 0 (front) or 1 (back), and we need to
1595 * turn it into a NIR bool where true means front.
1596 */
1597 ntq_store_dest(c, &instr->dest, 0,
1598 qir_ADD(c,
1599 qir_uniform_ui(c, -1),
1600 qir_reg(QFILE_FRAG_REV_FLAG, 0)));
1601 break;
1602
1603 case nir_intrinsic_load_input:
1604 assert(instr->num_components == 1);
1605 const_offset = nir_src_as_const_value(instr->src[0]);
1606 assert(const_offset && "vc4 doesn't support indirect inputs");
1607 if (instr->const_index[0] >= VC4_NIR_TLB_COLOR_READ_INPUT) {
1608 assert(const_offset->u32[0] == 0);
1609 /* Reads of the per-sample color need to be done in
1610 * order.
1611 */
1612 int sample_index = (instr->const_index[0] -
1613 VC4_NIR_TLB_COLOR_READ_INPUT);
1614 for (int i = 0; i <= sample_index; i++) {
1615 if (c->color_reads[i].file == QFILE_NULL) {
1616 c->color_reads[i] =
1617 qir_TLB_COLOR_READ(c);
1618 }
1619 }
1620 ntq_store_dest(c, &instr->dest, 0,
1621 c->color_reads[sample_index]);
1622 } else {
1623 offset = instr->const_index[0] + const_offset->u32[0];
1624 ntq_store_dest(c, &instr->dest, 0,
1625 c->inputs[offset]);
1626 }
1627 break;
1628
1629 case nir_intrinsic_store_output:
1630 const_offset = nir_src_as_const_value(instr->src[1]);
1631 assert(const_offset && "vc4 doesn't support indirect outputs");
1632 offset = instr->const_index[0] + const_offset->u32[0];
1633
1634 /* MSAA color outputs are the only case where we have an
1635 * output that's not lowered to being a store of a single 32
1636 * bit value.
1637 */
1638 if (c->stage == QSTAGE_FRAG && instr->num_components == 4) {
1639 assert(offset == c->output_color_index);
1640 for (int i = 0; i < 4; i++) {
1641 c->sample_colors[i] =
1642 qir_MOV(c, ntq_get_src(c, instr->src[0],
1643 i));
1644 }
1645 } else {
1646 assert(instr->num_components == 1);
1647 c->outputs[offset] =
1648 qir_MOV(c, ntq_get_src(c, instr->src[0], 0));
1649 c->num_outputs = MAX2(c->num_outputs, offset + 1);
1650 }
1651 break;
1652
1653 case nir_intrinsic_discard:
1654 c->discard = qir_uniform_ui(c, ~0);
1655 break;
1656
1657 case nir_intrinsic_discard_if:
1658 if (c->discard.file == QFILE_NULL)
1659 c->discard = qir_uniform_ui(c, 0);
1660 c->discard = qir_OR(c, c->discard,
1661 ntq_get_src(c, instr->src[0], 0));
1662 break;
1663
1664 default:
1665 fprintf(stderr, "Unknown intrinsic: ");
1666 nir_print_instr(&instr->instr, stderr);
1667 fprintf(stderr, "\n");
1668 break;
1669 }
1670 }
1671
1672 /* Clears (activates) the execute flags for any channels whose jump target
1673 * matches this block.
1674 */
1675 static void
1676 ntq_activate_execute_for_block(struct vc4_compile *c)
1677 {
1678 qir_SF(c, qir_SUB(c,
1679 c->execute,
1680 qir_uniform_ui(c, c->cur_block->index)));
1681 qir_MOV_cond(c, QPU_COND_ZS, c->execute, qir_uniform_ui(c, 0));
1682 }
1683
1684 static void
1685 ntq_emit_if(struct vc4_compile *c, nir_if *if_stmt)
1686 {
1687 if (!c->vc4->screen->has_control_flow) {
1688 fprintf(stderr,
1689 "IF statement support requires updated kernel.\n");
1690 return;
1691 }
1692
1693 nir_cf_node *nir_first_else_node = nir_if_first_else_node(if_stmt);
1694 nir_cf_node *nir_last_else_node = nir_if_last_else_node(if_stmt);
1695 nir_block *nir_else_block = nir_cf_node_as_block(nir_first_else_node);
1696 bool empty_else_block =
1697 (nir_first_else_node == nir_last_else_node &&
1698 exec_list_is_empty(&nir_else_block->instr_list));
1699
1700 struct qblock *then_block = qir_new_block(c);
1701 struct qblock *after_block = qir_new_block(c);
1702 struct qblock *else_block;
1703 if (empty_else_block)
1704 else_block = after_block;
1705 else
1706 else_block = qir_new_block(c);
1707
1708 bool was_top_level = false;
1709 if (c->execute.file == QFILE_NULL) {
1710 c->execute = qir_MOV(c, qir_uniform_ui(c, 0));
1711 was_top_level = true;
1712 }
1713
1714 /* Set ZS for executing (execute == 0) and jumping (if->condition ==
1715 * 0) channels, and then update execute flags for those to point to
1716 * the ELSE block.
1717 */
1718 qir_SF(c, qir_OR(c,
1719 c->execute,
1720 ntq_get_src(c, if_stmt->condition, 0)));
1721 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1722 qir_uniform_ui(c, else_block->index));
1723
1724 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1725 * through.
1726 */
1727 qir_SF(c, c->execute);
1728 qir_BRANCH(c, QPU_COND_BRANCH_ALL_ZC);
1729 qir_link_blocks(c->cur_block, else_block);
1730 qir_link_blocks(c->cur_block, then_block);
1731
1732 /* Process the THEN block. */
1733 qir_set_emit_block(c, then_block);
1734 ntq_emit_cf_list(c, &if_stmt->then_list);
1735
1736 if (!empty_else_block) {
1737 /* Handle the end of the THEN block. First, all currently
1738 * active channels update their execute flags to point to
1739 * ENDIF
1740 */
1741 qir_SF(c, c->execute);
1742 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1743 qir_uniform_ui(c, after_block->index));
1744
1745 /* If everything points at ENDIF, then jump there immediately. */
1746 qir_SF(c, qir_SUB(c, c->execute, qir_uniform_ui(c, after_block->index)));
1747 qir_BRANCH(c, QPU_COND_BRANCH_ALL_ZS);
1748 qir_link_blocks(c->cur_block, after_block);
1749 qir_link_blocks(c->cur_block, else_block);
1750
1751 qir_set_emit_block(c, else_block);
1752 ntq_activate_execute_for_block(c);
1753 ntq_emit_cf_list(c, &if_stmt->else_list);
1754 }
1755
1756 qir_link_blocks(c->cur_block, after_block);
1757
1758 qir_set_emit_block(c, after_block);
1759 if (was_top_level)
1760 c->execute = c->undef;
1761 else
1762 ntq_activate_execute_for_block(c);
1763
1764 }
1765
1766 static void
1767 ntq_emit_jump(struct vc4_compile *c, nir_jump_instr *jump)
1768 {
1769 switch (jump->type) {
1770 case nir_jump_break:
1771 qir_SF(c, c->execute);
1772 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1773 qir_uniform_ui(c, c->loop_break_block->index));
1774 break;
1775
1776 case nir_jump_continue:
1777 qir_SF(c, c->execute);
1778 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1779 qir_uniform_ui(c, c->loop_cont_block->index));
1780 break;
1781
1782 case nir_jump_return:
1783 unreachable("All returns shouold be lowered\n");
1784 }
1785 }
1786
1787 static void
1788 ntq_emit_instr(struct vc4_compile *c, nir_instr *instr)
1789 {
1790 switch (instr->type) {
1791 case nir_instr_type_alu:
1792 ntq_emit_alu(c, nir_instr_as_alu(instr));
1793 break;
1794
1795 case nir_instr_type_intrinsic:
1796 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
1797 break;
1798
1799 case nir_instr_type_load_const:
1800 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
1801 break;
1802
1803 case nir_instr_type_ssa_undef:
1804 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
1805 break;
1806
1807 case nir_instr_type_tex:
1808 ntq_emit_tex(c, nir_instr_as_tex(instr));
1809 break;
1810
1811 case nir_instr_type_jump:
1812 ntq_emit_jump(c, nir_instr_as_jump(instr));
1813 break;
1814
1815 default:
1816 fprintf(stderr, "Unknown NIR instr type: ");
1817 nir_print_instr(instr, stderr);
1818 fprintf(stderr, "\n");
1819 abort();
1820 }
1821 }
1822
1823 static void
1824 ntq_emit_block(struct vc4_compile *c, nir_block *block)
1825 {
1826 nir_foreach_instr(instr, block) {
1827 ntq_emit_instr(c, instr);
1828 }
1829 }
1830
1831 static void ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list);
1832
1833 static void
1834 ntq_emit_loop(struct vc4_compile *c, nir_loop *loop)
1835 {
1836 if (!c->vc4->screen->has_control_flow) {
1837 fprintf(stderr,
1838 "loop support requires updated kernel.\n");
1839 ntq_emit_cf_list(c, &loop->body);
1840 return;
1841 }
1842
1843 bool was_top_level = false;
1844 if (c->execute.file == QFILE_NULL) {
1845 c->execute = qir_MOV(c, qir_uniform_ui(c, 0));
1846 was_top_level = true;
1847 }
1848
1849 struct qblock *save_loop_cont_block = c->loop_cont_block;
1850 struct qblock *save_loop_break_block = c->loop_break_block;
1851
1852 c->loop_cont_block = qir_new_block(c);
1853 c->loop_break_block = qir_new_block(c);
1854
1855 qir_link_blocks(c->cur_block, c->loop_cont_block);
1856 qir_set_emit_block(c, c->loop_cont_block);
1857 ntq_activate_execute_for_block(c);
1858
1859 ntq_emit_cf_list(c, &loop->body);
1860
1861 /* If anything had explicitly continued, or is here at the end of the
1862 * loop, then we need to loop again. SF updates are masked by the
1863 * instruction's condition, so we can do the OR of the two conditions
1864 * within SF.
1865 */
1866 qir_SF(c, c->execute);
1867 struct qinst *cont_check =
1868 qir_SUB_dest(c,
1869 c->undef,
1870 c->execute,
1871 qir_uniform_ui(c, c->loop_cont_block->index));
1872 cont_check->cond = QPU_COND_ZC;
1873 cont_check->sf = true;
1874
1875 qir_BRANCH(c, QPU_COND_BRANCH_ANY_ZS);
1876 qir_link_blocks(c->cur_block, c->loop_cont_block);
1877 qir_link_blocks(c->cur_block, c->loop_break_block);
1878
1879 qir_set_emit_block(c, c->loop_break_block);
1880 if (was_top_level)
1881 c->execute = c->undef;
1882 else
1883 ntq_activate_execute_for_block(c);
1884
1885 c->loop_break_block = save_loop_break_block;
1886 c->loop_cont_block = save_loop_cont_block;
1887 }
1888
1889 static void
1890 ntq_emit_function(struct vc4_compile *c, nir_function_impl *func)
1891 {
1892 fprintf(stderr, "FUNCTIONS not handled.\n");
1893 abort();
1894 }
1895
1896 static void
1897 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list)
1898 {
1899 foreach_list_typed(nir_cf_node, node, node, list) {
1900 switch (node->type) {
1901 case nir_cf_node_block:
1902 ntq_emit_block(c, nir_cf_node_as_block(node));
1903 break;
1904
1905 case nir_cf_node_if:
1906 ntq_emit_if(c, nir_cf_node_as_if(node));
1907 break;
1908
1909 case nir_cf_node_loop:
1910 ntq_emit_loop(c, nir_cf_node_as_loop(node));
1911 break;
1912
1913 case nir_cf_node_function:
1914 ntq_emit_function(c, nir_cf_node_as_function(node));
1915 break;
1916
1917 default:
1918 fprintf(stderr, "Unknown NIR node type\n");
1919 abort();
1920 }
1921 }
1922 }
1923
1924 static void
1925 ntq_emit_impl(struct vc4_compile *c, nir_function_impl *impl)
1926 {
1927 ntq_setup_registers(c, &impl->registers);
1928 ntq_emit_cf_list(c, &impl->body);
1929 }
1930
1931 static void
1932 nir_to_qir(struct vc4_compile *c)
1933 {
1934 ntq_setup_inputs(c);
1935 ntq_setup_outputs(c);
1936 ntq_setup_uniforms(c);
1937 ntq_setup_registers(c, &c->s->registers);
1938
1939 /* Find the main function and emit the body. */
1940 nir_foreach_function(function, c->s) {
1941 assert(strcmp(function->name, "main") == 0);
1942 assert(function->impl);
1943 ntq_emit_impl(c, function->impl);
1944 }
1945 }
1946
1947 static const nir_shader_compiler_options nir_options = {
1948 .lower_extract_byte = true,
1949 .lower_extract_word = true,
1950 .lower_ffma = true,
1951 .lower_flrp32 = true,
1952 .lower_fpow = true,
1953 .lower_fsat = true,
1954 .lower_fsqrt = true,
1955 .lower_negate = true,
1956 };
1957
1958 static int
1959 count_nir_instrs(nir_shader *nir)
1960 {
1961 int count = 0;
1962 nir_foreach_function(function, nir) {
1963 if (!function->impl)
1964 continue;
1965 nir_foreach_block(block, function->impl) {
1966 nir_foreach_instr(instr, block)
1967 count++;
1968 }
1969 }
1970 return count;
1971 }
1972
1973 static struct vc4_compile *
1974 vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage,
1975 struct vc4_key *key)
1976 {
1977 struct vc4_compile *c = qir_compile_init();
1978
1979 c->vc4 = vc4;
1980 c->stage = stage;
1981 c->shader_state = &key->shader_state->base;
1982 c->program_id = key->shader_state->program_id;
1983 c->variant_id =
1984 p_atomic_inc_return(&key->shader_state->compiled_variant_count);
1985
1986 c->key = key;
1987 switch (stage) {
1988 case QSTAGE_FRAG:
1989 c->fs_key = (struct vc4_fs_key *)key;
1990 if (c->fs_key->is_points) {
1991 c->point_x = emit_fragment_varying(c, ~0, 0);
1992 c->point_y = emit_fragment_varying(c, ~0, 0);
1993 } else if (c->fs_key->is_lines) {
1994 c->line_x = emit_fragment_varying(c, ~0, 0);
1995 }
1996 break;
1997 case QSTAGE_VERT:
1998 c->vs_key = (struct vc4_vs_key *)key;
1999 break;
2000 case QSTAGE_COORD:
2001 c->vs_key = (struct vc4_vs_key *)key;
2002 break;
2003 }
2004
2005 c->s = nir_shader_clone(c, key->shader_state->base.ir.nir);
2006 NIR_PASS_V(c->s, nir_opt_global_to_local);
2007 NIR_PASS_V(c->s, nir_convert_to_ssa);
2008
2009 if (stage == QSTAGE_FRAG)
2010 NIR_PASS_V(c->s, vc4_nir_lower_blend, c);
2011
2012 struct nir_lower_tex_options tex_options = {
2013 /* We would need to implement txs, but we don't want the
2014 * int/float conversions
2015 */
2016 .lower_rect = false,
2017
2018 .lower_txp = ~0,
2019
2020 /* Apply swizzles to all samplers. */
2021 .swizzle_result = ~0,
2022 };
2023
2024 /* Lower the format swizzle and ARB_texture_swizzle-style swizzle.
2025 * The format swizzling applies before sRGB decode, and
2026 * ARB_texture_swizzle is the last thing before returning the sample.
2027 */
2028 for (int i = 0; i < ARRAY_SIZE(key->tex); i++) {
2029 enum pipe_format format = c->key->tex[i].format;
2030
2031 if (!format)
2032 continue;
2033
2034 const uint8_t *format_swizzle = vc4_get_format_swizzle(format);
2035
2036 for (int j = 0; j < 4; j++) {
2037 uint8_t arb_swiz = c->key->tex[i].swizzle[j];
2038
2039 if (arb_swiz <= 3) {
2040 tex_options.swizzles[i][j] =
2041 format_swizzle[arb_swiz];
2042 } else {
2043 tex_options.swizzles[i][j] = arb_swiz;
2044 }
2045 }
2046
2047 if (util_format_is_srgb(format))
2048 tex_options.lower_srgb |= (1 << i);
2049 }
2050
2051 NIR_PASS_V(c->s, nir_normalize_cubemap_coords);
2052 NIR_PASS_V(c->s, nir_lower_tex, &tex_options);
2053
2054 if (c->fs_key && c->fs_key->light_twoside)
2055 NIR_PASS_V(c->s, nir_lower_two_sided_color);
2056
2057 if (c->vs_key && c->vs_key->clamp_color)
2058 NIR_PASS_V(c->s, nir_lower_clamp_color_outputs);
2059
2060 if (stage == QSTAGE_FRAG)
2061 NIR_PASS_V(c->s, nir_lower_clip_fs, c->key->ucp_enables);
2062 else
2063 NIR_PASS_V(c->s, nir_lower_clip_vs, c->key->ucp_enables);
2064
2065 NIR_PASS_V(c->s, vc4_nir_lower_io, c);
2066 NIR_PASS_V(c->s, vc4_nir_lower_txf_ms, c);
2067 NIR_PASS_V(c->s, nir_lower_idiv);
2068 NIR_PASS_V(c->s, nir_lower_load_const_to_scalar);
2069
2070 vc4_optimize_nir(c->s);
2071
2072 NIR_PASS_V(c->s, nir_remove_dead_variables, nir_var_local);
2073 NIR_PASS_V(c->s, nir_convert_from_ssa, true);
2074
2075 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2076 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d NIR instructions\n",
2077 qir_get_stage_name(c->stage),
2078 c->program_id, c->variant_id,
2079 count_nir_instrs(c->s));
2080 }
2081
2082 if (vc4_debug & VC4_DEBUG_NIR) {
2083 fprintf(stderr, "%s prog %d/%d NIR:\n",
2084 qir_get_stage_name(c->stage),
2085 c->program_id, c->variant_id);
2086 nir_print_shader(c->s, stderr);
2087 }
2088
2089 nir_to_qir(c);
2090
2091 switch (stage) {
2092 case QSTAGE_FRAG:
2093 emit_frag_end(c);
2094 break;
2095 case QSTAGE_VERT:
2096 emit_vert_end(c,
2097 vc4->prog.fs->input_slots,
2098 vc4->prog.fs->num_inputs);
2099 break;
2100 case QSTAGE_COORD:
2101 emit_coord_end(c);
2102 break;
2103 }
2104
2105 if (vc4_debug & VC4_DEBUG_QIR) {
2106 fprintf(stderr, "%s prog %d/%d pre-opt QIR:\n",
2107 qir_get_stage_name(c->stage),
2108 c->program_id, c->variant_id);
2109 qir_dump(c);
2110 fprintf(stderr, "\n");
2111 }
2112
2113 qir_optimize(c);
2114 qir_lower_uniforms(c);
2115
2116 qir_schedule_instructions(c);
2117
2118 if (vc4_debug & VC4_DEBUG_QIR) {
2119 fprintf(stderr, "%s prog %d/%d QIR:\n",
2120 qir_get_stage_name(c->stage),
2121 c->program_id, c->variant_id);
2122 qir_dump(c);
2123 fprintf(stderr, "\n");
2124 }
2125
2126 qir_reorder_uniforms(c);
2127 vc4_generate_code(vc4, c);
2128
2129 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2130 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d instructions\n",
2131 qir_get_stage_name(c->stage),
2132 c->program_id, c->variant_id,
2133 c->qpu_inst_count);
2134 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
2135 qir_get_stage_name(c->stage),
2136 c->program_id, c->variant_id,
2137 c->num_uniforms);
2138 }
2139
2140 ralloc_free(c->s);
2141
2142 return c;
2143 }
2144
2145 static void *
2146 vc4_shader_state_create(struct pipe_context *pctx,
2147 const struct pipe_shader_state *cso)
2148 {
2149 struct vc4_context *vc4 = vc4_context(pctx);
2150 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
2151 if (!so)
2152 return NULL;
2153
2154 so->program_id = vc4->next_uncompiled_program_id++;
2155
2156 nir_shader *s = tgsi_to_nir(cso->tokens, &nir_options);
2157
2158 if (vc4_debug & VC4_DEBUG_TGSI) {
2159 fprintf(stderr, "%s prog %d TGSI:\n",
2160 gl_shader_stage_name(s->stage),
2161 so->program_id);
2162 tgsi_dump(cso->tokens, 0);
2163 fprintf(stderr, "\n");
2164 }
2165
2166 so->base.type = PIPE_SHADER_IR_NIR;
2167 so->base.ir.nir = s;
2168
2169 return so;
2170 }
2171
2172 static void
2173 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
2174 struct vc4_compile *c)
2175 {
2176 int count = c->num_uniforms;
2177 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2178
2179 uinfo->count = count;
2180 uinfo->data = ralloc_array(shader, uint32_t, count);
2181 memcpy(uinfo->data, c->uniform_data,
2182 count * sizeof(*uinfo->data));
2183 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
2184 memcpy(uinfo->contents, c->uniform_contents,
2185 count * sizeof(*uinfo->contents));
2186 uinfo->num_texture_samples = c->num_texture_samples;
2187
2188 vc4_set_shader_uniform_dirty_flags(shader);
2189 }
2190
2191 static struct vc4_compiled_shader *
2192 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
2193 struct vc4_key *key)
2194 {
2195 struct hash_table *ht;
2196 uint32_t key_size;
2197 if (stage == QSTAGE_FRAG) {
2198 ht = vc4->fs_cache;
2199 key_size = sizeof(struct vc4_fs_key);
2200 } else {
2201 ht = vc4->vs_cache;
2202 key_size = sizeof(struct vc4_vs_key);
2203 }
2204
2205 struct vc4_compiled_shader *shader;
2206 struct hash_entry *entry = _mesa_hash_table_search(ht, key);
2207 if (entry)
2208 return entry->data;
2209
2210 struct vc4_compile *c = vc4_shader_ntq(vc4, stage, key);
2211 shader = rzalloc(NULL, struct vc4_compiled_shader);
2212
2213 shader->program_id = vc4->next_compiled_program_id++;
2214 if (stage == QSTAGE_FRAG) {
2215 bool input_live[c->num_input_slots];
2216
2217 memset(input_live, 0, sizeof(input_live));
2218 qir_for_each_inst_inorder(inst, c) {
2219 for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
2220 if (inst->src[i].file == QFILE_VARY)
2221 input_live[inst->src[i].index] = true;
2222 }
2223 }
2224
2225 shader->input_slots = ralloc_array(shader,
2226 struct vc4_varying_slot,
2227 c->num_input_slots);
2228
2229 for (int i = 0; i < c->num_input_slots; i++) {
2230 struct vc4_varying_slot *slot = &c->input_slots[i];
2231
2232 if (!input_live[i])
2233 continue;
2234
2235 /* Skip non-VS-output inputs. */
2236 if (slot->slot == (uint8_t)~0)
2237 continue;
2238
2239 if (slot->slot == VARYING_SLOT_COL0 ||
2240 slot->slot == VARYING_SLOT_COL1 ||
2241 slot->slot == VARYING_SLOT_BFC0 ||
2242 slot->slot == VARYING_SLOT_BFC1) {
2243 shader->color_inputs |= (1 << shader->num_inputs);
2244 }
2245
2246 shader->input_slots[shader->num_inputs] = *slot;
2247 shader->num_inputs++;
2248 }
2249 } else {
2250 shader->num_inputs = c->num_inputs;
2251
2252 shader->vattr_offsets[0] = 0;
2253 for (int i = 0; i < 8; i++) {
2254 shader->vattr_offsets[i + 1] =
2255 shader->vattr_offsets[i] + c->vattr_sizes[i];
2256
2257 if (c->vattr_sizes[i])
2258 shader->vattrs_live |= (1 << i);
2259 }
2260 }
2261
2262 copy_uniform_state_to_shader(shader, c);
2263 shader->bo = vc4_bo_alloc_shader(vc4->screen, c->qpu_insts,
2264 c->qpu_inst_count * sizeof(uint64_t));
2265
2266 /* Copy the compiler UBO range state to the compiled shader, dropping
2267 * out arrays that were never referenced by an indirect load.
2268 *
2269 * (Note that QIR dead code elimination of an array access still
2270 * leaves that array alive, though)
2271 */
2272 if (c->num_ubo_ranges) {
2273 shader->num_ubo_ranges = c->num_ubo_ranges;
2274 shader->ubo_ranges = ralloc_array(shader, struct vc4_ubo_range,
2275 c->num_ubo_ranges);
2276 uint32_t j = 0;
2277 for (int i = 0; i < c->num_uniform_ranges; i++) {
2278 struct vc4_compiler_ubo_range *range =
2279 &c->ubo_ranges[i];
2280 if (!range->used)
2281 continue;
2282
2283 shader->ubo_ranges[j].dst_offset = range->dst_offset;
2284 shader->ubo_ranges[j].src_offset = range->src_offset;
2285 shader->ubo_ranges[j].size = range->size;
2286 shader->ubo_size += c->ubo_ranges[i].size;
2287 j++;
2288 }
2289 }
2290 if (shader->ubo_size) {
2291 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2292 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d UBO uniforms\n",
2293 qir_get_stage_name(c->stage),
2294 c->program_id, c->variant_id,
2295 shader->ubo_size / 4);
2296 }
2297 }
2298
2299 qir_compile_destroy(c);
2300
2301 struct vc4_key *dup_key;
2302 dup_key = ralloc_size(shader, key_size);
2303 memcpy(dup_key, key, key_size);
2304 _mesa_hash_table_insert(ht, dup_key, shader);
2305
2306 return shader;
2307 }
2308
2309 static void
2310 vc4_setup_shared_key(struct vc4_context *vc4, struct vc4_key *key,
2311 struct vc4_texture_stateobj *texstate)
2312 {
2313 for (int i = 0; i < texstate->num_textures; i++) {
2314 struct pipe_sampler_view *sampler = texstate->textures[i];
2315 struct pipe_sampler_state *sampler_state =
2316 texstate->samplers[i];
2317
2318 if (!sampler)
2319 continue;
2320
2321 key->tex[i].format = sampler->format;
2322 key->tex[i].swizzle[0] = sampler->swizzle_r;
2323 key->tex[i].swizzle[1] = sampler->swizzle_g;
2324 key->tex[i].swizzle[2] = sampler->swizzle_b;
2325 key->tex[i].swizzle[3] = sampler->swizzle_a;
2326
2327 if (sampler->texture->nr_samples > 1) {
2328 key->tex[i].msaa_width = sampler->texture->width0;
2329 key->tex[i].msaa_height = sampler->texture->height0;
2330 } else if (sampler){
2331 key->tex[i].compare_mode = sampler_state->compare_mode;
2332 key->tex[i].compare_func = sampler_state->compare_func;
2333 key->tex[i].wrap_s = sampler_state->wrap_s;
2334 key->tex[i].wrap_t = sampler_state->wrap_t;
2335 }
2336 }
2337
2338 key->ucp_enables = vc4->rasterizer->base.clip_plane_enable;
2339 }
2340
2341 static void
2342 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
2343 {
2344 struct vc4_fs_key local_key;
2345 struct vc4_fs_key *key = &local_key;
2346
2347 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2348 VC4_DIRTY_BLEND |
2349 VC4_DIRTY_FRAMEBUFFER |
2350 VC4_DIRTY_ZSA |
2351 VC4_DIRTY_RASTERIZER |
2352 VC4_DIRTY_SAMPLE_MASK |
2353 VC4_DIRTY_FRAGTEX |
2354 VC4_DIRTY_TEXSTATE |
2355 VC4_DIRTY_UNCOMPILED_FS))) {
2356 return;
2357 }
2358
2359 memset(key, 0, sizeof(*key));
2360 vc4_setup_shared_key(vc4, &key->base, &vc4->fragtex);
2361 key->base.shader_state = vc4->prog.bind_fs;
2362 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
2363 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
2364 prim_mode <= PIPE_PRIM_LINE_STRIP);
2365 key->blend = vc4->blend->rt[0];
2366 if (vc4->blend->logicop_enable) {
2367 key->logicop_func = vc4->blend->logicop_func;
2368 } else {
2369 key->logicop_func = PIPE_LOGICOP_COPY;
2370 }
2371 if (vc4->msaa) {
2372 key->msaa = vc4->rasterizer->base.multisample;
2373 key->sample_coverage = (vc4->rasterizer->base.multisample &&
2374 vc4->sample_mask != (1 << VC4_MAX_SAMPLES) - 1);
2375 key->sample_alpha_to_coverage = vc4->blend->alpha_to_coverage;
2376 key->sample_alpha_to_one = vc4->blend->alpha_to_one;
2377 }
2378
2379 if (vc4->framebuffer.cbufs[0])
2380 key->color_format = vc4->framebuffer.cbufs[0]->format;
2381
2382 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
2383 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
2384 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
2385 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
2386 key->stencil_enabled);
2387 if (vc4->zsa->base.alpha.enabled) {
2388 key->alpha_test = true;
2389 key->alpha_test_func = vc4->zsa->base.alpha.func;
2390 }
2391
2392 if (key->is_points) {
2393 key->point_sprite_mask =
2394 vc4->rasterizer->base.sprite_coord_enable;
2395 key->point_coord_upper_left =
2396 (vc4->rasterizer->base.sprite_coord_mode ==
2397 PIPE_SPRITE_COORD_UPPER_LEFT);
2398 }
2399
2400 key->light_twoside = vc4->rasterizer->base.light_twoside;
2401
2402 struct vc4_compiled_shader *old_fs = vc4->prog.fs;
2403 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
2404 if (vc4->prog.fs == old_fs)
2405 return;
2406
2407 vc4->dirty |= VC4_DIRTY_COMPILED_FS;
2408 if (vc4->rasterizer->base.flatshade &&
2409 old_fs && vc4->prog.fs->color_inputs != old_fs->color_inputs) {
2410 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
2411 }
2412 }
2413
2414 static void
2415 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
2416 {
2417 struct vc4_vs_key local_key;
2418 struct vc4_vs_key *key = &local_key;
2419
2420 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2421 VC4_DIRTY_RASTERIZER |
2422 VC4_DIRTY_VERTTEX |
2423 VC4_DIRTY_TEXSTATE |
2424 VC4_DIRTY_VTXSTATE |
2425 VC4_DIRTY_UNCOMPILED_VS |
2426 VC4_DIRTY_COMPILED_FS))) {
2427 return;
2428 }
2429
2430 memset(key, 0, sizeof(*key));
2431 vc4_setup_shared_key(vc4, &key->base, &vc4->verttex);
2432 key->base.shader_state = vc4->prog.bind_vs;
2433 key->compiled_fs_id = vc4->prog.fs->program_id;
2434 key->clamp_color = vc4->rasterizer->base.clamp_vertex_color;
2435
2436 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
2437 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
2438
2439 key->per_vertex_point_size =
2440 (prim_mode == PIPE_PRIM_POINTS &&
2441 vc4->rasterizer->base.point_size_per_vertex);
2442
2443 struct vc4_compiled_shader *vs =
2444 vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
2445 if (vs != vc4->prog.vs) {
2446 vc4->prog.vs = vs;
2447 vc4->dirty |= VC4_DIRTY_COMPILED_VS;
2448 }
2449
2450 key->is_coord = true;
2451 struct vc4_compiled_shader *cs =
2452 vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
2453 if (cs != vc4->prog.cs) {
2454 vc4->prog.cs = cs;
2455 vc4->dirty |= VC4_DIRTY_COMPILED_CS;
2456 }
2457 }
2458
2459 void
2460 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
2461 {
2462 vc4_update_compiled_fs(vc4, prim_mode);
2463 vc4_update_compiled_vs(vc4, prim_mode);
2464 }
2465
2466 static uint32_t
2467 fs_cache_hash(const void *key)
2468 {
2469 return _mesa_hash_data(key, sizeof(struct vc4_fs_key));
2470 }
2471
2472 static uint32_t
2473 vs_cache_hash(const void *key)
2474 {
2475 return _mesa_hash_data(key, sizeof(struct vc4_vs_key));
2476 }
2477
2478 static bool
2479 fs_cache_compare(const void *key1, const void *key2)
2480 {
2481 return memcmp(key1, key2, sizeof(struct vc4_fs_key)) == 0;
2482 }
2483
2484 static bool
2485 vs_cache_compare(const void *key1, const void *key2)
2486 {
2487 return memcmp(key1, key2, sizeof(struct vc4_vs_key)) == 0;
2488 }
2489
2490 static void
2491 delete_from_cache_if_matches(struct hash_table *ht,
2492 struct hash_entry *entry,
2493 struct vc4_uncompiled_shader *so)
2494 {
2495 const struct vc4_key *key = entry->key;
2496
2497 if (key->shader_state == so) {
2498 struct vc4_compiled_shader *shader = entry->data;
2499 _mesa_hash_table_remove(ht, entry);
2500 vc4_bo_unreference(&shader->bo);
2501 ralloc_free(shader);
2502 }
2503 }
2504
2505 static void
2506 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
2507 {
2508 struct vc4_context *vc4 = vc4_context(pctx);
2509 struct vc4_uncompiled_shader *so = hwcso;
2510
2511 struct hash_entry *entry;
2512 hash_table_foreach(vc4->fs_cache, entry)
2513 delete_from_cache_if_matches(vc4->fs_cache, entry, so);
2514 hash_table_foreach(vc4->vs_cache, entry)
2515 delete_from_cache_if_matches(vc4->vs_cache, entry, so);
2516
2517 ralloc_free(so->base.ir.nir);
2518 free(so);
2519 }
2520
2521 static void
2522 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2523 {
2524 struct vc4_context *vc4 = vc4_context(pctx);
2525 vc4->prog.bind_fs = hwcso;
2526 vc4->dirty |= VC4_DIRTY_UNCOMPILED_FS;
2527 }
2528
2529 static void
2530 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2531 {
2532 struct vc4_context *vc4 = vc4_context(pctx);
2533 vc4->prog.bind_vs = hwcso;
2534 vc4->dirty |= VC4_DIRTY_UNCOMPILED_VS;
2535 }
2536
2537 void
2538 vc4_program_init(struct pipe_context *pctx)
2539 {
2540 struct vc4_context *vc4 = vc4_context(pctx);
2541
2542 pctx->create_vs_state = vc4_shader_state_create;
2543 pctx->delete_vs_state = vc4_shader_state_delete;
2544
2545 pctx->create_fs_state = vc4_shader_state_create;
2546 pctx->delete_fs_state = vc4_shader_state_delete;
2547
2548 pctx->bind_fs_state = vc4_fp_state_bind;
2549 pctx->bind_vs_state = vc4_vp_state_bind;
2550
2551 vc4->fs_cache = _mesa_hash_table_create(pctx, fs_cache_hash,
2552 fs_cache_compare);
2553 vc4->vs_cache = _mesa_hash_table_create(pctx, vs_cache_hash,
2554 vs_cache_compare);
2555 }
2556
2557 void
2558 vc4_program_fini(struct pipe_context *pctx)
2559 {
2560 struct vc4_context *vc4 = vc4_context(pctx);
2561
2562 struct hash_entry *entry;
2563 hash_table_foreach(vc4->fs_cache, entry) {
2564 struct vc4_compiled_shader *shader = entry->data;
2565 vc4_bo_unreference(&shader->bo);
2566 ralloc_free(shader);
2567 _mesa_hash_table_remove(vc4->fs_cache, entry);
2568 }
2569
2570 hash_table_foreach(vc4->vs_cache, entry) {
2571 struct vc4_compiled_shader *shader = entry->data;
2572 vc4_bo_unreference(&shader->bo);
2573 ralloc_free(shader);
2574 _mesa_hash_table_remove(vc4->vs_cache, entry);
2575 }
2576 }