2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #include "gen_device_info.h"
30 #include "compiler/shader_enums.h"
31 #include "util/bitscan.h"
32 #include "util/macros.h"
34 #include "drm-uapi/i915_drm.h"
37 * Get the PCI ID for the device name.
39 * Returns -1 if the device is not known.
42 gen_device_name_to_pci_device_id(const char *name
)
69 for (unsigned i
= 0; i
< ARRAY_SIZE(name_map
); i
++) {
70 if (!strcmp(name_map
[i
].name
, name
))
71 return name_map
[i
].pci_id
;
78 * Get the overridden PCI ID for the device. This is set with the
79 * INTEL_DEVID_OVERRIDE environment variable.
81 * Returns -1 if the override is not set.
84 gen_get_pci_device_id_override(void)
86 if (geteuid() == getuid()) {
87 const char *devid_override
= getenv("INTEL_DEVID_OVERRIDE");
89 const int id
= gen_device_name_to_pci_device_id(devid_override
);
90 return id
>= 0 ? id
: strtol(devid_override
, NULL
, 0);
97 static const struct gen_device_info gen_device_info_i965
= {
99 .has_negative_rhw_bug
= true,
101 .num_subslices
= { 1, },
102 .num_eu_per_subslice
= 8,
103 .num_thread_per_eu
= 4,
104 .max_vs_threads
= 16,
106 .max_wm_threads
= 8 * 4,
110 .timestamp_frequency
= 12500000,
114 static const struct gen_device_info gen_device_info_g4x
= {
118 .has_surface_tile_offset
= true,
121 .num_subslices
= { 1, },
122 .num_eu_per_subslice
= 10,
123 .num_thread_per_eu
= 5,
124 .max_vs_threads
= 32,
126 .max_wm_threads
= 10 * 5,
130 .timestamp_frequency
= 12500000,
134 static const struct gen_device_info gen_device_info_ilk
= {
138 .has_surface_tile_offset
= true,
140 .num_subslices
= { 1, },
141 .num_eu_per_subslice
= 12,
142 .num_thread_per_eu
= 6,
143 .max_vs_threads
= 72,
144 .max_gs_threads
= 32,
145 .max_wm_threads
= 12 * 6,
149 .timestamp_frequency
= 12500000,
153 static const struct gen_device_info gen_device_info_snb_gt1
= {
156 .has_hiz_and_separate_stencil
= true,
159 .has_surface_tile_offset
= true,
160 .needs_unlit_centroid_workaround
= true,
162 .num_subslices
= { 1, },
163 .num_eu_per_subslice
= 6,
164 .num_thread_per_eu
= 6, /* Not confirmed */
165 .max_vs_threads
= 24,
166 .max_gs_threads
= 21, /* conservative; 24 if rendering disabled. */
167 .max_wm_threads
= 40,
171 [MESA_SHADER_VERTEX
] = 24,
174 [MESA_SHADER_VERTEX
] = 256,
175 [MESA_SHADER_GEOMETRY
] = 256,
178 .timestamp_frequency
= 12500000,
182 static const struct gen_device_info gen_device_info_snb_gt2
= {
185 .has_hiz_and_separate_stencil
= true,
188 .has_surface_tile_offset
= true,
189 .needs_unlit_centroid_workaround
= true,
191 .num_subslices
= { 1, },
192 .num_eu_per_subslice
= 12,
193 .num_thread_per_eu
= 6, /* Not confirmed */
194 .max_vs_threads
= 60,
195 .max_gs_threads
= 60,
196 .max_wm_threads
= 80,
200 [MESA_SHADER_VERTEX
] = 24,
203 [MESA_SHADER_VERTEX
] = 256,
204 [MESA_SHADER_GEOMETRY
] = 256,
207 .timestamp_frequency
= 12500000,
211 #define GEN7_FEATURES \
213 .has_hiz_and_separate_stencil = true, \
214 .must_use_separate_stencil = true, \
217 .has_64bit_types = true, \
218 .has_surface_tile_offset = true, \
219 .timestamp_frequency = 12500000
221 static const struct gen_device_info gen_device_info_ivb_gt1
= {
222 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 1,
224 .num_subslices
= { 1, },
225 .num_eu_per_subslice
= 6,
226 .num_thread_per_eu
= 6,
228 .max_vs_threads
= 36,
229 .max_tcs_threads
= 36,
230 .max_tes_threads
= 36,
231 .max_gs_threads
= 36,
232 .max_wm_threads
= 48,
233 .max_cs_threads
= 36,
237 [MESA_SHADER_VERTEX
] = 32,
238 [MESA_SHADER_TESS_EVAL
] = 10,
241 [MESA_SHADER_VERTEX
] = 512,
242 [MESA_SHADER_TESS_CTRL
] = 32,
243 [MESA_SHADER_TESS_EVAL
] = 288,
244 [MESA_SHADER_GEOMETRY
] = 192,
250 static const struct gen_device_info gen_device_info_ivb_gt2
= {
251 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 2,
253 .num_subslices
= { 1, },
254 .num_eu_per_subslice
= 12,
255 .num_thread_per_eu
= 8, /* Not sure why this isn't a multiple of
256 * @max_wm_threads ... */
258 .max_vs_threads
= 128,
259 .max_tcs_threads
= 128,
260 .max_tes_threads
= 128,
261 .max_gs_threads
= 128,
262 .max_wm_threads
= 172,
263 .max_cs_threads
= 64,
267 [MESA_SHADER_VERTEX
] = 32,
268 [MESA_SHADER_TESS_EVAL
] = 10,
271 [MESA_SHADER_VERTEX
] = 704,
272 [MESA_SHADER_TESS_CTRL
] = 64,
273 [MESA_SHADER_TESS_EVAL
] = 448,
274 [MESA_SHADER_GEOMETRY
] = 320,
280 static const struct gen_device_info gen_device_info_byt
= {
281 GEN7_FEATURES
, .is_baytrail
= true, .gt
= 1,
283 .num_subslices
= { 1, },
284 .num_eu_per_subslice
= 4,
285 .num_thread_per_eu
= 8,
288 .max_vs_threads
= 36,
289 .max_tcs_threads
= 36,
290 .max_tes_threads
= 36,
291 .max_gs_threads
= 36,
292 .max_wm_threads
= 48,
293 .max_cs_threads
= 32,
297 [MESA_SHADER_VERTEX
] = 32,
298 [MESA_SHADER_TESS_EVAL
] = 10,
301 [MESA_SHADER_VERTEX
] = 512,
302 [MESA_SHADER_TESS_CTRL
] = 32,
303 [MESA_SHADER_TESS_EVAL
] = 288,
304 [MESA_SHADER_GEOMETRY
] = 192,
310 #define HSW_FEATURES \
312 .is_haswell = true, \
313 .supports_simd16_3src = true, \
314 .has_resource_streamer = true
316 static const struct gen_device_info gen_device_info_hsw_gt1
= {
317 HSW_FEATURES
, .gt
= 1,
319 .num_subslices
= { 1, },
320 .num_eu_per_subslice
= 10,
321 .num_thread_per_eu
= 7,
323 .max_vs_threads
= 70,
324 .max_tcs_threads
= 70,
325 .max_tes_threads
= 70,
326 .max_gs_threads
= 70,
327 .max_wm_threads
= 102,
328 .max_cs_threads
= 70,
332 [MESA_SHADER_VERTEX
] = 32,
333 [MESA_SHADER_TESS_EVAL
] = 10,
336 [MESA_SHADER_VERTEX
] = 640,
337 [MESA_SHADER_TESS_CTRL
] = 64,
338 [MESA_SHADER_TESS_EVAL
] = 384,
339 [MESA_SHADER_GEOMETRY
] = 256,
345 static const struct gen_device_info gen_device_info_hsw_gt2
= {
346 HSW_FEATURES
, .gt
= 2,
348 .num_subslices
= { 2, },
349 .num_eu_per_subslice
= 10,
350 .num_thread_per_eu
= 7,
352 .max_vs_threads
= 280,
353 .max_tcs_threads
= 256,
354 .max_tes_threads
= 280,
355 .max_gs_threads
= 256,
356 .max_wm_threads
= 204,
357 .max_cs_threads
= 70,
361 [MESA_SHADER_VERTEX
] = 64,
362 [MESA_SHADER_TESS_EVAL
] = 10,
365 [MESA_SHADER_VERTEX
] = 1664,
366 [MESA_SHADER_TESS_CTRL
] = 128,
367 [MESA_SHADER_TESS_EVAL
] = 960,
368 [MESA_SHADER_GEOMETRY
] = 640,
374 static const struct gen_device_info gen_device_info_hsw_gt3
= {
375 HSW_FEATURES
, .gt
= 3,
377 .num_subslices
= { 2, },
378 .num_eu_per_subslice
= 10,
379 .num_thread_per_eu
= 7,
381 .max_vs_threads
= 280,
382 .max_tcs_threads
= 256,
383 .max_tes_threads
= 280,
384 .max_gs_threads
= 256,
385 .max_wm_threads
= 408,
386 .max_cs_threads
= 70,
390 [MESA_SHADER_VERTEX
] = 64,
391 [MESA_SHADER_TESS_EVAL
] = 10,
394 [MESA_SHADER_VERTEX
] = 1664,
395 [MESA_SHADER_TESS_CTRL
] = 128,
396 [MESA_SHADER_TESS_EVAL
] = 960,
397 [MESA_SHADER_GEOMETRY
] = 640,
403 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
404 * so keep things conservative for now and set has_sample_with_hiz = false.
406 #define GEN8_FEATURES \
408 .has_hiz_and_separate_stencil = true, \
409 .has_resource_streamer = true, \
410 .must_use_separate_stencil = true, \
412 .has_sample_with_hiz = false, \
414 .has_integer_dword_mul = true, \
415 .has_64bit_types = true, \
416 .supports_simd16_3src = true, \
417 .has_surface_tile_offset = true, \
418 .num_thread_per_eu = 7, \
419 .max_vs_threads = 504, \
420 .max_tcs_threads = 504, \
421 .max_tes_threads = 504, \
422 .max_gs_threads = 504, \
423 .max_wm_threads = 384, \
424 .timestamp_frequency = 12500000
426 static const struct gen_device_info gen_device_info_bdw_gt1
= {
427 GEN8_FEATURES
, .gt
= 1,
428 .is_broadwell
= true,
430 .num_subslices
= { 2, },
431 .num_eu_per_subslice
= 8,
433 .max_cs_threads
= 42,
437 [MESA_SHADER_VERTEX
] = 64,
438 [MESA_SHADER_TESS_EVAL
] = 34,
441 [MESA_SHADER_VERTEX
] = 2560,
442 [MESA_SHADER_TESS_CTRL
] = 504,
443 [MESA_SHADER_TESS_EVAL
] = 1536,
444 [MESA_SHADER_GEOMETRY
] = 960,
450 static const struct gen_device_info gen_device_info_bdw_gt2
= {
451 GEN8_FEATURES
, .gt
= 2,
452 .is_broadwell
= true,
454 .num_subslices
= { 3, },
455 .num_eu_per_subslice
= 8,
457 .max_cs_threads
= 56,
461 [MESA_SHADER_VERTEX
] = 64,
462 [MESA_SHADER_TESS_EVAL
] = 34,
465 [MESA_SHADER_VERTEX
] = 2560,
466 [MESA_SHADER_TESS_CTRL
] = 504,
467 [MESA_SHADER_TESS_EVAL
] = 1536,
468 [MESA_SHADER_GEOMETRY
] = 960,
474 static const struct gen_device_info gen_device_info_bdw_gt3
= {
475 GEN8_FEATURES
, .gt
= 3,
476 .is_broadwell
= true,
478 .num_subslices
= { 3, 3, },
479 .num_eu_per_subslice
= 8,
481 .max_cs_threads
= 56,
485 [MESA_SHADER_VERTEX
] = 64,
486 [MESA_SHADER_TESS_EVAL
] = 34,
489 [MESA_SHADER_VERTEX
] = 2560,
490 [MESA_SHADER_TESS_CTRL
] = 504,
491 [MESA_SHADER_TESS_EVAL
] = 1536,
492 [MESA_SHADER_GEOMETRY
] = 960,
498 static const struct gen_device_info gen_device_info_chv
= {
499 GEN8_FEATURES
, .is_cherryview
= 1, .gt
= 1,
501 .has_integer_dword_mul
= false,
503 .num_subslices
= { 2, },
504 .num_eu_per_subslice
= 8,
506 .max_vs_threads
= 80,
507 .max_tcs_threads
= 80,
508 .max_tes_threads
= 80,
509 .max_gs_threads
= 80,
510 .max_wm_threads
= 128,
511 .max_cs_threads
= 6 * 7,
515 [MESA_SHADER_VERTEX
] = 34,
516 [MESA_SHADER_TESS_EVAL
] = 34,
519 [MESA_SHADER_VERTEX
] = 640,
520 [MESA_SHADER_TESS_CTRL
] = 80,
521 [MESA_SHADER_TESS_EVAL
] = 384,
522 [MESA_SHADER_GEOMETRY
] = 256,
528 #define GEN9_HW_INFO \
530 .max_vs_threads = 336, \
531 .max_gs_threads = 336, \
532 .max_tcs_threads = 336, \
533 .max_tes_threads = 336, \
534 .max_cs_threads = 56, \
535 .timestamp_frequency = 12000000, \
539 [MESA_SHADER_VERTEX] = 64, \
540 [MESA_SHADER_TESS_EVAL] = 34, \
543 [MESA_SHADER_VERTEX] = 1856, \
544 [MESA_SHADER_TESS_CTRL] = 672, \
545 [MESA_SHADER_TESS_EVAL] = 1120, \
546 [MESA_SHADER_GEOMETRY] = 640, \
550 #define GEN9_LP_FEATURES \
553 .has_integer_dword_mul = false, \
556 .has_sample_with_hiz = true, \
558 .num_thread_per_eu = 6, \
559 .max_vs_threads = 112, \
560 .max_tcs_threads = 112, \
561 .max_tes_threads = 112, \
562 .max_gs_threads = 112, \
563 .max_cs_threads = 6 * 6, \
564 .timestamp_frequency = 19200000, \
568 [MESA_SHADER_VERTEX] = 34, \
569 [MESA_SHADER_TESS_EVAL] = 34, \
572 [MESA_SHADER_VERTEX] = 704, \
573 [MESA_SHADER_TESS_CTRL] = 256, \
574 [MESA_SHADER_TESS_EVAL] = 416, \
575 [MESA_SHADER_GEOMETRY] = 256, \
579 #define GEN9_LP_FEATURES_3X6 \
581 .num_subslices = { 3, }, \
582 .num_eu_per_subslice = 6
584 #define GEN9_LP_FEATURES_2X6 \
586 .num_subslices = { 2, }, \
587 .num_eu_per_subslice = 6, \
588 .max_vs_threads = 56, \
589 .max_tcs_threads = 56, \
590 .max_tes_threads = 56, \
591 .max_gs_threads = 56, \
592 .max_cs_threads = 6 * 6, \
596 [MESA_SHADER_VERTEX] = 34, \
597 [MESA_SHADER_TESS_EVAL] = 34, \
600 [MESA_SHADER_VERTEX] = 352, \
601 [MESA_SHADER_TESS_CTRL] = 128, \
602 [MESA_SHADER_TESS_EVAL] = 208, \
603 [MESA_SHADER_GEOMETRY] = 128, \
607 #define GEN9_FEATURES \
610 .has_sample_with_hiz = true
612 static const struct gen_device_info gen_device_info_skl_gt1
= {
613 GEN9_FEATURES
, .gt
= 1,
616 .num_subslices
= { 2, },
617 .num_eu_per_subslice
= 6,
620 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
621 * leading to some vertices to go missing if we use too much URB.
623 .urb
.max_entries
[MESA_SHADER_VERTEX
] = 928,
627 static const struct gen_device_info gen_device_info_skl_gt2
= {
628 GEN9_FEATURES
, .gt
= 2,
631 .num_subslices
= { 3, },
632 .num_eu_per_subslice
= 8,
637 static const struct gen_device_info gen_device_info_skl_gt3
= {
638 GEN9_FEATURES
, .gt
= 3,
641 .num_subslices
= { 3, 3, },
642 .num_eu_per_subslice
= 8,
647 static const struct gen_device_info gen_device_info_skl_gt4
= {
648 GEN9_FEATURES
, .gt
= 4,
651 .num_subslices
= { 3, 3, 3, },
652 .num_eu_per_subslice
= 8,
654 /* From the "L3 Allocation and Programming" documentation:
656 * "URB is limited to 1008KB due to programming restrictions. This is not a
657 * restriction of the L3 implementation, but of the FF and other clients.
658 * Therefore, in a GT4 implementation it is possible for the programmed
659 * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
660 * only 1008KB of this will be used."
662 .urb
.size
= 1008 / 3,
666 static const struct gen_device_info gen_device_info_bxt
= {
667 GEN9_LP_FEATURES_3X6
,
673 static const struct gen_device_info gen_device_info_bxt_2x6
= {
674 GEN9_LP_FEATURES_2X6
,
680 * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
681 * There's no KBL entry. Using the default SKL (GEN9) GS entries value.
684 static const struct gen_device_info gen_device_info_kbl_gt1
= {
689 .max_cs_threads
= 7 * 6,
692 .num_subslices
= { 2, },
693 .num_eu_per_subslice
= 6,
695 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
696 * leading to some vertices to go missing if we use too much URB.
698 .urb
.max_entries
[MESA_SHADER_VERTEX
] = 928,
702 static const struct gen_device_info gen_device_info_kbl_gt1_5
= {
707 .max_cs_threads
= 7 * 6,
709 .num_subslices
= { 3, },
710 .num_eu_per_subslice
= 6,
715 static const struct gen_device_info gen_device_info_kbl_gt2
= {
721 .num_subslices
= { 3, },
722 .num_eu_per_subslice
= 8,
727 static const struct gen_device_info gen_device_info_kbl_gt3
= {
733 .num_subslices
= { 3, 3, },
734 .num_eu_per_subslice
= 8,
739 static const struct gen_device_info gen_device_info_kbl_gt4
= {
745 * From the "L3 Allocation and Programming" documentation:
747 * "URB is limited to 1008KB due to programming restrictions. This
748 * is not a restriction of the L3 implementation, but of the FF and
749 * other clients. Therefore, in a GT4 implementation it is
750 * possible for the programmed allocation of the L3 data array to
751 * provide 3*384KB=1152KB for URB, but only 1008KB of this
754 .urb
.size
= 1008 / 3,
756 .num_subslices
= { 3, 3, 3, },
757 .num_eu_per_subslice
= 8,
762 static const struct gen_device_info gen_device_info_glk
= {
763 GEN9_LP_FEATURES_3X6
,
764 .is_geminilake
= true,
769 static const struct gen_device_info gen_device_info_glk_2x6
= {
770 GEN9_LP_FEATURES_2X6
,
771 .is_geminilake
= true,
776 static const struct gen_device_info gen_device_info_cfl_gt1
= {
778 .is_coffeelake
= true,
782 .num_subslices
= { 2, },
783 .num_eu_per_subslice
= 6,
786 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
787 * leading to some vertices to go missing if we use too much URB.
789 .urb
.max_entries
[MESA_SHADER_VERTEX
] = 928,
792 static const struct gen_device_info gen_device_info_cfl_gt2
= {
794 .is_coffeelake
= true,
798 .num_subslices
= { 3, },
799 .num_eu_per_subslice
= 8,
804 static const struct gen_device_info gen_device_info_cfl_gt3
= {
806 .is_coffeelake
= true,
810 .num_subslices
= { 3, 3, },
811 .num_eu_per_subslice
= 8,
816 #define GEN10_HW_INFO \
818 .num_thread_per_eu = 7, \
819 .max_vs_threads = 728, \
820 .max_gs_threads = 432, \
821 .max_tcs_threads = 432, \
822 .max_tes_threads = 624, \
823 .max_cs_threads = 56, \
824 .timestamp_frequency = 19200000, \
828 [MESA_SHADER_VERTEX] = 64, \
829 [MESA_SHADER_TESS_EVAL] = 34, \
832 [MESA_SHADER_VERTEX] = 3936, \
833 [MESA_SHADER_TESS_CTRL] = 896, \
834 [MESA_SHADER_TESS_EVAL] = 2064, \
835 [MESA_SHADER_GEOMETRY] = 832, \
839 #define subslices(args...) { args, }
841 #define GEN10_FEATURES(_gt, _slices, _subslices, _l3) \
844 .has_sample_with_hiz = true, \
846 .num_slices = _slices, \
847 .num_subslices = _subslices, \
848 .num_eu_per_subslice = 8, \
851 static const struct gen_device_info gen_device_info_cnl_2x8
= {
853 GEN10_FEATURES(1, 1, subslices(2), 2),
854 .is_cannonlake
= true,
858 static const struct gen_device_info gen_device_info_cnl_3x8
= {
860 GEN10_FEATURES(1, 1, subslices(3), 3),
861 .is_cannonlake
= true,
865 static const struct gen_device_info gen_device_info_cnl_4x8
= {
867 GEN10_FEATURES(1, 2, subslices(2, 2), 6),
868 .is_cannonlake
= true,
872 static const struct gen_device_info gen_device_info_cnl_5x8
= {
874 GEN10_FEATURES(2, 2, subslices(3, 2), 6),
875 .is_cannonlake
= true,
879 #define GEN11_HW_INFO \
882 .max_vs_threads = 364, \
883 .max_gs_threads = 224, \
884 .max_tcs_threads = 224, \
885 .max_tes_threads = 364, \
888 #define GEN11_FEATURES(_gt, _slices, _subslices, _l3) \
891 .has_64bit_types = false, \
892 .has_integer_dword_mul = false, \
893 .has_sample_with_hiz = false, \
894 .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
895 .num_subslices = _subslices, \
896 .num_eu_per_subslice = 8
898 #define GEN11_URB_MIN_MAX_ENTRIES \
900 [MESA_SHADER_VERTEX] = 64, \
901 [MESA_SHADER_TESS_EVAL] = 34, \
904 [MESA_SHADER_VERTEX] = 2384, \
905 [MESA_SHADER_TESS_CTRL] = 1032, \
906 [MESA_SHADER_TESS_EVAL] = 2384, \
907 [MESA_SHADER_GEOMETRY] = 1032, \
910 static const struct gen_device_info gen_device_info_icl_8x8
= {
911 GEN11_FEATURES(2, 1, subslices(8), 8),
914 GEN11_URB_MIN_MAX_ENTRIES
,
919 static const struct gen_device_info gen_device_info_icl_6x8
= {
920 GEN11_FEATURES(1, 1, subslices(6), 6),
923 GEN11_URB_MIN_MAX_ENTRIES
,
928 static const struct gen_device_info gen_device_info_icl_4x8
= {
929 GEN11_FEATURES(1, 1, subslices(4), 6),
932 GEN11_URB_MIN_MAX_ENTRIES
,
937 static const struct gen_device_info gen_device_info_icl_1x8
= {
938 GEN11_FEATURES(1, 1, subslices(1), 6),
941 GEN11_URB_MIN_MAX_ENTRIES
,
946 static const struct gen_device_info gen_device_info_ehl_4x8
= {
947 GEN11_FEATURES(1, 1, subslices(4), 4),
951 [MESA_SHADER_VERTEX
] = 64,
952 [MESA_SHADER_TESS_EVAL
] = 34,
955 [MESA_SHADER_VERTEX
] = 2384,
956 [MESA_SHADER_TESS_CTRL
] = 1032,
957 [MESA_SHADER_TESS_EVAL
] = 2384,
958 [MESA_SHADER_GEOMETRY
] = 1032,
964 /* FIXME: Verfiy below entries when more information is available for this SKU.
966 static const struct gen_device_info gen_device_info_ehl_4x4
= {
967 GEN11_FEATURES(1, 1, subslices(4), 4),
971 [MESA_SHADER_VERTEX
] = 64,
972 [MESA_SHADER_TESS_EVAL
] = 34,
975 [MESA_SHADER_VERTEX
] = 2384,
976 [MESA_SHADER_TESS_CTRL
] = 1032,
977 [MESA_SHADER_TESS_EVAL
] = 2384,
978 [MESA_SHADER_GEOMETRY
] = 1032,
981 .num_eu_per_subslice
= 4,
985 /* FIXME: Verfiy below entries when more information is available for this SKU.
987 static const struct gen_device_info gen_device_info_ehl_2x4
= {
988 GEN11_FEATURES(1, 1, subslices(2), 4),
992 [MESA_SHADER_VERTEX
] = 64,
993 [MESA_SHADER_TESS_EVAL
] = 34,
996 [MESA_SHADER_VERTEX
] = 2384,
997 [MESA_SHADER_TESS_CTRL
] = 1032,
998 [MESA_SHADER_TESS_EVAL
] = 2384,
999 [MESA_SHADER_GEOMETRY
] = 1032,
1002 .num_eu_per_subslice
=4,
1007 gen_device_info_set_eu_mask(struct gen_device_info
*devinfo
,
1012 unsigned subslice_offset
= slice
* devinfo
->eu_slice_stride
+
1013 subslice
* devinfo
->eu_subslice_stride
;
1015 for (unsigned b_eu
= 0; b_eu
< devinfo
->eu_subslice_stride
; b_eu
++) {
1016 devinfo
->eu_masks
[subslice_offset
+ b_eu
] =
1017 (((1U << devinfo
->num_eu_per_subslice
) - 1) >> (b_eu
* 8)) & 0xff;
1021 /* Generate slice/subslice/eu masks from number of
1022 * slices/subslices/eu_per_subslices in the per generation/gt gen_device_info
1025 * These can be overridden with values reported by the kernel either from
1026 * getparam SLICE_MASK/SUBSLICE_MASK values or from the kernel version 4.17+
1027 * through the i915 query uapi.
1030 fill_masks(struct gen_device_info
*devinfo
)
1032 devinfo
->slice_masks
= (1U << devinfo
->num_slices
) - 1;
1034 /* Subslice masks */
1035 unsigned max_subslices
= 0;
1036 for (int s
= 0; s
< devinfo
->num_slices
; s
++)
1037 max_subslices
= MAX2(devinfo
->num_subslices
[s
], max_subslices
);
1038 devinfo
->subslice_slice_stride
= DIV_ROUND_UP(max_subslices
, 8);
1040 for (int s
= 0; s
< devinfo
->num_slices
; s
++) {
1041 devinfo
->subslice_masks
[s
* devinfo
->subslice_slice_stride
] =
1042 (1U << devinfo
->num_subslices
[s
]) - 1;
1046 devinfo
->eu_subslice_stride
= DIV_ROUND_UP(devinfo
->num_eu_per_subslice
, 8);
1047 devinfo
->eu_slice_stride
= max_subslices
* devinfo
->eu_subslice_stride
;
1049 for (int s
= 0; s
< devinfo
->num_slices
; s
++) {
1050 for (int ss
= 0; ss
< devinfo
->num_subslices
[s
]; ss
++) {
1051 gen_device_info_set_eu_mask(devinfo
, s
, ss
,
1052 (1U << devinfo
->num_eu_per_subslice
) - 1);
1058 gen_device_info_update_from_masks(struct gen_device_info
*devinfo
,
1059 uint32_t slice_mask
,
1060 uint32_t subslice_mask
,
1064 struct drm_i915_query_topology_info base
;
1068 assert((slice_mask
& 0xff) == slice_mask
);
1070 memset(&topology
, 0, sizeof(topology
));
1072 topology
.base
.max_slices
= util_last_bit(slice_mask
);
1073 topology
.base
.max_subslices
= util_last_bit(subslice_mask
);
1075 topology
.base
.subslice_offset
= DIV_ROUND_UP(topology
.base
.max_slices
, 8);
1076 topology
.base
.subslice_stride
= DIV_ROUND_UP(topology
.base
.max_subslices
, 8);
1078 uint32_t n_subslices
= __builtin_popcount(slice_mask
) *
1079 __builtin_popcount(subslice_mask
);
1080 uint32_t num_eu_per_subslice
= DIV_ROUND_UP(n_eus
, n_subslices
);
1081 uint32_t eu_mask
= (1U << num_eu_per_subslice
) - 1;
1083 topology
.base
.eu_offset
= topology
.base
.subslice_offset
+
1084 DIV_ROUND_UP(topology
.base
.max_subslices
, 8);
1085 topology
.base
.eu_stride
= DIV_ROUND_UP(num_eu_per_subslice
, 8);
1087 /* Set slice mask in topology */
1088 for (int b
= 0; b
< topology
.base
.subslice_offset
; b
++)
1089 topology
.base
.data
[b
] = (slice_mask
>> (b
* 8)) & 0xff;
1091 for (int s
= 0; s
< topology
.base
.max_slices
; s
++) {
1093 /* Set subslice mask in topology */
1094 for (int b
= 0; b
< topology
.base
.subslice_stride
; b
++) {
1095 int subslice_offset
= topology
.base
.subslice_offset
+
1096 s
* topology
.base
.subslice_stride
+ b
;
1098 topology
.base
.data
[subslice_offset
] = (subslice_mask
>> (b
* 8)) & 0xff;
1101 /* Set eu mask in topology */
1102 for (int ss
= 0; ss
< topology
.base
.max_subslices
; ss
++) {
1103 for (int b
= 0; b
< topology
.base
.eu_stride
; b
++) {
1104 int eu_offset
= topology
.base
.eu_offset
+
1105 (s
* topology
.base
.max_subslices
+ ss
) * topology
.base
.eu_stride
+ b
;
1107 topology
.base
.data
[eu_offset
] = (eu_mask
>> (b
* 8)) & 0xff;
1112 gen_device_info_update_from_topology(devinfo
, &topology
.base
);
1116 reset_masks(struct gen_device_info
*devinfo
)
1118 devinfo
->subslice_slice_stride
= 0;
1119 devinfo
->eu_subslice_stride
= 0;
1120 devinfo
->eu_slice_stride
= 0;
1122 devinfo
->num_slices
= 0;
1123 devinfo
->num_eu_per_subslice
= 0;
1124 memset(devinfo
->num_subslices
, 0, sizeof(devinfo
->num_subslices
));
1126 memset(&devinfo
->slice_masks
, 0, sizeof(devinfo
->slice_masks
));
1127 memset(devinfo
->subslice_masks
, 0, sizeof(devinfo
->subslice_masks
));
1128 memset(devinfo
->eu_masks
, 0, sizeof(devinfo
->eu_masks
));
1132 gen_device_info_update_from_topology(struct gen_device_info
*devinfo
,
1133 const struct drm_i915_query_topology_info
*topology
)
1135 reset_masks(devinfo
);
1137 devinfo
->subslice_slice_stride
= topology
->subslice_stride
;
1139 devinfo
->eu_subslice_stride
= DIV_ROUND_UP(topology
->max_eus_per_subslice
, 8);
1140 devinfo
->eu_slice_stride
= topology
->max_subslices
* devinfo
->eu_subslice_stride
;
1142 assert(sizeof(devinfo
->slice_masks
) >= DIV_ROUND_UP(topology
->max_slices
, 8));
1143 memcpy(&devinfo
->slice_masks
, topology
->data
, DIV_ROUND_UP(topology
->max_slices
, 8));
1144 devinfo
->num_slices
= __builtin_popcount(devinfo
->slice_masks
);
1146 uint32_t subslice_mask_len
=
1147 topology
->max_slices
* topology
->subslice_stride
;
1148 assert(sizeof(devinfo
->subslice_masks
) >= subslice_mask_len
);
1149 memcpy(devinfo
->subslice_masks
, &topology
->data
[topology
->subslice_offset
],
1152 uint32_t n_subslices
= 0;
1153 for (int s
= 0; s
< topology
->max_slices
; s
++) {
1154 if ((devinfo
->slice_masks
& (1UL << s
)) == 0)
1157 for (int b
= 0; b
< devinfo
->subslice_slice_stride
; b
++) {
1158 devinfo
->num_subslices
[s
] +=
1159 __builtin_popcount(devinfo
->subslice_masks
[b
]);
1161 n_subslices
+= devinfo
->num_subslices
[s
];
1163 assert(n_subslices
> 0);
1165 uint32_t eu_mask_len
=
1166 topology
->eu_stride
* topology
->max_subslices
* topology
->max_slices
;
1167 assert(sizeof(devinfo
->eu_masks
) >= eu_mask_len
);
1168 memcpy(devinfo
->eu_masks
, &topology
->data
[topology
->eu_offset
], eu_mask_len
);
1171 for (int b
= 0; b
< eu_mask_len
; b
++)
1172 n_eus
+= __builtin_popcount(devinfo
->eu_masks
[b
]);
1174 devinfo
->num_eu_per_subslice
= DIV_ROUND_UP(n_eus
, n_subslices
);
1178 gen_get_device_info(int devid
, struct gen_device_info
*devinfo
)
1182 #define CHIPSET(id, family, name) \
1183 case id: *devinfo = gen_device_info_##family; break;
1184 #include "pci_ids/i965_pci_ids.h"
1186 fprintf(stderr
, "i965_dri.so does not support the 0x%x PCI ID.\n", devid
);
1190 fill_masks(devinfo
);
1192 /* From the Skylake PRM, 3DSTATE_PS::Scratch Space Base Pointer:
1194 * "Scratch Space per slice is computed based on 4 sub-slices. SW must
1195 * allocate scratch space enough so that each slice has 4 slices allowed."
1197 * The equivalent internal documentation says that this programming note
1198 * applies to all Gen9+ platforms.
1200 * The hardware typically calculates the scratch space pointer by taking
1201 * the base address, and adding per-thread-scratch-space * thread ID.
1202 * Extra padding can be necessary depending how the thread IDs are
1203 * calculated for a particular shader stage.
1206 switch(devinfo
->gen
) {
1209 devinfo
->max_wm_threads
= 64 /* threads-per-PSD */
1210 * devinfo
->num_slices
1211 * 4; /* effective subslices per slice */
1214 devinfo
->max_wm_threads
= 128 /* threads-per-PSD */
1215 * devinfo
->num_slices
1216 * 8; /* subslices per slice */
1222 assert(devinfo
->num_slices
<= ARRAY_SIZE(devinfo
->num_subslices
));
1228 gen_get_device_name(int devid
)
1232 #define CHIPSET(id, family, name) case id: return name;
1233 #include "pci_ids/i965_pci_ids.h"