src/intel/tools/i965_gram.y

   1 %{
   2 /*
   3  * Copyright © 2018 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #include <stdio.h>
  26 #include <stdlib.h>
  27 #include <string.h>
  28 #include <strings.h>
  29 #include "i965_asm.h"
  30
  31 #define YYLTYPE YYLTYPE
  32 typedef struct YYLTYPE
  33 {
  34         int first_line;
  35         int first_column;
  36         int last_line;
  37         int last_column;
  38 } YYLTYPE;
  39
  40 enum message_level {
  41         WARN,
  42         ERROR,
  43 };
  44
  45 int yydebug = 1;
  46
  47 static void
  48 message(enum message_level level, YYLTYPE *location,
  49         const char *fmt, ...)
  50 {
  51         static const char *level_str[] = { "warning", "error" };
  52         va_list args;
  53
  54         if (location)
  55                 fprintf(stderr, "%s:%d:%d: %s: ", input_filename,
  56                         location->first_line,
  57                         location->first_column, level_str[level]);
  58         else
  59                 fprintf(stderr, "%s:%s: ", input_filename, level_str[level]);
  60
  61         va_start(args, fmt);
  62         vfprintf(stderr, fmt, args);
  63         va_end(args);
  64 }
  65
  66 #define warn(flag, l, fmt, ...)                                  \
  67         do {                                                     \
  68                 if (warning_flags & WARN_ ## flag)               \
  69                         message(WARN, l, fmt, ## __VA_ARGS__);   \
  70         } while (0)
  71
  72 #define error(l, fmt, ...)                                       \
  73         do {                                                     \
  74                 message(ERROR, l, fmt, ## __VA_ARGS__);          \
  75         } while (0)
  76
  77 static bool
  78 isPowerofTwo(unsigned int x)
  79 {
  80         return x && (!(x & (x - 1)));
  81 }
  82
  83 static struct brw_reg
  84 set_direct_src_operand(struct brw_reg *reg, int type)
  85 {
  86         return brw_reg(reg->file,
  87                        reg->nr,
  88                        reg->subnr,
  89                        0,               // negate
  90                        0,               // abs
  91                        type,
  92                        0,               // vstride
  93                        0,               // width
  94                        0,               // hstride
  95                        BRW_SWIZZLE_NOOP,
  96                        WRITEMASK_XYZW);
  97 }
  98
  99 static void
 100 i965_asm_unary_instruction(int opcode, struct brw_codegen *p,
 101                            struct brw_reg dest, struct brw_reg src0)
 102 {
 103         switch (opcode) {
 104         case BRW_OPCODE_BFREV:
 105                 brw_BFREV(p, dest, src0);
 106                 break;
 107         case BRW_OPCODE_CBIT:
 108                 brw_CBIT(p, dest, src0);
 109                 break;
 110         case BRW_OPCODE_F32TO16:
 111                 brw_F32TO16(p, dest, src0);
 112                 break;
 113         case BRW_OPCODE_F16TO32:
 114                 brw_F16TO32(p, dest, src0);
 115                 break;
 116         case BRW_OPCODE_MOV:
 117                 brw_MOV(p, dest, src0);
 118                 break;
 119         case BRW_OPCODE_FBL:
 120                 brw_FBL(p, dest, src0);
 121                 break;
 122         case BRW_OPCODE_FRC:
 123                 brw_FRC(p, dest, src0);
 124                 break;
 125         case BRW_OPCODE_FBH:
 126                 brw_FBH(p, dest, src0);
 127                 break;
 128         case BRW_OPCODE_NOT:
 129                 brw_NOT(p, dest, src0);
 130                 break;
 131         case BRW_OPCODE_RNDE:
 132                 brw_RNDE(p, dest, src0);
 133                 break;
 134         case BRW_OPCODE_RNDZ:
 135                 brw_RNDZ(p, dest, src0);
 136                 break;
 137         case BRW_OPCODE_RNDD:
 138                 brw_RNDD(p, dest, src0);
 139                 break;
 140         case BRW_OPCODE_LZD:
 141                 brw_LZD(p, dest, src0);
 142                 break;
 143         case BRW_OPCODE_DIM:
 144                 brw_DIM(p, dest, src0);
 145                 break;
 146         case BRW_OPCODE_RNDU:
 147                 fprintf(stderr, "Opcode BRW_OPCODE_RNDU unhandled\n");
 148                 break;
 149         default:
 150                 fprintf(stderr, "Unsupported unary opcode\n");
 151         }
 152 }
 153
 154 static void
 155 i965_asm_binary_instruction(int opcode,
 156                             struct brw_codegen *p,
 157                             struct brw_reg dest,
 158                             struct brw_reg src0,
 159                             struct brw_reg src1)
 160 {
 161         switch (opcode) {
 162         case BRW_OPCODE_ADDC:
 163                 brw_ADDC(p, dest, src0, src1);
 164                 break;
 165         case BRW_OPCODE_BFI1:
 166                 brw_BFI1(p, dest, src0, src1);
 167                 break;
 168         case BRW_OPCODE_DP2:
 169                 brw_DP2(p, dest, src0, src1);
 170                 break;
 171         case BRW_OPCODE_DP3:
 172                 brw_DP3(p, dest, src0, src1);
 173                 break;
 174         case BRW_OPCODE_DP4:
 175                 brw_DP4(p, dest, src0, src1);
 176                 break;
 177         case BRW_OPCODE_DPH:
 178                 brw_DPH(p, dest, src0, src1);
 179                 break;
 180         case BRW_OPCODE_LINE:
 181                 brw_LINE(p, dest, src0, src1);
 182                 break;
 183         case BRW_OPCODE_MAC:
 184                 brw_MAC(p, dest, src0, src1);
 185                 break;
 186         case BRW_OPCODE_MACH:
 187                 brw_MACH(p, dest, src0, src1);
 188                 break;
 189         case BRW_OPCODE_PLN:
 190                 brw_PLN(p, dest, src0, src1);
 191                 break;
 192         case BRW_OPCODE_ROL:
 193                 brw_ROL(p, dest, src0, src1);
 194                 break;
 195         case BRW_OPCODE_ROR:
 196                 brw_ROR(p, dest, src0, src1);
 197                 break;
 198         case BRW_OPCODE_SAD2:
 199                 fprintf(stderr, "Opcode BRW_OPCODE_SAD2 unhandled\n");
 200                 break;
 201         case BRW_OPCODE_SADA2:
 202                 fprintf(stderr, "Opcode BRW_OPCODE_SADA2 unhandled\n");
 203                 break;
 204         case BRW_OPCODE_SUBB:
 205                 brw_SUBB(p, dest, src0, src1);
 206                 break;
 207         case BRW_OPCODE_ADD:
 208                 brw_ADD(p, dest, src0, src1);
 209                 break;
 210         case BRW_OPCODE_CMP:
 211                 /* Third parameter is conditional modifier
 212                  * which gets updated later
 213                  */
 214                 brw_CMP(p, dest, 0, src0, src1);
 215                 break;
 216         case BRW_OPCODE_AND:
 217                 brw_AND(p, dest, src0, src1);
 218                 break;
 219         case BRW_OPCODE_ASR:
 220                 brw_ASR(p, dest, src0, src1);
 221                 break;
 222         case BRW_OPCODE_AVG:
 223                 brw_AVG(p, dest, src0, src1);
 224                 break;
 225         case BRW_OPCODE_OR:
 226                 brw_OR(p, dest, src0, src1);
 227                 break;
 228         case BRW_OPCODE_SEL:
 229                 brw_SEL(p, dest, src0, src1);
 230                 break;
 231         case BRW_OPCODE_SHL:
 232                 brw_SHL(p, dest, src0, src1);
 233                 break;
 234         case BRW_OPCODE_SHR:
 235                 brw_SHR(p, dest, src0, src1);
 236                 break;
 237         case BRW_OPCODE_XOR:
 238                 brw_XOR(p, dest, src0, src1);
 239                 break;
 240         case BRW_OPCODE_MUL:
 241                 brw_MUL(p, dest, src0, src1);
 242                 break;
 243         default:
 244                 fprintf(stderr, "Unsupported binary opcode\n");
 245         }
 246 }
 247
 248 static void
 249 i965_asm_ternary_instruction(int opcode,
 250                              struct brw_codegen *p,
 251                              struct brw_reg dest,
 252                              struct brw_reg src0,
 253                              struct brw_reg src1,
 254                              struct brw_reg src2)
 255 {
 256         switch (opcode) {
 257         case BRW_OPCODE_MAD:
 258                 brw_MAD(p, dest, src0, src1, src2);
 259                 break;
 260         case BRW_OPCODE_CSEL:
 261                 brw_CSEL(p, dest, src0, src1, src2);
 262                 break;
 263         case BRW_OPCODE_LRP:
 264                 brw_LRP(p, dest, src0, src1, src2);
 265                 break;
 266         case BRW_OPCODE_BFE:
 267                 brw_BFE(p, dest, src0, src1, src2);
 268                 break;
 269         case BRW_OPCODE_BFI2:
 270                 brw_BFI2(p, dest, src0, src1, src2);
 271                 break;
 272         default:
 273                 fprintf(stderr, "Unsupported ternary opcode\n");
 274         }
 275 }
 276
 277 static void
 278 i965_asm_set_instruction_options(struct brw_codegen *p,
 279                                  struct options options)
 280 {
 281         brw_inst_set_access_mode(p->devinfo, brw_last_inst,
 282                                  options.access_mode);
 283         brw_inst_set_mask_control(p->devinfo, brw_last_inst,
 284                                   options.mask_control);
 285         brw_inst_set_thread_control(p->devinfo, brw_last_inst,
 286                                     options.thread_control);
 287         brw_inst_set_no_dd_check(p->devinfo, brw_last_inst,
 288                                  options.no_dd_check);
 289         brw_inst_set_no_dd_clear(p->devinfo, brw_last_inst,
 290                                  options.no_dd_clear);
 291         brw_inst_set_debug_control(p->devinfo, brw_last_inst,
 292                                    options.debug_control);
 293         if (p->devinfo->gen >= 6)
 294                 brw_inst_set_acc_wr_control(p->devinfo, brw_last_inst,
 295                                             options.acc_wr_control);
 296         brw_inst_set_cmpt_control(p->devinfo, brw_last_inst,
 297                                   options.compaction);
 298 }
 299
 300 static void
 301 i965_asm_set_dst_nr(struct brw_codegen *p,
 302                     struct brw_reg *reg,
 303                     struct options options)
 304 {
 305         if (p->devinfo->gen <= 6) {
 306                 if (reg->file == BRW_MESSAGE_REGISTER_FILE &&
 307                     options.qtr_ctrl == BRW_COMPRESSION_COMPRESSED &&
 308                     !options.is_compr)
 309                         reg->nr |= BRW_MRF_COMPR4;
 310         }
 311 }
 312
 313 %}
 314
 315 %locations
 316
 317 %start ROOT
 318
 319 %union {
 320         double number;
 321         int integer;
 322         unsigned long long int llint;
 323         struct brw_reg reg;
 324         struct brw_codegen *program;
 325         struct predicate predicate;
 326         struct condition condition;
 327         struct options options;
 328         brw_inst *instruction;
 329 }
 330
 331 %token ABS
 332 %token COLON
 333 %token COMMA
 334 %token DOT
 335 %token LANGLE RANGLE
 336 %token LCURLY RCURLY
 337 %token LPAREN RPAREN
 338 %token LSQUARE RSQUARE
 339 %token PLUS MINUS
 340 %token SEMICOLON
 341
 342 /* datatypes */
 343 %token <integer> TYPE_B TYPE_UB
 344 %token <integer> TYPE_W TYPE_UW
 345 %token <integer> TYPE_D TYPE_UD
 346 %token <integer> TYPE_Q TYPE_UQ
 347 %token <integer> TYPE_V TYPE_UV
 348 %token <integer> TYPE_F TYPE_HF
 349 %token <integer> TYPE_DF TYPE_NF
 350 %token <integer> TYPE_VF
 351
 352 /* opcodes */
 353 %token <integer> ADD ADD3 ADDC AND ASR AVG
 354 %token <integer> BFE BFI1 BFI2 BFB BFREV BRC BRD BREAK
 355 %token <integer> CALL CALLA CASE CBIT CMP CMPN CONT CSEL
 356 %token <integer> DIM DO DPAS DPASW DP2 DP3 DP4 DP4A DPH
 357 %token <integer> ELSE ENDIF F16TO32 F32TO16 FBH FBL FORK FRC
 358 %token <integer> GOTO
 359 %token <integer> HALT
 360 %token <integer> IF IFF ILLEGAL
 361 %token <integer> JMPI JOIN
 362 %token <integer> LINE LRP LZD
 363 %token <integer> MAC MACH MAD MADM MOV MOVI MUL MREST MSAVE
 364 %token <integer> NENOP NOP NOT
 365 %token <integer> OR
 366 %token <integer> PLN POP PUSH
 367 %token <integer> RET RNDD RNDE RNDU RNDZ ROL ROR
 368 %token <integer> SAD2 SADA2 SEL SEND SENDC SENDS SENDSC SHL SHR SMOV SUBB SYNC
 369 %token <integer> WAIT WHILE
 370 %token <integer> XOR
 371
 372 /* extended math functions */
 373 %token <integer> COS EXP FDIV INV INVM INTDIV INTDIVMOD INTMOD LOG POW RSQ
 374 %token <integer> RSQRTM SIN SINCOS SQRT
 375
 376 /* shared functions for send */
 377 %token CONST CRE DATA DP_DATA_1 GATEWAY MATH PIXEL_INTERP READ RENDER SAMPLER
 378 %token THREAD_SPAWNER URB VME WRITE DP_SAMPLER
 379
 380 /* Conditional modifiers */
 381 %token <integer> EQUAL GREATER GREATER_EQUAL LESS LESS_EQUAL NOT_EQUAL
 382 %token <integer> NOT_ZERO OVERFLOW UNORDERED ZERO
 383
 384 /* register Access Modes */
 385 %token ALIGN1 ALIGN16
 386
 387 /* accumulator write control */
 388 %token ACCWREN
 389
 390 /* compaction control */
 391 %token CMPTCTRL
 392
 393 /* compression control */
 394 %token COMPR COMPR4 SECHALF
 395
 396 /* mask control (WeCtrl) */
 397 %token WECTRL
 398
 399 /* debug control */
 400 %token BREAKPOINT
 401
 402 /* dependency control */
 403 %token NODDCLR NODDCHK
 404
 405 /* end of thread */
 406 %token EOT
 407
 408 /* mask control */
 409 %token MASK_DISABLE;
 410
 411 /* predicate control */
 412 %token <integer> ANYV ALLV ANY2H ALL2H ANY4H ALL4H ANY8H ALL8H ANY16H ALL16H
 413 %token <integer> ANY32H ALL32H
 414
 415 /* round instructions */
 416 %token <integer> ROUND_INCREMENT
 417
 418 /* staturation */
 419 %token SATURATE
 420
 421 /* thread control */
 422 %token ATOMIC SWITCH
 423
 424 /* quater control */
 425 %token QTR_2Q QTR_3Q QTR_4Q QTR_2H QTR_2N QTR_3N QTR_4N QTR_5N
 426 %token QTR_6N QTR_7N QTR_8N
 427
 428 /* channels */
 429 %token <integer> X Y Z W
 430
 431 /* reg files */
 432 %token GENREGFILE MSGREGFILE
 433
 434 /* vertical stride in register region */
 435 %token VxH
 436
 437 /* register type */
 438 %token <integer> GENREG MSGREG ADDRREG ACCREG FLAGREG NOTIFYREG STATEREG
 439 %token <integer> CONTROLREG IPREG PERFORMANCEREG THREADREG CHANNELENABLEREG
 440 %token <integer> MASKREG
 441
 442 %token <integer> INTEGER
 443 %token <llint> LONG
 444 %token NULL_TOKEN
 445
 446 %precedence SUBREGNUM
 447 %left PLUS MINUS
 448 %precedence DOT
 449 %precedence EMPTYEXECSIZE
 450 %precedence LPAREN
 451
 452 %type <integer> execsize simple_int exp
 453 %type <llint> exp2
 454
 455 /* predicate control */
 456 %type <integer> predctrl predstate
 457 %type <predicate> predicate
 458
 459 /* conditional modifier */
 460 %type <condition> cond_mod
 461 %type <integer> condModifiers
 462
 463 /* instruction options  */
 464 %type <options> instoptions instoption_list
 465 %type <integer> instoption
 466
 467 /* writemask */
 468 %type <integer> writemask_x writemask_y writemask_z writemask_w
 469 %type <reg> writemask
 470
 471 /* dst operand */
 472 %type <reg> dst dstoperand dstoperandex dstoperandex_typed dstreg dsttype
 473 %type <integer> dstregion
 474
 475 %type <integer> saturate relativelocation rellocation
 476 %type <reg> relativelocation2
 477
 478 /* src operand */
 479 %type <reg> directsrcoperand directsrcaccoperand indirectsrcoperand srcacc
 480 %type <reg> srcarcoperandex srcaccimm srcarcoperandex_typed srctype srcimm
 481 %type <reg> srcimmtype indirectgenreg indirectregion
 482 %type <reg> immreg src reg32 payload directgenreg_list addrparam region
 483 %type <reg> region_wh swizzle directgenreg directmsgreg indirectmsgreg
 484
 485 /* registers */
 486 %type <reg> accreg addrreg channelenablereg controlreg flagreg ipreg
 487 %type <reg> notifyreg nullreg performancereg threadcontrolreg statereg maskreg
 488 %type <integer> subregnum
 489
 490 /* immediate values */
 491 %type <llint> immval
 492
 493 /* instruction opcodes */
 494 %type <integer> unaryopcodes binaryopcodes binaryaccopcodes ternaryopcodes
 495 %type <integer> sendop
 496 %type <instruction> sendopcode
 497
 498 %type <integer> negate abs chansel math_function sharedfunction
 499
 500 %code {
 501
 502 static void
 503 add_instruction_option(struct options *options, int option)
 504 {
 505         switch (option) {
 506         case ALIGN1:
 507                 options->access_mode = BRW_ALIGN_1;
 508                 break;
 509         case ALIGN16:
 510                 options->access_mode = BRW_ALIGN_16;
 511                 break;
 512         case SECHALF:
 513                 options->qtr_ctrl |= BRW_COMPRESSION_2NDHALF;
 514                 break;
 515         case COMPR:
 516                 options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED;
 517                 options->is_compr = true;
 518                 break;
 519         case COMPR4:
 520                 options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED;
 521                 break;
 522         case SWITCH:
 523                 options->thread_control |= BRW_THREAD_SWITCH;
 524                 break;
 525         case ATOMIC:
 526                 options->thread_control |= BRW_THREAD_ATOMIC;
 527                 break;
 528         case NODDCHK:
 529                 options->no_dd_check = true;
 530                 break;
 531         case NODDCLR:
 532                 options->no_dd_clear = BRW_DEPENDENCY_NOTCLEARED;
 533                 break;
 534         case MASK_DISABLE:
 535                 options->mask_control |= BRW_MASK_DISABLE;
 536                 break;
 537         case BREAKPOINT:
 538                 options->debug_control = BRW_DEBUG_BREAKPOINT;
 539                 break;
 540         case WECTRL:
 541                 options->mask_control |= BRW_WE_ALL;
 542                 break;
 543         case CMPTCTRL:
 544                 options->compaction = true;
 545                 break;
 546         case ACCWREN:
 547                 options->acc_wr_control = true;
 548                 break;
 549         case EOT:
 550                 options->end_of_thread = true;
 551                 break;
 552         /* TODO : Figure out how to set instruction group and get rid of
 553          * code below
 554          */
 555         case QTR_2Q:
 556                 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
 557                 break;
 558         case QTR_3Q:
 559                 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
 560                 break;
 561         case QTR_4Q:
 562                 options->qtr_ctrl = 3;
 563                 break;
 564         case QTR_2H:
 565                 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
 566                 break;
 567         case QTR_2N:
 568                 options->qtr_ctrl = BRW_COMPRESSION_NONE;
 569                 options->nib_ctrl = true;
 570                 break;
 571         case QTR_3N:
 572                 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
 573                 break;
 574         case QTR_4N:
 575                 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
 576                 options->nib_ctrl = true;
 577                 break;
 578         case QTR_5N:
 579                 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
 580                 break;
 581         case QTR_6N:
 582                 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
 583                 options->nib_ctrl = true;
 584                 break;
 585         case QTR_7N:
 586                 options->qtr_ctrl = 3;
 587                 break;
 588         case QTR_8N:
 589                 options->qtr_ctrl = 3;
 590                 options->nib_ctrl = true;
 591                 break;
 592         }
 593 }
 594 }
 595 %%
 596
 597 ROOT:
 598         instrseq
 599         ;
 600
 601 instrseq:
 602         instrseq instruction SEMICOLON
 603         | instrseq relocatableinstruction SEMICOLON
 604         | instruction SEMICOLON
 605         | relocatableinstruction SEMICOLON
 606         ;
 607
 608 /* Instruction Group */
 609 instruction:
 610         unaryinstruction
 611         | binaryinstruction
 612         | binaryaccinstruction
 613         | mathinstruction
 614         | nopinstruction
 615         | syncinstruction
 616         | ternaryinstruction
 617         | sendinstruction
 618         | illegalinstruction
 619         ;
 620
 621 relocatableinstruction:
 622         jumpinstruction
 623         | branchinstruction
 624         | breakinstruction
 625         | loopinstruction
 626         ;
 627
 628 illegalinstruction:
 629         ILLEGAL execsize instoptions
 630         {
 631                 brw_next_insn(p, $1);
 632                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
 633                 i965_asm_set_instruction_options(p, $3);
 634         }
 635         ;
 636
 637 /* Unary instruction */
 638 unaryinstruction:
 639         predicate unaryopcodes saturate cond_mod execsize dst srcaccimm instoptions
 640         {
 641                 i965_asm_set_dst_nr(p, &$6, $8);
 642                 brw_set_default_access_mode(p, $8.access_mode);
 643                 i965_asm_unary_instruction($2, p, $6, $7);
 644                 brw_pop_insn_state(p);
 645                 i965_asm_set_instruction_options(p, $8);
 646                 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
 647                                            $4.cond_modifier);
 648
 649                 if (p->devinfo->gen >= 7) {
 650                         if ($2 != BRW_OPCODE_DIM) {
 651                                 brw_inst_set_flag_reg_nr(p->devinfo,
 652                                                          brw_last_inst,
 653                                                          $4.flag_reg_nr);
 654                                 brw_inst_set_flag_subreg_nr(p->devinfo,
 655                                                             brw_last_inst,
 656                                                             $4.flag_subreg_nr);
 657                         }
 658                 }
 659
 660                 if ($7.file != BRW_IMMEDIATE_VALUE) {
 661                         brw_inst_set_src0_vstride(p->devinfo, brw_last_inst,
 662                                                   $7.vstride);
 663                 }
 664                 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
 665                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
 666                 // TODO: set instruction group instead of qtr and nib ctrl
 667                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 668                                          $8.qtr_ctrl);
 669
 670                 if (p->devinfo->gen >= 7)
 671                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 672                                                  $8.nib_ctrl);
 673         }
 674         ;
 675
 676 unaryopcodes:
 677         BFREV
 678         | CBIT
 679         | DIM
 680         | F16TO32
 681         | F32TO16
 682         | FBH
 683         | FBL
 684         | FRC
 685         | LZD
 686         | MOV
 687         | NOT
 688         | RNDD
 689         | RNDE
 690         | RNDU
 691         | RNDZ
 692         ;
 693
 694 /* Binary instruction */
 695 binaryinstruction:
 696         predicate binaryopcodes saturate cond_mod execsize dst srcimm srcimm instoptions
 697         {
 698                 i965_asm_set_dst_nr(p, &$6, $9);
 699                 brw_set_default_access_mode(p, $9.access_mode);
 700                 i965_asm_binary_instruction($2, p, $6, $7, $8);
 701                 i965_asm_set_instruction_options(p, $9);
 702                 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
 703                                            $4.cond_modifier);
 704
 705                 if (p->devinfo->gen >= 7) {
 706                         brw_inst_set_flag_reg_nr(p->devinfo, brw_last_inst,
 707                                                  $4.flag_reg_nr);
 708                         brw_inst_set_flag_subreg_nr(p->devinfo, brw_last_inst,
 709                                                     $4.flag_subreg_nr);
 710                 }
 711
 712                 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
 713                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
 714                 // TODO: set instruction group instead of qtr and nib ctrl
 715                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 716                                          $9.qtr_ctrl);
 717
 718                 if (p->devinfo->gen >= 7)
 719                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 720                                                  $9.nib_ctrl);
 721
 722                 brw_pop_insn_state(p);
 723         }
 724         ;
 725
 726 binaryopcodes:
 727         ADDC
 728         | BFI1
 729         | DP2
 730         | DP3
 731         | DP4
 732         | DPH
 733         | LINE
 734         | MAC
 735         | MACH
 736         | MUL
 737         | PLN
 738         | ROL
 739         | ROR
 740         | SAD2
 741         | SADA2
 742         | SUBB
 743         ;
 744
 745 /* Binary acc instruction */
 746 binaryaccinstruction:
 747         predicate binaryaccopcodes saturate cond_mod execsize dst srcacc srcimm instoptions
 748         {
 749                 i965_asm_set_dst_nr(p, &$6, $9);
 750                 brw_set_default_access_mode(p, $9.access_mode);
 751                 i965_asm_binary_instruction($2, p, $6, $7, $8);
 752                 brw_pop_insn_state(p);
 753                 i965_asm_set_instruction_options(p, $9);
 754                 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
 755                                            $4.cond_modifier);
 756
 757                 if (p->devinfo->gen >= 7) {
 758                         if (!brw_inst_flag_reg_nr(p->devinfo, brw_last_inst)) {
 759                                 brw_inst_set_flag_reg_nr(p->devinfo,
 760                                                          brw_last_inst,
 761                                                          $4.flag_reg_nr);
 762                                 brw_inst_set_flag_subreg_nr(p->devinfo,
 763                                                             brw_last_inst,
 764                                                             $4.flag_subreg_nr);
 765                         }
 766                 }
 767
 768                 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
 769                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
 770                 // TODO: set instruction group instead of qtr and nib ctrl
 771                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 772                                          $9.qtr_ctrl);
 773
 774                 if (p->devinfo->gen >= 7)
 775                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 776                                                  $9.nib_ctrl);
 777         }
 778         ;
 779
 780 binaryaccopcodes:
 781         ADD
 782         | AND
 783         | ASR
 784         | AVG
 785         | CMP
 786         | CMPN
 787         | OR
 788         | SEL
 789         | SHL
 790         | SHR
 791         | XOR
 792         ;
 793
 794 /* Math instruction */
 795 mathinstruction:
 796         predicate MATH saturate math_function execsize dst src srcimm instoptions
 797         {
 798                 brw_set_default_access_mode(p, $9.access_mode);
 799                 gen6_math(p, $6, $4, $7, $8);
 800                 i965_asm_set_instruction_options(p, $9);
 801                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
 802                 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
 803                 // TODO: set instruction group instead
 804                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 805                                          $9.qtr_ctrl);
 806
 807                 if (p->devinfo->gen >= 7)
 808                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 809                                                  $9.nib_ctrl);
 810
 811                 brw_pop_insn_state(p);
 812         }
 813         ;
 814
 815 math_function:
 816         COS
 817         | EXP
 818         | FDIV
 819         | INV
 820         | INVM
 821         | INTDIV
 822         | INTDIVMOD
 823         | INTMOD
 824         | LOG
 825         | POW
 826         | RSQ
 827         | RSQRTM
 828         | SIN
 829         | SQRT
 830         | SINCOS
 831         ;
 832
 833 /* NOP instruction */
 834 nopinstruction:
 835         NOP
 836         {
 837                 brw_NOP(p);
 838         }
 839         ;
 840
 841 /* Ternary operand instruction */
 842 ternaryinstruction:
 843         predicate ternaryopcodes saturate cond_mod execsize dst src src src instoptions
 844         {
 845                 brw_set_default_access_mode(p, $10.access_mode);
 846                 i965_asm_ternary_instruction($2, p, $6, $7, $8, $9);
 847                 brw_pop_insn_state(p);
 848                 i965_asm_set_instruction_options(p, $10);
 849                 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
 850                                            $4.cond_modifier);
 851
 852                 if (p->devinfo->gen >= 7) {
 853                         brw_inst_set_3src_a16_flag_reg_nr(p->devinfo, brw_last_inst,
 854                                                  $4.flag_reg_nr);
 855                         brw_inst_set_3src_a16_flag_subreg_nr(p->devinfo, brw_last_inst,
 856                                                     $4.flag_subreg_nr);
 857                 }
 858
 859                 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
 860                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
 861                 // TODO: set instruction group instead of qtr and nib ctrl
 862                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 863                                          $10.qtr_ctrl);
 864
 865                 if (p->devinfo->gen >= 7)
 866                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 867                                                  $10.nib_ctrl);
 868         }
 869         ;
 870
 871 ternaryopcodes:
 872         CSEL
 873         | BFE
 874         | BFI2
 875         | LRP
 876         | MAD
 877         ;
 878
 879 /* Sync instruction */
 880 syncinstruction:
 881         WAIT execsize src instoptions
 882         {
 883                 brw_next_insn(p, $1);
 884                 i965_asm_set_instruction_options(p, $4);
 885                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
 886                 brw_set_default_access_mode(p, $4.access_mode);
 887                 struct brw_reg src = brw_notification_reg();
 888                 brw_set_dest(p, brw_last_inst, src);
 889                 brw_set_src0(p, brw_last_inst, src);
 890                 brw_set_src1(p, brw_last_inst, brw_null_reg());
 891                 brw_inst_set_mask_control(p->devinfo, brw_last_inst, BRW_MASK_DISABLE);
 892         }
 893         ;
 894
 895 /* Send instruction */
 896 sendinstruction:
 897         predicate sendopcode execsize dst payload exp2 sharedfunction instoptions
 898         {
 899                 i965_asm_set_instruction_options(p, $8);
 900                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
 901                 brw_set_dest(p, brw_last_inst, $4);
 902                 brw_set_src0(p, brw_last_inst, $5);
 903                 brw_inst_set_bits(brw_last_inst, 127, 96, $6);
 904                 brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
 905                                             BRW_IMMEDIATE_VALUE,
 906                                             BRW_REGISTER_TYPE_UD);
 907                 brw_inst_set_sfid(p->devinfo, brw_last_inst, $7);
 908                 brw_inst_set_eot(p->devinfo, brw_last_inst, $8.end_of_thread);
 909                 // TODO: set instruction group instead of qtr and nib ctrl
 910                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 911                                          $8.qtr_ctrl);
 912
 913                 if (p->devinfo->gen >= 7)
 914                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 915                                                  $8.nib_ctrl);
 916
 917                 brw_pop_insn_state(p);
 918         }
 919         | predicate sendopcode execsize exp dst payload exp2 sharedfunction instoptions
 920         {
 921                 i965_asm_set_instruction_options(p, $9);
 922                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
 923                 brw_inst_set_base_mrf(p->devinfo, brw_last_inst, $4);
 924                 brw_set_dest(p, brw_last_inst, $5);
 925                 brw_set_src0(p, brw_last_inst, $6);
 926                 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
 927                 brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
 928                                             BRW_IMMEDIATE_VALUE,
 929                                             BRW_REGISTER_TYPE_UD);
 930                 brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
 931                 brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
 932                 // TODO: set instruction group instead of qtr and nib ctrl
 933                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 934                                          $9.qtr_ctrl);
 935
 936                 if (p->devinfo->gen >= 7)
 937                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 938                                                  $9.nib_ctrl);
 939
 940                 brw_pop_insn_state(p);
 941         }
 942         | predicate sendopcode execsize dst payload payload exp2 sharedfunction instoptions
 943         {
 944                 i965_asm_set_instruction_options(p, $9);
 945                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
 946                 brw_set_dest(p, brw_last_inst, $4);
 947                 brw_set_src0(p, brw_last_inst, $5);
 948                 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
 949                 brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
 950                 brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
 951                 // TODO: set instruction group instead of qtr and nib ctrl
 952                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 953                                          $9.qtr_ctrl);
 954
 955                 if (p->devinfo->gen >= 7)
 956                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 957                                                  $9.nib_ctrl);
 958
 959                 brw_pop_insn_state(p);
 960         }
 961         | predicate SENDS execsize dst payload payload exp2 exp2 sharedfunction instoptions
 962         {
 963                 brw_next_insn(p, $2);
 964                 i965_asm_set_instruction_options(p, $10);
 965                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
 966                 brw_set_dest(p, brw_last_inst, $4);
 967                 brw_set_src0(p, brw_last_inst, $5);
 968                 brw_set_src1(p, brw_last_inst, $6);
 969
 970                 if (brw_inst_send_sel_reg32_ex_desc(p->devinfo, brw_last_inst)) {
 971                         brw_inst_set_send_ex_desc_ia_subreg_nr(p->devinfo, brw_last_inst, $5.subnr);
 972                 } else {
 973                         brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8);
 974                 }
 975
 976                 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
 977                 brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
 978                 brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
 979                 // TODO: set instruction group instead of qtr and nib ctrl
 980                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 981                                          $10.qtr_ctrl);
 982
 983                 if (p->devinfo->gen >= 7)
 984                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 985                                                  $10.nib_ctrl);
 986
 987                 brw_pop_insn_state(p);
 988         }
 989         | predicate SENDS execsize dst payload payload src exp2 sharedfunction instoptions
 990         {
 991                 brw_next_insn(p, $2);
 992                 i965_asm_set_instruction_options(p, $10);
 993                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
 994                 brw_set_dest(p, brw_last_inst, $4);
 995                 brw_set_src0(p, brw_last_inst, $5);
 996                 brw_set_src1(p, brw_last_inst, $6);
 997
 998                 brw_inst_set_send_sel_reg32_desc(p->devinfo, brw_last_inst, 1);
 999                 brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8);
1000
1001                 brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
1002                 brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
1003                 // TODO: set instruction group instead of qtr and nib ctrl
1004                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
1005                                          $10.qtr_ctrl);
1006
1007                 if (p->devinfo->gen >= 7)
1008                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
1009                                                  $10.nib_ctrl);
1010
1011                 brw_pop_insn_state(p);
1012         }
1013         ;
1014
1015 sendop:
1016         SEND
1017         | SENDC
1018         ;
1019
1020 sendopcode:
1021         sendop   { $$ = brw_next_insn(p, $1); }
1022         ;
1023
1024 sharedfunction:
1025         NULL_TOKEN              { $$ = BRW_SFID_NULL; }
1026         | MATH                  { $$ = BRW_SFID_MATH; }
1027         | GATEWAY               { $$ = BRW_SFID_MESSAGE_GATEWAY; }
1028         | READ                  { $$ = BRW_SFID_DATAPORT_READ; }
1029         | WRITE                 { $$ = BRW_SFID_DATAPORT_WRITE; }
1030         | URB                   { $$ = BRW_SFID_URB; }
1031         | THREAD_SPAWNER        { $$ = BRW_SFID_THREAD_SPAWNER; }
1032         | VME                   { $$ = BRW_SFID_VME; }
1033         | RENDER                { $$ = GEN6_SFID_DATAPORT_RENDER_CACHE; }
1034         | CONST                 { $$ = GEN6_SFID_DATAPORT_CONSTANT_CACHE; }
1035         | DATA                  { $$ = GEN7_SFID_DATAPORT_DATA_CACHE; }
1036         | PIXEL_INTERP          { $$ = GEN7_SFID_PIXEL_INTERPOLATOR; }
1037         | DP_DATA_1             { $$ = HSW_SFID_DATAPORT_DATA_CACHE_1; }
1038         | CRE                   { $$ = HSW_SFID_CRE; }
1039         | SAMPLER               { $$ = BRW_SFID_SAMPLER; }
1040         | DP_SAMPLER            { $$ = GEN6_SFID_DATAPORT_SAMPLER_CACHE; }
1041         ;
1042
1043 exp2:
1044         LONG            { $$ = $1; }
1045         | MINUS LONG    { $$ = -$2; }
1046         ;
1047
1048 /* Jump instruction */
1049 jumpinstruction:
1050         predicate JMPI execsize relativelocation2 instoptions
1051         {
1052                 brw_next_insn(p, $2);
1053                 i965_asm_set_instruction_options(p, $5);
1054                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1055                 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1056                 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1057                 brw_set_src1(p, brw_last_inst, $4);
1058                 brw_inst_set_pred_control(p->devinfo, brw_last_inst,
1059                                           brw_inst_pred_control(p->devinfo,
1060                                                                 brw_last_inst));
1061                 brw_pop_insn_state(p);
1062         }
1063         ;
1064
1065 /* branch instruction */
1066 branchinstruction:
1067         predicate ENDIF execsize relativelocation instoptions
1068         {
1069                 brw_next_insn(p, $2);
1070                 i965_asm_set_instruction_options(p, $5);
1071                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1072
1073                 if (p->devinfo->gen < 6) {
1074                         brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1075                                      BRW_REGISTER_TYPE_D));
1076                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1077                                      BRW_REGISTER_TYPE_D));
1078                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1079                         brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1080                                                     $4);
1081                 } else if (p->devinfo->gen == 6) {
1082                         brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1083                         brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1084                                                      $4);
1085                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1086                                      BRW_REGISTER_TYPE_D));
1087                         brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
1088                                      BRW_REGISTER_TYPE_D));
1089                 } else if (p->devinfo->gen == 7) {
1090                         brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1091                                      BRW_REGISTER_TYPE_D));
1092                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1093                                      BRW_REGISTER_TYPE_D));
1094                         brw_set_src1(p, brw_last_inst, brw_imm_w(0x0));
1095                         brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1096                 } else {
1097                         brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1098                 }
1099
1100                 if (p->devinfo->gen < 6)
1101                         brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1102                                                     BRW_THREAD_SWITCH);
1103                 brw_pop_insn_state(p);
1104         }
1105         | ELSE execsize relativelocation rellocation instoptions
1106         {
1107                 brw_next_insn(p, $1);
1108                 i965_asm_set_instruction_options(p, $5);
1109                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1110
1111                 if (p->devinfo->gen < 6) {
1112                         brw_set_dest(p, brw_last_inst, brw_ip_reg());
1113                         brw_set_src0(p, brw_last_inst, brw_ip_reg());
1114                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1115                         brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1116                                                      $3);
1117                         brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1118                                                     $4);
1119                 } else if (p->devinfo->gen == 6) {
1120                         brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1121                         brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1122                                                      $3);
1123                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1124                                      BRW_REGISTER_TYPE_D));
1125                         brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
1126                                      BRW_REGISTER_TYPE_D));
1127                 } else if (p->devinfo->gen == 7) {
1128                         brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1129                                      BRW_REGISTER_TYPE_D));
1130                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1131                                      BRW_REGISTER_TYPE_D));
1132                         brw_set_src1(p, brw_last_inst, brw_imm_w($3));
1133                         brw_inst_set_jip(p->devinfo, brw_last_inst, $3);
1134                         brw_inst_set_uip(p->devinfo, brw_last_inst, $4);
1135                 } else {
1136                         brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1137                                      BRW_REGISTER_TYPE_D));
1138                         brw_set_src0(p, brw_last_inst, brw_imm_d($3));
1139                         brw_inst_set_jip(p->devinfo, brw_last_inst, $3);
1140                         brw_inst_set_uip(p->devinfo, brw_last_inst, $4);
1141                 }
1142
1143                 if (!p->single_program_flow && p->devinfo->gen < 6)
1144                         brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1145                                                     BRW_THREAD_SWITCH);
1146         }
1147         | predicate IF execsize relativelocation rellocation instoptions
1148         {
1149                 brw_next_insn(p, $2);
1150                 i965_asm_set_instruction_options(p, $6);
1151                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1152
1153                 if (p->devinfo->gen < 6) {
1154                         brw_set_dest(p, brw_last_inst, brw_ip_reg());
1155                         brw_set_src0(p, brw_last_inst, brw_ip_reg());
1156                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1157                         brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1158                                                      $4);
1159                         brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1160                                                     $5);
1161                 } else if (p->devinfo->gen == 6) {
1162                         brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1163                         brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1164                                                      $4);
1165                         brw_set_src0(p, brw_last_inst,
1166                                      vec1(retype(brw_null_reg(),
1167                                      BRW_REGISTER_TYPE_D)));
1168                         brw_set_src1(p, brw_last_inst,
1169                                      vec1(retype(brw_null_reg(),
1170                                      BRW_REGISTER_TYPE_D)));
1171                 } else if (p->devinfo->gen == 7) {
1172                         brw_set_dest(p, brw_last_inst,
1173                                      vec1(retype(brw_null_reg(),
1174                                      BRW_REGISTER_TYPE_D)));
1175                         brw_set_src0(p, brw_last_inst,
1176                                      vec1(retype(brw_null_reg(),
1177                                      BRW_REGISTER_TYPE_D)));
1178                         brw_set_src1(p, brw_last_inst, brw_imm_w($4));
1179                         brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1180                         brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1181                 } else {
1182                         brw_set_dest(p, brw_last_inst,
1183                                      vec1(retype(brw_null_reg(),
1184                                      BRW_REGISTER_TYPE_D)));
1185                         brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1186                         brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1187                         brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1188                 }
1189
1190                 if (!p->single_program_flow && p->devinfo->gen < 6)
1191                         brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1192                                                     BRW_THREAD_SWITCH);
1193
1194                 brw_pop_insn_state(p);
1195         }
1196         | predicate IFF execsize relativelocation instoptions
1197         {
1198                 brw_next_insn(p, $2);
1199                 i965_asm_set_instruction_options(p, $5);
1200                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1201
1202                 if (p->devinfo->gen < 6) {
1203                         brw_set_dest(p, brw_last_inst, brw_ip_reg());
1204                         brw_set_src0(p, brw_last_inst, brw_ip_reg());
1205                         brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1206                                                      $4);
1207                         brw_set_src1(p, brw_last_inst, brw_imm_d($4));
1208                 } else if (p->devinfo->gen == 6) {
1209                         brw_set_dest(p, brw_last_inst, brw_imm_w($4));
1210                         brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1211                                                      $4);
1212                         brw_set_src0(p, brw_last_inst,
1213                                      vec1(retype(brw_null_reg(),
1214                                      BRW_REGISTER_TYPE_D)));
1215                         brw_set_src1(p, brw_last_inst,
1216                                      vec1(retype(brw_null_reg(),
1217                                      BRW_REGISTER_TYPE_D)));
1218                 } else if (p->devinfo->gen == 7) {
1219                         brw_set_dest(p, brw_last_inst,
1220                                      vec1(retype(brw_null_reg(),
1221                                      BRW_REGISTER_TYPE_D)));
1222                         brw_set_src0(p, brw_last_inst,
1223                                      vec1(retype(brw_null_reg(),
1224                                      BRW_REGISTER_TYPE_D)));
1225                         brw_set_src1(p, brw_last_inst, brw_imm_w($4));
1226                         brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1227                 } else {
1228                         brw_set_dest(p, brw_last_inst,
1229                                      vec1(retype(brw_null_reg(),
1230                                      BRW_REGISTER_TYPE_D)));
1231                         brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1232                         brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1233                 }
1234
1235                 if (!p->single_program_flow && p->devinfo->gen < 6)
1236                         brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1237                                                     BRW_THREAD_SWITCH);
1238
1239                 brw_pop_insn_state(p);
1240         }
1241         ;
1242
1243 /* break instruction */
1244 breakinstruction:
1245         predicate BREAK execsize relativelocation relativelocation instoptions
1246         {
1247                 brw_next_insn(p, $2);
1248                 i965_asm_set_instruction_options(p, $6);
1249                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1250
1251                 if (p->devinfo->gen >= 8) {
1252                         brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1253                                      BRW_REGISTER_TYPE_D));
1254                         brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1255                         brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1256                 } else if (p->devinfo->gen >= 6) {
1257                         brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1258                                      BRW_REGISTER_TYPE_D));
1259                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1260                                      BRW_REGISTER_TYPE_D));
1261                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1262                         brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1263                         brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1264                 } else {
1265                         brw_set_dest(p, brw_last_inst, brw_ip_reg());
1266                         brw_set_src0(p, brw_last_inst, brw_ip_reg());
1267                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1268                         brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1269                                                      $4);
1270                         brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1271                                                     $5);
1272                 }
1273
1274                 brw_pop_insn_state(p);
1275         }
1276         | predicate HALT execsize relativelocation relativelocation instoptions
1277         {
1278                 brw_next_insn(p, $2);
1279                 i965_asm_set_instruction_options(p, $6);
1280                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1281                 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1282                              BRW_REGISTER_TYPE_D));
1283
1284                 if (p->devinfo->gen >= 8) {
1285                         brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1286                         brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1287                 } else {
1288                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1289                                      BRW_REGISTER_TYPE_D));
1290                         brw_set_src1(p, brw_last_inst, brw_imm_d($5));
1291                 }
1292
1293                 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1294                 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1295                 brw_pop_insn_state(p);
1296         }
1297         | predicate CONT execsize relativelocation relativelocation instoptions
1298         {
1299                 brw_next_insn(p, $2);
1300                 i965_asm_set_instruction_options(p, $6);
1301                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1302                 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1303
1304                 if (p->devinfo->gen >= 8) {
1305                         brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1306                         brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1307                         brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1308                 } else {
1309                         brw_set_src0(p, brw_last_inst, brw_ip_reg());
1310                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1311                         if (p->devinfo->gen >= 6) {
1312                                 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1313                                 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1314                         } else {
1315                                 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1316                                                              $4);
1317                                 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1318                                                             $5);
1319                         }
1320                 }
1321
1322                 brw_pop_insn_state(p);
1323         }
1324         ;
1325
1326 /* loop instruction */
1327 loopinstruction:
1328         predicate WHILE execsize relativelocation instoptions
1329         {
1330                 brw_next_insn(p, $2);
1331                 i965_asm_set_instruction_options(p, $5);
1332                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1333
1334                 if (p->devinfo->gen >= 6) {
1335                         if (p->devinfo->gen >= 8) {
1336                                 brw_set_dest(p, brw_last_inst,
1337                                              retype(brw_null_reg(),
1338                                              BRW_REGISTER_TYPE_D));
1339                                 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1340                         } else if (p->devinfo->gen == 7) {
1341                                 brw_set_dest(p, brw_last_inst,
1342                                              retype(brw_null_reg(),
1343                                              BRW_REGISTER_TYPE_D));
1344                                 brw_set_src0(p, brw_last_inst,
1345                                              retype(brw_null_reg(),
1346                                              BRW_REGISTER_TYPE_D));
1347                                 brw_set_src1(p, brw_last_inst,
1348                                              brw_imm_w(0x0));
1349                                 brw_inst_set_jip(p->devinfo, brw_last_inst,
1350                                                  $4);
1351                         } else {
1352                                 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1353                                 brw_inst_set_gen6_jump_count(p->devinfo,
1354                                                              brw_last_inst,
1355                                                              $4);
1356                                 brw_set_src0(p, brw_last_inst,
1357                                              retype(brw_null_reg(),
1358                                              BRW_REGISTER_TYPE_D));
1359                                 brw_set_src1(p, brw_last_inst,
1360                                              retype(brw_null_reg(),
1361                                              BRW_REGISTER_TYPE_D));
1362                         }
1363                 } else {
1364                         brw_set_dest(p, brw_last_inst, brw_ip_reg());
1365                         brw_set_src0(p, brw_last_inst, brw_ip_reg());
1366                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1367                         brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1368                                                      $4);
1369                         brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1370                                                     0);
1371                 }
1372                 brw_pop_insn_state(p);
1373         }
1374         | DO execsize instoptions
1375         {
1376                 brw_next_insn(p, $1);
1377                 if (p->devinfo->gen < 6) {
1378                         brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1379                         i965_asm_set_instruction_options(p, $3);
1380                         brw_set_dest(p, brw_last_inst, brw_null_reg());
1381                         brw_set_src0(p, brw_last_inst, brw_null_reg());
1382                         brw_set_src1(p, brw_last_inst, brw_null_reg());
1383
1384                         brw_inst_set_qtr_control(p->devinfo, brw_last_inst, BRW_COMPRESSION_NONE);
1385                 }
1386         }
1387         ;
1388
1389 /* Relative location */
1390 relativelocation2:
1391         immreg
1392         | reg32
1393         ;
1394
1395 simple_int:
1396         INTEGER                 { $$ = $1; }
1397         | MINUS INTEGER         { $$ = -$2; }
1398         | LONG                  { $$ = $1; }
1399         | MINUS LONG            { $$ = -$2; }
1400         ;
1401
1402 rellocation:
1403         relativelocation
1404         | %empty { $$ = 0; }
1405         ;
1406
1407 relativelocation:
1408         simple_int
1409         {
1410                 $$ = $1;
1411         }
1412         ;
1413
1414 /* Destination register */
1415 dst:
1416         dstoperand
1417         | dstoperandex
1418         ;
1419
1420 dstoperand:
1421         dstreg dstregion writemask dsttype
1422         {
1423                 $$ = $1;
1424
1425                 if ($2 == -1) {
1426                         $$.hstride = BRW_HORIZONTAL_STRIDE_1;
1427                         $$.vstride = BRW_VERTICAL_STRIDE_1;
1428                         $$.width = BRW_WIDTH_1;
1429                 } else {
1430                         $$.hstride = $2;
1431                 }
1432                 $$.type = $4.type;
1433                 $$.writemask = $3.writemask;
1434                 $$.swizzle = BRW_SWIZZLE_NOOP;
1435                 $$.subnr = $$.subnr * brw_reg_type_to_size($4.type);
1436         }
1437         ;
1438
1439 dstoperandex:
1440         dstoperandex_typed dstregion writemask dsttype
1441         {
1442                 $$ = $1;
1443                 $$.hstride = $2;
1444                 $$.type = $4.type;
1445                 $$.writemask = $3.writemask;
1446                 $$.subnr = $$.subnr * brw_reg_type_to_size($4.type);
1447         }
1448         /* BSpec says "When the conditional modifier is present, updates
1449          * to the selected flag register also occur. In this case, the
1450          * register region fields of the ‘null’ operand are valid."
1451          */
1452         | nullreg dstregion writemask dsttype
1453         {
1454                 $$ = $1;
1455                 if ($2 == -1) {
1456                         $$.hstride = BRW_HORIZONTAL_STRIDE_1;
1457                         $$.vstride = BRW_VERTICAL_STRIDE_1;
1458                         $$.width = BRW_WIDTH_1;
1459                 } else {
1460                         $$.hstride = $2;
1461                 }
1462                 $$.writemask = $3.writemask;
1463                 $$.type = $4.type;
1464         }
1465         | threadcontrolreg
1466         {
1467                 $$ = $1;
1468                 $$.hstride = 1;
1469                 $$.type = BRW_REGISTER_TYPE_UW;
1470         }
1471         ;
1472
1473 dstoperandex_typed:
1474         accreg
1475         | addrreg
1476         | channelenablereg
1477         | controlreg
1478         | flagreg
1479         | ipreg
1480         | maskreg
1481         | performancereg
1482         | statereg
1483         ;
1484
1485 dstreg:
1486         directgenreg
1487         {
1488                 $$ = $1;
1489                 $$.address_mode = BRW_ADDRESS_DIRECT;
1490         }
1491         | indirectgenreg
1492         {
1493                 $$ = $1;
1494                 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1495         }
1496         | directmsgreg
1497         {
1498                 $$ = $1;
1499                 $$.address_mode = BRW_ADDRESS_DIRECT;
1500         }
1501         | indirectmsgreg
1502         {
1503                 $$ = $1;
1504                 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1505         }
1506         ;
1507
1508 /* Source register */
1509 srcaccimm:
1510         srcacc
1511         | immreg
1512         ;
1513
1514 immreg:
1515         immval srcimmtype
1516         {
1517                 uint32_t u32;
1518                 uint64_t u64;
1519                 switch ($2.type) {
1520                 case BRW_REGISTER_TYPE_UD:
1521                         u32 = $1;
1522                         $$ = brw_imm_ud(u32);
1523                         break;
1524                 case BRW_REGISTER_TYPE_D:
1525                         $$ = brw_imm_d($1);
1526                         break;
1527                 case BRW_REGISTER_TYPE_UW:
1528                         u32 = $1 | ($1 << 16);
1529                         $$ = brw_imm_uw(u32);
1530                         break;
1531                 case BRW_REGISTER_TYPE_W:
1532                         u32 = $1;
1533                         $$ = brw_imm_w(u32);
1534                         break;
1535                 case BRW_REGISTER_TYPE_F:
1536                         $$ = brw_imm_reg(BRW_REGISTER_TYPE_F);
1537                         $$.u64 = $1;
1538                         $$.ud = $1;
1539                         break;
1540                 case BRW_REGISTER_TYPE_V:
1541                         $$ = brw_imm_v($1);
1542                         break;
1543                 case BRW_REGISTER_TYPE_UV:
1544                         $$ = brw_imm_uv($1);
1545                         break;
1546                 case BRW_REGISTER_TYPE_VF:
1547                         $$ = brw_imm_reg(BRW_REGISTER_TYPE_VF);
1548                         $$.d = $1;
1549                         break;
1550                 case BRW_REGISTER_TYPE_Q:
1551                         u64 = $1;
1552                         $$ = brw_imm_q(u64);
1553                         break;
1554                 case BRW_REGISTER_TYPE_UQ:
1555                         u64 = $1;
1556                         $$ = brw_imm_uq(u64);
1557                         break;
1558                 case BRW_REGISTER_TYPE_DF:
1559                         $$ = brw_imm_reg(BRW_REGISTER_TYPE_DF);
1560                         $$.d64 = $1;
1561                         break;
1562                 default:
1563                         error(&@2, "Unknown immediate type %s\n",
1564                               brw_reg_type_to_letters($2.type));
1565                 }
1566         }
1567         ;
1568
1569 reg32:
1570         directgenreg region srctype
1571         {
1572                 $$ = set_direct_src_operand(&$1, $3.type);
1573                 $$ = stride($$, $2.vstride, $2.width, $2.hstride);
1574         }
1575         ;
1576
1577 payload:
1578         directsrcoperand
1579         ;
1580
1581 src:
1582         directsrcoperand
1583         | indirectsrcoperand
1584         ;
1585
1586 srcacc:
1587         directsrcaccoperand
1588         | indirectsrcoperand
1589         ;
1590
1591 srcimm:
1592         directsrcoperand
1593         | indirectsrcoperand
1594         | immreg
1595         ;
1596
1597 directsrcaccoperand:
1598         directsrcoperand
1599         | accreg region srctype
1600         {
1601                 $$ = set_direct_src_operand(&$1, $3.type);
1602                 $$.vstride = $2.vstride;
1603                 $$.width = $2.width;
1604                 $$.hstride = $2.hstride;
1605         }
1606         ;
1607
1608 srcarcoperandex:
1609         srcarcoperandex_typed region srctype
1610         {
1611                 $$ = brw_reg($1.file,
1612                              $1.nr,
1613                              $1.subnr,
1614                              0,
1615                              0,
1616                              $3.type,
1617                              $2.vstride,
1618                              $2.width,
1619                              $2.hstride,
1620                              BRW_SWIZZLE_NOOP,
1621                              WRITEMASK_XYZW);
1622         }
1623         | nullreg region srctype
1624         {
1625                 $$ = set_direct_src_operand(&$1, $3.type);
1626                 $$.vstride = $2.vstride;
1627                 $$.width = $2.width;
1628                 $$.hstride = $2.hstride;
1629         }
1630         | threadcontrolreg
1631         {
1632                 $$ = set_direct_src_operand(&$1, BRW_REGISTER_TYPE_UW);
1633         }
1634         ;
1635
1636 srcarcoperandex_typed:
1637         channelenablereg
1638         | controlreg
1639         | flagreg
1640         | ipreg
1641         | maskreg
1642         | statereg
1643         ;
1644
1645 indirectsrcoperand:
1646         negate abs indirectgenreg indirectregion swizzle srctype
1647         {
1648                 $$ = brw_reg($3.file,
1649                              0,
1650                              $3.subnr,
1651                              $1,  // negate
1652                              $2,  // abs
1653                              $6.type,
1654                              $4.vstride,
1655                              $4.width,
1656                              $4.hstride,
1657                              $5.swizzle,
1658                              WRITEMASK_X);
1659
1660                 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1661                 // brw_reg set indirect_offset to 0 so set it to valid value
1662                 $$.indirect_offset = $3.indirect_offset;
1663         }
1664         ;
1665
1666 directgenreg_list:
1667         directgenreg
1668         | directmsgreg
1669         | notifyreg
1670         | addrreg
1671         | performancereg
1672         ;
1673
1674 directsrcoperand:
1675         negate abs directgenreg_list region swizzle srctype
1676         {
1677                 $$ = brw_reg($3.file,
1678                              $3.nr,
1679                              $3.subnr,
1680                              $1,
1681                              $2,
1682                              $6.type,
1683                              $4.vstride,
1684                              $4.width,
1685                              $4.hstride,
1686                              $5.swizzle,
1687                              WRITEMASK_X);
1688         }
1689         | srcarcoperandex
1690         ;
1691
1692 /* Address register */
1693 addrparam:
1694         addrreg exp
1695         {
1696                 memset(&$$, '\0', sizeof($$));
1697                 $$.subnr = $1.subnr;
1698                 $$.indirect_offset = $2;
1699         }
1700         | addrreg
1701         ;
1702
1703 /* Register files and register numbers */
1704 exp:
1705         INTEGER         { $$ = $1; }
1706         | LONG          { $$ = $1; }
1707         ;
1708
1709 subregnum:
1710         DOT exp                         { $$ = $2; }
1711         | %empty %prec SUBREGNUM        { $$ = 0; }
1712         ;
1713
1714 directgenreg:
1715         GENREG subregnum
1716         {
1717                 memset(&$$, '\0', sizeof($$));
1718                 $$.file = BRW_GENERAL_REGISTER_FILE;
1719                 $$.nr = $1;
1720                 $$.subnr = $2;
1721         }
1722         ;
1723
1724 indirectgenreg:
1725         GENREGFILE LSQUARE addrparam RSQUARE
1726         {
1727                 memset(&$$, '\0', sizeof($$));
1728                 $$.file = BRW_GENERAL_REGISTER_FILE;
1729                 $$.subnr = $3.subnr;
1730                 $$.indirect_offset = $3.indirect_offset;
1731         }
1732         ;
1733
1734 directmsgreg:
1735         MSGREG subregnum
1736         {
1737                 $$ = brw_message_reg($1);
1738                 $$.subnr = $2;
1739         }
1740         ;
1741
1742 indirectmsgreg:
1743         MSGREGFILE LSQUARE addrparam RSQUARE
1744         {
1745                 memset(&$$, '\0', sizeof($$));
1746                 $$.file = BRW_MESSAGE_REGISTER_FILE;
1747                 $$.subnr = $3.subnr;
1748                 $$.indirect_offset = $3.indirect_offset;
1749         }
1750         ;
1751
1752 addrreg:
1753         ADDRREG subregnum
1754         {
1755                 int subnr = (p->devinfo->gen >= 8) ? 16 : 8;
1756
1757                 if ($2 > subnr)
1758                         error(&@2, "Address sub register number %d"
1759                                    "out of range\n", $2);
1760
1761                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1762                 $$.nr = BRW_ARF_ADDRESS;
1763                 $$.subnr = $2;
1764         }
1765         ;
1766
1767 accreg:
1768         ACCREG subregnum
1769         {
1770                 int nr_reg;
1771                 if (p->devinfo->gen < 8)
1772                         nr_reg = 2;
1773                 else
1774                         nr_reg = 10;
1775
1776                 if ($1 > nr_reg)
1777                         error(&@1, "Accumulator register number %d"
1778                                    " out of range\n", $1);
1779
1780                 memset(&$$, '\0', sizeof($$));
1781                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1782                 $$.nr = BRW_ARF_ACCUMULATOR;
1783                 $$.subnr = $2;
1784         }
1785         ;
1786
1787 flagreg:
1788         FLAGREG subregnum
1789         {
1790                 // SNB = 1 flag reg and IVB+ = 2 flag reg
1791                 int nr_reg = (p->devinfo->gen >= 7) ? 2 : 1;
1792                 int subnr = nr_reg;
1793
1794                 if ($1 > nr_reg)
1795                         error(&@1, "Flag register number %d"
1796                                    " out of range \n", $1);
1797                 if ($2 > subnr)
1798                         error(&@2, "Flag subregister number %d"
1799                                    " out of range\n", $2);
1800
1801                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1802                 $$.nr = BRW_ARF_FLAG | $1;
1803                 $$.subnr = $2;
1804         }
1805         ;
1806
1807 maskreg:
1808         MASKREG subregnum
1809         {
1810                 if ($1 > 0)
1811                         error(&@1, "Mask register number %d"
1812                                    " out of range\n", $1);
1813
1814                 $$ = brw_mask_reg($2);
1815         }
1816         ;
1817
1818 notifyreg:
1819         NOTIFYREG subregnum
1820         {
1821                 if ($1 > 0)
1822                         error(&@1, "Notification register number %d"
1823                                    " out of range\n", $1);
1824
1825                 int subnr = (p->devinfo->gen >= 11) ? 2 : 3;
1826                 if ($2 > subnr)
1827                         error(&@2, "Notification sub register number %d"
1828                                    " out of range\n", $2);
1829
1830                 $$ = brw_notification_reg();
1831                 $$.subnr = $2;
1832         }
1833         ;
1834
1835 statereg:
1836         STATEREG subregnum
1837         {
1838                 if ($1 > 2)
1839                         error(&@1, "State register number %d"
1840                                    " out of range\n", $1);
1841
1842                 if ($2 > 4)
1843                         error(&@2, "State sub register number %d"
1844                                    " out of range\n", $2);
1845
1846                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1847                 $$.nr = BRW_ARF_STATE;
1848                 $$.subnr = $2;
1849         }
1850         ;
1851
1852 controlreg:
1853         CONTROLREG subregnum
1854         {
1855                 if ($2 > 3)
1856                         error(&@2, "control sub register number %d"
1857                                    " out of range\n", $2);
1858
1859                 $$ = brw_cr0_reg($2);
1860         }
1861         ;
1862
1863 ipreg:
1864         IPREG           { $$ = brw_ip_reg(); }
1865         ;
1866
1867 nullreg:
1868         NULL_TOKEN      { $$ = brw_null_reg(); }
1869         ;
1870
1871 threadcontrolreg:
1872         THREADREG subregnum
1873         {
1874                 if ($1 > 0)
1875                         error(&@1, "Thread control register number %d"
1876                                    " out of range\n", $1);
1877
1878                 if ($2 > 7)
1879                         error(&@2, "Thread control sub register number %d"
1880                                    " out of range\n", $2);
1881
1882                 $$ = brw_tdr_reg();
1883                 $$.subnr = $2;
1884         }
1885         ;
1886
1887 performancereg:
1888         PERFORMANCEREG subregnum
1889         {
1890                 int subnr;
1891                 if (p->devinfo->gen >= 10)
1892                         subnr = 5;
1893                 else if (p->devinfo->gen <= 8)
1894                         subnr = 3;
1895                 else
1896                         subnr = 4;
1897
1898                 if ($2 > subnr)
1899                         error(&@2, "Performance sub register number %d"
1900                                    " out of range\n", $2);
1901
1902                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1903                 $$.nr = BRW_ARF_TIMESTAMP;
1904         }
1905         ;
1906
1907 channelenablereg:
1908         CHANNELENABLEREG subregnum
1909         {
1910                 if ($1 > 0)
1911                         error(&@1, "Channel enable register number %d"
1912                                    " out of range\n", $1);
1913
1914                 $$ = brw_mask_reg($2);
1915         }
1916         ;
1917
1918 /* Immediate values */
1919 immval:
1920         exp2
1921         {
1922                 $$ = $1;
1923         }
1924         | LSQUARE exp2 COMMA exp2 COMMA exp2 COMMA exp2 RSQUARE
1925         {
1926                 $$ = ($2 << 0) | ($4 << 8) | ($6 << 16) | ($8 << 24);
1927         }
1928         ;
1929
1930 /* Regions */
1931 dstregion:
1932         %empty  { $$ = -1; }
1933         | LANGLE exp RANGLE
1934         {
1935                 if ($2 != 0 && ($2 > 4 || !isPowerofTwo($2)))
1936                         error(&@2, "Invalid Horizontal stride %d\n", $2);
1937
1938                 $$ = ffs($2);
1939         }
1940         ;
1941
1942 indirectregion:
1943         region
1944         | region_wh
1945         ;
1946
1947 region:
1948         %empty
1949         {
1950                 $$ = stride($$, BRW_VERTICAL_STRIDE_1, BRW_WIDTH_2, BRW_HORIZONTAL_STRIDE_1);
1951         }
1952         | LANGLE exp RANGLE
1953         {
1954                 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1955                         error(&@2, "Invalid VertStride %d\n", $2);
1956
1957                 $$ = stride($$, $2, BRW_WIDTH_1, 0);
1958         }
1959         | LANGLE exp COMMA exp COMMA exp RANGLE
1960         {
1961
1962                 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1963                         error(&@2, "Invalid VertStride %d\n", $2);
1964
1965                 if ($4 > 16 || !isPowerofTwo($4))
1966                         error(&@4, "Invalid width %d\n", $4);
1967
1968                 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1969                         error(&@6, "Invalid Horizontal stride in"
1970                                    "  region_wh %d\n", $6);
1971
1972                 $$ = stride($$, $2, $4, $6);
1973         }
1974         | LANGLE exp SEMICOLON exp COMMA exp RANGLE
1975         {
1976                 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1977                         error(&@2, "Invalid VertStride %d\n", $2);
1978
1979                 if ($4 > 16 || !isPowerofTwo($4))
1980                         error(&@4, "Invalid width %d\n", $4);
1981
1982                 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1983                         error(&@6, "Invalid Horizontal stride in"
1984                                    " region_wh %d\n", $6);
1985
1986                 $$ = stride($$, $2, $4, $6);
1987         }
1988         | LANGLE VxH COMMA exp COMMA exp RANGLE
1989         {
1990                 if ($4 > 16 || !isPowerofTwo($4))
1991                         error(&@4, "Invalid width %d\n", $4);
1992
1993                 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1994                         error(&@6, "Invalid Horizontal stride in"
1995                                    " region_wh %d\n", $6);
1996
1997                 $$ = brw_VxH_indirect(0, 0);
1998         }
1999         ;
2000
2001 region_wh:
2002         LANGLE exp COMMA exp RANGLE
2003         {
2004                 if ($2 > 16 || !isPowerofTwo($2))
2005                         error(&@2, "Invalid width %d\n", $2);
2006
2007                 if ($4 != 0 && ($4 > 4 || !isPowerofTwo($4)))
2008                         error(&@4, "Invalid Horizontal stride in"
2009                                    " region_wh %d\n", $4);
2010
2011                 $$ = stride($$, BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL, $2, $4);
2012         }
2013         ;
2014
2015 srctype:
2016         %empty          { $$ = retype($$, BRW_REGISTER_TYPE_F); }
2017         | TYPE_F        { $$ = retype($$, BRW_REGISTER_TYPE_F); }
2018         | TYPE_UD       { $$ = retype($$, BRW_REGISTER_TYPE_UD); }
2019         | TYPE_D        { $$ = retype($$, BRW_REGISTER_TYPE_D); }
2020         | TYPE_UW       { $$ = retype($$, BRW_REGISTER_TYPE_UW); }
2021         | TYPE_W        { $$ = retype($$, BRW_REGISTER_TYPE_W); }
2022         | TYPE_UB       { $$ = retype($$, BRW_REGISTER_TYPE_UB); }
2023         | TYPE_B        { $$ = retype($$, BRW_REGISTER_TYPE_B); }
2024         | TYPE_DF       { $$ = retype($$, BRW_REGISTER_TYPE_DF); }
2025         | TYPE_UQ       { $$ = retype($$, BRW_REGISTER_TYPE_UQ); }
2026         | TYPE_Q        { $$ = retype($$, BRW_REGISTER_TYPE_Q); }
2027         | TYPE_HF       { $$ = retype($$, BRW_REGISTER_TYPE_HF); }
2028         | TYPE_NF       { $$ = retype($$, BRW_REGISTER_TYPE_NF); }
2029         ;
2030
2031 srcimmtype:
2032         srctype         { $$ = $1; }
2033         | TYPE_V        { $$ = retype($$, BRW_REGISTER_TYPE_V); }
2034         | TYPE_VF       { $$ = retype($$, BRW_REGISTER_TYPE_VF); }
2035         | TYPE_UV       { $$ = retype($$, BRW_REGISTER_TYPE_UV); }
2036         ;
2037
2038 dsttype:
2039         srctype         { $$ = $1; }
2040         ;
2041
2042 writemask:
2043         %empty
2044         {
2045                 $$= brw_set_writemask($$, WRITEMASK_XYZW);
2046         }
2047         | DOT writemask_x writemask_y writemask_z writemask_w
2048         {
2049                 $$ = brw_set_writemask($$, $2 | $3 | $4 | $5);
2050         }
2051         ;
2052
2053 writemask_x:
2054         %empty  { $$ = 0; }
2055         | X     { $$ = 1 << BRW_CHANNEL_X; }
2056         ;
2057
2058 writemask_y:
2059         %empty  { $$ = 0; }
2060         | Y     { $$ = 1 << BRW_CHANNEL_Y; }
2061         ;
2062
2063 writemask_z:
2064         %empty  { $$ = 0; }
2065         | Z     { $$ = 1 << BRW_CHANNEL_Z; }
2066         ;
2067
2068 writemask_w:
2069         %empty  { $$ = 0; }
2070         | W     { $$ = 1 << BRW_CHANNEL_W; }
2071         ;
2072
2073 swizzle:
2074         %empty
2075         {
2076                 $$.swizzle = BRW_SWIZZLE_NOOP;
2077         }
2078         | DOT chansel
2079         {
2080                 $$.swizzle = BRW_SWIZZLE4($2, $2, $2, $2);
2081         }
2082         | DOT chansel chansel chansel chansel
2083         {
2084                 $$.swizzle = BRW_SWIZZLE4($2, $3, $4, $5);
2085         }
2086         ;
2087
2088 chansel:
2089         X
2090         | Y
2091         | Z
2092         | W
2093         ;
2094
2095 /* Instruction prediction and modifiers */
2096 predicate:
2097         %empty
2098         {
2099                 brw_push_insn_state(p);
2100                 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
2101                 brw_set_default_flag_reg(p, 0, 0);
2102                 brw_set_default_predicate_inverse(p, false);
2103         }
2104         | LPAREN predstate flagreg predctrl RPAREN
2105         {
2106                 brw_push_insn_state(p);
2107                 brw_set_default_predicate_inverse(p, $2);
2108                 brw_set_default_flag_reg(p, $3.nr, $3.subnr);
2109                 brw_set_default_predicate_control(p, $4);
2110         }
2111         ;
2112
2113 predstate:
2114         %empty          { $$ = 0; }
2115         | PLUS          { $$ = 0; }
2116         | MINUS         { $$ = 1; }
2117         ;
2118
2119 predctrl:
2120         %empty          { $$ = BRW_PREDICATE_NORMAL; }
2121         | DOT X         { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_X; }
2122         | DOT Y         { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Y; }
2123         | DOT Z         { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Z; }
2124         | DOT W         { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_W; }
2125         | ANYV
2126         | ALLV
2127         | ANY2H
2128         | ALL2H
2129         | ANY4H
2130         | ALL4H
2131         | ANY8H
2132         | ALL8H
2133         | ANY16H
2134         | ALL16H
2135         | ANY32H
2136         | ALL32H
2137         ;
2138
2139 /* Source Modification */
2140 negate:
2141         %empty          { $$ = 0; }
2142         | MINUS         { $$ = 1; }
2143         ;
2144
2145 abs:
2146         %empty  { $$ = 0; }
2147         | ABS   { $$ = 1; }
2148         ;
2149
2150 /* Flag (Conditional) Modifier */
2151 cond_mod:
2152         condModifiers
2153         {
2154                 $$.cond_modifier = $1;
2155                 $$.flag_reg_nr = 0;
2156                 $$.flag_subreg_nr = 0;
2157         }
2158         | condModifiers DOT flagreg
2159         {
2160                 $$.cond_modifier = $1;
2161                 $$.flag_reg_nr = $3.nr;
2162                 $$.flag_subreg_nr = $3.subnr;
2163         }
2164         ;
2165
2166 condModifiers:
2167         %empty  { $$ = BRW_CONDITIONAL_NONE; }
2168         | ZERO
2169         | EQUAL
2170         | NOT_ZERO
2171         | NOT_EQUAL
2172         | GREATER
2173         | GREATER_EQUAL
2174         | LESS
2175         | LESS_EQUAL
2176         | OVERFLOW
2177         | ROUND_INCREMENT
2178         | UNORDERED
2179         ;
2180
2181 saturate:
2182         %empty          { $$ = BRW_INSTRUCTION_NORMAL; }
2183         | SATURATE      { $$ = BRW_INSTRUCTION_SATURATE; }
2184         ;
2185
2186 /* Execution size */
2187 execsize:
2188         %empty %prec EMPTYEXECSIZE
2189         {
2190                 $$ = 0;
2191         }
2192         | LPAREN exp2 RPAREN
2193         {
2194                 if ($2 > 32 || !isPowerofTwo($2))
2195                         error(&@2, "Invalid execution size %d\n", $2);
2196
2197                 $$ = cvt($2) - 1;
2198         }
2199         ;
2200
2201 /* Instruction options */
2202 instoptions:
2203         %empty
2204         {
2205                 memset(&$$, 0, sizeof($$));
2206         }
2207         | LCURLY instoption_list RCURLY
2208         {
2209                 memset(&$$, 0, sizeof($$));
2210                 $$ = $2;
2211         }
2212         ;
2213
2214 instoption_list:
2215         instoption_list COMMA instoption
2216         {
2217                 memset(&$$, 0, sizeof($$));
2218                 $$ = $1;
2219                 add_instruction_option(&$$, $3);
2220         }
2221         | instoption_list instoption
2222         {
2223                 memset(&$$, 0, sizeof($$));
2224                 $$ = $1;
2225                 add_instruction_option(&$$, $2);
2226         }
2227         | %empty
2228         {
2229                 memset(&$$, 0, sizeof($$));
2230         }
2231         ;
2232
2233 instoption:
2234         ALIGN1          { $$ = ALIGN1;}
2235         | ALIGN16       { $$ = ALIGN16; }
2236         | ACCWREN       { $$ = ACCWREN; }
2237         | SECHALF       { $$ = SECHALF; }
2238         | COMPR         { $$ = COMPR; }
2239         | COMPR4        { $$ = COMPR4; }
2240         | BREAKPOINT    { $$ = BREAKPOINT; }
2241         | NODDCLR       { $$ = NODDCLR; }
2242         | NODDCHK       { $$ = NODDCHK; }
2243         | MASK_DISABLE  { $$ = MASK_DISABLE; }
2244         | EOT           { $$ = EOT; }
2245         | SWITCH        { $$ = SWITCH; }
2246         | ATOMIC        { $$ = ATOMIC; }
2247         | CMPTCTRL      { $$ = CMPTCTRL; }
2248         | WECTRL        { $$ = WECTRL; }
2249         | QTR_2Q        { $$ = QTR_2Q; }
2250         | QTR_3Q        { $$ = QTR_3Q; }
2251         | QTR_4Q        { $$ = QTR_4Q; }
2252         | QTR_2H        { $$ = QTR_2H; }
2253         | QTR_2N        { $$ = QTR_2N; }
2254         | QTR_3N        { $$ = QTR_3N; }
2255         | QTR_4N        { $$ = QTR_4N; }
2256         | QTR_5N        { $$ = QTR_5N; }
2257         | QTR_6N        { $$ = QTR_6N; }
2258         | QTR_7N        { $$ = QTR_7N; }
2259         | QTR_8N        { $$ = QTR_8N; }
2260         ;
2261
2262 %%
2263
2264 extern int yylineno;
2265
2266 void
2267 yyerror(char *msg)
2268 {
2269         fprintf(stderr, "%s: %d: %s at \"%s\"\n",
2270                 input_filename, yylineno, msg, lex_text());
2271         ++errors;
2272 }