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intel/gen11+: Enable Hardware filtering of Semi-Pipelined State in WM
[mesa.git] / src / intel / vulkan / genX_state.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "anv_private.h"
31
32 #include "common/gen_sample_positions.h"
33 #include "genxml/gen_macros.h"
34 #include "genxml/genX_pack.h"
35
36 #include "vk_util.h"
37
38 #if GEN_GEN == 10
39 /**
40 * From Gen10 Workarounds page in h/w specs:
41 * WaSampleOffsetIZ:
42 * "Prior to the 3DSTATE_SAMPLE_PATTERN driver must ensure there are no
43 * markers in the pipeline by programming a PIPE_CONTROL with stall."
44 */
45 static void
46 gen10_emit_wa_cs_stall_flush(struct anv_batch *batch)
47 {
48
49 anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) {
50 pc.CommandStreamerStallEnable = true;
51 pc.StallAtPixelScoreboard = true;
52 }
53 }
54
55 /**
56 * From Gen10 Workarounds page in h/w specs:
57 * WaSampleOffsetIZ:_cs_stall_flush
58 * "When 3DSTATE_SAMPLE_PATTERN is programmed, driver must then issue an
59 * MI_LOAD_REGISTER_IMM command to an offset between 0x7000 and 0x7FFF(SVL)
60 * after the command to ensure the state has been delivered prior to any
61 * command causing a marker in the pipeline."
62 */
63 static void
64 gen10_emit_wa_lri_to_cache_mode_zero(struct anv_batch *batch)
65 {
66 /* Before changing the value of CACHE_MODE_0 register, GFX pipeline must
67 * be idle; i.e., full flush is required.
68 */
69 anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) {
70 pc.DepthCacheFlushEnable = true;
71 pc.DCFlushEnable = true;
72 pc.RenderTargetCacheFlushEnable = true;
73 pc.InstructionCacheInvalidateEnable = true;
74 pc.StateCacheInvalidationEnable = true;
75 pc.TextureCacheInvalidationEnable = true;
76 pc.VFCacheInvalidationEnable = true;
77 pc.ConstantCacheInvalidationEnable =true;
78 }
79
80 /* Write to CACHE_MODE_0 (0x7000) */
81 uint32_t cache_mode_0 = 0;
82 anv_pack_struct(&cache_mode_0, GENX(CACHE_MODE_0));
83
84 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
85 lri.RegisterOffset = GENX(CACHE_MODE_0_num);
86 lri.DataDWord = cache_mode_0;
87 }
88 }
89 #endif
90
91 static void
92 genX(emit_slice_hashing_state)(struct anv_device *device,
93 struct anv_batch *batch)
94 {
95 device->slice_hash = (struct anv_state) { 0 };
96
97 #if GEN_GEN == 11
98 const unsigned *ppipe_subslices = device->info.ppipe_subslices;
99 int subslices_delta = ppipe_subslices[0] - ppipe_subslices[1];
100 if (subslices_delta == 0)
101 return;
102
103 unsigned size = GENX(SLICE_HASH_TABLE_length) * 4;
104 device->slice_hash =
105 anv_state_pool_alloc(&device->dynamic_state_pool, size, 64);
106
107 struct GENX(SLICE_HASH_TABLE) table0 = {
108 .Entry = {
109 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
110 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
111 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
112 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
113 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
114 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
115 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
116 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
117 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
118 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
119 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
120 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
121 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
122 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
123 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
124 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 }
125 }
126 };
127
128 struct GENX(SLICE_HASH_TABLE) table1 = {
129 .Entry = {
130 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
131 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
132 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
133 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
134 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
135 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
136 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
137 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
138 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
139 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
140 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
141 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
142 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
143 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
144 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
145 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 }
146 }
147 };
148
149 const struct GENX(SLICE_HASH_TABLE) *table =
150 subslices_delta < 0 ? &table0 : &table1;
151 GENX(SLICE_HASH_TABLE_pack)(NULL, device->slice_hash.map, table);
152
153 anv_batch_emit(batch, GENX(3DSTATE_SLICE_TABLE_STATE_POINTERS), ptr) {
154 ptr.SliceHashStatePointerValid = true;
155 ptr.SliceHashTableStatePointer = device->slice_hash.offset;
156 }
157
158 anv_batch_emit(batch, GENX(3DSTATE_3D_MODE), mode) {
159 mode.SliceHashingTableEnable = true;
160 }
161 #endif
162 }
163
164 VkResult
165 genX(init_device_state)(struct anv_device *device)
166 {
167 device->default_mocs = GENX(MOCS);
168 #if GEN_GEN >= 8
169 device->external_mocs = GENX(EXTERNAL_MOCS);
170 #else
171 device->external_mocs = device->default_mocs;
172 #endif
173
174 struct anv_batch batch;
175
176 uint32_t cmds[64];
177 batch.start = batch.next = cmds;
178 batch.end = (void *) cmds + sizeof(cmds);
179
180 anv_batch_emit(&batch, GENX(PIPELINE_SELECT), ps) {
181 #if GEN_GEN >= 9
182 ps.MaskBits = 3;
183 #endif
184 ps.PipelineSelection = _3D;
185 }
186
187 #if GEN_GEN == 9
188 uint32_t cache_mode_1;
189 anv_pack_struct(&cache_mode_1, GENX(CACHE_MODE_1),
190 .FloatBlendOptimizationEnable = true,
191 .FloatBlendOptimizationEnableMask = true,
192 .PartialResolveDisableInVC = true,
193 .PartialResolveDisableInVCMask = true);
194
195 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
196 lri.RegisterOffset = GENX(CACHE_MODE_1_num);
197 lri.DataDWord = cache_mode_1;
198 }
199 #endif
200
201 anv_batch_emit(&batch, GENX(3DSTATE_AA_LINE_PARAMETERS), aa);
202
203 anv_batch_emit(&batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
204 rect.ClippedDrawingRectangleYMin = 0;
205 rect.ClippedDrawingRectangleXMin = 0;
206 rect.ClippedDrawingRectangleYMax = UINT16_MAX;
207 rect.ClippedDrawingRectangleXMax = UINT16_MAX;
208 rect.DrawingRectangleOriginY = 0;
209 rect.DrawingRectangleOriginX = 0;
210 }
211
212 #if GEN_GEN >= 8
213 anv_batch_emit(&batch, GENX(3DSTATE_WM_CHROMAKEY), ck);
214
215 #if GEN_GEN == 10
216 gen10_emit_wa_cs_stall_flush(&batch);
217 #endif
218
219 /* See the Vulkan 1.0 spec Table 24.1 "Standard sample locations" and
220 * VkPhysicalDeviceFeatures::standardSampleLocations.
221 */
222 anv_batch_emit(&batch, GENX(3DSTATE_SAMPLE_PATTERN), sp) {
223 GEN_SAMPLE_POS_1X(sp._1xSample);
224 GEN_SAMPLE_POS_2X(sp._2xSample);
225 GEN_SAMPLE_POS_4X(sp._4xSample);
226 GEN_SAMPLE_POS_8X(sp._8xSample);
227 #if GEN_GEN >= 9
228 GEN_SAMPLE_POS_16X(sp._16xSample);
229 #endif
230 }
231
232 /* The BDW+ docs describe how to use the 3DSTATE_WM_HZ_OP instruction in the
233 * section titled, "Optimized Depth Buffer Clear and/or Stencil Buffer
234 * Clear." It mentions that the packet overrides GPU state for the clear
235 * operation and needs to be reset to 0s to clear the overrides. Depending
236 * on the kernel, we may not get a context with the state for this packet
237 * zeroed. Do it ourselves just in case. We've observed this to prevent a
238 * number of GPU hangs on ICL.
239 */
240 anv_batch_emit(&batch, GENX(3DSTATE_WM_HZ_OP), hzp);
241 #endif
242
243 #if GEN_GEN == 10
244 gen10_emit_wa_lri_to_cache_mode_zero(&batch);
245 #endif
246
247 #if GEN_GEN == 11
248 /* The default behavior of bit 5 "Headerless Message for Pre-emptable
249 * Contexts" in SAMPLER MODE register is set to 0, which means
250 * headerless sampler messages are not allowed for pre-emptable
251 * contexts. Set the bit 5 to 1 to allow them.
252 */
253 uint32_t sampler_mode;
254 anv_pack_struct(&sampler_mode, GENX(SAMPLER_MODE),
255 .HeaderlessMessageforPreemptableContexts = true,
256 .HeaderlessMessageforPreemptableContextsMask = true);
257
258 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
259 lri.RegisterOffset = GENX(SAMPLER_MODE_num);
260 lri.DataDWord = sampler_mode;
261 }
262
263 /* Bit 1 "Enabled Texel Offset Precision Fix" must be set in
264 * HALF_SLICE_CHICKEN7 register.
265 */
266 uint32_t half_slice_chicken7;
267 anv_pack_struct(&half_slice_chicken7, GENX(HALF_SLICE_CHICKEN7),
268 .EnabledTexelOffsetPrecisionFix = true,
269 .EnabledTexelOffsetPrecisionFixMask = true);
270
271 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
272 lri.RegisterOffset = GENX(HALF_SLICE_CHICKEN7_num);
273 lri.DataDWord = half_slice_chicken7;
274 }
275
276 #endif
277 genX(emit_slice_hashing_state)(device, &batch);
278
279 #if GEN_GEN >= 11
280 /* hardware specification recommends disabling repacking for
281 * the compatibility with decompression mechanism in display controller.
282 */
283 if (device->info.disable_ccs_repack) {
284 uint32_t cache_mode_0;
285 anv_pack_struct(&cache_mode_0,
286 GENX(CACHE_MODE_0),
287 .DisableRepackingforCompression = true,
288 .DisableRepackingforCompressionMask = true);
289
290 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
291 lri.RegisterOffset = GENX(CACHE_MODE_0_num);
292 lri.DataDWord = cache_mode_0;
293 }
294 }
295
296 /* WA_220160979: Enable Hardware filtering of Semi-Pipelined State in WM. */
297 uint32_t common_slice_chicken4;
298 anv_pack_struct(&common_slice_chicken4, GENX(COMMON_SLICE_CHICKEN4),
299 .EnableHardwareFilteringinWM = true,
300 .EnableHardwareFilteringinWMMask = true);
301
302 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
303 lri.RegisterOffset = GENX(COMMON_SLICE_CHICKEN4_num);
304 lri.DataDWord = common_slice_chicken4;
305 }
306 #endif
307
308 /* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so
309 * 3DSTATE_CONSTANT_XS buffer 0 is an absolute address.
310 *
311 * This is only safe on kernels with context isolation support.
312 */
313 if (GEN_GEN >= 8 &&
314 device->instance->physicalDevice.has_context_isolation) {
315 UNUSED uint32_t tmp_reg;
316 #if GEN_GEN >= 9
317 anv_pack_struct(&tmp_reg, GENX(CS_DEBUG_MODE2),
318 .CONSTANT_BUFFERAddressOffsetDisable = true,
319 .CONSTANT_BUFFERAddressOffsetDisableMask = true);
320 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
321 lri.RegisterOffset = GENX(CS_DEBUG_MODE2_num);
322 lri.DataDWord = tmp_reg;
323 }
324 #elif GEN_GEN == 8
325 anv_pack_struct(&tmp_reg, GENX(INSTPM),
326 .CONSTANT_BUFFERAddressOffsetDisable = true,
327 .CONSTANT_BUFFERAddressOffsetDisableMask = true);
328 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
329 lri.RegisterOffset = GENX(INSTPM_num);
330 lri.DataDWord = tmp_reg;
331 }
332 #endif
333 }
334
335 anv_batch_emit(&batch, GENX(MI_BATCH_BUFFER_END), bbe);
336
337 assert(batch.next <= batch.end);
338
339 return anv_device_submit_simple_batch(device, &batch);
340 }
341
342 static uint32_t
343 vk_to_gen_tex_filter(VkFilter filter, bool anisotropyEnable)
344 {
345 switch (filter) {
346 default:
347 assert(!"Invalid filter");
348 case VK_FILTER_NEAREST:
349 return anisotropyEnable ? MAPFILTER_ANISOTROPIC : MAPFILTER_NEAREST;
350 case VK_FILTER_LINEAR:
351 return anisotropyEnable ? MAPFILTER_ANISOTROPIC : MAPFILTER_LINEAR;
352 }
353 }
354
355 static uint32_t
356 vk_to_gen_max_anisotropy(float ratio)
357 {
358 return (anv_clamp_f(ratio, 2, 16) - 2) / 2;
359 }
360
361 static const uint32_t vk_to_gen_mipmap_mode[] = {
362 [VK_SAMPLER_MIPMAP_MODE_NEAREST] = MIPFILTER_NEAREST,
363 [VK_SAMPLER_MIPMAP_MODE_LINEAR] = MIPFILTER_LINEAR
364 };
365
366 static const uint32_t vk_to_gen_tex_address[] = {
367 [VK_SAMPLER_ADDRESS_MODE_REPEAT] = TCM_WRAP,
368 [VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT] = TCM_MIRROR,
369 [VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE] = TCM_CLAMP,
370 [VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE] = TCM_MIRROR_ONCE,
371 [VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER] = TCM_CLAMP_BORDER,
372 };
373
374 /* Vulkan specifies the result of shadow comparisons as:
375 * 1 if ref <op> texel,
376 * 0 otherwise.
377 *
378 * The hardware does:
379 * 0 if texel <op> ref,
380 * 1 otherwise.
381 *
382 * So, these look a bit strange because there's both a negation
383 * and swapping of the arguments involved.
384 */
385 static const uint32_t vk_to_gen_shadow_compare_op[] = {
386 [VK_COMPARE_OP_NEVER] = PREFILTEROPALWAYS,
387 [VK_COMPARE_OP_LESS] = PREFILTEROPLEQUAL,
388 [VK_COMPARE_OP_EQUAL] = PREFILTEROPNOTEQUAL,
389 [VK_COMPARE_OP_LESS_OR_EQUAL] = PREFILTEROPLESS,
390 [VK_COMPARE_OP_GREATER] = PREFILTEROPGEQUAL,
391 [VK_COMPARE_OP_NOT_EQUAL] = PREFILTEROPEQUAL,
392 [VK_COMPARE_OP_GREATER_OR_EQUAL] = PREFILTEROPGREATER,
393 [VK_COMPARE_OP_ALWAYS] = PREFILTEROPNEVER,
394 };
395
396 #if GEN_GEN >= 9
397 static const uint32_t vk_to_gen_sampler_reduction_mode[] = {
398 [VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT] = STD_FILTER,
399 [VK_SAMPLER_REDUCTION_MODE_MIN_EXT] = MINIMUM,
400 [VK_SAMPLER_REDUCTION_MODE_MAX_EXT] = MAXIMUM,
401 };
402 #endif
403
404 VkResult genX(CreateSampler)(
405 VkDevice _device,
406 const VkSamplerCreateInfo* pCreateInfo,
407 const VkAllocationCallbacks* pAllocator,
408 VkSampler* pSampler)
409 {
410 ANV_FROM_HANDLE(anv_device, device, _device);
411 const struct anv_physical_device *pdevice =
412 &device->instance->physicalDevice;
413 struct anv_sampler *sampler;
414
415 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
416
417 sampler = vk_zalloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
418 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
419 if (!sampler)
420 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
421
422 sampler->n_planes = 1;
423
424 uint32_t border_color_stride = GEN_IS_HASWELL ? 512 : 64;
425 uint32_t border_color_offset = device->border_colors.offset +
426 pCreateInfo->borderColor *
427 border_color_stride;
428
429 #if GEN_GEN >= 9
430 unsigned sampler_reduction_mode = STD_FILTER;
431 bool enable_sampler_reduction = false;
432 #endif
433
434 vk_foreach_struct(ext, pCreateInfo->pNext) {
435 switch (ext->sType) {
436 case VK_STRUCTURE_TYPE_SAMPLER_YCBCR_CONVERSION_INFO: {
437 VkSamplerYcbcrConversionInfo *pSamplerConversion =
438 (VkSamplerYcbcrConversionInfo *) ext;
439 ANV_FROM_HANDLE(anv_ycbcr_conversion, conversion,
440 pSamplerConversion->conversion);
441
442 /* Ignore conversion for non-YUV formats. This fulfills a requirement
443 * for clients that want to utilize same code path for images with
444 * external formats (VK_FORMAT_UNDEFINED) and "regular" RGBA images
445 * where format is known.
446 */
447 if (conversion == NULL || !conversion->format->can_ycbcr)
448 break;
449
450 sampler->n_planes = conversion->format->n_planes;
451 sampler->conversion = conversion;
452 break;
453 }
454 #if GEN_GEN >= 9
455 case VK_STRUCTURE_TYPE_SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT: {
456 struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
457 (struct VkSamplerReductionModeCreateInfoEXT *) ext;
458 sampler_reduction_mode =
459 vk_to_gen_sampler_reduction_mode[sampler_reduction->reductionMode];
460 enable_sampler_reduction = true;
461 break;
462 }
463 #endif
464 default:
465 anv_debug_ignored_stype(ext->sType);
466 break;
467 }
468 }
469
470 if (pdevice->has_bindless_samplers) {
471 /* If we have bindless, allocate enough samplers. We allocate 32 bytes
472 * for each sampler instead of 16 bytes because we want all bindless
473 * samplers to be 32-byte aligned so we don't have to use indirect
474 * sampler messages on them.
475 */
476 sampler->bindless_state =
477 anv_state_pool_alloc(&device->dynamic_state_pool,
478 sampler->n_planes * 32, 32);
479 }
480
481 for (unsigned p = 0; p < sampler->n_planes; p++) {
482 const bool plane_has_chroma =
483 sampler->conversion && sampler->conversion->format->planes[p].has_chroma;
484 const VkFilter min_filter =
485 plane_has_chroma ? sampler->conversion->chroma_filter : pCreateInfo->minFilter;
486 const VkFilter mag_filter =
487 plane_has_chroma ? sampler->conversion->chroma_filter : pCreateInfo->magFilter;
488 const bool enable_min_filter_addr_rounding = min_filter != VK_FILTER_NEAREST;
489 const bool enable_mag_filter_addr_rounding = mag_filter != VK_FILTER_NEAREST;
490 /* From Broadwell PRM, SAMPLER_STATE:
491 * "Mip Mode Filter must be set to MIPFILTER_NONE for Planar YUV surfaces."
492 */
493 const uint32_t mip_filter_mode =
494 (sampler->conversion &&
495 isl_format_is_yuv(sampler->conversion->format->planes[0].isl_format)) ?
496 MIPFILTER_NONE : vk_to_gen_mipmap_mode[pCreateInfo->mipmapMode];
497
498 struct GENX(SAMPLER_STATE) sampler_state = {
499 .SamplerDisable = false,
500 .TextureBorderColorMode = DX10OGL,
501
502 #if GEN_GEN >= 8
503 .LODPreClampMode = CLAMP_MODE_OGL,
504 #else
505 .LODPreClampEnable = CLAMP_ENABLE_OGL,
506 #endif
507
508 #if GEN_GEN == 8
509 .BaseMipLevel = 0.0,
510 #endif
511 .MipModeFilter = mip_filter_mode,
512 .MagModeFilter = vk_to_gen_tex_filter(mag_filter, pCreateInfo->anisotropyEnable),
513 .MinModeFilter = vk_to_gen_tex_filter(min_filter, pCreateInfo->anisotropyEnable),
514 .TextureLODBias = anv_clamp_f(pCreateInfo->mipLodBias, -16, 15.996),
515 .AnisotropicAlgorithm = EWAApproximation,
516 .MinLOD = anv_clamp_f(pCreateInfo->minLod, 0, 14),
517 .MaxLOD = anv_clamp_f(pCreateInfo->maxLod, 0, 14),
518 .ChromaKeyEnable = 0,
519 .ChromaKeyIndex = 0,
520 .ChromaKeyMode = 0,
521 .ShadowFunction = vk_to_gen_shadow_compare_op[pCreateInfo->compareOp],
522 .CubeSurfaceControlMode = OVERRIDE,
523
524 .BorderColorPointer = border_color_offset,
525
526 #if GEN_GEN >= 8
527 .LODClampMagnificationMode = MIPNONE,
528 #endif
529
530 .MaximumAnisotropy = vk_to_gen_max_anisotropy(pCreateInfo->maxAnisotropy),
531 .RAddressMinFilterRoundingEnable = enable_min_filter_addr_rounding,
532 .RAddressMagFilterRoundingEnable = enable_mag_filter_addr_rounding,
533 .VAddressMinFilterRoundingEnable = enable_min_filter_addr_rounding,
534 .VAddressMagFilterRoundingEnable = enable_mag_filter_addr_rounding,
535 .UAddressMinFilterRoundingEnable = enable_min_filter_addr_rounding,
536 .UAddressMagFilterRoundingEnable = enable_mag_filter_addr_rounding,
537 .TrilinearFilterQuality = 0,
538 .NonnormalizedCoordinateEnable = pCreateInfo->unnormalizedCoordinates,
539 .TCXAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeU],
540 .TCYAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeV],
541 .TCZAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeW],
542
543 #if GEN_GEN >= 9
544 .ReductionType = sampler_reduction_mode,
545 .ReductionTypeEnable = enable_sampler_reduction,
546 #endif
547 };
548
549 GENX(SAMPLER_STATE_pack)(NULL, sampler->state[p], &sampler_state);
550
551 if (sampler->bindless_state.map) {
552 memcpy(sampler->bindless_state.map + p * 32,
553 sampler->state[p], GENX(SAMPLER_STATE_length) * 4);
554 }
555 }
556
557 *pSampler = anv_sampler_to_handle(sampler);
558
559 return VK_SUCCESS;
560 }