2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "anv_private.h"
32 #include "common/gen_sample_positions.h"
33 #include "genxml/gen_macros.h"
34 #include "genxml/genX_pack.h"
40 * From Gen10 Workarounds page in h/w specs:
42 * "Prior to the 3DSTATE_SAMPLE_PATTERN driver must ensure there are no
43 * markers in the pipeline by programming a PIPE_CONTROL with stall."
46 gen10_emit_wa_cs_stall_flush(struct anv_batch
*batch
)
49 anv_batch_emit(batch
, GENX(PIPE_CONTROL
), pc
) {
50 pc
.CommandStreamerStallEnable
= true;
51 pc
.StallAtPixelScoreboard
= true;
56 * From Gen10 Workarounds page in h/w specs:
57 * WaSampleOffsetIZ:_cs_stall_flush
58 * "When 3DSTATE_SAMPLE_PATTERN is programmed, driver must then issue an
59 * MI_LOAD_REGISTER_IMM command to an offset between 0x7000 and 0x7FFF(SVL)
60 * after the command to ensure the state has been delivered prior to any
61 * command causing a marker in the pipeline."
64 gen10_emit_wa_lri_to_cache_mode_zero(struct anv_batch
*batch
)
66 /* Before changing the value of CACHE_MODE_0 register, GFX pipeline must
67 * be idle; i.e., full flush is required.
69 anv_batch_emit(batch
, GENX(PIPE_CONTROL
), pc
) {
70 pc
.DepthCacheFlushEnable
= true;
71 pc
.DCFlushEnable
= true;
72 pc
.RenderTargetCacheFlushEnable
= true;
73 pc
.InstructionCacheInvalidateEnable
= true;
74 pc
.StateCacheInvalidationEnable
= true;
75 pc
.TextureCacheInvalidationEnable
= true;
76 pc
.VFCacheInvalidationEnable
= true;
77 pc
.ConstantCacheInvalidationEnable
=true;
80 /* Write to CACHE_MODE_0 (0x7000) */
81 uint32_t cache_mode_0
= 0;
82 anv_pack_struct(&cache_mode_0
, GENX(CACHE_MODE_0
));
84 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
85 lri
.RegisterOffset
= GENX(CACHE_MODE_0_num
);
86 lri
.DataDWord
= cache_mode_0
;
92 genX(init_device_state
)(struct anv_device
*device
)
94 device
->default_mocs
= GENX(MOCS
);
96 device
->external_mocs
= GENX(EXTERNAL_MOCS
);
98 device
->external_mocs
= device
->default_mocs
;
101 struct anv_batch batch
;
104 batch
.start
= batch
.next
= cmds
;
105 batch
.end
= (void *) cmds
+ sizeof(cmds
);
107 anv_batch_emit(&batch
, GENX(PIPELINE_SELECT
), ps
) {
111 ps
.PipelineSelection
= _3D
;
115 uint32_t cache_mode_1
;
116 anv_pack_struct(&cache_mode_1
, GENX(CACHE_MODE_1
),
117 .FloatBlendOptimizationEnable
= true,
118 .FloatBlendOptimizationEnableMask
= true,
119 .PartialResolveDisableInVC
= true,
120 .PartialResolveDisableInVCMask
= true);
122 anv_batch_emit(&batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
123 lri
.RegisterOffset
= GENX(CACHE_MODE_1_num
);
124 lri
.DataDWord
= cache_mode_1
;
128 anv_batch_emit(&batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), aa
);
130 anv_batch_emit(&batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
131 rect
.ClippedDrawingRectangleYMin
= 0;
132 rect
.ClippedDrawingRectangleXMin
= 0;
133 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
134 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
135 rect
.DrawingRectangleOriginY
= 0;
136 rect
.DrawingRectangleOriginX
= 0;
140 anv_batch_emit(&batch
, GENX(3DSTATE_WM_CHROMAKEY
), ck
);
143 gen10_emit_wa_cs_stall_flush(&batch
);
146 /* See the Vulkan 1.0 spec Table 24.1 "Standard sample locations" and
147 * VkPhysicalDeviceFeatures::standardSampleLocations.
149 anv_batch_emit(&batch
, GENX(3DSTATE_SAMPLE_PATTERN
), sp
) {
150 GEN_SAMPLE_POS_1X(sp
._1xSample
);
151 GEN_SAMPLE_POS_2X(sp
._2xSample
);
152 GEN_SAMPLE_POS_4X(sp
._4xSample
);
153 GEN_SAMPLE_POS_8X(sp
._8xSample
);
155 GEN_SAMPLE_POS_16X(sp
._16xSample
);
159 /* The BDW+ docs describe how to use the 3DSTATE_WM_HZ_OP instruction in the
160 * section titled, "Optimized Depth Buffer Clear and/or Stencil Buffer
161 * Clear." It mentions that the packet overrides GPU state for the clear
162 * operation and needs to be reset to 0s to clear the overrides. Depending
163 * on the kernel, we may not get a context with the state for this packet
164 * zeroed. Do it ourselves just in case. We've observed this to prevent a
165 * number of GPU hangs on ICL.
167 anv_batch_emit(&batch
, GENX(3DSTATE_WM_HZ_OP
), hzp
);
171 gen10_emit_wa_lri_to_cache_mode_zero(&batch
);
175 /* The default behavior of bit 5 "Headerless Message for Pre-emptable
176 * Contexts" in SAMPLER MODE register is set to 0, which means
177 * headerless sampler messages are not allowed for pre-emptable
178 * contexts. Set the bit 5 to 1 to allow them.
180 uint32_t sampler_mode
;
181 anv_pack_struct(&sampler_mode
, GENX(SAMPLER_MODE
),
182 .HeaderlessMessageforPreemptableContexts
= true,
183 .HeaderlessMessageforPreemptableContextsMask
= true);
185 anv_batch_emit(&batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
186 lri
.RegisterOffset
= GENX(SAMPLER_MODE_num
);
187 lri
.DataDWord
= sampler_mode
;
190 /* Bit 1 "Enabled Texel Offset Precision Fix" must be set in
191 * HALF_SLICE_CHICKEN7 register.
193 uint32_t half_slice_chicken7
;
194 anv_pack_struct(&half_slice_chicken7
, GENX(HALF_SLICE_CHICKEN7
),
195 .EnabledTexelOffsetPrecisionFix
= true,
196 .EnabledTexelOffsetPrecisionFixMask
= true);
198 anv_batch_emit(&batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
199 lri
.RegisterOffset
= GENX(HALF_SLICE_CHICKEN7_num
);
200 lri
.DataDWord
= half_slice_chicken7
;
203 /* WA_2204188704: Pixel Shader Panic dispatch must be disabled.
205 uint32_t common_slice_chicken3
;
206 anv_pack_struct(&common_slice_chicken3
, GENX(COMMON_SLICE_CHICKEN3
),
207 .PSThreadPanicDispatch
= 0x3,
208 .PSThreadPanicDispatchMask
= 0x3);
210 anv_batch_emit(&batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
211 lri
.RegisterOffset
= GENX(COMMON_SLICE_CHICKEN3_num
);
212 lri
.DataDWord
= common_slice_chicken3
;
215 /* WaEnableStateCacheRedirectToCS:icl */
216 uint32_t slice_common_eco_chicken1
;
217 anv_pack_struct(&slice_common_eco_chicken1
,
218 GENX(SLICE_COMMON_ECO_CHICKEN1
),
219 .StateCacheRedirectToCSSectionEnable
= true,
220 .StateCacheRedirectToCSSectionEnableMask
= true);
222 anv_batch_emit(&batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
223 lri
.RegisterOffset
= GENX(SLICE_COMMON_ECO_CHICKEN1_num
);
224 lri
.DataDWord
= slice_common_eco_chicken1
;
228 /* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so
229 * 3DSTATE_CONSTANT_XS buffer 0 is an absolute address.
231 * This is only safe on kernels with context isolation support.
234 device
->instance
->physicalDevice
.has_context_isolation
) {
235 UNUSED
uint32_t tmp_reg
;
237 anv_pack_struct(&tmp_reg
, GENX(CS_DEBUG_MODE2
),
238 .CONSTANT_BUFFERAddressOffsetDisable
= true,
239 .CONSTANT_BUFFERAddressOffsetDisableMask
= true);
240 anv_batch_emit(&batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
241 lri
.RegisterOffset
= GENX(CS_DEBUG_MODE2_num
);
242 lri
.DataDWord
= tmp_reg
;
245 anv_pack_struct(&tmp_reg
, GENX(INSTPM
),
246 .CONSTANT_BUFFERAddressOffsetDisable
= true,
247 .CONSTANT_BUFFERAddressOffsetDisableMask
= true);
248 anv_batch_emit(&batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
249 lri
.RegisterOffset
= GENX(INSTPM_num
);
250 lri
.DataDWord
= tmp_reg
;
255 anv_batch_emit(&batch
, GENX(MI_BATCH_BUFFER_END
), bbe
);
257 assert(batch
.next
<= batch
.end
);
259 return anv_device_submit_simple_batch(device
, &batch
);
263 vk_to_gen_tex_filter(VkFilter filter
, bool anisotropyEnable
)
267 assert(!"Invalid filter");
268 case VK_FILTER_NEAREST
:
269 return anisotropyEnable
? MAPFILTER_ANISOTROPIC
: MAPFILTER_NEAREST
;
270 case VK_FILTER_LINEAR
:
271 return anisotropyEnable
? MAPFILTER_ANISOTROPIC
: MAPFILTER_LINEAR
;
276 vk_to_gen_max_anisotropy(float ratio
)
278 return (anv_clamp_f(ratio
, 2, 16) - 2) / 2;
281 static const uint32_t vk_to_gen_mipmap_mode
[] = {
282 [VK_SAMPLER_MIPMAP_MODE_NEAREST
] = MIPFILTER_NEAREST
,
283 [VK_SAMPLER_MIPMAP_MODE_LINEAR
] = MIPFILTER_LINEAR
286 static const uint32_t vk_to_gen_tex_address
[] = {
287 [VK_SAMPLER_ADDRESS_MODE_REPEAT
] = TCM_WRAP
,
288 [VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT
] = TCM_MIRROR
,
289 [VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
] = TCM_CLAMP
,
290 [VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
291 [VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
294 /* Vulkan specifies the result of shadow comparisons as:
295 * 1 if ref <op> texel,
299 * 0 if texel <op> ref,
302 * So, these look a bit strange because there's both a negation
303 * and swapping of the arguments involved.
305 static const uint32_t vk_to_gen_shadow_compare_op
[] = {
306 [VK_COMPARE_OP_NEVER
] = PREFILTEROPALWAYS
,
307 [VK_COMPARE_OP_LESS
] = PREFILTEROPLEQUAL
,
308 [VK_COMPARE_OP_EQUAL
] = PREFILTEROPNOTEQUAL
,
309 [VK_COMPARE_OP_LESS_OR_EQUAL
] = PREFILTEROPLESS
,
310 [VK_COMPARE_OP_GREATER
] = PREFILTEROPGEQUAL
,
311 [VK_COMPARE_OP_NOT_EQUAL
] = PREFILTEROPEQUAL
,
312 [VK_COMPARE_OP_GREATER_OR_EQUAL
] = PREFILTEROPGREATER
,
313 [VK_COMPARE_OP_ALWAYS
] = PREFILTEROPNEVER
,
317 static const uint32_t vk_to_gen_sampler_reduction_mode
[] = {
318 [VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT
] = STD_FILTER
,
319 [VK_SAMPLER_REDUCTION_MODE_MIN_EXT
] = MINIMUM
,
320 [VK_SAMPLER_REDUCTION_MODE_MAX_EXT
] = MAXIMUM
,
324 VkResult
genX(CreateSampler
)(
326 const VkSamplerCreateInfo
* pCreateInfo
,
327 const VkAllocationCallbacks
* pAllocator
,
330 ANV_FROM_HANDLE(anv_device
, device
, _device
);
331 const struct anv_physical_device
*pdevice
=
332 &device
->instance
->physicalDevice
;
333 struct anv_sampler
*sampler
;
335 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
);
337 sampler
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*sampler
), 8,
338 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
340 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
342 sampler
->n_planes
= 1;
344 uint32_t border_color_offset
= device
->border_colors
.offset
+
345 pCreateInfo
->borderColor
* 64;
348 unsigned sampler_reduction_mode
= STD_FILTER
;
349 bool enable_sampler_reduction
= false;
352 vk_foreach_struct(ext
, pCreateInfo
->pNext
) {
353 switch (ext
->sType
) {
354 case VK_STRUCTURE_TYPE_SAMPLER_YCBCR_CONVERSION_INFO
: {
355 VkSamplerYcbcrConversionInfo
*pSamplerConversion
=
356 (VkSamplerYcbcrConversionInfo
*) ext
;
357 ANV_FROM_HANDLE(anv_ycbcr_conversion
, conversion
,
358 pSamplerConversion
->conversion
);
360 /* Ignore conversion for non-YUV formats. This fulfills a requirement
361 * for clients that want to utilize same code path for images with
362 * external formats (VK_FORMAT_UNDEFINED) and "regular" RGBA images
363 * where format is known.
365 if (conversion
== NULL
|| !conversion
->format
->can_ycbcr
)
368 sampler
->n_planes
= conversion
->format
->n_planes
;
369 sampler
->conversion
= conversion
;
373 case VK_STRUCTURE_TYPE_SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT
: {
374 struct VkSamplerReductionModeCreateInfoEXT
*sampler_reduction
=
375 (struct VkSamplerReductionModeCreateInfoEXT
*) ext
;
376 sampler_reduction_mode
=
377 vk_to_gen_sampler_reduction_mode
[sampler_reduction
->reductionMode
];
378 enable_sampler_reduction
= true;
383 anv_debug_ignored_stype(ext
->sType
);
388 if (pdevice
->has_bindless_samplers
) {
389 /* If we have bindless, allocate enough samplers. We allocate 32 bytes
390 * for each sampler instead of 16 bytes because we want all bindless
391 * samplers to be 32-byte aligned so we don't have to use indirect
392 * sampler messages on them.
394 sampler
->bindless_state
=
395 anv_state_pool_alloc(&device
->dynamic_state_pool
,
396 sampler
->n_planes
* 32, 32);
399 for (unsigned p
= 0; p
< sampler
->n_planes
; p
++) {
400 const bool plane_has_chroma
=
401 sampler
->conversion
&& sampler
->conversion
->format
->planes
[p
].has_chroma
;
402 const VkFilter min_filter
=
403 plane_has_chroma
? sampler
->conversion
->chroma_filter
: pCreateInfo
->minFilter
;
404 const VkFilter mag_filter
=
405 plane_has_chroma
? sampler
->conversion
->chroma_filter
: pCreateInfo
->magFilter
;
406 const bool enable_min_filter_addr_rounding
= min_filter
!= VK_FILTER_NEAREST
;
407 const bool enable_mag_filter_addr_rounding
= mag_filter
!= VK_FILTER_NEAREST
;
408 /* From Broadwell PRM, SAMPLER_STATE:
409 * "Mip Mode Filter must be set to MIPFILTER_NONE for Planar YUV surfaces."
411 const uint32_t mip_filter_mode
=
412 (sampler
->conversion
&&
413 isl_format_is_yuv(sampler
->conversion
->format
->planes
[0].isl_format
)) ?
414 MIPFILTER_NONE
: vk_to_gen_mipmap_mode
[pCreateInfo
->mipmapMode
];
416 struct GENX(SAMPLER_STATE
) sampler_state
= {
417 .SamplerDisable
= false,
418 .TextureBorderColorMode
= DX10OGL
,
421 .LODPreClampMode
= CLAMP_MODE_OGL
,
423 .LODPreClampEnable
= CLAMP_ENABLE_OGL
,
429 .MipModeFilter
= mip_filter_mode
,
430 .MagModeFilter
= vk_to_gen_tex_filter(mag_filter
, pCreateInfo
->anisotropyEnable
),
431 .MinModeFilter
= vk_to_gen_tex_filter(min_filter
, pCreateInfo
->anisotropyEnable
),
432 .TextureLODBias
= anv_clamp_f(pCreateInfo
->mipLodBias
, -16, 15.996),
433 .AnisotropicAlgorithm
= EWAApproximation
,
434 .MinLOD
= anv_clamp_f(pCreateInfo
->minLod
, 0, 14),
435 .MaxLOD
= anv_clamp_f(pCreateInfo
->maxLod
, 0, 14),
436 .ChromaKeyEnable
= 0,
439 .ShadowFunction
= vk_to_gen_shadow_compare_op
[pCreateInfo
->compareOp
],
440 .CubeSurfaceControlMode
= OVERRIDE
,
442 .BorderColorPointer
= border_color_offset
,
445 .LODClampMagnificationMode
= MIPNONE
,
448 .MaximumAnisotropy
= vk_to_gen_max_anisotropy(pCreateInfo
->maxAnisotropy
),
449 .RAddressMinFilterRoundingEnable
= enable_min_filter_addr_rounding
,
450 .RAddressMagFilterRoundingEnable
= enable_mag_filter_addr_rounding
,
451 .VAddressMinFilterRoundingEnable
= enable_min_filter_addr_rounding
,
452 .VAddressMagFilterRoundingEnable
= enable_mag_filter_addr_rounding
,
453 .UAddressMinFilterRoundingEnable
= enable_min_filter_addr_rounding
,
454 .UAddressMagFilterRoundingEnable
= enable_mag_filter_addr_rounding
,
455 .TrilinearFilterQuality
= 0,
456 .NonnormalizedCoordinateEnable
= pCreateInfo
->unnormalizedCoordinates
,
457 .TCXAddressControlMode
= vk_to_gen_tex_address
[pCreateInfo
->addressModeU
],
458 .TCYAddressControlMode
= vk_to_gen_tex_address
[pCreateInfo
->addressModeV
],
459 .TCZAddressControlMode
= vk_to_gen_tex_address
[pCreateInfo
->addressModeW
],
462 .ReductionType
= sampler_reduction_mode
,
463 .ReductionTypeEnable
= enable_sampler_reduction
,
467 GENX(SAMPLER_STATE_pack
)(NULL
, sampler
->state
[p
], &sampler_state
);
469 if (sampler
->bindless_state
.map
) {
470 memcpy(sampler
->bindless_state
.map
+ p
* 32,
471 sampler
->state
[p
], GENX(SAMPLER_STATE_length
) * 4);
475 *pSampler
= anv_sampler_to_handle(sampler
);