2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
38 #include "main/imports.h"
39 #include "main/macros.h"
41 #include "main/mtypes.h"
42 #include "brw_structs.h"
43 #include "intel_aub.h"
44 #include "program/prog_parameter.h"
48 /* Evil hack for using libdrm in a c++ compiler. */
53 #include <intel_bufmgr.h>
63 #include "intel_debug.h"
64 #include "intel_screen.h"
65 #include "intel_tex_obj.h"
66 #include "intel_resolve_map.h"
70 * URB - uniform resource buffer. A mid-sized buffer which is
71 * partitioned between the fixed function units and used for passing
72 * values (vertices, primitives, constants) between them.
74 * CURBE - constant URB entry. An urb region (entry) used to hold
75 * constant values which the fixed function units can be instructed to
76 * preload into the GRF when spawning a thread.
78 * VUE - vertex URB entry. An urb entry holding a vertex and usually
79 * a vertex header. The header contains control information and
80 * things like primitive type, Begin/end flags and clip codes.
82 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
83 * unit holding rasterization and interpolation parameters.
85 * GRF - general register file. One of several register files
86 * addressable by programmed threads. The inputs (r0, payload, curbe,
87 * urb) of the thread are preloaded to this area before the thread is
88 * spawned. The registers are individually 8 dwords wide and suitable
89 * for general usage. Registers holding thread input values are not
90 * special and may be overwritten.
92 * MRF - message register file. Threads communicate (and terminate)
93 * by sending messages. Message parameters are placed in contiguous
94 * MRF registers. All program output is via these messages. URB
95 * entries are populated by sending a message to the shared URB
96 * function containing the new data, together with a control word,
97 * often an unmodified copy of R0.
99 * R0 - GRF register 0. Typically holds control information used when
100 * sending messages to other threads.
102 * EU or GEN4 EU: The name of the programmable subsystem of the
103 * i965 hardware. Threads are executed by the EU, the registers
104 * described above are part of the EU architecture.
106 * Fixed function units:
108 * CS - Command streamer. Notional first unit, little software
109 * interaction. Holds the URB entries used for constant data, ie the
112 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
113 * this unit is responsible for pulling vertices out of vertex buffers
114 * in vram and injecting them into the processing pipe as VUEs. If
115 * enabled, it first passes them to a VS thread which is a good place
116 * for the driver to implement any active vertex shader.
118 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
119 * enabled, incoming strips etc are passed to GS threads in individual
120 * line/triangle/point units. The GS thread may perform arbitary
121 * computation and emit whatever primtives with whatever vertices it
122 * chooses. This makes GS an excellent place to implement GL's
123 * unfilled polygon modes, though of course it is capable of much
124 * more. Additionally, GS is used to translate away primitives not
125 * handled by latter units, including Quads and Lineloops.
127 * CS - Clipper. Mesa's clipping algorithms are imported to run on
128 * this unit. The fixed function part performs cliptesting against
129 * the 6 fixed clipplanes and makes descisions on whether or not the
130 * incoming primitive needs to be passed to a thread for clipping.
131 * User clip planes are handled via cooperation with the VS thread.
133 * SF - Strips Fans or Setup: Triangles are prepared for
134 * rasterization. Interpolation coefficients are calculated.
135 * Flatshading and two-side lighting usually performed here.
137 * WM - Windower. Interpolation of vertex attributes performed here.
138 * Fragment shader implemented here. SIMD aspects of EU taken full
139 * advantage of, as pixels are processed in blocks of 16.
141 * CC - Color Calculator. No EU threads associated with this unit.
142 * Handles blending and (presumably) depth and stencil testing.
147 struct brw_vs_prog_key
;
148 struct brw_vue_prog_key
;
149 struct brw_wm_prog_key
;
150 struct brw_wm_prog_data
;
151 struct brw_cs_prog_key
;
152 struct brw_cs_prog_data
;
156 BRW_COMPUTE_PIPELINE
,
163 BRW_CACHE_BLORP_BLIT_PROG
,
166 BRW_CACHE_FF_GS_PROG
,
175 /* brw_cache_ids must come first - see brw_state_cache.c */
176 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
177 BRW_STATE_FRAGMENT_PROGRAM
,
178 BRW_STATE_GEOMETRY_PROGRAM
,
179 BRW_STATE_VERTEX_PROGRAM
,
180 BRW_STATE_CURBE_OFFSETS
,
181 BRW_STATE_REDUCED_PRIMITIVE
,
186 BRW_STATE_VS_BINDING_TABLE
,
187 BRW_STATE_GS_BINDING_TABLE
,
188 BRW_STATE_PS_BINDING_TABLE
,
192 BRW_STATE_INDEX_BUFFER
,
193 BRW_STATE_VS_CONSTBUF
,
194 BRW_STATE_GS_CONSTBUF
,
195 BRW_STATE_PROGRAM_CACHE
,
196 BRW_STATE_STATE_BASE_ADDRESS
,
197 BRW_STATE_VUE_MAP_GEOM_OUT
,
198 BRW_STATE_TRANSFORM_FEEDBACK
,
199 BRW_STATE_RASTERIZER_DISCARD
,
201 BRW_STATE_UNIFORM_BUFFER
,
202 BRW_STATE_ATOMIC_BUFFER
,
203 BRW_STATE_IMAGE_UNITS
,
204 BRW_STATE_META_IN_PROGRESS
,
205 BRW_STATE_INTERPOLATION_MAP
,
206 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
207 BRW_STATE_NUM_SAMPLES
,
208 BRW_STATE_TEXTURE_BUFFER
,
209 BRW_STATE_GEN4_UNIT_STATE
,
213 BRW_STATE_SAMPLER_STATE_TABLE
,
214 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
215 BRW_STATE_COMPUTE_PROGRAM
,
216 BRW_STATE_CS_WORK_GROUPS
,
221 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
223 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
224 * When the currently bound shader program differs from the previous draw
225 * call, these will be flagged. They cover brw->{stage}_program and
226 * ctx->{Stage}Program->_Current.
228 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
229 * driver perspective. Even if the same shader is bound at the API level,
230 * we may need to switch between multiple versions of that shader to handle
231 * changes in non-orthagonal state.
233 * Additionally, multiple shader programs may have identical vertex shaders
234 * (for example), or compile down to the same code in the backend. We combine
235 * those into a single program cache entry.
237 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
238 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
240 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
241 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
242 * use the normal state upload paths), but the cache is still used. To avoid
243 * polluting the brw_state_cache code with special cases, we retain the dirty
244 * bit for now. It should eventually be removed.
246 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_BLIT_PROG)
247 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
248 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
249 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
250 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
251 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
252 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
253 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
254 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
255 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
256 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
257 #define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS)
258 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
259 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
260 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
261 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
262 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
263 #define BRW_NEW_VS_BINDING_TABLE (1ull << BRW_STATE_VS_BINDING_TABLE)
264 #define BRW_NEW_GS_BINDING_TABLE (1ull << BRW_STATE_GS_BINDING_TABLE)
265 #define BRW_NEW_PS_BINDING_TABLE (1ull << BRW_STATE_PS_BINDING_TABLE)
266 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
267 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
269 * Used for any batch entry with a relocated pointer that will be used
270 * by any 3D rendering.
272 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
273 /** \see brw.state.depth_region */
274 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
275 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
276 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
277 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
278 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
279 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
280 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
281 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
282 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
283 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
284 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
285 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
286 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
287 #define BRW_NEW_INTERPOLATION_MAP (1ull << BRW_STATE_INTERPOLATION_MAP)
288 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
289 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
290 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
291 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
292 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
293 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
294 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
295 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
296 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
297 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
298 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
300 struct brw_state_flags
{
301 /** State update flags signalled by mesa internals */
304 * State update flags signalled as the result of brw_tracked_state updates
309 /** Subclass of Mesa vertex program */
310 struct brw_vertex_program
{
311 struct gl_vertex_program program
;
316 /** Subclass of Mesa geometry program */
317 struct brw_geometry_program
{
318 struct gl_geometry_program program
;
319 unsigned id
; /**< serial no. to identify geom progs, never re-used */
323 /** Subclass of Mesa fragment program */
324 struct brw_fragment_program
{
325 struct gl_fragment_program program
;
326 GLuint id
; /**< serial no. to identify frag progs, never re-used */
330 /** Subclass of Mesa compute program */
331 struct brw_compute_program
{
332 struct gl_compute_program program
;
333 unsigned id
; /**< serial no. to identify compute progs, never re-used */
338 struct gl_shader base
;
343 /* Note: If adding fields that need anything besides a normal memcmp() for
344 * comparing them, be sure to go fix brw_stage_prog_data_compare().
346 struct brw_stage_prog_data
{
348 /** size of our binding table. */
352 * surface indices for the various groups of surfaces
354 uint32_t pull_constants_start
;
355 uint32_t texture_start
;
356 uint32_t gather_texture_start
;
359 uint32_t image_start
;
360 uint32_t shader_time_start
;
364 uint32_t *map_entries
;
366 uint32_t index_count
;
368 } bind_map
[8]; /* MAX_SETS from vulkan/private.h */
370 GLuint nr_params
; /**< number of float params/constants */
371 GLuint nr_pull_params
;
372 unsigned nr_image_params
;
374 unsigned curb_read_length
;
375 unsigned total_scratch
;
378 * Register where the thread expects to find input data from the URB
379 * (typically uniforms, followed by vertex or fragment attributes).
381 unsigned dispatch_grf_start_reg
;
383 bool use_alt_mode
; /**< Use ALT floating point mode? Otherwise, IEEE. */
385 /* Pointers to tracked values (only valid once
386 * _mesa_load_state_parameters has been called at runtime).
388 * These must be the last fields of the struct (see
389 * brw_stage_prog_data_compare()).
391 const gl_constant_value
**param
;
392 const gl_constant_value
**pull_param
;
395 * Image metadata passed to the shader as uniforms. This is deliberately
396 * ignored by brw_stage_prog_data_compare() because its contents don't have
397 * any influence on program compilation.
399 struct brw_image_param
*image_param
;
403 * Image metadata structure as laid out in the shader parameter
404 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
405 * able to use them. That's okay because the padding and any unused
406 * entries [most of them except when we're doing untyped surface
407 * access] will be removed by the uniform packing pass.
409 #define BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET 0
410 #define BRW_IMAGE_PARAM_OFFSET_OFFSET 4
411 #define BRW_IMAGE_PARAM_SIZE_OFFSET 8
412 #define BRW_IMAGE_PARAM_STRIDE_OFFSET 12
413 #define BRW_IMAGE_PARAM_TILING_OFFSET 16
414 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 20
415 #define BRW_IMAGE_PARAM_SIZE 24
417 struct brw_image_param
{
418 /** Surface binding table index. */
419 uint32_t surface_idx
;
421 /** Offset applied to the X and Y surface coordinates. */
424 /** Surface X, Y and Z dimensions. */
427 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
428 * pixels, vertical slice stride in pixels.
432 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
436 * Right shift to apply for bit 6 address swizzling. Two different
437 * swizzles can be specified and will be applied one after the other. The
438 * resulting address will be:
440 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
441 * (addr >> swizzling[1])))
443 * Use \c 0xff if any of the swizzles is not required.
445 uint32_t swizzling
[2];
448 /* Data about a particular attempt to compile a program. Note that
449 * there can be many of these, each in a different GL state
450 * corresponding to a different brw_wm_prog_key struct, with different
453 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
456 struct brw_wm_prog_data
{
457 struct brw_stage_prog_data base
;
459 GLuint num_varying_inputs
;
461 GLuint dispatch_grf_start_reg_16
;
463 GLuint reg_blocks_16
;
467 * surface indices the WM-specific surfaces
469 uint32_t render_target_start
;
473 uint8_t computed_depth_mode
;
475 bool early_fragment_tests
;
478 bool uses_pos_offset
;
482 uint32_t prog_offset_16
;
485 * Mask of which interpolation modes are required by the fragment shader.
486 * Used in hardware setup on gen6+.
488 uint32_t barycentric_interp_modes
;
491 * Map from gl_varying_slot to the position within the FS setup data
492 * payload where the varying's attribute vertex deltas should be delivered.
493 * For varying slots that are not used by the FS, the value is -1.
495 int urb_setup
[VARYING_SLOT_MAX
];
498 /* Note: brw_cs_prog_data_compare() must be updated when adding fields to this
501 struct brw_cs_prog_data
{
502 struct brw_stage_prog_data base
;
504 GLuint dispatch_grf_start_reg_16
;
505 unsigned local_size
[3];
508 bool uses_num_work_groups
;
512 * surface indices the CS-specific surfaces
514 uint32_t work_groups_start
;
520 * Enum representing the i965-specific vertex results that don't correspond
521 * exactly to any element of gl_varying_slot. The values of this enum are
522 * assigned such that they don't conflict with gl_varying_slot.
526 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
527 BRW_VARYING_SLOT_PAD
,
529 * Technically this is not a varying but just a placeholder that
530 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
531 * builtin variable to be compiled correctly. see compile_sf_prog() for
534 BRW_VARYING_SLOT_PNTC
,
535 BRW_VARYING_SLOT_COUNT
540 * Data structure recording the relationship between the gl_varying_slot enum
541 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
542 * single octaword within the VUE (128 bits).
544 * Note that each BRW register contains 256 bits (2 octawords), so when
545 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
546 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
547 * in a vertex shader), each register corresponds to a single VUE slot, since
548 * it contains data for two separate vertices.
552 * Bitfield representing all varying slots that are (a) stored in this VUE
553 * map, and (b) actually written by the shader. Does not include any of
554 * the additional varying slots defined in brw_varying_slot.
556 GLbitfield64 slots_valid
;
559 * Is this VUE map for a separate shader pipeline?
561 * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
562 * without the linker having a chance to dead code eliminate unused varyings.
564 * This means that we have to use a fixed slot layout, based on the output's
565 * location field, rather than assigning slots in a compact contiguous block.
570 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
571 * not stored in a slot (because they are not written, or because
572 * additional processing is applied before storing them in the VUE), the
575 signed char varying_to_slot
[BRW_VARYING_SLOT_COUNT
];
578 * Map from VUE slot to gl_varying_slot value. For slots that do not
579 * directly correspond to a gl_varying_slot, the value comes from
582 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
583 * simplifies code that uses the value stored in slot_to_varying to
584 * create a bit mask).
586 signed char slot_to_varying
[BRW_VARYING_SLOT_COUNT
];
589 * Total number of VUE slots in use
595 * Convert a VUE slot number into a byte offset within the VUE.
597 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
603 * Convert a vertex output (brw_varying_slot) into a byte offset within the
606 static inline GLuint
brw_varying_to_offset(struct brw_vue_map
*vue_map
,
609 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
612 void brw_compute_vue_map(const struct brw_device_info
*devinfo
,
613 struct brw_vue_map
*vue_map
,
614 GLbitfield64 slots_valid
,
615 bool separate_shader
);
619 * Bitmask indicating which fragment shader inputs represent varyings (and
620 * hence have to be delivered to the fragment shader by the SF/SBE stage).
622 #define BRW_FS_VARYING_INPUT_MASK \
623 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
624 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
628 * Mapping of VUE map slots to interpolation modes.
630 struct interpolation_mode_map
{
631 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
634 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
636 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
637 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
643 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
645 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
646 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
653 struct brw_sf_prog_data
{
654 GLuint urb_read_length
;
657 /* Each vertex may have upto 12 attributes, 4 components each,
658 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
661 * Actually we use 4 for each, so call it 12 rows.
663 GLuint urb_entry_size
;
668 * We always program SF to start reading at an offset of 1 (2 varying slots)
669 * from the start of the vertex URB entry. This causes it to skip:
670 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
671 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
673 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
676 struct brw_clip_prog_data
{
677 GLuint curb_read_length
; /* user planes? */
679 GLuint urb_read_length
;
683 struct brw_ff_gs_prog_data
{
684 GLuint urb_read_length
;
688 * Gen6 transform feedback: Amount by which the streaming vertex buffer
689 * indices should be incremented each time the GS is invoked.
691 unsigned svbi_postincrement_value
;
694 enum shader_dispatch_mode
{
695 DISPATCH_MODE_4X1_SINGLE
= 0,
696 DISPATCH_MODE_4X2_DUAL_INSTANCE
= 1,
697 DISPATCH_MODE_4X2_DUAL_OBJECT
= 2,
698 DISPATCH_MODE_SIMD8
= 3,
701 /* Note: brw_vue_prog_data_compare() must be updated when adding fields to
704 struct brw_vue_prog_data
{
705 struct brw_stage_prog_data base
;
706 struct brw_vue_map vue_map
;
708 GLuint urb_read_length
;
711 /* Used for calculating urb partitions. In the VS, this is the size of the
712 * URB entry used for both input and output to the thread. In the GS, this
713 * is the size of the URB entry used for output.
715 GLuint urb_entry_size
;
717 enum shader_dispatch_mode dispatch_mode
;
721 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
724 struct brw_vs_prog_data
{
725 struct brw_vue_prog_data base
;
727 GLbitfield64 inputs_read
;
730 bool uses_instanceid
;
733 /** Number of texture sampler units */
734 #define BRW_MAX_TEX_UNIT 32
736 /** Max number of render targets in a shader */
737 #define BRW_MAX_DRAW_BUFFERS 8
739 /** Max number of atomic counter buffer objects in a shader */
740 #define BRW_MAX_ABO 16
742 /** Max number of image uniforms in a shader */
743 #define BRW_MAX_IMAGES 32
746 * Max number of binding table entries used for stream output.
748 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
749 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
751 * On Gen6, the size of transform feedback data is limited not by the number
752 * of components but by the number of binding table entries we set aside. We
753 * use one binding table entry for a float, one entry for a vector, and one
754 * entry per matrix column. Since the only way we can communicate our
755 * transform feedback capabilities to the client is via
756 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
757 * worst case, in which all the varyings are floats, so we use up one binding
758 * table entry per component. Therefore we need to set aside at least 64
759 * binding table entries for use by transform feedback.
761 * Note: since we don't currently pack varyings, it is currently impossible
762 * for the client to actually use up all of these binding table entries--if
763 * all of their varyings were floats, they would run out of varying slots and
764 * fail to link. But that's a bug, so it seems prudent to go ahead and
765 * allocate the number of binding table entries we will need once the bug is
768 #define BRW_MAX_SOL_BINDINGS 64
770 /** Maximum number of actual buffers used for stream output */
771 #define BRW_MAX_SOL_BUFFERS 4
773 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
774 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
778 2 + /* shader time, pull constants */ \
779 1 /* cs num work groups */)
781 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
783 /* Note: brw_gs_prog_data_compare() must be updated when adding fields to
786 struct brw_gs_prog_data
788 struct brw_vue_prog_data base
;
791 * Size of an output vertex, measured in HWORDS (32 bytes).
793 unsigned output_vertex_size_hwords
;
795 unsigned output_topology
;
798 * Size of the control data (cut bits or StreamID bits), in hwords (32
799 * bytes). 0 if there is no control data.
801 unsigned control_data_header_size_hwords
;
804 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
805 * if the control data is StreamID bits, or
806 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
807 * Ignored if control_data_header_size is 0.
809 unsigned control_data_format
;
811 bool include_primitive_id
;
814 * The number of vertices emitted, if constant - otherwise -1.
816 int static_vertex_count
;
821 * Gen6 transform feedback enabled flag.
823 bool gen6_xfb_enabled
;
826 * Gen6: Provoking vertex convention for odd-numbered triangles
832 * Gen6: Number of varyings that are output to transform feedback.
834 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
837 * Gen6: Map from the index of a transform feedback binding table entry to the
838 * gl_varying_slot that should be streamed out through that binding table
841 unsigned char transform_feedback_bindings
[BRW_MAX_SOL_BINDINGS
];
844 * Gen6: Map from the index of a transform feedback binding table entry to the
845 * swizzles that should be used when streaming out data through that
846 * binding table entry.
848 unsigned char transform_feedback_swizzles
[BRW_MAX_SOL_BINDINGS
];
852 * Stride in bytes between shader_time entries.
854 * We separate entries by a cacheline to reduce traffic between EUs writing to
857 #define SHADER_TIME_STRIDE 64
859 struct brw_cache_item
{
861 * Effectively part of the key, cache_id identifies what kind of state
862 * buffer is involved, and also which dirty flag should set.
864 enum brw_cache_id cache_id
;
865 /** 32-bit hash of the key data */
867 GLuint key_size
; /* for variable-sized keys */
874 struct brw_cache_item
*next
;
878 typedef bool (*cache_aux_compare_func
)(const void *a
, const void *b
);
879 typedef void (*cache_aux_free_func
)(const void *aux
);
882 struct brw_context
*brw
;
884 struct brw_cache_item
**items
;
886 GLuint size
, n_items
;
888 uint32_t next_offset
;
892 * Optional functions used in determining whether the prog_data for a new
893 * cache item matches an existing cache item (in case there's relevant data
894 * outside of the prog_data). If NULL, a plain memcmp is done.
896 cache_aux_compare_func aux_compare
[BRW_MAX_CACHE
];
897 /** Optional functions for freeing other pointers attached to a prog_data. */
898 cache_aux_free_func aux_free
[BRW_MAX_CACHE
];
902 /* Considered adding a member to this struct to document which flags
903 * an update might raise so that ordering of the state atoms can be
904 * checked or derived at runtime. Dropped the idea in favor of having
905 * a debug mode where the state is monitored for flags which are
906 * raised that have already been tested against.
908 struct brw_tracked_state
{
909 struct brw_state_flags dirty
;
910 void (*emit
)( struct brw_context
*brw
);
913 enum shader_time_shader_type
{
922 struct brw_vertex_buffer
{
923 /** Buffer object containing the uploaded vertex data */
926 /** Byte stride between elements in the uploaded array */
930 struct brw_vertex_element
{
931 const struct gl_client_array
*glarray
;
935 /** Offset of the first element within the buffer object */
939 struct brw_query_object
{
940 struct gl_query_object Base
;
942 /** Last query BO associated with this query. */
945 /** Last index in bo with query data for this object. */
948 /** True if we know the batch has been flushed since we ended the query. */
958 struct intel_batchbuffer
{
959 /** Current batchbuffer being queued up. */
961 /** Last BO submitted to the hardware. Used for glFinish(). */
962 drm_intel_bo
*last_bo
;
965 uint16_t emit
, total
;
967 uint16_t reserved_space
;
971 #define BATCH_SZ (8192*sizeof(uint32_t))
973 uint32_t state_batch_offset
;
974 enum brw_gpu_ring ring
;
975 bool needs_sol_reset
;
983 #define BRW_MAX_XFB_STREAMS 4
985 struct brw_transform_feedback_object
{
986 struct gl_transform_feedback_object base
;
988 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
989 drm_intel_bo
*offset_bo
;
991 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
994 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
995 GLenum primitive_mode
;
998 * Count of primitives generated during this transform feedback operation.
1001 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
1002 drm_intel_bo
*prim_count_bo
;
1003 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
1007 * Number of vertices written between last Begin/EndTransformFeedback().
1009 * Used to implement DrawTransformFeedback().
1011 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
1012 bool vertices_written_valid
;
1016 * Data shared between each programmable stage in the pipeline (vs, gs, and
1019 struct brw_stage_state
1021 gl_shader_stage stage
;
1022 struct brw_stage_prog_data
*prog_data
;
1025 * Optional scratch buffer used to store spilled register values and
1026 * variably-indexed GRF arrays.
1028 drm_intel_bo
*scratch_bo
;
1030 /** Offset in the program cache to the program */
1031 uint32_t prog_offset
;
1033 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
1034 uint32_t state_offset
;
1036 uint32_t push_const_offset
; /* Offset in the batchbuffer */
1037 int push_const_size
; /* in 256-bit register increments */
1039 /* Binding table: pointers to SURFACE_STATE entries. */
1040 uint32_t bind_bo_offset
;
1041 uint32_t surf_offset
[BRW_MAX_SURFACES
];
1043 /** SAMPLER_STATE count and table offset */
1044 uint32_t sampler_count
;
1045 uint32_t sampler_offset
;
1048 enum brw_predicate_state
{
1049 /* The first two states are used if we can determine whether to draw
1050 * without having to look at the values in the query object buffer. This
1051 * will happen if there is no conditional render in progress, if the query
1052 * object is already completed or if something else has already added
1053 * samples to the preliminary result such as via a BLT command.
1055 BRW_PREDICATE_STATE_RENDER
,
1056 BRW_PREDICATE_STATE_DONT_RENDER
,
1057 /* In this case whether to draw or not depends on the result of an
1058 * MI_PREDICATE command so the predicate enable bit needs to be checked.
1060 BRW_PREDICATE_STATE_USE_BIT
1063 struct shader_times
;
1066 * brw_context is derived from gl_context.
1070 struct gl_context ctx
; /**< base class, must be first field */
1074 void (*update_texture_surface
)(struct gl_context
*ctx
,
1076 uint32_t *surf_offset
,
1078 uint32_t (*update_renderbuffer_surface
)(struct brw_context
*brw
,
1079 struct gl_renderbuffer
*rb
,
1080 bool layered
, unsigned unit
,
1081 uint32_t surf_index
);
1083 void (*emit_texture_surface_state
)(struct brw_context
*brw
,
1084 struct intel_mipmap_tree
*mt
,
1092 uint32_t *surf_offset
,
1093 bool rw
, bool for_gather
);
1094 void (*emit_buffer_surface_state
)(struct brw_context
*brw
,
1095 uint32_t *out_offset
,
1097 unsigned buffer_offset
,
1098 unsigned surface_format
,
1099 unsigned buffer_size
,
1102 void (*emit_null_surface_state
)(struct brw_context
*brw
,
1106 uint32_t *out_offset
);
1109 * Send the appropriate state packets to configure depth, stencil, and
1110 * HiZ buffers (i965+ only)
1112 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
1113 struct intel_mipmap_tree
*depth_mt
,
1114 uint32_t depth_offset
,
1115 uint32_t depthbuffer_format
,
1116 uint32_t depth_surface_type
,
1117 struct intel_mipmap_tree
*stencil_mt
,
1118 bool hiz
, bool separate_stencil
,
1119 uint32_t width
, uint32_t height
,
1120 uint32_t tile_x
, uint32_t tile_y
);
1126 drm_intel_context
*hw_ctx
;
1128 /** BO for post-sync nonzero writes for gen6 workaround. */
1129 drm_intel_bo
*workaround_bo
;
1130 uint8_t pipe_controls_since_last_cs_stall
;
1133 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
1134 * and would need flushing before being used from another cache domain that
1135 * isn't coherent with it (i.e. the sampler).
1137 struct set
*render_cache
;
1140 * Number of resets observed in the system at context creation.
1142 * This is tracked in the context so that we can determine that another
1143 * reset has occurred.
1145 uint32_t reset_count
;
1147 struct intel_batchbuffer batch
;
1152 uint32_t next_offset
;
1156 * Set if rendering has occurred to the drawable's front buffer.
1158 * This is used in the DRI2 case to detect that glFlush should also copy
1159 * the contents of the fake front buffer to the real front buffer.
1161 bool front_buffer_dirty
;
1163 /** Framerate throttling: @{ */
1164 drm_intel_bo
*throttle_batch
[2];
1166 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
1167 * frame of rendering to complete. This gives a very precise cap to the
1168 * latency between input and output such that rendering never gets more
1169 * than a frame behind the user. (With the caveat that we technically are
1170 * not using the SwapBuffers itself as a barrier but the first batch
1171 * submitted afterwards, which may be immediately prior to the next
1174 bool need_swap_throttle
;
1176 /** General throttling, not caught by throttling between SwapBuffers */
1177 bool need_flush_throttle
;
1187 bool always_flush_batch
;
1188 bool always_flush_cache
;
1189 bool disable_throttling
;
1192 driOptionCache optionCache
;
1195 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
1197 GLenum reduced_primitive
;
1200 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
1201 * variable is set, this is the flag indicating to do expensive work that
1202 * might lead to a perf_debug() call.
1206 uint32_t max_gtt_map_object_size
;
1218 bool has_separate_stencil
;
1219 bool must_use_separate_stencil
;
1222 bool has_surface_tile_offset
;
1224 bool has_negative_rhw_bug
;
1228 bool use_resource_streamer
;
1231 * Some versions of Gen hardware don't do centroid interpolation correctly
1232 * on unlit pixels, causing incorrect values for derivatives near triangle
1233 * edges. Enabling this flag causes the fragment shader to use
1234 * non-centroid interpolation for unlit pixels, at the expense of two extra
1235 * fragment shader instructions.
1237 bool needs_unlit_centroid_workaround
;
1241 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
1244 enum brw_pipeline last_pipeline
;
1246 struct brw_cache cache
;
1248 /** IDs for meta stencil blit shader programs. */
1249 unsigned meta_stencil_blit_programs
[2];
1251 /* Whether a meta-operation is in progress. */
1252 bool meta_in_progress
;
1254 /* Whether the last depth/stencil packets were both NULL. */
1255 bool no_depth_or_stencil
;
1257 /* The last PMA stall bits programmed. */
1258 uint32_t pma_stall_bits
;
1261 /** The value of gl_BaseVertex for the current _mesa_prim. */
1265 * Buffer and offset used for GL_ARB_shader_draw_parameters
1266 * (for now, only gl_BaseVertex).
1268 drm_intel_bo
*draw_params_bo
;
1269 uint32_t draw_params_offset
;
1274 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
1275 * an indirect call, and num_work_groups_offset is valid. Otherwise,
1276 * num_work_groups is set based on glDispatchCompute.
1278 drm_intel_bo
*num_work_groups_bo
;
1279 GLintptr num_work_groups_offset
;
1280 const GLuint
*num_work_groups
;
1284 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
1285 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
1287 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
1291 /* Summary of size and varying of active arrays, so we can check
1292 * for changes to this state:
1294 unsigned int min_index
, max_index
;
1296 /* Offset from start of vertex buffer so we can avoid redefining
1297 * the same VB packed over and over again.
1299 unsigned int start_vertex_bias
;
1302 * Certain vertex attribute formats aren't natively handled by the
1303 * hardware and require special VS code to fix up their values.
1305 * These bitfields indicate which workarounds are needed.
1307 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
1312 * Index buffer for this draw_prims call.
1314 * Updates are signaled by BRW_NEW_INDICES.
1316 const struct _mesa_index_buffer
*ib
;
1318 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
1322 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
1323 * avoid re-uploading the IB packet over and over if we're actually
1324 * referencing the same index buffer.
1326 unsigned int start_vertex_offset
;
1329 /* Active vertex program:
1331 const struct gl_vertex_program
*vertex_program
;
1332 const struct gl_geometry_program
*geometry_program
;
1333 const struct gl_fragment_program
*fragment_program
;
1334 const struct gl_compute_program
*compute_program
;
1337 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
1338 * that we don't have to reemit that state every time we change FBOs.
1343 * Platform specific constants containing the maximum number of threads
1344 * for each pipeline stage.
1346 unsigned max_vs_threads
;
1347 unsigned max_hs_threads
;
1348 unsigned max_ds_threads
;
1349 unsigned max_gs_threads
;
1350 unsigned max_wm_threads
;
1351 unsigned max_cs_threads
;
1353 /* BRW_NEW_URB_ALLOCATIONS:
1356 GLuint vsize
; /* vertex size plus header in urb registers */
1357 GLuint gsize
; /* GS output size in urb registers */
1358 GLuint csize
; /* constant buffer size in urb registers */
1359 GLuint sfsize
; /* setup data size in urb registers */
1363 GLuint min_vs_entries
; /* Minimum number of VS entries */
1364 GLuint max_vs_entries
; /* Maximum number of VS entries */
1365 GLuint max_hs_entries
; /* Maximum number of HS entries */
1366 GLuint max_ds_entries
; /* Maximum number of DS entries */
1367 GLuint max_gs_entries
; /* Maximum number of GS entries */
1369 GLuint nr_vs_entries
;
1370 GLuint nr_gs_entries
;
1371 GLuint nr_clip_entries
;
1372 GLuint nr_sf_entries
;
1373 GLuint nr_cs_entries
;
1380 GLuint size
; /* Hardware URB size, in KB. */
1382 /* True if the most recently sent _3DSTATE_URB message allocated
1383 * URB space for the GS.
1389 /* BRW_NEW_CURBE_OFFSETS:
1392 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1393 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1401 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1402 * for upload to the CURBE.
1404 drm_intel_bo
*curbe_bo
;
1405 /** Offset within curbe_bo of space for current curbe entry */
1406 GLuint curbe_offset
;
1410 * Layout of vertex data exiting the geometry portion of the pipleine.
1411 * This comes from the last enabled shader stage (GS, DS, or VS).
1413 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1415 struct brw_vue_map vue_map_geom_out
;
1418 struct brw_stage_state base
;
1419 struct brw_vs_prog_data
*prog_data
;
1423 struct brw_stage_state base
;
1424 struct brw_gs_prog_data
*prog_data
;
1427 * True if the 3DSTATE_GS command most recently emitted to the 3D
1428 * pipeline enabled the GS; false otherwise.
1434 struct brw_ff_gs_prog_data
*prog_data
;
1437 /** Offset in the program cache to the CLIP program pre-gen6 */
1438 uint32_t prog_offset
;
1439 uint32_t state_offset
;
1441 uint32_t bind_bo_offset
;
1443 * Surface offsets for the binding table. We only need surfaces to
1444 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1445 * need in this case.
1447 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1451 struct brw_clip_prog_data
*prog_data
;
1453 /** Offset in the program cache to the CLIP program pre-gen6 */
1454 uint32_t prog_offset
;
1456 /* Offset in the batch to the CLIP state on pre-gen6. */
1457 uint32_t state_offset
;
1459 /* As of gen6, this is the offset in the batch to the CLIP VP,
1467 struct brw_sf_prog_data
*prog_data
;
1469 /** Offset in the program cache to the CLIP program pre-gen6 */
1470 uint32_t prog_offset
;
1471 uint32_t state_offset
;
1473 bool viewport_transform_enable
;
1477 struct brw_stage_state base
;
1478 struct brw_wm_prog_data
*prog_data
;
1483 * Buffer object used in place of multisampled null render targets on
1484 * Gen6. See brw_emit_null_surface_state().
1486 drm_intel_bo
*multisampled_null_render_target_bo
;
1487 uint32_t fast_clear_op
;
1491 struct brw_stage_state base
;
1492 struct brw_cs_prog_data
*prog_data
;
1495 /* RS hardware binding table */
1498 uint32_t next_offset
;
1502 uint32_t state_offset
;
1503 uint32_t blend_state_offset
;
1504 uint32_t depth_stencil_state_offset
;
1509 struct brw_query_object
*obj
;
1514 enum brw_predicate_state state
;
1519 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1520 const int *statistics_registers
;
1522 /** The number of active monitors using OA counters. */
1526 * A buffer object storing OA counter snapshots taken at the start and
1527 * end of each batch (creating "bookends" around the batch).
1529 drm_intel_bo
*bookend_bo
;
1531 /** The number of snapshots written to bookend_bo. */
1532 int bookend_snapshots
;
1535 * An array of monitors whose results haven't yet been assembled based on
1536 * the data in buffer objects.
1538 * These may be active, or have already ended. However, the results
1539 * have not been requested.
1541 struct brw_perf_monitor_object
**unresolved
;
1542 int unresolved_elements
;
1543 int unresolved_array_size
;
1546 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1547 * the counter which MI_REPORT_PERF_COUNT stores there.
1549 const int *oa_snapshot_layout
;
1551 /** Number of 32-bit entries in a hardware counter snapshot. */
1552 int entries_per_oa_snapshot
;
1555 int num_atoms
[BRW_NUM_PIPELINES
];
1556 const struct brw_tracked_state render_atoms
[60];
1557 const struct brw_tracked_state compute_atoms
[7];
1559 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1563 enum aub_state_struct_type type
;
1565 } *state_batch_list
;
1566 int state_batch_count
;
1568 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1569 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1571 /* Interpolation modes, one byte per vue slot.
1572 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1574 struct interpolation_mode_map interpolation_mode
;
1576 /* PrimitiveRestart */
1579 bool enable_cut_index
;
1582 /** Computed depth/stencil/hiz state from the current attached
1583 * renderbuffers, valid only during the drawing state upload loop after
1584 * brw_workaround_depthstencil_alignment().
1587 struct intel_mipmap_tree
*depth_mt
;
1588 struct intel_mipmap_tree
*stencil_mt
;
1590 /* Inter-tile (page-aligned) byte offsets. */
1591 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1592 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1593 uint32_t tile_x
, tile_y
;
1596 uint32_t num_instances
;
1603 enum shader_time_shader_type
*types
;
1604 struct shader_times
*cumulative
;
1610 struct brw_fast_clear_state
*fast_clear_state
;
1612 __DRIcontext
*driContext
;
1613 struct intel_screen
*intelScreen
;
1616 /*======================================================================
1619 void brwInitVtbl( struct brw_context
*brw
);
1622 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1624 /*======================================================================
1627 extern const char *const brw_vendor_string
;
1629 extern const char *brw_get_renderer_string(unsigned deviceID
);
1632 DRI_CONF_BO_REUSE_DISABLED
,
1633 DRI_CONF_BO_REUSE_ALL
1636 void intel_update_renderbuffers(__DRIcontext
*context
,
1637 __DRIdrawable
*drawable
);
1638 void intel_prepare_render(struct brw_context
*brw
);
1640 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1641 __DRIdrawable
*drawable
);
1643 GLboolean
brwCreateContext(gl_api api
,
1644 const struct gl_config
*mesaVis
,
1645 __DRIcontext
*driContextPriv
,
1646 unsigned major_version
,
1647 unsigned minor_version
,
1651 void *sharedContextPrivate
);
1653 /*======================================================================
1656 GLuint
brw_get_rb_for_slice(struct brw_context
*brw
,
1657 struct intel_mipmap_tree
*mt
,
1658 unsigned level
, unsigned layer
, bool flat
);
1660 void brw_meta_updownsample(struct brw_context
*brw
,
1661 struct intel_mipmap_tree
*src
,
1662 struct intel_mipmap_tree
*dst
);
1664 void brw_meta_fbo_stencil_blit(struct brw_context
*brw
,
1665 struct gl_framebuffer
*read_fb
,
1666 struct gl_framebuffer
*draw_fb
,
1667 GLfloat srcX0
, GLfloat srcY0
,
1668 GLfloat srcX1
, GLfloat srcY1
,
1669 GLfloat dstX0
, GLfloat dstY0
,
1670 GLfloat dstX1
, GLfloat dstY1
);
1672 void brw_meta_stencil_updownsample(struct brw_context
*brw
,
1673 struct intel_mipmap_tree
*src
,
1674 struct intel_mipmap_tree
*dst
);
1676 bool brw_meta_fast_clear(struct brw_context
*brw
,
1677 struct gl_framebuffer
*fb
,
1679 bool partial_clear
);
1682 brw_meta_resolve_color(struct brw_context
*brw
,
1683 struct intel_mipmap_tree
*mt
);
1685 brw_meta_fast_clear_free(struct brw_context
*brw
);
1688 /*======================================================================
1691 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1692 uint32_t depth_level
,
1693 uint32_t depth_layer
,
1694 struct intel_mipmap_tree
*stencil_mt
,
1695 uint32_t *out_tile_mask_x
,
1696 uint32_t *out_tile_mask_y
);
1697 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1698 GLbitfield clear_mask
);
1700 /* brw_object_purgeable.c */
1701 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1703 /*======================================================================
1706 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1707 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1708 void brw_emit_query_begin(struct brw_context
*brw
);
1709 void brw_emit_query_end(struct brw_context
*brw
);
1711 /** gen6_queryobj.c */
1712 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1713 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1714 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1715 void brw_store_register_mem64(struct brw_context
*brw
,
1716 drm_intel_bo
*bo
, uint32_t reg
, int idx
);
1718 /** brw_conditional_render.c */
1719 void brw_init_conditional_render_functions(struct dd_function_table
*functions
);
1720 bool brw_check_conditional_render(struct brw_context
*brw
);
1722 /** intel_batchbuffer.c */
1723 void brw_load_register_mem(struct brw_context
*brw
,
1726 uint32_t read_domains
, uint32_t write_domain
,
1728 void brw_load_register_mem64(struct brw_context
*brw
,
1731 uint32_t read_domains
, uint32_t write_domain
,
1734 /*======================================================================
1737 void brw_debug_batch(struct brw_context
*brw
);
1738 void brw_annotate_aub(struct brw_context
*brw
);
1740 /*======================================================================
1743 void brw_validate_textures( struct brw_context
*brw
);
1746 /*======================================================================
1749 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1751 int brw_get_scratch_size(int size
);
1752 void brw_get_scratch_bo(struct brw_context
*brw
,
1753 drm_intel_bo
**scratch_bo
, int size
);
1754 void brw_init_shader_time(struct brw_context
*brw
);
1755 int brw_get_shader_time_index(struct brw_context
*brw
,
1756 struct gl_shader_program
*shader_prog
,
1757 struct gl_program
*prog
,
1758 enum shader_time_shader_type type
);
1759 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1760 void brw_destroy_shader_time(struct brw_context
*brw
);
1764 void brw_upload_urb_fence(struct brw_context
*brw
);
1768 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1770 /* brw_fs_reg_allocate.cpp
1772 void brw_fs_alloc_reg_sets(struct brw_compiler
*compiler
);
1774 /* brw_vec4_reg_allocate.cpp */
1775 void brw_vec4_alloc_reg_set(struct brw_compiler
*compiler
);
1778 int brw_disassemble_inst(FILE *file
, const struct brw_device_info
*devinfo
,
1779 struct brw_inst
*inst
, bool is_compacted
);
1782 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1784 /* brw_draw_upload.c */
1785 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1786 const struct gl_client_array
*glarray
);
1788 static inline unsigned
1789 brw_get_index_type(GLenum type
)
1791 assert((type
== GL_UNSIGNED_BYTE
)
1792 || (type
== GL_UNSIGNED_SHORT
)
1793 || (type
== GL_UNSIGNED_INT
));
1795 /* The possible values for type are GL_UNSIGNED_BYTE (0x1401),
1796 * GL_UNSIGNED_SHORT (0x1403), and GL_UNSIGNED_INT (0x1405) which we want
1797 * to map to scale factors of 0, 1, and 2, respectively. These scale
1798 * factors are then left-shfited by 8 to be in the correct position in the
1799 * CMD_INDEX_BUFFER packet.
1801 * Subtracting 0x1401 gives 0, 2, and 4. Shifting left by 7 afterwards
1802 * gives 0x00000000, 0x00000100, and 0x00000200. These just happen to be
1803 * the values the need to be written in the CMD_INDEX_BUFFER packet.
1805 return (type
- 0x1401) << 7;
1808 void brw_prepare_vertices(struct brw_context
*brw
);
1810 /* brw_wm_surface_state.c */
1811 void brw_init_surface_formats(struct brw_context
*brw
);
1812 void brw_create_constant_surface(struct brw_context
*brw
,
1816 uint32_t *out_offset
,
1818 void brw_create_buffer_surface(struct brw_context
*brw
,
1822 uint32_t *out_offset
,
1824 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1826 uint32_t *surf_offset
);
1828 brw_update_sol_surface(struct brw_context
*brw
,
1829 struct gl_buffer_object
*buffer_obj
,
1830 uint32_t *out_offset
, unsigned num_vector_components
,
1831 unsigned stride_dwords
, unsigned offset_dwords
);
1832 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1833 struct gl_shader
*shader
,
1834 struct brw_stage_state
*stage_state
,
1835 struct brw_stage_prog_data
*prog_data
,
1837 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1838 struct gl_shader_program
*prog
,
1839 struct brw_stage_state
*stage_state
,
1840 struct brw_stage_prog_data
*prog_data
);
1841 void brw_upload_image_surfaces(struct brw_context
*brw
,
1842 struct gl_shader
*shader
,
1843 struct brw_stage_state
*stage_state
,
1844 struct brw_stage_prog_data
*prog_data
);
1846 /* brw_surface_formats.c */
1847 bool brw_render_target_supported(struct brw_context
*brw
,
1848 struct gl_renderbuffer
*rb
);
1849 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1850 mesa_format
brw_lower_mesa_image_format(const struct brw_device_info
*devinfo
,
1851 mesa_format format
);
1853 /* brw_performance_monitor.c */
1854 void brw_init_performance_monitors(struct brw_context
*brw
);
1855 void brw_dump_perf_monitors(struct brw_context
*brw
);
1856 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1857 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1859 /* intel_buffer_objects.c */
1860 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1861 const char *bo_name
);
1862 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1863 const char *bo_name
);
1865 /* intel_extensions.c */
1866 extern void intelInitExtensions(struct gl_context
*ctx
);
1869 extern int intel_translate_shadow_compare_func(GLenum func
);
1870 extern int intel_translate_compare_func(GLenum func
);
1871 extern int intel_translate_stencil_op(GLenum op
);
1872 extern int intel_translate_logic_op(GLenum opcode
);
1874 /* intel_syncobj.c */
1875 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
1878 struct gl_transform_feedback_object
*
1879 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1881 brw_delete_transform_feedback(struct gl_context
*ctx
,
1882 struct gl_transform_feedback_object
*obj
);
1884 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1885 struct gl_transform_feedback_object
*obj
);
1887 brw_end_transform_feedback(struct gl_context
*ctx
,
1888 struct gl_transform_feedback_object
*obj
);
1890 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1891 struct gl_transform_feedback_object
*obj
,
1894 /* gen7_sol_state.c */
1896 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1897 struct gl_transform_feedback_object
*obj
);
1899 gen7_end_transform_feedback(struct gl_context
*ctx
,
1900 struct gl_transform_feedback_object
*obj
);
1902 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1903 struct gl_transform_feedback_object
*obj
);
1905 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1906 struct gl_transform_feedback_object
*obj
);
1908 /* brw_blorp_blit.cpp */
1910 brw_blorp_framebuffer(struct brw_context
*brw
,
1911 struct gl_framebuffer
*readFb
,
1912 struct gl_framebuffer
*drawFb
,
1913 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1914 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1915 GLbitfield mask
, GLenum filter
);
1918 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1919 struct gl_renderbuffer
*src_rb
,
1920 struct gl_texture_image
*dst_image
,
1922 int srcX0
, int srcY0
,
1923 int dstX0
, int dstY0
,
1924 int width
, int height
);
1926 /* gen6_multisample_state.c */
1928 gen6_determine_sample_mask(struct brw_context
*brw
);
1931 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1932 unsigned num_samples
);
1934 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1936 gen6_get_sample_position(struct gl_context
*ctx
,
1937 struct gl_framebuffer
*fb
,
1941 gen6_set_sample_maps(struct gl_context
*ctx
);
1943 /* gen8_multisample_state.c */
1944 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1945 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1949 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1950 unsigned gs_size
, unsigned fs_size
);
1953 gen7_emit_urb_state(struct brw_context
*brw
,
1954 unsigned nr_vs_entries
, unsigned vs_size
,
1955 unsigned vs_start
, unsigned nr_gs_entries
,
1956 unsigned gs_size
, unsigned gs_start
);
1961 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1965 brw_init_compute_functions(struct dd_function_table
*functions
);
1967 /*======================================================================
1968 * Inline conversion functions. These are better-typed than the
1969 * macros used previously:
1971 static inline struct brw_context
*
1972 brw_context( struct gl_context
*ctx
)
1974 return (struct brw_context
*)ctx
;
1977 static inline struct brw_vertex_program
*
1978 brw_vertex_program(struct gl_vertex_program
*p
)
1980 return (struct brw_vertex_program
*) p
;
1983 static inline const struct brw_vertex_program
*
1984 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1986 return (const struct brw_vertex_program
*) p
;
1989 static inline struct brw_geometry_program
*
1990 brw_geometry_program(struct gl_geometry_program
*p
)
1992 return (struct brw_geometry_program
*) p
;
1995 static inline struct brw_fragment_program
*
1996 brw_fragment_program(struct gl_fragment_program
*p
)
1998 return (struct brw_fragment_program
*) p
;
2001 static inline const struct brw_fragment_program
*
2002 brw_fragment_program_const(const struct gl_fragment_program
*p
)
2004 return (const struct brw_fragment_program
*) p
;
2007 static inline struct brw_compute_program
*
2008 brw_compute_program(struct gl_compute_program
*p
)
2010 return (struct brw_compute_program
*) p
;
2014 * Pre-gen6, the register file of the EUs was shared between threads,
2015 * and each thread used some subset allocated on a 16-register block
2016 * granularity. The unit states wanted these block counts.
2019 brw_register_blocks(int reg_count
)
2021 return ALIGN(reg_count
, 16) / 16 - 1;
2024 static inline uint32_t
2025 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
2026 uint32_t prog_offset
)
2028 if (brw
->gen
>= 5) {
2029 /* Using state base address. */
2033 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
2037 I915_GEM_DOMAIN_INSTRUCTION
, 0);
2039 return brw
->cache
.bo
->offset64
+ prog_offset
;
2042 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
2043 bool brw_lower_texture_gradients(struct brw_context
*brw
,
2044 struct exec_list
*instructions
);
2045 bool brw_do_lower_unnormalized_offset(struct exec_list
*instructions
);
2047 struct opcode_desc
{
2053 extern const struct opcode_desc opcode_descs
[128];
2054 extern const char * const conditional_modifier
[16];
2057 brw_emit_depthbuffer(struct brw_context
*brw
);
2060 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
2061 struct intel_mipmap_tree
*depth_mt
,
2062 uint32_t depth_offset
, uint32_t depthbuffer_format
,
2063 uint32_t depth_surface_type
,
2064 struct intel_mipmap_tree
*stencil_mt
,
2065 bool hiz
, bool separate_stencil
,
2066 uint32_t width
, uint32_t height
,
2067 uint32_t tile_x
, uint32_t tile_y
);
2070 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
2071 struct intel_mipmap_tree
*depth_mt
,
2072 uint32_t depth_offset
, uint32_t depthbuffer_format
,
2073 uint32_t depth_surface_type
,
2074 struct intel_mipmap_tree
*stencil_mt
,
2075 bool hiz
, bool separate_stencil
,
2076 uint32_t width
, uint32_t height
,
2077 uint32_t tile_x
, uint32_t tile_y
);
2080 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
2081 struct intel_mipmap_tree
*depth_mt
,
2082 uint32_t depth_offset
, uint32_t depthbuffer_format
,
2083 uint32_t depth_surface_type
,
2084 struct intel_mipmap_tree
*stencil_mt
,
2085 bool hiz
, bool separate_stencil
,
2086 uint32_t width
, uint32_t height
,
2087 uint32_t tile_x
, uint32_t tile_y
);
2089 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
2090 struct intel_mipmap_tree
*depth_mt
,
2091 uint32_t depth_offset
, uint32_t depthbuffer_format
,
2092 uint32_t depth_surface_type
,
2093 struct intel_mipmap_tree
*stencil_mt
,
2094 bool hiz
, bool separate_stencil
,
2095 uint32_t width
, uint32_t height
,
2096 uint32_t tile_x
, uint32_t tile_y
);
2098 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
2099 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
);
2101 uint32_t get_hw_prim_for_gl_prim(int mode
);
2104 gen6_upload_push_constants(struct brw_context
*brw
,
2105 const struct gl_program
*prog
,
2106 const struct brw_stage_prog_data
*prog_data
,
2107 struct brw_stage_state
*stage_state
,
2108 enum aub_state_struct_type type
);
2111 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
2112 const struct intel_mipmap_tree
*mt
);
2114 /* brw_pipe_control.c */
2115 int brw_init_pipe_control(struct brw_context
*brw
,
2116 const struct brw_device_info
*info
);
2117 void brw_fini_pipe_control(struct brw_context
*brw
);
2119 void brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
);
2120 void brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
2121 drm_intel_bo
*bo
, uint32_t offset
,
2122 uint32_t imm_lower
, uint32_t imm_upper
);
2123 void brw_emit_mi_flush(struct brw_context
*brw
);
2124 void brw_emit_post_sync_nonzero_flush(struct brw_context
*brw
);
2125 void brw_emit_depth_stall_flushes(struct brw_context
*brw
);
2126 void gen7_emit_vs_workaround_flush(struct brw_context
*brw
);
2127 void gen7_emit_cs_stall_flush(struct brw_context
*brw
);