2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "drm-uapi/drm_fourcc.h"
30 #include "main/context.h"
31 #include "main/framebuffer.h"
32 #include "main/renderbuffer.h"
33 #include "main/texobj.h"
34 #include "main/hash.h"
35 #include "main/fbobject.h"
36 #include "main/version.h"
37 #include "main/glthread.h"
38 #include "swrast/s_renderbuffer.h"
39 #include "util/ralloc.h"
40 #include "util/disk_cache.h"
41 #include "brw_defines.h"
42 #include "brw_state.h"
43 #include "compiler/nir/nir.h"
46 #include "util/disk_cache.h"
47 #include "util/xmlpool.h"
48 #include "util/u_memory.h"
50 #include "common/gen_defines.h"
52 static const __DRIconfigOptionsExtension brw_config_options
= {
53 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
56 DRI_CONF_SECTION_PERFORMANCE
57 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
58 * DRI_CONF_BO_REUSE_ALL
60 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
61 DRI_CONF_DESC_BEGIN(en
, "Buffer object reuse")
62 DRI_CONF_ENUM(0, "Disable buffer object reuse")
63 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
66 DRI_CONF_MESA_NO_ERROR("false")
67 DRI_CONF_MESA_GLTHREAD("false")
70 DRI_CONF_SECTION_QUALITY
71 DRI_CONF_PRECISE_TRIG("false")
73 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
74 DRI_CONF_DESC(en
, "Clamp the value of GL_MAX_SAMPLES to the "
75 "given integer. If negative, then do not clamp.")
79 DRI_CONF_SECTION_DEBUG
80 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
81 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
82 DRI_CONF_DISABLE_THROTTLING("false")
83 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
84 DRI_CONF_FORCE_GLSL_VERSION(0)
85 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
86 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
87 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
88 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
89 DRI_CONF_ALLOW_GLSL_BUILTIN_VARIABLE_REDECLARATION("false")
90 DRI_CONF_ALLOW_GLSL_CROSS_STAGE_INTERPOLATION_MISMATCH("false")
91 DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
92 DRI_CONF_FORCE_COMPAT_PROFILE("false")
93 DRI_CONF_FORCE_GLSL_ABS_SQRT("false")
95 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
96 DRI_CONF_DESC(en
, "Perform code generation at shader link time.")
100 DRI_CONF_SECTION_MISCELLANEOUS
101 DRI_CONF_GLSL_ZERO_INIT("false")
102 DRI_CONF_VS_POSITION_ALWAYS_INVARIANT("false")
103 DRI_CONF_ALLOW_RGB10_CONFIGS("false")
104 DRI_CONF_ALLOW_RGB565_CONFIGS("true")
105 DRI_CONF_ALLOW_FP16_CONFIGS("false")
110 #include "intel_batchbuffer.h"
111 #include "intel_buffers.h"
112 #include "brw_bufmgr.h"
113 #include "intel_fbo.h"
114 #include "intel_mipmap_tree.h"
115 #include "intel_screen.h"
116 #include "intel_tex.h"
117 #include "intel_image.h"
119 #include "brw_context.h"
121 #include "drm-uapi/i915_drm.h"
124 * For debugging purposes, this returns a time in seconds.
131 clock_gettime(CLOCK_MONOTONIC
, &tp
);
133 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
136 static const __DRItexBufferExtension intelTexBufferExtension
= {
137 .base
= { __DRI_TEX_BUFFER
, 3 },
139 .setTexBuffer
= intelSetTexBuffer
,
140 .setTexBuffer2
= intelSetTexBuffer2
,
141 .releaseTexBuffer
= intelReleaseTexBuffer
,
145 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
146 __DRIdrawable
*dPriv
,
148 enum __DRI2throttleReason reason
)
150 struct brw_context
*brw
= cPriv
->driverPrivate
;
155 struct gl_context
*ctx
= &brw
->ctx
;
157 _mesa_glthread_finish(ctx
);
159 FLUSH_VERTICES(ctx
, 0);
161 if (flags
& __DRI2_FLUSH_DRAWABLE
)
162 intel_resolve_for_dri2_flush(brw
, dPriv
);
164 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
)
165 brw
->need_swap_throttle
= true;
166 if (reason
== __DRI2_THROTTLE_FLUSHFRONT
)
167 brw
->need_flush_throttle
= true;
169 intel_batchbuffer_flush(brw
);
173 * Provides compatibility with loaders that only support the older (version
174 * 1-3) flush interface.
176 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
179 intel_dri2_flush(__DRIdrawable
*drawable
)
181 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
182 __DRI2_FLUSH_DRAWABLE
,
183 __DRI2_THROTTLE_SWAPBUFFER
);
186 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
187 .base
= { __DRI2_FLUSH
, 4 },
189 .flush
= intel_dri2_flush
,
190 .invalidate
= dri2InvalidateDrawable
,
191 .flush_with_flags
= intel_dri2_flush_with_flags
,
194 static const struct intel_image_format intel_image_formats
[] = {
195 { DRM_FORMAT_ABGR16161616F
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
196 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR16161616F
, 8 } } },
198 { DRM_FORMAT_XBGR16161616F
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
199 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR16161616F
, 8 } } },
201 { DRM_FORMAT_ARGB2101010
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
202 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB2101010
, 4 } } },
204 { DRM_FORMAT_XRGB2101010
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
205 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB2101010
, 4 } } },
207 { DRM_FORMAT_ABGR2101010
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
208 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR2101010
, 4 } } },
210 { DRM_FORMAT_XBGR2101010
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
211 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR2101010
, 4 } } },
213 { DRM_FORMAT_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
214 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
216 { DRM_FORMAT_ABGR8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
217 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
219 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
220 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
222 { __DRI_IMAGE_FOURCC_SXRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
223 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SXRGB8
, 4 } } },
225 { DRM_FORMAT_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
226 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
228 { DRM_FORMAT_XBGR8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
229 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 }, } },
231 { DRM_FORMAT_ARGB1555
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
232 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555
, 2 } } },
234 { DRM_FORMAT_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
235 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
237 { DRM_FORMAT_R8
, __DRI_IMAGE_COMPONENTS_R
, 1,
238 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 }, } },
240 { DRM_FORMAT_R16
, __DRI_IMAGE_COMPONENTS_R
, 1,
241 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 1 }, } },
243 { DRM_FORMAT_GR88
, __DRI_IMAGE_COMPONENTS_RG
, 1,
244 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 }, } },
246 { DRM_FORMAT_GR1616
, __DRI_IMAGE_COMPONENTS_RG
, 1,
247 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616
, 2 }, } },
249 { DRM_FORMAT_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
250 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
251 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
252 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
254 { DRM_FORMAT_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
255 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
256 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
257 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
259 { DRM_FORMAT_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
260 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
261 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
262 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
264 { DRM_FORMAT_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
265 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
266 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
267 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
269 { DRM_FORMAT_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
270 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
271 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
272 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
274 { DRM_FORMAT_YVU410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
275 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
276 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
277 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
279 { DRM_FORMAT_YVU411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
280 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
281 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
282 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
284 { DRM_FORMAT_YVU420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
285 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
286 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
287 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
289 { DRM_FORMAT_YVU422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
290 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
291 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
292 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
294 { DRM_FORMAT_YVU444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
295 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
296 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
297 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
299 { DRM_FORMAT_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
300 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
301 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
303 { DRM_FORMAT_P010
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
304 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 2 },
305 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616
, 4 } } },
307 { DRM_FORMAT_P012
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
308 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 2 },
309 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616
, 4 } } },
311 { DRM_FORMAT_P016
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
312 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 2 },
313 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616
, 4 } } },
315 { DRM_FORMAT_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
316 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
317 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
319 { DRM_FORMAT_AYUV
, __DRI_IMAGE_COMPONENTS_AYUV
, 1,
320 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
322 { DRM_FORMAT_XYUV8888
, __DRI_IMAGE_COMPONENTS_XYUV
, 1,
323 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 } } },
325 /* For YUYV and UYVY buffers, we set up two overlapping DRI images
326 * and treat them as planar buffers in the compositors.
327 * Plane 0 is GR88 and samples YU or YV pairs and places Y into
328 * the R component, while plane 1 is ARGB/ABGR and samples YUYV/UYVY
329 * clusters and places pairs and places U into the G component and
330 * V into A. This lets the texture sampler interpolate the Y
331 * components correctly when sampling from plane 0, and interpolate
332 * U and V correctly when sampling from plane 1. */
333 { DRM_FORMAT_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
334 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
335 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
336 { DRM_FORMAT_UYVY
, __DRI_IMAGE_COMPONENTS_Y_UXVX
, 2,
337 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
338 { 0, 1, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } }
341 static const struct {
344 } supported_modifiers
[] = {
345 { .modifier
= DRM_FORMAT_MOD_LINEAR
, .since_gen
= 1 },
346 { .modifier
= I915_FORMAT_MOD_X_TILED
, .since_gen
= 1 },
347 { .modifier
= I915_FORMAT_MOD_Y_TILED
, .since_gen
= 6 },
348 { .modifier
= I915_FORMAT_MOD_Y_TILED_CCS
, .since_gen
= 9 },
352 modifier_is_supported(const struct gen_device_info
*devinfo
,
353 const struct intel_image_format
*fmt
, int dri_format
,
356 const struct isl_drm_modifier_info
*modinfo
=
357 isl_drm_modifier_get_info(modifier
);
360 /* ISL had better know about the modifier */
364 if (modinfo
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
365 /* If INTEL_DEBUG=norbc is set, don't support any CCS_E modifiers */
366 if (unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
))
369 /* CCS_E is not supported for planar images */
370 if (fmt
&& fmt
->nplanes
> 1)
374 assert(dri_format
== 0);
375 dri_format
= fmt
->planes
[0].dri_format
;
378 mesa_format format
= driImageFormatToGLFormat(dri_format
);
379 /* Whether or not we support compression is based on the RGBA non-sRGB
380 * version of the format.
382 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
383 format
= _mesa_get_srgb_format_linear(format
);
384 if (!isl_format_supports_ccs_e(devinfo
,
385 brw_isl_format_for_mesa_format(format
)))
389 for (i
= 0; i
< ARRAY_SIZE(supported_modifiers
); i
++) {
390 if (supported_modifiers
[i
].modifier
!= modifier
)
393 return supported_modifiers
[i
].since_gen
<= devinfo
->gen
;
400 tiling_to_modifier(uint32_t tiling
)
402 static const uint64_t map
[] = {
403 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
404 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
405 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
408 assert(tiling
< ARRAY_SIZE(map
));
414 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
416 uint32_t tiling
, swizzle
;
417 brw_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
419 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
420 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
421 func
, image
->offset
);
425 static const struct intel_image_format
*
426 intel_image_format_lookup(int fourcc
)
428 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
429 if (intel_image_formats
[i
].fourcc
== fourcc
)
430 return &intel_image_formats
[i
];
437 intel_image_get_fourcc(__DRIimage
*image
, int *fourcc
)
439 if (image
->planar_format
) {
440 *fourcc
= image
->planar_format
->fourcc
;
444 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
445 if (intel_image_formats
[i
].planes
[0].dri_format
== image
->dri_format
) {
446 *fourcc
= intel_image_formats
[i
].fourcc
;
454 intel_allocate_image(struct intel_screen
*screen
, int dri_format
,
459 image
= calloc(1, sizeof *image
);
463 image
->screen
= screen
;
464 image
->dri_format
= dri_format
;
467 image
->format
= driImageFormatToGLFormat(dri_format
);
468 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
469 image
->format
== MESA_FORMAT_NONE
) {
474 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
475 image
->data
= loaderPrivate
;
481 * Sets up a DRIImage structure to point to a slice out of a miptree.
484 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
485 struct intel_mipmap_tree
*mt
, GLuint level
,
488 intel_miptree_make_shareable(brw
, mt
);
490 intel_miptree_check_level_layer(mt
, level
, zoffset
);
492 image
->width
= minify(mt
->surf
.phys_level0_sa
.width
,
493 level
- mt
->first_level
);
494 image
->height
= minify(mt
->surf
.phys_level0_sa
.height
,
495 level
- mt
->first_level
);
496 image
->pitch
= mt
->surf
.row_pitch_B
;
498 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
502 brw_bo_unreference(image
->bo
);
504 brw_bo_reference(mt
->bo
);
508 intel_create_image_from_name(__DRIscreen
*dri_screen
,
509 int width
, int height
, int format
,
510 int name
, int pitch
, void *loaderPrivate
)
512 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
516 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
520 if (image
->format
== MESA_FORMAT_NONE
)
523 cpp
= _mesa_get_format_bytes(image
->format
);
525 image
->width
= width
;
526 image
->height
= height
;
527 image
->pitch
= pitch
* cpp
;
528 image
->bo
= brw_bo_gem_create_from_name(screen
->bufmgr
, "image",
534 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
540 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
541 int renderbuffer
, void *loaderPrivate
)
544 struct brw_context
*brw
= context
->driverPrivate
;
545 struct gl_context
*ctx
= &brw
->ctx
;
546 struct gl_renderbuffer
*rb
;
547 struct intel_renderbuffer
*irb
;
549 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
551 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
555 irb
= intel_renderbuffer(rb
);
556 intel_miptree_make_shareable(brw
, irb
->mt
);
557 image
= calloc(1, sizeof *image
);
561 image
->internal_format
= rb
->InternalFormat
;
562 image
->format
= rb
->Format
;
563 image
->modifier
= tiling_to_modifier(
564 isl_tiling_to_i915_tiling(irb
->mt
->surf
.tiling
));
566 image
->data
= loaderPrivate
;
567 brw_bo_unreference(image
->bo
);
568 image
->bo
= irb
->mt
->bo
;
569 brw_bo_reference(irb
->mt
->bo
);
570 image
->width
= rb
->Width
;
571 image
->height
= rb
->Height
;
572 image
->pitch
= irb
->mt
->surf
.row_pitch_B
;
573 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
574 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
576 rb
->NeedsFinishRenderTexture
= true;
581 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
582 unsigned texture
, int zoffset
,
588 struct brw_context
*brw
= context
->driverPrivate
;
589 struct gl_texture_object
*obj
;
590 struct intel_texture_object
*iobj
;
593 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
594 if (!obj
|| obj
->Target
!= target
) {
595 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
599 if (target
== GL_TEXTURE_CUBE_MAP
)
602 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
603 iobj
= intel_texture_object(obj
);
604 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
605 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
609 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
610 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
614 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
615 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
618 image
= calloc(1, sizeof *image
);
620 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
624 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
625 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
626 image
->modifier
= tiling_to_modifier(
627 isl_tiling_to_i915_tiling(iobj
->mt
->surf
.tiling
));
628 image
->data
= loaderPrivate
;
629 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
630 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
631 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
632 image
->planar_format
= iobj
->planar_format
;
633 if (image
->dri_format
== __DRI_IMAGE_FORMAT_NONE
) {
634 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
639 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
644 intel_destroy_image(__DRIimage
*image
)
646 brw_bo_unreference(image
->bo
);
650 enum modifier_priority
{
651 MODIFIER_PRIORITY_INVALID
= 0,
652 MODIFIER_PRIORITY_LINEAR
,
655 MODIFIER_PRIORITY_Y_CCS
,
658 const uint64_t priority_to_modifier
[] = {
659 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
660 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
661 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
662 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
663 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
667 select_best_modifier(struct gen_device_info
*devinfo
,
669 const uint64_t *modifiers
,
670 const unsigned count
)
672 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
674 for (int i
= 0; i
< count
; i
++) {
675 if (!modifier_is_supported(devinfo
, NULL
, dri_format
, modifiers
[i
]))
678 switch (modifiers
[i
]) {
679 case I915_FORMAT_MOD_Y_TILED_CCS
:
680 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
682 case I915_FORMAT_MOD_Y_TILED
:
683 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
685 case I915_FORMAT_MOD_X_TILED
:
686 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
688 case DRM_FORMAT_MOD_LINEAR
:
689 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
691 case DRM_FORMAT_MOD_INVALID
:
697 return priority_to_modifier
[prio
];
701 intel_create_image_common(__DRIscreen
*dri_screen
,
702 int width
, int height
, int format
,
704 const uint64_t *modifiers
,
709 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
710 uint64_t modifier
= DRM_FORMAT_MOD_INVALID
;
713 /* Callers of this may specify a modifier, or a dri usage, but not both. The
714 * newer modifier interface deprecates the older usage flags.
716 assert(!(use
&& count
));
718 if (use
& __DRI_IMAGE_USE_CURSOR
) {
719 if (width
!= 64 || height
!= 64)
721 modifier
= DRM_FORMAT_MOD_LINEAR
;
724 if (use
& __DRI_IMAGE_USE_LINEAR
)
725 modifier
= DRM_FORMAT_MOD_LINEAR
;
727 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
729 /* User requested specific modifiers */
730 modifier
= select_best_modifier(&screen
->devinfo
, format
,
732 if (modifier
== DRM_FORMAT_MOD_INVALID
)
735 /* Historically, X-tiled was the default, and so lack of modifier means
738 modifier
= I915_FORMAT_MOD_X_TILED
;
742 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
746 const struct isl_drm_modifier_info
*mod_info
=
747 isl_drm_modifier_get_info(modifier
);
749 struct isl_surf surf
;
750 ok
= isl_surf_init(&screen
->isl_dev
, &surf
,
751 .dim
= ISL_SURF_DIM_2D
,
752 .format
= brw_isl_format_for_mesa_format(image
->format
),
759 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
|
760 ISL_SURF_USAGE_TEXTURE_BIT
|
761 ISL_SURF_USAGE_STORAGE_BIT
|
762 ((use
& __DRI_IMAGE_USE_SCANOUT
) ?
763 ISL_SURF_USAGE_DISPLAY_BIT
: 0),
764 .tiling_flags
= (1 << mod_info
->tiling
));
771 struct isl_surf aux_surf
= {0,};
772 if (mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
773 ok
= isl_surf_get_ccs_surf(&screen
->isl_dev
, &surf
, &aux_surf
, NULL
, 0);
779 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
);
783 /* We request that the bufmgr zero the buffer for us for two reasons:
785 * 1) If a buffer gets re-used from the pool, we don't want to leak random
786 * garbage from our process to some other.
788 * 2) For images with CCS_E, we want to ensure that the CCS starts off in
789 * a valid state. A CCS value of 0 indicates that the given block is
790 * in the pass-through state which is what we want.
792 image
->bo
= brw_bo_alloc_tiled(screen
->bufmgr
, "image",
793 surf
.size_B
+ aux_surf
.size_B
,
795 isl_tiling_to_i915_tiling(mod_info
->tiling
),
796 surf
.row_pitch_B
, BO_ALLOC_ZEROED
);
797 if (image
->bo
== NULL
) {
801 image
->width
= width
;
802 image
->height
= height
;
803 image
->pitch
= surf
.row_pitch_B
;
804 image
->modifier
= modifier
;
806 if (aux_surf
.size_B
) {
807 image
->aux_offset
= surf
.size_B
;
808 image
->aux_pitch
= aux_surf
.row_pitch_B
;
809 image
->aux_size
= aux_surf
.size_B
;
816 intel_create_image(__DRIscreen
*dri_screen
,
817 int width
, int height
, int format
,
821 return intel_create_image_common(dri_screen
, width
, height
, format
, use
, NULL
, 0,
826 intel_map_image(__DRIcontext
*context
, __DRIimage
*image
,
827 int x0
, int y0
, int width
, int height
,
828 unsigned int flags
, int *stride
, void **map_info
)
830 struct brw_context
*brw
= NULL
;
831 struct brw_bo
*bo
= NULL
;
832 void *raw_data
= NULL
;
837 if (!context
|| !image
|| !stride
|| !map_info
|| *map_info
)
840 if (x0
< 0 || x0
>= image
->width
|| width
> image
->width
- x0
)
843 if (y0
< 0 || y0
>= image
->height
|| height
> image
->height
- y0
)
846 if (flags
& MAP_INTERNAL_MASK
)
849 brw
= context
->driverPrivate
;
855 /* DRI flags and GL_MAP.*_BIT flags are the same, so just pass them on. */
856 raw_data
= brw_bo_map(brw
, bo
, flags
);
860 _mesa_get_format_block_size(image
->format
, &pix_w
, &pix_h
);
861 pix_bytes
= _mesa_get_format_bytes(image
->format
);
865 assert(pix_bytes
> 0);
867 raw_data
+= (x0
/ pix_w
) * pix_bytes
+ (y0
/ pix_h
) * image
->pitch
;
869 brw_bo_reference(bo
);
871 *stride
= image
->pitch
;
878 intel_unmap_image(__DRIcontext
*context
, __DRIimage
*image
, void *map_info
)
880 struct brw_bo
*bo
= map_info
;
883 brw_bo_unreference(bo
);
887 intel_create_image_with_modifiers(__DRIscreen
*dri_screen
,
888 int width
, int height
, int format
,
889 const uint64_t *modifiers
,
890 const unsigned count
,
893 return intel_create_image_common(dri_screen
, width
, height
, format
, 0,
894 modifiers
, count
, loaderPrivate
);
898 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
901 case __DRI_IMAGE_ATTRIB_STRIDE
:
902 *value
= image
->pitch
;
904 case __DRI_IMAGE_ATTRIB_HANDLE
:
905 *value
= brw_bo_export_gem_handle(image
->bo
);
907 case __DRI_IMAGE_ATTRIB_NAME
:
908 return !brw_bo_flink(image
->bo
, (uint32_t *) value
);
909 case __DRI_IMAGE_ATTRIB_FORMAT
:
910 *value
= image
->dri_format
;
912 case __DRI_IMAGE_ATTRIB_WIDTH
:
913 *value
= image
->width
;
915 case __DRI_IMAGE_ATTRIB_HEIGHT
:
916 *value
= image
->height
;
918 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
919 if (image
->planar_format
== NULL
)
921 *value
= image
->planar_format
->components
;
923 case __DRI_IMAGE_ATTRIB_FD
:
924 return !brw_bo_gem_export_to_prime(image
->bo
, value
);
925 case __DRI_IMAGE_ATTRIB_FOURCC
:
926 return intel_image_get_fourcc(image
, value
);
927 case __DRI_IMAGE_ATTRIB_NUM_PLANES
:
928 if (isl_drm_modifier_has_aux(image
->modifier
)) {
929 assert(!image
->planar_format
|| image
->planar_format
->nplanes
== 1);
931 } else if (image
->planar_format
) {
932 *value
= image
->planar_format
->nplanes
;
937 case __DRI_IMAGE_ATTRIB_OFFSET
:
938 *value
= image
->offset
;
940 case __DRI_IMAGE_ATTRIB_MODIFIER_LOWER
:
941 *value
= (image
->modifier
& 0xffffffff);
943 case __DRI_IMAGE_ATTRIB_MODIFIER_UPPER
:
944 *value
= ((image
->modifier
>> 32) & 0xffffffff);
953 intel_query_format_modifier_attribs(__DRIscreen
*dri_screen
,
954 uint32_t fourcc
, uint64_t modifier
,
955 int attrib
, uint64_t *value
)
957 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
958 const struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
960 if (!modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
964 case __DRI_IMAGE_FORMAT_MODIFIER_ATTRIB_PLANE_COUNT
:
965 *value
= isl_drm_modifier_has_aux(modifier
) ? 2 : f
->nplanes
;
974 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
978 image
= calloc(1, sizeof *image
);
982 brw_bo_reference(orig_image
->bo
);
983 image
->screen
= orig_image
->screen
;
984 image
->bo
= orig_image
->bo
;
985 image
->internal_format
= orig_image
->internal_format
;
986 image
->planar_format
= orig_image
->planar_format
;
987 image
->dri_format
= orig_image
->dri_format
;
988 image
->format
= orig_image
->format
;
989 image
->modifier
= orig_image
->modifier
;
990 image
->offset
= orig_image
->offset
;
991 image
->width
= orig_image
->width
;
992 image
->height
= orig_image
->height
;
993 image
->pitch
= orig_image
->pitch
;
994 image
->tile_x
= orig_image
->tile_x
;
995 image
->tile_y
= orig_image
->tile_y
;
996 image
->has_depthstencil
= orig_image
->has_depthstencil
;
997 image
->data
= loaderPrivate
;
998 image
->aux_offset
= orig_image
->aux_offset
;
999 image
->aux_pitch
= orig_image
->aux_pitch
;
1001 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
1002 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
1008 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
1010 if (use
& __DRI_IMAGE_USE_CURSOR
) {
1011 if (image
->width
!= 64 || image
->height
!= 64)
1019 intel_create_image_from_names(__DRIscreen
*dri_screen
,
1020 int width
, int height
, int fourcc
,
1021 int *names
, int num_names
,
1022 int *strides
, int *offsets
,
1023 void *loaderPrivate
)
1025 const struct intel_image_format
*f
= NULL
;
1029 if (dri_screen
== NULL
|| names
== NULL
|| num_names
!= 1)
1032 f
= intel_image_format_lookup(fourcc
);
1036 image
= intel_create_image_from_name(dri_screen
, width
, height
,
1037 __DRI_IMAGE_FORMAT_NONE
,
1038 names
[0], strides
[0],
1044 image
->planar_format
= f
;
1045 for (i
= 0; i
< f
->nplanes
; i
++) {
1046 index
= f
->planes
[i
].buffer_index
;
1047 image
->offsets
[index
] = offsets
[index
];
1048 image
->strides
[index
] = strides
[index
];
1055 intel_create_image_from_fds_common(__DRIscreen
*dri_screen
,
1056 int width
, int height
, int fourcc
,
1057 uint64_t modifier
, int *fds
, int num_fds
,
1058 int *strides
, int *offsets
,
1059 void *loaderPrivate
)
1061 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1062 const struct intel_image_format
*f
;
1067 if (fds
== NULL
|| num_fds
< 1)
1070 f
= intel_image_format_lookup(fourcc
);
1074 if (modifier
!= DRM_FORMAT_MOD_INVALID
&&
1075 !modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
1078 if (f
->nplanes
== 1)
1079 image
= intel_allocate_image(screen
, f
->planes
[0].dri_format
,
1082 image
= intel_allocate_image(screen
, __DRI_IMAGE_FORMAT_NONE
,
1088 image
->width
= width
;
1089 image
->height
= height
;
1090 image
->pitch
= strides
[0];
1092 image
->planar_format
= f
;
1094 if (modifier
!= DRM_FORMAT_MOD_INVALID
) {
1095 const struct isl_drm_modifier_info
*mod_info
=
1096 isl_drm_modifier_get_info(modifier
);
1097 uint32_t tiling
= isl_tiling_to_i915_tiling(mod_info
->tiling
);
1098 image
->bo
= brw_bo_gem_create_from_prime_tiled(screen
->bufmgr
, fds
[0],
1099 tiling
, strides
[0]);
1101 image
->bo
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[0]);
1104 if (image
->bo
== NULL
) {
1109 /* We only support all planes from the same bo.
1110 * brw_bo_gem_create_from_prime() should return the same pointer for all
1111 * fds received here */
1112 for (i
= 1; i
< num_fds
; i
++) {
1113 struct brw_bo
*aux
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[i
]);
1114 brw_bo_unreference(aux
);
1115 if (aux
!= image
->bo
) {
1116 brw_bo_unreference(image
->bo
);
1122 if (modifier
!= DRM_FORMAT_MOD_INVALID
)
1123 image
->modifier
= modifier
;
1125 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
1127 const struct isl_drm_modifier_info
*mod_info
=
1128 isl_drm_modifier_get_info(image
->modifier
);
1131 struct isl_surf surf
;
1132 for (i
= 0; i
< f
->nplanes
; i
++) {
1133 index
= f
->planes
[i
].buffer_index
;
1134 image
->offsets
[index
] = offsets
[index
];
1135 image
->strides
[index
] = strides
[index
];
1137 mesa_format format
= driImageFormatToGLFormat(f
->planes
[i
].dri_format
);
1138 /* The images we will create are actually based on the RGBA non-sRGB
1139 * version of the format.
1141 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1142 format
= _mesa_get_srgb_format_linear(format
);
1144 ok
= isl_surf_init(&screen
->isl_dev
, &surf
,
1145 .dim
= ISL_SURF_DIM_2D
,
1146 .format
= brw_isl_format_for_mesa_format(format
),
1147 .width
= image
->width
>> f
->planes
[i
].width_shift
,
1148 .height
= image
->height
>> f
->planes
[i
].height_shift
,
1153 .row_pitch_B
= strides
[index
],
1154 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1155 ISL_SURF_USAGE_TEXTURE_BIT
|
1156 ISL_SURF_USAGE_STORAGE_BIT
,
1157 .tiling_flags
= (1 << mod_info
->tiling
));
1159 brw_bo_unreference(image
->bo
);
1164 const int end
= offsets
[index
] + surf
.size_B
;
1169 if (mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1170 /* Even though we initialize surf in the loop above, we know that
1171 * anything with CCS_E will have exactly one plane so surf is properly
1172 * initialized when we get here.
1174 assert(f
->nplanes
== 1);
1176 image
->aux_offset
= offsets
[1];
1177 image
->aux_pitch
= strides
[1];
1179 /* Scanout hardware requires that the CCS be placed after the main
1180 * surface in memory. We consider any CCS that is placed any earlier in
1181 * memory to be invalid and reject it.
1183 * At some point in the future, this restriction may be relaxed if the
1184 * hardware becomes less strict but we may need a new modifier for that.
1187 if (image
->aux_offset
< size
) {
1188 brw_bo_unreference(image
->bo
);
1193 struct isl_surf aux_surf
= {0,};
1194 ok
= isl_surf_get_ccs_surf(&screen
->isl_dev
, &surf
, &aux_surf
, NULL
,
1197 brw_bo_unreference(image
->bo
);
1202 image
->aux_size
= aux_surf
.size_B
;
1204 const int end
= image
->aux_offset
+ aux_surf
.size_B
;
1208 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
);
1211 /* Check that the requested image actually fits within the BO. 'size'
1212 * is already relative to the offsets, so we don't need to add that. */
1213 if (image
->bo
->size
== 0) {
1214 image
->bo
->size
= size
;
1215 } else if (size
> image
->bo
->size
) {
1216 brw_bo_unreference(image
->bo
);
1221 if (f
->nplanes
== 1) {
1222 image
->offset
= image
->offsets
[0];
1223 intel_image_warn_if_unaligned(image
, __func__
);
1230 intel_create_image_from_fds(__DRIscreen
*dri_screen
,
1231 int width
, int height
, int fourcc
,
1232 int *fds
, int num_fds
, int *strides
, int *offsets
,
1233 void *loaderPrivate
)
1235 return intel_create_image_from_fds_common(dri_screen
, width
, height
, fourcc
,
1236 DRM_FORMAT_MOD_INVALID
,
1237 fds
, num_fds
, strides
, offsets
,
1242 intel_create_image_from_dma_bufs2(__DRIscreen
*dri_screen
,
1243 int width
, int height
,
1244 int fourcc
, uint64_t modifier
,
1245 int *fds
, int num_fds
,
1246 int *strides
, int *offsets
,
1247 enum __DRIYUVColorSpace yuv_color_space
,
1248 enum __DRISampleRange sample_range
,
1249 enum __DRIChromaSiting horizontal_siting
,
1250 enum __DRIChromaSiting vertical_siting
,
1252 void *loaderPrivate
)
1255 const struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
1258 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
1262 image
= intel_create_image_from_fds_common(dri_screen
, width
, height
,
1264 fds
, num_fds
, strides
, offsets
,
1268 * Invalid parameters and any inconsistencies between are assumed to be
1269 * checked by the caller. Therefore besides unsupported formats one can fail
1270 * only in allocation.
1273 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
1277 image
->yuv_color_space
= yuv_color_space
;
1278 image
->sample_range
= sample_range
;
1279 image
->horizontal_siting
= horizontal_siting
;
1280 image
->vertical_siting
= vertical_siting
;
1281 image
->imported_dmabuf
= true;
1283 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
1288 intel_create_image_from_dma_bufs(__DRIscreen
*dri_screen
,
1289 int width
, int height
, int fourcc
,
1290 int *fds
, int num_fds
,
1291 int *strides
, int *offsets
,
1292 enum __DRIYUVColorSpace yuv_color_space
,
1293 enum __DRISampleRange sample_range
,
1294 enum __DRIChromaSiting horizontal_siting
,
1295 enum __DRIChromaSiting vertical_siting
,
1297 void *loaderPrivate
)
1299 return intel_create_image_from_dma_bufs2(dri_screen
, width
, height
,
1300 fourcc
, DRM_FORMAT_MOD_INVALID
,
1301 fds
, num_fds
, strides
, offsets
,
1311 intel_image_format_is_supported(const struct gen_device_info
*devinfo
,
1312 const struct intel_image_format
*fmt
)
1314 /* Currently, all formats with an intel_image_format are available on all
1315 * platforms so there's really nothing to check there.
1319 if (fmt
->nplanes
== 1) {
1320 mesa_format format
= driImageFormatToGLFormat(fmt
->planes
[0].dri_format
);
1321 /* The images we will create are actually based on the RGBA non-sRGB
1322 * version of the format.
1324 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1325 format
= _mesa_get_srgb_format_linear(format
);
1326 enum isl_format isl_format
= brw_isl_format_for_mesa_format(format
);
1327 assert(isl_format_supports_rendering(devinfo
, isl_format
));
1335 intel_query_dma_buf_formats(__DRIscreen
*_screen
, int max
,
1336 int *formats
, int *count
)
1338 struct intel_screen
*screen
= _screen
->driverPrivate
;
1339 int num_formats
= 0, i
;
1341 for (i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
1342 /* These formats are valid DRI formats but do not exist in drm_fourcc.h
1343 * in the Linux kernel. We don't want to accidentally advertise them
1344 * them through the EGL layer.
1346 if (intel_image_formats
[i
].fourcc
== __DRI_IMAGE_FOURCC_SARGB8888
||
1347 intel_image_formats
[i
].fourcc
== __DRI_IMAGE_FOURCC_SABGR8888
||
1348 intel_image_formats
[i
].fourcc
== __DRI_IMAGE_FOURCC_SXRGB8888
)
1351 if (!intel_image_format_is_supported(&screen
->devinfo
,
1352 &intel_image_formats
[i
]))
1359 formats
[num_formats
- 1] = intel_image_formats
[i
].fourcc
;
1360 if (num_formats
>= max
)
1364 *count
= num_formats
;
1369 intel_query_dma_buf_modifiers(__DRIscreen
*_screen
, int fourcc
, int max
,
1370 uint64_t *modifiers
,
1371 unsigned int *external_only
,
1374 struct intel_screen
*screen
= _screen
->driverPrivate
;
1375 const struct intel_image_format
*f
;
1376 int num_mods
= 0, i
;
1378 f
= intel_image_format_lookup(fourcc
);
1382 if (!intel_image_format_is_supported(&screen
->devinfo
, f
))
1385 for (i
= 0; i
< ARRAY_SIZE(supported_modifiers
); i
++) {
1386 uint64_t modifier
= supported_modifiers
[i
].modifier
;
1387 if (!modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
1394 modifiers
[num_mods
- 1] = modifier
;
1395 if (num_mods
>= max
)
1399 if (external_only
!= NULL
) {
1400 for (i
= 0; i
< num_mods
&& i
< max
; i
++) {
1401 if (f
->components
== __DRI_IMAGE_COMPONENTS_Y_U_V
||
1402 f
->components
== __DRI_IMAGE_COMPONENTS_Y_UV
||
1403 f
->components
== __DRI_IMAGE_COMPONENTS_AYUV
||
1404 f
->components
== __DRI_IMAGE_COMPONENTS_XYUV
||
1405 f
->components
== __DRI_IMAGE_COMPONENTS_Y_XUXV
||
1406 f
->components
== __DRI_IMAGE_COMPONENTS_Y_UXVX
) {
1407 external_only
[i
] = GL_TRUE
;
1410 external_only
[i
] = GL_FALSE
;
1420 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
1422 int width
, height
, offset
, stride
, size
, dri_format
;
1428 width
= parent
->width
;
1429 height
= parent
->height
;
1431 const struct intel_image_format
*f
= parent
->planar_format
;
1433 if (f
&& plane
< f
->nplanes
) {
1434 /* Use the planar format definition. */
1435 width
>>= f
->planes
[plane
].width_shift
;
1436 height
>>= f
->planes
[plane
].height_shift
;
1437 dri_format
= f
->planes
[plane
].dri_format
;
1438 int index
= f
->planes
[plane
].buffer_index
;
1439 offset
= parent
->offsets
[index
];
1440 stride
= parent
->strides
[index
];
1441 size
= height
* stride
;
1442 } else if (plane
== 0) {
1443 /* The only plane of a non-planar image: copy the parent definition
1445 dri_format
= parent
->dri_format
;
1446 offset
= parent
->offset
;
1447 stride
= parent
->pitch
;
1448 size
= height
* stride
;
1449 } else if (plane
== 1 && parent
->modifier
!= DRM_FORMAT_MOD_INVALID
&&
1450 isl_drm_modifier_has_aux(parent
->modifier
)) {
1451 /* Auxiliary plane */
1452 dri_format
= parent
->dri_format
;
1453 offset
= parent
->aux_offset
;
1454 stride
= parent
->aux_pitch
;
1455 size
= parent
->aux_size
;
1460 if (offset
+ size
> parent
->bo
->size
) {
1461 _mesa_warning(NULL
, "intel_from_planar: subimage out of bounds");
1465 image
= intel_allocate_image(parent
->screen
, dri_format
, loaderPrivate
);
1469 image
->bo
= parent
->bo
;
1470 brw_bo_reference(parent
->bo
);
1471 image
->modifier
= parent
->modifier
;
1473 image
->width
= width
;
1474 image
->height
= height
;
1475 image
->pitch
= stride
;
1476 image
->offset
= offset
;
1478 intel_image_warn_if_unaligned(image
, __func__
);
1483 static const __DRIimageExtension intelImageExtension
= {
1484 .base
= { __DRI_IMAGE
, 16 },
1486 .createImageFromName
= intel_create_image_from_name
,
1487 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
1488 .destroyImage
= intel_destroy_image
,
1489 .createImage
= intel_create_image
,
1490 .queryImage
= intel_query_image
,
1491 .dupImage
= intel_dup_image
,
1492 .validateUsage
= intel_validate_usage
,
1493 .createImageFromNames
= intel_create_image_from_names
,
1494 .fromPlanar
= intel_from_planar
,
1495 .createImageFromTexture
= intel_create_image_from_texture
,
1496 .createImageFromFds
= intel_create_image_from_fds
,
1497 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
,
1499 .getCapabilities
= NULL
,
1500 .mapImage
= intel_map_image
,
1501 .unmapImage
= intel_unmap_image
,
1502 .createImageWithModifiers
= intel_create_image_with_modifiers
,
1503 .createImageFromDmaBufs2
= intel_create_image_from_dma_bufs2
,
1504 .queryDmaBufFormats
= intel_query_dma_buf_formats
,
1505 .queryDmaBufModifiers
= intel_query_dma_buf_modifiers
,
1506 .queryDmaBufFormatModifierAttribs
= intel_query_format_modifier_attribs
,
1510 brw_query_renderer_integer(__DRIscreen
*dri_screen
,
1511 int param
, unsigned int *value
)
1513 const struct intel_screen
*const screen
=
1514 (struct intel_screen
*) dri_screen
->driverPrivate
;
1517 case __DRI2_RENDERER_VENDOR_ID
:
1520 case __DRI2_RENDERER_DEVICE_ID
:
1521 value
[0] = screen
->deviceID
;
1523 case __DRI2_RENDERER_ACCELERATED
:
1526 case __DRI2_RENDERER_VIDEO_MEMORY
: {
1527 /* Once a batch uses more than 75% of the maximum mappable size, we
1528 * assume that there's some fragmentation, and we start doing extra
1529 * flushing, etc. That's the big cliff apps will care about.
1531 const unsigned gpu_mappable_megabytes
=
1532 screen
->aperture_threshold
/ (1024 * 1024);
1534 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
1535 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
1537 if (system_memory_pages
<= 0 || system_page_size
<= 0)
1540 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
1541 * (uint64_t) system_page_size
;
1543 const unsigned system_memory_megabytes
=
1544 (unsigned) (system_memory_bytes
/ (1024 * 1024));
1546 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
1549 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
1552 case __DRI2_RENDERER_HAS_TEXTURE_3D
:
1555 case __DRI2_RENDERER_HAS_CONTEXT_PRIORITY
:
1557 if (brw_hw_context_set_priority(screen
->bufmgr
,
1558 0, GEN_CONTEXT_HIGH_PRIORITY
) == 0)
1559 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_HIGH
;
1560 if (brw_hw_context_set_priority(screen
->bufmgr
,
1561 0, GEN_CONTEXT_LOW_PRIORITY
) == 0)
1562 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_LOW
;
1563 /* reset to default last, just in case */
1564 if (brw_hw_context_set_priority(screen
->bufmgr
,
1565 0, GEN_CONTEXT_MEDIUM_PRIORITY
) == 0)
1566 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_MEDIUM
;
1568 case __DRI2_RENDERER_HAS_FRAMEBUFFER_SRGB
:
1572 return driQueryRendererIntegerCommon(dri_screen
, param
, value
);
1579 brw_query_renderer_string(__DRIscreen
*dri_screen
,
1580 int param
, const char **value
)
1582 const struct intel_screen
*screen
=
1583 (struct intel_screen
*) dri_screen
->driverPrivate
;
1586 case __DRI2_RENDERER_VENDOR_ID
:
1587 value
[0] = brw_vendor_string
;
1589 case __DRI2_RENDERER_DEVICE_ID
:
1590 value
[0] = brw_get_renderer_string(screen
);
1600 brw_set_cache_funcs(__DRIscreen
*dri_screen
,
1601 __DRIblobCacheSet set
, __DRIblobCacheGet get
)
1603 const struct intel_screen
*const screen
=
1604 (struct intel_screen
*) dri_screen
->driverPrivate
;
1606 if (!screen
->disk_cache
)
1609 disk_cache_set_callbacks(screen
->disk_cache
, set
, get
);
1612 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
1613 .base
= { __DRI2_RENDERER_QUERY
, 1 },
1615 .queryInteger
= brw_query_renderer_integer
,
1616 .queryString
= brw_query_renderer_string
1619 static const __DRIrobustnessExtension dri2Robustness
= {
1620 .base
= { __DRI2_ROBUSTNESS
, 1 }
1623 static const __DRI2blobExtension intelBlobExtension
= {
1624 .base
= { __DRI2_BLOB
, 1 },
1625 .set_cache_funcs
= brw_set_cache_funcs
1628 static const __DRImutableRenderBufferDriverExtension intelMutableRenderBufferExtension
= {
1629 .base
= { __DRI_MUTABLE_RENDER_BUFFER_DRIVER
, 1 },
1632 static const __DRIextension
*screenExtensions
[] = {
1633 &intelTexBufferExtension
.base
,
1634 &intelFenceExtension
.base
,
1635 &intelFlushExtension
.base
,
1636 &intelImageExtension
.base
,
1637 &intelRendererQueryExtension
.base
,
1638 &intelMutableRenderBufferExtension
.base
,
1639 &dri2ConfigQueryExtension
.base
,
1640 &dri2NoErrorExtension
.base
,
1641 &intelBlobExtension
.base
,
1645 static const __DRIextension
*intelRobustScreenExtensions
[] = {
1646 &intelTexBufferExtension
.base
,
1647 &intelFenceExtension
.base
,
1648 &intelFlushExtension
.base
,
1649 &intelImageExtension
.base
,
1650 &intelRendererQueryExtension
.base
,
1651 &intelMutableRenderBufferExtension
.base
,
1652 &dri2ConfigQueryExtension
.base
,
1653 &dri2Robustness
.base
,
1654 &dri2NoErrorExtension
.base
,
1655 &intelBlobExtension
.base
,
1660 intel_get_param(struct intel_screen
*screen
, int param
, int *value
)
1663 struct drm_i915_getparam gp
;
1665 memset(&gp
, 0, sizeof(gp
));
1669 if (drmIoctl(screen
->fd
, DRM_IOCTL_I915_GETPARAM
, &gp
) == -1) {
1672 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
1679 intel_get_boolean(struct intel_screen
*screen
, int param
)
1682 return (intel_get_param(screen
, param
, &value
) == 0) && value
;
1686 intel_get_integer(struct intel_screen
*screen
, int param
)
1690 if (intel_get_param(screen
, param
, &value
) == 0)
1697 intelDestroyScreen(__DRIscreen
* sPriv
)
1699 struct intel_screen
*screen
= sPriv
->driverPrivate
;
1701 brw_bufmgr_unref(screen
->bufmgr
);
1702 driDestroyOptionInfo(&screen
->optionCache
);
1704 disk_cache_destroy(screen
->disk_cache
);
1706 ralloc_free(screen
);
1707 sPriv
->driverPrivate
= NULL
;
1712 * Create a gl_framebuffer and attach it to __DRIdrawable::driverPrivate.
1714 *_This implements driDriverAPI::createNewDrawable, which the DRI layer calls
1715 * when creating a EGLSurface, GLXDrawable, or GLXPixmap. Despite the name,
1716 * this does not allocate GPU memory.
1719 intelCreateBuffer(__DRIscreen
*dri_screen
,
1720 __DRIdrawable
* driDrawPriv
,
1721 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
1723 struct intel_renderbuffer
*rb
;
1724 struct intel_screen
*screen
= (struct intel_screen
*)
1725 dri_screen
->driverPrivate
;
1726 mesa_format rgbFormat
;
1727 unsigned num_samples
=
1728 intel_quantize_num_samples(screen
, mesaVis
->samples
);
1733 struct gl_framebuffer
*fb
= CALLOC_STRUCT(gl_framebuffer
);
1737 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
1739 if (screen
->winsys_msaa_samples_override
!= -1) {
1740 num_samples
= screen
->winsys_msaa_samples_override
;
1741 fb
->Visual
.samples
= num_samples
;
1744 if (mesaVis
->redBits
== 16 && mesaVis
->alphaBits
> 0 && mesaVis
->floatMode
) {
1745 rgbFormat
= MESA_FORMAT_RGBA_FLOAT16
;
1746 } else if (mesaVis
->redBits
== 16 && mesaVis
->floatMode
) {
1747 rgbFormat
= MESA_FORMAT_RGBX_FLOAT16
;
1748 } else if (mesaVis
->redBits
== 10 && mesaVis
->alphaBits
> 0) {
1749 rgbFormat
= mesaVis
->redMask
== 0x3ff00000 ? MESA_FORMAT_B10G10R10A2_UNORM
1750 : MESA_FORMAT_R10G10B10A2_UNORM
;
1751 } else if (mesaVis
->redBits
== 10) {
1752 rgbFormat
= mesaVis
->redMask
== 0x3ff00000 ? MESA_FORMAT_B10G10R10X2_UNORM
1753 : MESA_FORMAT_R10G10B10X2_UNORM
;
1754 } else if (mesaVis
->redBits
== 5) {
1755 rgbFormat
= mesaVis
->redMask
== 0x1f ? MESA_FORMAT_R5G6B5_UNORM
1756 : MESA_FORMAT_B5G6R5_UNORM
;
1757 } else if (mesaVis
->alphaBits
== 0) {
1758 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8X8_SRGB
1759 : MESA_FORMAT_B8G8R8X8_SRGB
;
1760 fb
->Visual
.sRGBCapable
= true;
1761 } else if (mesaVis
->sRGBCapable
) {
1762 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1763 : MESA_FORMAT_B8G8R8A8_SRGB
;
1764 fb
->Visual
.sRGBCapable
= true;
1766 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1767 : MESA_FORMAT_B8G8R8A8_SRGB
;
1768 fb
->Visual
.sRGBCapable
= true;
1771 /* mesaVis->sRGBCapable was set, user is asking for sRGB */
1772 bool srgb_cap_set
= mesaVis
->redBits
>= 8 && mesaVis
->sRGBCapable
;
1774 /* setup the hardware-based renderbuffers */
1775 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1776 _mesa_attach_and_own_rb(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
1777 rb
->need_srgb
= srgb_cap_set
;
1779 if (mesaVis
->doubleBufferMode
) {
1780 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1781 _mesa_attach_and_own_rb(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
1782 rb
->need_srgb
= srgb_cap_set
;
1786 * Assert here that the gl_config has an expected depth/stencil bit
1787 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1788 * which constructs the advertised configs.)
1790 if (mesaVis
->depthBits
== 24) {
1791 assert(mesaVis
->stencilBits
== 8);
1793 if (screen
->devinfo
.has_hiz_and_separate_stencil
) {
1794 rb
= intel_create_private_renderbuffer(screen
,
1795 MESA_FORMAT_Z24_UNORM_X8_UINT
,
1797 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1798 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_S_UINT8
,
1800 _mesa_attach_and_own_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1803 * Use combined depth/stencil. Note that the renderbuffer is
1804 * attached to two attachment points.
1806 rb
= intel_create_private_renderbuffer(screen
,
1807 MESA_FORMAT_Z24_UNORM_S8_UINT
,
1809 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1810 _mesa_attach_and_reference_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1813 else if (mesaVis
->depthBits
== 16) {
1814 assert(mesaVis
->stencilBits
== 0);
1815 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_Z_UNORM16
,
1817 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1820 assert(mesaVis
->depthBits
== 0);
1821 assert(mesaVis
->stencilBits
== 0);
1824 /* now add any/all software-based renderbuffers we may need */
1825 _swrast_add_soft_renderbuffers(fb
,
1826 false, /* never sw color */
1827 false, /* never sw depth */
1828 false, /* never sw stencil */
1829 mesaVis
->accumRedBits
> 0,
1830 false, /* never sw alpha */
1831 false /* never sw aux */ );
1832 driDrawPriv
->driverPrivate
= fb
;
1838 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1840 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1842 _mesa_reference_framebuffer(&fb
, NULL
);
1846 intel_cs_timestamp_frequency(struct intel_screen
*screen
)
1848 /* We shouldn't need to update gen_device_info.timestamp_frequency prior to
1849 * gen10, PCI-id is enough to figure it out.
1851 assert(screen
->devinfo
.gen
>= 10);
1855 ret
= intel_get_param(screen
, I915_PARAM_CS_TIMESTAMP_FREQUENCY
,
1859 "Kernel 4.15 required to read the CS timestamp frequency.\n");
1863 screen
->devinfo
.timestamp_frequency
= freq
;
1867 intel_detect_sseu(struct intel_screen
*screen
)
1869 assert(screen
->devinfo
.gen
>= 8);
1872 screen
->subslice_total
= -1;
1873 screen
->eu_total
= -1;
1875 ret
= intel_get_param(screen
, I915_PARAM_SUBSLICE_TOTAL
,
1876 &screen
->subslice_total
);
1877 if (ret
< 0 && ret
!= -EINVAL
)
1880 ret
= intel_get_param(screen
,
1881 I915_PARAM_EU_TOTAL
, &screen
->eu_total
);
1882 if (ret
< 0 && ret
!= -EINVAL
)
1885 /* Without this information, we cannot get the right Braswell brandstrings,
1886 * and we have to use conservative numbers for GPGPU on many platforms, but
1887 * otherwise, things will just work.
1889 if (screen
->subslice_total
< 1 || screen
->eu_total
< 1)
1891 "Kernel 4.1 required to properly query GPU properties.\n");
1896 screen
->subslice_total
= -1;
1897 screen
->eu_total
= -1;
1898 _mesa_warning(NULL
, "Failed to query GPU properties (%s).\n", strerror(-ret
));
1902 intel_init_bufmgr(struct intel_screen
*screen
)
1904 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1906 if (getenv("INTEL_NO_HW") != NULL
)
1907 screen
->no_hw
= true;
1909 bool bo_reuse
= false;
1910 int bo_reuse_mode
= driQueryOptioni(&screen
->optionCache
, "bo_reuse");
1911 switch (bo_reuse_mode
) {
1912 case DRI_CONF_BO_REUSE_DISABLED
:
1914 case DRI_CONF_BO_REUSE_ALL
:
1919 screen
->bufmgr
= brw_bufmgr_get_for_fd(&screen
->devinfo
, dri_screen
->fd
, bo_reuse
);
1920 if (screen
->bufmgr
== NULL
) {
1921 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1922 __func__
, __LINE__
);
1925 screen
->fd
= brw_bufmgr_get_fd(screen
->bufmgr
);
1927 if (!intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_NO_RELOC
)) {
1928 fprintf(stderr
, "[%s: %u] Kernel 3.9 required.\n", __func__
, __LINE__
);
1936 intel_detect_swizzling(struct intel_screen
*screen
)
1938 /* Broadwell PRM says:
1940 * "Before Gen8, there was a historical configuration control field to
1941 * swizzle address bit[6] for in X/Y tiling modes. This was set in three
1942 * different places: TILECTL[1:0], ARB_MODE[5:4], and
1943 * DISP_ARB_CTL[14:13].
1945 * For Gen8 and subsequent generations, the swizzle fields are all
1946 * reserved, and the CPU's memory controller performs all address
1947 * swizzling modifications."
1949 if (screen
->devinfo
.gen
>= 8)
1952 uint32_t tiling
= I915_TILING_X
;
1953 uint32_t swizzle_mode
= 0;
1954 struct brw_bo
*buffer
=
1955 brw_bo_alloc_tiled(screen
->bufmgr
, "swizzle test", 32768,
1956 BRW_MEMZONE_OTHER
, tiling
, 512, 0);
1960 brw_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1961 brw_bo_unreference(buffer
);
1963 return swizzle_mode
!= I915_BIT_6_SWIZZLE_NONE
;
1967 intel_detect_timestamp(struct intel_screen
*screen
)
1969 uint64_t dummy
= 0, last
= 0;
1970 int upper
, lower
, loops
;
1972 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1973 * TIMESTAMP register being shifted and the low 32bits always zero.
1975 * More recent kernels offer an interface to read the full 36bits
1978 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &dummy
) == 0)
1981 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1982 * upper 32bits for a rapidly changing timestamp.
1984 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &last
))
1988 for (loops
= 0; loops
< 10; loops
++) {
1989 /* The TIMESTAMP should change every 80ns, so several round trips
1990 * through the kernel should be enough to advance it.
1992 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &dummy
))
1995 upper
+= (dummy
>> 32) != (last
>> 32);
1996 if (upper
> 1) /* beware 32bit counter overflow */
1997 return 2; /* upper dword holds the low 32bits of the timestamp */
1999 lower
+= (dummy
& 0xffffffff) != (last
& 0xffffffff);
2001 return 1; /* timestamp is unshifted */
2006 /* No advancement? No timestamp! */
2011 * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
2013 * Some combinations of hardware and kernel versions allow this feature,
2014 * while others don't. Instead of trying to enumerate every case, just
2015 * try and write a register and see if works.
2018 intel_detect_pipelined_register(struct intel_screen
*screen
,
2019 int reg
, uint32_t expected_value
, bool reset
)
2024 struct brw_bo
*results
, *bo
;
2026 uint32_t offset
= 0;
2028 bool success
= false;
2030 /* Create a zero'ed temporary buffer for reading our results */
2031 results
= brw_bo_alloc(screen
->bufmgr
, "registers", 4096, BRW_MEMZONE_OTHER
);
2032 if (results
== NULL
)
2035 bo
= brw_bo_alloc(screen
->bufmgr
, "batchbuffer", 4096, BRW_MEMZONE_OTHER
);
2039 map
= brw_bo_map(NULL
, bo
, MAP_WRITE
);
2045 /* Write the register. */
2046 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
2048 *batch
++ = expected_value
;
2050 /* Save the register's value back to the buffer. */
2051 *batch
++ = MI_STORE_REGISTER_MEM
| (3 - 2);
2053 struct drm_i915_gem_relocation_entry reloc
= {
2054 .offset
= (char *) batch
- (char *) map
,
2055 .delta
= offset
* sizeof(uint32_t),
2056 .target_handle
= results
->gem_handle
,
2057 .read_domains
= I915_GEM_DOMAIN_INSTRUCTION
,
2058 .write_domain
= I915_GEM_DOMAIN_INSTRUCTION
,
2060 *batch
++ = reloc
.presumed_offset
+ reloc
.delta
;
2062 /* And afterwards clear the register */
2064 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
2069 *batch
++ = MI_BATCH_BUFFER_END
;
2071 struct drm_i915_gem_exec_object2 exec_objects
[2] = {
2073 .handle
= results
->gem_handle
,
2076 .handle
= bo
->gem_handle
,
2077 .relocation_count
= 1,
2078 .relocs_ptr
= (uintptr_t) &reloc
,
2082 struct drm_i915_gem_execbuffer2 execbuf
= {
2083 .buffers_ptr
= (uintptr_t) exec_objects
,
2085 .batch_len
= ALIGN((char *) batch
- (char *) map
, 8),
2086 .flags
= I915_EXEC_RENDER
,
2089 /* Don't bother with error checking - if the execbuf fails, the
2090 * value won't be written and we'll just report that there's no access.
2092 drmIoctl(screen
->fd
, DRM_IOCTL_I915_GEM_EXECBUFFER2
, &execbuf
);
2094 /* Check whether the value got written. */
2095 void *results_map
= brw_bo_map(NULL
, results
, MAP_READ
);
2097 success
= *((uint32_t *)results_map
+ offset
) == expected_value
;
2098 brw_bo_unmap(results
);
2102 brw_bo_unreference(bo
);
2104 brw_bo_unreference(results
);
2110 intel_detect_pipelined_so(struct intel_screen
*screen
)
2112 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2114 /* Supposedly, Broadwell just works. */
2115 if (devinfo
->gen
>= 8)
2118 if (devinfo
->gen
<= 6)
2121 /* See the big explanation about command parser versions below */
2122 if (screen
->cmd_parser_version
>= (devinfo
->is_haswell
? 7 : 2))
2125 /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
2126 * statistics registers), and we already reset it to zero before using it.
2128 return intel_detect_pipelined_register(screen
,
2129 GEN7_SO_WRITE_OFFSET(0),
2135 * Return array of MSAA modes supported by the hardware. The array is
2136 * zero-terminated and sorted in decreasing order.
2139 intel_supported_msaa_modes(const struct intel_screen
*screen
)
2141 static const int gen9_modes
[] = {16, 8, 4, 2, 0, -1};
2142 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
2143 static const int gen7_modes
[] = {8, 4, 0, -1};
2144 static const int gen6_modes
[] = {4, 0, -1};
2145 static const int gen4_modes
[] = {0, -1};
2147 if (screen
->devinfo
.gen
>= 9) {
2149 } else if (screen
->devinfo
.gen
>= 8) {
2151 } else if (screen
->devinfo
.gen
>= 7) {
2153 } else if (screen
->devinfo
.gen
== 6) {
2161 intel_loader_get_cap(const __DRIscreen
*dri_screen
, enum dri_loader_cap cap
)
2163 if (dri_screen
->dri2
.loader
&& dri_screen
->dri2
.loader
->base
.version
>= 4 &&
2164 dri_screen
->dri2
.loader
->getCapability
)
2165 return dri_screen
->dri2
.loader
->getCapability(dri_screen
->loaderPrivate
, cap
);
2167 if (dri_screen
->image
.loader
&& dri_screen
->image
.loader
->base
.version
>= 2 &&
2168 dri_screen
->image
.loader
->getCapability
)
2169 return dri_screen
->image
.loader
->getCapability(dri_screen
->loaderPrivate
, cap
);
2175 intel_allowed_format(__DRIscreen
*dri_screen
, mesa_format format
)
2177 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2179 /* Expose only BGRA ordering if the loader doesn't support RGBA ordering. */
2180 bool allow_rgba_ordering
= intel_loader_get_cap(dri_screen
, DRI_LOADER_CAP_RGBA_ORDERING
);
2181 if (!allow_rgba_ordering
&&
2182 (format
== MESA_FORMAT_R8G8B8A8_UNORM
||
2183 format
== MESA_FORMAT_R8G8B8X8_UNORM
||
2184 format
== MESA_FORMAT_R8G8B8A8_SRGB
))
2187 /* Shall we expose 10 bpc formats? */
2188 bool allow_rgb10_configs
= driQueryOptionb(&screen
->optionCache
,
2189 "allow_rgb10_configs");
2190 if (!allow_rgb10_configs
&&
2191 (format
== MESA_FORMAT_B10G10R10A2_UNORM
||
2192 format
== MESA_FORMAT_B10G10R10X2_UNORM
))
2195 /* Shall we expose 565 formats? */
2196 bool allow_rgb565_configs
= driQueryOptionb(&screen
->optionCache
,
2197 "allow_rgb565_configs");
2198 if (!allow_rgb565_configs
&& format
== MESA_FORMAT_B5G6R5_UNORM
)
2201 /* Shall we expose fp16 formats? */
2202 bool allow_fp16_configs
= driQueryOptionb(&screen
->optionCache
,
2203 "allow_fp16_configs");
2204 allow_fp16_configs
&= intel_loader_get_cap(dri_screen
, DRI_LOADER_CAP_FP16
);
2205 if (!allow_fp16_configs
&&
2206 (format
== MESA_FORMAT_RGBA_FLOAT16
||
2207 format
== MESA_FORMAT_RGBX_FLOAT16
))
2213 static __DRIconfig
**
2214 intel_screen_make_configs(__DRIscreen
*dri_screen
)
2216 static const mesa_format formats
[] = {
2217 MESA_FORMAT_B5G6R5_UNORM
,
2218 MESA_FORMAT_B8G8R8A8_UNORM
,
2219 MESA_FORMAT_B8G8R8X8_UNORM
,
2221 MESA_FORMAT_B8G8R8A8_SRGB
,
2222 MESA_FORMAT_B8G8R8X8_SRGB
,
2224 /* For 10 bpc, 30 bit depth framebuffers. */
2225 MESA_FORMAT_B10G10R10A2_UNORM
,
2226 MESA_FORMAT_B10G10R10X2_UNORM
,
2228 MESA_FORMAT_RGBA_FLOAT16
,
2229 MESA_FORMAT_RGBX_FLOAT16
,
2231 /* The 32-bit RGBA format must not precede the 32-bit BGRA format.
2232 * Likewise for RGBX and BGRX. Otherwise, the GLX client and the GLX
2233 * server may disagree on which format the GLXFBConfig represents,
2234 * resulting in swapped color channels.
2236 * The problem, as of 2017-05-30:
2237 * When matching a GLXFBConfig to a __DRIconfig, GLX ignores the channel
2238 * order and chooses the first __DRIconfig with the expected channel
2239 * sizes. Specifically, GLX compares the GLXFBConfig's and __DRIconfig's
2240 * __DRI_ATTRIB_{CHANNEL}_SIZE but ignores __DRI_ATTRIB_{CHANNEL}_MASK.
2242 * EGL does not suffer from this problem. It correctly compares the
2243 * channel masks when matching EGLConfig to __DRIconfig.
2246 /* Required by Android, for HAL_PIXEL_FORMAT_RGBA_8888. */
2247 MESA_FORMAT_R8G8B8A8_UNORM
,
2249 /* Required by Android, for HAL_PIXEL_FORMAT_RGBX_8888. */
2250 MESA_FORMAT_R8G8B8X8_UNORM
,
2252 MESA_FORMAT_R8G8B8A8_SRGB
,
2255 /* __DRI_ATTRIB_SWAP_COPY is not supported due to page flipping. */
2256 static const GLenum back_buffer_modes
[] = {
2257 __DRI_ATTRIB_SWAP_UNDEFINED
, __DRI_ATTRIB_SWAP_NONE
2260 static const uint8_t singlesample_samples
[1] = {0};
2262 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2263 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2264 uint8_t depth_bits
[4], stencil_bits
[4];
2265 __DRIconfig
**configs
= NULL
;
2267 unsigned num_formats
= ARRAY_SIZE(formats
);
2269 /* Generate singlesample configs, each without accumulation buffer
2270 * and with EGL_MUTABLE_RENDER_BUFFER_BIT_KHR.
2272 for (unsigned i
= 0; i
< num_formats
; i
++) {
2273 __DRIconfig
**new_configs
;
2274 int num_depth_stencil_bits
= 1;
2276 if (!intel_allowed_format(dri_screen
, formats
[i
]))
2279 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
2280 * buffer that has a different number of bits per pixel than the color
2281 * buffer, gen >= 6 supports this.
2284 stencil_bits
[0] = 0;
2286 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2287 if (devinfo
->gen
>= 8) {
2288 depth_bits
[num_depth_stencil_bits
] = 16;
2289 stencil_bits
[num_depth_stencil_bits
] = 0;
2290 num_depth_stencil_bits
++;
2292 if (devinfo
->gen
>= 6) {
2293 depth_bits
[num_depth_stencil_bits
] = 24;
2294 stencil_bits
[num_depth_stencil_bits
] = 8;
2295 num_depth_stencil_bits
++;
2298 depth_bits
[num_depth_stencil_bits
] = 24;
2299 stencil_bits
[num_depth_stencil_bits
] = 8;
2300 num_depth_stencil_bits
++;
2303 new_configs
= driCreateConfigs(formats
[i
],
2306 num_depth_stencil_bits
,
2307 back_buffer_modes
, 2,
2308 singlesample_samples
, 1,
2310 /*mutable_render_buffer*/ true);
2311 configs
= driConcatConfigs(configs
, new_configs
);
2314 /* Generate the minimum possible set of configs that include an
2315 * accumulation buffer.
2317 for (unsigned i
= 0; i
< num_formats
; i
++) {
2318 __DRIconfig
**new_configs
;
2320 if (!intel_allowed_format(dri_screen
, formats
[i
]))
2323 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2324 if (devinfo
->gen
>= 8) {
2326 stencil_bits
[0] = 0;
2327 } else if (devinfo
->gen
>= 6) {
2329 stencil_bits
[0] = 8;
2332 stencil_bits
[0] = 0;
2336 stencil_bits
[0] = 8;
2339 new_configs
= driCreateConfigs(formats
[i
],
2340 depth_bits
, stencil_bits
, 1,
2341 back_buffer_modes
, 1,
2342 singlesample_samples
, 1,
2343 true, false, false);
2344 configs
= driConcatConfigs(configs
, new_configs
);
2347 /* Generate multisample configs.
2349 * This loop breaks early, and hence is a no-op, on gen < 6.
2351 * Multisample configs must follow the singlesample configs in order to
2352 * work around an X server bug present in 1.12. The X server chooses to
2353 * associate the first listed RGBA888-Z24S8 config, regardless of its
2354 * sample count, with the 32-bit depth visual used for compositing.
2356 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
2357 * supported. Singlebuffer configs are not supported because no one wants
2360 for (unsigned i
= 0; i
< num_formats
; i
++) {
2361 if (devinfo
->gen
< 6)
2364 if (!intel_allowed_format(dri_screen
, formats
[i
]))
2367 __DRIconfig
**new_configs
;
2368 const int num_depth_stencil_bits
= 2;
2369 int num_msaa_modes
= 0;
2370 const uint8_t *multisample_samples
= NULL
;
2373 stencil_bits
[0] = 0;
2375 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
&& devinfo
->gen
>= 8) {
2377 stencil_bits
[1] = 0;
2380 stencil_bits
[1] = 8;
2383 if (devinfo
->gen
>= 9) {
2384 static const uint8_t multisample_samples_gen9
[] = {2, 4, 8, 16};
2385 multisample_samples
= multisample_samples_gen9
;
2386 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen9
);
2387 } else if (devinfo
->gen
== 8) {
2388 static const uint8_t multisample_samples_gen8
[] = {2, 4, 8};
2389 multisample_samples
= multisample_samples_gen8
;
2390 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen8
);
2391 } else if (devinfo
->gen
== 7) {
2392 static const uint8_t multisample_samples_gen7
[] = {4, 8};
2393 multisample_samples
= multisample_samples_gen7
;
2394 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen7
);
2395 } else if (devinfo
->gen
== 6) {
2396 static const uint8_t multisample_samples_gen6
[] = {4};
2397 multisample_samples
= multisample_samples_gen6
;
2398 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen6
);
2401 new_configs
= driCreateConfigs(formats
[i
],
2404 num_depth_stencil_bits
,
2405 back_buffer_modes
, 1,
2406 multisample_samples
,
2408 false, false, false);
2409 configs
= driConcatConfigs(configs
, new_configs
);
2412 if (configs
== NULL
) {
2413 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
2422 set_max_gl_versions(struct intel_screen
*screen
)
2424 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
2425 const bool has_astc
= screen
->devinfo
.gen
>= 9;
2427 switch (screen
->devinfo
.gen
) {
2432 dri_screen
->max_gl_core_version
= 46;
2433 dri_screen
->max_gl_compat_version
= 30;
2434 dri_screen
->max_gl_es1_version
= 11;
2435 dri_screen
->max_gl_es2_version
= has_astc
? 32 : 31;
2438 dri_screen
->max_gl_core_version
= 33;
2439 if (can_do_pipelined_register_writes(screen
)) {
2440 dri_screen
->max_gl_core_version
= 42;
2441 if (screen
->devinfo
.is_haswell
&& can_do_compute_dispatch(screen
))
2442 dri_screen
->max_gl_core_version
= 43;
2443 if (screen
->devinfo
.is_haswell
&& can_do_mi_math_and_lrr(screen
))
2444 dri_screen
->max_gl_core_version
= 45;
2446 dri_screen
->max_gl_compat_version
= 30;
2447 dri_screen
->max_gl_es1_version
= 11;
2448 dri_screen
->max_gl_es2_version
= screen
->devinfo
.is_haswell
? 31 : 30;
2451 dri_screen
->max_gl_core_version
= 33;
2452 dri_screen
->max_gl_compat_version
= 30;
2453 dri_screen
->max_gl_es1_version
= 11;
2454 dri_screen
->max_gl_es2_version
= 30;
2458 dri_screen
->max_gl_core_version
= 0;
2459 dri_screen
->max_gl_compat_version
= 21;
2460 dri_screen
->max_gl_es1_version
= 11;
2461 dri_screen
->max_gl_es2_version
= 20;
2464 unreachable("unrecognized intel_screen::gen");
2469 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
2471 struct brw_context
*brw
= (struct brw_context
*)data
;
2474 va_start(args
, fmt
);
2476 _mesa_gl_vdebugf(&brw
->ctx
, &msg_id
,
2477 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
2478 MESA_DEBUG_TYPE_OTHER
,
2479 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
2484 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
2486 struct brw_context
*brw
= (struct brw_context
*)data
;
2489 va_start(args
, fmt
);
2491 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
2493 va_copy(args_copy
, args
);
2494 vfprintf(stderr
, fmt
, args_copy
);
2498 if (brw
->perf_debug
) {
2500 _mesa_gl_vdebugf(&brw
->ctx
, &msg_id
,
2501 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
2502 MESA_DEBUG_TYPE_PERFORMANCE
,
2503 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
2509 * This is the driver specific part of the createNewScreen entry point.
2510 * Called when using DRI2.
2512 * \return the struct gl_config supported by this driver
2515 __DRIconfig
**intelInitScreen2(__DRIscreen
*dri_screen
)
2517 struct intel_screen
*screen
;
2519 if (dri_screen
->image
.loader
) {
2520 } else if (dri_screen
->dri2
.loader
->base
.version
<= 2 ||
2521 dri_screen
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
2523 "\nERROR! DRI2 loader with getBuffersWithFormat() "
2524 "support required\n");
2528 /* Allocate the private area */
2529 screen
= rzalloc(NULL
, struct intel_screen
);
2531 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
2534 /* parse information in __driConfigOptions */
2535 driOptionCache options
;
2536 memset(&options
, 0, sizeof(options
));
2538 driParseOptionInfo(&options
, brw_config_options
.xml
);
2539 driParseConfigFiles(&screen
->optionCache
, &options
, dri_screen
->myNum
,
2540 "i965", NULL
, NULL
, 0);
2541 driDestroyOptionCache(&options
);
2543 screen
->driScrnPriv
= dri_screen
;
2544 dri_screen
->driverPrivate
= (void *) screen
;
2546 if (!gen_get_device_info_from_fd(dri_screen
->fd
, &screen
->devinfo
))
2549 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2550 screen
->deviceID
= devinfo
->chipset_id
;
2551 screen
->no_hw
= devinfo
->no_hw
;
2553 if (devinfo
->gen
>= 12) {
2554 fprintf(stderr
, "gen12 and newer are not supported on i965\n");
2558 if (!intel_init_bufmgr(screen
))
2561 brw_process_intel_debug_variable();
2563 if ((INTEL_DEBUG
& DEBUG_SHADER_TIME
) && devinfo
->gen
< 7) {
2565 "shader_time debugging requires gen7 (Ivybridge) or better.\n");
2566 INTEL_DEBUG
&= ~DEBUG_SHADER_TIME
;
2569 if (intel_get_integer(screen
, I915_PARAM_MMAP_GTT_VERSION
) >= 1) {
2570 /* Theorectically unlimited! At least for individual objects...
2572 * Currently the entire (global) address space for all GTT maps is
2573 * limited to 64bits. That is all objects on the system that are
2574 * setup for GTT mmapping must fit within 64bits. An attempt to use
2575 * one that exceeds the limit with fail in brw_bo_map_gtt().
2577 * Long before we hit that limit, we will be practically limited by
2578 * that any single object must fit in physical memory (RAM). The upper
2579 * limit on the CPU's address space is currently 48bits (Skylake), of
2580 * which only 39bits can be physical memory. (The GPU itself also has
2581 * a 48bit addressable virtual space.) We can fit over 32 million
2582 * objects of the current maximum allocable size before running out
2585 screen
->max_gtt_map_object_size
= UINT64_MAX
;
2587 /* Estimate the size of the mappable aperture into the GTT. There's an
2588 * ioctl to get the whole GTT size, but not one to get the mappable subset.
2589 * It turns out it's basically always 256MB, though some ancient hardware
2592 uint32_t gtt_size
= 256 * 1024 * 1024;
2594 /* We don't want to map two objects such that a memcpy between them would
2595 * just fault one mapping in and then the other over and over forever. So
2596 * we would need to divide the GTT size by 2. Additionally, some GTT is
2597 * taken up by things like the framebuffer and the ringbuffer and such, so
2598 * be more conservative.
2600 screen
->max_gtt_map_object_size
= gtt_size
/ 4;
2603 screen
->aperture_threshold
= devinfo
->aperture_bytes
* 3 / 4;
2605 screen
->hw_has_swizzling
= intel_detect_swizzling(screen
);
2606 screen
->hw_has_timestamp
= intel_detect_timestamp(screen
);
2608 isl_device_init(&screen
->isl_dev
, &screen
->devinfo
,
2609 screen
->hw_has_swizzling
);
2611 if (devinfo
->gen
>= 10)
2612 intel_cs_timestamp_frequency(screen
);
2614 /* GENs prior to 8 do not support EU/Subslice info */
2615 if (devinfo
->gen
>= 8) {
2616 intel_detect_sseu(screen
);
2617 } else if (devinfo
->gen
== 7) {
2618 screen
->subslice_total
= 1 << (devinfo
->gt
- 1);
2621 /* Gen7-7.5 kernel requirements / command parser saga:
2624 * Haswell and Baytrail cannot use any privileged batchbuffer features.
2626 * Ivybridge has aliasing PPGTT on by default, which accidentally marks
2627 * all batches secure, allowing them to use any feature with no checking.
2628 * This is effectively equivalent to a command parser version of
2629 * \infinity - everything is possible.
2631 * The command parser does not exist, and querying the version will
2635 * The kernel enables the command parser by default, for systems with
2636 * aliasing PPGTT enabled (Ivybridge and Haswell). However, the
2637 * hardware checker is still enabled, so Haswell and Baytrail cannot
2640 * Ivybridge goes from "everything is possible" to "only what the
2641 * command parser allows" (if the user boots with i915.cmd_parser=0,
2642 * then everything is possible again). We can only safely use features
2643 * allowed by the supported command parser version.
2645 * Annoyingly, I915_PARAM_CMD_PARSER_VERSION reports the static version
2646 * implemented by the kernel, even if it's turned off. So, checking
2647 * for version > 0 does not mean that you can write registers. We have
2648 * to try it and see. The version does, however, indicate the age of
2651 * Instead of matching the hardware checker's behavior of converting
2652 * privileged commands to MI_NOOP, it makes execbuf2 start returning
2653 * -EINVAL, making it dangerous to try and use privileged features.
2655 * Effective command parser versions:
2656 * - Haswell: 0 (reporting 1, writes don't work)
2657 * - Baytrail: 0 (reporting 1, writes don't work)
2658 * - Ivybridge: 1 (enabled) or infinite (disabled)
2661 * Baytrail aliasing PPGTT is enabled, making it like Ivybridge:
2662 * effectively version 1 (enabled) or infinite (disabled).
2664 * - v3.19: f1f55cc0556031c8ee3fe99dae7251e78b9b653b
2665 * Command parser v2 supports predicate writes.
2667 * - Haswell: 0 (reporting 1, writes don't work)
2668 * - Baytrail: 2 (enabled) or infinite (disabled)
2669 * - Ivybridge: 2 (enabled) or infinite (disabled)
2671 * So version >= 2 is enough to know that Ivybridge and Baytrail
2672 * will work. Haswell still can't do anything.
2674 * - v4.0: Version 3 happened. Largely not relevant.
2676 * - v4.1: 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b
2677 * L3 config registers are properly saved and restored as part
2678 * of the hardware context. We can approximately detect this point
2679 * in time by checking if I915_PARAM_REVISION is recognized - it
2680 * landed in a later commit, but in the same release cycle.
2682 * - v4.2: 245054a1fe33c06ad233e0d58a27ec7b64db9284
2683 * Command parser finally gains secure batch promotion. On Haswell,
2684 * the hardware checker gets disabled, which finally allows it to do
2685 * privileged commands.
2687 * I915_PARAM_CMD_PARSER_VERSION reports 3. Effective versions:
2688 * - Haswell: 3 (enabled) or 0 (disabled)
2689 * - Baytrail: 3 (enabled) or infinite (disabled)
2690 * - Ivybridge: 3 (enabled) or infinite (disabled)
2692 * Unfortunately, detecting this point in time is tricky, because
2693 * no version bump happened when this important change occurred.
2694 * On Haswell, if we can write any register, then the kernel is at
2695 * least this new, and we can start trusting the version number.
2697 * - v4.4: 2bbe6bbb0dc94fd4ce287bdac9e1bd184e23057b and
2698 * Command parser reaches version 4, allowing access to Haswell
2699 * atomic scratch and chicken3 registers. If version >= 4, we know
2700 * the kernel is new enough to support privileged features on all
2701 * hardware. However, the user might have disabled it...and the
2702 * kernel will still report version 4. So we still have to guess
2705 * - v4.4: 7b9748cb513a6bef4af87b79f0da3ff7e8b56cd8
2706 * Command parser v5 whitelists indirect compute shader dispatch
2707 * registers, needed for OpenGL 4.3 and later.
2710 * Command parser v7 lets us use MI_MATH on Haswell.
2712 * Additionally, the kernel begins reporting version 0 when
2713 * the command parser is disabled, allowing us to skip the
2714 * guess-and-check step on Haswell. Unfortunately, this also
2715 * means that we can no longer use it as an indicator of the
2716 * age of the kernel.
2718 if (intel_get_param(screen
, I915_PARAM_CMD_PARSER_VERSION
,
2719 &screen
->cmd_parser_version
) < 0) {
2720 /* Command parser does not exist - getparam is unrecognized */
2721 screen
->cmd_parser_version
= 0;
2724 /* Kernel 4.13 retuired for exec object capture */
2725 if (intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_CAPTURE
)) {
2726 screen
->kernel_features
|= KERNEL_ALLOWS_EXEC_CAPTURE
;
2729 if (intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_BATCH_FIRST
)) {
2730 screen
->kernel_features
|= KERNEL_ALLOWS_EXEC_BATCH_FIRST
;
2733 if (!intel_detect_pipelined_so(screen
)) {
2734 /* We can't do anything, so the effective version is 0. */
2735 screen
->cmd_parser_version
= 0;
2737 screen
->kernel_features
|= KERNEL_ALLOWS_SOL_OFFSET_WRITES
;
2740 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 2)
2741 screen
->kernel_features
|= KERNEL_ALLOWS_PREDICATE_WRITES
;
2743 /* Haswell requires command parser version 4 in order to have L3
2744 * atomic scratch1 and chicken3 bits
2746 if (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 4) {
2747 screen
->kernel_features
|=
2748 KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3
;
2751 /* Haswell requires command parser version 6 in order to write to the
2752 * MI_MATH GPR registers, and version 7 in order to use
2753 * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
2755 if (devinfo
->gen
>= 8 ||
2756 (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 7)) {
2757 screen
->kernel_features
|= KERNEL_ALLOWS_MI_MATH_AND_LRR
;
2760 /* Gen7 needs at least command parser version 5 to support compute */
2761 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 5)
2762 screen
->kernel_features
|= KERNEL_ALLOWS_COMPUTE_DISPATCH
;
2764 if (intel_get_boolean(screen
, I915_PARAM_HAS_CONTEXT_ISOLATION
))
2765 screen
->kernel_features
|= KERNEL_ALLOWS_CONTEXT_ISOLATION
;
2767 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
2769 screen
->winsys_msaa_samples_override
=
2770 intel_quantize_num_samples(screen
, atoi(force_msaa
));
2771 printf("Forcing winsys sample count to %d\n",
2772 screen
->winsys_msaa_samples_override
);
2774 screen
->winsys_msaa_samples_override
= -1;
2777 set_max_gl_versions(screen
);
2779 /* Notification of GPU resets requires hardware contexts and a kernel new
2780 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
2781 * supported, calling it with a context of 0 will either generate EPERM or
2782 * no error. If the ioctl is not supported, it always generate EINVAL.
2783 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
2784 * extension to the loader.
2786 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
2788 if (devinfo
->gen
>= 6) {
2789 struct drm_i915_reset_stats stats
;
2790 memset(&stats
, 0, sizeof(stats
));
2792 const int ret
= drmIoctl(screen
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
2794 screen
->has_context_reset_notification
=
2795 (ret
!= -1 || errno
!= EINVAL
);
2798 dri_screen
->extensions
= !screen
->has_context_reset_notification
2799 ? screenExtensions
: intelRobustScreenExtensions
;
2801 screen
->compiler
= brw_compiler_create(screen
, devinfo
);
2802 screen
->compiler
->shader_debug_log
= shader_debug_log_mesa
;
2803 screen
->compiler
->shader_perf_log
= shader_perf_log_mesa
;
2805 /* Changing the meaning of constant buffer pointers from a dynamic state
2806 * offset to an absolute address is only safe if the kernel isolates other
2807 * contexts from our changes.
2809 screen
->compiler
->constant_buffer_0_is_relative
= devinfo
->gen
< 8 ||
2810 !(screen
->kernel_features
& KERNEL_ALLOWS_CONTEXT_ISOLATION
);
2812 screen
->compiler
->glsl_compiler_options
[MESA_SHADER_VERTEX
].PositionAlwaysInvariant
= driQueryOptionb(&screen
->optionCache
, "vs_position_always_invariant");
2814 screen
->compiler
->supports_pull_constants
= true;
2815 screen
->compiler
->compact_params
= true;
2816 screen
->compiler
->lower_variable_group_size
= true;
2818 screen
->has_exec_fence
=
2819 intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_FENCE
);
2821 intel_screen_init_surface_formats(screen
);
2823 if (INTEL_DEBUG
& (DEBUG_BATCH
| DEBUG_SUBMIT
)) {
2824 unsigned int caps
= intel_get_integer(screen
, I915_PARAM_HAS_SCHEDULER
);
2826 fprintf(stderr
, "Kernel scheduler detected: %08x\n", caps
);
2827 if (caps
& I915_SCHEDULER_CAP_PRIORITY
)
2828 fprintf(stderr
, " - User priority sorting enabled\n");
2829 if (caps
& I915_SCHEDULER_CAP_PREEMPTION
)
2830 fprintf(stderr
, " - Preemption enabled\n");
2834 brw_disk_cache_init(screen
);
2836 return (const __DRIconfig
**) intel_screen_make_configs(dri_screen
);
2839 struct intel_buffer
{
2844 static __DRIbuffer
*
2845 intelAllocateBuffer(__DRIscreen
*dri_screen
,
2846 unsigned attachment
, unsigned format
,
2847 int width
, int height
)
2849 struct intel_buffer
*intelBuffer
;
2850 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2852 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
2853 attachment
== __DRI_BUFFER_BACK_LEFT
);
2855 intelBuffer
= calloc(1, sizeof *intelBuffer
);
2856 if (intelBuffer
== NULL
)
2859 /* The front and back buffers are color buffers, which are X tiled. GEN9+
2860 * supports Y tiled and compressed buffers, but there is no way to plumb that
2861 * through to here. */
2863 int cpp
= format
/ 8;
2864 intelBuffer
->bo
= brw_bo_alloc_tiled_2d(screen
->bufmgr
,
2865 "intelAllocateBuffer",
2870 I915_TILING_X
, &pitch
,
2873 if (intelBuffer
->bo
== NULL
) {
2878 brw_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
2880 intelBuffer
->base
.attachment
= attachment
;
2881 intelBuffer
->base
.cpp
= cpp
;
2882 intelBuffer
->base
.pitch
= pitch
;
2884 return &intelBuffer
->base
;
2888 intelReleaseBuffer(__DRIscreen
*dri_screen
, __DRIbuffer
*buffer
)
2890 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
2892 brw_bo_unreference(intelBuffer
->bo
);
2896 static const struct __DriverAPIRec brw_driver_api
= {
2897 .InitScreen
= intelInitScreen2
,
2898 .DestroyScreen
= intelDestroyScreen
,
2899 .CreateContext
= brwCreateContext
,
2900 .DestroyContext
= intelDestroyContext
,
2901 .CreateBuffer
= intelCreateBuffer
,
2902 .DestroyBuffer
= intelDestroyBuffer
,
2903 .MakeCurrent
= intelMakeCurrent
,
2904 .UnbindContext
= intelUnbindContext
,
2905 .AllocateBuffer
= intelAllocateBuffer
,
2906 .ReleaseBuffer
= intelReleaseBuffer
2909 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
2910 .base
= { __DRI_DRIVER_VTABLE
, 1 },
2911 .vtable
= &brw_driver_api
,
2914 static const __DRIextension
*brw_driver_extensions
[] = {
2915 &driCoreExtension
.base
,
2916 &driImageDriverExtension
.base
,
2917 &driDRI2Extension
.base
,
2919 &brw_config_options
.base
,
2923 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
2925 globalDriverAPI
= &brw_driver_api
;
2927 return brw_driver_extensions
;