2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "drm-uapi/drm_fourcc.h"
30 #include "main/context.h"
31 #include "main/framebuffer.h"
32 #include "main/renderbuffer.h"
33 #include "main/texobj.h"
34 #include "main/hash.h"
35 #include "main/fbobject.h"
36 #include "main/version.h"
37 #include "main/glthread.h"
38 #include "swrast/s_renderbuffer.h"
39 #include "util/ralloc.h"
40 #include "util/disk_cache.h"
41 #include "brw_defines.h"
42 #include "brw_state.h"
43 #include "compiler/nir/nir.h"
46 #include "util/disk_cache.h"
47 #include "util/xmlpool.h"
48 #include "util/u_memory.h"
50 #include "common/gen_defines.h"
52 static const __DRIconfigOptionsExtension brw_config_options
= {
53 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
56 DRI_CONF_SECTION_PERFORMANCE
57 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
58 * DRI_CONF_BO_REUSE_ALL
60 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
61 DRI_CONF_DESC_BEGIN(en
, "Buffer object reuse")
62 DRI_CONF_ENUM(0, "Disable buffer object reuse")
63 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
66 DRI_CONF_MESA_NO_ERROR("false")
67 DRI_CONF_MESA_GLTHREAD("false")
70 DRI_CONF_SECTION_QUALITY
71 DRI_CONF_PRECISE_TRIG("false")
73 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
74 DRI_CONF_DESC(en
, "Clamp the value of GL_MAX_SAMPLES to the "
75 "given integer. If negative, then do not clamp.")
79 DRI_CONF_SECTION_DEBUG
80 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
81 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
82 DRI_CONF_DISABLE_THROTTLING("false")
83 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
84 DRI_CONF_FORCE_GLSL_VERSION(0)
85 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
86 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
87 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
88 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
89 DRI_CONF_ALLOW_GLSL_BUILTIN_VARIABLE_REDECLARATION("false")
90 DRI_CONF_ALLOW_GLSL_CROSS_STAGE_INTERPOLATION_MISMATCH("false")
91 DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
92 DRI_CONF_FORCE_COMPAT_PROFILE("false")
93 DRI_CONF_FORCE_GLSL_ABS_SQRT("false")
95 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
96 DRI_CONF_DESC(en
, "Perform code generation at shader link time.")
100 DRI_CONF_SECTION_MISCELLANEOUS
101 DRI_CONF_GLSL_ZERO_INIT("false")
102 DRI_CONF_VS_POSITION_ALWAYS_INVARIANT("false")
103 DRI_CONF_ALLOW_RGB10_CONFIGS("false")
104 DRI_CONF_ALLOW_RGB565_CONFIGS("true")
105 DRI_CONF_ALLOW_FP16_CONFIGS("false")
110 #include "intel_batchbuffer.h"
111 #include "intel_buffers.h"
112 #include "brw_bufmgr.h"
113 #include "intel_fbo.h"
114 #include "intel_mipmap_tree.h"
115 #include "intel_screen.h"
116 #include "intel_tex.h"
117 #include "intel_image.h"
119 #include "brw_context.h"
121 #include "drm-uapi/i915_drm.h"
124 * For debugging purposes, this returns a time in seconds.
131 clock_gettime(CLOCK_MONOTONIC
, &tp
);
133 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
136 static const __DRItexBufferExtension intelTexBufferExtension
= {
137 .base
= { __DRI_TEX_BUFFER
, 3 },
139 .setTexBuffer
= intelSetTexBuffer
,
140 .setTexBuffer2
= intelSetTexBuffer2
,
141 .releaseTexBuffer
= intelReleaseTexBuffer
,
145 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
146 __DRIdrawable
*dPriv
,
148 enum __DRI2throttleReason reason
)
150 struct brw_context
*brw
= cPriv
->driverPrivate
;
155 struct gl_context
*ctx
= &brw
->ctx
;
157 _mesa_glthread_finish(ctx
);
159 FLUSH_VERTICES(ctx
, 0);
161 if (flags
& __DRI2_FLUSH_DRAWABLE
)
162 intel_resolve_for_dri2_flush(brw
, dPriv
);
164 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
)
165 brw
->need_swap_throttle
= true;
166 if (reason
== __DRI2_THROTTLE_FLUSHFRONT
)
167 brw
->need_flush_throttle
= true;
169 intel_batchbuffer_flush(brw
);
173 * Provides compatibility with loaders that only support the older (version
174 * 1-3) flush interface.
176 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
179 intel_dri2_flush(__DRIdrawable
*drawable
)
181 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
182 __DRI2_FLUSH_DRAWABLE
,
183 __DRI2_THROTTLE_SWAPBUFFER
);
186 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
187 .base
= { __DRI2_FLUSH
, 4 },
189 .flush
= intel_dri2_flush
,
190 .invalidate
= dri2InvalidateDrawable
,
191 .flush_with_flags
= intel_dri2_flush_with_flags
,
194 static const struct intel_image_format intel_image_formats
[] = {
195 { DRM_FORMAT_ABGR16161616F
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
196 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR16161616F
, 8 } } },
198 { DRM_FORMAT_XBGR16161616F
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
199 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR16161616F
, 8 } } },
201 { DRM_FORMAT_ARGB2101010
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
202 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB2101010
, 4 } } },
204 { DRM_FORMAT_XRGB2101010
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
205 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB2101010
, 4 } } },
207 { DRM_FORMAT_ABGR2101010
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
208 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR2101010
, 4 } } },
210 { DRM_FORMAT_XBGR2101010
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
211 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR2101010
, 4 } } },
213 { DRM_FORMAT_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
214 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
216 { DRM_FORMAT_ABGR8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
217 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
219 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
220 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
222 { __DRI_IMAGE_FOURCC_SXRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
223 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SXRGB8
, 4 } } },
225 { DRM_FORMAT_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
226 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
228 { DRM_FORMAT_XBGR8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
229 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 }, } },
231 { DRM_FORMAT_ARGB1555
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
232 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555
, 2 } } },
234 { DRM_FORMAT_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
235 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
237 { DRM_FORMAT_R8
, __DRI_IMAGE_COMPONENTS_R
, 1,
238 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 }, } },
240 { DRM_FORMAT_R16
, __DRI_IMAGE_COMPONENTS_R
, 1,
241 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 1 }, } },
243 { DRM_FORMAT_GR88
, __DRI_IMAGE_COMPONENTS_RG
, 1,
244 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 }, } },
246 { DRM_FORMAT_GR1616
, __DRI_IMAGE_COMPONENTS_RG
, 1,
247 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616
, 2 }, } },
249 { DRM_FORMAT_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
250 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
251 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
252 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
254 { DRM_FORMAT_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
255 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
256 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
257 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
259 { DRM_FORMAT_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
260 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
261 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
262 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
264 { DRM_FORMAT_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
265 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
266 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
267 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
269 { DRM_FORMAT_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
270 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
271 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
272 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
274 { DRM_FORMAT_YVU410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
275 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
276 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
277 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
279 { DRM_FORMAT_YVU411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
280 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
281 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
282 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
284 { DRM_FORMAT_YVU420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
285 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
286 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
287 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
289 { DRM_FORMAT_YVU422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
290 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
291 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
292 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
294 { DRM_FORMAT_YVU444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
295 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
296 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
297 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
299 { DRM_FORMAT_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
300 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
301 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
303 { DRM_FORMAT_P010
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
304 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 2 },
305 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616
, 4 } } },
307 { DRM_FORMAT_P012
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
308 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 2 },
309 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616
, 4 } } },
311 { DRM_FORMAT_P016
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
312 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 2 },
313 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616
, 4 } } },
315 { DRM_FORMAT_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
316 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
317 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
319 { DRM_FORMAT_AYUV
, __DRI_IMAGE_COMPONENTS_AYUV
, 1,
320 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
322 { DRM_FORMAT_XYUV8888
, __DRI_IMAGE_COMPONENTS_XYUV
, 1,
323 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 } } },
325 /* For YUYV and UYVY buffers, we set up two overlapping DRI images
326 * and treat them as planar buffers in the compositors.
327 * Plane 0 is GR88 and samples YU or YV pairs and places Y into
328 * the R component, while plane 1 is ARGB/ABGR and samples YUYV/UYVY
329 * clusters and places pairs and places U into the G component and
330 * V into A. This lets the texture sampler interpolate the Y
331 * components correctly when sampling from plane 0, and interpolate
332 * U and V correctly when sampling from plane 1. */
333 { DRM_FORMAT_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
334 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
335 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
336 { DRM_FORMAT_UYVY
, __DRI_IMAGE_COMPONENTS_Y_UXVX
, 2,
337 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
338 { 0, 1, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } }
341 static const struct {
344 } supported_modifiers
[] = {
345 { .modifier
= DRM_FORMAT_MOD_LINEAR
, .since_gen
= 1 },
346 { .modifier
= I915_FORMAT_MOD_X_TILED
, .since_gen
= 1 },
347 { .modifier
= I915_FORMAT_MOD_Y_TILED
, .since_gen
= 6 },
348 { .modifier
= I915_FORMAT_MOD_Y_TILED_CCS
, .since_gen
= 9 },
352 modifier_is_supported(const struct gen_device_info
*devinfo
,
353 const struct intel_image_format
*fmt
, int dri_format
,
356 const struct isl_drm_modifier_info
*modinfo
=
357 isl_drm_modifier_get_info(modifier
);
360 /* ISL had better know about the modifier */
364 if (modinfo
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
365 /* If INTEL_DEBUG=norbc is set, don't support any CCS_E modifiers */
366 if (unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
))
369 /* CCS_E is not supported for planar images */
370 if (fmt
&& fmt
->nplanes
> 1)
374 assert(dri_format
== 0);
375 dri_format
= fmt
->planes
[0].dri_format
;
378 mesa_format format
= driImageFormatToGLFormat(dri_format
);
379 /* Whether or not we support compression is based on the RGBA non-sRGB
380 * version of the format.
382 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
383 format
= _mesa_get_srgb_format_linear(format
);
384 if (!isl_format_supports_ccs_e(devinfo
,
385 brw_isl_format_for_mesa_format(format
)))
389 for (i
= 0; i
< ARRAY_SIZE(supported_modifiers
); i
++) {
390 if (supported_modifiers
[i
].modifier
!= modifier
)
393 return supported_modifiers
[i
].since_gen
<= devinfo
->gen
;
400 tiling_to_modifier(uint32_t tiling
)
402 static const uint64_t map
[] = {
403 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
404 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
405 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
408 assert(tiling
< ARRAY_SIZE(map
));
414 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
416 uint32_t tiling
, swizzle
;
417 brw_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
419 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
420 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
421 func
, image
->offset
);
425 static const struct intel_image_format
*
426 intel_image_format_lookup(int fourcc
)
428 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
429 if (intel_image_formats
[i
].fourcc
== fourcc
)
430 return &intel_image_formats
[i
];
437 intel_image_get_fourcc(__DRIimage
*image
, int *fourcc
)
439 if (image
->planar_format
) {
440 *fourcc
= image
->planar_format
->fourcc
;
444 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
445 if (intel_image_formats
[i
].planes
[0].dri_format
== image
->dri_format
) {
446 *fourcc
= intel_image_formats
[i
].fourcc
;
454 intel_allocate_image(struct intel_screen
*screen
, int dri_format
,
459 image
= calloc(1, sizeof *image
);
463 image
->screen
= screen
;
464 image
->dri_format
= dri_format
;
467 image
->format
= driImageFormatToGLFormat(dri_format
);
468 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
469 image
->format
== MESA_FORMAT_NONE
) {
474 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
475 image
->data
= loaderPrivate
;
481 * Sets up a DRIImage structure to point to a slice out of a miptree.
484 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
485 struct intel_mipmap_tree
*mt
, GLuint level
,
488 intel_miptree_make_shareable(brw
, mt
);
490 intel_miptree_check_level_layer(mt
, level
, zoffset
);
492 image
->width
= minify(mt
->surf
.phys_level0_sa
.width
,
493 level
- mt
->first_level
);
494 image
->height
= minify(mt
->surf
.phys_level0_sa
.height
,
495 level
- mt
->first_level
);
496 image
->pitch
= mt
->surf
.row_pitch_B
;
498 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
502 brw_bo_unreference(image
->bo
);
504 brw_bo_reference(mt
->bo
);
508 intel_create_image_from_name(__DRIscreen
*dri_screen
,
509 int width
, int height
, int format
,
510 int name
, int pitch
, void *loaderPrivate
)
512 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
516 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
520 if (image
->format
== MESA_FORMAT_NONE
)
523 cpp
= _mesa_get_format_bytes(image
->format
);
525 image
->width
= width
;
526 image
->height
= height
;
527 image
->pitch
= pitch
* cpp
;
528 image
->bo
= brw_bo_gem_create_from_name(screen
->bufmgr
, "image",
534 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
540 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
541 int renderbuffer
, void *loaderPrivate
)
544 struct brw_context
*brw
= context
->driverPrivate
;
545 struct gl_context
*ctx
= &brw
->ctx
;
546 struct gl_renderbuffer
*rb
;
547 struct intel_renderbuffer
*irb
;
549 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
551 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
555 irb
= intel_renderbuffer(rb
);
556 intel_miptree_make_shareable(brw
, irb
->mt
);
557 image
= calloc(1, sizeof *image
);
561 image
->internal_format
= rb
->InternalFormat
;
562 image
->format
= rb
->Format
;
563 image
->modifier
= tiling_to_modifier(
564 isl_tiling_to_i915_tiling(irb
->mt
->surf
.tiling
));
566 image
->data
= loaderPrivate
;
567 brw_bo_unreference(image
->bo
);
568 image
->bo
= irb
->mt
->bo
;
569 brw_bo_reference(irb
->mt
->bo
);
570 image
->width
= rb
->Width
;
571 image
->height
= rb
->Height
;
572 image
->pitch
= irb
->mt
->surf
.row_pitch_B
;
573 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
574 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
576 rb
->NeedsFinishRenderTexture
= true;
581 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
582 unsigned texture
, int zoffset
,
588 struct brw_context
*brw
= context
->driverPrivate
;
589 struct gl_texture_object
*obj
;
590 struct intel_texture_object
*iobj
;
593 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
594 if (!obj
|| obj
->Target
!= target
) {
595 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
599 if (target
== GL_TEXTURE_CUBE_MAP
)
602 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
603 iobj
= intel_texture_object(obj
);
604 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
605 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
609 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
610 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
614 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
615 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
618 image
= calloc(1, sizeof *image
);
620 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
624 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
625 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
626 image
->modifier
= tiling_to_modifier(
627 isl_tiling_to_i915_tiling(iobj
->mt
->surf
.tiling
));
628 image
->data
= loaderPrivate
;
629 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
630 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
631 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
632 image
->planar_format
= iobj
->planar_format
;
633 if (image
->dri_format
== __DRI_IMAGE_FORMAT_NONE
) {
634 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
639 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
644 intel_destroy_image(__DRIimage
*image
)
646 brw_bo_unreference(image
->bo
);
650 enum modifier_priority
{
651 MODIFIER_PRIORITY_INVALID
= 0,
652 MODIFIER_PRIORITY_LINEAR
,
655 MODIFIER_PRIORITY_Y_CCS
,
658 const uint64_t priority_to_modifier
[] = {
659 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
660 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
661 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
662 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
663 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
667 select_best_modifier(struct gen_device_info
*devinfo
,
669 const uint64_t *modifiers
,
670 const unsigned count
)
672 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
674 for (int i
= 0; i
< count
; i
++) {
675 if (!modifier_is_supported(devinfo
, NULL
, dri_format
, modifiers
[i
]))
678 switch (modifiers
[i
]) {
679 case I915_FORMAT_MOD_Y_TILED_CCS
:
680 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
682 case I915_FORMAT_MOD_Y_TILED
:
683 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
685 case I915_FORMAT_MOD_X_TILED
:
686 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
688 case DRM_FORMAT_MOD_LINEAR
:
689 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
691 case DRM_FORMAT_MOD_INVALID
:
697 return priority_to_modifier
[prio
];
701 intel_create_image_common(__DRIscreen
*dri_screen
,
702 int width
, int height
, int format
,
704 const uint64_t *modifiers
,
709 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
710 uint64_t modifier
= DRM_FORMAT_MOD_INVALID
;
713 /* Callers of this may specify a modifier, or a dri usage, but not both. The
714 * newer modifier interface deprecates the older usage flags.
716 assert(!(use
&& count
));
718 if (use
& __DRI_IMAGE_USE_CURSOR
) {
719 if (width
!= 64 || height
!= 64)
721 modifier
= DRM_FORMAT_MOD_LINEAR
;
724 if (use
& __DRI_IMAGE_USE_LINEAR
)
725 modifier
= DRM_FORMAT_MOD_LINEAR
;
727 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
729 /* User requested specific modifiers */
730 modifier
= select_best_modifier(&screen
->devinfo
, format
,
732 if (modifier
== DRM_FORMAT_MOD_INVALID
)
735 /* Historically, X-tiled was the default, and so lack of modifier means
738 modifier
= I915_FORMAT_MOD_X_TILED
;
742 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
746 const struct isl_drm_modifier_info
*mod_info
=
747 isl_drm_modifier_get_info(modifier
);
749 struct isl_surf surf
;
750 ok
= isl_surf_init(&screen
->isl_dev
, &surf
,
751 .dim
= ISL_SURF_DIM_2D
,
752 .format
= brw_isl_format_for_mesa_format(image
->format
),
759 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
|
760 ISL_SURF_USAGE_TEXTURE_BIT
|
761 ISL_SURF_USAGE_STORAGE_BIT
|
762 ((use
& __DRI_IMAGE_USE_SCANOUT
) ?
763 ISL_SURF_USAGE_DISPLAY_BIT
: 0),
764 .tiling_flags
= (1 << mod_info
->tiling
));
771 struct isl_surf aux_surf
= {0,};
772 if (mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
773 ok
= isl_surf_get_ccs_surf(&screen
->isl_dev
, &surf
, &aux_surf
, NULL
, 0);
779 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
);
783 /* We request that the bufmgr zero the buffer for us for two reasons:
785 * 1) If a buffer gets re-used from the pool, we don't want to leak random
786 * garbage from our process to some other.
788 * 2) For images with CCS_E, we want to ensure that the CCS starts off in
789 * a valid state. A CCS value of 0 indicates that the given block is
790 * in the pass-through state which is what we want.
792 image
->bo
= brw_bo_alloc_tiled(screen
->bufmgr
, "image",
793 surf
.size_B
+ aux_surf
.size_B
,
795 isl_tiling_to_i915_tiling(mod_info
->tiling
),
796 surf
.row_pitch_B
, BO_ALLOC_ZEROED
);
797 if (image
->bo
== NULL
) {
801 image
->width
= width
;
802 image
->height
= height
;
803 image
->pitch
= surf
.row_pitch_B
;
804 image
->modifier
= modifier
;
806 if (aux_surf
.size_B
) {
807 image
->aux_offset
= surf
.size_B
;
808 image
->aux_pitch
= aux_surf
.row_pitch_B
;
809 image
->aux_size
= aux_surf
.size_B
;
816 intel_create_image(__DRIscreen
*dri_screen
,
817 int width
, int height
, int format
,
821 return intel_create_image_common(dri_screen
, width
, height
, format
, use
, NULL
, 0,
826 intel_map_image(__DRIcontext
*context
, __DRIimage
*image
,
827 int x0
, int y0
, int width
, int height
,
828 unsigned int flags
, int *stride
, void **map_info
)
830 struct brw_context
*brw
= NULL
;
831 struct brw_bo
*bo
= NULL
;
832 void *raw_data
= NULL
;
837 if (!context
|| !image
|| !stride
|| !map_info
|| *map_info
)
840 if (x0
< 0 || x0
>= image
->width
|| width
> image
->width
- x0
)
843 if (y0
< 0 || y0
>= image
->height
|| height
> image
->height
- y0
)
846 if (flags
& MAP_INTERNAL_MASK
)
849 brw
= context
->driverPrivate
;
855 /* DRI flags and GL_MAP.*_BIT flags are the same, so just pass them on. */
856 raw_data
= brw_bo_map(brw
, bo
, flags
);
860 _mesa_get_format_block_size(image
->format
, &pix_w
, &pix_h
);
861 pix_bytes
= _mesa_get_format_bytes(image
->format
);
865 assert(pix_bytes
> 0);
867 raw_data
+= (x0
/ pix_w
) * pix_bytes
+ (y0
/ pix_h
) * image
->pitch
;
869 brw_bo_reference(bo
);
871 *stride
= image
->pitch
;
878 intel_unmap_image(__DRIcontext
*context
, __DRIimage
*image
, void *map_info
)
880 struct brw_bo
*bo
= map_info
;
883 brw_bo_unreference(bo
);
887 intel_create_image_with_modifiers(__DRIscreen
*dri_screen
,
888 int width
, int height
, int format
,
889 const uint64_t *modifiers
,
890 const unsigned count
,
893 return intel_create_image_common(dri_screen
, width
, height
, format
, 0,
894 modifiers
, count
, loaderPrivate
);
898 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
901 case __DRI_IMAGE_ATTRIB_STRIDE
:
902 *value
= image
->pitch
;
904 case __DRI_IMAGE_ATTRIB_HANDLE
:
905 *value
= brw_bo_export_gem_handle(image
->bo
);
907 case __DRI_IMAGE_ATTRIB_NAME
:
908 return !brw_bo_flink(image
->bo
, (uint32_t *) value
);
909 case __DRI_IMAGE_ATTRIB_FORMAT
:
910 *value
= image
->dri_format
;
912 case __DRI_IMAGE_ATTRIB_WIDTH
:
913 *value
= image
->width
;
915 case __DRI_IMAGE_ATTRIB_HEIGHT
:
916 *value
= image
->height
;
918 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
919 if (image
->planar_format
== NULL
)
921 *value
= image
->planar_format
->components
;
923 case __DRI_IMAGE_ATTRIB_FD
:
924 return !brw_bo_gem_export_to_prime(image
->bo
, value
);
925 case __DRI_IMAGE_ATTRIB_FOURCC
:
926 return intel_image_get_fourcc(image
, value
);
927 case __DRI_IMAGE_ATTRIB_NUM_PLANES
:
928 if (isl_drm_modifier_has_aux(image
->modifier
)) {
929 assert(!image
->planar_format
|| image
->planar_format
->nplanes
== 1);
931 } else if (image
->planar_format
) {
932 *value
= image
->planar_format
->nplanes
;
937 case __DRI_IMAGE_ATTRIB_OFFSET
:
938 *value
= image
->offset
;
940 case __DRI_IMAGE_ATTRIB_MODIFIER_LOWER
:
941 *value
= (image
->modifier
& 0xffffffff);
943 case __DRI_IMAGE_ATTRIB_MODIFIER_UPPER
:
944 *value
= ((image
->modifier
>> 32) & 0xffffffff);
953 intel_query_format_modifier_attribs(__DRIscreen
*dri_screen
,
954 uint32_t fourcc
, uint64_t modifier
,
955 int attrib
, uint64_t *value
)
957 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
958 const struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
960 if (!modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
964 case __DRI_IMAGE_FORMAT_MODIFIER_ATTRIB_PLANE_COUNT
:
965 *value
= isl_drm_modifier_has_aux(modifier
) ? 2 : f
->nplanes
;
974 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
978 image
= calloc(1, sizeof *image
);
982 brw_bo_reference(orig_image
->bo
);
983 image
->bo
= orig_image
->bo
;
984 image
->internal_format
= orig_image
->internal_format
;
985 image
->planar_format
= orig_image
->planar_format
;
986 image
->dri_format
= orig_image
->dri_format
;
987 image
->format
= orig_image
->format
;
988 image
->modifier
= orig_image
->modifier
;
989 image
->offset
= orig_image
->offset
;
990 image
->width
= orig_image
->width
;
991 image
->height
= orig_image
->height
;
992 image
->pitch
= orig_image
->pitch
;
993 image
->tile_x
= orig_image
->tile_x
;
994 image
->tile_y
= orig_image
->tile_y
;
995 image
->has_depthstencil
= orig_image
->has_depthstencil
;
996 image
->data
= loaderPrivate
;
997 image
->aux_offset
= orig_image
->aux_offset
;
998 image
->aux_pitch
= orig_image
->aux_pitch
;
1000 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
1001 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
1007 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
1009 if (use
& __DRI_IMAGE_USE_CURSOR
) {
1010 if (image
->width
!= 64 || image
->height
!= 64)
1018 intel_create_image_from_names(__DRIscreen
*dri_screen
,
1019 int width
, int height
, int fourcc
,
1020 int *names
, int num_names
,
1021 int *strides
, int *offsets
,
1022 void *loaderPrivate
)
1024 const struct intel_image_format
*f
= NULL
;
1028 if (dri_screen
== NULL
|| names
== NULL
|| num_names
!= 1)
1031 f
= intel_image_format_lookup(fourcc
);
1035 image
= intel_create_image_from_name(dri_screen
, width
, height
,
1036 __DRI_IMAGE_FORMAT_NONE
,
1037 names
[0], strides
[0],
1043 image
->planar_format
= f
;
1044 for (i
= 0; i
< f
->nplanes
; i
++) {
1045 index
= f
->planes
[i
].buffer_index
;
1046 image
->offsets
[index
] = offsets
[index
];
1047 image
->strides
[index
] = strides
[index
];
1054 intel_create_image_from_fds_common(__DRIscreen
*dri_screen
,
1055 int width
, int height
, int fourcc
,
1056 uint64_t modifier
, int *fds
, int num_fds
,
1057 int *strides
, int *offsets
,
1058 void *loaderPrivate
)
1060 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1061 const struct intel_image_format
*f
;
1066 if (fds
== NULL
|| num_fds
< 1)
1069 f
= intel_image_format_lookup(fourcc
);
1073 if (modifier
!= DRM_FORMAT_MOD_INVALID
&&
1074 !modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
1077 if (f
->nplanes
== 1)
1078 image
= intel_allocate_image(screen
, f
->planes
[0].dri_format
,
1081 image
= intel_allocate_image(screen
, __DRI_IMAGE_FORMAT_NONE
,
1087 image
->width
= width
;
1088 image
->height
= height
;
1089 image
->pitch
= strides
[0];
1091 image
->planar_format
= f
;
1093 if (modifier
!= DRM_FORMAT_MOD_INVALID
) {
1094 const struct isl_drm_modifier_info
*mod_info
=
1095 isl_drm_modifier_get_info(modifier
);
1096 uint32_t tiling
= isl_tiling_to_i915_tiling(mod_info
->tiling
);
1097 image
->bo
= brw_bo_gem_create_from_prime_tiled(screen
->bufmgr
, fds
[0],
1098 tiling
, strides
[0]);
1100 image
->bo
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[0]);
1103 if (image
->bo
== NULL
) {
1108 /* We only support all planes from the same bo.
1109 * brw_bo_gem_create_from_prime() should return the same pointer for all
1110 * fds received here */
1111 for (i
= 1; i
< num_fds
; i
++) {
1112 struct brw_bo
*aux
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[i
]);
1113 brw_bo_unreference(aux
);
1114 if (aux
!= image
->bo
) {
1115 brw_bo_unreference(image
->bo
);
1121 if (modifier
!= DRM_FORMAT_MOD_INVALID
)
1122 image
->modifier
= modifier
;
1124 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
1126 const struct isl_drm_modifier_info
*mod_info
=
1127 isl_drm_modifier_get_info(image
->modifier
);
1130 struct isl_surf surf
;
1131 for (i
= 0; i
< f
->nplanes
; i
++) {
1132 index
= f
->planes
[i
].buffer_index
;
1133 image
->offsets
[index
] = offsets
[index
];
1134 image
->strides
[index
] = strides
[index
];
1136 mesa_format format
= driImageFormatToGLFormat(f
->planes
[i
].dri_format
);
1137 /* The images we will create are actually based on the RGBA non-sRGB
1138 * version of the format.
1140 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1141 format
= _mesa_get_srgb_format_linear(format
);
1143 ok
= isl_surf_init(&screen
->isl_dev
, &surf
,
1144 .dim
= ISL_SURF_DIM_2D
,
1145 .format
= brw_isl_format_for_mesa_format(format
),
1146 .width
= image
->width
>> f
->planes
[i
].width_shift
,
1147 .height
= image
->height
>> f
->planes
[i
].height_shift
,
1152 .row_pitch_B
= strides
[index
],
1153 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1154 ISL_SURF_USAGE_TEXTURE_BIT
|
1155 ISL_SURF_USAGE_STORAGE_BIT
,
1156 .tiling_flags
= (1 << mod_info
->tiling
));
1158 brw_bo_unreference(image
->bo
);
1163 const int end
= offsets
[index
] + surf
.size_B
;
1168 if (mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1169 /* Even though we initialize surf in the loop above, we know that
1170 * anything with CCS_E will have exactly one plane so surf is properly
1171 * initialized when we get here.
1173 assert(f
->nplanes
== 1);
1175 image
->aux_offset
= offsets
[1];
1176 image
->aux_pitch
= strides
[1];
1178 /* Scanout hardware requires that the CCS be placed after the main
1179 * surface in memory. We consider any CCS that is placed any earlier in
1180 * memory to be invalid and reject it.
1182 * At some point in the future, this restriction may be relaxed if the
1183 * hardware becomes less strict but we may need a new modifier for that.
1186 if (image
->aux_offset
< size
) {
1187 brw_bo_unreference(image
->bo
);
1192 struct isl_surf aux_surf
= {0,};
1193 ok
= isl_surf_get_ccs_surf(&screen
->isl_dev
, &surf
, &aux_surf
, NULL
,
1196 brw_bo_unreference(image
->bo
);
1201 image
->aux_size
= aux_surf
.size_B
;
1203 const int end
= image
->aux_offset
+ aux_surf
.size_B
;
1207 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
);
1210 /* Check that the requested image actually fits within the BO. 'size'
1211 * is already relative to the offsets, so we don't need to add that. */
1212 if (image
->bo
->size
== 0) {
1213 image
->bo
->size
= size
;
1214 } else if (size
> image
->bo
->size
) {
1215 brw_bo_unreference(image
->bo
);
1220 if (f
->nplanes
== 1) {
1221 image
->offset
= image
->offsets
[0];
1222 intel_image_warn_if_unaligned(image
, __func__
);
1229 intel_create_image_from_fds(__DRIscreen
*dri_screen
,
1230 int width
, int height
, int fourcc
,
1231 int *fds
, int num_fds
, int *strides
, int *offsets
,
1232 void *loaderPrivate
)
1234 return intel_create_image_from_fds_common(dri_screen
, width
, height
, fourcc
,
1235 DRM_FORMAT_MOD_INVALID
,
1236 fds
, num_fds
, strides
, offsets
,
1241 intel_create_image_from_dma_bufs2(__DRIscreen
*dri_screen
,
1242 int width
, int height
,
1243 int fourcc
, uint64_t modifier
,
1244 int *fds
, int num_fds
,
1245 int *strides
, int *offsets
,
1246 enum __DRIYUVColorSpace yuv_color_space
,
1247 enum __DRISampleRange sample_range
,
1248 enum __DRIChromaSiting horizontal_siting
,
1249 enum __DRIChromaSiting vertical_siting
,
1251 void *loaderPrivate
)
1254 const struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
1257 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
1261 image
= intel_create_image_from_fds_common(dri_screen
, width
, height
,
1263 fds
, num_fds
, strides
, offsets
,
1267 * Invalid parameters and any inconsistencies between are assumed to be
1268 * checked by the caller. Therefore besides unsupported formats one can fail
1269 * only in allocation.
1272 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
1276 image
->yuv_color_space
= yuv_color_space
;
1277 image
->sample_range
= sample_range
;
1278 image
->horizontal_siting
= horizontal_siting
;
1279 image
->vertical_siting
= vertical_siting
;
1280 image
->imported_dmabuf
= true;
1282 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
1287 intel_create_image_from_dma_bufs(__DRIscreen
*dri_screen
,
1288 int width
, int height
, int fourcc
,
1289 int *fds
, int num_fds
,
1290 int *strides
, int *offsets
,
1291 enum __DRIYUVColorSpace yuv_color_space
,
1292 enum __DRISampleRange sample_range
,
1293 enum __DRIChromaSiting horizontal_siting
,
1294 enum __DRIChromaSiting vertical_siting
,
1296 void *loaderPrivate
)
1298 return intel_create_image_from_dma_bufs2(dri_screen
, width
, height
,
1299 fourcc
, DRM_FORMAT_MOD_INVALID
,
1300 fds
, num_fds
, strides
, offsets
,
1310 intel_image_format_is_supported(const struct gen_device_info
*devinfo
,
1311 const struct intel_image_format
*fmt
)
1313 /* Currently, all formats with an intel_image_format are available on all
1314 * platforms so there's really nothing to check there.
1318 if (fmt
->nplanes
== 1) {
1319 mesa_format format
= driImageFormatToGLFormat(fmt
->planes
[0].dri_format
);
1320 /* The images we will create are actually based on the RGBA non-sRGB
1321 * version of the format.
1323 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1324 format
= _mesa_get_srgb_format_linear(format
);
1325 enum isl_format isl_format
= brw_isl_format_for_mesa_format(format
);
1326 assert(isl_format_supports_rendering(devinfo
, isl_format
));
1334 intel_query_dma_buf_formats(__DRIscreen
*_screen
, int max
,
1335 int *formats
, int *count
)
1337 struct intel_screen
*screen
= _screen
->driverPrivate
;
1338 int num_formats
= 0, i
;
1340 for (i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
1341 /* These formats are valid DRI formats but do not exist in drm_fourcc.h
1342 * in the Linux kernel. We don't want to accidentally advertise them
1343 * them through the EGL layer.
1345 if (intel_image_formats
[i
].fourcc
== __DRI_IMAGE_FOURCC_SARGB8888
||
1346 intel_image_formats
[i
].fourcc
== __DRI_IMAGE_FOURCC_SABGR8888
||
1347 intel_image_formats
[i
].fourcc
== __DRI_IMAGE_FOURCC_SXRGB8888
)
1350 if (!intel_image_format_is_supported(&screen
->devinfo
,
1351 &intel_image_formats
[i
]))
1358 formats
[num_formats
- 1] = intel_image_formats
[i
].fourcc
;
1359 if (num_formats
>= max
)
1363 *count
= num_formats
;
1368 intel_query_dma_buf_modifiers(__DRIscreen
*_screen
, int fourcc
, int max
,
1369 uint64_t *modifiers
,
1370 unsigned int *external_only
,
1373 struct intel_screen
*screen
= _screen
->driverPrivate
;
1374 const struct intel_image_format
*f
;
1375 int num_mods
= 0, i
;
1377 f
= intel_image_format_lookup(fourcc
);
1381 if (!intel_image_format_is_supported(&screen
->devinfo
, f
))
1384 for (i
= 0; i
< ARRAY_SIZE(supported_modifiers
); i
++) {
1385 uint64_t modifier
= supported_modifiers
[i
].modifier
;
1386 if (!modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
1393 modifiers
[num_mods
- 1] = modifier
;
1394 if (num_mods
>= max
)
1398 if (external_only
!= NULL
) {
1399 for (i
= 0; i
< num_mods
&& i
< max
; i
++) {
1400 if (f
->components
== __DRI_IMAGE_COMPONENTS_Y_U_V
||
1401 f
->components
== __DRI_IMAGE_COMPONENTS_Y_UV
||
1402 f
->components
== __DRI_IMAGE_COMPONENTS_AYUV
||
1403 f
->components
== __DRI_IMAGE_COMPONENTS_XYUV
||
1404 f
->components
== __DRI_IMAGE_COMPONENTS_Y_XUXV
||
1405 f
->components
== __DRI_IMAGE_COMPONENTS_Y_UXVX
) {
1406 external_only
[i
] = GL_TRUE
;
1409 external_only
[i
] = GL_FALSE
;
1419 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
1421 int width
, height
, offset
, stride
, size
, dri_format
;
1427 width
= parent
->width
;
1428 height
= parent
->height
;
1430 const struct intel_image_format
*f
= parent
->planar_format
;
1432 if (f
&& plane
< f
->nplanes
) {
1433 /* Use the planar format definition. */
1434 width
>>= f
->planes
[plane
].width_shift
;
1435 height
>>= f
->planes
[plane
].height_shift
;
1436 dri_format
= f
->planes
[plane
].dri_format
;
1437 int index
= f
->planes
[plane
].buffer_index
;
1438 offset
= parent
->offsets
[index
];
1439 stride
= parent
->strides
[index
];
1440 size
= height
* stride
;
1441 } else if (plane
== 0) {
1442 /* The only plane of a non-planar image: copy the parent definition
1444 dri_format
= parent
->dri_format
;
1445 offset
= parent
->offset
;
1446 stride
= parent
->pitch
;
1447 size
= height
* stride
;
1448 } else if (plane
== 1 && parent
->modifier
!= DRM_FORMAT_MOD_INVALID
&&
1449 isl_drm_modifier_has_aux(parent
->modifier
)) {
1450 /* Auxiliary plane */
1451 dri_format
= parent
->dri_format
;
1452 offset
= parent
->aux_offset
;
1453 stride
= parent
->aux_pitch
;
1454 size
= parent
->aux_size
;
1459 if (offset
+ size
> parent
->bo
->size
) {
1460 _mesa_warning(NULL
, "intel_from_planar: subimage out of bounds");
1464 image
= intel_allocate_image(parent
->screen
, dri_format
, loaderPrivate
);
1468 image
->bo
= parent
->bo
;
1469 brw_bo_reference(parent
->bo
);
1470 image
->modifier
= parent
->modifier
;
1472 image
->width
= width
;
1473 image
->height
= height
;
1474 image
->pitch
= stride
;
1475 image
->offset
= offset
;
1477 intel_image_warn_if_unaligned(image
, __func__
);
1482 static const __DRIimageExtension intelImageExtension
= {
1483 .base
= { __DRI_IMAGE
, 16 },
1485 .createImageFromName
= intel_create_image_from_name
,
1486 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
1487 .destroyImage
= intel_destroy_image
,
1488 .createImage
= intel_create_image
,
1489 .queryImage
= intel_query_image
,
1490 .dupImage
= intel_dup_image
,
1491 .validateUsage
= intel_validate_usage
,
1492 .createImageFromNames
= intel_create_image_from_names
,
1493 .fromPlanar
= intel_from_planar
,
1494 .createImageFromTexture
= intel_create_image_from_texture
,
1495 .createImageFromFds
= intel_create_image_from_fds
,
1496 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
,
1498 .getCapabilities
= NULL
,
1499 .mapImage
= intel_map_image
,
1500 .unmapImage
= intel_unmap_image
,
1501 .createImageWithModifiers
= intel_create_image_with_modifiers
,
1502 .createImageFromDmaBufs2
= intel_create_image_from_dma_bufs2
,
1503 .queryDmaBufFormats
= intel_query_dma_buf_formats
,
1504 .queryDmaBufModifiers
= intel_query_dma_buf_modifiers
,
1505 .queryDmaBufFormatModifierAttribs
= intel_query_format_modifier_attribs
,
1509 get_aperture_size(int fd
)
1511 struct drm_i915_gem_get_aperture aperture
;
1513 if (drmIoctl(fd
, DRM_IOCTL_I915_GEM_GET_APERTURE
, &aperture
) != 0)
1516 return aperture
.aper_size
;
1520 brw_query_renderer_integer(__DRIscreen
*dri_screen
,
1521 int param
, unsigned int *value
)
1523 const struct intel_screen
*const screen
=
1524 (struct intel_screen
*) dri_screen
->driverPrivate
;
1527 case __DRI2_RENDERER_VENDOR_ID
:
1530 case __DRI2_RENDERER_DEVICE_ID
:
1531 value
[0] = screen
->deviceID
;
1533 case __DRI2_RENDERER_ACCELERATED
:
1536 case __DRI2_RENDERER_VIDEO_MEMORY
: {
1537 /* Once a batch uses more than 75% of the maximum mappable size, we
1538 * assume that there's some fragmentation, and we start doing extra
1539 * flushing, etc. That's the big cliff apps will care about.
1541 const unsigned gpu_mappable_megabytes
=
1542 screen
->aperture_threshold
/ (1024 * 1024);
1544 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
1545 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
1547 if (system_memory_pages
<= 0 || system_page_size
<= 0)
1550 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
1551 * (uint64_t) system_page_size
;
1553 const unsigned system_memory_megabytes
=
1554 (unsigned) (system_memory_bytes
/ (1024 * 1024));
1556 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
1559 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
1562 case __DRI2_RENDERER_HAS_TEXTURE_3D
:
1565 case __DRI2_RENDERER_HAS_CONTEXT_PRIORITY
:
1567 if (brw_hw_context_set_priority(screen
->bufmgr
,
1568 0, GEN_CONTEXT_HIGH_PRIORITY
) == 0)
1569 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_HIGH
;
1570 if (brw_hw_context_set_priority(screen
->bufmgr
,
1571 0, GEN_CONTEXT_LOW_PRIORITY
) == 0)
1572 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_LOW
;
1573 /* reset to default last, just in case */
1574 if (brw_hw_context_set_priority(screen
->bufmgr
,
1575 0, GEN_CONTEXT_MEDIUM_PRIORITY
) == 0)
1576 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_MEDIUM
;
1578 case __DRI2_RENDERER_HAS_FRAMEBUFFER_SRGB
:
1582 return driQueryRendererIntegerCommon(dri_screen
, param
, value
);
1589 brw_query_renderer_string(__DRIscreen
*dri_screen
,
1590 int param
, const char **value
)
1592 const struct intel_screen
*screen
=
1593 (struct intel_screen
*) dri_screen
->driverPrivate
;
1596 case __DRI2_RENDERER_VENDOR_ID
:
1597 value
[0] = brw_vendor_string
;
1599 case __DRI2_RENDERER_DEVICE_ID
:
1600 value
[0] = brw_get_renderer_string(screen
);
1610 brw_set_cache_funcs(__DRIscreen
*dri_screen
,
1611 __DRIblobCacheSet set
, __DRIblobCacheGet get
)
1613 const struct intel_screen
*const screen
=
1614 (struct intel_screen
*) dri_screen
->driverPrivate
;
1616 if (!screen
->disk_cache
)
1619 disk_cache_set_callbacks(screen
->disk_cache
, set
, get
);
1622 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
1623 .base
= { __DRI2_RENDERER_QUERY
, 1 },
1625 .queryInteger
= brw_query_renderer_integer
,
1626 .queryString
= brw_query_renderer_string
1629 static const __DRIrobustnessExtension dri2Robustness
= {
1630 .base
= { __DRI2_ROBUSTNESS
, 1 }
1633 static const __DRI2blobExtension intelBlobExtension
= {
1634 .base
= { __DRI2_BLOB
, 1 },
1635 .set_cache_funcs
= brw_set_cache_funcs
1638 static const __DRImutableRenderBufferDriverExtension intelMutableRenderBufferExtension
= {
1639 .base
= { __DRI_MUTABLE_RENDER_BUFFER_DRIVER
, 1 },
1642 static const __DRIextension
*screenExtensions
[] = {
1643 &intelTexBufferExtension
.base
,
1644 &intelFenceExtension
.base
,
1645 &intelFlushExtension
.base
,
1646 &intelImageExtension
.base
,
1647 &intelRendererQueryExtension
.base
,
1648 &intelMutableRenderBufferExtension
.base
,
1649 &dri2ConfigQueryExtension
.base
,
1650 &dri2NoErrorExtension
.base
,
1651 &intelBlobExtension
.base
,
1655 static const __DRIextension
*intelRobustScreenExtensions
[] = {
1656 &intelTexBufferExtension
.base
,
1657 &intelFenceExtension
.base
,
1658 &intelFlushExtension
.base
,
1659 &intelImageExtension
.base
,
1660 &intelRendererQueryExtension
.base
,
1661 &intelMutableRenderBufferExtension
.base
,
1662 &dri2ConfigQueryExtension
.base
,
1663 &dri2Robustness
.base
,
1664 &dri2NoErrorExtension
.base
,
1665 &intelBlobExtension
.base
,
1670 intel_get_param(struct intel_screen
*screen
, int param
, int *value
)
1673 struct drm_i915_getparam gp
;
1675 memset(&gp
, 0, sizeof(gp
));
1679 if (drmIoctl(screen
->fd
, DRM_IOCTL_I915_GETPARAM
, &gp
) == -1) {
1682 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
1689 intel_get_boolean(struct intel_screen
*screen
, int param
)
1692 return (intel_get_param(screen
, param
, &value
) == 0) && value
;
1696 intel_get_integer(struct intel_screen
*screen
, int param
)
1700 if (intel_get_param(screen
, param
, &value
) == 0)
1707 intelDestroyScreen(__DRIscreen
* sPriv
)
1709 struct intel_screen
*screen
= sPriv
->driverPrivate
;
1711 brw_bufmgr_unref(screen
->bufmgr
);
1712 driDestroyOptionInfo(&screen
->optionCache
);
1714 disk_cache_destroy(screen
->disk_cache
);
1716 ralloc_free(screen
);
1717 sPriv
->driverPrivate
= NULL
;
1722 * Create a gl_framebuffer and attach it to __DRIdrawable::driverPrivate.
1724 *_This implements driDriverAPI::createNewDrawable, which the DRI layer calls
1725 * when creating a EGLSurface, GLXDrawable, or GLXPixmap. Despite the name,
1726 * this does not allocate GPU memory.
1729 intelCreateBuffer(__DRIscreen
*dri_screen
,
1730 __DRIdrawable
* driDrawPriv
,
1731 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
1733 struct intel_renderbuffer
*rb
;
1734 struct intel_screen
*screen
= (struct intel_screen
*)
1735 dri_screen
->driverPrivate
;
1736 mesa_format rgbFormat
;
1737 unsigned num_samples
=
1738 intel_quantize_num_samples(screen
, mesaVis
->samples
);
1743 struct gl_framebuffer
*fb
= CALLOC_STRUCT(gl_framebuffer
);
1747 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
1749 if (screen
->winsys_msaa_samples_override
!= -1) {
1750 num_samples
= screen
->winsys_msaa_samples_override
;
1751 fb
->Visual
.samples
= num_samples
;
1754 if (mesaVis
->redBits
== 16 && mesaVis
->alphaBits
> 0 && mesaVis
->floatMode
) {
1755 rgbFormat
= MESA_FORMAT_RGBA_FLOAT16
;
1756 } else if (mesaVis
->redBits
== 16 && mesaVis
->floatMode
) {
1757 rgbFormat
= MESA_FORMAT_RGBX_FLOAT16
;
1758 } else if (mesaVis
->redBits
== 10 && mesaVis
->alphaBits
> 0) {
1759 rgbFormat
= mesaVis
->redMask
== 0x3ff00000 ? MESA_FORMAT_B10G10R10A2_UNORM
1760 : MESA_FORMAT_R10G10B10A2_UNORM
;
1761 } else if (mesaVis
->redBits
== 10) {
1762 rgbFormat
= mesaVis
->redMask
== 0x3ff00000 ? MESA_FORMAT_B10G10R10X2_UNORM
1763 : MESA_FORMAT_R10G10B10X2_UNORM
;
1764 } else if (mesaVis
->redBits
== 5) {
1765 rgbFormat
= mesaVis
->redMask
== 0x1f ? MESA_FORMAT_R5G6B5_UNORM
1766 : MESA_FORMAT_B5G6R5_UNORM
;
1767 } else if (mesaVis
->alphaBits
== 0) {
1768 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8X8_SRGB
1769 : MESA_FORMAT_B8G8R8X8_SRGB
;
1770 fb
->Visual
.sRGBCapable
= true;
1771 } else if (mesaVis
->sRGBCapable
) {
1772 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1773 : MESA_FORMAT_B8G8R8A8_SRGB
;
1774 fb
->Visual
.sRGBCapable
= true;
1776 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1777 : MESA_FORMAT_B8G8R8A8_SRGB
;
1778 fb
->Visual
.sRGBCapable
= true;
1781 /* mesaVis->sRGBCapable was set, user is asking for sRGB */
1782 bool srgb_cap_set
= mesaVis
->redBits
>= 8 && mesaVis
->sRGBCapable
;
1784 /* setup the hardware-based renderbuffers */
1785 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1786 _mesa_attach_and_own_rb(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
1787 rb
->need_srgb
= srgb_cap_set
;
1789 if (mesaVis
->doubleBufferMode
) {
1790 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1791 _mesa_attach_and_own_rb(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
1792 rb
->need_srgb
= srgb_cap_set
;
1796 * Assert here that the gl_config has an expected depth/stencil bit
1797 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1798 * which constructs the advertised configs.)
1800 if (mesaVis
->depthBits
== 24) {
1801 assert(mesaVis
->stencilBits
== 8);
1803 if (screen
->devinfo
.has_hiz_and_separate_stencil
) {
1804 rb
= intel_create_private_renderbuffer(screen
,
1805 MESA_FORMAT_Z24_UNORM_X8_UINT
,
1807 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1808 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_S_UINT8
,
1810 _mesa_attach_and_own_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1813 * Use combined depth/stencil. Note that the renderbuffer is
1814 * attached to two attachment points.
1816 rb
= intel_create_private_renderbuffer(screen
,
1817 MESA_FORMAT_Z24_UNORM_S8_UINT
,
1819 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1820 _mesa_attach_and_reference_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1823 else if (mesaVis
->depthBits
== 16) {
1824 assert(mesaVis
->stencilBits
== 0);
1825 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_Z_UNORM16
,
1827 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1830 assert(mesaVis
->depthBits
== 0);
1831 assert(mesaVis
->stencilBits
== 0);
1834 /* now add any/all software-based renderbuffers we may need */
1835 _swrast_add_soft_renderbuffers(fb
,
1836 false, /* never sw color */
1837 false, /* never sw depth */
1838 false, /* never sw stencil */
1839 mesaVis
->accumRedBits
> 0,
1840 false, /* never sw alpha */
1841 false /* never sw aux */ );
1842 driDrawPriv
->driverPrivate
= fb
;
1848 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1850 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1852 _mesa_reference_framebuffer(&fb
, NULL
);
1856 intel_cs_timestamp_frequency(struct intel_screen
*screen
)
1858 /* We shouldn't need to update gen_device_info.timestamp_frequency prior to
1859 * gen10, PCI-id is enough to figure it out.
1861 assert(screen
->devinfo
.gen
>= 10);
1865 ret
= intel_get_param(screen
, I915_PARAM_CS_TIMESTAMP_FREQUENCY
,
1869 "Kernel 4.15 required to read the CS timestamp frequency.\n");
1873 screen
->devinfo
.timestamp_frequency
= freq
;
1877 intel_detect_sseu(struct intel_screen
*screen
)
1879 assert(screen
->devinfo
.gen
>= 8);
1882 screen
->subslice_total
= -1;
1883 screen
->eu_total
= -1;
1885 ret
= intel_get_param(screen
, I915_PARAM_SUBSLICE_TOTAL
,
1886 &screen
->subslice_total
);
1887 if (ret
< 0 && ret
!= -EINVAL
)
1890 ret
= intel_get_param(screen
,
1891 I915_PARAM_EU_TOTAL
, &screen
->eu_total
);
1892 if (ret
< 0 && ret
!= -EINVAL
)
1895 /* Without this information, we cannot get the right Braswell brandstrings,
1896 * and we have to use conservative numbers for GPGPU on many platforms, but
1897 * otherwise, things will just work.
1899 if (screen
->subslice_total
< 1 || screen
->eu_total
< 1)
1901 "Kernel 4.1 required to properly query GPU properties.\n");
1906 screen
->subslice_total
= -1;
1907 screen
->eu_total
= -1;
1908 _mesa_warning(NULL
, "Failed to query GPU properties (%s).\n", strerror(-ret
));
1912 intel_init_bufmgr(struct intel_screen
*screen
)
1914 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1916 if (getenv("INTEL_NO_HW") != NULL
)
1917 screen
->no_hw
= true;
1919 bool bo_reuse
= false;
1920 int bo_reuse_mode
= driQueryOptioni(&screen
->optionCache
, "bo_reuse");
1921 switch (bo_reuse_mode
) {
1922 case DRI_CONF_BO_REUSE_DISABLED
:
1924 case DRI_CONF_BO_REUSE_ALL
:
1929 screen
->bufmgr
= brw_bufmgr_get_for_fd(&screen
->devinfo
, dri_screen
->fd
, bo_reuse
);
1930 if (screen
->bufmgr
== NULL
) {
1931 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1932 __func__
, __LINE__
);
1935 screen
->fd
= brw_bufmgr_get_fd(screen
->bufmgr
);
1937 if (!intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_NO_RELOC
)) {
1938 fprintf(stderr
, "[%s: %u] Kernel 3.9 required.\n", __func__
, __LINE__
);
1946 intel_detect_swizzling(struct intel_screen
*screen
)
1948 /* Broadwell PRM says:
1950 * "Before Gen8, there was a historical configuration control field to
1951 * swizzle address bit[6] for in X/Y tiling modes. This was set in three
1952 * different places: TILECTL[1:0], ARB_MODE[5:4], and
1953 * DISP_ARB_CTL[14:13].
1955 * For Gen8 and subsequent generations, the swizzle fields are all
1956 * reserved, and the CPU's memory controller performs all address
1957 * swizzling modifications."
1959 if (screen
->devinfo
.gen
>= 8)
1962 uint32_t tiling
= I915_TILING_X
;
1963 uint32_t swizzle_mode
= 0;
1964 struct brw_bo
*buffer
=
1965 brw_bo_alloc_tiled(screen
->bufmgr
, "swizzle test", 32768,
1966 BRW_MEMZONE_OTHER
, tiling
, 512, 0);
1970 brw_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1971 brw_bo_unreference(buffer
);
1973 return swizzle_mode
!= I915_BIT_6_SWIZZLE_NONE
;
1977 intel_detect_timestamp(struct intel_screen
*screen
)
1979 uint64_t dummy
= 0, last
= 0;
1980 int upper
, lower
, loops
;
1982 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1983 * TIMESTAMP register being shifted and the low 32bits always zero.
1985 * More recent kernels offer an interface to read the full 36bits
1988 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &dummy
) == 0)
1991 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1992 * upper 32bits for a rapidly changing timestamp.
1994 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &last
))
1998 for (loops
= 0; loops
< 10; loops
++) {
1999 /* The TIMESTAMP should change every 80ns, so several round trips
2000 * through the kernel should be enough to advance it.
2002 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &dummy
))
2005 upper
+= (dummy
>> 32) != (last
>> 32);
2006 if (upper
> 1) /* beware 32bit counter overflow */
2007 return 2; /* upper dword holds the low 32bits of the timestamp */
2009 lower
+= (dummy
& 0xffffffff) != (last
& 0xffffffff);
2011 return 1; /* timestamp is unshifted */
2016 /* No advancement? No timestamp! */
2021 * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
2023 * Some combinations of hardware and kernel versions allow this feature,
2024 * while others don't. Instead of trying to enumerate every case, just
2025 * try and write a register and see if works.
2028 intel_detect_pipelined_register(struct intel_screen
*screen
,
2029 int reg
, uint32_t expected_value
, bool reset
)
2034 struct brw_bo
*results
, *bo
;
2036 uint32_t offset
= 0;
2038 bool success
= false;
2040 /* Create a zero'ed temporary buffer for reading our results */
2041 results
= brw_bo_alloc(screen
->bufmgr
, "registers", 4096, BRW_MEMZONE_OTHER
);
2042 if (results
== NULL
)
2045 bo
= brw_bo_alloc(screen
->bufmgr
, "batchbuffer", 4096, BRW_MEMZONE_OTHER
);
2049 map
= brw_bo_map(NULL
, bo
, MAP_WRITE
);
2055 /* Write the register. */
2056 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
2058 *batch
++ = expected_value
;
2060 /* Save the register's value back to the buffer. */
2061 *batch
++ = MI_STORE_REGISTER_MEM
| (3 - 2);
2063 struct drm_i915_gem_relocation_entry reloc
= {
2064 .offset
= (char *) batch
- (char *) map
,
2065 .delta
= offset
* sizeof(uint32_t),
2066 .target_handle
= results
->gem_handle
,
2067 .read_domains
= I915_GEM_DOMAIN_INSTRUCTION
,
2068 .write_domain
= I915_GEM_DOMAIN_INSTRUCTION
,
2070 *batch
++ = reloc
.presumed_offset
+ reloc
.delta
;
2072 /* And afterwards clear the register */
2074 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
2079 *batch
++ = MI_BATCH_BUFFER_END
;
2081 struct drm_i915_gem_exec_object2 exec_objects
[2] = {
2083 .handle
= results
->gem_handle
,
2086 .handle
= bo
->gem_handle
,
2087 .relocation_count
= 1,
2088 .relocs_ptr
= (uintptr_t) &reloc
,
2092 struct drm_i915_gem_execbuffer2 execbuf
= {
2093 .buffers_ptr
= (uintptr_t) exec_objects
,
2095 .batch_len
= ALIGN((char *) batch
- (char *) map
, 8),
2096 .flags
= I915_EXEC_RENDER
,
2099 /* Don't bother with error checking - if the execbuf fails, the
2100 * value won't be written and we'll just report that there's no access.
2102 drmIoctl(screen
->fd
, DRM_IOCTL_I915_GEM_EXECBUFFER2
, &execbuf
);
2104 /* Check whether the value got written. */
2105 void *results_map
= brw_bo_map(NULL
, results
, MAP_READ
);
2107 success
= *((uint32_t *)results_map
+ offset
) == expected_value
;
2108 brw_bo_unmap(results
);
2112 brw_bo_unreference(bo
);
2114 brw_bo_unreference(results
);
2120 intel_detect_pipelined_so(struct intel_screen
*screen
)
2122 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2124 /* Supposedly, Broadwell just works. */
2125 if (devinfo
->gen
>= 8)
2128 if (devinfo
->gen
<= 6)
2131 /* See the big explanation about command parser versions below */
2132 if (screen
->cmd_parser_version
>= (devinfo
->is_haswell
? 7 : 2))
2135 /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
2136 * statistics registers), and we already reset it to zero before using it.
2138 return intel_detect_pipelined_register(screen
,
2139 GEN7_SO_WRITE_OFFSET(0),
2145 * Return array of MSAA modes supported by the hardware. The array is
2146 * zero-terminated and sorted in decreasing order.
2149 intel_supported_msaa_modes(const struct intel_screen
*screen
)
2151 static const int gen9_modes
[] = {16, 8, 4, 2, 0, -1};
2152 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
2153 static const int gen7_modes
[] = {8, 4, 0, -1};
2154 static const int gen6_modes
[] = {4, 0, -1};
2155 static const int gen4_modes
[] = {0, -1};
2157 if (screen
->devinfo
.gen
>= 9) {
2159 } else if (screen
->devinfo
.gen
>= 8) {
2161 } else if (screen
->devinfo
.gen
>= 7) {
2163 } else if (screen
->devinfo
.gen
== 6) {
2171 intel_loader_get_cap(const __DRIscreen
*dri_screen
, enum dri_loader_cap cap
)
2173 if (dri_screen
->dri2
.loader
&& dri_screen
->dri2
.loader
->base
.version
>= 4 &&
2174 dri_screen
->dri2
.loader
->getCapability
)
2175 return dri_screen
->dri2
.loader
->getCapability(dri_screen
->loaderPrivate
, cap
);
2177 if (dri_screen
->image
.loader
&& dri_screen
->image
.loader
->base
.version
>= 2 &&
2178 dri_screen
->image
.loader
->getCapability
)
2179 return dri_screen
->image
.loader
->getCapability(dri_screen
->loaderPrivate
, cap
);
2185 intel_allowed_format(__DRIscreen
*dri_screen
, mesa_format format
)
2187 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2189 /* Expose only BGRA ordering if the loader doesn't support RGBA ordering. */
2190 bool allow_rgba_ordering
= intel_loader_get_cap(dri_screen
, DRI_LOADER_CAP_RGBA_ORDERING
);
2191 if (!allow_rgba_ordering
&&
2192 (format
== MESA_FORMAT_R8G8B8A8_UNORM
||
2193 format
== MESA_FORMAT_R8G8B8X8_UNORM
||
2194 format
== MESA_FORMAT_R8G8B8A8_SRGB
))
2197 /* Shall we expose 10 bpc formats? */
2198 bool allow_rgb10_configs
= driQueryOptionb(&screen
->optionCache
,
2199 "allow_rgb10_configs");
2200 if (!allow_rgb10_configs
&&
2201 (format
== MESA_FORMAT_B10G10R10A2_UNORM
||
2202 format
== MESA_FORMAT_B10G10R10X2_UNORM
))
2205 /* Shall we expose 565 formats? */
2206 bool allow_rgb565_configs
= driQueryOptionb(&screen
->optionCache
,
2207 "allow_rgb565_configs");
2208 if (!allow_rgb565_configs
&& format
== MESA_FORMAT_B5G6R5_UNORM
)
2211 /* Shall we expose fp16 formats? */
2212 bool allow_fp16_configs
= driQueryOptionb(&screen
->optionCache
,
2213 "allow_fp16_configs");
2214 allow_fp16_configs
&= intel_loader_get_cap(dri_screen
, DRI_LOADER_CAP_FP16
);
2215 if (!allow_fp16_configs
&&
2216 (format
== MESA_FORMAT_RGBA_FLOAT16
||
2217 format
== MESA_FORMAT_RGBX_FLOAT16
))
2223 static __DRIconfig
**
2224 intel_screen_make_configs(__DRIscreen
*dri_screen
)
2226 static const mesa_format formats
[] = {
2227 MESA_FORMAT_B5G6R5_UNORM
,
2228 MESA_FORMAT_B8G8R8A8_UNORM
,
2229 MESA_FORMAT_B8G8R8X8_UNORM
,
2231 MESA_FORMAT_B8G8R8A8_SRGB
,
2232 MESA_FORMAT_B8G8R8X8_SRGB
,
2234 /* For 10 bpc, 30 bit depth framebuffers. */
2235 MESA_FORMAT_B10G10R10A2_UNORM
,
2236 MESA_FORMAT_B10G10R10X2_UNORM
,
2238 MESA_FORMAT_RGBA_FLOAT16
,
2239 MESA_FORMAT_RGBX_FLOAT16
,
2241 /* The 32-bit RGBA format must not precede the 32-bit BGRA format.
2242 * Likewise for RGBX and BGRX. Otherwise, the GLX client and the GLX
2243 * server may disagree on which format the GLXFBConfig represents,
2244 * resulting in swapped color channels.
2246 * The problem, as of 2017-05-30:
2247 * When matching a GLXFBConfig to a __DRIconfig, GLX ignores the channel
2248 * order and chooses the first __DRIconfig with the expected channel
2249 * sizes. Specifically, GLX compares the GLXFBConfig's and __DRIconfig's
2250 * __DRI_ATTRIB_{CHANNEL}_SIZE but ignores __DRI_ATTRIB_{CHANNEL}_MASK.
2252 * EGL does not suffer from this problem. It correctly compares the
2253 * channel masks when matching EGLConfig to __DRIconfig.
2256 /* Required by Android, for HAL_PIXEL_FORMAT_RGBA_8888. */
2257 MESA_FORMAT_R8G8B8A8_UNORM
,
2259 /* Required by Android, for HAL_PIXEL_FORMAT_RGBX_8888. */
2260 MESA_FORMAT_R8G8B8X8_UNORM
,
2262 MESA_FORMAT_R8G8B8A8_SRGB
,
2265 /* __DRI_ATTRIB_SWAP_COPY is not supported due to page flipping. */
2266 static const GLenum back_buffer_modes
[] = {
2267 __DRI_ATTRIB_SWAP_UNDEFINED
, __DRI_ATTRIB_SWAP_NONE
2270 static const uint8_t singlesample_samples
[1] = {0};
2272 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2273 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2274 uint8_t depth_bits
[4], stencil_bits
[4];
2275 __DRIconfig
**configs
= NULL
;
2277 unsigned num_formats
= ARRAY_SIZE(formats
);
2279 /* Generate singlesample configs, each without accumulation buffer
2280 * and with EGL_MUTABLE_RENDER_BUFFER_BIT_KHR.
2282 for (unsigned i
= 0; i
< num_formats
; i
++) {
2283 __DRIconfig
**new_configs
;
2284 int num_depth_stencil_bits
= 1;
2286 if (!intel_allowed_format(dri_screen
, formats
[i
]))
2289 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
2290 * buffer that has a different number of bits per pixel than the color
2291 * buffer, gen >= 6 supports this.
2294 stencil_bits
[0] = 0;
2296 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2297 if (devinfo
->gen
>= 8) {
2298 depth_bits
[num_depth_stencil_bits
] = 16;
2299 stencil_bits
[num_depth_stencil_bits
] = 0;
2300 num_depth_stencil_bits
++;
2302 if (devinfo
->gen
>= 6) {
2303 depth_bits
[num_depth_stencil_bits
] = 24;
2304 stencil_bits
[num_depth_stencil_bits
] = 8;
2305 num_depth_stencil_bits
++;
2308 depth_bits
[num_depth_stencil_bits
] = 24;
2309 stencil_bits
[num_depth_stencil_bits
] = 8;
2310 num_depth_stencil_bits
++;
2313 new_configs
= driCreateConfigs(formats
[i
],
2316 num_depth_stencil_bits
,
2317 back_buffer_modes
, 2,
2318 singlesample_samples
, 1,
2320 /*mutable_render_buffer*/ true);
2321 configs
= driConcatConfigs(configs
, new_configs
);
2324 /* Generate the minimum possible set of configs that include an
2325 * accumulation buffer.
2327 for (unsigned i
= 0; i
< num_formats
; i
++) {
2328 __DRIconfig
**new_configs
;
2330 if (!intel_allowed_format(dri_screen
, formats
[i
]))
2333 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2334 if (devinfo
->gen
>= 8) {
2336 stencil_bits
[0] = 0;
2337 } else if (devinfo
->gen
>= 6) {
2339 stencil_bits
[0] = 8;
2342 stencil_bits
[0] = 0;
2346 stencil_bits
[0] = 8;
2349 new_configs
= driCreateConfigs(formats
[i
],
2350 depth_bits
, stencil_bits
, 1,
2351 back_buffer_modes
, 1,
2352 singlesample_samples
, 1,
2353 true, false, false);
2354 configs
= driConcatConfigs(configs
, new_configs
);
2357 /* Generate multisample configs.
2359 * This loop breaks early, and hence is a no-op, on gen < 6.
2361 * Multisample configs must follow the singlesample configs in order to
2362 * work around an X server bug present in 1.12. The X server chooses to
2363 * associate the first listed RGBA888-Z24S8 config, regardless of its
2364 * sample count, with the 32-bit depth visual used for compositing.
2366 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
2367 * supported. Singlebuffer configs are not supported because no one wants
2370 for (unsigned i
= 0; i
< num_formats
; i
++) {
2371 if (devinfo
->gen
< 6)
2374 if (!intel_allowed_format(dri_screen
, formats
[i
]))
2377 __DRIconfig
**new_configs
;
2378 const int num_depth_stencil_bits
= 2;
2379 int num_msaa_modes
= 0;
2380 const uint8_t *multisample_samples
= NULL
;
2383 stencil_bits
[0] = 0;
2385 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
&& devinfo
->gen
>= 8) {
2387 stencil_bits
[1] = 0;
2390 stencil_bits
[1] = 8;
2393 if (devinfo
->gen
>= 9) {
2394 static const uint8_t multisample_samples_gen9
[] = {2, 4, 8, 16};
2395 multisample_samples
= multisample_samples_gen9
;
2396 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen9
);
2397 } else if (devinfo
->gen
== 8) {
2398 static const uint8_t multisample_samples_gen8
[] = {2, 4, 8};
2399 multisample_samples
= multisample_samples_gen8
;
2400 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen8
);
2401 } else if (devinfo
->gen
== 7) {
2402 static const uint8_t multisample_samples_gen7
[] = {4, 8};
2403 multisample_samples
= multisample_samples_gen7
;
2404 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen7
);
2405 } else if (devinfo
->gen
== 6) {
2406 static const uint8_t multisample_samples_gen6
[] = {4};
2407 multisample_samples
= multisample_samples_gen6
;
2408 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen6
);
2411 new_configs
= driCreateConfigs(formats
[i
],
2414 num_depth_stencil_bits
,
2415 back_buffer_modes
, 1,
2416 multisample_samples
,
2418 false, false, false);
2419 configs
= driConcatConfigs(configs
, new_configs
);
2422 if (configs
== NULL
) {
2423 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
2432 set_max_gl_versions(struct intel_screen
*screen
)
2434 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
2435 const bool has_astc
= screen
->devinfo
.gen
>= 9;
2437 switch (screen
->devinfo
.gen
) {
2442 dri_screen
->max_gl_core_version
= 46;
2443 dri_screen
->max_gl_compat_version
= 30;
2444 dri_screen
->max_gl_es1_version
= 11;
2445 dri_screen
->max_gl_es2_version
= has_astc
? 32 : 31;
2448 dri_screen
->max_gl_core_version
= 33;
2449 if (can_do_pipelined_register_writes(screen
)) {
2450 dri_screen
->max_gl_core_version
= 42;
2451 if (screen
->devinfo
.is_haswell
&& can_do_compute_dispatch(screen
))
2452 dri_screen
->max_gl_core_version
= 43;
2453 if (screen
->devinfo
.is_haswell
&& can_do_mi_math_and_lrr(screen
))
2454 dri_screen
->max_gl_core_version
= 45;
2456 dri_screen
->max_gl_compat_version
= 30;
2457 dri_screen
->max_gl_es1_version
= 11;
2458 dri_screen
->max_gl_es2_version
= screen
->devinfo
.is_haswell
? 31 : 30;
2461 dri_screen
->max_gl_core_version
= 33;
2462 dri_screen
->max_gl_compat_version
= 30;
2463 dri_screen
->max_gl_es1_version
= 11;
2464 dri_screen
->max_gl_es2_version
= 30;
2468 dri_screen
->max_gl_core_version
= 0;
2469 dri_screen
->max_gl_compat_version
= 21;
2470 dri_screen
->max_gl_es1_version
= 11;
2471 dri_screen
->max_gl_es2_version
= 20;
2474 unreachable("unrecognized intel_screen::gen");
2479 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
2481 struct brw_context
*brw
= (struct brw_context
*)data
;
2484 va_start(args
, fmt
);
2486 _mesa_gl_vdebugf(&brw
->ctx
, &msg_id
,
2487 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
2488 MESA_DEBUG_TYPE_OTHER
,
2489 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
2494 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
2496 struct brw_context
*brw
= (struct brw_context
*)data
;
2499 va_start(args
, fmt
);
2501 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
2503 va_copy(args_copy
, args
);
2504 vfprintf(stderr
, fmt
, args_copy
);
2508 if (brw
->perf_debug
) {
2510 _mesa_gl_vdebugf(&brw
->ctx
, &msg_id
,
2511 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
2512 MESA_DEBUG_TYPE_PERFORMANCE
,
2513 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
2519 * This is the driver specific part of the createNewScreen entry point.
2520 * Called when using DRI2.
2522 * \return the struct gl_config supported by this driver
2525 __DRIconfig
**intelInitScreen2(__DRIscreen
*dri_screen
)
2527 struct intel_screen
*screen
;
2529 if (dri_screen
->image
.loader
) {
2530 } else if (dri_screen
->dri2
.loader
->base
.version
<= 2 ||
2531 dri_screen
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
2533 "\nERROR! DRI2 loader with getBuffersWithFormat() "
2534 "support required\n");
2538 /* Allocate the private area */
2539 screen
= rzalloc(NULL
, struct intel_screen
);
2541 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
2544 /* parse information in __driConfigOptions */
2545 driOptionCache options
;
2546 memset(&options
, 0, sizeof(options
));
2548 driParseOptionInfo(&options
, brw_config_options
.xml
);
2549 driParseConfigFiles(&screen
->optionCache
, &options
, dri_screen
->myNum
,
2550 "i965", NULL
, NULL
, 0);
2551 driDestroyOptionCache(&options
);
2553 screen
->driScrnPriv
= dri_screen
;
2554 dri_screen
->driverPrivate
= (void *) screen
;
2556 if (!gen_get_device_info_from_fd(dri_screen
->fd
, &screen
->devinfo
))
2559 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2560 screen
->deviceID
= devinfo
->chipset_id
;
2561 screen
->no_hw
= devinfo
->no_hw
;
2563 if (devinfo
->gen
>= 12) {
2564 fprintf(stderr
, "gen12 and newer are not supported on i965\n");
2568 if (!intel_init_bufmgr(screen
))
2571 brw_process_intel_debug_variable();
2573 if ((INTEL_DEBUG
& DEBUG_SHADER_TIME
) && devinfo
->gen
< 7) {
2575 "shader_time debugging requires gen7 (Ivybridge) or better.\n");
2576 INTEL_DEBUG
&= ~DEBUG_SHADER_TIME
;
2579 if (intel_get_integer(screen
, I915_PARAM_MMAP_GTT_VERSION
) >= 1) {
2580 /* Theorectically unlimited! At least for individual objects...
2582 * Currently the entire (global) address space for all GTT maps is
2583 * limited to 64bits. That is all objects on the system that are
2584 * setup for GTT mmapping must fit within 64bits. An attempt to use
2585 * one that exceeds the limit with fail in brw_bo_map_gtt().
2587 * Long before we hit that limit, we will be practically limited by
2588 * that any single object must fit in physical memory (RAM). The upper
2589 * limit on the CPU's address space is currently 48bits (Skylake), of
2590 * which only 39bits can be physical memory. (The GPU itself also has
2591 * a 48bit addressable virtual space.) We can fit over 32 million
2592 * objects of the current maximum allocable size before running out
2595 screen
->max_gtt_map_object_size
= UINT64_MAX
;
2597 /* Estimate the size of the mappable aperture into the GTT. There's an
2598 * ioctl to get the whole GTT size, but not one to get the mappable subset.
2599 * It turns out it's basically always 256MB, though some ancient hardware
2602 uint32_t gtt_size
= 256 * 1024 * 1024;
2604 /* We don't want to map two objects such that a memcpy between them would
2605 * just fault one mapping in and then the other over and over forever. So
2606 * we would need to divide the GTT size by 2. Additionally, some GTT is
2607 * taken up by things like the framebuffer and the ringbuffer and such, so
2608 * be more conservative.
2610 screen
->max_gtt_map_object_size
= gtt_size
/ 4;
2613 screen
->aperture_threshold
= get_aperture_size(screen
->fd
) * 3 / 4;
2615 screen
->hw_has_swizzling
= intel_detect_swizzling(screen
);
2616 screen
->hw_has_timestamp
= intel_detect_timestamp(screen
);
2618 isl_device_init(&screen
->isl_dev
, &screen
->devinfo
,
2619 screen
->hw_has_swizzling
);
2621 if (devinfo
->gen
>= 10)
2622 intel_cs_timestamp_frequency(screen
);
2624 /* GENs prior to 8 do not support EU/Subslice info */
2625 if (devinfo
->gen
>= 8) {
2626 intel_detect_sseu(screen
);
2627 } else if (devinfo
->gen
== 7) {
2628 screen
->subslice_total
= 1 << (devinfo
->gt
- 1);
2631 /* Gen7-7.5 kernel requirements / command parser saga:
2634 * Haswell and Baytrail cannot use any privileged batchbuffer features.
2636 * Ivybridge has aliasing PPGTT on by default, which accidentally marks
2637 * all batches secure, allowing them to use any feature with no checking.
2638 * This is effectively equivalent to a command parser version of
2639 * \infinity - everything is possible.
2641 * The command parser does not exist, and querying the version will
2645 * The kernel enables the command parser by default, for systems with
2646 * aliasing PPGTT enabled (Ivybridge and Haswell). However, the
2647 * hardware checker is still enabled, so Haswell and Baytrail cannot
2650 * Ivybridge goes from "everything is possible" to "only what the
2651 * command parser allows" (if the user boots with i915.cmd_parser=0,
2652 * then everything is possible again). We can only safely use features
2653 * allowed by the supported command parser version.
2655 * Annoyingly, I915_PARAM_CMD_PARSER_VERSION reports the static version
2656 * implemented by the kernel, even if it's turned off. So, checking
2657 * for version > 0 does not mean that you can write registers. We have
2658 * to try it and see. The version does, however, indicate the age of
2661 * Instead of matching the hardware checker's behavior of converting
2662 * privileged commands to MI_NOOP, it makes execbuf2 start returning
2663 * -EINVAL, making it dangerous to try and use privileged features.
2665 * Effective command parser versions:
2666 * - Haswell: 0 (reporting 1, writes don't work)
2667 * - Baytrail: 0 (reporting 1, writes don't work)
2668 * - Ivybridge: 1 (enabled) or infinite (disabled)
2671 * Baytrail aliasing PPGTT is enabled, making it like Ivybridge:
2672 * effectively version 1 (enabled) or infinite (disabled).
2674 * - v3.19: f1f55cc0556031c8ee3fe99dae7251e78b9b653b
2675 * Command parser v2 supports predicate writes.
2677 * - Haswell: 0 (reporting 1, writes don't work)
2678 * - Baytrail: 2 (enabled) or infinite (disabled)
2679 * - Ivybridge: 2 (enabled) or infinite (disabled)
2681 * So version >= 2 is enough to know that Ivybridge and Baytrail
2682 * will work. Haswell still can't do anything.
2684 * - v4.0: Version 3 happened. Largely not relevant.
2686 * - v4.1: 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b
2687 * L3 config registers are properly saved and restored as part
2688 * of the hardware context. We can approximately detect this point
2689 * in time by checking if I915_PARAM_REVISION is recognized - it
2690 * landed in a later commit, but in the same release cycle.
2692 * - v4.2: 245054a1fe33c06ad233e0d58a27ec7b64db9284
2693 * Command parser finally gains secure batch promotion. On Haswell,
2694 * the hardware checker gets disabled, which finally allows it to do
2695 * privileged commands.
2697 * I915_PARAM_CMD_PARSER_VERSION reports 3. Effective versions:
2698 * - Haswell: 3 (enabled) or 0 (disabled)
2699 * - Baytrail: 3 (enabled) or infinite (disabled)
2700 * - Ivybridge: 3 (enabled) or infinite (disabled)
2702 * Unfortunately, detecting this point in time is tricky, because
2703 * no version bump happened when this important change occurred.
2704 * On Haswell, if we can write any register, then the kernel is at
2705 * least this new, and we can start trusting the version number.
2707 * - v4.4: 2bbe6bbb0dc94fd4ce287bdac9e1bd184e23057b and
2708 * Command parser reaches version 4, allowing access to Haswell
2709 * atomic scratch and chicken3 registers. If version >= 4, we know
2710 * the kernel is new enough to support privileged features on all
2711 * hardware. However, the user might have disabled it...and the
2712 * kernel will still report version 4. So we still have to guess
2715 * - v4.4: 7b9748cb513a6bef4af87b79f0da3ff7e8b56cd8
2716 * Command parser v5 whitelists indirect compute shader dispatch
2717 * registers, needed for OpenGL 4.3 and later.
2720 * Command parser v7 lets us use MI_MATH on Haswell.
2722 * Additionally, the kernel begins reporting version 0 when
2723 * the command parser is disabled, allowing us to skip the
2724 * guess-and-check step on Haswell. Unfortunately, this also
2725 * means that we can no longer use it as an indicator of the
2726 * age of the kernel.
2728 if (intel_get_param(screen
, I915_PARAM_CMD_PARSER_VERSION
,
2729 &screen
->cmd_parser_version
) < 0) {
2730 /* Command parser does not exist - getparam is unrecognized */
2731 screen
->cmd_parser_version
= 0;
2734 /* Kernel 4.13 retuired for exec object capture */
2735 if (intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_CAPTURE
)) {
2736 screen
->kernel_features
|= KERNEL_ALLOWS_EXEC_CAPTURE
;
2739 if (intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_BATCH_FIRST
)) {
2740 screen
->kernel_features
|= KERNEL_ALLOWS_EXEC_BATCH_FIRST
;
2743 if (!intel_detect_pipelined_so(screen
)) {
2744 /* We can't do anything, so the effective version is 0. */
2745 screen
->cmd_parser_version
= 0;
2747 screen
->kernel_features
|= KERNEL_ALLOWS_SOL_OFFSET_WRITES
;
2750 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 2)
2751 screen
->kernel_features
|= KERNEL_ALLOWS_PREDICATE_WRITES
;
2753 /* Haswell requires command parser version 4 in order to have L3
2754 * atomic scratch1 and chicken3 bits
2756 if (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 4) {
2757 screen
->kernel_features
|=
2758 KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3
;
2761 /* Haswell requires command parser version 6 in order to write to the
2762 * MI_MATH GPR registers, and version 7 in order to use
2763 * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
2765 if (devinfo
->gen
>= 8 ||
2766 (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 7)) {
2767 screen
->kernel_features
|= KERNEL_ALLOWS_MI_MATH_AND_LRR
;
2770 /* Gen7 needs at least command parser version 5 to support compute */
2771 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 5)
2772 screen
->kernel_features
|= KERNEL_ALLOWS_COMPUTE_DISPATCH
;
2774 if (intel_get_boolean(screen
, I915_PARAM_HAS_CONTEXT_ISOLATION
))
2775 screen
->kernel_features
|= KERNEL_ALLOWS_CONTEXT_ISOLATION
;
2777 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
2779 screen
->winsys_msaa_samples_override
=
2780 intel_quantize_num_samples(screen
, atoi(force_msaa
));
2781 printf("Forcing winsys sample count to %d\n",
2782 screen
->winsys_msaa_samples_override
);
2784 screen
->winsys_msaa_samples_override
= -1;
2787 set_max_gl_versions(screen
);
2789 /* Notification of GPU resets requires hardware contexts and a kernel new
2790 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
2791 * supported, calling it with a context of 0 will either generate EPERM or
2792 * no error. If the ioctl is not supported, it always generate EINVAL.
2793 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
2794 * extension to the loader.
2796 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
2798 if (devinfo
->gen
>= 6) {
2799 struct drm_i915_reset_stats stats
;
2800 memset(&stats
, 0, sizeof(stats
));
2802 const int ret
= drmIoctl(screen
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
2804 screen
->has_context_reset_notification
=
2805 (ret
!= -1 || errno
!= EINVAL
);
2808 dri_screen
->extensions
= !screen
->has_context_reset_notification
2809 ? screenExtensions
: intelRobustScreenExtensions
;
2811 screen
->compiler
= brw_compiler_create(screen
, devinfo
);
2812 screen
->compiler
->shader_debug_log
= shader_debug_log_mesa
;
2813 screen
->compiler
->shader_perf_log
= shader_perf_log_mesa
;
2815 /* Changing the meaning of constant buffer pointers from a dynamic state
2816 * offset to an absolute address is only safe if the kernel isolates other
2817 * contexts from our changes.
2819 screen
->compiler
->constant_buffer_0_is_relative
= devinfo
->gen
< 8 ||
2820 !(screen
->kernel_features
& KERNEL_ALLOWS_CONTEXT_ISOLATION
);
2822 screen
->compiler
->glsl_compiler_options
[MESA_SHADER_VERTEX
].PositionAlwaysInvariant
= driQueryOptionb(&screen
->optionCache
, "vs_position_always_invariant");
2824 screen
->compiler
->supports_pull_constants
= true;
2825 screen
->compiler
->compact_params
= true;
2826 screen
->compiler
->lower_variable_group_size
= true;
2828 screen
->has_exec_fence
=
2829 intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_FENCE
);
2831 intel_screen_init_surface_formats(screen
);
2833 if (INTEL_DEBUG
& (DEBUG_BATCH
| DEBUG_SUBMIT
)) {
2834 unsigned int caps
= intel_get_integer(screen
, I915_PARAM_HAS_SCHEDULER
);
2836 fprintf(stderr
, "Kernel scheduler detected: %08x\n", caps
);
2837 if (caps
& I915_SCHEDULER_CAP_PRIORITY
)
2838 fprintf(stderr
, " - User priority sorting enabled\n");
2839 if (caps
& I915_SCHEDULER_CAP_PREEMPTION
)
2840 fprintf(stderr
, " - Preemption enabled\n");
2844 brw_disk_cache_init(screen
);
2846 return (const __DRIconfig
**) intel_screen_make_configs(dri_screen
);
2849 struct intel_buffer
{
2854 static __DRIbuffer
*
2855 intelAllocateBuffer(__DRIscreen
*dri_screen
,
2856 unsigned attachment
, unsigned format
,
2857 int width
, int height
)
2859 struct intel_buffer
*intelBuffer
;
2860 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2862 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
2863 attachment
== __DRI_BUFFER_BACK_LEFT
);
2865 intelBuffer
= calloc(1, sizeof *intelBuffer
);
2866 if (intelBuffer
== NULL
)
2869 /* The front and back buffers are color buffers, which are X tiled. GEN9+
2870 * supports Y tiled and compressed buffers, but there is no way to plumb that
2871 * through to here. */
2873 int cpp
= format
/ 8;
2874 intelBuffer
->bo
= brw_bo_alloc_tiled_2d(screen
->bufmgr
,
2875 "intelAllocateBuffer",
2880 I915_TILING_X
, &pitch
,
2883 if (intelBuffer
->bo
== NULL
) {
2888 brw_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
2890 intelBuffer
->base
.attachment
= attachment
;
2891 intelBuffer
->base
.cpp
= cpp
;
2892 intelBuffer
->base
.pitch
= pitch
;
2894 return &intelBuffer
->base
;
2898 intelReleaseBuffer(__DRIscreen
*dri_screen
, __DRIbuffer
*buffer
)
2900 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
2902 brw_bo_unreference(intelBuffer
->bo
);
2906 static const struct __DriverAPIRec brw_driver_api
= {
2907 .InitScreen
= intelInitScreen2
,
2908 .DestroyScreen
= intelDestroyScreen
,
2909 .CreateContext
= brwCreateContext
,
2910 .DestroyContext
= intelDestroyContext
,
2911 .CreateBuffer
= intelCreateBuffer
,
2912 .DestroyBuffer
= intelDestroyBuffer
,
2913 .MakeCurrent
= intelMakeCurrent
,
2914 .UnbindContext
= intelUnbindContext
,
2915 .AllocateBuffer
= intelAllocateBuffer
,
2916 .ReleaseBuffer
= intelReleaseBuffer
2919 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
2920 .base
= { __DRI_DRIVER_VTABLE
, 1 },
2921 .vtable
= &brw_driver_api
,
2924 static const __DRIextension
*brw_driver_extensions
[] = {
2925 &driCoreExtension
.base
,
2926 &driImageDriverExtension
.base
,
2927 &driDRI2Extension
.base
,
2929 &brw_config_options
.base
,
2933 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
2935 globalDriverAPI
= &brw_driver_api
;
2937 return brw_driver_extensions
;