1 /**************************************************************************
3 * Copyright 2003 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
31 #include "main/glheader.h"
32 #include "main/context.h"
33 #include "main/framebuffer.h"
34 #include "main/renderbuffer.h"
35 #include "main/texobj.h"
36 #include "main/hash.h"
37 #include "main/fbobject.h"
38 #include "main/version.h"
39 #include "swrast/s_renderbuffer.h"
40 #include "util/ralloc.h"
45 static const __DRIconfigOptionsExtension brw_config_options
= {
46 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
49 DRI_CONF_SECTION_PERFORMANCE
50 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_ALWAYS_SYNC
)
51 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
52 * DRI_CONF_BO_REUSE_ALL
54 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
55 DRI_CONF_DESC_BEGIN(en
, "Buffer object reuse")
56 DRI_CONF_ENUM(0, "Disable buffer object reuse")
57 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
61 DRI_CONF_OPT_BEGIN_B(hiz
, "true")
62 DRI_CONF_DESC(en
, "Enable Hierarchical Z on gen6+")
65 DRI_CONF_OPT_BEGIN_B(disable_derivative_optimization
, "false")
66 DRI_CONF_DESC(en
, "Derivatives with finer granularity by default")
70 DRI_CONF_SECTION_QUALITY
71 DRI_CONF_FORCE_S3TC_ENABLE("false")
73 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
74 DRI_CONF_DESC(en
, "Clamp the value of GL_MAX_SAMPLES to the "
75 "given integer. If negative, then do not clamp.")
79 DRI_CONF_SECTION_DEBUG
80 DRI_CONF_NO_RAST("false")
81 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
82 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
83 DRI_CONF_DISABLE_THROTTLING("false")
84 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
85 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
86 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
87 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
89 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
90 DRI_CONF_DESC(en
, "Perform code generation at shader link time.")
96 #include "intel_batchbuffer.h"
97 #include "intel_buffers.h"
98 #include "intel_bufmgr.h"
99 #include "intel_chipset.h"
100 #include "intel_fbo.h"
101 #include "intel_mipmap_tree.h"
102 #include "intel_screen.h"
103 #include "intel_tex.h"
104 #include "intel_image.h"
106 #include "brw_context.h"
108 #include "i915_drm.h"
111 * For debugging purposes, this returns a time in seconds.
118 clock_gettime(CLOCK_MONOTONIC
, &tp
);
120 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
124 aub_dump_bmp(struct gl_context
*ctx
)
126 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
128 for (int i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
129 struct intel_renderbuffer
*irb
=
130 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
132 if (irb
&& irb
->mt
) {
133 enum aub_dump_bmp_format format
;
135 switch (irb
->Base
.Base
.Format
) {
136 case MESA_FORMAT_B8G8R8A8_UNORM
:
137 case MESA_FORMAT_B8G8R8X8_UNORM
:
138 format
= AUB_DUMP_BMP_FORMAT_ARGB_8888
;
144 drm_intel_gem_bo_aub_dump_bmp(irb
->mt
->bo
,
147 irb
->Base
.Base
.Width
,
148 irb
->Base
.Base
.Height
,
156 static const __DRItexBufferExtension intelTexBufferExtension
= {
157 .base
= { __DRI_TEX_BUFFER
, 3 },
159 .setTexBuffer
= intelSetTexBuffer
,
160 .setTexBuffer2
= intelSetTexBuffer2
,
161 .releaseTexBuffer
= NULL
,
165 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
166 __DRIdrawable
*dPriv
,
168 enum __DRI2throttleReason reason
)
170 struct brw_context
*brw
= cPriv
->driverPrivate
;
175 struct gl_context
*ctx
= &brw
->ctx
;
177 FLUSH_VERTICES(ctx
, 0);
179 if (flags
& __DRI2_FLUSH_DRAWABLE
)
180 intel_resolve_for_dri2_flush(brw
, dPriv
);
182 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
||
183 reason
== __DRI2_THROTTLE_FLUSHFRONT
) {
184 brw
->need_throttle
= true;
187 intel_batchbuffer_flush(brw
);
189 if (INTEL_DEBUG
& DEBUG_AUB
) {
195 * Provides compatibility with loaders that only support the older (version
196 * 1-3) flush interface.
198 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
201 intel_dri2_flush(__DRIdrawable
*drawable
)
203 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
204 __DRI2_FLUSH_DRAWABLE
,
205 __DRI2_THROTTLE_SWAPBUFFER
);
208 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
209 .base
= { __DRI2_FLUSH
, 4 },
211 .flush
= intel_dri2_flush
,
212 .invalidate
= dri2InvalidateDrawable
,
213 .flush_with_flags
= intel_dri2_flush_with_flags
,
216 static struct intel_image_format intel_image_formats
[] = {
217 { __DRI_IMAGE_FOURCC_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
218 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
220 { __DRI_IMAGE_FOURCC_ABGR8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
221 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
223 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
224 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
226 { __DRI_IMAGE_FOURCC_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
227 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
229 { __DRI_IMAGE_FOURCC_XBGR8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
230 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 }, } },
232 { __DRI_IMAGE_FOURCC_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
233 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
235 { __DRI_IMAGE_FOURCC_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
236 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
237 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
238 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
240 { __DRI_IMAGE_FOURCC_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
241 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
242 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
243 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
245 { __DRI_IMAGE_FOURCC_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
246 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
247 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
248 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
250 { __DRI_IMAGE_FOURCC_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
251 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
252 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
253 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
255 { __DRI_IMAGE_FOURCC_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
256 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
257 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
258 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
260 { __DRI_IMAGE_FOURCC_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
261 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
262 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
264 { __DRI_IMAGE_FOURCC_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
265 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
266 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
268 /* For YUYV buffers, we set up two overlapping DRI images and treat
269 * them as planar buffers in the compositors. Plane 0 is GR88 and
270 * samples YU or YV pairs and places Y into the R component, while
271 * plane 1 is ARGB and samples YUYV clusters and places pairs and
272 * places U into the G component and V into A. This lets the
273 * texture sampler interpolate the Y components correctly when
274 * sampling from plane 0, and interpolate U and V correctly when
275 * sampling from plane 1. */
276 { __DRI_IMAGE_FOURCC_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
277 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
278 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } }
282 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
284 uint32_t tiling
, swizzle
;
285 drm_intel_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
287 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
288 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
289 func
, image
->offset
);
293 static struct intel_image_format
*
294 intel_image_format_lookup(int fourcc
)
296 struct intel_image_format
*f
= NULL
;
298 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
299 if (intel_image_formats
[i
].fourcc
== fourcc
) {
300 f
= &intel_image_formats
[i
];
309 intel_allocate_image(int dri_format
, void *loaderPrivate
)
313 image
= calloc(1, sizeof *image
);
317 image
->dri_format
= dri_format
;
320 image
->format
= driImageFormatToGLFormat(dri_format
);
321 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
322 image
->format
== MESA_FORMAT_NONE
) {
327 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
328 image
->data
= loaderPrivate
;
334 * Sets up a DRIImage structure to point to a slice out of a miptree.
337 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
338 struct intel_mipmap_tree
*mt
, GLuint level
,
341 intel_miptree_make_shareable(brw
, mt
);
343 intel_miptree_check_level_layer(mt
, level
, zoffset
);
345 image
->width
= minify(mt
->physical_width0
, level
- mt
->first_level
);
346 image
->height
= minify(mt
->physical_height0
, level
- mt
->first_level
);
347 image
->pitch
= mt
->pitch
;
349 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
353 drm_intel_bo_unreference(image
->bo
);
355 drm_intel_bo_reference(mt
->bo
);
359 intel_create_image_from_name(__DRIscreen
*screen
,
360 int width
, int height
, int format
,
361 int name
, int pitch
, void *loaderPrivate
)
363 struct intel_screen
*intelScreen
= screen
->driverPrivate
;
367 image
= intel_allocate_image(format
, loaderPrivate
);
371 if (image
->format
== MESA_FORMAT_NONE
)
374 cpp
= _mesa_get_format_bytes(image
->format
);
376 image
->width
= width
;
377 image
->height
= height
;
378 image
->pitch
= pitch
* cpp
;
379 image
->bo
= drm_intel_bo_gem_create_from_name(intelScreen
->bufmgr
, "image",
390 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
391 int renderbuffer
, void *loaderPrivate
)
394 struct brw_context
*brw
= context
->driverPrivate
;
395 struct gl_context
*ctx
= &brw
->ctx
;
396 struct gl_renderbuffer
*rb
;
397 struct intel_renderbuffer
*irb
;
399 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
401 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
405 irb
= intel_renderbuffer(rb
);
406 intel_miptree_make_shareable(brw
, irb
->mt
);
407 image
= calloc(1, sizeof *image
);
411 image
->internal_format
= rb
->InternalFormat
;
412 image
->format
= rb
->Format
;
414 image
->data
= loaderPrivate
;
415 drm_intel_bo_unreference(image
->bo
);
416 image
->bo
= irb
->mt
->bo
;
417 drm_intel_bo_reference(irb
->mt
->bo
);
418 image
->width
= rb
->Width
;
419 image
->height
= rb
->Height
;
420 image
->pitch
= irb
->mt
->pitch
;
421 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
422 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
424 rb
->NeedsFinishRenderTexture
= true;
429 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
430 unsigned texture
, int zoffset
,
436 struct brw_context
*brw
= context
->driverPrivate
;
437 struct gl_texture_object
*obj
;
438 struct intel_texture_object
*iobj
;
441 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
442 if (!obj
|| obj
->Target
!= target
) {
443 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
447 if (target
== GL_TEXTURE_CUBE_MAP
)
450 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
451 iobj
= intel_texture_object(obj
);
452 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
453 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
457 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
458 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
462 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
463 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
466 image
= calloc(1, sizeof *image
);
468 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
472 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
473 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
474 image
->data
= loaderPrivate
;
475 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
476 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
477 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
478 if (image
->dri_format
== MESA_FORMAT_NONE
) {
479 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
484 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
489 intel_destroy_image(__DRIimage
*image
)
491 drm_intel_bo_unreference(image
->bo
);
496 intel_create_image(__DRIscreen
*screen
,
497 int width
, int height
, int format
,
502 struct intel_screen
*intelScreen
= screen
->driverPrivate
;
507 tiling
= I915_TILING_X
;
508 if (use
& __DRI_IMAGE_USE_CURSOR
) {
509 if (width
!= 64 || height
!= 64)
511 tiling
= I915_TILING_NONE
;
514 if (use
& __DRI_IMAGE_USE_LINEAR
)
515 tiling
= I915_TILING_NONE
;
517 image
= intel_allocate_image(format
, loaderPrivate
);
522 cpp
= _mesa_get_format_bytes(image
->format
);
523 image
->bo
= drm_intel_bo_alloc_tiled(intelScreen
->bufmgr
, "image",
524 width
, height
, cpp
, &tiling
,
526 if (image
->bo
== NULL
) {
530 image
->width
= width
;
531 image
->height
= height
;
532 image
->pitch
= pitch
;
538 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
541 case __DRI_IMAGE_ATTRIB_STRIDE
:
542 *value
= image
->pitch
;
544 case __DRI_IMAGE_ATTRIB_HANDLE
:
545 *value
= image
->bo
->handle
;
547 case __DRI_IMAGE_ATTRIB_NAME
:
548 return !drm_intel_bo_flink(image
->bo
, (uint32_t *) value
);
549 case __DRI_IMAGE_ATTRIB_FORMAT
:
550 *value
= image
->dri_format
;
552 case __DRI_IMAGE_ATTRIB_WIDTH
:
553 *value
= image
->width
;
555 case __DRI_IMAGE_ATTRIB_HEIGHT
:
556 *value
= image
->height
;
558 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
559 if (image
->planar_format
== NULL
)
561 *value
= image
->planar_format
->components
;
563 case __DRI_IMAGE_ATTRIB_FD
:
564 if (drm_intel_bo_gem_export_to_prime(image
->bo
, value
) == 0)
573 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
577 image
= calloc(1, sizeof *image
);
581 drm_intel_bo_reference(orig_image
->bo
);
582 image
->bo
= orig_image
->bo
;
583 image
->internal_format
= orig_image
->internal_format
;
584 image
->planar_format
= orig_image
->planar_format
;
585 image
->dri_format
= orig_image
->dri_format
;
586 image
->format
= orig_image
->format
;
587 image
->offset
= orig_image
->offset
;
588 image
->width
= orig_image
->width
;
589 image
->height
= orig_image
->height
;
590 image
->pitch
= orig_image
->pitch
;
591 image
->tile_x
= orig_image
->tile_x
;
592 image
->tile_y
= orig_image
->tile_y
;
593 image
->has_depthstencil
= orig_image
->has_depthstencil
;
594 image
->data
= loaderPrivate
;
596 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
597 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
603 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
605 if (use
& __DRI_IMAGE_USE_CURSOR
) {
606 if (image
->width
!= 64 || image
->height
!= 64)
614 intel_create_image_from_names(__DRIscreen
*screen
,
615 int width
, int height
, int fourcc
,
616 int *names
, int num_names
,
617 int *strides
, int *offsets
,
620 struct intel_image_format
*f
= NULL
;
624 if (screen
== NULL
|| names
== NULL
|| num_names
!= 1)
627 f
= intel_image_format_lookup(fourcc
);
631 image
= intel_create_image_from_name(screen
, width
, height
,
632 __DRI_IMAGE_FORMAT_NONE
,
633 names
[0], strides
[0],
639 image
->planar_format
= f
;
640 for (i
= 0; i
< f
->nplanes
; i
++) {
641 index
= f
->planes
[i
].buffer_index
;
642 image
->offsets
[index
] = offsets
[index
];
643 image
->strides
[index
] = strides
[index
];
650 intel_create_image_from_fds(__DRIscreen
*screen
,
651 int width
, int height
, int fourcc
,
652 int *fds
, int num_fds
, int *strides
, int *offsets
,
655 struct intel_screen
*intelScreen
= screen
->driverPrivate
;
656 struct intel_image_format
*f
;
660 if (fds
== NULL
|| num_fds
!= 1)
663 f
= intel_image_format_lookup(fourcc
);
668 image
= intel_allocate_image(f
->planes
[0].dri_format
, loaderPrivate
);
670 image
= intel_allocate_image(__DRI_IMAGE_FORMAT_NONE
, loaderPrivate
);
675 image
->bo
= drm_intel_bo_gem_create_from_prime(intelScreen
->bufmgr
,
677 height
* strides
[0]);
678 if (image
->bo
== NULL
) {
682 image
->width
= width
;
683 image
->height
= height
;
684 image
->pitch
= strides
[0];
686 image
->planar_format
= f
;
687 for (i
= 0; i
< f
->nplanes
; i
++) {
688 index
= f
->planes
[i
].buffer_index
;
689 image
->offsets
[index
] = offsets
[index
];
690 image
->strides
[index
] = strides
[index
];
693 if (f
->nplanes
== 1) {
694 image
->offset
= image
->offsets
[0];
695 intel_image_warn_if_unaligned(image
, __FUNCTION__
);
702 intel_create_image_from_dma_bufs(__DRIscreen
*screen
,
703 int width
, int height
, int fourcc
,
704 int *fds
, int num_fds
,
705 int *strides
, int *offsets
,
706 enum __DRIYUVColorSpace yuv_color_space
,
707 enum __DRISampleRange sample_range
,
708 enum __DRIChromaSiting horizontal_siting
,
709 enum __DRIChromaSiting vertical_siting
,
714 struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
716 /* For now only packed formats that have native sampling are supported. */
717 if (!f
|| f
->nplanes
!= 1) {
718 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
722 image
= intel_create_image_from_fds(screen
, width
, height
, fourcc
, fds
,
723 num_fds
, strides
, offsets
,
727 * Invalid parameters and any inconsistencies between are assumed to be
728 * checked by the caller. Therefore besides unsupported formats one can fail
729 * only in allocation.
732 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
736 image
->dma_buf_imported
= true;
737 image
->yuv_color_space
= yuv_color_space
;
738 image
->sample_range
= sample_range
;
739 image
->horizontal_siting
= horizontal_siting
;
740 image
->vertical_siting
= vertical_siting
;
742 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
747 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
749 int width
, height
, offset
, stride
, dri_format
, index
;
750 struct intel_image_format
*f
;
753 if (parent
== NULL
|| parent
->planar_format
== NULL
)
756 f
= parent
->planar_format
;
758 if (plane
>= f
->nplanes
)
761 width
= parent
->width
>> f
->planes
[plane
].width_shift
;
762 height
= parent
->height
>> f
->planes
[plane
].height_shift
;
763 dri_format
= f
->planes
[plane
].dri_format
;
764 index
= f
->planes
[plane
].buffer_index
;
765 offset
= parent
->offsets
[index
];
766 stride
= parent
->strides
[index
];
768 image
= intel_allocate_image(dri_format
, loaderPrivate
);
772 if (offset
+ height
* stride
> parent
->bo
->size
) {
773 _mesa_warning(NULL
, "intel_create_sub_image: subimage out of bounds");
778 image
->bo
= parent
->bo
;
779 drm_intel_bo_reference(parent
->bo
);
781 image
->width
= width
;
782 image
->height
= height
;
783 image
->pitch
= stride
;
784 image
->offset
= offset
;
786 intel_image_warn_if_unaligned(image
, __FUNCTION__
);
791 static const __DRIimageExtension intelImageExtension
= {
792 .base
= { __DRI_IMAGE
, 8 },
794 .createImageFromName
= intel_create_image_from_name
,
795 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
796 .destroyImage
= intel_destroy_image
,
797 .createImage
= intel_create_image
,
798 .queryImage
= intel_query_image
,
799 .dupImage
= intel_dup_image
,
800 .validateUsage
= intel_validate_usage
,
801 .createImageFromNames
= intel_create_image_from_names
,
802 .fromPlanar
= intel_from_planar
,
803 .createImageFromTexture
= intel_create_image_from_texture
,
804 .createImageFromFds
= intel_create_image_from_fds
,
805 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
809 brw_query_renderer_integer(__DRIscreen
*psp
, int param
, unsigned int *value
)
811 const struct intel_screen
*const intelScreen
=
812 (struct intel_screen
*) psp
->driverPrivate
;
815 case __DRI2_RENDERER_VENDOR_ID
:
818 case __DRI2_RENDERER_DEVICE_ID
:
819 value
[0] = intelScreen
->deviceID
;
821 case __DRI2_RENDERER_ACCELERATED
:
824 case __DRI2_RENDERER_VIDEO_MEMORY
: {
825 /* Once a batch uses more than 75% of the maximum mappable size, we
826 * assume that there's some fragmentation, and we start doing extra
827 * flushing, etc. That's the big cliff apps will care about.
830 size_t mappable_size
;
832 drm_intel_get_aperture_sizes(psp
->fd
, &mappable_size
, &aper_size
);
834 const unsigned gpu_mappable_megabytes
=
835 (aper_size
/ (1024 * 1024)) * 3 / 4;
837 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
838 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
840 if (system_memory_pages
<= 0 || system_page_size
<= 0)
843 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
844 * (uint64_t) system_page_size
;
846 const unsigned system_memory_megabytes
=
847 (unsigned) (system_memory_bytes
/ (1024 * 1024));
849 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
852 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
856 return driQueryRendererIntegerCommon(psp
, param
, value
);
863 brw_query_renderer_string(__DRIscreen
*psp
, int param
, const char **value
)
865 const struct intel_screen
*intelScreen
=
866 (struct intel_screen
*) psp
->driverPrivate
;
869 case __DRI2_RENDERER_VENDOR_ID
:
870 value
[0] = brw_vendor_string
;
872 case __DRI2_RENDERER_DEVICE_ID
:
873 value
[0] = brw_get_renderer_string(intelScreen
->deviceID
);
882 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
883 .base
= { __DRI2_RENDERER_QUERY
, 1 },
885 .queryInteger
= brw_query_renderer_integer
,
886 .queryString
= brw_query_renderer_string
889 static const __DRIrobustnessExtension dri2Robustness
= {
890 .base
= { __DRI2_ROBUSTNESS
, 1 }
893 static const __DRIextension
*intelScreenExtensions
[] = {
894 &intelTexBufferExtension
.base
,
895 &intelFlushExtension
.base
,
896 &intelImageExtension
.base
,
897 &intelRendererQueryExtension
.base
,
898 &dri2ConfigQueryExtension
.base
,
902 static const __DRIextension
*intelRobustScreenExtensions
[] = {
903 &intelTexBufferExtension
.base
,
904 &intelFlushExtension
.base
,
905 &intelImageExtension
.base
,
906 &intelRendererQueryExtension
.base
,
907 &dri2ConfigQueryExtension
.base
,
908 &dri2Robustness
.base
,
913 intel_get_param(__DRIscreen
*psp
, int param
, int *value
)
916 struct drm_i915_getparam gp
;
918 memset(&gp
, 0, sizeof(gp
));
922 ret
= drmCommandWriteRead(psp
->fd
, DRM_I915_GETPARAM
, &gp
, sizeof(gp
));
925 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
933 intel_get_boolean(__DRIscreen
*psp
, int param
)
936 return intel_get_param(psp
, param
, &value
) && value
;
940 intelDestroyScreen(__DRIscreen
* sPriv
)
942 struct intel_screen
*intelScreen
= sPriv
->driverPrivate
;
944 dri_bufmgr_destroy(intelScreen
->bufmgr
);
945 driDestroyOptionInfo(&intelScreen
->optionCache
);
947 ralloc_free(intelScreen
);
948 sPriv
->driverPrivate
= NULL
;
953 * This is called when we need to set up GL rendering to a new X window.
956 intelCreateBuffer(__DRIscreen
* driScrnPriv
,
957 __DRIdrawable
* driDrawPriv
,
958 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
960 struct intel_renderbuffer
*rb
;
961 struct intel_screen
*screen
= (struct intel_screen
*) driScrnPriv
->driverPrivate
;
962 mesa_format rgbFormat
;
963 unsigned num_samples
= intel_quantize_num_samples(screen
, mesaVis
->samples
);
964 struct gl_framebuffer
*fb
;
969 fb
= CALLOC_STRUCT(gl_framebuffer
);
973 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
975 if (screen
->winsys_msaa_samples_override
!= -1) {
976 num_samples
= screen
->winsys_msaa_samples_override
;
977 fb
->Visual
.samples
= num_samples
;
980 if (mesaVis
->redBits
== 5)
981 rgbFormat
= MESA_FORMAT_B5G6R5_UNORM
;
982 else if (mesaVis
->sRGBCapable
)
983 rgbFormat
= MESA_FORMAT_B8G8R8A8_SRGB
;
984 else if (mesaVis
->alphaBits
== 0)
985 rgbFormat
= MESA_FORMAT_B8G8R8X8_UNORM
;
987 rgbFormat
= MESA_FORMAT_B8G8R8A8_SRGB
;
988 fb
->Visual
.sRGBCapable
= true;
991 /* setup the hardware-based renderbuffers */
992 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
993 _mesa_add_renderbuffer(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
995 if (mesaVis
->doubleBufferMode
) {
996 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
997 _mesa_add_renderbuffer(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
1001 * Assert here that the gl_config has an expected depth/stencil bit
1002 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1003 * which constructs the advertised configs.)
1005 if (mesaVis
->depthBits
== 24) {
1006 assert(mesaVis
->stencilBits
== 8);
1008 if (screen
->devinfo
->has_hiz_and_separate_stencil
) {
1009 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_X8_UINT
,
1011 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1012 rb
= intel_create_private_renderbuffer(MESA_FORMAT_S_UINT8
,
1014 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1017 * Use combined depth/stencil. Note that the renderbuffer is
1018 * attached to two attachment points.
1020 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_S8_UINT
,
1022 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1023 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1026 else if (mesaVis
->depthBits
== 16) {
1027 assert(mesaVis
->stencilBits
== 0);
1028 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z_UNORM16
,
1030 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1033 assert(mesaVis
->depthBits
== 0);
1034 assert(mesaVis
->stencilBits
== 0);
1037 /* now add any/all software-based renderbuffers we may need */
1038 _swrast_add_soft_renderbuffers(fb
,
1039 false, /* never sw color */
1040 false, /* never sw depth */
1041 false, /* never sw stencil */
1042 mesaVis
->accumRedBits
> 0,
1043 false, /* never sw alpha */
1044 false /* never sw aux */ );
1045 driDrawPriv
->driverPrivate
= fb
;
1051 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1053 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1055 _mesa_reference_framebuffer(&fb
, NULL
);
1059 intel_init_bufmgr(struct intel_screen
*intelScreen
)
1061 __DRIscreen
*spriv
= intelScreen
->driScrnPriv
;
1063 intelScreen
->no_hw
= getenv("INTEL_NO_HW") != NULL
;
1065 intelScreen
->bufmgr
= intel_bufmgr_gem_init(spriv
->fd
, BATCH_SZ
);
1066 if (intelScreen
->bufmgr
== NULL
) {
1067 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1068 __func__
, __LINE__
);
1072 drm_intel_bufmgr_gem_enable_fenced_relocs(intelScreen
->bufmgr
);
1074 if (!intel_get_boolean(spriv
, I915_PARAM_HAS_RELAXED_DELTA
)) {
1075 fprintf(stderr
, "[%s: %u] Kernel 2.6.39 required.\n", __func__
, __LINE__
);
1083 intel_detect_swizzling(struct intel_screen
*screen
)
1085 drm_intel_bo
*buffer
;
1086 unsigned long flags
= 0;
1087 unsigned long aligned_pitch
;
1088 uint32_t tiling
= I915_TILING_X
;
1089 uint32_t swizzle_mode
= 0;
1091 buffer
= drm_intel_bo_alloc_tiled(screen
->bufmgr
, "swizzle test",
1093 &tiling
, &aligned_pitch
, flags
);
1097 drm_intel_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1098 drm_intel_bo_unreference(buffer
);
1100 if (swizzle_mode
== I915_BIT_6_SWIZZLE_NONE
)
1107 * Return array of MSAA modes supported by the hardware. The array is
1108 * zero-terminated and sorted in decreasing order.
1111 intel_supported_msaa_modes(const struct intel_screen
*screen
)
1113 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
1114 static const int gen7_modes
[] = {8, 4, 0, -1};
1115 static const int gen6_modes
[] = {4, 0, -1};
1116 static const int gen4_modes
[] = {0, -1};
1118 if (screen
->devinfo
->gen
>= 8) {
1120 } else if (screen
->devinfo
->gen
>= 7) {
1122 } else if (screen
->devinfo
->gen
== 6) {
1129 static __DRIconfig
**
1130 intel_screen_make_configs(__DRIscreen
*dri_screen
)
1132 static const mesa_format formats
[] = {
1133 MESA_FORMAT_B5G6R5_UNORM
,
1134 MESA_FORMAT_B8G8R8A8_UNORM
1137 /* GLX_SWAP_COPY_OML is not supported due to page flipping. */
1138 static const GLenum back_buffer_modes
[] = {
1139 GLX_SWAP_UNDEFINED_OML
, GLX_NONE
,
1142 static const uint8_t singlesample_samples
[1] = {0};
1143 static const uint8_t multisample_samples
[2] = {4, 8};
1145 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1146 const struct brw_device_info
*devinfo
= screen
->devinfo
;
1147 uint8_t depth_bits
[4], stencil_bits
[4];
1148 __DRIconfig
**configs
= NULL
;
1150 /* Generate singlesample configs without accumulation buffer. */
1151 for (int i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1152 __DRIconfig
**new_configs
;
1153 int num_depth_stencil_bits
= 2;
1155 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
1156 * buffer that has a different number of bits per pixel than the color
1157 * buffer, gen >= 6 supports this.
1160 stencil_bits
[0] = 0;
1162 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1164 stencil_bits
[1] = 0;
1165 if (devinfo
->gen
>= 6) {
1167 stencil_bits
[2] = 8;
1168 num_depth_stencil_bits
= 3;
1172 stencil_bits
[1] = 8;
1175 new_configs
= driCreateConfigs(formats
[i
],
1178 num_depth_stencil_bits
,
1179 back_buffer_modes
, 2,
1180 singlesample_samples
, 1,
1182 configs
= driConcatConfigs(configs
, new_configs
);
1185 /* Generate the minimum possible set of configs that include an
1186 * accumulation buffer.
1188 for (int i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1189 __DRIconfig
**new_configs
;
1191 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1193 stencil_bits
[0] = 0;
1196 stencil_bits
[0] = 8;
1199 new_configs
= driCreateConfigs(formats
[i
],
1200 depth_bits
, stencil_bits
, 1,
1201 back_buffer_modes
, 1,
1202 singlesample_samples
, 1,
1204 configs
= driConcatConfigs(configs
, new_configs
);
1207 /* Generate multisample configs.
1209 * This loop breaks early, and hence is a no-op, on gen < 6.
1211 * Multisample configs must follow the singlesample configs in order to
1212 * work around an X server bug present in 1.12. The X server chooses to
1213 * associate the first listed RGBA888-Z24S8 config, regardless of its
1214 * sample count, with the 32-bit depth visual used for compositing.
1216 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
1217 * supported. Singlebuffer configs are not supported because no one wants
1220 for (int i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1221 if (devinfo
->gen
< 6)
1224 __DRIconfig
**new_configs
;
1225 const int num_depth_stencil_bits
= 2;
1226 int num_msaa_modes
= 0;
1229 stencil_bits
[0] = 0;
1231 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1233 stencil_bits
[1] = 0;
1236 stencil_bits
[1] = 8;
1239 if (devinfo
->gen
>= 7)
1241 else if (devinfo
->gen
== 6)
1244 new_configs
= driCreateConfigs(formats
[i
],
1247 num_depth_stencil_bits
,
1248 back_buffer_modes
, 1,
1249 multisample_samples
,
1252 configs
= driConcatConfigs(configs
, new_configs
);
1255 if (configs
== NULL
) {
1256 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
1265 set_max_gl_versions(struct intel_screen
*screen
)
1267 __DRIscreen
*psp
= screen
->driScrnPriv
;
1269 switch (screen
->devinfo
->gen
) {
1272 psp
->max_gl_core_version
= 33;
1273 psp
->max_gl_compat_version
= 30;
1274 psp
->max_gl_es1_version
= 11;
1275 psp
->max_gl_es2_version
= 30;
1278 psp
->max_gl_core_version
= 32;
1279 psp
->max_gl_compat_version
= 30;
1280 psp
->max_gl_es1_version
= 11;
1281 psp
->max_gl_es2_version
= 30;
1285 psp
->max_gl_core_version
= 0;
1286 psp
->max_gl_compat_version
= 21;
1287 psp
->max_gl_es1_version
= 11;
1288 psp
->max_gl_es2_version
= 20;
1291 unreachable("unrecognized intel_screen::gen");
1296 * This is the driver specific part of the createNewScreen entry point.
1297 * Called when using DRI2.
1299 * \return the struct gl_config supported by this driver
1302 __DRIconfig
**intelInitScreen2(__DRIscreen
*psp
)
1304 struct intel_screen
*intelScreen
;
1306 if (psp
->image
.loader
) {
1307 } else if (psp
->dri2
.loader
->base
.version
<= 2 ||
1308 psp
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
1310 "\nERROR! DRI2 loader with getBuffersWithFormat() "
1311 "support required\n");
1315 /* Allocate the private area */
1316 intelScreen
= rzalloc(NULL
, struct intel_screen
);
1318 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
1321 /* parse information in __driConfigOptions */
1322 driParseOptionInfo(&intelScreen
->optionCache
, brw_config_options
.xml
);
1324 intelScreen
->driScrnPriv
= psp
;
1325 psp
->driverPrivate
= (void *) intelScreen
;
1327 if (!intel_init_bufmgr(intelScreen
))
1330 intelScreen
->deviceID
= drm_intel_bufmgr_gem_get_devid(intelScreen
->bufmgr
);
1331 intelScreen
->devinfo
= brw_get_device_info(intelScreen
->deviceID
);
1332 if (!intelScreen
->devinfo
)
1335 intelScreen
->hw_must_use_separate_stencil
= intelScreen
->devinfo
->gen
>= 7;
1337 intelScreen
->hw_has_swizzling
= intel_detect_swizzling(intelScreen
);
1339 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
1341 intelScreen
->winsys_msaa_samples_override
=
1342 intel_quantize_num_samples(intelScreen
, atoi(force_msaa
));
1343 printf("Forcing winsys sample count to %d\n",
1344 intelScreen
->winsys_msaa_samples_override
);
1346 intelScreen
->winsys_msaa_samples_override
= -1;
1349 set_max_gl_versions(intelScreen
);
1351 /* Notification of GPU resets requires hardware contexts and a kernel new
1352 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
1353 * supported, calling it with a context of 0 will either generate EPERM or
1354 * no error. If the ioctl is not supported, it always generate EINVAL.
1355 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
1356 * extension to the loader.
1358 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
1360 if (intelScreen
->devinfo
->gen
>= 6) {
1361 struct drm_i915_reset_stats stats
;
1362 memset(&stats
, 0, sizeof(stats
));
1364 const int ret
= drmIoctl(psp
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
1366 intelScreen
->has_context_reset_notification
=
1367 (ret
!= -1 || errno
!= EINVAL
);
1370 psp
->extensions
= !intelScreen
->has_context_reset_notification
1371 ? intelScreenExtensions
: intelRobustScreenExtensions
;
1373 brw_fs_alloc_reg_sets(intelScreen
);
1374 brw_vec4_alloc_reg_set(intelScreen
);
1376 return (const __DRIconfig
**) intel_screen_make_configs(psp
);
1379 struct intel_buffer
{
1384 static __DRIbuffer
*
1385 intelAllocateBuffer(__DRIscreen
*screen
,
1386 unsigned attachment
, unsigned format
,
1387 int width
, int height
)
1389 struct intel_buffer
*intelBuffer
;
1390 struct intel_screen
*intelScreen
= screen
->driverPrivate
;
1392 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
1393 attachment
== __DRI_BUFFER_BACK_LEFT
);
1395 intelBuffer
= calloc(1, sizeof *intelBuffer
);
1396 if (intelBuffer
== NULL
)
1399 /* The front and back buffers are color buffers, which are X tiled. */
1400 uint32_t tiling
= I915_TILING_X
;
1401 unsigned long pitch
;
1402 int cpp
= format
/ 8;
1403 intelBuffer
->bo
= drm_intel_bo_alloc_tiled(intelScreen
->bufmgr
,
1404 "intelAllocateBuffer",
1409 BO_ALLOC_FOR_RENDER
);
1411 if (intelBuffer
->bo
== NULL
) {
1416 drm_intel_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
1418 intelBuffer
->base
.attachment
= attachment
;
1419 intelBuffer
->base
.cpp
= cpp
;
1420 intelBuffer
->base
.pitch
= pitch
;
1422 return &intelBuffer
->base
;
1426 intelReleaseBuffer(__DRIscreen
*screen
, __DRIbuffer
*buffer
)
1428 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
1430 drm_intel_bo_unreference(intelBuffer
->bo
);
1434 static const struct __DriverAPIRec brw_driver_api
= {
1435 .InitScreen
= intelInitScreen2
,
1436 .DestroyScreen
= intelDestroyScreen
,
1437 .CreateContext
= brwCreateContext
,
1438 .DestroyContext
= intelDestroyContext
,
1439 .CreateBuffer
= intelCreateBuffer
,
1440 .DestroyBuffer
= intelDestroyBuffer
,
1441 .MakeCurrent
= intelMakeCurrent
,
1442 .UnbindContext
= intelUnbindContext
,
1443 .AllocateBuffer
= intelAllocateBuffer
,
1444 .ReleaseBuffer
= intelReleaseBuffer
1447 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
1448 .base
= { __DRI_DRIVER_VTABLE
, 1 },
1449 .vtable
= &brw_driver_api
,
1452 static const __DRIextension
*brw_driver_extensions
[] = {
1453 &driCoreExtension
.base
,
1454 &driImageDriverExtension
.base
,
1455 &driDRI2Extension
.base
,
1457 &brw_config_options
.base
,
1461 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
1463 globalDriverAPI
= &brw_driver_api
;
1465 return brw_driver_extensions
;