gallium/radeon: add micro_tile_mode to radeon_surf

for easier access

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index c2d1f9ef3ea4718e8dd6b97bcb846717b1d751ab..bbf91a841c2f30d5db3768f446c800efbd3a6e10 100644 (file)
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -398,6 +398,7 @@ struct radeon_surf {
     uint32_t                    pipe_config;
     uint32_t                    num_banks;
     uint32_t                    macro_tile_index;
     uint32_t                    pipe_config;
     uint32_t                    num_banks;
     uint32_t                    macro_tile_index;

+    uint32_t                    micro_tile_mode; /* displayable, thin, depth, rotated */

 
     uint64_t                    dcc_size;
     uint64_t                    dcc_alignment;
 
     uint64_t                    dcc_size;
     uint64_t                    dcc_alignment;

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index 9f52588c1470a87fadd67d6018eea0739b15a399..a45bcb0f7767cb5daeab566580e7407314d973a2 100644 (file)
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -255,6 +255,20 @@ static int compute_level(struct amdgpu_winsys *ws,
    return 0;
 }
 
    return 0;
 }
 

+#define   G_009910_MICRO_TILE_MODE(x)          (((x) >> 0) & 0x03)
+#define   G_009910_MICRO_TILE_MODE_NEW(x)      (((x) >> 22) & 0x07)
+
+static void set_micro_tile_mode(struct radeon_surf *surf,
+                                struct radeon_info *info)
+{
+   uint32_t tile_mode = info->si_tile_mode_array[surf->tiling_index[0]];
+
+   if (info->chip_class >= CIK)
+      surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
+   else
+      surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
+}
+

 static int amdgpu_surface_init(struct radeon_winsys *rws,
                                struct radeon_surf *surf)
 {
 static int amdgpu_surface_init(struct radeon_winsys *rws,
                                struct radeon_surf *surf)
 {


@@ -411,6 +425,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
       if (level == 0) {
          surf->bo_alignment = AddrSurfInfoOut.baseAlign;
          surf->pipe_config = AddrSurfInfoOut.pTileInfo->pipeConfig - 1;
       if (level == 0) {
          surf->bo_alignment = AddrSurfInfoOut.baseAlign;
          surf->pipe_config = AddrSurfInfoOut.pTileInfo->pipeConfig - 1;

+         set_micro_tile_mode(surf, &ws->info);

 
          /* For 2D modes only. */
          if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
 
          /* For 2D modes only. */
          if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
index 6fb877490ea4a62138e2eaafdda744ed05968b23..c6025ff03d8e4f65a8773da708c1b7ca3cf3503c 100644 (file)
--- a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
@@ -45,6 +45,27 @@ static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
        return index;
 }
 
        return index;
 }
 

+#define   G_009910_MICRO_TILE_MODE(x)          (((x) >> 0) & 0x03)
+#define   G_009910_MICRO_TILE_MODE_NEW(x)      (((x) >> 22) & 0x07)
+
+static void set_micro_tile_mode(struct radeon_surf *surf,
+                                struct radeon_info *info)
+{
+    uint32_t tile_mode;
+
+    if (info->chip_class < SI) {
+        surf->micro_tile_mode = 0;
+        return;
+    }
+
+    tile_mode = info->si_tile_mode_array[surf->tiling_index[0]];
+
+    if (info->chip_class >= CIK)
+        surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
+    else
+        surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
+}
+

 static void surf_level_winsys_to_drm(struct radeon_surface_level *level_drm,
                                      const struct radeon_surf_level *level_ws)
 {
 static void surf_level_winsys_to_drm(struct radeon_surface_level *level_drm,
                                      const struct radeon_surf_level *level_ws)
 {


@@ -114,7 +135,8 @@ static void surf_winsys_to_drm(struct radeon_surface *surf_drm,
     }
 }
 
     }
 }
 

-static void surf_drm_to_winsys(struct radeon_surf *surf_ws,
+static void surf_drm_to_winsys(struct radeon_drm_winsys *ws,
+                               struct radeon_surf *surf_ws,

                                const struct radeon_surface *surf_drm)
 {
     int i;
                                const struct radeon_surface *surf_drm)
 {
     int i;


@@ -153,6 +175,8 @@ static void surf_drm_to_winsys(struct radeon_surf *surf_ws,
         surf_ws->tiling_index[i] = surf_drm->tiling_index[i];
         surf_ws->stencil_tiling_index[i] = surf_drm->stencil_tiling_index[i];
     }
         surf_ws->tiling_index[i] = surf_drm->tiling_index[i];
         surf_ws->stencil_tiling_index[i] = surf_drm->stencil_tiling_index[i];
     }

+
+    set_micro_tile_mode(surf_ws, &ws->info);

 }
 
 static int radeon_winsys_surface_init(struct radeon_winsys *rws,
 }
 
 static int radeon_winsys_surface_init(struct radeon_winsys *rws,


@@ -168,7 +192,7 @@ static int radeon_winsys_surface_init(struct radeon_winsys *rws,
     if (r)
         return r;
 
     if (r)
         return r;
 

-    surf_drm_to_winsys(surf_ws, &surf_drm);
+    surf_drm_to_winsys(ws, surf_ws, &surf_drm);

     return 0;
 }
 
     return 0;
 }
 


@@ -185,7 +209,7 @@ static int radeon_winsys_surface_best(struct radeon_winsys *rws,
     if (r)
         return r;
 
     if (r)
         return r;
 

-    surf_drm_to_winsys(surf_ws, &surf_drm);
+    surf_drm_to_winsys(ws, surf_ws, &surf_drm);

     return 0;
 }
 
     return 0;
 }