resolve internal (nmigen_soc) imports

[nmigen-soc.git] / nmigen_soc / wishbone / __init__.py

diff --git a/nmigen_soc/wishbone/__init__.py b/nmigen_soc/wishbone/__init__.py
index 4a197f74c7d54d60b4ff79795a978c7a1cd2f07e..9e567ac97125c5c3b4b003f2a8251ade86e3df17 100644 (file)
--- a/nmigen_soc/wishbone/__init__.py
+++ b/nmigen_soc/wishbone/__init__.py
@@ -1,2 +1,3 @@
-from .bus import *
-from .sram import *
+from nmigen_soc.wishbone.bus import (Interface, CycleType, Decoder,
+                                     InterconnectShared, Arbiter,
+                                     BurstTypeExt)