test in sram for deliberately delaying response

[nmigen-soc.git] / nmigen_soc / wishbone / sram.py

diff --git a/nmigen_soc/wishbone/sram.py b/nmigen_soc/wishbone/sram.py
index c518ff9a718bea68f334b853783936b761d7b273..22b0efdd330f2af99dc25bcdc0133f95b0e59957 100644 (file)
--- a/nmigen_soc/wishbone/sram.py
+++ b/nmigen_soc/wishbone/sram.py
@@ -1,4 +1,4 @@
-from nmigen import Elaboratable, Memory, Module
+from nmigen import Elaboratable, Memory, Module, Signal
 from nmigen.utils import log2_int
 
 from nmigen_soc.wishbone.bus import Interface
@@ -86,17 +86,25 @@ class SRAM(Elaboratable):
                 wrport.addr.eq(self.bus.adr[:len(rdport.addr)]),
                 wrport.data.eq(self.bus.dat_w)
             ]
-            n_wrport = wrport.en.shape()[0]
-            n_bussel = self.bus.sel.shape()[0]
+            n_wrport = wrport.en.width
+            n_bussel = self.bus.sel.width
             assert n_wrport == n_bussel, "bus enable count %d " \
                     "must match memory wen count %d" % (n_wrport, n_bussel)
-            for i in range(n_wrport):
-                m.d.comb += wrport.en[i].eq(self.bus.cyc & self.bus.stb &
-                                            self.bus.we & self.bus.sel[i])
+            wen = Signal()
+            m.d.comb += wen.eq(self.bus.cyc & self.bus.stb & self.bus.we)
+            with m.If(wen):
+                m.d.comb += wrport.en.eq(self.bus.sel)
 
         # generate ack
         m.d.sync += self.bus.ack.eq(0)
         with m.If(self.bus.cyc & self.bus.stb & ~self.bus.ack):
-            m.d.sync += self.bus.ack.eq(1)
+            if False: # test which deliberately delays response
+                counter = Signal(3)
+                m.d.sync += counter.eq(counter + 1)
+                with m.If(counter == 7):
+                    m.d.sync += self.bus.ack.eq(1)
+                    m.d.sync += counter.eq(0)
+            else:
+                m.d.sync += self.bus.ack.eq(1)
 
         return m