dont have to but test latchregister incoming is a Record

[nmutil.git] / src / nmutil / latch.py

diff --git a/src/nmutil/latch.py b/src/nmutil/latch.py
index 5f3a0c01edc73fa0bc2559da4378e94df9a62885..7d6a1efe22c881585a626e397590337186f6ef1b 100644 (file)
--- a/src/nmutil/latch.py
+++ b/src/nmutil/latch.py
@@ -1,6 +1,6 @@
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
-from nmigen import Signal, Module, Const, Elaboratable
+from nmigen import Record, Signal, Module, Const, Elaboratable
 
 """ jk latch
 
@@ -22,7 +22,11 @@ endmodule
 """
 
 def latchregister(m, incoming, outgoing, settrue, name=None):
-    reg = Signal.like(incoming, name=name) # make reg same as input. reset OK.
+    # make reg same as input. reset OK.
+    if isinstance(incoming, Record):
+        reg = Record.like(incoming, name=name)
+    else:
+        reg = Signal.like(incoming, name=name)
     with m.If(settrue): # pass in some kind of expression/condition here
         m.d.sync += reg.eq(incoming)      # latch input into register
         m.d.comb += outgoing.eq(incoming) # return input (combinatorial)