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last changeThu, 9 Dec 2021 06:04:10 +0000 (22:04 -0800)
shortlog
46 min ago Jacob Lifshaymake ternlogi tests run master
118 min ago Jacob Lifshayrename ternaryi to ternlogi
119 min ago Jacob Lifshayadd initial ternlogi pseudo-code
11 hours ago Luke Kenneth... add instr_fault to PowerDecoder2
11 hours ago Luke Kenneth... whitespace
17 hours ago Luke Kenneth... code-comments for LDSTException.instr_fault
18 hours ago Luke Kenneth... add an on_Display function which is being used by some...
18 hours ago Luke Kenneth... found a way to print out the names of the signals
18 hours ago Luke Kenneth... absolute import again
18 hours ago Luke Kenneth... use full-path imports (so we know where they come from)
19 hours ago Mikolaj WielgusWIP: Output C instead of Python for Nmigen simulation
19 hours ago Mikolaj WielgusSource Nmigen simulator from this repository
39 hours ago Luke Kenneth... whoops wrong number
39 hours ago Luke Kenneth... add OP_FETCH_FAILED micro-op
2 days ago Jacob Lifshayfix broken url
3 days ago Tobias Platenfix microwatt_mmu and and wishbone_memory output in...
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tags
2 months ago DRAFT_SVP64_0_1
3 months ago xlen-bcd
6 months ago 0.0.3
7 months ago 0.0.1
heads
46 min ago master
8 weeks ago xlen
7 months ago libresoc-master