pysvp64db: fix traversal

[openpower-isa.git] / src / openpower / test / trap / trap_cases.py

diff --git a/src/openpower/test/trap/trap_cases.py b/src/openpower/test/trap/trap_cases.py
index dcab94f98725078781e923a3d2b8517d092fe68c..13d9b09437e2fbd6944831776e11c934c0266423 100644 (file)
--- a/src/openpower/test/trap/trap_cases.py
+++ b/src/openpower/test/trap/trap_cases.py
@@ -2,7 +2,7 @@ from openpower.simulator.program import Program
 from openpower.endian import bigendian
 from openpower.consts import MSR
 from openpower.test.state import ExpectedState
-
+from openpower.decoder.selectable_int import SelectableInt
 from openpower.test.common import TestAccumulatorBase
 import random
 
@@ -36,7 +36,10 @@ class TrapTestCase(TestAccumulatorBase):
         msr = 0xa000000000000003
         e = ExpectedState(pc=0x2700)
         e.intregs[1] = 1 << 13
-        e.msr = 0xa000000000000003  # TODO, not actually checked
+        e.sprs['SRR0'] = 0x4
+        e.sprs['SRR1'] = 0xa000000000080003
+        e.sprs['KAIVB'] = 0x2000
+        e.msr = 0xa000000000000001
         self.add_case(Program(lst, bigendian),
                       initial_regs, initial_sprs,
                       initial_msr=msr,
@@ -59,7 +62,7 @@ class TrapTestCase(TestAccumulatorBase):
         e = ExpectedState(pc=0xc00)
         e.intregs[1] = 1
         e.sprs['SRR0'] = 4                  # PC to return to: CIA+4
-        e.sprs['SRR1'] = 0x9000000000022903  # MSR to restore after sc return
+        e.sprs['SRR1'] = 0x9000000000002903  # MSR to restore after sc return
         e.msr = 0x9000000000000001          # MSR changed to this by sc/trap
         self.add_case(Program(lst, bigendian),
                       initial_regs, initial_sprs,
@@ -83,9 +86,12 @@ class TrapTestCase(TestAccumulatorBase):
         e.intregs[1] = 1 # should be unaltered
         e.intregs[0] = 2 # due to instruction at 0xc0c
         e.sprs['SRR0'] = 0xc0c              # PC to return to: CIA+4 (0xc0c)
-        e.sprs['SRR1'] = 0xffff_ffff_ffff_ffff # MSR after rfid return
-        e.msr = 0xffffffffffffffff          # MSR is restored (by rfid)
-        e.pc = 0xc10                        # should stop after addi 0,0,2
+        SRR1 = SelectableInt(-1, 64)
+        SRR1[33:37] = 0 # sc clears bits 33:36
+        SRR1[42:48] = 0 # sc clears bits 42:47
+        e.sprs['SRR1'] = int(SRR1)         # MSR after rfid return
+        e.msr = 0xffff_ffff_ffff_ffff      # MSR is restored (by rfid)
+        e.pc = 0xc10                       # should stop after addi 0,0,2
         self.add_case(Program(lst, bigendian),
                       initial_regs, initial_sprs,
                       initial_msr=0xffff_ffff_ffff_ffff,